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D915GAV
Product Manual
110 pgs2.4 Mb0
Quick Reference
32 pgs2.27 Mb0
Schematics REV 4.0
106 pgs8.3 Mb0
Technical Product Specification
106 pgs1.03 Mb0
User Manual
80 pgs1.72 Mb0
User Manual
110 pgs2.12 Mb0

Intel D915GAV Schematics REV 4.0

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<XR_PAGE_TITLE>
28 7 6 5 4 3 1
PAGE #
COMPONENT/FUNCTION
[1. INDEX] [2. BLOCK DIAGRAM]
[3. RESET MAP]
D
[4. CLOCK DISTRIBUTION] [5. GPIO, IRQ, IDSEL MAP] [6. CPU-SOCKET] [7. CPU-SOCKET]
[8. CPU TERMINATION & MISC P/U P/D] [9. CPU-VCCP FILTERED ANALOG SUPPLY]
[10. MCH SECTIONS PAGE 1 OF 6] [11. MCH SECTIONS PAGE 2 OF 6] [12. MCH SECTIONS PAGE 3 OF 6] [13. MCH SECTIONS PAGE 4 OF 6] [14. MCH SECTIONS PAGE 5 OF 6] [15. MCH SECTIONS PAGE 6 OF 6]
C
[16. MCH 2P5_DAC & 1P5 FILTER] [17. MCH DECOUPLING AND COMP] [18. MCH DCPL & VGA TERMINATION] [19. MCH CHIPSET TERMINATION] [20. VGA CONNECTOR] [21. DDR1 DIMM-A 0/1] [22. DDR1 DIMM-A TERM] [23. DDR1 DIMM-A TERM] [24. DDR1 DIMM-A DCPL] [25. DDR1 DIMM-B 0/1] [26. DDR1 DIMM-B TERM]
B
[27. DDR1 DIMM-B TERM] [28. DDR1 DIMM-B DCPL] [29. CK410E PAGE 1 OF 2] [30. CK410E PAGE 2 OF 2] [31. BLANK PAGE] [32. PCIE 16-PORT] [33. PCIE COUPLING] [34. BLANK PAGE] [35. BLANK PAGE] [36. BLANK PAGE] [37. ICH 1 OF 6 - CONTROL] [38. ICH 2 OF 6 - CONTROL]
A
[39. ICH 3 OF 6 - CONTROL] [40. ICH 4 OF 6 - CONTROL] [41. ICH 5 OF 6 - POWER] [42. ICH 6 OF 6 - GROUND] [43. ICH TERMINATION]
PAGE #
COMPONENT/FUNCTION
[44. IDE_SOUTH_BRIDGE] [45. USB_BACKPANEL_CONN] [46. USB_FP #2 HEADER] [47. USB_FP_HEADER_POWER 1 & 2] [48. USB_FP #1 HEADER] [49. PCI_CONN_1] [50. PCI_CONN_2] [51. PCIE_X1_SLOT1] [52. PCIE_X1_SLOT2] [53. PCI_CONN_3] [54. ICH_PCI_TERMINATION] [55. BLANK] [56. LAN CONTROLLER, PART 1 OF 2] [57. LAN EEPROM, DECOUPLING] [58. BLANK] [59. LAN CONN] [60. AUDIO CODEC] [61. AUDIO BYPASS & DECOUPLING CAPS] [62. ATAPI CD HEADER & SPDIF HEADER] [63. AUDIO BACK PORT MIC-IN/LINE-IN/OUT] [64. AC HEADER FRONT PANEL PORT] [65. AUDIO TERMINATION P/U & VREF NETWORK] [66. AUDIO VREG] [67. BLANK] [68. BLANK] [69. BLANK] [70. TPM (TRUSTED PLATFORM MODULE)] [71. SATA CONNECTORS] [72. FIRMWARE HUB] [73. PORT ANGELES (1 OF 2)] [74. PORT ANGELES (2 OF 2)] [75. FDD CONN] [76. PS/2 MOUSE DOUBLE-STACKED] [77. LPT CONN] [78. SERIAL PORT A] [79. HARDWARE MANAGEMENT: HECETA] [80. SPEAKER & DIAGNOSTIC LED] [81. STD_FRONT_PANEL_HDR] [82. MTG_HOLES/LABELS] [83. FAN CONTROL] [84. VREG: VOLTAGE DISTRIBUTION] [85. V_SM SWITCHING VREG]
PAGE #
COMPONENT/FUNCTION
[86. STANDARD POWER CONNECTOR] [87. VREG_1P2_FSB_VTT] [88. VREG_2P5_MCH] [89. VREG_SM_VTT] [90. PCI VAUX/VREG_USB/V_BATTERY] [91. VREG_USB_BP_RIGHT/LEFT & PS2] [92. 3.3V STANDBY] [93. VREG_DCPL_BULK] [94. 5VDUAL VREG & USB_BP_MID] [95. VCCP VREG] [96. VCCP VREG] [97. VCCP VREG] [98. VCCP VREG DECOUPLING] [99. PCI_CONN_4] [100. DMI LAI PORT] [101. DEBUG_XDP] [102. VREG_1P5 CORE] [103. VR_THERMAL THROTTLE] [104. TEST SITE CAPS] [105. 1394A 1 OF 2] [106. 1394A 2 OF 2]
[107-116 REFERENCE PAGES]
NOTES:
POWER SYMBOLS USED: VCC3
VCC +12V
-12V
1. THIS SCHEMATIC DOCUMENTS THE GENERIC PRODUCT WITH ALL POSSIBLE CONFIGURATIONS. PLEASE REFER TO SPECIFIC PRODUCT PBA EPL FOR ITEMS SHOWN AS OPTIONAL IN THE SCHEMATIC.
2. RESISTORS ARE IN OHMS UNLESS OTHERWISE SPECIFIED.
3. VCC = +5V UNLESS OTHERWISE SPECIFIED.
4. * SUFFIX INDICATES ACTIVE LOW SIGNAL.
5. \I SUFFIX INDICATES SIGNAL EXITS HIERARCHICAL BLOCK.
6. THIS DOCUMENT ALSO EXISTS ON ELECTRONIC MEDIA.
AVALON
GRANTSDALE / DDR1 / ICH6 / UATX
FAB D
REV 4.0
TAPE-OUT:
D
C
B
A
8 7
[PAGE_TITLE=INDEX]
INTEL
45
36
CONFIDENTIAL
2 1
DOCUMENT NUMBER PAGE REV
C77862
1/106
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
POWER
D
C
SUPPLY CONN
PORT 1
PORT 2
BACK PANEL(R)
USB PORT 1
USB PORT 2
USB PORT 3
USB PORT 4
B
A
FRONT PANEL 1
USB PORT 5 (1)
USB PORT 6 (2)
FRONT PANEL 2
USB PORT 7 (3)
USB PORT 8 (4)
SENSOR S3
SM BUS S3
SM BUS S0
PS2 MOUSE & KEYBOARD
COPIED BLOCK DIAGRAM FROM TGRVP_A, 14/10/2003 BLOCK DIAGRAM UPDATED: 12/15/2003
8 7
XDP
(BACK SIDE)
SM BUS S3
VREG
PARALLEL (1)
SERIAL (1)
PORT ANGELES
SIO
PCIE X16
GRFX CONN
VGA CONN
1394A
SATA CONN
1 & 2
3 & 4
IDE CONN 1
LPC BUS
FLOPPY DISK DRIVE CONN
GRANTSDALE
SM BUS S3
FWH: FIRMWARE HUB
LAND GRID ARRAY (LGA) CONNECTOR
LGA775
PROCESSOR SOCKET
FSB
GMCH:
GRAPHIC MEMORY CONTROLLER HUB
DMI: DIRECT MEDIA INTERFACE
ICH6: I/O
CONTROLLER HUB
CHIPSET
TPM: SECURITY
CHANNEL A DDR 333/400
CHANNEL B DDR 333/400
PCIE
PCI (33MHZ)
PCIE
AUDIO LINK
MIC IN
LINE IN
CD IN
45
CORE
SM BUS S3
AZALIA
AUDIO CORE
DUAL DATA RATE SDRAM (2-DDR SDRAM DIMMS)
DUAL DATA RATE SDRAM (2-DDR SDRAM DIMMS)
LAN
MARVELL
10/100/1000
SM BUS S3
FRONT PANEL LINE OUT
36
SM BUS S0
CK_410 CLOCK
DIMM 0:1
DIMM 0:1
RJ45
UATX FORM FACTOR
PCI SLOTS 1
PCI SLOTS 2
PCIE X1 PORT1
SM BUS S3
ICH6
PORT_ANGELES
SM BUS S3
SENSOR S3
BLOCK DIAGRAM
[PAGE_TITLE=BLOCK DIAGRAM]
INTEL
CONFIDENTIAL
2 1
SM BUS S0
HECETA
HARDWARE
MONITOR
DMI LAI HDR
(2X12 BACKSIDE)
DOCUMENT NUMBER PAGE REV
C77862
2
D
C
B
A
4.0
<XR_PAGE_TITLE>
AFTER P_PCIRST*, HANDSHAKE (ON HL BUS) BETWEEN ICH/MCH MUST
CORE
D
HAPPEN BEFORE H_CPURST* WILL BE ASSERTED/DE-ASSERTED
MCH: MEMORY
P_PCIRST* PWRGD_3V
CONTROLLER HUB
H_CPURST*
H_CPURST*
H_PWRGD
PLTRST*
XDP
28 7 6 5 4 3 1
RSTN* H_CPURST*
H_PWRGD
PGA478 SOCKET
U
D
PORT ANGELES
PCIRST_OUT*
RES: PA_P_TRST*
C
POWER
SUPPLY CONN
P_PCIRST* SLP_S4/S5* SLP_S3*
FP_RST*
PWRGP_PSPS_ON* PWRGD_PS
CDC_DWN_RST*
PWRGD_3V
RSMRST*
IDE_RST*
LAN_DSABLE*
KBRST* PS_ON*
TESTPOINT
IDE_RST*
RES: P_TRST_SLOTS*
IDE CONN1
PCIe GRAPHICS
PWRGD 1X16 CONN
PCIE CONN
X1 PORT 1
PWRGD
RES:FWM_RST*
RST*
RESET
FWH: FIRMWARE HUB
C
TPM (SECURITY)
RES: PS_ON_HEADER*
RES:P_TRST_LAN*
RES:ICH_RSMRST_R*
PE_RST* LAN_PWRGD
LAN
B
A
COPIED RESET MAP FROM TGRVP_A, 14/10/2003 RESET MAP UPDATED: XX/XX/2003
8 7
FRONT PANEL CONN
PWR ON SWITCH
RESET SWITCH
EV_SW_ON*
XDP
HECETA
RES: SW_ON*
FP_RST*
FP_RST*
DBR*
SW_ON*
JUMPER-STRAP-GND
PULL-UP TERMINATION
PWRGD_3V RSMRST* LAN_DISABLE* RCIN*
SYS_RESET*
RTC_RST*
SW_ON*
FWH
ICH TESTIN
ICH6: I/O
CONTROLLER HUB
45
PLTRST*
P_PCIRST* H_PWRGD
ACZ_RST*
SLP_S4* SLP_S3*
VREG SEQUENCING CONTROL
SLP_S3*
PORT ANGELES
36
CDC_DWN_RST*
P_PCIRST*
PCI SLOT 1
PCI SLOT 2
CONTROL: CDC_DOWN_RST*
RES: AUD_LINK_RST_HDR*
RESET MAP
CONFIDENTIAL
AUDIO CODEC
RESET*
AUD_LINK_RST_HDR*
[PAGE_TITLE=RESET MAP]
INTEL
2 1
DOCUMENT NUMBER PAGE REV
C77862
2X8 Audio HDR
B
A
3
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
14.318MHZ
D
C
3.3 VOLT
3.3 VOLT
33MHZ 33MHZ
33MHZ 33MHZ 33MHZ
48MHZ
PCI SLOT 1 PCI SLOT 2
32.7KHZ
LANCLK CLK14
PCICLK RTCCLK USBCLK
DMICLK SATACLK AUD_BCLK
ICH 6
SMBUS CLK SCLK
ICH
SCLK
SUSCLK
SUSCLK
32.7KHZ
AUDIO
XTAL-IN
FWH TPM
HECETA
HARDWARE MANAGEMENT
CODEC
AUD_BCLK
32.7KHZ
12.288 MHZ
PORT
ANGELES
CLK14 33M
KBCLK
MCLK
D
MS/KB
C
1394
100MHZ 100MHZ
CK410E
B
14.318MHZ
100MHZ
100MHZ
100MHZ
100MHZ
X16 PCI-EXPRESS
SCLK
25MHZ
LAN
CRYSTAL PE_CLK
X1 PCI-EXPRESS #1
EEPROM CLK
PROM
B
A
HOST CLOCK PAIRS
CORE
COPIED CLOCK DISTRIBUTION FROM TGRVP_A, 14/10/2003 CLOCK DISTRIBUTION UPDATED: 12/15/2003
8 7
100MHZ
96MHZ
100/133/167/200 MHZ CPU_CK
100/133/167/200 MHZ CPU_CK
MCH GFX
XDP CLK-OUT OPTION FROM CPU
CPU
CORE
XDP CLK-OUT
XDP CLK-OUT OPTION
CLOCK DISTRIBUTION
XDP PORT
XDP PORT
MCH
VIDEO TEST GCLKIN
HOST
DUAL CHANNEL DDR
CHAN A
DIMM 0
DIMM 1
CHAN B
A
DIMM 0
DIMM 1
[PAGE_TITLE=CLOCK DISTRIBUTION]
INTEL
45
36
CONFIDENTIAL
2 1
DOCUMENT NUMBER PAGE REV
C77862
4
4.0
<XR_PAGE_TITLE>
SLOT6 1394
IRQA
DURING
RESET
---
---
---
---
---
---
---
---
HIGH HIGH
---
---
---
HIGH
HIGH HI-Z HI-Z
---
---
---
---
---
---
HIGH HIGH
--­HIGH HIGH
---
---
---
HIGH HIGH
HIGH
---
--­HIGH HI-Z
INPUT INPUT INPUT INPUT INPUT
OUTPUT INPUT
INPUT
OUTPUT OUTPUT
OUTPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT
5
21
PCIE X16 X1_1 IRQA
IRQA
S3/S5
DRIVEN DRIVEN
DEFINED
DEFINED DEFINED
DEFINED DEFINED DEFINED DEFINED DEFINED
DEFINED DEFINED
DEFINED DEFINED DEFINED
IRQA
---
---
---
---
---
--­OFF
---
---
---
---
--­DRIVEN DRIVEN DRIVEN
LAN
NOTES
P/U ON PAGE 54, 2.7K TO VCC P/U ON PAGE 54, 2.7K TO VCC P/U ON PAGE 54, 8.2K TO VCC3 P/U ON PAGE 54, 8.2K TO VCC3 P/U ON PAGE 54, 8.2K TO VCC3
P/U ON PAGE 54, 8.2K TO VCC3
10K P/D TO 3.3V PG 43 10K P/D TO 3.3V STBY PG 43
10K P/U TO 3.3V STBY PG 43 10K P/D TO GND PG 43
OFF OFF
---
---
---
---
---
--­OFF
---
---
---
--­OFF OFF
OFF LOW
LOW OFF OFF
4.7K P/U TO 3.3V PG 39
10K P/D TO GND PG 43
4.7K P/U TO 3.3V PG 39
4.7K P/U TO 3.3V PG 39
4.7K P/U TO 3.3V PG 39
CONFIG JUMPER MANUF MODE
HI/LOW BIOS CONFIG FOR IDE PRI (FEATURE IS DEFAULT LOW)
DESIGN FEATURE WITH RESISTOR STRAPPING DESIGN FEATURE WITH RESISTOR STRAPPING
2X12_DETECT
USB1-F1
USB1-F0
IRQB
USB1-F2
IRQC
USB1-F3
IRQD
USB #2
SMBUS AZALIA
IRQA
IRQB
COPIED INFO FROM TGRVP_A, 10/14/2003
INFORMATION UPDATED: 12/12/2003
GPIO, IRQ, IDSEL MAPS
IRQA
24
IRQA
45
36
PIN NAME
GPI[0] GPI[2] GPI[2] GPI[3] GPI[4] GPI[5]
ICH
FWH
GPI[6] GPI[7] GPI[8]
GPI[9] GPI[10] GPI[11] GPI[12] GPI[13] GPI[14] GPI[15] GPO[16] GPO[17]
GPO[19] GPO[20]
6
GPO[21] GPO[22] GPO[23] GPIO[24] GPIO[25] GPIO[26]
GPIO[27] GPIO[28] GPIO[29] GPIO[30] GPIO[31] GPIO[32] GPIO[33] GPIO[34] GPI[40] GPI[41] GPO[48]
GPI4
GPI3
GPI2
GPI1
GPI0
GPO0 GPO1 GPO2
D
C
B
WELL
RESUME RESUME RESUME RESUME
RESUME RESUME RESUME
RESUME RESUME MAIN RESUME RESUME
CORE CORE CORE CORE
CORE
GPO3
GPO4
GPO5
GPI6
GPI7
PORT
A
GPI010
GPIO11
ANGELES
GPIO12
GPI013
GPI14
IO_PME*
GRN_LED
YLW_LED
IRQ ROUTING TABLE
P_INTA* P_INTB* P_INTC* P_INTD* P_INTE* P_INTF* P_INTG* P_INTH* REQ/GNT IDSEL
USAGE
MAIN
P_REQ6* ---
MAIN
P_REQ5*
MAIN
P_INTE*
MAIN
P_INTF*
MAIN
P_INTG*
MAIN
P_INTH*
MAIN
1X4_DETECT
MAIN
MAIN
MAIN MAIN
MAIN MAIN
MAIN
---­MAIN
FP_AUD_DETECT AC_OK (FOR DEBUG HDR) - NOT USED OC[4]* OC[5]* SMBALERT* SATA HOT SWAP NOT USED IO_PME* OC[6]* OC[7]* GNT[6]* GNT[5]* STP_PCI# NOT USEMAINGPO[18] OEM_LED0 STP_PCI# NOT ASSIGN
---­1394 ENABLE CTRL BOARD ID 0 INTERNAL VRM STRAP SATAGP0
BOARD ID 1
RPS_OFF* (FOR DEBUG HDR) - NOT USED MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN
SATAGP1
SATAGP2
SATAGP3
NOT USED
BOARD ID 2
BOARD ID 3
REQ[4]* LDRQ[1]*
CPUGPO[49]
GNT[4]* CPUPWRGD
NORM MFG_MODE* BSKU4 BAT_WARN (FOR DEBUG HDR) - NOT USED DMA66_DETECT_PRI
NA NA
GPO_LAN_DISABLE NA
BSKU5/1_WATT NA FAN_TACH1 FAN_TACH2 5V_DDCSDA 5V_DDCSCL 3V_DDCSDA 3V_DDCSCL CDC_DWN_ENAB* IO_PME* GRN_LED YLW_LED
SLOT1
IRQD IRQA IRQB IRQC
0
16
PA1.5
SLOT2 SLOT3 SLOT4
IRQC IRQB IRQA IRQD
1
17
PA3.0 SENSOR_SDA FANTACH3
FANTACH4
FANPWM1 FANPWM2 FANPWM3 FAN_TACH1 FAN_TACH2 5V_DDCSDA 5V_DDCSCL 3V_DDCSDA 3V_DDCSCL
CDC_DWN_ENAB*
SLOT5
8 7
28 7 6 5 4 3 1
[PAGE_TITLE=GPIO, IRQ, IDSEL MAP]
INTEL
DOCUMENT NUMBER PAGE REV
CONFIDENTIAL
2 1
C77862
D
C
B
A
5
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
J3E1D
10
D
10
10 10
C
10
10
B
H_A*[16..3]
BI
H_REQ*[4..0]
BI
H_ADSTB0*
BI
H_PCREQ*
IN
H_A*[31..17]
BI
TP_CPU_AH4
TP_CPU_AH5 TP_CPU_AJ5
TP_CPU_AJ6 TP_CPU_AC4
H_ADSTB1*
BI
TP_CPU_AE4
L5
3
H_A*3
A<3>*
P6
4
H_A*4
A<4>*
M5
5
H_A*5
A<5>*
L4
6
H_A*6
A<6>*
M4
7
H_A*7
A<7>*
R4
8
H_A*8
A<8>*
T5
9
H_A*9
A<9>*
U6
10
H_A*10
A<10>*
T4
11
H_A*11
A<11>*
U5
12
H_A*12
A<12>*
U4
13
H_A*13
A<13>*
V5
14
H_A*14
A<14>*
V4
15
H_A*15
A<15>*
W5
16
H_A*16
A<16>*
N4
RSVD
P5
TP_CPU_P5
17 18 19 20 21 22 23 24 25 26 27 28 29 30
31
RSVD
K4
0
H_REQ*0
REQ<0>*
J5
1
H_REQ*1
REQ<1>*
M6
2
H_REQ*2
REQ<2>*
K6
3
H_REQ*3
REQ<3>*
J6
4
H_REQ*4
REQ<4>*
R6
ADSTB<0>*
G5
PCREQ*
AB6
H_A*17
A<17>*
W6
H_A*18
A<18>*
Y6
H_A*19
A<19>*
Y4
H_A*20
A<20>*
AA4
H_A*21
A<21>*
AD6
H_A*22
A<22>*
AA5
H_A*23
A<23>*
AB5
H_A*24
A<24>*
AC5
H_A*25
A<25>*
AB4
H_A*26
A<26>*
AF5
H_A*27
A<27>*
AF4
H_A*28
A<28>*
AG6
H_A*29
A<29>*
AG4
H_A*30
A<30>*
AG5
H_A*31
A<31>*
AH4
A<32>*
AH5
A<33>*
AJ5
A<34>*
AJ6
A<35>*
AC4
RSVD
AE4
RSVD
AD5
ADSTB<1>*
2.0
LGA775
BPRI* DBSY* DRDY* HITM* IERR* INIT* LOCK*
TRDY* BINIT* DEFER* EDRDY* MCERR*
AP<0>* AP<1>*
BR<0>*
TESTHI_8 TESTHI_9
TESTHI_10
DP<0>* DP<1>* DP<2>* DP<3>*
GTLREF
RESET*
RS<0>* RS<1>* RS<2>*
1 of 4
ADS* BNR* HIT* RSP*
RSVD
D2
H_ADS*
C2
H_BNR*
D4
H_HIT*
H4
TP_RSP*
G8
H_BPRI*
B2
H_DBSY*
C1
H_DRDY*
E4
H_HITM*
AB2
H_IERR*
P3
H_INIT*
C3
H_LOCK*
E3
H_TRDY*
AD3
TP_BINIT*
G7
H_DEFER*
F2
H_EDRDY*
AB3
TP_MCERR*
U2
TP_AP<0>
U3
TP_AP<1>
F3
H_BR0*
G3
H_TESTHI_8
G4
H_TESTHI_9
H5
H_TESTHI_10
J16
TP_DP<0>
H15
TP_DP<1>
H16
TP_DP<2>
J17
TP_DP<3>
H2 H1
CPU_GTLREF
G23
H_CPURST*
0
B3
H_RS*0
1
F5
H_RS*1
2
A3
H_RS*2
H_RS*[2..0]
IC
10
BI
10
BI
10
BI
10
IN
10
BI
10
BI
10
BI
8
OUT
40
IN
10
BI
10
IN
10
IN
10
OUT
8,10
BI
8
BI
8
BI
8
BI
8
IN
8,10,101
IN
10
IN
CAD NOTE:
PLACE CAPS CLOSE TO CPU BEFORE ROUTING TO CIRCUITS THAT USE THIS VOLTAGE
VTT_OUT_LEFT
7,8,95
IN
J3E1A
LGA775
P2 K3 R3 K1
L1 N2 M3
A23 B23 D23 C23
AM2
0
H_VID_ISOLATE0
AL5
1
H_VID_ISOLATE1
AM3
2
H_VID_ISOLATE2
AL6
3
H_VID_ISOLATE3
AK4
4
H_VID_ISOLATE4
AL4
5
H_VID_ISOLATE5
AM5
F28 G28
AE8
AL1 AK1
AN3 AN4 AN5 AN6
F29
H29
8,40
9 9
9 7
IN IN IN IN IN IN IN
IN IN
IN
OUT
IN IN
OUT
IN
OUT
OUT OUT OUT OUT
OUT
ICH_H_SMI* H_A20M* H_FERR* H_INTR H_NMI H_IGNNE* H_STPCLK*
H_VCCA H_VSSA
H_VCCIOPLL
H_VID_ISOLATE[5..0]
CK_H_CPU CK_H_CPU*
H_SKTOCC*
H_TEMP_RET H_TEMP_SRC
VCC_SENSE VSS_SENSE VCC_PKGSENSE VSS_PKGSENSE
VTT_PKGSENSE
TP_VCCPLL
TP_VID6
17
RSVD_DET
OUT
40 40
40 40 40 40
30 30
74
79 79
87
2.0
SMI* A20M* FERR*/PBE* LINT0 LINT1 IGNNE* STPCLK*
VCCA VSSA RSVD VCCIOPLL
VID<0> VID<1> VID<2> VID<3> VID<4> VID<5> RSVD
BCLK<0> BCLK<1>
SKTOCC*
THERMDA THERMDC
VCC_SENSE VSS_SENSE VCC_MB_REGULATION VSS_MB_REGULATION
RSVD
GND
3 of 4
TESTHI_0
TESTHI_1 TESTHI_11 TESTHI_12
TESTHI_2
TESTHI_3
TESTHI_4
TESTHI_5
TESTHI_6
TESTHI_7
RSVD RSVD
SLP* RSVD
PWRGOOD
PROCHOT*
THERMTRIP*
COMP<0> COMP<1> COMP<2> COMP<3>
RSVD RSVD
RSVD RSVD RSVD RSVD RSVD RSVD
RSVD RSVD RSVD RSVD RSVD RSVD
BOOTSELECT
LL_ID<0>
LL_ID<1>
F26
H_TESTHI_0
W3
H_TESTHI_1
P1
H_TESTHI_11
W2
H_TESTHI_12
F25 G25 G27 G26 G24 F24 AK6 G6
L2 AH2 N1 AL2 M2
A13 T1 G2 R1 J2 T2
N5 AE6 C9 G10 D16 A20
E23 E24 F23 V1 W1 J3
Y1 V2 AA2
TP_H_PSMI*
TP_RSVD_CPU_N5
TP_RSVD_CPU_AE6 TP_RSVD_CPU_C9
TP_RSVD_CPU_G10
TP_RSVD_CPU_D16 TP_RSVD_CPU_A20
H_TESTHI_2_7 RSVD_AK6 RSVD_G6
H_SLP*
H_PWRGD H_PROCHOT* H_THERMTRIP_ICH*
H_COMP0 H_COMP1 H_COMP2 H_COMP3
H_RSVD1 H_RSVD2
CPU_BOOT LL_ID0 TP_LL_ID1
8
IN
8
IN
8
IN IN
8
IN IN IN
40
IN
8,40,101
IN
8,103
IN
8,40
OUT
8
IN
8
IN IN IN IN IN
IN
95
OUT
D
C
B
IC
A
IN
IN
IN
IN
CORE PAGE
VCC_SENSE
VCC_PKGSENSE
VSS_SENSE
VSS_PKGSENSE
R2F16
0 5%
402 EMPTY
R2F17
0
402 CH
R1F3
0 5%
EMPTY402
R1F2
0
4025%CH
8 7
5%
12
12
12
12
VCC_VRM_SENSE
VSS_VRM_SENSE
C2F6
.1UF 20% 25V EMPTY 603
C2E1
.1UF 20% 25V EMPTY 603
2
1
2
1
8,95
OUT
8,95
OUT
VTT_OUT_RIGHT
7,8,95,101
IN
2
1
R2F21
62 5%
EMPTY 402
2
1
R2F4
100 1%
CH 402
2
R3F3
100 1%
CH 402
1
H_COMP2
2
R2F6
62 5%
CH 402
1
H_TESTHI_12 H_COMP2
H_COMP3
RSVD_G6
2
R2F11
62 5%
EMPTY 402
1
2
R2F29
1K 5%
EMPTY 402
1
CPU_BOOT
RSVD_AK6
OUT
OUT
45
12
12
R2F28
R2F18
60.4
60.4
1%
1%
EMPTY
EMPTY
402
402
H_RSVD2
OUT
H_RSVD1
OUT
OUT OUT
OUT
OUT
A
CPU SOCKET
[PAGE_TITLE=CPU-SOCKET]
INTEL
CONFIDENTIAL
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
6
4.0
D
C
B
A
6
10
BI
10
BI
10
BI
10
BI
10
BI
10
BI
10
BI
10
BI
CORE PAGE
<XR_PAGE_TITLE>
BOM NOTE:
H_VID_ISOLATE[5..0]
IN
H_D*[15..0]
H_DBI0* H_STBN0*
H_STBP0 H_D*[31..16]
H_DBI1* H_STBN1*
H_STBP1
8 7
0
1
2
3
4
5
8,17,29
ALWAYS STUFF ON PRODUCT BOARDS
H_VID_ISOLATE0
0
402
H_VID_ISOLATE1
H_VID_ISOLATE2
H_VID_ISOLATE3
H_VID_ISOLATE4
H_VID_ISOLATE5
0 5%
8,17,29
B4
0
H_D*0
C5
1
H_D*1
A4
2
H_D*2
C6
3
H_D*3
A5
4
H_D*4
B6
5
H_D*5
B7
6
H_D*6
A7
7
H_D*7
A10
8
H_D*8
A11
9
H_D*9
B10
10
H_D*10
C11
11
H_D*11
D8
12
H_D*12
B12
13
H_D*13
C12
14
H_D*14
D11
15
H_D*15
A8 C8 B9
G9
16
H_D*16
F8
17
H_D*17
F9
18
H_D*18
E9
19
H_D*19
D7
20
H_D*20
E10
21
H_D*21
D10
22
H_D*22
F11
23
H_D*23
F12
24
H_D*24
D13
25
H_D*25
E13
26
H_D*26
G13
27
H_D*27
F14
28
H_D*28
G14
29
H_D*29
F15
30
H_D*30
G15
31
H_D*31
G11 G12 E12
R1F17
5% CH
R1F19
5%0 CH402
R1F15
5%0 CH402
R1F18
5%0 CH402
R1F20
5%0 CH402
R1F16
CH402
8,17,29
OUT
OUT
D<0>* D<1>* D<2>* D<3>* D<4>* D<5>* D<6>* D<7>* D<8>* D<9>* D<10>* D<11>* D<12>* D<13>* D<14>* D<15>* DBI<0>*
DSTBN<0>* DSTBP<0>
D<16>* D<17>* D<18>* D<19>* D<20>* D<21>* D<22>* D<23>* D<24>* D<25>* D<26>* D<27>* D<28>* D<29>* D<30>* D<31>* DBI<1>*
DSTBN<1>* DSTBP<1>
H_VID[5..0]
12
0
H_VID0
12
1
H_VID1
12
2
H_VID2
12
3
H_VID3
12
4
H_VID4
12
5
H_VID5
H_FSBSEL0 H_FSBSEL0_ISOL
OUT
H_FSBSEL1 H_FSBSEL1_ISOL
H_FSBSEL2 H_FSBSEL2_ISOL
J3E1B
LGA775
2.0
D<32>* D<33>* D<34>* D<35>* D<36>* D<37>* D<38>* D<39>* D<40>* D<41>* D<42>* D<43>* D<44>* D<45>* D<46>* D<47>*
DBI<2>*
DSTBN<2>*
DSTBP<2>
D<48>* D<49>* D<50>* D<51>* D<52>* D<53>* D<54>* D<55>* D<56>* D<57>* D<58>* D<59>* D<60>* D<61>* D<62>* D<63>*
DBI<3>*
DSTBN<3>*
DSTBP<3>
95
OUT
101 101 101 101 101
101
40,43,74,81,101
101 101
R4C20
12
5%0
R4C25
12
5%
0
CH
402
G16
32
H_D*32
E15
33
H_D*33
E16
34
H_D*34
G18
35
H_D*35
G17
36
H_D*36
F17
37
H_D*37
F18
38
H_D*38
E18
39
H_D*39
E19
40
H_D*40
F20
41
H_D*41
E21
42
H_D*42
F21
43
H_D*43
G21
44
H_D*44
E22
45
H_D*45
D22
46
H_D*46
G22
47
H_D*47
D19 G20 G19
D20
48
H_D*48
D17
49
H_D*49
A14
50
H_D*50
C15
51
H_D*51
C14
52
H_D*52
B15
53
H_D*53
C18
54
H_D*54
B16
55
H_D*55
A17
56
H_D*56
B18
57
H_D*57
C21
58
H_D*58
B21
59
H_D*59
B19
60
H_D*60
A19
61
H_D*61
A22
62
H_D*62
B22
63
H_D*63
C20
H_DBI3*
A16
H_STBN3*
C17
H_STBP3
R4C21
H_D*[47..32]
H_DBI2* H_STBN2*
H_STBP2 H_D*[63..48]
CH402
12
5%0 CH402
BI BI BI
2 of 4
IC
28 7 6 5 4 3 1
J3E1C
LGA775
TCK TDI TDO TMS TRST*
BPM<0>* BPM<1>* BPM<2>* BPM<3>* BPM<4>* BPM<5>*
DBR*
ITPCLK<0> ITPCLK<1>
BSEL<0> BSEL<1> BSEL<2>
45
2.0
BOM NOTE:
ALWAYS STUFF ON PRODUCT BOARDS
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
VTT_PWRGD
VTT_OUT VTT_OUT VTT_SEL
4 of 4
A29 B25 B29 B30 C29 A26 B27 C28 A25 A28 A27 C30 A30 C25 C26 C27 B26 D27 D28 D25 D26 B28 D29 D30 AM6
AA1 J1 F27
IC
VTT_PWRGD
VTT_OUT_RIGHT VTT_OUT_LEFT
VTT_SEL
V_FSB_VTT
TPEV_VCCFUSEPRG TPEV_VIDFUSEPRG
8,9,12,17,18,41,43,87
IN
D
VCC3
IN IN
95
IN
OUT
OUT
6,8,95,101
6,8,95
OUT
87
2
R4C22
1K 5%
EMPTY 402
1
C
B
IN
VTT_OUT_RIGHT
6,8,95,101
A
2
2
2
R1F26
R1F25
680
680
5%
OUT OUT
95
H_VID[5..0]
IN
1
5%
CH
CH
402
402
1
H_VID0
H_VID1
0
1
INTEL
CONFIDENTIAL
36
2 1
2
R1F24
R2F42
680
680
5%
5%
CH
CH
402
1
H_VID2
2
402
1
H_VID3
3
DOCUMENT NUMBER PAGE REV
C77862
2
2
1
4
H_VID4
R2F40
680 5%
CH 402
R1F28
680 5%
CH 402
1
H_VID5
5
7
4.0
0
H_BPM*0
1
H_BPM*1
2
H_BPM*2
3
H_BPM*3
4
H_BPM*4
5
H_BPM*5
V_FSB_VTT
2
R4C26
0 5%
CH 402
1
AE1 AD1
AF1 AC1 AG1
AJ2
AJ1 AD2 AG2
AF2 AG3
AC2
AK3
AJ3
G29
H30 G30
2
R4C27
0 5%
CH 402
1
TPEV_VIDFUSEPRG
TPEV_VCCFUSEPRG
H_TCK
IN
H_TDI
IN
H_TDO
OUT
H_TMS
IN
H_TRST*
IN
H_BPM*[5..0]
BI
FP_RST*
IN
XDP_CLKOUT
OUT
XDP_CLKOUT*
OUT
VCCP=AG22,K29,AM26,AL8,AE12,AE11 VCCP=W23,W24,W25,T25,Y28,AL18,AC25,W30,Y30,AN14,AD28,Y26,AC29,M29,U24,J23,AC27,AM18,AM19,AB8 VCCP=AC26,J8,J28,T30,AM9,AF15,AC8,AE14,N23,W29,U29,AC24,AC23,Y23,AN26,AN25,AN11,AN18,Y27,Y25 VCCP=AD24,AE23,AE22,AN19,V8,K8,AE21,AM30,AE19,AC30,AE15,M30,K27,M24,AN21,T8,AC28,N25,AE18,W26 VCCP=AD25,M8,N30,AD26,AJ26,AM29,M25,M26,L8,U25,Y8,AJ12,AD27,U23,M23,AG29,N27,AM22,U28,K28
10
BI
10
BI
10
BI
10
BI
10
BI
10 10 10
VCCP=U8,AK18,AD8,K24,AH28,AH21,AK12,AH22,T29,AM14,AM25,AE9,Y29,AK25,AK19,AG15,J22,T24,AG21,AM21 VCCP=J25,U30,AL21,AG25,AJ18,J19,AH30,J15,AG12,AJ22,J20,AH18,AH26,W27,AL25,AN8,AH14,U27,T23,R8 VCCP=AK22,AN29,AG11,AK26,J10,AJ15,AG26,AN9,AH15,AF18,AL15,J26,J18,J21,AG27,AK15,AF11,AD23,AM15,AF8 VCCP=AK21,AG30,AJ21,AM11,AL11,AJ11,K30,AL14,AN30,AH25,AL12,AJ9,AK11,AG14,N29,AL30,AJ25,AH9,J29,J11 VCCP=K25,P8,K23,AL19,AM8,T26,N28,AH12,AL22,AN15,AJ8,U26,AJ19,T27,AK8,AN12,AG9,N26,AF9,AF22 VCCP=AH11,AJ14,AH19,AH29,AH27,AG28,AL26,AM12,J24,J13,T28,W28,J12,J27,AG19,AL9,AD30,AF21,Y24,AK14 VCCP=J9,M27,AF14,J30,AG18,AA8,AG8,AL29,AD29,W8,AH8,N24,AN22,J14,K26,AF19,N8,AF12,M28,AK9 GND=C10,D12,AM7,C24,K2,C22,AN1,B14,K7,AE16,B11,AL10,AK23,H12,AF7,AK7 GND=H7,E14,L28,Y5,E11,AL16,AL24,AK13,AL3,D21,AL20,D18,AN2,AK16,AK20,AM27,AM1,AL13,AL17,C19 GND=E28,AH7,AK30,D24,AL23,A12,L25,J7,AE28,AE29,K5,J4,AE30,AN20,AF10,AE24,AM24,AN23,H9,H8 GND=H13,AC6,AC7,AH6,C16,AM16,AE25,AE27,AJ28,AJ7,F19,AH13,AD7,AH16,AK17,E17,AH17,AH20,AE5,AH23 GND=AE7,AM13,AH24,AJ30,AJ10,AF3,AK5,AJ16,AF6,AK29,AJ17,F22,AH3,AK10,AM10,F16,AJ23,F13,AG7,F10 GND=L26,AD4,H11,L24,L23,AM23,A15,AH10,B24,L3,H27,A21,AE2,AJ29,A24,AK27,AK28,B20,AM20 GND=H26,B17,H25,H24,AA3,AA7,H23,AA6,H10,H22,H21,H20,H19,H18,AB7,H17,AJ24,AM17,AC3,H14 GND=P28,V6,AK2,P27,P26,AM28,AJ13,W4,P25,AJ20,W7,P23,C7,Y2,L30,L29,D15,AL27,Y7,L27 GND=AA29,N6,N7,AA28,AN13,AA27,AA26,P4,AA25,AA24,P7,E26,V30,R2,V29,V28,R5,V27,R7,E20 GND=AN10,V25,T3,V24,V23,T6,AL7,E25,U1,R29,R28,R27,R26,R25,U7,R24,R23,P30,V3,P29 GND=AF16,AE10,AF13,H6,A18,A2,E2,D9,C4,A6,D6,D5,A9,D3,B1,B5,B8,AJ4,AE26,AH1 GND=E29,V7,C13,AK24,AB30,L6,L7,AB29,M1,AB28,AN17,AB27,AB26,AN16,M7,AB25,AB24,AB23,N3,AA30 GND=F4,AG10,AE13,AF30,H28,F7,AF29,AF28,G1,AF27,AF26,AF25,AN28,AN27,AF24,AF23,AG24,AF17,AN24,H3 GND=AN7,P24,AE20,AE17,E27,T7,R30,AJ27,AB1,AM4,V26,AA23,AL28,AF20,AG23,AG20,E8,AG17,AG16,AG13 NC=F6,Y3,AE3,E7,B13,D14,E6,D1,E5,
8,9,12,17,18,41,43,87
IN
[PAGE_TITLE=CPU-SOCKET]
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
VTT_OUT_RIGHT
6,7,95,101
IN
VTT_OUT_LEFT
6,7,95
IN
D
R3F1
62 5%
CH 402
H_BR0*
1 2
C
V_FSB_VTT
7,9,12,17,18,41,43,87
IN
VTT_OUT_LEFT
6,7,95
IN
B
VCC_VRM_SENSE
6,95
IN
NEVER JUMPER THIS HEADER!!!
VSS_VRM_SENSE
6,95
IN
PRECISION FSB COMPENSATION RESISTORS
A
PLACE RESISTORS OUTSIDE SOCKET CAVITY IF NO ROOM FOR VARIABLE RESISTOR DON'T PLACE.
R4D1
60.4CH1% 402
R2F5
60.4 1% 402
12
12
CH
CORE PAGE
8 7
2
R4C24
62 5%
CH 402
1
7,9,12,17,18,41,43,87
IN
CAD NOTE: PLACE AT
ICH END OF ROUTE
V_FSB_VTT
2
R7H2
62 5%
CH 402
1
2
R4C23
62 5%
EMPTY 402
1
H_TESTHI_0 H_TESTHI_2_7 H_TESTHI_1 H_TESTHI_8 H_TESTHI_9 H_TESTHI_10 H_TESTHI_11
2
R7H3
62 5%
CH 402
1
H_THERMTRIP_ICH*
H_FERR* H_IERR*
H_CPURST*
H_PROCHOT*
H_PWRGD
H_BR0*
TESTHI PIN NAME MAPPING
TESTHI[0] TESTHI[1] ODT TESTHI[5:2] TESTHI[7:6] TESTHI[10:8] TESTHI[11] TESTHI[12]
BYPASSEN
MCLK[3:0] MCLKIO[1:0] BR#[3:1] DPSLP# DT_SVR#
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
RSVD_DET6,17
RSVD_DET
V_FSB_VTT
7,9,12,17,18,41,43,87
IN
2
6,40
OUT
6,40
OUT
6
OUT
OUT OUT
6,10,101
OUT
6,103
OUT
6,40,101
6,10
R4C18
470 5%
CH 402
1
2
R4C15
1K 5%
EMPTY 402
1
2
R4C19
470 5%
CH 402
1
2
R4C16
1K 5%
EMPTY 402
1
2
R4C17
470 5%
CH 402
1
2
R4C14
1K 5%
EMPTY 402
1
H_FSBSEL0 H_FSBSEL1 H_FSBSEL2
DESIGN NOTE:
STRAPPING OPTION FOR DEBUG
OUT OUT OUT
7,17,29
7,17,29 7,17,29
D
C
B
R4C29
1 2
249
1% 402
Q4C4
SOT23 201924-001
FET
VTT_OUT_RIGHT
GTLREF VOLTAGE SHOULD BE 0.67*VTT = 0.8V
6,7,95,101
IN
2
1
2
VCC3
CH
12
R4C11
110
CH 1% 402
H_TESTHI_0
12
R4C13
61.9
CH 1% 402
OUT
C4C3 .1UF
20% 16V
1 2
Y5V 402
1
6
100 OHMS OVER 210 OHMS RESISTORS
R2F23
100 1%
CH 402
CPU_GTLREF_DIVIDER
R2F24
210 1%
CH 402
2
1
C2F2
1.0UF 20% 10V Y5V 603
(FOR THIS DESIGN)
EVAL FEATURE
2
C2F1
220PF 10% 50V
1
EMPTY 402
R2F20
12
CPU_GTLREF
5%
30
CH
402
6
OUT
A
CAD NOTE: PLACE AT
CPU END OF ROUTE
2
2
1
R2F31
62 5%
CH 402
R2F2
100 5%
CH 402
1
2
R2F19
62 5%
EMPTY 402
1
2
R2F25
62 5%
CH 402
1
CPU SIGNAL TERMINATION
TESTHI PULLUPS
2
2
2
2
R2F3
62 5%
CH 402
1
1
1
1X2HDR
EMPTY 102276-001
2
H_COMP0
H_COMP1
R3F2
R2F1
62
62
5%
5%
CH
CH
402
402
1
J1F1
6
OUT
6
OUT
2
R3F4
R2F7
62
62
5%
5%
CH
CH
402
1
402
1
DESIGN NOTE: THE PINS WILL BE USED AS TEST/PROBE POINTS ONLY.
CAD NOTE: PLACE HEADERS AS CLOSE TO CPU PINS AS POSSIBLE
[PAGE_TITLE=CPU TERMINATION & MISC]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
8
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
D
CPU PLL SUPPLY FILTER
V_FSB_VTT
7,8,12,17,18,41,43,87
IN
1
693286-014
FB4C1
FB
2
C
7,8,12,17,18,41,43,87
IN
1
693286-014
FB4C2
FB
2
B
V_FSB_VTT
1
2
1
2
10UH
L4C2
EMPTY
721891-026
"125 MA" "0805"
10UH
L4C1
EMPTY
721891-026
"125 MA" "0805"
"201307-107"
H_VCCIOPLL
2
R4C12
0 5%
CH
402
1
2
C4C5
1.0UF 20% 10V
1
EMPTY
603
"Y5V"
H_VCCA
R4C7
1
C4C1
2
33UF 20% 25V ALUM
2
RDL
C4C4
1.0UF 20% 10V
1
EMPTY
603
"Y5V"
1 2
0 5%
402
EMPTY
DESIGN NOTE:
ALWAYS EMPTY. DEBUG HOOK.
H_VSSA
OUT
OUT
TP_H_VCCA_STEP
OUT
6
C
6
B
6
A
CORE PAGE
CAD NOTE: PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET TRACE WIDTH TO CAPS MUST BE NO SMALLER THAN 12MIL
8 7
A
[PAGE_TITLE=CPU ANALOG PLL FILTER]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
9
4.0
<XR_PAGE_TITLE>
U6D1G
GDG_DDR1_1210
6
H_A*[31..3]
D
J4D1
J6F1
J4F1
1
NC
A13494-005
EMPTY
1
NC
EMPTY
1
NC
EMPTY
J6D1
1
NC
EMPTY
HS6D1
GDG_WAVEHS
1 2
NC_2
NC_1
NC_3
NC_4
C44993-001
HEATSINK
34
BI
WAVE SOLDER HEAT-SINK = WSHS
C
6
H_REQ*[4..0]
BI
6
H_ADSTB0*
BI
6
H_ADSTB1*
BI
6
H_PCREQ*
OUT
7
H_STBP0
BI
7
H_STBN0*
BI
7
H_DBI0*
B
A
BI
7
H_STBP1
BI
7
H_STBN1*
BI
7
H_DBI1*
BI
7
H_STBP2
BI
7
H_STBN2*
BI
7
H_DBI2*
BI
7
H_STBP3
BI
7
H_STBN3*
BI
7
H_DBI3*
BI
6
H_ADS*
BI
6
H_BNR*
BI
6
H_BPRI*
OUT
6,8
H_BR0*
OUT
6,8,101
H_CPURST*
OUT
6
H_DBSY*
BI
6
H_DEFER*
OUT
6
H_DRDY*
OUT
6
H_EDRDY*
IN
6
H_HIT*
OUT
6
H_HITM*
OUT
6
H_LOCK*
IN
6
H_RS*[2..0]
BI
6
H_TRDY*
OUT
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 1 2 3 4
0 1 2
H29
H_A*3
H_A*4
H_A*5
H_A*6
H_A*7
H_A*8
H_A*9
H_A*10
H_A*11
H_A*12
H_A*13
H_A*14
H_A*15
H_A*16
H_A*17
H_A*18
H_A*19
H_A*20
H_A*21
H_A*22
H_A*23
H_A*24
H_A*25
H_A*26
H_A*27
H_A*28
H_A*29
H_A*30
H_A*31
H_REQ*0
H_REQ*1
H_REQ*2
H_REQ*3
H_REQ*4
H_RS*0
H_RS*1
H_RS*2
HA3*
K29
HA4*
J29
HA5*
G30
HA6*
G32
HA7*
K30
HA8*
L29
HA9*
M30
HA10*
L31
HA11*
L28
HA12*
J28
HA13*
K27
HA14*
K33
HA15*
M28
HA16*
R29
HA17*
L26
HA18*
N26
HA19*
M26
HA20*
N31
HA21*
P26
HA22*
N29
HA23*
P28
HA24*
R28
HA25*
N33
HA26*
T27
HA27*
T31
HA28*
U28
HA29*
T26
HA30*
T29
HA31*
F33
HREQ0*
E32
HREQ1*
H31
HREQ2*
G31
HREQ3*
F31
HREQ4*
J31
HADSTB0*
N27
HADSTB1*
E31
HPCREQ*
E33
HDSTBP0
E35
HDSTBN0*
E34
HDINV0*
H26
HDSTBP1
F26
HDSTBN1*
J26
HDINV1*
J19
HDSTBP2
F19
HDSTBN2*
K19
HDINV2*
B29
HDSTBP3
C29
HDSTBN3*
B26
HDINV3*
M31
HADS*
M35
HBNR*
E30
HBPRI*
R33
HBREQ0*
G24
HCPURST*
L35
HDBSY*
J35
HDEFER*
M32
HDRDY*
P33
HEDRDY*
L34
HHIT*
N35
HHITM*
L33
HLOCK*
K34
HRS0*
P34
HRS1*
J32
HRS2*
N34
HTRDY*
1.0
HD0* HD1* HD2* HD3* HD4* HD5* HD6* HD7* HD8* HD9*
HD10* HD11* HD12* HD13* HD14* HD15* HD16* HD17* HD18* HD19* HD20* HD21* HD22* HD23* HD24* HD25* HD26* HD27* HD28* HD29* HD30* HD31* HD32* HD33* HD34* HD35* HD36* HD37* HD38* HD39* HD40* HD41* HD42* HD43* HD44* HD45* HD46* HD47* HD48* HD49* HD50* HD51* HD52* HD53* HD54* HD55* HD56* HD57* HD58* HD59* HD60* HD61* HD62* HD63*
HXSWING HXSCOMP HXRCOMP
HVREF
HCLKINP HCLKINN
1 of 7
J33 H33 J34 G35 H35 G34 F34 G33 D34 C33 D33 B34 C34 B33 C32 B32 E28 C30 D29 H28 G29 J27 F28 F27 E27 E25 G25 J25 K25 L25 L23 K23 J22 J24 K22 J21 M21 H23 M19 K21 H20 H19 M18 K18 K17 G18 H18 F17 A25 C27 C31 B30 B31 A31 B27 A29 C28 A28 C25 C26 D27 A27 E24 B25
A23 D24 B23 A24
M23 M22
IC
0
H_D*0
1
H_D*1
2
H_D*2
3
H_D*3
4
H_D*4
5
H_D*5
6
H_D*6
7
H_D*7
8
H_D*8
9
H_D*9
10
H_D*10
11
H_D*11
12
H_D*12
13
H_D*13
14
H_D*14
15
H_D*15
16
H_D*16
17
H_D*17
18
H_D*18
19
H_D*19
20
H_D*20
21
H_D*21
22
H_D*22
23
H_D*23
24
H_D*24
25
H_D*25
26
H_D*26
27
H_D*27
28
H_D*28
29
H_D*29
30
H_D*30
31
H_D*31
32
H_D*32
33
H_D*33
34
H_D*34
35
H_D*35
36
H_D*36
37
H_D*37
38
H_D*38
39
H_D*39
40
H_D*40
41
H_D*41
42
H_D*42
43
H_D*43
44
H_D*44
45
H_D*45
46
H_D*46
47
H_D*47
48
H_D*48
49
H_D*49
50
H_D*50
51
H_D*51
52
H_D*52
53
H_D*53
54
H_D*54
55
H_D*55
56
H_D*56
57
H_D*57
58
H_D*58
59
H_D*59
60
H_D*60
61
H_D*61
62
H_D*62
63
H_D*63
28 7 6 5 4 3 1
H_D*[63..0]
HXSWING HXSCOMP HXRCOMP
MCH_GTLREF
CK_H_MCH
CK_H_MCH*
BI
17
IN
17
IN
17
IN
17
IN
30
IN
30
IN
7
D
C
B
A
CORE PAGE
8 7
[PAGE_TITLE=MCH SECTIONS PAGE 1 OF 6]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
10
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
C
SIGNAL NAMING CONVENTION
EXP: PCI EXPRESS DMI: DIRECT MEDIA INTERFACE ITP: ICH TRANSMIT POSITIVE ITN: ICH TRANSMIT NEGATIVE
B
IRP: ICH RECEIVE POSITIVE IRN: ICH RECEIVE NEGATIVE MTP: MCH TRANSMIT POSITIVE MTN: MCH TRANSMIT NEGATIVE MRP: MCH RECEIVE POSITIVE
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
32
IN
38,100
BI
38,100
BI
38,100
BI
38,100
BI
38,100
BI
38,100
BI
38,100
BI
38,100
BI
30
IN
30
IN
32
BI
32
OUT
EXP_A_RXP_0 EXP_A_RXN_0 EXP_A_RXP_1 EXP_A_RXN_1 EXP_A_RXP_2 EXP_A_RXN_2 EXP_A_RXP_3 EXP_A_RXN_3 EXP_A_RXP_4 EXP_A_RXN_4 EXP_A_RXP_5 EXP_A_RXN_5 EXP_A_RXP_6 EXP_A_RXN_6 EXP_A_RXP_7 EXP_A_RXN_7 EXP_A_RXP_8 EXP_A_RXN_8 EXP_A_RXP_9 EXP_A_RXN_9 EXP_A_RXP_10 EXP_A_RXN_10 EXP_A_RXP_11 EXP_A_RXN_11 EXP_A_RXP_12 EXP_A_RXN_12 EXP_A_RXP_13 EXP_A_RXN_13 EXP_A_RXP_14 EXP_A_RXN_14 EXP_A_RXP_15 EXP_A_RXN_15
CK_PE_100M_MCH CK_PE_100M_MCH*
SDVO_CTRL_DATA SDVO_CTRL_CLK
DMI_ITP_MRP_0 DMI_ITN_MRN_0 DMI_ITP_MRP_1 DMI_ITN_MRN_1 DMI_ITP_MRP_2 DMI_ITN_MRN_2 DMI_ITP_MRP_3 DMI_ITN_MRN_3
E11 F11
J11
H11
F9 E9 F7 E7 B3 B4 D5 E5 G6 G5 H8 H7
J6
J5 K8 K7
L6
L5
P10 R10
M8 M7 N6 N5 P7 P8 R6 R5
U5
U6
T9
T8
V7
V8
V10 U10
A11 B11
K13
J13
EXPARXP0 EXPARXN0 EXPARXP1 EXPARXN1 EXPARXP2 EXPARXN2 EXPARXP3 EXPARXN3 EXPARXP4 EXPARXN4 EXPARXP5 EXPARXN5 EXPARXP6 EXPARXN6 EXPARXP7 EXPARXN7 EXPARXP8 EXPARXN8 EXPARXP9 EXPARXN9 EXPARXP10 EXPARXN10 EXPARXP11 EXPARXN11 EXPARXP12 EXPARXN12 EXPARXP13 EXPARXN13 EXPARXP14 EXPARXN14 EXPARXP15 EXPARXN15
DMIRXP0 DMIRXN0 DMIRXP1 DMIRXN1 DMIRXP2 DMIRXN2 DMIRXP3 DMIRXN3
GCLKINP GCLKINN
SDVOCTRLDATA SDVOCTRLCLK
MRN: MCH RECEIVE NEGATIVE
U6D1A
GDG_DDR1_1210
1.0
EXPATXP0 EXPATXN0 EXPATXP1 EXPATXN1 EXPATXP2 EXPATXN2 EXPATXP3 EXPATXN3 EXPATXP4 EXPATXN4 EXPATXP5 EXPATXN5 EXPATXP6 EXPATXN6 EXPATXP7 EXPATXN7 EXPATXP8 EXPATXN8 EXPATXP9 EXPATXN9
EXPATXP10 EXPATXN10 EXPATXP11 EXPATXN11 EXPATXP12 EXPATXN12 EXPATXP13 EXPATXN13 EXPATXP14 EXPATXN14 EXPATXP15 EXPATXN15
DMITXP0 DMITXN0 DMITXP1 DMITXN1 DMITXP2 DMITXN2 DMITXP3 DMITXN3
EXPACOMPO EXPACOMPI
2 of 7
C10 C9 A9 A8 C8 C7 A7 A6 C6 C5 C2 D2 E3 F3 F1 G1 G3 H3 H1 J1 J3 K3 K1 L1 L3 M3 M1 N1 N3 P3 P1 R1
R3 T3 T1 U1 U3 V3 V5 W5
Y10 W10
EXP_A_TXP_0 EXP_A_TXN_0 EXP_A_TXP_1 EXP_A_TXN_1 EXP_A_TXP_2 EXP_A_TXN_2 EXP_A_TXP_3 EXP_A_TXN_3 EXP_A_TXP_4 EXP_A_TXN_4 EXP_A_TXP_5 EXP_A_TXN_5 EXP_A_TXP_6 EXP_A_TXN_6 EXP_A_TXP_7 EXP_A_TXN_7 EXP_A_TXP_8 EXP_A_TXN_8 EXP_A_TXP_9 EXP_A_TXN_9 EXP_A_TXP_10 EXP_A_TXN_10 EXP_A_TXP_11 EXP_A_TXN_11 EXP_A_TXP_12 EXP_A_TXN_12 EXP_A_TXP_13 EXP_A_TXN_13 EXP_A_TXP_14 EXP_A_TXN_14 EXP_A_TXP_15 EXP_A_TXN_15
DMI_MTP_IRP_0 DMI_MTN_IRN_0 DMI_MTP_IRP_1 DMI_MTN_IRN_1 DMI_MTP_IRP_2 DMI_MTN_IRN_2 DMI_MTP_IRP_3 DMI_MTN_IRN_3
GRCOMP
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
33
OUT
38,100
BI
38,100
BI
38,100
BI
38,100
BI
38,100
BI
38,100
BI
38,100
BI
38,100
BI
17
IN
D
C
B
IC
A
SDVO CTRL DATA
1 SDVO CARD PRESENT, PEG DISABLED 0 SDVO DISABLED (DEFAULT)
CORE PAGE
8 7
A
[PAGE_TITLE=MCH SECTIONS PAGE 2 OF 6]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
11
4.0
<XR_PAGE_TITLE>
U6D1B
GDG_DDR1_1210
V_1P5_CORE
15..17,38,39,41,79,87,88,102
IN
D
15..17,38,39,41,79,87,88,102
V_1P5_CORE
IN
C
B
A
AC11 AB11
AA13 AA14 AA16 AA18 AA20 AA21 AA22 AA23 AA24 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24
Y20 Y19 Y17
Y16 W20 W16
U20
U16
T20
T19
T17
T16
N13
N14
N15
N16
N18
N20
N21
P13
P14
P15
P17
P19
P21
P22
R13
R14
R15
R16
R18
R20
R22
R23
T13
T14
T15
T21
T23
T24
U13
U14
U22
U24
V13
V14
V15
V21
V23
V24 W13 W14 W22 W24
Y13
Y14
Y15
Y21
Y23
Y24
CORE PAGE
8 7
VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF
VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF VCCNCTF
1.0
VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF
VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF VSSNCTF
RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD
7 of 7
AC25 AB25 AA25 AA11 Y25 Y18 Y11 W25 W11 V25 V20 V16 V11 U25 U11 T25 T18 T11 R25 R11 P25 P11 N25 AD25 N11 M11
AA15 AA17 AA19 N17 N19 P16 P18 P20 R17 R19 R21 T22 U15 U21 U23 V22 W15 W21 W23 Y22
AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22
N12
NC
N22
NC
N23
NC
N24
NC
P12
NC
P23
NC
P24
NC
R12
NC
R24
NC
T12
NC
U12
NC
V12
NC
W12
NC
Y12
NC
AA12
NC
AB12
NC
AC23
NC
AC24
NC
DESIGN NOTE:
RSRVD PINS DO NOT NEED TO BE TESTPOINTED IN THIS INSTANCE
15..17,38,39,41,79,87,88,102
15,16,87,88
17
16 16 16 16 16
16,18
IN
IN
IN IN IN IN IN
IN
IN
V_1P5_CORE
V_1P5_PCIEXPRESS
VCCA_HPLL VCCA_MPLL
VCCA_DPLLA VCCA_DPLLB
VCCA_GPLL
V_2P5_MCH
V_2P5_DAC_FILTERED
AD10
AC10
AB10
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1
AC9 AC8 AC7 AC6 AC5 AC4 AC3 AC2 AC1
AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1
W18
V19 V17 U18
Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2
Y1 W9 W8 W7 W6 W4 W3 W2 W1
A17 B17 A12 B13 A14
A13 E13 D13 F13
GDG_DDR1_1210
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC3G VCC3G VCC3G VCC3G VCC3G VCC3G VCC3G VCC3G VCC3G VCC3G VCC3G VCC3G VCC3G VCC3G VCC3G VCC3G VCC3G
VCCAHPLL VCCAMPLL VCCADPLLA VCCADPLLB VCCA3GPLL
VCCHV VCCACRTDAC VCCACRTDAC VSSACRTDAC
U6D1C
1.0
VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM
6 of 7
AR33 AR31 AR26 AR22 AR18 AR14 AR10 AP28 AP24 AP20 AP16 AP12 AN35 AM32 AM28 AM26 AM25 AM23 AM22 AM20 AM19 AM17 AM16 AM14 AM13 AM11 AM10 AK35
H22
VTT
G22
VTT
G21
VTT
F22
VTT
F21
VTT
F20
VTT
E22
VTT
E21
VTT
E20
VTT
E19
VTT
D22
VTT
D21
VTT
D20
VTT
D19
VTT
C22
VTT
C21
VTT
C20
VTT
C19
VTT
B22
VTT
B21
VTT
B20
VTT
B19
VTT
A22
VTT
A21
VTT
A20
VTT
A19
VTT
IC
[PAGE_TITLE=MCH SECTIONS PAGE 3 OF 6]
IC
45
36
28 7 6 5 4 3 1
V_SM
V_FSB_VTT
INTEL
DOCUMENT NUMBER PAGE REV
CONFIDENTIAL
2 1
IN
IN
C77862
18,19,21,24,25,28,85,89
7..9,17,18,41,43,87
D
C
B
A
12
4.0
<XR_PAGE_TITLE>
U6D1D
SACS0* SACS1* SACS2* SACS3*
SACKE0 SACKE1 SACKE2 SACKE3
RSVRD RSVRD RSVRD RSVRD
4 of 7
GDG_DDR1_1210
DDRA
1.0
SADQS0 RSVRD SADM0 SADQ0 SADQ1 SADQ2 SADQ3 SADQ4 SADQ5 SADQ6 SADQ7
SADQS1 RSVRD SADM1 SADQ8
SADQ9 SADQ10 SADQ11 SADQ12 SADQ13 SADQ14 SADQ15
SADQS2
RSVRD
SADM2 SADQ16 SADQ17 SADQ18 SADQ19 SADQ20 SADQ21 SADQ22 SADQ23
SADQS3
RSVRD
SADM3 SADQ24 SADQ25 SADQ26 SADQ27 SADQ28 SADQ29 SADQ30 SADQ31
SADQS4
RSVRD
SADM4 SADQ32 SADQ33 SADQ34 SADQ35 SADQ36 SADQ37 SADQ38 SADQ39
SADQS5
RSVRD
SADM5 SADQ40 SADQ41 SADQ42 SADQ43 SADQ44 SADQ45 SADQ46 SADQ47
SADQS6
RSVRD
SADM6 SADQ48 SADQ49 SADQ50 SADQ51 SADQ52 SADQ53 SADQ54 SADQ55
SADQS7
RSVRD
SADM7 SADQ56 SADQ57 SADQ58 SADQ59 SADQ60 SADQ61 SADQ62 SADQ63
AG1 AG2 AF2 AE3 AF3 AH3 AJ2 AE2 AE1 AG3 AH2
AL3 AL2 AL1 AK2 AK3 AN4 AP4 AJ1 AJ3 AP2 AP3
AP7 AR7 AN7 AR5 AP6 AP9 AN9 AN5 AP5 AN8 AR8
AF17 AG17 AH16 AL17 AJ17 AF19 AH18 AK16 AF16 AD17 AE19
AM30 AL29 AK29 AK27 AJ28 AL31 AK31 AH27 AL27 AN30 AL30
AG35 AG33 AG34 AH33 AH35 AF33 AE33 AJ33 AJ34 AG32 AF34
AA34 AA35 AA33 AD31 AD35 Y33 W34 AE35 AE34 AA32 Y35
U34 U35 U33 V34 V33 R32 R34 W35 W33 T33 T35
IC
45
BI
OUT OUT OUT
BI
BI
BI
21
BI
21
BI
21
BI
21
BI
21
BI
21
BI
21
BI
21
BI
21
BI
21
BI
21
BI
21
BI
19
IN
M_MAA_A[13..0]
M_WE_A* M_CAS_A* M_RAS_A*
M_SBS_A[1..0]
M_SCS_A*[3..0]
M_SCKE_A[3..0]
CK_M_166M_P_DDR0_A CK_M_166M_N_DDR0_A CK_M_166M_P_DDR1_A CK_M_166M_N_DDR1_A CK_M_166M_P_DDR2_A CK_M_166M_N_DDR2_A
CK_M_166M_P_DDR3_A CK_M_166M_N_DDR3_A CK_M_166M_P_DDR4_A CK_M_166M_N_DDR4_A CK_M_166M_P_DDR5_A CK_M_166M_N_DDR5_A
TP_SA_RCVENOUT TP_SA_RCVENIN
SM_XSLEWIN
MCH_VREF_A
0 1 2 3 4 5 6 7 8 9 10 11 12
0 1
0 1 2 3
0 1 2 3
AN22
M_MAA_A0
M_MAA_A1
M_MAA_A2
M_MAA_A3
M_MAA_A4
M_MAA_A5
M_MAA_A6
M_MAA_A7
M_MAA_A8
M_MAA_A9
M_MAA_A10
M_MAA_A11
M_MAA_A12
M_SBS_A0
M_SBS_A1
M_SCS_A*0
M_SCS_A*1
M_SCS_A*2
M_SCS_A*3
M_SCKE_A0
M_SCKE_A1
M_SCKE_A2
M_SCKE_A3
13
M_MAA_A13
AP22 AN21 AP21 AM21 AP19 AR20 AN16 AN18 AM15 AN23 AP15 AP13 AN31
AP31
AN29
AN28 AP26 AR23
AM34
AK34
AN11 AP11 AR11
AP33 AR24 AR28 AR29
AM24 AN25
AB34 AC33
AP25 AN26
AC35 AC34
AB33
AH15 AE16
AK12
SAMA0 SAMA1 SAMA2 SAMA3 SAMA4 SAMA5 SAMA6 SAMA7 SAMA8 SAMA9 SAMA10 SAMA11 SAMA12 RSVRD
SAWE*
AL34
SACAS* SARAS*
SABA0 SABA1 RSVRD
AL35
AL33
AL12
SACK0 SACK0*
AN2
SACK1
AN3
SACK1* SACK2 SACK2*
SACK3 SACK3*
AM2
SACK4
AM3
SACK4* SACK5 SACK5*
SADDR1MA13
SARCVENOUT* SARCVENIN*
AJ12
SMXSLEWIN SMXSLEWOUT
AE7
SMVREF0
21,22
D
21,23 21,23 21,23
21,23
21,23
21,23
C
B
BI
M_MAA_A[13..0]
21,22
A
CORE PAGE
8 7
0
M_DQS_A0
0
M_DQM_A0
0
M_DATA_A0
1
M_DATA_A1
2
M_DATA_A2
3
M_DATA_A3
4
M_DATA_A4
5
M_DATA_A5
6
M_DATA_A6
7
M_DATA_A7
1
M_DQS_A1
1
M_DQM_A1
8
M_DATA_A8
9
M_DATA_A9
10
M_DATA_A10
11
M_DATA_A11
12
M_DATA_A12
13
M_DATA_A13
14
M_DATA_A14
15
M_DATA_A15
2
M_DQS_A2
2
M_DQM_A2
16
M_DATA_A16
17
M_DATA_A17
18
M_DATA_A18
19
M_DATA_A19
20
M_DATA_A20
21
M_DATA_A21
22
M_DATA_A22
23
M_DATA_A23
3
M_DQS_A3
3
M_DQM_A3
24
M_DATA_A24
25
M_DATA_A25
26
M_DATA_A26
27
M_DATA_A27
28
M_DATA_A28
29
M_DATA_A29
30
M_DATA_A30
31
M_DATA_A31
4
M_DQS_A4
4
M_DQM_A4
32
M_DATA_A32
33
M_DATA_A33
34
M_DATA_A34
35
M_DATA_A35
36
M_DATA_A36
37
M_DATA_A37
38
M_DATA_A38
39
M_DATA_A39
5
M_DQS_A5
5
M_DQM_A5
40
M_DATA_A40
41
M_DATA_A41
42
M_DATA_A42
43
M_DATA_A43
44
M_DATA_A44
45
M_DATA_A45
46
M_DATA_A46
47
M_DATA_A47
6
M_DQS_A6
6
M_DQM_A6
48
M_DATA_A48
49
M_DATA_A49
50
M_DATA_A50
51
M_DATA_A51
52
M_DATA_A52
53
M_DATA_A53
54
M_DATA_A54
55
M_DATA_A55
7
M_DQS_A7
7
M_DQM_A7
56
M_DATA_A56
57
M_DATA_A57
58
M_DATA_A58
59
M_DATA_A59
60
M_DATA_A60
61
M_DATA_A61
62
M_DATA_A62
63
M_DATA_A63
M_DQS_A[7..0] M_DQM_A[7..0]
M_DATA_A[63..0]
M_DQS_A[7..0] M_DQM_A[7..0]
M_DATA_A[63..0]
M_DQS_A[7..0] M_DQM_A[7..0]
M_DATA_A[63..0]
M_DQS_A[7..0] M_DQM_A[7..0]
M_DATA_A[63..0]
M_DQS_A[7..0] M_DQM_A[7..0]
M_DATA_A[63..0]
M_DQS_A[7..0] M_DQM_A[7..0]
M_DATA_A[63..0]
M_DQS_A[7..0] M_DQM_A[7..0]
M_DATA_A[63..0]
M_DQS_A[7..0] M_DQM_A[7..0]
M_DATA_A[63..0]
BI
BI BI
BI
BI BI
BI
BI BI
BI
BI BI
BI
BI BI
BI
BI BI
BI
BI BI
BI
BI BI
21,23
21,22 21,22
21,23
21,22 21,22
21,23
21,22 21,22
21,23
21,22 21,22
21,23
21,22 21,22
21,23
21,22 21,22
21,23
21,22 21,22
21,23
21,22 21,22
[PAGE_TITLE=MCH SECTIONS PAGE 4 OF 6]
36
28 7 6 5 4 3 1
INTEL
DOCUMENT NUMBER PAGE REV
CONFIDENTIAL
2 1
C77862
D
C
B
A
13
4.0
D
C
B
A
CORE PAGE
<XR_PAGE_TITLE>
8 7
U6D1E
SBCS0* SBCS1* SBCS2* SBCS3*
SBCKE0 SBCKE1 SBCKE2 SBCKE3
RSVRD RSVRD RSVRD RSVRD
SBDDR1MA13
SBRCVENOUT* SBRCVENIN*
SMYSLEWIN SMYSLEWOUT
SMVREF1
SMRCOMPP SMRCOMPN SMOCDCOMP1 SMOCDCOMP0
3 of 7
GDG_DDR1_1210
DDRB
1.0
SBDQS0 RSVRD SBDM0 SBDQ0 SBDQ1 SBDQ2SBMA5 SBDQ3 SBDQ4 SBDQ5 SBDQ6 SBDQ7
SBDQS1 RSVRD SBDM1 SBDQ8
SBDQ9 SBDQ10 SBDQ11 SBDQ12 SBDQ13 SBDQ14 SBDQ15
SBDQS2
RSVRD
SBDM2 SBDQ16 SBDQ17 SBDQ18 SBDQ19 SBDQ20 SBDQ21 SBDQ22 SBDQ23
SBDQS3
RSVRD
SBDM3 SBDQ24 SBDQ25 SBDQ26 SBDQ27 SBDQ28 SBDQ29 SBDQ30 SBDQ31
SBDQS4
RSVRD
SBDM4 SBDQ32 SBDQ33 SBDQ34 SBDQ35 SBDQ36 SBDQ37 SBDQ38 SBDQ39
SBDQS5
RSVRD
SBDM5 SBDQ40 SBDQ41 SBDQ42 SBDQ43 SBDQ44 SBDQ45 SBDQ46 SBDQ47
SBDQS6
RSVRD
SBDM6 SBDQ48 SBDQ49 SBDQ50 SBDQ51 SBDQ52 SBDQ53 SBDQ54 SBDQ55
SBDQS7
RSVRD
SBDM7 SBDQ56 SBDQ57 SBDQ58 SBDQ59 SBDQ60 SBDQ61 SBDQ62 SBDQ63
AK5 AL4 AJ5 AH4 AJ6 AL6 AN6 AG9 AH7 AL5 AM5
AK10 AH10 AH9 AJ8 AL8 AF11 AE11 AJ7 AL7 AG10 AG11
AK13 AL14 AH13 AF13 AH12 AD14 AD15 AD12 AE13 AG14 AF14
AD20 AF20 AG20 AK19 AH19 AH21 AD21 AD18 AL18 AE22 AF22
AH25 AG26 AG24 AF24 AF25 AL26 AJ26 AF23 AD23 AL25 AJ25
AH28 AH30 AH31 AK32 AJ31 AG31 AF28 AJ29 AK33 AG30 AG27
AB31 AC30 AD24 AF27 AE27 AC26 AB26 AE31 AE29 AC28 AB27
W27 Y28 W31 AA28 W29 V28 V29 Y26 AA29 W26 U26
0
M_DQS_B0
0
M_DQM_B0
0
M_DATA_B0
1
M_DATA_B1
2
M_DATA_B2
3
M_DATA_B3
4
M_DATA_B4
5
M_DATA_B5
6
M_DATA_B6
7
M_DATA_B7
1
M_DQS_B1
1
M_DQM_B1
8
M_DATA_B8
9
M_DATA_B9
10
M_DATA_B10
11
M_DATA_B11
12
M_DATA_B12
13
M_DATA_B13
14
M_DATA_B14
15
M_DATA_B15
2
M_DQS_B2
2
M_DQM_B2
16
M_DATA_B16
17
M_DATA_B17
18
M_DATA_B18
19
M_DATA_B19
20
M_DATA_B20
21
M_DATA_B21
22
M_DATA_B22
23
M_DATA_B23
3
M_DQS_B3
3
M_DQM_B3
24
M_DATA_B24
25
M_DATA_B25
26
M_DATA_B26
27
M_DATA_B27
28
M_DATA_B28
29
M_DATA_B29
30
M_DATA_B30
31
M_DATA_B31
4
M_DQS_B4
4
M_DQM_B4
32
M_DATA_B32
33
M_DATA_B33
34
M_DATA_B34
35
M_DATA_B35
36
M_DATA_B36
37
M_DATA_B37
38
M_DATA_B38
39
M_DATA_B39
5
M_DQS_B5
5
M_DQM_B5
40
M_DATA_B40
41
M_DATA_B41
42
M_DATA_B42
43
M_DATA_B43
44
M_DATA_B44
45
M_DATA_B45
46
M_DATA_B46
47
M_DATA_B47
6
M_DQS_B6
6
M_DQM_B6
48
M_DATA_B48
49
M_DATA_B49
50
M_DATA_B50
51
M_DATA_B51
52
M_DATA_B52
53
M_DATA_B53
54
M_DATA_B54
55
M_DATA_B55
7
M_DQS_B7
7
M_DQM_B7
56
M_DATA_B56
57
M_DATA_B57
58
M_DATA_B58
59
M_DATA_B59
60
M_DATA_B60
61
M_DATA_B61
62
M_DATA_B62
63
M_DATA_B63
M_DQS_B[7..0] M_DQM_B[7..0]
M_DATA_B[63..0]
M_DQS_B[7..0] M_DQM_B[7..0]
M_DATA_B[63..0]
M_DQS_B[7..0] M_DQM_B[7..0]
M_DATA_B[63..0]
M_DQS_B[7..0] M_DQM_B[7..0]
M_DATA_B[63..0]
M_DQS_B[7..0] M_DQM_B[7..0]
M_DATA_B[63..0]
M_DQS_B[7..0] M_DQM_B[7..0]
M_DATA_B[63..0]
M_DQS_B[7..0] M_DQM_B[7..0]
M_DATA_B[63..0]
M_DQS_B[7..0] M_DQM_B[7..0]
M_DATA_B[63..0]
BI
BI BI
BI
BI BI
BI
BI BI
BI
BI BI
BI
BI BI
BI
BI BI
BI
BI BI
BI
BI BI
[PAGE_TITLE=MCH SECTIONS PAGE 5 OF 6]
25,27
25,26 25,26
25,27
25,26 25,26
25,27
25,26 25,26
25,27
25,26 25,26
25,27
25,26 25,26
25,27
25,26 25,26
25,27
25,26 25,26
25,27
25,26 25,26
IC
45
36
25,26
25,27 25,27 25,27
25,27
25,27
25,27
25,26
BI
M_MAA_B[13..0]
25 25 25 25 25 25
25 25 25 25 25 25
BI
OUT OUT OUT
BI
BI
BI
BI BI BI BI BI BI
BI BI BI BI BI BI
19
IN
19
IN
19
IN
M_MAA_B[13..0]
M_WE_B* M_CAS_B* M_RAS_B*
M_SBS_B[1..0]
M_SCS_B*[3..0]
M_SCKE_B[3..0]
CK_M_166M_P_DDR0_B CK_M_166M_N_DDR0_B CK_M_166M_P_DDR1_B CK_M_166M_N_DDR1_B CK_M_166M_P_DDR2_B CK_M_166M_N_DDR2_B
CK_M_166M_P_DDR3_B CK_M_166M_N_DDR3_B CK_M_166M_P_DDR4_B CK_M_166M_N_DDR4_B CK_M_166M_P_DDR5_B CK_M_166M_N_DDR5_B
TP_SB_RCVENOUT TP_SB_RCVENIN
SM_YSLEWIN
MCH_VREF_B
SMRCOMP_P SMRCOMP_N
0 1 2 3 4 5 6 7 8 9 10 11 12
0 1
0 1 2 3
0 1 2 3
AM18
M_MAA_B0
M_MAA_B1
M_MAA_B2
M_MAA_B3
M_MAA_B4
M_MAA_B5
M_MAA_B6
M_MAA_B7
M_MAA_B8
M_MAA_B9
M_MAA_B10
M_MAA_B11
M_MAA_B12
M_SBS_B0
M_SBS_B1
M_SCS_B*0
M_SCS_B*1
M_SCS_B*2
M_SCS_B*3
M_SCKE_B0
M_SCKE_B1
M_SCKE_B2
M_SCKE_B3
13
M_MAA_B13
AP18 AN17 AR16 AR15 AN15 AP17
AP14 AN13 AN20 AR12 AM12
AR27 AN27 AP27
AM27 AR19 AP23
AP34 AN34 AN33 AM33
AN10
AP10
AN32 AP29 AP30 AP32
AH22 AG23
AE26 AE25
AK22
AD29 AD28
AD32
AK15 AN14
AE10
SBMA0 SBMA1 SBMA2 SBMA3 SBMA4
SBMA6
AL15
SBMA7 SBMA8 SBMA9 SBMA10 SBMA11 SBMA12
AL24
RSVRD
SBWE* SBCAS* SBRAS*
SBBA0 SBBA1 SBBA2
AM9
AR9
SBCK0 SBCK0*
AL11
SBCK1
AJ11
SBCK1* SBCK2 SBCK2*
AL23
SBCK3 SBCK3*
AK9
SBCK4
AL9
SBCK4* SBCK5 SBCK5*
AF9
AE8
AG8 AG4 AE5 AF5
28 7 6 5 4 3 1
INTEL
DOCUMENT NUMBER PAGE REV
CONFIDENTIAL
2 1
C77862
D
C
B
A
14
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
U6D1F
GDG_DDR1_1210
17 17 17
17
17
NOA_0
IN
NOA_1
IN
NOA_2
IN
TP_NOA_3 TP_NOA_4
NOA_5
IN
TP_NOA_6 TP_NOA_7
NOA_8
IN
TP_NOA_9
H16
NOA0
E15
NOA1
D17
NOA2
M16
NOA3
F15
NOA4
C15
NOA5
A16
NOA6
B15
NOA7
C14
NOA8
K15
NOA9
C
AN19
AH24
AD30
AK21 AK24
AK18
L10 M10
AL28 AJ14
AG6
P30 L19 L12 K12
H17 H15 H12 G12 F24 F12 E16 C16
AJ21
AL21 AL20
AJ24 AJ23 AJ18 AJ20
J12
DREFSSCLKINP DREFSSCLKINN
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD
12,16,17,38,39,41,79,87,88,102
V_1P5_CORE
IN
B
A
1.0
CRTHSYNC CRTVSYNC
CRTRED
CRTGREEN
CRTBLUE
CRTREDB
CRTGREENB
CRTBLUEB
CRTDDCDATA
CRTDDCCLK
DREFCLKINP DREFCLKINN
CRTIREF
PMEXTTS*
PMBMBUSY*
TESTIN*
RSTIN*
PWROK ICH_SYNC* MCHDETECT
RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD RSVRD
5 of 7
E12 D12
F14 D14 H14
G14 E14 J14
L14 M15
M13 M12
A15
AR35
NC
AR34
NC
AR2
NC
AR1
NC
AP35
NC
AP1
NC
B35
NC
B1
NC
A34
NC
A2
NC
K16 G16 R35 AF7 AG7 M14 A35
V31 V30 U30 V32 Y30 AB29 R31 R30 AA31 AA30
TPEV_EXTTS*
TP_BMBUSY
TESTIN*
PLTRST* PWRGD_3V ICH_SYNC*
TPEV_MCH_DET*
HSYNC VSYNC
VGA_RED
VGA_GREEN
VGA_BLUE
MCH_DDC_DATA MCH_DDC_CLK
CK_96M_DREF CK_96M_DREF*
DACREFSET
OUT
IN
BI
IN IN
OUT OUT
OUT OUT OUT
BI BI
IN IN
IN
18 18
18,20 18,20 18,20
18,74 18,74
30 30
18
101 37,55,56,70,72,73 40,72,74 40
R6C25
12
05%
EMPTY
402
DESIGN NOTE: STUFF FOR GD-P
EMPTY FOR GD-G
OUT
TPEV_EXTTS*
R6C31
5% 10K CH
12
402
V_1P5_CORE
V_2P5_MCH
12,16,17,38,39,41,79,87,88,102
IN
12,16,87,88
IN
IC
D
C
B
A
CORE PAGE
8 7
[PAGE_TITLE=MCH SECTIONS PAGE 6 OF 6]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
15
4.0
<XR_PAGE_TITLE>
R5D16
12
5%
6031CH
IN
V_1P5_CORE
D
12,15,17,38,39,41,79,87,88,102
L5D1
1 2
IND
1UH
721891-022
BOM NOTE:
OPTION: USE 721891-009 FOR 10UH INDUCTOR DEFAULT: USE 108506-002 FOR 0 OHM RESISTOR
I_VCCA_GPLL_R
1 2
MULTI
CH 805
108506-002
M5D3
202285-623
R5D17
6031CH
202285-623
12
5%
2
C5D10
10.0UF 20%
6.3V
1
X5R 1206
C5D8
1
470UF
20%
10V ALUM
2
RDL
VCCA_GPLL
2
1
VCCA_HPLL
2
1
C5D15
.1UF 10% 16V X7R 603
C5D21
.1UF 10% 16V X7R 603
12
OUT
12
OUT
C
M6D2
1 2
IND
10UH
721891-009
BOM Note: Default: For GD-G skus, stuff with 10uH Ind, use ipn 721891-009. Option: For GD-P skus, stuff with 0 ohm, use ipn 108506-002.
M5D2
ANALOG FILTERS
B
1 2
10UH
721891-009
IND
C6D10
1
220UF 20%
6.3V ALUM
2
RDL
C6D11
1
220UF 20%
6.3V ALUM
2
RDL
VCCA_DPLLA
2
C6D20
.1UF 10% 16V
1
X7R 603
2
C5D19
.1UF 10% 16V
1
X7R 603
BOM Note: Default: For GD-G skus, stuff all 4 caps on DPLLA and DPLLB. Option: For GD-P skus, Empty all 4 caps on DPLLA and DPLLB.
VCCA_DPLLB
12
OUT
12
OUT
28 7 6 5 4 3 1
D
C
B
BOM NOTE:
OPTION: USE 721891-009 FOR 10UH INDUCTOR DEFAULT: USE 108506-002 FOR 0 OHM RESISTOR
A
DEBUG ONLY
12,15,87,88
REPLACE 0 OHM WITH 1 OHM 1% ONLY IF NECESSARY FOR SIGNAL QUALITY
V_2P5_MCH
IN
R5D8
402 CH
V_2P5_DAC_FILTERED_PN1
12
5%0
1 2
IND
BOM NOTE:
DEFAULT: 721891-009 FOR10uH Inductor OPTION: USE 693286-026 FOR FERRITE BEAD
1 2
MULTI
CH
108506-002
M6D1
MULTI
805
721891-009
M5D1
805
C5D7
1
2
470UF 20% 10V ALUM RDL
2
C5D20
.1UF 10% 16V
1
X7R 603
VCCA_MPLL
12
OUT
A
V_2P5_DAC_FILTERED
2 C5D18
C6D5
1
100UF 20%
25V
ELEC
2
RDL
C6D16
.1UF 20% 25V
1
Y5V 603
2
.01UF
10%
50V
1
X7R 603
12,18
OUT
[PAGE_TITLE=MCH 2P5_DAC & 1P5 FILTER]
CORE PAGE
8 7
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
16
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
CAPS FOR SPECIFIC CORE MCH
V_1P5_CORE
12,15,16,38,39,41,79,87,88,102
IN
D
V_FSB_VTT
7..9,12,18,41,43,87
IN
C
2
C6E11
10UF 20%
6.3V
1
X5R 805
2
R5D23
301 1%
CH 402
1
2
R5D22
100 1%
CH 402
1
NOA H L DESCRIPTION
0 SEE BSEL TABLE BSEL0
B
1 SEE BSEL TABLE BSEL1 2 SEE BSEL TABLE BSEL2 3 NORM ALL-Z ALL-Z TEST MODE 4 NORM XOR XOR CHAIN 5 DDR1 DDR2 MEMORY TYPE 6 NORM REVERSE PCI-EXPRESS LANE REVERSAL 7 DIS ENABLE FSB HARDWARE STRAPS
8 NEW LTSSM OLD LTSSM LTSSM MODE (1.0 OLD, 1.0A NEW)
9 NORM BYPASS ICH PCI-EXPRESS RST BYPASS
3,4,5,6,7,8,9 ALL HAVE INTERNAL PULL-UP
BSEL TABLE
A
2 1 0 PSB FREQUENCY
0 0 0 267 MHZ (1067) 0 0 1 133 MHZ (533) 0 1 0 200 MHZ (800) 0 1 1 167 MHZ (667) 1 0 0 333 MHZ (RSVD) 1 0 1 100 MHZ (400) 1 1 0 400 MHZ (RSVD) 1 1 1 RESERVED
8 7
2
2
C6E15
C6E12
10UF
10UF
20%
20%
6.3V
6.3V
1
1
EMPTY
X5R
805
805
CAD NOTE: HD_SWING VOLTAGE "10MIL TRACE, 7MIL SPACE" PLACE DIVIDER RESISTORS NEAR VTT
HXSWING
2
C5D14
.01UF 10% 50V
1
X7R 603
PCI EXPRESS FILTER
12,15,16,38,39,41,79,87,88,102
IN
OUT
CORE PAGE
10
V_1P5_CORE
M6E1
1 2
MULTI
0OHM
SM
108506-007IND
C6E8
1
220UF 20%
6.3V ALUM
2
RDL
V_FSB_VTT
7..9,12,18,41,43,87
IN
C5D23
C5D17
10.0UF
10.0UF 20%
20%
6.3V
6.3V EMPTY
EMPTY
1 2
1 2
1206
1206
"X5R"
CAPS FOR FSB GENERIC
V_1P5_PCIEXPRESS
2
C6E9
4.7UF 20% 10V
1
Y5V 805
1 2
C5D13
10.0UF 20%
6.3V EMPTY 1206
12
OUT
2
C6E10
10.0UF 20%
6.3V
1
EMPTY 805
V_FSB_VTT
7..9,12,18,41,43,87
IN
V_1P5_PCIEXPRESS
12
IN
R5D19
1 2
402
R5D25
1 2
20 1%
402
R6E1
1 2
24.9 402
1%60.4 CH
2
1
HXSCOMP
C5D22
3.9PF .25PF 50V
EMPTY
603
HXRCOMP
CH
1% CH
GRCOMP
10
OUT
10
OUT
11
OUT
D
COMP SIGNAL TERMINATION
97 96
V_FSB_VTT
7..9,12,18,41,43,87
IN
VCCP
IN
1
R5D18
619 1% CH
+12V
402
2
R5D15
10K 5%
CH 402
6
VCCP_DRIVER
RSVD_DET
IN
Q5D2
SOT23 201924-001
FET
7,8,29
7,8,29
7,8,29
45
2
R5D21
100 1%
CH 402
1
2
R5D20
210
1% CH
402
1
H_FSBSEL0
IN
H_FSBSEL1
IN
H_FSBSEL2
IN
36
GTLREF VOLTAGE SHOULD BE 0.67*VTT = 0.8V
(FOR THIS DESIGN)
100 OHMS OVER 210 OHMS: 7/23/2003
C5D16
.1UF
20% 25V Y5V 603
1 2
10K 5%
402
1 2
402
1 2
402
R5D5
1 2
402
1 2
1K 5%
402
R4C8
R4C10
R4C9
EMPTY
R5D4
5%1K
EMPTY
2
1
"X7R"
CH
5%10K CH
5%CH10K
NOA_0
NOA_1
NOA_2
NOA_5
NOA_8
220PF
EMPTY
C5D12
10% 50V
603
2
1
CAD NOTE:
CAP FOR GTLREF INPUTS @GMCH USE 12MIL TRACE, ISOLATE W/ 15MIL SPACE CAP SHOULD BE PLACED NEAR MCH PIN
OUT
OUT
OUT
OUT
OUT
NOA SIGNAL TERMINATION
[PAGE_TITLE=MCH DECOUPLING AND COMP]
INTEL
CONFIDENTIAL
2 1
MCH_GTLREF
15
15
15
15
15
DOCUMENT NUMBER PAGE REV
C77862
10
OUT
17
C
B
A
4.0
<XR_PAGE_TITLE>
VCC
3
RP2J1C
2.7K 5%
V_FSB_VTT
7..9,12,17,41,43,87
C4C6
IN
15,74
2
2
C4C7
.1UF
.1UF
20%
20%
25V
25V
1
Y5V
603
1
C5F3
2.2UF 20% 16V
2
Y5V 805
1
Y5V
603
1
2
C4F1
2.2UF 20% 16V Y5V 805
C5D9
2
.1UF 20%
25V
1
Y5V
603
1
NOTE:
C4F2
LEAVE EMPTY,
2.2UF 20%
INTERFERES WITH
16V
WS HEAT SINK
2
EMPTY 805
12,16
IN
IN
BOM NOTE:
STUFF FOR GD-G EMPTY FOR GD-P
15,20 15,20 15,20
BOM NOTE:
STUFF FOR GD-P EMPTY FOR GD-G
V_2P5_DAC_FILTERED
IN IN IN
VGA_RED VGA_GREEN VGA_BLUE
D
FSB GENERIC DECOUPLING
V_SM
12,19,21,24,25,28,85,89
IN
C
1
2
C5F2
2.2UF 20% 16V Y5V 805
1
2
C5F1
2.2UF 20% 16V Y5V 805
1
C5F4
2.2UF 20% 16V
2
Y5V 805
.063W IC SM
6
5
RP2J1D
2.7K 5% .063W IC SM
4
R5C29
1
0 5%
R6C26
1
EMPTY
2
0
402
5% EMPTY
2
402
15,74
R6C28
1
0 5%
EMPTY
2
402
28 7 6 5 4 3 1
MCH_DDC_CLKMCH_DDC_DATA
IN
CR6C1
3
1 2
GP
SOT23S
EMPTY
3
1 2
CR6C2
GP
SOT23S
EMPTY
3
1 2
VCC
2
7
8
1
CR6C3
GP
SOT23S
EMPTY
RP2J1B
2.7K 5% .063W IC SM
RP2J1A
2.7K 5% .063W IC SM
D
C
MCH MEMORY DECOUPLING
2
C6C15
.1UF 20% 25V
1
Y5V
R6C24
1 2
R6C27
1 2
5% CH
C77862
603
VSYNC_3V
HSYNC_3V
B
20
OUT
20
OUT
A
18
4.0
BOM NOTE:
STUFF FOR GD-G EMPTY FOR GD-P
BOM NOTE:
STUFF WITH 255 OHM, 1% FOR GD-G STUFF WITH 0 OHM, 5% FOR GD-P
HSYNC_BUFFER
VCC3
U6C1
74LVC2G125
8
VCC
1
1OE*
2
1A
7
2OE*
5
2A
A80005-001
6
1Y
3
2Y
4
GND
IC
BOM NOTE:
STUFF FOR GD-G EMPTY FOR GD-P
[PAGE_TITLE=MCH DCPL & VGA TERMINATION]
INTEL
VSYNC_PN1_BUF
HSYNC_PN1_BUF
39CH5%
402
SLEW RATE
CONTROL FEATURE
39
402
DOCUMENT NUMBER PAGE REV
R6D5
VSYNC
15
IN
R6D2
1
10K 5%
EMPTY
2
402
15
HSYNC
IN
R6D1
1
10K 5%
EMPTY
2
12,15..17,38,39,41,79,87,88,102
V_1P5_CORE
IN
2
C6C21
22PF 10% 50V
1
EMPTY
VCC3
402
2
1
C6C6
.1UF 20% 25V Y5V 603
BOM NOTE:
STUFF FOR GD-P EMPTY FOR GD-G
402
DESIGN NOTE:
VSYNC_BUFFER
1 2
5%
39
CH
402
SLEW RATE CONTROL FEATURE
R6D4
1 2
39
5% CH
402
CAD NOTE:
PLACE BOTH RESISTORS CLOSE TO MCH
PER THE SPEC: ALL UNUSED INPUTS OF THE DEVICE MUST BE HELD AT VCC/VCC3 OR GND TO ENSURE PROPER DEVICE OPERATION. PER THE SPEC: DESIGNED FOR 1.65-V TO 5.5-V VCC OPERATION.
CORE PAGE
B
2
R5D24
255 1%
CH 402
1
VGA_RED
A
15,20
IN
VGA_GREEN
15,20
IN
VGA_BLUE
15,20
IN
CAD NOTE:
PLACE CLOSE TO MCH, WITHIN 750 MIL OF PIN
DACREFSET
CAD NOTE:
PLACE CLOSE TO MCH
M6D7
1 2
150 1%
M6D6
1 2
150 1%
M6D3
1 2
150 1%
MULTI
CH402
MULTI
CH402
MULTI
CH402
15
OUT
CONFIDENTIAL
8 7
45
36
2 1
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
R7F2
V_SM
12,18,21,24,25,28,85,89
IN
C
V_SM
12,18,21,24,25,28,85,89
IN
B
V_SM
12,18,21,24,25,28,85,89
IN
A
12
1KCH1%
402
R6F4
12
1%
1K
CH402
CAD NOTES:
PLACE CLOSE TO MCH
R6H2
12
1%1K
CH
402
R6H1
12
1%1K
CH
402
CAD NOTES:
PLACE CLOSE TO CH_B DIMMS
R6G2
12
1%
1K
CH
402
R6G1
12
1%1K
CH
402
CAD NOTES:
PLACE CLOSE TO CH_A DIMMS
R6F3
1 2
5%
4020CH
2
C6E13
.1UF 20% 25V
1
Y5V 603
2
C6E14
.1UF 20% 25V
1
Y5V 603
2
C6H7
.1UF 20%
CAD NOTES:
25V
PLACE 0.1UF CAP CLOSE TO RESISTOR DIVIDER
1
EMPTY
603
DIMM_VREF_A
2
C6G1
.1UF 20%
CAD NOTES:
25V
1
PLACE 0.1UF CAP CLOSE TO RESISTOR DIVIDER
EMPTY 603
MCH_VREF_B
CAD NOTES:
PLACE 0.1UF CAP CLOSE TO MCH
MCH_VREF_A
CAD NOTES:
PLACE 0.1UF CAP CLOSE TO MCH
DIMM_VREF_B
14
OUT
13
OUT
R6F1
12
12,18,21,24,25,28,85,89
25
OUT
V_SM
IN
2
C7F8
.1UF 20% 25V
1
Y5V 603
80.6 402
R6F2
21
OUT
1%
CH
12
1%80.6
CH402
SMRCOMP_N
DESIGN NOTE:
BUFFERS CALIBRATE TO 20/80% OF V_SM. INTERNAL BUFFERS SET TO 20 OHMS
SMRCOMP_P
14
OUT
14
OUT
D
C
B
A
CORE PAGE
8 7
[PAGE_TITLE=MCH CHIPSET TERMINATION]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
19
4.0
<XR_PAGE_TITLE>
BOM NOTE:
DEFAULT: STUFF WITH FERRITE BEAD (693286-006) FOR 5 POINT FILTER
VGA_RED
15,18
IN
VGA_GREEN
15,18
IN
VGA_BLUE
15,18
D
IN
693286-006
FB3A2
1 2
FB
"47 OHM"
HSYNC_3V
18
IN
VSYNC_3V
18
IN
2
C4A13
10PF 5% 50V
1
COG 402
C
B
2
R4A8
150 1%
CH 402
1
CAD NOTE:
PLACE RESISTORS CLOSE TO FILTERS (CAPS/FERITE-BEADS)
M3A3
1 2
MULTI
FB 603
VGA_BLUE_FB1
STUFF WITH 3.3PF (A36094-006) FOR 3 POINT FILTER STUFF WITH 10PF (A36094-001) FOR 5 POINT FILTER
2
C3A14
22PF 10% 50V
1
NPO 402
BOM NOTE:
BOM NOTE:
STUFF WITH 3.3PF (A36094-006) FOR 3 POINT FILTER STUFF WITH 22PF (A36095-006) FOR 5 POINT FILTER
2
C3A1
10PF 5% 50V
1
COG 402
A36094-001
"COG"
EMPTY FOR 3 POINT FILTER STUFF WITH 10PF (A36094-001) FOR 5 POINT FILTER
2
1
OPTION: STUFF 0 OHM 0603 FOR 3 POINT FILTER
693286-006
1 2
"47 OHM"
2
C4A12
10PF 5% 50V
1
COG 402
BOM NOTE:
R4A6
150 1%
CH 402
FB4A1
FB
1 2
FB 603
VGA_GREEN_FB1
2
1
MULTI
C4A9
22PF 10% 50V NPO 402
M3A2
693286-006
FB3A1
1 2
FB
"47 OHM"
2
C4A6
10PF 5% 50V
1
COG 402
2
C4A8
10PF 5% 50V
1
COG 402
"COG"
2
R4A1
150 1%
CH 402
1
1 2
FB 603
VGA_RED_FB1
2
C4A4
22PF 10% 50V
1
NPO 402
MULTI
M3A1
2
C4A2
10PF 5% 50V
1
COG 402
"COG"
28 7 6 5 4 3 1
VCC
RT3A1
12
VDO_THERM_PN1
THRMSTR
VDO_RED_L VDO_THERM_9 VDO_GREEN_L
VDO_BLUE_L
TP_VDOCONN_11_CORE TP_VDOCONN_4_CORE
2
C4A3
100PF
2
5%
C4A1
50V
1
EMPTY 402
100PF 5% 50V
1
EMPTY 402
M3A4
1 2
MULTI
805CH
J3A1
16
1 9 2 10 3 11 4 12 5 13 6 14 7 15 8
17
RCPT
2
C3A2
.1UF 20% 25V
1
Y5V 603
D
C
B
VCC
2
A
74
74
DDCSDA_5V
BI
DDCSCL_5V
BI
1
CORE PAGE
8 7
R4A3
2.2K 5%
CH 402
2
R4A5
2.2K 5%
CH 402
1
R4A4
1 2
100
R4A2
1 2
100 402
5% CH402
5% CH
VDO_MONID1_R
VDO_MONID2_R
123 456
I36
CR4A2
TVS6_2V
6.2V EMPTY
A
2
1
C4A7
100PF 5% 50V EMPTY 402
2
C4A5
100PF 5% 50V
1
EMPTY 402
[PAGE_TITLE=VGA CONNECTOR]
COMPONENTS ARE DFM29
45
INTEL
CONFIDENTIAL
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
20
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
C
B
A
13,22
BOM NOTE:
USE A87935-007 FOR BLACK CONN WITH WHITE TABS
USE A87935-008 FOR BLACK CONN WITH BLACK TABS
13,23
13,23 13,23
13,22
13,22 13,23
13,23 13 13
13,23 13,23
12,18,19,24,25,28,85,89
13,22
BOM NOTE:
USE A87935-006 FOR BLUE CONN WITH WHITE TABS
USE A87935-007 FOR BLACK CONN WITH WHITE TABS
13,23 13,23
13,23
13,22
13,22
13,23
13,23
13 13 13,23
13,23
CORE PAGE
8 7
M_DATA_A[63..0]
BI
M_WE_A*
IN
M_RAS_A*
IN
M_CAS_A*
IN
M_MAA_A[13..0]
BI
M_DQM_A[7..0]
BI
M_DQS_A[7..0]
BI
M_SCS_A*[3..0]
IN
CK_M_166M_P_DDR3_A
IN
CK_M_166M_N_DDR3_A
IN
M_SCKE_A[3..0]
IN
M_SBS_A[1..0]
IN
V_SM
IN
M_DATA_A[63..0]
BI
M_WE_A*
IN
M_RAS_A*
IN
M_CAS_A*
IN
M_MAA_A[13..0]
BI
M_DQM_A[7..0]
BI
M_DQS_A[7..0]
BI
M_SCS_A*[3..0]
IN
CK_M_166M_P_DDR0_A
IN
CK_M_166M_N_DDR0_A
IN
M_SCKE_A[3..0]
IN
M_SBS_A[1..0]
IN
J6G1
J6G2
179
DIMM2P_184_1Gb
636465
M_DATA_A62
M_DATA_A63
178
179
DQ62
DQ63
DIMM2P_184_1Gb
RAS*
WE*
636465
154
M_DATA_A61
M_DATA_A62
M_DATA_A63
63
6263616260
174
175
178
DQ61
DQ62
DQ63
CAS*
RAS*
WE*
154
DQ60
M_DATA_A61
61
175
DQ61
CAS*
M_DATA_A60
596058
88
DQ59
A13
167
13
M_DATA_A59
M_DATA_A60
59
58
87
88
174
DQ59
DQ60
DQ58
A13
167
M_MAA_A13
13
M_DATA_A57
M_DATA_A58
M_DATA_A59
57
84
87
DQ58
DQ57
A12A9A8A4A5A6A7
115
M_MAA_A12
M_MAA_A13
12
11
M_DATA_A55
M_DATA_A56
M_DATA_A57
M_DATA_A58
57
56
55
83
84
171
DQ55
DQ56
DQ57
A10
A11
A12A9A8A4A5A6A7
115
118
141
M_MAA_A10
M_MAA_A11
M_MAA_A12
12
11
10
M_DATA_A54
M_DATA_A55
M_DATA_A56
56
55
54
49
83
166
170
171
DQ54
DQ55
DQ56
DQ53
A10
A11
272829
118
122
141
M_MAA_A10
M_MAA_A11
M_MAA_A9
9
8
10
M_DATA_A54
54
166
170
DQ54
272829
122
M_MAA_A9
9
8
M_DATA_A48
M_DATA_A49
48
165
DQ52
M_MAA_A7
M_MAA_A8
7
6
49
DQ53
M_DATA_A48
M_DATA_A49
48
51
80
165
DQ51
DQ52
125
M_MAA_A7
M_MAA_A8
7
6
M_DATA_A50
M_DATA_A51
51
50
79
80
DQ50
DQ51
32
125
M_MAA_A5
M_MAA_A6
5
4
M_DATA_A43
M_DATA_A50
M_DATA_A51
M_DATA_A52
M_DATA_A53
50
53
52
43
72
73
79
161
162
DQ49
DQ50
DQ48
DQ47
A3A0A1A2DM7
32
37
414243
130
M_MAA_A2
M_MAA_A3
M_MAA_A4
M_MAA_A5
M_MAA_A6
5
4
3
2
M_DATA_A42
M_DATA_A43
M_DATA_A52
M_DATA_A53
53
52
43
42
40
72
73
155
161
162
DQ45
DQ49
DQ48
DQ46
DQ47
A3A0A1A2DM7
37
414243
48
130
M_MAA_A1
M_MAA_A2
M_MAA_A3
M_MAA_A4
3
2
1
0
42
DQ46
M_DATA_A27
M_DATA_A32
M_DATA_A33
M_DATA_A34
M_DATA_A35
M_DATA_A36
M_DATA_A37
M_DATA_A38
DQ44
M_DATA_A39
M_DATA_A41
M_DATA_A44
M_DATA_A45
M_DATA_A46
M_DATA_A47
47
46
41
45
34
39
33
37
353238
32
36
27
5354555657
60
61
68
69
147
150
151
DQ43
DQ39
DQ40
DQ41
DQ42
DQ38
DQ37
131
133
146
DQ33
DQ34
DQ35
DQ36
DQ31
DQ32
M_DATA_A40
M_DATA_A42
404744
153
155
DQ45
31
DQ30
M_DATA_A29
M_DATA_A31
25
29
26
40
126
127
DQ28
DQ29
DQ27
M_DATA_A28
M_DATA_A30
30
24192823191723201718202218162221161521
31
333435
39
114
117
121
123
DQ23
DQ24
DQ25
DQ26
DQ20
DQ21
DQ22
DQ19
DQ18
23
24
DQ17
M_DATA_A16
M_DATA_A17
M_DATA_A18
M_DATA_A19
M_DATA_A20
M_DATA_A22
M_DATA_A23
M_DATA_A24
M_DATA_A25
M_DATA_A26
DDR CHANNEL A DIMM 1
DQS8
DM6
DM4
DM5
DM8/DQS17
48
140
149
159
169
177
M_DQM_A4
M_DQM_A5
M_DQM_A6
M_DQM_A7
7
6
5
4
M_MAA_A0
M_MAA_A1
1
0
TP_CHA_1_DM8
M_DATA_A34
44
DQ44
M_DATA_A39
M_DATA_A41
M_DATA_A44
M_DATA_A45
M_DATA_A46
M_DATA_A47
46
41
45
34
39
33
61
68
69
147
150
151
DQ43
DQ39
DQ40
DQ41
DQ42
DQ38
DQ37
M_DATA_A40
153
DQS7
DM0
DM1
DM2
DM3
47
86
97
107
119
129
M_DQM_A0
M_DQM_A1
M_DQM_A2
M_DQM_A3
3
M_DATA_A33
M_DQS_A7
2
1
0
7
TP_CHA_1_DQS8
M_DATA_A27
M_DATA_A32
M_DATA_A35
M_DATA_A36
M_DATA_A37
M_DATA_A38
37
35
38
36
27
31
5354555657
60
131
133
146
DQ33
DQ34
DQ35
DQ36
DQ30
DQ31
DQ32
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
67
78
M_DQS_A5
M_DQS_A6
6
5
M_DATA_A25
M_DATA_A31
25
29
126
127
DQ28
DQ29
CB7
CB1
CB2
CB3
CB4
CB5
CB6
14
25
36
144
M_DQS_A0
M_DQS_A1
M_DQS_A2
M_DQS_A3
M_DQS_A4
4
3
2
1
0
TP_CHA_1_CB7
M_DATA_A19
M_DATA_A23
M_DATA_A24
M_DATA_A26
M_DATA_A28
M_DATA_A29
M_DATA_A30
26
30
24
28
333435
39
40
117
121
123
DQ23
DQ24
DQ25
DQ26
DQ27
DQ21
DQ22
142
TP_CHA_1_CB6
M_DATA_A17
114
DQ20
44
45
495051
134
135
TP_CHA_1_CB1
TP_CHA_1_CB2
TP_CHA_1_CB3
TP_CHA_1_CB4
TP_CHA_1_CB5
M_DATA_A15
M_DATA_A16
M_DATA_A18
M_DATA_A20
M_DATA_A21
M_DATA_A22
23
24
31
110
DQ15
DQ18
DQ19
DQ16
DQ17
DDR CHANNEL A DIMM 0
DQS8
M_MAA_A0
TP_CHA_0_DM8
DM6
DM4
DM5
DM8/DQS17
140
149
159
169
177
M_DQM_A4
M_DQM_A5
M_DQM_A6
M_DQM_A7
7
6
5
4
M_DQM_A[7..0]
DQS7
DM0
DM1
DM2
DM3
47
86
97
107
119
129
3
M_DQS_A7
M_DQM_A0
M_DQM_A1
M_DQM_A2
M_DQM_A3
7
2
1
0
TP_CHA_0_DQS8
M_DQS_A[7..0]
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
67
78
M_DQS_A5
M_DQS_A6
6
5
CB7
14
25
36
144
M_DQS_A0
M_DQS_A1
M_DQS_A2
M_DQS_A3
M_DQS_A4
4
3
2
1
0
TP_CHA_0_CB0
CB0
CB1
CB2
CB3
CB4
CB5
CB6
44
45
495051
134
135
142
TP_CHA_0_CB1
TP_CHA_0_CB2
TP_CHA_0_CB3
TP_CHA_0_CB4
TP_CHA_0_CB5
TP_CHA_0_CB6
TP_CHA_0_CB7
DQ16
CB0
TP_CHA_1_CB0
CK_M_166M_P_DDR4_A CK_M_166M_N_DDR4_A
TP_DIMM1_SCS2*
CK_M_166M_N_DDR5_A
16
17
CK1
CK1*
CK_M_166M_P_DDR5_A
TP_DIMM1_SCS3*
71
75
76
163
CK2
CS2*
CS3*
CK2*
CONN
M_DATA_A6
64534
95
M_DATA_A0
M_DATA_A1
M_DATA_A3
M_DATA_A4
M_DATA_A5
M_DATA_A7
3
7
1
0
2345678
94
DQ3
DQ4
DQ5
DQ2
DQ1
DQ0
18
26
58
66
74
81
89
93
100
116
124
132
139
145
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
9
101
152
160
VSS
VSS
102
NCNCNC
173
NC
176
VSS
M_DATA_A10
M_DATA_A11
M_DATA_A12
M_DATA_A13
M_DATA_A14
M_DATA_A15
M_DATA_A21
15
14
106
109
110
DQ14
DQ15
M_DATA_A9
911131011810
20
105
DQ13
DQ12
DQ11
M_DATA_A2
M_DATA_A8
12
12
13
19
98
99
DQ8
DQ9
DQ7
DQ6
DQ10
13
IN
13
IN
13
IN
13
IN
D
I2C = 001
CS1*
CK0P
CKE0
CKE1
BA2
BA1
CSO*
CK0N
21
137
138
157
158
M_SCKE_A2
M_SCS_A*2
M_SCS_A*3
2
3
2
BA0
52
59
111
113
M_SBS_A0
M_SBS_A1
M_SCKE_A3
3
1
0
TP_BA2_113_DIMM1_A
M_DATA_A10
M_DATA_A11
M_DATA_A12
M_DATA_A13
M_DATA_A14
14
106
109
DQ14
9
DQ13
M_DATA_A2
M_DATA_A8
M_DATA_A9
13
1282
12
13
19
20
98
99
105
DQ8
DQ9
DQ7
DQ12
DQ10
DQ11
M_DATA_A0
M_DATA_A1
M_DATA_A3
M_DATA_A4
M_DATA_A5
M_DATA_A6
M_DATA_A7
625
7
1
0
2345678
94
95
DQ3
DQ4
DQ5
DQ6
DQ2
DQ1
DQ0
SA2
182
183
SA1
SA0
181
VSS
909192
VSS
RESET*
SDA
FETEN/NC
WP/NC
SCL
10 11
103
2
1
TP_FETEN_103_DIMM1_A
TP_WP_90_DIMM1_A
TP_RESET_10_DIMM1_A
SMB_CLK_MAIN
18
26
58
VSS
VSS
VSS
VSS
VSS
VSS
VREF
VDDSPD
VDDID
1
82
184
V_SM
C6G3
.1UF 20% 25V Y5V 603
NEAR DIMM PIN
66
74
81
VSS
VSS
89
VSS
VDD
VDD
38
93
100
VSS
VSS
VDD
VDD
VDD
VDD
46
70
85
108
TP_VDDID_82_DIMM1_A
116
124
132
139
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
15
120
148
168
145
152
160
176
VSS
VSS
VSS
VSS
VSS
VDDQ
22
30
62
77
96
104
9
101
102
173
NCNCNC
NC
VDDQ
VDDQ
VDDQ
112
128
16
CK1
VDDQ
VDDQ
VDDQ
VDDQ
136
143
156
164
SMB_CLK_MAIN SMB_DATA_MAIN
CK_M_166M_P_DDR1_A CK_M_166M_N_DDR1_A
CK_M_166M_N_DDR2_A CK_M_166M_P_DDR2_A
17
71
75
76
163
CK2
CS2*
CS3*
CK2*
CK1*
VDDQ
VDDQ
172
180
V_SM
V_SM
DIMM_VREF_A
TP_DIMM0_SCS2*
TP_DIMM0_SCS3*
CONN
IN
IN
IN
IN
IN
IN IN
IN IN
12,18,19,24,25,28,85,89
12,18,19,24,25,28,85,89
19
25,29,74
25,29,74
13 13
13 13
C
B
I2C = 000
CS1*
CK0P
CKE0
CKE1
BA2
BA1
CSO*
CK0N
21
137
138
157
158
M_SCKE_A0
M_SCS_A*0M_SCS_A*1
0
0
1
BA0
52
59
111
113
M_SBS_A0
M_SBS_A1
M_SCKE_A1
1
0
1
TP_BA2_113_DIMM0_A
SA1
SA2
182
183
SA0
WP/NC
10 11
909192
181
TP_WP_90_DIMM0_A
RESET*
SDA
VREF
FETEN/NC
SCL
VDDSPD
1
82
103
184
DIMM_VREF_A
2
C6G2
.1UF 20% 25V
TP_FETEN_103_DIMM0_A
TP_RESET_10_DIMM0_A
1
Y5V 603
VDD
VDDID
VDD
38
46
V_SM
TP_VDDID_82_DIMM0_A
NEAR DIMM PIN
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
70
15
85
108
120
148
168
VDDQ
22
30
62
77
96
104
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
112
128
136
143
156
164
172
180
V_SM
V_SM
DIMM_VREF_A
SMB_CLK_MAIN SMB_DATA_MAIN
12,18,19,24,25,28,85,89
IN
12,18,19,24,25,28,85,89
IN
19
IN
IN
IN
A
25,29,74
25,29,74
[PAGE_TITLE=DDR1 DIMM-A 0/1]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
21
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
SPARE SECTIONS
CAD NOTE: FLOOD VTT THROUGH PIN 5
DESIGN NOTE;
C
KEEP 603 RESISTORS DO NOT CHANGE TO 402
B
A
13,21
BI
13,21
BI
13,21
BI
CORE PAGE
RP3G3D
4 5
SM
.063WIC5%56
M_DQM_A[7..0]
M_DATA_A[63..0]
M_MAA_A[13..0]
8 7
DDR RESISTOR TERMINATION
RP1G1C
3 6
63
M_DATA_A63
56
5% .063W
SM IC
RP1G1D
4 5
62
M_DATA_A62
61
M_DATA_A61
60
M_DATA_A60
59
M_DATA_A59
58
M_DATA_A58
57
M_DATA_A57
56
M_DATA_A56
RP6G2D
4 5
0
M_DQM_A0
56
5% .063W
SM IC
RP5G1A
1 8
1
M_DQM_A1
56
5% .063W
SM IC
RP5G5C
3 6
2
M_DQM_A2
3
M_DQM_A3
4
M_DQM_A4
5
M_DQM_A5
6
M_DQM_A6
7
M_DQM_A7
SM56IC
RP4G3A
1 8
SM56IC
RP3G2B
2 7
56
SM IC
56
603
RP2G4D
4 5
SM56IC
RP2G6B
2 7
56
SM5%IC
5% .063W
5% .063W
5% .063W
R2G1
5% CH
5% .063W
.063W
12
55
M_DATA_A55
54
M_DATA_A54
53
M_DATA_A53
52
M_DATA_A52
51
M_DATA_A51
50
M_DATA_A50
49
M_DATA_A49
48
M_DATA_A48
5% .063W
SM56IC
RP2G5A
1 8
56 5%IC.063W
SM
RP2G5B
2 7
5% .063W
SM56IC
RP1G1A
1 8
56
5% .063W
SM IC
RP1G1B
2 7
56
5% .063W
SM IC
RP2G6C
3 6
56 5%IC.063W
SM
RP2G6D
4 5
56 5%IC.063W
SM
RP2G4A
1 8
56SM5%IC.063W
RP2G4B
2 7
56SM5%IC.063W
RP2G3C
3 6
56SM5%IC.063W
RP2G3D
4 5
56 5%IC.063W
SM
RP2G5C
3 6
56
5% .063W
SM IC
RP2G5D
4 5
56SM5%IC.063W
RP2G3A
1 8
56
5% .063W
SM IC
RP2G3B
2 7
56 5%IC.063W
SM
47
M_DATA_A47
46
M_DATA_A46
45
M_DATA_A45
44
M_DATA_A44
43
M_DATA_A43
42
M_DATA_A42
41
M_DATA_A41
40
M_DATA_A40
39
M_DATA_A39
38
M_DATA_A38
37
M_DATA_A37
36
M_DATA_A36
35
M_DATA_A35
34
M_DATA_A34
33
M_DATA_A33
32
M_DATA_A32
1 8
2 7
3 6
RP2G2C
3 6
56SM5%IC.063W
RP2G2D
4 5
5% .063W
SM56IC
R3G2
RP3G3A
56SM5%IC.063W
RP2G2A
1 8
56SM5%IC.063W
RP2G2B
2 7
56
5% .063W
SM IC
R3G4
56
603
R3G3
56
603
RP3G2A
1 8
56
5% .063W
SM IC
RP3G2D
4 5
56SM5%IC.063W
RP3G1B
2 7
56SM5%IC.063W
RP3G1C
3 6
56
5% .063W
SM IC
RP3G3B
56SM5%IC.063W
RP3G3C
56
5% .063W
SM IC
RP3G1D
4 5
56SM5%IC.063W
RP3G1A
1 8
56
5% .063W
SM IC
RP4G4B
2 7
31
M_DATA_A31
SM56IC
30
M_DATA_A30
SM56IC
12
5%56 CH603
29
M_DATA_A29
28
M_DATA_A28
27
M_DATA_A27
2 7
56 5% .063W
SM IC
56 5% .063W
SM
SM56IC
26
M_DATA_A26
56 5% .063W
SM
12
5% CH
12
5% CH
25
M_DATA_A25
24
M_DATA_A24
23
M_DATA_A23
22
M_DATA_A22
2 7
56 5% .063W
SM
56 5% .063W
SM
56 5% .063W
SM
SM56IC
21
M_DATA_A21
SM56IC
20
M_DATA_A20
56 5% .063W
SM
3 6
19
M_DATA_A19
SM56IC
4 5
18
M_DATA_A18
56 5% .063W
SM
17
M_DATA_A17
SM56IC
16
M_DATA_A16
SM56IC
RP4G4D
4 5
RP4G2A
1 8
RP4G2B
RP4G4A
1 8
RP4G4C
3 6
RP4G3B
2 7
RP4G3D
4 5
RP5G5A
1 8
RP5G5B
RP5G4C
3 6
RP5G4D
4 5
RP4G2C
RP4G2D
RP5G4A
1 8
RP5G4B
2 7
.063W5%
.063W5%
IC
.063W5%
IC
IC
IC
IC
.063W5%
.063W5%
IC
.063W5%
IC
.063W5%
.063W5%
15
M_DATA_A15
14
M_DATA_A14
13
M_DATA_A13
12
M_DATA_A12
11
M_DATA_A11
10
M_DATA_A10
9
M_DATA_A9
8
M_DATA_A8
7
M_DATA_A7
6
M_DATA_A6
5
M_DATA_A5
4
M_DATA_A4
3
M_DATA_A3
2
M_DATA_A2
1
M_DATA_A1
0
M_DATA_A0
3 6
4 5
1 8
2 7
1 8
2 7
3 6
4 5
RP5G2C
56SM5%IC.063W
RP5G2D
56 5%IC.063W
SM
RP6G3A
5% .063W
SM56IC
RP6G3B
56 5%IC.063W
SM
RP5G2A
56SM5%IC.063W
RP5G2B
56SM5%IC.063W
RP5G1C
56 5%IC.063W
SM
RP5G1D
56 5%IC.063W
SM
RP6G2A
1 8
56SM5%IC.063W
RP6G2B
2 7
56SM5%IC.063W
RP6G1C
3 6
56
5% .063W
SM IC
RP6G1D
4 5
56SM5%IC.063W
RP6G3C
3 6
56
5% .063W
SM IC
RP6G3D
4 5
56 5%IC.063W
SM
RP6G1A
1 8
56
5% .063W
SM IC
RP6G1B
2 7
56 5%IC.063W
SM
23,24,26..28,89
V_SM_VTT
IN
R2G3
13
M_MAA_A13
12
M_MAA_A12
11
M_MAA_A11
RP4G5A
10
M_MAA_A10
1 8
SM
9
M_MAA_A9
RP4G1C
8
M_MAA_A8
7
M_MAA_A7
3 6
47
SM
RP4G1D
4 5
SM
RP4G1A
6
M_MAA_A6
5
M_MAA_A5
4
M_MAA_A4
3
M_MAA_A3
2
M_MAA_A2
1
M_MAA_A1
0
M_MAA_A0
1 8
47
SM
RP4G1B
2 7
47
SM
RP4G5D
4 5
RP4G5C
3 6
47
SM
RP4G5B
2 7
47 5%
R5G1
47CH5%
603
R5G2
47 5%
.063WIC5%47
R5G3
47CH5%
603
.063W5%
IC
.063WIC5%47
.063W5%
IC
.063W5%
IC
R4G1
47 5%
603
R4G2
47CH5%
603
.063W5%47
ICSM
.063W5%
IC
.063W47 5%
ICSM
12
CH603
12
12
CH603
12
12
CH
12
D
C
B
A
[PAGE_TITLE=DDR1 DIMM-A 0/1 TERM]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
22
4.0
<XR_PAGE_TITLE>
CHANNEL A
DESIGN NOTE;
D
C
B
KEEP 603 RESISTORS DO NOT CHANGE TO 402
28 7 6 5 4 3 1
22,24,26..28,89
V_SM_VTT
IN
D
RP2G6A
7
M_DQS_A7
6
M_DQS_A6
5
M_DQS_A5
4
M_DQS_A4
3
M_DQS_A3
2
M_DQS_A2
1
M_DQS_A1
0
M_DQS_A0
IN
M_DQS_A[7..0]
13,21
1 8
56
SM
RP2G4C
3 6
SM
56CH5%
603
RP3G2C
3 6
56
SM
RP4G3C
3 6
56
SM
RP5G5D
4 5
SM
RP5G1B
2 7
56
SM
RP6G2C
3 6
SM5%IC
.063W5%
IC
.063WIC5%56
R2G2
.063W5%
IC
.063W5%
IC
.063WIC5%56
5%IC.063W
.063W56
R3G1
1
M_SBS_A1
12
M_SBS_A[1..0]
13,21
IN
0
M_SBS_A0
RP3G4D
4 5
SM IC
47 5%
.063W
5%47
12
CH603
C
M_SCS_A*[3..0]
13,21
IN
3
M_SCS_A*3
2
M_SCS_A*2
1
M_SCS_A*1
0
M_SCS_A*0
RP2G1A
1 8
56 .063W5%
RP2G1C
3 6
56 .063W5%
SM IC
RP2G1B
2 7
56 .063W5%
RP2G1D
4 5
56 .063W5%
ICSM
ICSM
B
ICSM
M_SCKE_A[3..0]
13,21
IN
RP3G4C
M_RAS_A*
13,21
IN
M_CAS_A*
13,21
IN
M_WE_A*
13,21
A
IN
3 6
SM IC
RP3G4A
1 8
SM
RP3G4B
2 7
47
SM
.063W
5%47
.063WIC5%47
.063W5%
IC
3
M_SCKE_A3
2
M_SCKE_A2
1
M_SCKE_A1
0
M_SCKE_A0
RP5G3C
3 6
56SM5%IC.063W
RP5G3B
2 7
56
5% .063W
SM IC
RP5G3D
4 5
56SM5%IC.063W
RP5G3A
1 8
56
5% .063W
SM IC
A
DDR RESISTOR TERMINATION
CORE PAGE
8 7
[PAGE_TITLE=DDR1 DIMM-A 0/1 TERM]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
23
4.0
<XR_PAGE_TITLE>
DDR CHANNEL A
28 7 6 5 4 3 1
D
D
DECOUPLING CAPACITORS FOR DDR TERMINATION RESISTORS
V_SM_VTT
22,23,26..28,89
IN
C
V_SM_VTT
22,23,26..28,89
IN
C2H3
4.7UF 20% 16V Y5V
1206
2
1
2
1
12
C5G5
.1UF 20% 25V Y5V 603
C2G7
.1UF 20% 25V Y5V 603
2
1
2
1
C6H10
4.7UF 20% 16V Y5V 1206
C6G7
.1UF 20% 25V Y5V 603
C5G8
.1UF 20% 25V Y5V 603
2
1
2
1
12
C6G8
.1UF 20% 25V Y5V 603
C4G8
.1UF 20% 25V Y5V 603
2
1
2
1
C4H1
12
20%4.7UF
16V Y5V 1206
PLACED AT LEFT AND RIGHT ENDS
OF VTT ISLAND
B
V_SM
IN
2
2
2
2
C4G6
C4H4
.1UF 20% 25V
1
1
Y5V 603
C6H8
.1UF
.1UF
20%
20%
25V
25V
1
Y5V
Y5V
603
603
A
2
C3G5
C4F3
.1UF
.1UF
20%
20%
25V
1
25V
1
Y5V
Y5V
603
603
C3G7
.1UF 20% 25V Y5V 603
C4G10
.1UF 20% 25V Y5V 603
2
1
2
1
1
C6G5
470UF 20% 10V ALUM
2
RDL
2
C6G4
.1UF 20% 25V
1
Y5V 603
C3G10
.1UF 20% 25V Y5V 603
C3G6
.1UF 20% 25V Y5V 603
2
1
2
1
12,18,19,21,25,28,85,89
IN
1
C1H3
4.7UF 20% 16V
2
Y5V 1206
C5G9
.1UF 20% 25V Y5V 603
C5G11
.1UF 20% 25V Y5V 603
V_SM
C4G1
22UF
1 2
ELEC
RDL
2
1
2
1
25V20%
C4G9
.1UF 20% 25V Y5V 603
C3G12
.1UF 20% 25V Y5V 603
2
1
2
1
12,18,19,21,25,28,85,89
2
C3G9
.1UF 20% 25V
1
Y5V 603
2
C5G6
.1UF 20% 25V
1
Y5V 603
V_SM
IN
C5G10
.1UF 20% 25V Y5V 603
C5G7
.1UF 20% 25V Y5V 603
.1UF
.1UF 20%
.1UF
.1UF
.1UF
2
1
2
1
C3G4
12
20% 25V Y5V 603
C2G3
12
25V Y5V 603
C3G2
12
20% 25V Y5V 603
C2G2
12
20% 25V Y5V 603
C4G4
12
20% 25V Y5V 603
C3G11
.1UF 20% 25V Y5V 603
C2G6
.1UF 20% 25V Y5V 603
2
1
2
1
C5G3
12
.1UF
20% 25V Y5V 603
C5G2
12
.1UF
20% 25V Y5V 603
C4G5
12
.1UF
20% 25V Y5V 603
C2G5
12
.1UF
20% 25V Y5V 603
C2G1
12
20%
.1UF
25V Y5V 603
C3G8
.1UF 20% 25V Y5V 603
C4G12
.1UF 20% 25V Y5V 603
2
1
2
1
C4G3
.1UF
20% 25V Y5V 603
C4G2
.1UF20%
25V Y5V 603
C5G1
.1UF
20% 25V Y5V 603
C3G1
.1UF
20% 25V Y5V 603
C2G4
.1UF
20% 25V Y5V 603
C2G9
.1UF 20% 25V Y5V 603
C6G6
.1UF 20% 25V Y5V 603
2
C2G8
.1UF 20% 25V
1
Y5V 603
DIMM
2
C4G11
.1UF 20% 25V
1
Y5V 603
C3G3
12
12
12
12
12
12
.1UF
20% 25V Y5V 603
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ16 DQ17 DQ18 DQ19 DQ20
DQ22 DQ23
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
CHANNEL A
DIMM TO MCH
BIT SWAPPING
MCH DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ13 DQ9 DQ10 DQ11 DQ12 DQ8 DQ14 DQ15
DQ21 DQ16 DQ22 DQ18 DQ20
DQ23 DQ19
DQ28 DQ24 DQ30 DQ26 DQ29 DQ25 DQ31 DQ27
DIMM
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQ48 DQ49 DQ50 DQ51 DQ52
DQ54 DQ55
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
MCH DQ36 DQ32 DQ38 DQ35 DQ37 DQ33 DQ39 DQ34
DQ45 DQ41 DQ46 DQ47 DQ44 DQ40 DQ42 DQ43
DQ52 DQ53 DQ50 DQ51 DQ48 DQ49DQ53DQ17DQ21 DQ54 DQ55
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
C
B
A
CORE PAGE
8 7
[PAGE_TITLE=DDR1 DIMM-A 0/1 TERM DCPL]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
24
4.0
<XR_PAGE_TITLE>
BI
M_DATA_B[63..0]
M_DATA_B27
M_DATA_B32
M_DATA_B33
M_DATA_B34
M_DATA_B35
M_DATA_B36
M_DATA_B37
M_DATA_B38
DQ44
M_DATA_B39
M_DATA_B41
M_DATA_B42
M_DATA_B44
M_DATA_B45
M_DATA_B46
42
46
41
44
34
39
32
37
353338
33
36
27
5354555657
60
61
68
69
147
150
151
DQ43
DQ39
DQ40
DQ41
DQ42
DQ38
DQ37
131
133
146
DQ33
DQ34
DQ35
DQ36
DQ31
DQ32
61
DQ56
M_DATA_B55
M_DATA_B61
50
54
49
53
51
55
48
52
43
47
404245
72
73
79
80
165
166
170
171
DQ54
DQ55
DQ53
DQ51
DQ52
DQ50
DQ49
DQ48
153
155
161
162
DQ45
DQ46
DQ47
M_DATA_B56
M_DATA_B57
M_DATA_B58
M_DATA_B59
M_DATA_B60
M_DATA_B62
M_DATA_B63
56
59
63
57
83
84
87
88
174
175
178
179
DQ59
DQ60
DQ61
DQ62
DQ63
DQ58
DQ57
M_DATA_B40
M_DATA_B43
M_DATA_B47
M_DATA_B48
M_DATA_B49
M_DATA_B50
M_DATA_B51
M_DATA_B52
M_DATA_B53
M_DATA_B54
31
DQ30
M_DATA_B29
M_DATA_B31
25
29
26
40
126
127
DQ28
DQ29
DQ27
M_DATA_B28
M_DATA_B30
30
24192823191723201718202218162221161521
31
333435
39
114
117
121
123
DQ23
DQ24
DQ25
DQ26
DQ20
DQ21
DQ22
DQ19
DQ18
M_DATA_B8
M_DATA_B9
15
14
10
13
12
9118
12
13
19
20
23
24
109
110
DQ14
DQ15
DQ16
DQ17
99
105
106
DQ8
DQ9
DQ13
DQ12
DQ10
DQ11
M_DATA_B19
M_DATA_B20
M_DATA_B21
M_DATA_B22
M_DATA_B23
M_DATA_B24
M_DATA_B25
M_DATA_B26
M_DATA_B1
M_DATA_B2
M_DATA_B3
M_DATA_B4
M_DATA_B5
M_DATA_B6
M_DATA_B7
74034
3
6
1
5
2345678
94
95
98
DQ3
DQ4
DQ7
DQ5
DQ6
DQ2
DQ1
DQ0
18
26
58
66
74
81
89
93
100
116
124
132
139
145
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
9
16
17
71
101
152
160
VSS
VSS
102
NCNCNC
173
NC
CK1
CK1*
176
VSS
M_DATA_B0
M_DATA_B10
M_DATA_B11
M_DATA_B12
M_DATA_B13
M_DATA_B14
M_DATA_B15
M_DATA_B16
M_DATA_B17
M_DATA_B18
14,26
D
DDR CHANNEL B DIMM 1
J6H2
DIMM2P_184_1Gb
CS1*
DQS8
CAS*
RAS*
WE*
636465
M_WE_B*
14,27
IN
M_RAS_B*
14,27
IN
M_CAS_B*
14,27
IN
BI
M_MAA_B[13..0]
14,26
154
A13
167
M_MAA_B13
13
A10
A11
A12A9A8A4A5A6A7
272829
115
118
141
M_MAA_B10
M_MAA_B11
M_MAA_B12
M_MAA_B9
12
11
10
9
122
8
M_MAA_B8
7
32
125
M_MAA_B6
M_MAA_B7
6
5
A3A0A1A2DM7
37
414243
130
M_MAA_B2
M_MAA_B3
M_MAA_B4
M_MAA_B5
4
3
2
1
DM6
DM4
DM5
DM8/DQS17
48
140
149
159
169
177
M_DQM_B4
M_DQM_B5
M_DQM_B6
M_DQM_B7
M_MAA_B0
M_MAA_B1
0
7
6
5
4
TP_CHB_1_DM8
DQS7
DM0
DM1
DM2
DM3
47
86
97
107
119
129
3
M_DQS_B7
M_DQM_B0
M_DQM_B1
M_DQM_B2
M_DQM_B3
7
2
1
0
TP_CHB_1_DQS8
C
BI BI
14,27
IN
14
IN
14
IN
14,27
IN
14,27
IN
12,18,19,21,24,28,85,89
IN
BI
M_DQM_B[7..0] M_DQS_B[7..0] M_SCS_B*[3..0] CK_M_166M_P_DDR3_B CK_M_166M_N_DDR3_B M_SCKE_B[3..0] M_SBS_B[1..0] V_SM
M_DATA_B[63..0]
M_DATA_B58
58
179
DQ63
M_DATA_B62
6258566260
178
DQ62
45
DQ44
M_DATA_B39
M_DATA_B41
M_DATA_B42
M_DATA_B44
M_DATA_B45
M_DATA_B46
46
41
44
34
39
32
37
35
38
36
27
31
5354555657
60
61
68
69
147
150
151
DQ43
DQ39
DQ40
DQ41
DQ42
DQ38
DQ37
131
133
146
DQ33
DQ34
DQ35
DQ36
DQ30
DQ31
DQ32
61
DQ56
M_DATA_B55
M_DATA_B61
50
54
49
53
51
55
48
52
43
47
40
72
73
79
80
165
166
170
171
DQ54
DQ55
DQ53
DQ51
DQ52
DQ50
DQ49
DQ48
153
155
161
162
DQ45
DQ46
DQ47
M_DATA_B56
M_DATA_B57
M_DATA_B59
M_DATA_B60
M_DATA_B63
596063
57
83
84
87
88
174
175
DQ59
DQ60
DQ61
DQ58
DQ57
M_DATA_B40
M_DATA_B43
M_DATA_B47
M_DATA_B48
M_DATA_B49
M_DATA_B50
M_DATA_B51
M_DATA_B52
M_DATA_B53
M_DATA_B54
M_DATA_B27
M_DATA_B32
M_DATA_B33
M_DATA_B34
M_DATA_B35
M_DATA_B36
M_DATA_B37
M_DATA_B38
14,26
14,27
14,26
B
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
67
78
M_DQS_B5
M_DQS_B6
6
5
M_DATA_B25
M_DATA_B31
25
29
126
127
DQ28
DQ29
CB7
CB2
CB3
CB4
CB5
CB6
14
25
36
M_DQS_B0
M_DQS_B1
M_DQS_B2
M_DQS_B3
M_DQS_B4
4
3
2
1
0
M_DATA_B24
M_DATA_B26
M_DATA_B28
M_DATA_B29
M_DATA_B30
26
30
24
28
333435
39
40
123
DQ24
DQ25
DQ26
DQ27
144
TP_CHB_1_CB7
M_DATA_B19
M_DATA_B23
117
121
DQ23
DQ21
DQ22
134
135
142
TP_CHB_1_CB3
TP_CHB_1_CB4
TP_CHB_1_CB5
TP_CHB_1_CB6
M_DATA_B17
M_DATA_B18
M_DATA_B20
M_DATA_B22
31
114
DQ18
DQ19
DQ20
495051
TP_CHB_1_CB2
M_DATA_B16
23
24
DQ16
DQ17
CSO*
CB0
CB1
44
45
157
M_SCS_B*2
2
TP_CHB_1_CB0
TP_CHB_1_CB1
M_DATA_B14
M_DATA_B15
M_DATA_B21
M_DATA_B9
14
9
105
106
109
110
DQ13
DQ14
DQ15
8
DQ12
CK0P
CKE0
CKE1
BA2
BA1
CK0N
21
137
138
158
M_SCKE_B2
M_SCS_B*3
3
2
BA0
52
59
111
113
M_SBS_B0
M_SBS_B1
M_SCKE_B3
3
1
0
TP_BA2_113_DIMM1_B
M_DATA_B0
M_DATA_B10
M_DATA_B11
M_DATA_B12
M_DATA_B13
M_DATA_B8
101113
12
12
13
19
20
99
DQ8
DQ9
DQ10
DQ11
M_DATA_B1
M_DATA_B2
M_DATA_B3
M_DATA_B4
M_DATA_B5
M_DATA_B6
M_DATA_B7
2
720
6
1
5
2345678
94
95
98
DQ3
DQ4
DQ7
DQ5
DQ6
DQ2
DQ1
DQ0
SA1
SA2
182
183
V_SM
RESET*
SA0
WP/NC
10 11
909192
181
TP_WP_90_DIMM1_B
TP_RESET_10_DIMM1_B
18
26
VSS
VSS
VSS
SDA
VREF
FETEN/NC
SCL
VDDSPD
1
82
103
184
V_SM
2
C6H9
.1UF 20% 25V
1
Y5V 603
TP_FETEN_103_DIMM1_B
SMB_CLK_MAIN
58
66
74
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDID
81
89
VSS
VSS
VDD
VDD
VDD
VDD
VDD
38
46
70
85
NEAR DIMM PIN
93
100
116
124
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
108
120
148
168
TP_VDDID_82_DIMM1_B
132
139
145
152
160
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
15
22
30
62
77
96
104
112
128
136
143
156
9
16
17
71
101
176
NCNCNC
VSS
VSS
75
102
173
NC
CK1
CS2*
CK2*
CK1*
DDR CHANNEL B DIMM 0
J6H1
DIMM2P_184_1Gb
CS1*
DQS8
CAS*
RAS*
WE*
636465
M_WE_B*
14,27
IN
M_RAS_B*
14,27
IN
M_CAS_B*
14,27
IN
14,26
A
14,26 14,27
M_MAA_B[13..0]
BI
M_DQM_B[7..0]
BI
M_DQS_B[7..0]
BI
14,27
14 14 14,27
14,27
12,18,19,21,24,28,85,89
M_SCS_B*[3..0]
IN
CK_M_166M_P_DDR0_B
IN
CK_M_166M_N_DDR0_B
IN
M_SCKE_B[3..0]
IN
M_SBS_B[1..0]
IN
V_SM
IN
154
A13
M_MAA_B13
167
13
A10
A11
A12A9A8A4A5A6A7
M_MAA_B10
M_MAA_B11
M_MAA_B12
115
118
141
9
12
11
10
272829
M_MAA_B9
122
8
M_MAA_B8
7
32
M_MAA_B5
M_MAA_B6
M_MAA_B7
125
6
5
4
A3A0A1A2DM7
37
414243
48
M_MAA_B0
M_MAA_B1
M_MAA_B2
M_MAA_B3
M_MAA_B4
130
3
2
1
0
DM6
DM8/DQS17
140
169
177
M_DQM_B6
M_DQM_B7
7
6
TP_CHB_0_DM8
M_DQM_B[7..0]
DM4
DM5
129
149
159
M_DQM_B4
M_DQM_B5
5
4
3
DQS7
DM0
DM1
DM2
DM3
47
86
97
M_DQS_B7
107
119
M_DQM_B0
M_DQM_B1
M_DQM_B2
M_DQM_B3
7
2
1
0
TP_CHB_0_DQS8
M_DQS_B[7..0]
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
67
78
M_DQS_B5
M_DQS_B6
6
5
CB7
CB2
CB3
CB4
CB5
CB6
14
25
36
M_DQS_B0
M_DQS_B1
M_DQS_B2
M_DQS_B3
M_DQS_B4
4
3
2
1
0
134
135
142
144
TP_CHB_0_CB5
TP_CHB_0_CB6
TP_CHB_0_CB7
45
495051
TP_CHB_0_CB2
TP_CHB_0_CB3
TP_CHB_0_CB4
CSO*
CB0
CB1
44
157
M_SCS_B*0M_SCS_B*1
0
TP_CHB_0_CB0
TP_CHB_0_CB1
CK0P
CKE0
CKE1
BA2
BA1
CK0N
21
M_SCKE_B0
137
138
158
0
1
BA0
52
59
M_SBS_B0
M_SBS_B1
111
113
M_SCKE_B1
1
0
1
TP_BA2_113_DIMM0_B
CORE PAGE
8 7
SA1
SA2
182
183
SA0
WP/NC
10 11
909192
181
TP_WP_90_DIMM0_B
45
RESET*
SDA
VREF
FETEN/NC
SCL
VDDSPD
1
103
184
DIMM_VREF_B
2
C6H2
.1UF 20% 25V
1
Y5V
TP_FETEN_193_DIMM0_B
TP_RESET_10_DIMM0_B
603
VDD
VDD
VDD
VDDID
VDD
38
46
70
82
TP_VDDID_82_DIMM0_B
NEAR DIMM PIN
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
85
108
120
148
168
VDDQ
15
22
30
62
77
96
104
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
112
128
136
143
156
164
36
28 7 6 5 4 3 1
CK_M_166M_P_DDR4_B CK_M_166M_N_DDR4_B
TP_DIMM1_SCS_B2*
CK_M_166M_N_DDR5_B CK_M_166M_P_DDR5_B
TP_DIMM1_SCS_B3*
75
76
163
CK2
CS2*
CS3*
VDDQ
CK2*
VDDQ
VDDQ
164
172
180
CONN
VDDQ
BOM NOTE:
USE A87935-007 FOR BLACK CONN WITH WHITE TABS
USE A87935-008 FOR BLACK CONN WITH BLACK TABS
V_SM
V_SM
DIMM_VREF_B
SMB_CLK_MAIN SMB_DATA_MAIN
CK_M_166M_P_DDR1_B CK_M_166M_N_DDR1_B
TP_DIMM0_SCS_B2*
CK_M_166M_N_DDR2_B CK_M_166M_P_DDR2_B
TP_DIMM0_SCS_B3*
76
163
CK2
CS3*
VDDQ
VDDQ
172
180
CONN
BOM NOTE:
USE A87935-006 FOR BLUE CONN WITH WHITE TABS
USE A87935-007 FOR BLACK CONN WITH WHITE TABS
V_SM
V_SM
DIMM_VREF_B
SMB_CLK_MAIN SMB_DATA_MAIN
[PAGE_TITLE=DDR1 DIMM-B 0/1]
INTEL
CONFIDENTIAL
2 1
14
IN
14
IN
14
IN
14
IN
DESIGN NOTE:
I2C = 011
12,18,19,21,24,28,85,89
IN
12,18,19,21,24,28,85,89
IN
19
IN
21,29,74
IN
21,29,74
IN
14
IN
14
IN
14
IN
14
IN
DESIGN NOTE:
I2C = 010
12,18,19,21,24,28,85,89
IN
12,18,19,21,24,28,85,89
IN
19
IN
21,29,74
IN
21,29,74
IN
DOCUMENT NUMBER PAGE REV
C77862
25
D
C
B
A
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
CHANNEL B
D
DESIGN NOTE;
KEEP 603 RESISTORS DO NOT CHANGE TO 402
C
B
A
14,25
BI
14,25
BI
14,25
BI
M_DQM_B[7..0]
M_DATA_B[63..0]
M_MAA_B[13..0]
CORE PAGE
8 7
3 6
0
M_DQM_B0
SM IC
1 8
1
M_DQM_B1
SM IC
2
M_DQM_B2
3
M_DQM_B3
3 6
4
M_DQM_B4
SM
5
M_DQM_B5
6
M_DQM_B6
2 7
7
M_DQM_B7
56
RP6H2C
RP5H1A
RP5H5C
3 6
SM
RP4H3A
1 8
SM
RP3H2C
56
603
RP2H3D
4 5
SM IC
RP2H5B
5% .063W56
.063W
5%56
.063WIC5%56
.063WIC5%56
.063WIC5%56
R2H1
.063W5%56
5% .063W
ICSM
DDR RESISTOR TERMINATION
RP1H1C
3 6
63
M_DATA_B63
62
M_DATA_B62
61
M_DATA_B61
60
M_DATA_B60
59
M_DATA_B59
58
M_DATA_B58
57
M_DATA_B57
56
M_DATA_B56
55
M_DATA_B55
54
M_DATA_B54
3 6
53
M_DATA_B53
4 5
52
M_DATA_B52
51
M_DATA_B51
12
5% CH
50
M_DATA_B50
1 8
49
M_DATA_B49
2 7
48
M_DATA_B48
SM IC
RP1H1D
4 5
56
SM
RP2H4A
1 8
56
RP2H4B
2 7
56
SM
RP1H1A
1 8
56
SM
RP1H1B
2 7
56
SM
RP2H5C
3 6
56
SM
RP2H5D
4 5
56
RP2H3A
1 8
56
SM
RP2H3B
2 7
56
SM
RP2H2C
56
SM
RP2H2D
56
SM
RP2H4C
3 6
SM IC
RP2H4D
4 5
56
SM
RP2H2A
SM IC
RP2H2B
56
SM
.063W5%56
.063W5%
IC
5% .063W
ICSM
.063W5%
IC
.063W5%
IC
5% .063W
IC
5% .063W
IC
5% .063W
ICSM
5% .063W
IC
5% .063W
IC
5% .063W
IC
5% .063W
IC
.063W5%56
5% .063W
IC
.063W5%56
5% .063W
IC
3 6
47
M_DATA_B47
56
4 5
46
M_DATA_B46
45
M_DATA_B45
1 8
44
M_DATA_B44
1 8
43
M_DATA_B43
56
2 7
42
M_DATA_B42
41
M_DATA_B41
2 7
40
M_DATA_B40
1 8
39
M_DATA_B39
2 7
38
M_DATA_B38
56
3 6
37
M_DATA_B37
56
4 5
36
M_DATA_B36
35
M_DATA_B35
56
4 5
34
M_DATA_B34
1 8
33
M_DATA_B33
56
2 7
32
M_DATA_B32
RP2H1C
SM
RP2H1D
SM IC
56
603
RP3H3A
SM IC
RP2H1A
SM
RP2H1B
SM IC
603
RP3H3B
SM IC
RP3H2A
SM IC
RP3H2B
SM
RP3H1C
SM
RP3H1D
SM IC
RP3H3C
3 6
SM
RP3H3D
SM IC
RP3H1A
SM
RP3H1B
SM IC
5% .063W
IC
.063W5%56
R3H2
.063W5%56
5% .063W
IC
.063W5%56
R3H3
.063W5%56
.063W5%56
5% .063W
IC
5% .063W
IC
.063W5%56
5% .063W
IC
.063W5%56
5% .063W
IC
.063W5%56
RP4H4B
2 7
31
M_DATA_B31
30
M_DATA_B30
12
5% CH
12
5%56 CH
1 8
29
M_DATA_B29
2 7
28
M_DATA_B28
1 8
27
M_DATA_B27
26
M_DATA_B26
25
M_DATA_B25
24
M_DATA_B24
1 8
23
M_DATA_B23
2 7
22
M_DATA_B22
3 6
21
M_DATA_B21
20
M_DATA_B20
4 5
19
M_DATA_B19
18
M_DATA_B18
1 8
17
M_DATA_B17
2 7
16
M_DATA_B16
SM IC
RP4H4C
3 6
SM IC
RP4H2A
5% .063W
56
SM
IC
RP4H2B
5% .063W
56
SM
IC
RP4H4A
SM IC
RP4H4D
4 5
5% .063W
56
SM
IC
RP4H3C
3 6
5% .063W
56
ICSM
RP4H3D
4 5
5% .063W
56
SM
IC
RP5H5A
5% .063W
56
SM
IC
RP5H5B
SM IC
RP5H4C
SM IC
RP5H4D
4 5
5% .063W
56
ICSM
RP4H2D
SM IC
RP4H2C
3 6
SM IC
RP5H4A
SM IC
RP5H4B
SM IC
.063W5%56
.063W5%56
.063W5%56
.063W5%56
.063W5%56
.063W5%56
.063W5%56
.063W5%56
.063W5%56
3 6
15
M_DATA_B15
SM
4 5
14
M_DATA_B14
56
SM
1 8
13
M_DATA_B13
SM
2 7
12
M_DATA_B12
56
SM
1 8
11
M_DATA_B11
56
SM
2 7
10
M_DATA_B10
2 7
9
M_DATA_B9
SM
4 5
8
M_DATA_B8
SM
1 8
7
M_DATA_B7
56
SM
2 7
6
M_DATA_B6
56
3 6
5
M_DATA_B5
56
SM
4 5
4
M_DATA_B4
56
SM
3 6
3
M_DATA_B3
56
SM
4 5
2
M_DATA_B2
56
1 8
1
M_DATA_B1
56
SM
2 7
0
M_DATA_B0
56
SM
RP5H2C
RP5H2D
RP6H3A
RP6H3B
RP5H2A
RP5H2B
RP5H1B
RP5H1D
RP6H2A
RP6H2B
RP6H1C
RP6H1D
RP6H3C
RP6H3D
RP6H1A
RP6H1B
.063WIC5%56
.063W5%
IC
.063WIC5%56
.063W5%
IC
.063W5%
IC
.063W5%56
ICSM
.063WIC5%56
.063WIC5%56
.063WIC5%
.063W5%
ICSM
.063WIC5%
.063W5%
IC
.063WIC5%
.063W5%
ICSM
.063WIC5%
.063W5%
IC
22..24,27,28,89
V_SM_VTT
IN
R2H2
13
M_MAA_B13
12
M_MAA_B12
11
M_MAA_B11
RP4H5A
10
M_MAA_B10
9
M_MAA_B9
8
M_MAA_B8
7
M_MAA_B7
6
M_MAA_B6
5
M_MAA_B5
4
M_MAA_B4
3
M_MAA_B3
2
M_MAA_B2
1
M_MAA_B1
0
M_MAA_B0
1 8
47 SM
RP4H1C
3 6
47 5% .063W
RP4H1D
4 5
47 SM
RP4H1A
1 8
47 5% .063W
RP4H1B
2 7
47 5% .063W
RP4H5D
4 5
47 5% .063W
RP4H5C
3 6
47 SM
RP4H5B
2 7
47 SM IC
47CH5%
603
R5H1
47 5%
R5H2
47CH5%
603
.063W5%
IC
R5H3
47 5%
ICSM
.063W5%
IC
ICSM
ICSM
R4H1
60347CH
R4H2
47CH5%
603
ICSM
.063W5%
IC
.063W5%
12
12
CH603
12
12
CH603
12
5%
12
D
C
B
A
[PAGE_TITLE=DDR1 DIMM-B 0/1 TERM]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
26
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
CHANNEL B
DESIGN NOTE;
KEEP 603 RESISTORS
D
DO NOT CHANGE TO 402
C
B
A
14,25
22..24,26,28,89
V_SM_VTT
IN
D
RP2H5A
7
M_DQS_B7
6
M_DQS_B6
5
M_DQS_B5
4
M_DQS_B4
3
M_DQS_B3
2
M_DQS_B2
1
M_DQS_B1
0
M_DQS_B[7..0]
IN
M_RAS_B*
14,25
IN
M_CAS_B*
14,25
IN
M_WE_B*
14,25
IN
M_DQS_B0
1 8
56
SM
3 6
56
SM
RP2H3C
.063W5%
IC
.063WIC5%
R3H4
603
RP3H2D
4 5
56 .063WSM5%
IC
RP4H3B
2 7
56
SM
4 5
56
SM
3 6
56
SM5%IC
4 5
56
SM5%IC
3 6
47 .063W
SM IC
1 8
47
SM
2 7
47
SM
RP5H5D
RP5H1C
RP6H2D
RP3H4C
RP3H4A
RP3H4B
.063W5%
IC
.063WIC5%
.063W
.063W
5%
.063WIC5%
.063W5%
IC
R3H1
1
M_SBS_B1
12
5%56 CH
M_SBS_B[1..0]
14,25
IN
0
M_SBS_B0
RP3H4D
4 5
47 .063W
SM IC
47 5%
5%
12
CH603
C
M_SCS_B*[3..0]
14,25
IN
IN
M_SCKE_B[3..0]
14,25
3
M_SCS_B*3
2
M_SCS_B*2
1
M_SCS_B*1
0
M_SCS_B*0
3
M_SCKE_B3
2
M_SCKE_B2
1
M_SCKE_B1
0
M_SCKE_B0
RP3H5C
3 6
56
SM
RP3H5D
4 5
56 .063W5%
SM
RP3H5A
1 8
56
SM
RP3H5B
2 7
56 .063W5%
SM
RP5H3D
4 5
56 5%IC.063W
SM
RP5H3B
2 7
56
SM IC
RP5H3C
3 6
56 5%IC.063W
SM
RP5H3A
1 8
56
SM
IC
IC
IC
IC
5% .063W
5% .063W IC
.063W5%
.063W5%
B
A
CORE PAGE
8 7
DDR RESISTOR TERMINATION
[PAGE_TITLE=DDR1 DIMM-B 0/1 TERM]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
27
4.0
<XR_PAGE_TITLE>
DDR CHANNEL B
28 7 6 5 4 3 1
D
22..24,26,27,89
C
12,18,19,21,24,25,85,89
IN
B
22..24,26,27,89
IN
A
IN
V_SM
V_SM_VTT
V_SM_VTT
2
C4H6
.1UF 20% 25V
1
Y5V 603
2
C5H6
.1UF 20% 25V
1
Y5V 603
V_SM_VTT
22..24,26,27,89
IN
4.7UF
C1H5
16V Y5V
1206
PLACED AT LEFT AND RIGHT ENDS OF VTT ISLAND
1
C1H7
470UF 20% 10V ALUM
2
RDL
1
C1G12
470UF 20% 10V ALUM
2
RDL
2
C2F12
22UF 20%
6.3V X5R 1206
C4J4
.1UF 20% 25V
1
Y5V 603
2
1
2
1
2
1
12
20%
2
1
C4H10
.1UF 20% 25V Y5V 603
C5H5
.1UF 20% 25V Y5V 603
C2H7
.1UF 20% 25V Y5V 603
2
1
2
1
C3J1
20%4.7UF
16V Y5V 1206
2
C5G4
.1UF 20% 25V
1
Y5V 603
2
C3H6
.1UF 20% 25V
1
Y5V 603
2
C5H4
.1UF 20% 25V
1
Y5V 603
12
C6H4
2
C4G7
.1UF 20% 25V
1
Y5V 603
2
C3H10
.1UF 20% 25V
1
Y5V 603
2
C2H8
.1UF 20% 25V
1
Y5V 603
12
20%4.7UF
16V Y5V 1206
2
C3H4
.1UF 20% 25V
1
Y5V 603
C3H9
.1UF 20% 25V Y5V 603
C2H12
.1UF 20% 25V Y5V 603
2
1
2
1
2
C5H3
.1UF 20% 25V
1
Y5V 603
C4H9
.1UF 20% 25V Y5V 603
C5H7
.1UF 20% 25V Y5V 603
2
1
2
1
12,18,19,21,24,25,85,89
C6H12
.1UF 20% 25V Y5V 603
C1G13
.1UF 20% 25V Y5V 603
IN
V_SM
2
1
2
1
C3H5
.1UF 20% 25V Y5V 603
C2G10
.1UF 20% 25V Y5V 603
C4H3
.1UF
25V Y5V 603
C4H2
.1UF20%
25V Y5V 603
C2H4
.1UF
25V Y5V 603
C3H3
.1UF
25V Y5V 603
C3H1
.1UF
25V Y5V 603
2
1
2
1
12
20%
12
12
20%
12
20%
12
20%
C4H11
.1UF 20% 25V Y5V 603
C3H8
.1UF 20% 25V Y5V 603
2
1
2
1
C6H3
20%
.1UF
25V
Y5V
603
C2H2
20%
.1UF
25V
Y5V
603
C4H5
20%
.1UF
25V
Y5V
603
C1H2
20%
.1UF
25V
Y5V
603
C5H1
20%
.1UF
25V
Y5V
603
2
C4H7
.1UF 20% 25V
1
Y5V 603
2
C2H9
.1UF 20% 25V
1
Y5V 603
C2H6
12
.1UF
25V Y5V 603
C5H2
12
.1UF 20%
25V Y5V 603
C3H2
12
.1UF
25V Y5V 603
C2H1
12
.1UF
25V Y5V 603
C2H5
12
.1UF
25V Y5V 603
2
C5H8
.1UF 20% 25V
1
Y5V 603
2
C1H8
.1UF 20% 25V
1
Y5V 603
12
20%
12
12
20%
12
20%
12
20%
C6H13
.1UF 20% 25V Y5V 603
C2H10
.1UF 20% 25V Y5V 603
2
C2H11
.1UF 20% 25V
1
Y5V 603
2
C3H7
.1UF 20% 25V
1
Y5V 603
DIMM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ7
DQ8 DQ9 DQ10
DQ12 DQ13 DQ14 DQ15
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29
DQ31 DQ27
2
C6H11
.1UF 20% 25V
1
Y5V 603
2
C4H8
.1UF 20% 25V
1
Y5V 603
CHANNEL B
DIMM TO MCH
BIT SWAPPING
MCH DQ5 DQ1 DQ6 DQ3 DQ4 DQ0
DQ2
DQ12 DQ13 DQ10 DQ11DQ11
DQ8
DQ9 DQ14 DQ15
DQ21 DQ16 DQ23 DQ18 DQ20 DQ17 DQ22 DQ19
DQ28 DQ24 DQ30 DQ26 DQ29 DQ25 DQ31DQ30
DIMM
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ39
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ62 DQ63 DQ58
MCH DQ36 DQ33 DQ38 DQ35 DQ37 DQ32
DQ34
DQ44 DQ41 DQ46 DQ42 DQ45 DQ40 DQ47 DQ43
DQ52 DQ48 DQ55 DQ51 DQ53 DQ49 DQ54 DQ50
DQ61 DQ57 DQ63 DQ59 DQ60 DQ56
D
C
B
A
DECOUPLING CAPACITORS FOR DDR TERMINATION RESISTORS
CORE PAGE
8 7
[PAGE_TITLE=DDR1 DIMM-B 0/1 DCPL]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
28
4.0
<XR_PAGE_TITLE>
BOM NOTE:
STUFF FOR AC97
5% EMPTY
R6B17
AUDIO ONLY
12
22
402
R6B13
5%CH33
CH
5%
CH
R5B10
5% 15
EMPTY
R5B12
5% CH
R5B11
1% 33 CH
R6B19
5% CH
5% 33 CH
12
402
R6B11
5%
R5B9
R6C2
12
402
12
33
402
12
402
12
33
402
12
402
R6B18
5%CH33
R6B16
12
225%
CH
402
R6B12
12
5%CH33
12
12
33
402
402
R6B10
33
402
EMPTY
R6C3
5%CH33
12
402
12
402
VCC3
DESIGN NOTE:
D
1
2
A51464-001
FB6B1
FB
0402, 120 OHM 200MA
2
SM
1
108426-120
2
C6B8
10.0UF 20%
6.3V X5R 1206
C6B17
.01UF 20% 50V
1
X7R 603
2
2
C6B12
.01UF 20% 50V
1
1
X7R 603
VDD_SRC_CLKA
C5B7
.01UF 20% 50V X7R 603
30
OUT
KEEP ALL SHARED 14MHZ CLOCKS AT 15 OHM
CK_14M_R
VCC3
R6C1
5%
2.40 CH
402
C
Y6B1
14.318MHZ
1 2
SM
12
C6B11
22PF 5% 50V NPO 603
VCC3_CLK48
12
2
2
C6C4
C6C1
4.7UF
.01UF
20%
20%
16V
1
202170-004
XTAL
12
C6B10
22PF 5% 50V NPO 603
50V
1
Y5V
X7R
1206
603
7,8,17 7,8,17 7,8,17
IN
IN
BI BI
R5C7
CH 402
IN IN IN
VTT_PWRGD*
V_3P3_STBY
SMB_DATA_MAIN SMB_CLK_MAIN
OSC_CK14M_XTALOUT OSC_CK14M_XTALIN
12
1%475
H_FSBSEL2 H_FSBSEL1 H_FSBSEL0
CLK_IREF
30
38..41,43,55,56,73,74,79,87,88,90,92,93,95,105,106
21,25,74 21,25,74
1 7
48
16
53
46 47
49 50
39
37 38 54
VDD VDD VDD_REF VDD_48
VTT_PWRGD*/PD
VDD_SUSPEND
SDA SCL
XTAL_OUT XTAL_IN
IREF
FSC FSB FSA
B
U6B2A
CK_410E
1
PCIF_2
PCIF_1
PCIF_0/TP_EN
PCI_4
PCI_3
PCI_2
PCI_1
PCI_0
USB_48
VSS_REF
VSS_48
1 of 2
REF0
VSS VSS
IC
CK_PCIF2_R
52
CK_PCIF1_R
1011
9
CK_PCIF0_R
8
CK_PCI4_R
5
4
3
56
55
12
2 6 51 13
CK_PCI3_R
CK_PCI2_R
CK_PCI1_R
CK_PCI0_R
CK_48M_USB_ICH_R
28 7 6 5 4 3 1
CK_14M_AUD
CK_14M_PA
CK_14M_ICH
CK_P_33M_ICH
CK_P_33M_FWH
12
CK_P_33M_1394
402
CK_P_33M_TPM
CK_P_33M_PA
CK_P_33M_S2
CK_P_33M_S1
CK_P_33M_S4
CK_P_33M_S5
335%
CK_P_33M_S3
CK_48M_USB_ICH
60
OUT
73
OUT
40
OUT
37
OUT
72
OUT
105
OUT
70
OUT
73
OUT
50
OUT
49
OUT
OUT
OUT
OUT
38
OUT
D
C
B
A
CORE PAGE
VCC
8 7
30
C7H8 .1UF
12
16V 20% 402
IN
105
IN
72
IN
CK_P_33M_S5
CK_P_33M_1394
CK_P_33M_FWH
2
C6B20
10PF 5% 50V
1
EMPTY 402
38 37 70
50 49
2
C7B8
10PF 5% 50V
1
EMPTY 402
CK_48M_USB_ICH
IN
CK_P_33M_ICH
IN
CK_P_33M_TPM
IN
CK_P_33M_S3
IN
CK_P_33M_S2
IN
CK_P_33M_S1
IN
CK_P_33M_S4
IN
2
2
2
2
2
2
C6B13
C6B14
C6B15
C5B5
10PF
10PF 5% 50V EMPTY 402
10PF 5% 50V
1
1
EMPTY 402
5% 50V
1
1
EMPTY
2
C6B9
10PF 5% 50V
1
EMPTY 402
402
10PF 5% 50V EMPTY 402
C6B19
10PF 5% 50V
1
EMPTY 402
45
2
C6B21
C6C3
10PF
10PF
5%
5% 50V EMPTY 402
50V
1
EMPTY
402
1
36
VDD_SRC_CLKA
IN
[PAGE_TITLE=CK410E PAGE 1 OF 2]
INTEL
CONFIDENTIAL
2 1
R6B14
2
10K
BOM NOTE:
5%
STUFF FOR XDP
EMPTY
EMPTY FOR X1 SLOT2
402
1
CK_P_33M_PA
R6B15
2
10K
BOM NOTE:
5%
STUFF FOR X1 SLOT2
CH
EMPTY FOR XDP
402
1
DOCUMENT NUMBER PAGE REV
C77862
73
IN
29
A
4.0
D
C
B
A
<XR_PAGE_TITLE>
VCC3 VCC3
0402, 120 OHM, 200MA
CORE PAGE
LOCATION
R5C12 R5C13 R5C15 R5C16
CK_H_XDP_NODE*
IN
IN
FB6C2
1 2
A51464-001
0402, 120 OHM, 200MA
EMPTY
VCC3_CLKA
2
1
FB6C1
1 2
A51464-001
X1 SLOT2
STUFF STUFF EMPTY EMPTY
FB
6
6
10
10
EMPTY EMPTY STUFF STUFF
VDD_A_FB
OUT
OUT
R5C9
1
49.9 1%
CH
2
402
OUT
OUT
R5C3
1
49.9 1%
CH
2
402
OUT
OUT
R5B13
1
49.9 1%
CH
2
402
XDP
0 5%
402
402 EMPTY
402 CH
CK_H_XDP_NODE
0 5%
402 EMPTY
8 7
C6C11
4.7UF 20%
6.3V Y5V 1206
1
2
1
2
1
2
R5C12
R5C15
R5C13
R5C16
R5C14
49.9 1%
CH 402
R5C6
49.9 1%
CH 402
R5B17
49.9 1%
CH 402
108426-120
CH
5%0
5%0
DESIGN NOTE:
STUFF FOR EVALUATION OF COST REDUCTION ON VOLTAGE SOURCE
29
VDD_SRC_CLKA
IN
2
1
2
1
CK_H_XDP_NODE*
CK_H_XDP_NODE
CK_H_CPU*
CK_H_CPU
CK_H_MCH*
CK_H_MCH
12
C5C3
.01UF 20% 50V X7R 603
C6C12
10.0UF 20%
6.3V X5R 1206
DESIGN NOTE:
REMOVE OFF-PAGE FOR UATX
CK_PE_100M_X1_2*
2
1
2
1
C5C1
.01UF 20% 50V X7R 603
C6C7
.01UF 20% 50V X7R 603
402
402
402
402
402
402
R5C11
1 2
33
R5C10
1 2
R5C5
1 2
33 5%
R5C4
1 2
R5B15
1 2
33
R5B14
1 2
33
5% CH
CK_H_XDP_R
5%CH33
CH
5%CH33
5% CH
5% CH
2
C6C10
.01UF 20% 50V
1
X7R 603
CK_H_CPU_R*
CK_H_CPU_R
CK_H_MCH_R*
12
12
CK_PE_100M_X1_2
12
1 2
402
CK_H_XDP_R*
CK_H_XDP*
CK_H_XDP
28 7 6 5 4 3 1
R5C1
5%0
CH
2
C6C5
.01UF 20% 50V
1
X7R 603
CK_H_MCH_R
52
OUT
OUT
52
OUT
OUT
19
43 28
35 36
41 42
44 45
25 40 20 29
101
101
CAD NOTE:
PLACE (1) PER PIN
VDD_SRC VDD_SRC VDD_CPU VDD_SATA
CPU2_ITP_SRC7* CPU2_ITP_SRC7
CPU_1* CPU_1
CPU_0* CPU_0
VSS_SATA VSS_CPU VSS_SRC VSS_SRC
97 96
U6B2B
CK_410E
29
1
IN
IN
SRC6*
SRC5*
SATA_SRC4*
SATA_SRC4
SRC3*
SRC2*
SRC1*
DOT_96*
DOT_96
2 of 2
VREG FEATURE
VDD_SRC_CLKA
VCCP
SRC6
SRC5
SRC3
SRC2
SRC1
32 3334
30 31
27 26
24 23
22 21
18 17
15 14
IC
1 2
R5C8
5%220 CH402
CK_PE_SRC6_R*
CK_PE_SRC6_R
CK_PE_SRC5_R*
CK_PE_SRC5_R
CK_PE_SRC4_R
CK_PE_SRC2_R*
CK_PE_SRC2_R
CK_PE_SRC1_R*
CK_PE_SRC1_R
CK_96M_DOT_R*
CK_96M_D0T_R
R5B18
1 2
402 CH
VTT_PWRGD_FET_CTRL
CK_PE_SRC4_R*
CK_PE_SRC3_R*
CK_PE_SRC3_R
5%10K
1
VTT_PWRGD*
3
Q5C1
MMBT3904 XSTR
2
45
R5C19
5% CH
R5C17
5% CH
R5C24
CH
R5C21
CH
CH
R6C18
CH
R6C16
CH
R6C15
5% 33 CH
R6C13
5% 33 CH
R6C11
5% CH
R6C9
R6C7
R6C5
5% 33 CH
R5C2
1
0 5%
EMPTY
2
402
R6C22
R6C21
12
33
402
12
33
402
12
335%
402
12
335%
402
12
335%
402
12
33CH5%
402
12
335%
402
12
335%
402
12
402
12
402
12
33
402
12
33CH5%
402
12
33CH5%
402
12
402
OUT
36
CK_PE_100M_LAN*
CK_PE_100M_LAN
CK_PE_100M_MCH*
CK_PE_100M_MCH
CK_ICHSATA*
CK_ICHSATA
CK_PE_100M_ICH*
CK_PE_100M_ICH
CK_PE_100M_16PORT*
CK_PE_100M_16PORT
CK_96M_DREF*
CK_96M_DREF
29
56
OUT
56
R5C20
1
49.9 1%
CH
2
402
R5C23
1
49.9 1%
CH
2
402
R6C23
1
49.9 1%
CH
2
402
R6C19
1
49.9 1%
CH
2
402
R6C14
1
49.9 1%
CH
2
402
R6C10
1
49.9 1%
CH
2
402
R6C6
1
49.9 1%
CH
2
402
OUT
R5C18
1
49.9 1%
CH
2
402
OUT
OUT
R5C22
1
49.9 1%
CH
2
402
OUT
OUT
R6C20
1
49.9 1%
CH
2
402
OUT
OUT
R6C17
1
49.9 1%
CH
2
402
CK_PE_100M_X1_1*
CK_PE_100M_X1_1
R6C12
1
49.9 1%
CH
2
402
OUT
OUT
R6C8
1
49.9 1%
CH
2
402
OUT
OUT
R6C4
1
49.9 1%
CH
2
402
11
11
39
SATA MUST BE ON PIN_26, PIN_27
39
38
38
32
32
15
15
[PAGE_TITLE=CK410E PAGE 2 OF 2]
INTEL
CONFIDENTIAL
2 1
DOCUMENT NUMBER PAGE REV
DESIGN NOTE:
C77862
D
C
51
OUT
51
OUT
B
A
30
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
C
D
C
BLANK PAGE
B
B
A
DOCUMENT NUMBER PAGE REV
C77862
31
8 7
[PAGE_TITLE=BLANK]
INTEL
45
36
CONFIDENTIAL
2 1
A
4.0
<XR_PAGE_TITLE>
VCC3 +12V +12V VCC3
B1 B2
D
39,49..51,56,74,79
39,49..51,56,74
40,43,51,56
C
B
A
BI
BI
49..51,56..59,90
IN OUT
33
IN
33
IN
11
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
11
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
33
IN
SMB_CLK_RESUME
SMB_DATA_RESUME
V_3P3_PCIVAUX
WAKE*
EXP_A_TXP_0_C EXP_A_TXN_0_C
SDVO_CTRL_CLK
EXP_A_TXP_1_C
EXP_A_TXN_1_C
EXP_A_TXP_2_C EXP_A_TXN_2_C
EXP_A_TXP_3_C
EXP_A_TXN_3_C
SDVO_CTRL_DATA
EXP_A_TXP_4_C EXP_A_TXN_4_C
EXP_A_TXP_5_C EXP_A_TXN_5_C
EXP_A_TXP_6_C EXP_A_TXN_6_C
EXP_A_TXP_7_C EXP_A_TXN_7_C
EXP_A_TXP_8_C EXP_A_TXN_8_C
EXP_A_TXP_9_C
EXP_A_TXN_9_C
EXP_A_TXP_10_C EXP_A_TXN_10_C
EXP_A_TXP_11_C EXP_A_TXN_11_C
EXP_A_TXP_12_C
EXP_A_TXN_12_C
EXP_A_TXP_13_C
EXP_A_TXN_13_C
EXP_A_TXP_14_C EXP_A_TXN_14_C
EXP_A_TXP_15_C
EXP_A_TXN_15_C
TP_3G16_JTAG1
TP_3G16_RSVD_B12
TP_16PRSNT_B43
TP_3G16_RSVD_B80 TP_16PRSNT_B82
B3 B4 B5 B6 B7 B8
B9 B10 B11
B12 B13 B14 B15 B16 B17 B18
B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82
CORE PAGE
8 7
12V 12V 12V GND SMCLK SMDAT GND
3.3V JTAG1
3.3VAUX WAKE*
RSVD GND HSOP0 HSON0 GND PRSNT2* GND
HSOP1 HSON1 GND GND HSOP2 HSON2 GND GND HSOP3 HSON3 GND RSVD PRSNT2* GND
HSOP4 HSON4 GND GND HSOP5 HSON5 GND GND HSOP6 HSON6 GND GND HSOP7 HSON7 GND PRSNT2* GND
HSOP8 HSON8 GND GND HSOP9 HSON9 GND GND HSOP10 HSON10 GND GND HSOP11 HSON11 GND GND HSOP12 HSON12 GND GND HSOP13 HSON13 GND GND HSOP14 HSON14 GND GND HSOP15 HSON15 GND PRSNT2* RSVD
J6C1
3GIO_X16
1.0
KEY
1 OF 1
PRSNT1*
JTAG2 JTAG3 JTAG4 JTAG5
PWRGD
REFCLK+ REFCLK-
HSIP0 HSIN0
HSIP1 HSIN1
HSIP2 HSIN2
HSIP3 HSIN3
HSIP4 HSIN4
HSIP5 HSIN5
HSIP6 HSIN6
HSIP7 HSIN7
HSIP8 HSIN8
HSIP9 HSIN9
HSIP10 HSIN10
HSIP11 HSIN11
HSIP12 HSIN12
HSIP13 HSIN13
HSIP14 HSIN14
HSIP15 HSIN15
12V
3.3V
3.3V
RSVD
RSVD
RSVD
RSVD
12V
GND
GND
GND
GND
GND
GND GND
GND GND
GND
GND
GND GND
GND GND
GND GND
GND
GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND
CONN
BOM NOTE:
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
A12 A13 A14 A15 A16 A17 A18
A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32
A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82
TP_16PRSNT_A1
TP_3G16_JTAG2 TP_3G16_JTAG3 TP_3G16_JTAG4 TP_3G16_JTAG5
P_RST_SLOTS*
EXP_A_RXP_0 EXP_A_RXN_0
TP_3G16RSVD_A19
EXP_A_RXP_1 EXP_A_RXN_1
EXP_A_RXP_2 EXP_A_RXN_2
EXP_A_RXP_3 EXP_A_RXN_3
TP_3G16_RSVD_A32
TP_3G16_RSVD_A33
EXP_A_RXP_4 EXP_A_RXN_4
EXP_A_RXP_5 EXP_A_RXN_5
EXP_A_RXP_6 EXP_A_RXN_6
EXP_A_RXP_7 EXP_A_RXN_7
TP_3G16_RSVD_A50
EXP_A_RXP_8 EXP_A_RXN_8
EXP_A_RXP_9 EXP_A_RXN_9
EXP_A_RXP_10 EXP_A_RXN_10
EXP_A_RXP_11 EXP_A_RXN_11
EXP_A_RXP_12 EXP_A_RXN_12
EXP_A_RXP_13 EXP_A_RXN_13
EXP_A_RXP_14 EXP_A_RXN_14
EXP_A_RXP_15 EXP_A_RXN_15
CK_PE_100M_16PORT
CK_PE_100M_16PORT*
45
USE C55845-002 FOR X16 CONN
IN
IN IN
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
OUT OUT
36
51,74
30 30
11 11
11 11
11 11
11 11
11 11
11 11
11 11
11 11
11 11
11 11
11 11
11 11
11 11
11 11
11 11
11 11
28 7 6 5 4 3 1
PCI EXPRESS
16-PORT
VCC3 +12V
C6B16
.1UF 20% 25V Y5V
1 2
603
V_3P3_PCIVAUX
49..51,56..59,90
IN
VCC3
1
C7B7
100UF 20% 25V ELEC
2
RDL
1
GND
2
GND
1.0
E
PCI RETENTION MODEL
[PAGE_TITLE=PCIE 16-PORT]
INTEL
DOCUMENT NUMBER PAGE REV
CONFIDENTIAL
2 1
J7E1
PCIE_RM
C7B6
.1UF 20% 25V Y5V
1 2
603
C77862
C51194-002
CONN
+12V
D
C
C7C1
.1UF 20% 25V Y5V
1 2
603
1
C7B5
470UF 20% 16V ALUM
2
RDL
B
A
32
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
11
D
IN
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
EXP_A_TXN_0 EXP_A_TXP_0
EXP_A_TXN_1 EXP_A_TXP_1
EXP_A_TXN_2 EXP_A_TXP_2
EXP_A_TXN_3 EXP_A_TXP_3
C6C8
.1UF
20%
25V
603
C6C13
.1UF
20%
25V
603
C6D2
.1UF 20%
25V
603
C
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
B
A
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
11
IN
EXP_A_TXN_4 EXP_A_TXP_4
EXP_A_TXN_5 EXP_A_TXP_5 EXP_A_TXP_5_C
EXP_A_TXN_6 EXP_A_TXN_6_C EXP_A_TXP_6
EXP_A_TXN_7 EXP_A_TXP_7
EXP_A_TXN_8 EXP_A_TXP_8
EXP_A_TXN_9 EXP_A_TXP_9
EXP_A_TXN_10 EXP_A_TXP_10
EXP_A_TXN_11 EXP_A_TXP_11
EXP_A_TXN_12 EXP_A_TXP_12 EXP_A_TXP_12_C
EXP_A_TXN_13 EXP_A_TXP_13
EXP_A_TXN_14 EXP_A_TXN_14_C EXP_A_TXP_14
EXP_A_TXN_15 EXP_A_TXP_15
C6D7
.1UF 20%
25V
603
C6D13
.1UF
20%
25V
603
C6D18
.1UF 20%
25V
603
C6D23
.1UF 20%
25V
603
C6E3
.1UF 20%
25V
603
C6E7
.1UF
20%
25V
603
C6C9
12
Y5V
12
Y5V
12
Y5V
12
Y5V
12
Y5V
12
Y5V
12
Y5V
12
Y5V
12
Y5V
12
.1UF
20%
25V
Y5V
603
C6C14
12
.1UF
20%
25V
Y5V
603
C6C20
12
.1UF
20%
25V
Y5V
603
C6D6
12
.1UF 20%
25V
Y5V
603
C6D12
12
.1UF 20%
25V
Y5V
603
C6D17
12
20%.1UF
25V
Y5V
603
C6D22
12
20%
.1UF
25V
Y5V
603
C6E2
12
20%.1UF
25V
Y5V
603
C6E6
12
.1UF
20%
25V
Y5V
603
C6C17
12
C6C16
1
.1UF 20%
25V
603
C6D4
.1UF 20%
25V
603
C6D9
.1UF 20%
25V
603
C6D15
.1UF 20%
25V
603
C6D21
.1UF 20%
25V
603
C6E1
.1UF 20%
25V
603
C6E5
.1UF
20%
25V
603
2
Y5V
.1UF
20%
25V
Y5V
603
12
C6D3
2
Y5V
12
Y5V
12
Y5V
12
Y5V
12
Y5V
12
Y5V
1
.1UF
20%
25V
Y5V
603
C6D8
1
2
20%
.1UF
25V
Y5V
603
C6D14
1
2
.1UF
20%
25V
Y5V
603
C6D19
1
2
.1UF 20%
25V
Y5V
603
C6D24
2
1
.1UF 20%
25V
Y5V
603
C6E4
1
2
20%.1UF
25V
Y5V
603
EXP_A_TXN_0_C EXP_A_TXP_0_C
EXP_A_TXN_1_C EXP_A_TXP_1_C
EXP_A_TXN_2_C
EXP_A_TXP_2_C
EXP_A_TXN_3_C
EXP_A_TXP_3_C
EXP_A_TXN_4_C EXP_A_TXP_4_C
EXP_A_TXN_5_C
EXP_A_TXP_6_C
EXP_A_TXN_7_C EXP_A_TXP_7_C
EXP_A_TXN_8_C EXP_A_TXP_8_C
EXP_A_TXN_9_C EXP_A_TXP_9_C
EXP_A_TXN_10_C EXP_A_TXP_10_C
EXP_A_TXN_11_C EXP_A_TXP_11_C
EXP_A_TXN_12_C
EXP_A_TXN_13_C EXP_A_TXP_13_C
EXP_A_TXP_14_C
EXP_A_TXN_15_C
EXP_A_TXP_15_C
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
D
C
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
32
OUT
B
A
CORE PAGE
8 7
[PAGE_TITLE=PCIE COUPLING]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
33
4.0
28 7 6 5 4 3 1
D
C
D
C
BLANK PAGE
B
B
A
DOCUMENT NUMBER PAGE REV
C77862
34
8 7
INTEL
CONFIDENTIAL
45
36
2 1
A
4.0
28 7 6 5 4 3 1
D
C
D
C
BLANK PAGE
B
B
A
DOCUMENT NUMBER PAGE REV
C77862
35
8 7
INTEL
45
36
CONFIDENTIAL
2 1
A
4.0
28 7 6 5 4 3 1
D
C
D
C
BLANK PAGE
B
B
A
DOCUMENT NUMBER PAGE REV
C77862
36
8 7
INTEL
45
36
CONFIDENTIAL
2 1
A
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
D
U8G1F
ICH6
PCI
2.0
AD_0 AD_1 AD_2 AD_3 AD_4 AD_5 AD_6 AD_7 AD_8 AD_9
AD_10 AD_11 AD_12 AD_13 AD_14 AD_15 AD_16 AD_17 AD_18 AD_19 AD_20 AD_21 AD_22 AD_23 AD_24 AD_25 AD_26 AD_27 AD_28 AD_29 AD_30 AD_31
C_BE_3* C_BE_2* C_BE_1* C_BE_0*
1 of 6
E2 E5 C2 F5 F3 E9 F2 D6 E6 D3 A2 D2 D5 H3 B4 J5 K2 K5 D4 L6 G3 H4 H2 H5 B3 M6 B2 K6 K3 A5 L1 K4
G2 G4 H6 J6
IC
49,50,105
49,50,54,105
29
49,50,105
15,55,56,70,72,73
C
VCC3
R8D10
12
4.7K 5% 402
J8D2
EMPTY
1X3HDR
1
OUT
BOOT_BIOS_DIS_SEL
2 3
EMPTY
B
49,50,54,105
49,50,57,105 49,50,54,105 49,50,54,105
49,50,54 49,50,54,105 49,50,54,105 49,50,54,105
105
49
50 53 99
54,105
49,54 50,54
54 54 54 54
54
54,105
54
54 49,50,54 49,50,54 49,50,54 49,50,54
P_PAR
BI
P_DEVSEL*
BI
CK_P_33M_ICH
IN
P_PCIRST*
OUT
PLTRST*
OUT
P_IRDY*
BI
P_PME*
BI
P_SERR*
BI
P_STOP*
BI
P_PLOCK*
BI
P_TRDY*
BI
P_PERR*
BI
P_FRAME*
BI
P_GNT0*
OUT
P_GNT1*
OUT
P_GNT2*
OUT
P_GNT3*
OUT
P_GNT4*
OUT
TP_P_GNT5* TP_P_GNT6*
P_REQ0*
IN
P_REQ1*
IN
P_REQ2*
IN
P_REQ3*
IN
P_REQ4*
IN
P_REQ5*
IN
P_REQ6*
IN
P_INTA*
IN
P_INTB*
IN
P_INTC*
IN
P_INTD*
IN
P_INTE*
IN
P_INTF*
IN
P_INTG*
IN
P_INTH*
IN
E1 C3 G6 R2 R5
A3
P6 G5
J1 C5
J2
E3
J3
C1
B6
F1 C8
E7
F6 D8
L5
B5 M5
B8
F7
E8
B7
N2
L2 M1
L3 D9 C7 C6 M3
PAR DEVSEL* PCICLK PCIRST* PLTRST* IRDY* PME* SERR* STOP* PLOCK* TRDY* PERR* FRAME*
GNT_0* GNT_1* GNT_2* GNT_3* GNT_4*_GPIO48 GNT_5*_GPIO17 GNT_6*_GPIO16
REQ_0* REQ_1* REQ_2* REQ_3* REQ_4*_GPIO40 REQ_5*_GPIO1 REQ_6*_GPIO0
PIRQA* PIRQB* PIRQC* PIRQD* PIRQE*_GPIO2 PIRQF*_GPIO3 PIRQG*_GPIO4 PIRQH*_GPIO5
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
3 2 1 0
P_AD0
P_AD1
P_AD2
P_AD3
P_AD4
P_AD5
P_AD6
P_AD7
P_AD8
P_AD9
P_AD10
P_AD11
P_AD12
P_AD13
P_AD14
P_AD15
P_AD16
P_AD17
P_AD18
P_AD19
P_AD20
P_AD21
P_AD22
P_AD23
P_AD24
P_AD25
P_AD26
P_AD27
P_AD28
P_AD29
P_AD30
P_AD31
P_C/BE*3
P_C/BE*2
P_C/BE*1
P_C/BE*0
P_AD[31..0]
P_C/BE*[3..0]
49,50,105
49,50,105
VCC3
C8F10
.1UF
25V
Y5V 603
C9G2
.1UF
25V
Y5V 603
C9G5
.1UF
25V
Y5V 603
C9G4
.1UF
25V
Y5V 603
CAD NOTE:
PLACE 1 EACH NEAR A3 & F1. PLACE REMAINDER ANYWHERE
12
C
20%
12
20%
12
20%
12
20%
B
BI
BI
A
A
[PAGE_TITLE=ICH 1 OF 6 - CONTROL]
DOCUMENT NUMBER PAGE REV
C77862
37
4.0
8 7
INTEL
CONFIDENTIAL
45
36
2 1
<XR_PAGE_TITLE>
DESIGN NOTE: FOR PCI_E X1 SLOT 1
D
DESIGN NOTE: FOR LAN
C
B
A
28 7 6 5 4 3 1
U8G1A
ICH6
DMI
USB
PCI EXPRESS
V_3P3_STBY
29,39..41,43,55,56,73,74,79,87,88,90,92,93,95,105,106
IN
PLACE (2) 0.1UF NEAR A17 PLACE 0.01UF NEAR A24
2.0
USBP_0N USBP_0P USBP_1N USBP_1P USBP_2N USBP_2P USBP_3N USBP_3P USBP_4N USBP_4P USBP_5N USBP_5P USBP_6N USBP_6P USBP_7N USBP_7P
OC_4*_GPIO9 OC_5*_GPIO10 OC_6*_GPIO14 OC_7*_GPIO15
USBRBIAS
USBRBIAS*
OC_0* OC_1* OC_2* OC_3*
CLK48
2 of 6
IC
USB CLASSIC FILTER
C21
USB_FRONT1*
D21
USB_FRONT1
A20
USB_FRONT2*
B20
USB_FRONT2
D19
USB_BACK4*
C19
USB_BACK4
A18
USB_FRONT3*
B18
USB_FRONT3
E17
USB_BACK3*
D17
USB_BACK3
B16
USB_FRONT4*
A16
USB_FRONT4
C15
USB_BACK2*
D15
USB_BACK2
A14
USB_BACK1*
B14
USB_BACK1
C27 B27 B26 C26 C23 D23 C25 C24
B22 A22
A27
C8F12
10%
.1UF
16V X7R 603
C8F13
10%
.1UF
16V X7R 603
BI BI BI BI BI BI BI BI BI BI
BI BI BI
USB_OC_FRONT12*
USB_OC_FRONT34_BACK56* USB_OC_BACK_RIGHT*
USB_OC_BACK_LEFT*
USBRBIAS_ICH
CAD NOTE:
TRACES TIED TOGETHER CLOSE TO PINS LENGTH NO LONGER THAN 200 MIL TO RESISTOR
CK_48M_USB_ICH
BI
402
12
12
BI BI
22.6CH1%
R8F12
12,15..17,39,41,79,87,88,102
48 48 48 48 45 45 46 46 45 45 46 46 59 59 59 59
IN
IN IN
IN
12
IN
IN
CAD NOTE:CAD NOTE:
PLACE 0.01UF NEAR A25 PLACE 0.1UF NEAR D27
47
47
91
91
29
USB HS (HI-SPEED) FILTER
V_1P5_CORE
C7F12
50V X7R 603
C7F11
.1UF 10%
16V X7R 603
D
C
B
12
20%.01UF
12
A
AB24 AB23 AA27 AA26
AD25 AC25
T25
DMI_0RXN
T24
DMI_0RXP
R27
DMI_0TXN
R26
DMI_0TXP
V25
DMI_1RXN
V24
DMI_1RXP
U27
DMI_1TXN
U26
DMI_1TXP
Y25
DMI_2RXN
Y24
DMI_2RXP
W27
DMI_2TXN
W26
DMI_2TXP DMI_3RXN DMI_3RXP DMI_3TXN DMI_3TXP
H25
PERN_1
H24
PERP_1
G27
PETN_1
G26
PETP_1
K25
PERN_2
K24
PERP_2
J27
PETN_2
J26
PETP_2
M25
PERN_3
M24
PERP_3
L27
PETN_3
L26
PETP_3
P24
PERN_4
P23
PERP_4
N27
PETN_4
N26
PETP_4
F24
DMI_ZCOMP
F23
DMI_IRCOMP
DMI_CLKN DMI_CLKP
C7G5
HSO_P0
IN
HSO_N0
IN
IN
IN
OUT
OUT
HSO_P1
HSO_N1
HSI_P1
HSI_N1
.1UF 20%
25V Y5V 603
C7G3
.1UF
25V Y5V 603
C7G7
.1UF20%
25V EMPTY 603
C7G4
.1UF20%
25V EMPTY 603
C8A7
.1UF20%
16V EMPTY 402
C8A8
.1UF20%
16V EMPTY 402
12
HSO_P0_C
12
HSO_N0_C
20%
12
HSO_P1_C
12
HSO_N1_C
12
HSI_P1_C
12
HSI_N1_C
51
OUT
51
OUT
56
OUT
56
OUT
56
IN
41
V_PCIEXPRESS_PWR
56
IN
IN
FOR PCI_E X1 SLOT 2 (ATX)DESIGN NOTE:
C7G9
12
C7G6
HSO_P2_C
25V 603
12
HSO_N2_C
20%
25V 603
12
TP_HSO_P3_C
20%
12
TP_HSO_N3_C
20%
52
OUT
52
OUT
IN
IN
IN
IN
HSO_P2
HSO_N2
HSO_P3
HSO_N3
.1UF20% CH
.1UF CH
C7G11
.1UF
25V
EMPTY
603
C7G10
.1UF
25V
EMPTY
603
11,100
11,100 11,100 11,100 11,100
11,100 11,100 11,100 11,100
11,100 11,100 11,100 11,100
11,100 11,100 11,100
52
CAD NOTE:
CONNECT TRACES TOGETHER CLOSE TO ICH PINS
30
30
DMI_MTN_IRN_0
IN
DMI_MTP_IRP_0
IN
DMI_ITN_MRN_0
OUT
DMI_ITP_MRP_0
OUT
DMI_MTN_IRN_1
IN
DMI_MTP_IRP_1
IN
DMI_ITN_MRN_1
OUT
DMI_ITP_MRP_1
OUT
DMI_MTN_IRN_2
IN
DMI_MTP_IRP_2
IN
DMI_ITN_MRN_2
OUT
DMI_ITP_MRP_2
OUT
DMI_MTN_IRN_3
IN
DMI_MTP_IRP_3
IN
DMI_ITN_MRN_3
OUT
DMI_ITP_MRP_3
OUT
51
HSI_N0
IN
51
HSI_P0
IN
HSO_N0
OUT
HSO_P0
OUT
HSI_N1
IN
HSI_P1
IN
HSO_N1
OUT
HSO_P1
OUT IN
52
IN OUT OUT
OUT OUT
R7G1
12
402
CH 1%
24.9
CK_PE_100M_ICH*
IN
CK_PE_100M_ICH
IN
HSO_N2 HSO_P2 TP_HSI_N3 TP_HSI_P3 HSO_N3 HSO_P3
DMICOMP_ICH
HSI_N2 HSI_P2
8 7
[PAGE_TITLE=ICH 2 OF 6 - CONTROL]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
38
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
C
B
A
CAD NOTE: PLACE AT ENDS OF PWR CORRIDORS
D
U8G1B
ICH6
44
44 44 44 44 44
44
44 44
ICH_IDE_DD[15..0]
BI
ICH_IDE_DDACK*
BI
ICH_IDE_DDREQ
BI
ICH_IDE_DIOR*
BI
ICH_IDE_DIOW*
BI
ICH_IDE_IORDY
BI
ICH_IDE_DA[2..0]
BI
ICH_IDE_DCS1*
BI
ICH_IDE_DCS3*
BI
ICH_IDE_IRQ
44
IN
AD13
15
ICH_IDE_DD15
14
ICH_IDE_DD14
13
ICH_IDE_DD13
12
ICH_IDE_DD12
11
ICH_IDE_DD11
10
ICH_IDE_DD10
9
ICH_IDE_DD9
8
ICH_IDE_DD8
7
ICH_IDE_DD7
6
ICH_IDE_DD6
5
ICH_IDE_DD5
4
ICH_IDE_DD4
3
ICH_IDE_DD3
2
ICH_IDE_DD2
1
ICH_IDE_DD1
0
ICH_IDE_DD0
0 1 2
DD_15
AG15
DD_14
AE15
DD_13
AC13
DD_12
AB13
DD_11
AB12
DD_10
AF13
DD_9
AE13
DD_8
AB11
DD_7
AD11
DD_6
AC11
DD_5
AE14
DD_4
AD12
DD_3
AF14
DD_2
AF15
DD_1
AD14
DD_0
AB15
DDACK*
AB14
DDREQ
AE16
DIOR*
AC14
DIOW*
AF16
IORDY
AC16
ICH_IDE_DA0
DA0
AB17
ICH_IDE_DA1
DA1
AC17
ICH_IDE_DA2
DA2
AD16
DCS1*
AE17
DCS3*
AB16
IDEIRQ
SATA FILTER
C8H1
V_1P5_CORE
IN
12
20%.1UF 25V Y5V 603
C8H2
12
20%
.1UF
25V Y5V 603
2.0
SATA_0RXN SATA_0RXP SATA_0TXN SATA_0TXP SATA_1RXN SATA_1RXP SATA_1TXN SATA_1TXP SATA_2RXN SATA_2RXP
IDE
SATA_2TXN SATA_2TXP SATA_3RXN SATA_3RXP SATA_3TXN SATA_3TXP
SATA_CLKN SATA_CLKP
SATARBIAS*
SATARBIAS
SATA
LINKALERT*
SATA_0GP/GPIO26 SATA_1GP/GPIO29 SATA_2GP/GPIO30 SATA_3GP/GPIO31
INTRUDER*
SMBCLK
SMBDATA
SMLINK_0 SMLINK_1
SATALED*
RSMRST*
RTCX1 RTCX2
RTCRST*
INTVRMEN
SPKR
3 of 6
AE3
SATAHDR_RX0N
AD3
SATAHDR_RX0P
AG2
SATAHDR_TX0N
AF2
SATAHDR_TX0P
AC5
SATAHDR_RX1N
AD5
SATAHDR_RX1P
AF4
SATAHDR_TX1N
AG4
SATAHDR_TX1P
AD7
SATAHDR_RX2N
AC7
SATAHDR_RX2P
AF6
SATAHDR_TX2N
AG6
SATAHDR_TX2P
AC9
SATAHDR_RX3N
AD9
SATAHDR_RX3P
AF8
SATAHDR_TX3N
AG8
SATAHDR_TX3P
AC2
CK_ICHSATA*
AC1
CK_ICHSATA
AG11
SATARBIAS_ICH
AF11
Y4
SMB_CLK_RESUME
W5
SMB_DATA_RESUME
Y5
SMLALERT_ICH
W4
SMLLINK0_ICH
U6
SMLINK1_ICH
AC19
ICH_SATA_LED*
AF17
SATAGP_PU
AE18 AF18 AG18 AA3
ICH_INTRUDER_HDR*
Y3
ICH_RSMRST*
Y1
ICH_RTCX1
Y2
ICH_RTCX2
AA2
ICH_RTCRST_PULLUP
AA5
INTVRMEM
F8
SPKR
IC
71
IN
71
IN
71
OUT
71
OUT
71
IN
71
IN
71
OUT
71
OUT
71
IN
71
IN
71
OUT
71
OUT
71
IN
71
IN
71
OUT
71
OUT
30
IN
CAD NOTE:
30
IN
TIE TRACES TOGETHER CLOSE TO ICH
BI BI
74
OUT
43
IN
40,55,74
IN
43
IN
43
IN
43
IN
OUT
61,72,80
32,49..51,56,74,79 32,49..51,56,74
R8H6
4.7K 402
12
5% CH
R8H1
12
24.9
1%
402
CH
VCC3
V_3P0_BAT_VREG
41,43,90
IN
R9H8
390K
BOM NOTE:
ALWAYS STUFF PULL-UP TO ENABLE INTERNAL VRM. EXTERNAL VRM IS NOT SUPPORTED ON THIS DESIGN.
402
V_3P3_STBY
29,38,40,41,43,55,56,73,74,79,87,88,90,92,93,95,105,106
IN
12
R9H1
10K
5%
402
CH
12
R9G21
10K
5%
402
CH
12
R9G18
10K
5%
402
CH
12
5% CH
C
B
A
VCC3
P-ATA FILTER
C8H4
12
.1UF 20%
25V Y5V 603
8 7
CAD NOTE: PLACE NEAR A15
[PAGE_TITLE=ICH 3 OF 6 - CONTROL]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
39
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
TP_L_DRQ1*
70,72,73
73
70,72,73
43
60
61
43 43
29
58 58
603
R7H1
1 2
58
58
56
56 56 56
1ACH0
C
DESIGN NOTE:
B
6
H_STPCLK* H_STPCLK_ICH*
OUT
VALIDATION FEATURE
CAD NOTE:
PLACE AWAY FROM CPU AREA NEAR ICH IS BEST
ICH_EE_CS
OUT
ICH_EE_DIN
OUT
ICH_EE_DOUT
IN
ICH_EE_CLK
OUT
ICH_LAN_JCLK
IN
ICH_LAN_JRST
56
OUT
ICH_LAN_JRX0
IN
ICH_LAN_JRX1
IN
ICH_LAN_JRX2
IN
ICH_LAN_JTX0
56
OUT
56
ICH_LAN_JTX1
OUT
ICH_LAN_JTX2
56
OUT
73
6 6
6 72 6 6 6,8 6
73
70,73,81
6
6,8
L_AD[3..0]
BI
L_DRQ*
BI
L_FRAME*
BI
AUD_LINK_BCLK_R
IN
AUD_LINK_RST*
OUT
IN OUT OUT
IN
IN OUT OUT
OUT OUT OUT OUT
IN OUT
IN BI OUT
IN
AUD_LINK_SDI2 AUD_LINK_SDO_R AUD_LINK_SYNC_R
CK_14M_ICH
A20GATE H_A20M* H_SLP*
H_IGNNE* ICH_INIT_33V H_INIT* H_INTR H_FERR* H_NMI KBRST* SER_IRQ ICH_H_SMI*
H_THERMTRIP_ICH*
TP_AUD_LINK_SDI0 TP_AUD_LINK_SDI1
TP_ICH_AB24 TP_DPRSTP TP_ICH_AD23
P4
LDRQ_1/GPIO41
P2
0
L_AD0
LAD_0/FB0
N3
1
L_AD1
LAD_1/FB1
N5
2
L_AD2
LAD_2/FB2
N4
3
L_AD3
LAD_3/FB3
N6
LDRQ_0*
P3
LFRAME*
C10
ACZ_BIT_CLK
A10
ACZ_RST*
F11
ACZ_SDIN_0
F10
ACZ_SDIN_1
B10
ACZ_SDIN_2
C9
ACZ_SDOUT
B9
ACZ_SYNC
E10
CLK14
D12
EE_CS EE_DIN EE_DOUT EE_SHCLK
LAN_CLK LAN_RSTSYNC LAN_RXD_0 LAN_RXD_1 LAN_RXD_2 LAN_TXD_0 LAN_TXD_1 LAN_TXD_2
A20GATE A20M* CPUSLP* DPRSLPVR/TP_1 TP_4 TP_2 IGNNE* INIT3_3V* INIT* INTR FERR* NMI RCIN* SERIRQ SMI* STPCLK* THRMTRIP*
EPROM
AF22 AF23 AE27 AE20 AE24 AD27 AG26 AE22 AF27 AG24 AF24 AF25 AD23 AB20 AG27 AE26 AE23
F13 D11 B12
F12 B11 E12 E11 C13 C12 C11 E13
AUDIO LPC
LAN
HOST
U8G1C
ICH6
2.0
MISC
GPI6 GPI7 GPI8
SMBALERT*/GPIO11
GPI12 GPI13
STP_PCI*/GPO18
GPO19
STP_CPU*/GPO20
GPO21
GPO23 GPIO24 GPIO25 GPIO27 GPIO28
CLKRUN*/GPIO32
GPIO33 GPIO34
CPUPWRGD/GPO49
MCH_SYNC*
PWRBTN*
SLP_S3* SLP_S4* SLP_S5*
SUS_STAT*/LPCPD*
SUSCLK
SYS_RESET*
LAN_RST*
TP_0 TP_3
VRMPWRGD
THRM*
WAKE*
PWROK
4 of 6
D
AD19
ICH_GPIO6_1X4_DETECT
AE19
FP_AUD_DETECT
R1
ICH_GPIO8_R
W6
ICH_GPIO11_R
M2
ICH_GPI12_PU
R6
IO_PME*
AC21
TP_ICH_GPO18*
AB21 AD22 AD20 AD21 V3 P5 R3 T3 AF19 AF20 AC18 AG25
AG21 U1 T2
RI*
T4 T5 T6 W3 V6 U2 V5 V2 U3 AF21 AC20 U5 AA1
ICH_GPO20 ICH_GPO21 ICH_GPO23*
ICH_GPIO25_R
ICH_GPIO28_R
TP_ICH_GPIO32
H_PWRGD
ICH_SYNC*
SW_ON* COM_RI_WAKE* SLP_S3* SLP_S4_R*
TP_SLP_S5*
LPCPD* SUSCLK FP_RST*
ICH_RSMRST*
ICH_BATLOW_PU
TP_DXFTEST
ICH_VRMPWRGD_PU ICH_THRM_PU* WAKE* PWRGD_3V
ICH_GPO19*
86
IN
43,64
IN
43
IN
43
IN
43
IN
73
IN
80
OUT
85
OUT
85
OUT
105
OUT
43
IN
43
OUT
6,8,101
OUT
15
IN
43,81
IN
43,78
IN
74,88
OUT
43
OUT
70,73
OUT
73
OUT
7,43,74,81,101
IN
39,55,74
IN
43
IN
43
IN
32,43,51,56
IN
15,72,74
IN
0
BOARDID0
1
BOARDID[5..0]
BOARDID1
2
BOARDID2
3
BOARDID3
IN
43,72,73
C
V_3P3_STBY
29,38,39,41,43,55,56,73,74,79,87,88,90,92,93,95,105,106
IN
R9G19
12
5% CH
DESIGN NOTE:
MOBILE BATTERY STRAP
10K 402
B
IC
A
A
[PAGE_TITLE=ICH 4 OF 6 - CONTROL]
DOCUMENT NUMBER PAGE REV
C77862
40
4.0
8 7
INTEL
CONFIDENTIAL
45
36
2 1
VCC3
1
D
2
IN
C
43
OUT
74
IN
B
PCI EXPRESS DECOUPLING FILTER
A
<XR_PAGE_TITLE>
DESIGN NOTE:
CIRCUIT REMAINS IN DESIGN FOR ENGINEERING EVALUATION OF CHIPSET. ISOLATION OF VOLTAGE SOURCE BY MAKING THE MIC5255 REGULATOR EMPTY.
1
INENOUT
M7G1
1 2
MULTI
0
V_5P0_STBY
3 2
GND BYP
SM
108506-007IND
"X5R"
IN
C8H9
4.7UF 10% 10V EMPTY 1206
V_1P5_CORE
1
C9G1
.1UF 10% 16V
2
EMPTY 603
"X7R"
V_REF5V_SUS
V_REF5V_SUS_SIO
V_1P5_CORE
IN
38
IN
CAD NOTE:
PLACE THESE CAPS AT ENDS OF POWER CORRIDORS
8 7
U8H1
MIC5255
5
4
ICH_REG_BYP
EMPTY
VCCA_PWR_GPLL_PN1_ICH
12,15..17,38,39,79,87,88,102
IN
R3J6
1
10 5%
CH
2
402
R3J2
1 2
EMPTY
402
M7G2
1 2
MULTI
0
SM
108506-002FB
V_PCIEXPRESS_PWR
V_2P5_ICH_VREGOUT
2
C8H8
.01UF 20% 50V
1
EMPTY 603
"X7R"
R7G7
402
V_1P5_CORE
5%0
V_PCIEXPRESS_PWR
12
5%1 CH
1
C7G8
2
C7G15
.01UF
50V X7R 603
C7G12
.01UF 20%
50V X7R 603
C7G2
.01UF 20%
50V X7R 603
1
2
220UF 20%
6.3V ALUM RDL
20%
C8H11
4.7UF 10% 10V EMPTY 1206
V_3P3_STBY
3
2
12
12
12
1
2
OUT
"X5R"
C7H2
4.7UF 20%
6.3V Y5V 1206
1
Q7G1
MMBT3904 XSTR
1
2
V_3P3_STBY
12,15..17,38,39,79,87,88,102
C7H1
.01UF 20% 50V X7R 603
U8G1D
28 7 6 5 4 3 1
ICH6
5 of 6
2.0
POWER
VCC_CPU_IO VCC_CPU_IO VCC_CPU_IO
VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3
VCCSUS1_5_A VCCSUS1_5_B VCCSUS1_5_C VCCSUS1_5_D VCCSUS1_5_E
A8
V_REF5V
43,74
IN
V_2P5_ICH
IN
43
V_REF5V_SUS
IN
VCCDMI_PLL_ICH
12,15..17,38,39,79,87,88,102
1
C8H6
.01UF 10% 50V
2
X7R 603
IN
38
OUT
V_1P5_CORE
IN
V_1P5_CORE
IN
29,38..40,43,55,56,73,74,79,87,88,90,92,93,95,105,106
AA18
AB18
P7
F21
AC27
AE1
A25
AA22 AA23 AA24 AA25 AB25 AB26 AB27
F25 F26
F27 G22 G23 G24 G25 H21 H22
J21
J22 K21 K22
L21
L22 M21 M22 N21 N22 N23 N24 N25 P21 P25 P26 P27 R21 R22
T21
T22 U21 U22
V21
V22
W21 W22
Y21
Y22
AA6
V_1P5_CORE
AB4 AB5 AB6 AC4 AD4 AE4 AE5 AG5 AF5 AA7 AA8 AA9 AB8 AC8 AD8 AE8 AE9 AF9 AG9
V5REF V5REF
VCC2_5 VCC2_5
V5REF_SUS
VCCDMIPLL
VCCSATAPLL
VCCUSBPLL
VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR VCCDMIPWR
VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5
VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5
VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3
VCCRTC
AA19 AA20 AA21 L11 L12 L14 L16 L17 M11 M17 P11 P17 T11 T17 U11 U12 U14 U16 U17 G8 D24 D25 D26 D27 E20 E21 E22 E23 E24 F9 F20 G20
AB22 AD26 AG23
E26 AA10 AA12 AA14 AA15 AA17 AC15 AD17 AG10 AG13 AG16 AG19 A6 B1 E4 H1 H7 J7 L4 L7 M7 P1
A13 F14 G13 G14 A11 A24 U4 V1 V7 W2 Y7 A17 B17 C16 C17 D16 E16 F15 F16 F18 G15 G16 G17 G18
V_1P5_CORE
V_FSB_VTT
VCC3
VCC3
IN
1
2
AB3
R7 U7 G19 G10 G11
IC
45
IN
V_2P5_ICH_VREGOUT
CAD NOTE:
PLACE NEAR E26
CAD NOTE:
PLACE NEAR AG10
C8F8
.01UF 20% 50V X7R 603
36
12,15..17,38,39,79,87,88,102
7..9,12,17,18,43,87
IN
CAD NOTE:
PLACE 0.01UF NEAR A24
VCCSUS_1P5A_ICH
VCCSUS_1P5B_ICH
VCCSUS_1P5C_ICH
R8H4
402
VCC3
C7G1
12
20%.1UF 25V Y5V 603
VCC3
C8H5
12
20%
.1UF
25V Y5V 603
[PAGE_TITLE=ICH 5 OF 6 - POWER]
CONFIDENTIAL
7..9,12,17,18,43,87
V_FSB_VTT
IN
CAD NOTE:
PLACE NEAR ONE OF PINS: AB22, AD26 OR AG23
V_2P5_ICH
IN
CAD NOTE:
PLACE NEAR A18
12
V_2P5_ICH
5%0
EMPTY
DESIGN NOTE:
STUFF ONLY FOR ENGINEERING EXPERIMENT ISOLATES 2P5 VREG
V_3P3_STBY
V_3P0_BAT_VREG
C9G6
12
C9G7
20%.01UF 50V X7R 603
50V X7R 603
INTEL
12
20%.01UF
DOCUMENT NUMBER PAGE REV
OUT
29,38..40,43,55,56,73,74,79,87,88,90,92,93,95,105,106
IN
39,43,90
IN
C7F9
12
.01UF 20%
50V X7R 603
C77862
2 1
1
C8H7
.1UF 20% 25V
2
Y5V 603
1
C8H10
.1UF 20% 25V
2
Y5V 603
D
C
B
A
41
4.0
<XR_PAGE_TITLE>
U8G1E
ICH6
2.0
A1
VSS
A12
AA11 AA13 AA16
AB10 AB19
AC10 AC12 AC22 AC23 AC24 AC26
AD10 AD15 AD18
AD24
AE10 AE11 AE12
AE21 AE25
AF12 AF26
AG12 AG14 AG17 AG20 AG22
VSS
A15
VSS
A19
VSS
A21
VSS
A23
VSS
A26
VSS
A4
VSS
A7
VSS
A9
VSS VSS VSS VSS
AA4
VSS
AB1
VSS VSS VSS
AB2
VSS
AB7
VSS
AB9
VSS VSS VSS VSS VSS VSS VSS
AC3
VSS
AC6
VSS
AD1
VSS VSS VSS VSS
AD2
VSS VSS
AD6
VSS VSS VSS VSS
AE2
VSS VSS VSS
AE6
VSS
AE7
VSS
AF1
VSS VSS VSS
AF3
VSS
AF7
VSS
AG1
VSS VSS VSS VSS VSS VSS
AG3
VSS
AG7
VSS
B13
VSS
B15
VSS
B19
VSS
B21
VSS
B23
VSS
B25
VSS
C14
VSS
C18
VSS
C20
VSS
C22
VSS
C4
VSS
D1
VSS
D10
VSS
D13
VSS
D14
VSS
D18
VSS
D20
VSS
D22
VSS
D7
VSS
E14
VSS
E15
VSS
E18
VSS
E19
VSS
E25
VSS
F17
VSS
F19
VSS
F22
VSS
F4
VSS
G1
VSS
G12
VSS
D
C
B
A
8 7
GND
6 of 6
G21
VSS
G7
VSS
G9
VSS
H23
VSS
H26
VSS
H27
VSS
J23
VSS
J24
VSS
J25
VSS
J4
VSS
K1
VSS
K23
VSS
K26
VSS
K27
VSS
K7
VSS
L13
VSS
L15
VSS
L23
VSS
L24
VSS
L25
VSS
M12
VSS
M13
VSS
M14
VSS
M15
VSS
M16
VSS
M23
VSS
M26
VSS
M27
VSS
M4
VSS
N1
VSS
N11
VSS
N12
VSS
N13
VSS
N14
VSS
N15
VSS
N16
VSS
N17
VSS
N7
VSS
P12
VSS
P13
VSS
P14
VSS
P15
VSS
P16
VSS
P22
VSS
R11
VSS
R12
VSS
R13
VSS
R14
VSS
R15
VSS
R16
VSS
R17
VSS
R23
VSS
R24
VSS
R25
VSS
R4
VSS
T1
VSS
T12
VSS
T13
VSS
T14
VSS
T15
VSS
T16
VSS
T23
VSS
T26
VSS
T27
VSS
T7
VSS
U13
VSS
U15
VSS
U23
VSS
U24
VSS
U25
VSS
V23
VSS
V26
VSS
V27
VSS
V4
VSS
W1
VSS
W23
VSS
W24
VSS
W25
VSS
W7
VSS
Y23
VSS
Y26
VSS
Y27
VSS
Y6
VSS
E27
VSS
AF10
VSS
B24
VSS
IC
45
36
28 7 6 5 4 3 1
HS8G1
ICH6_HSK
1 2
NC_1
NC_2
NC_4
NC_3
NOTE: NO PHYSICAL PINS ON ALLEGRO MODEL
TH
J9H1
1
A13494-005
NC
EMPTY
EMPTY
TH
J7F1
1
NC
EMPTY
A13494-005
[PAGE_TITLE=ICH 6 OF 6 - GROUND]
INTEL
DOCUMENT NUMBER PAGE REV
CONFIDENTIAL
2 1
C46655-001
34
C77862
D
C
B
A
42
4.0
<XR_PAGE_TITLE>
29,38..41,55,56,73,74,79,87,88,90,92,93,95,105,106
J8J3
1X3HDR
1 2 3
EMPTY
D
1-2
2-3
VCC3
2
R8H3
10K 5%
CH 402
1
C
2
R9G17
1K 5%
CH 402
1
B
V_3P3_STBY
IN
12
R9G22
12
R9G15
10K
10K
5%
A
5%
EMPTY
EMPTY
402
402
R9G23
1
10K 5%
R9G9
1
CH
2
10K
402
5% CH
2
402
* = DEFAULT
TP_CLRCMOS
ICH_RTCRST_PULLUP
NET_CLR_CMOS_JUMPER
NORMAL *
CLR CMOS
R8H2
10K 5%
CH 402
2
1
V_3P3_STBY
IN
2
R9G16
10K 5%
CH 402
1
2
1
VCC3
12
R8H7
10K 5%
EMPTY
402
R8H5
1
10K 5%
CH
2
402
8 7
R9G2
10K 5%
CH 402
1
2
OUT
2
R8J16
4.7K 5%
EMPTY 402
1
2
R7H14
10K 5%
CH 402
1
2
2
R1G2
R9H3
220
10K
5%
5%
CH
CH
402
1
12
R7H7
10K 5%
EMPTY
402
R7H6
10K 5%
CH 402
402
1
R8H18
1
10K 5%
EMPTY
2
402
R8H21
1
10K 5%
CH
2
402
39
2
1
FP_AUD_DETECT ICH_GPI12_PU
ICH_THRM_PU* ICH_VRMPWRGD_PU
ICH_GPIO11_R
FP_RST* COM_RI_WAKE*
WAKE*
PA
R2J5
10K 5%
1 2
CH
402
R2J7
1
10K 5%
EMPTY
2
402
R1J12
10K 5%
EMPTY 402
0 1 2 3
4 5
BOARDID0
BOARDID1
BOARDID2
BOARDID3
BOARDID4
BOARDID5
ICH_SATA_LED*
BOARDID[5..0]
OUT OUT OUT OUT
ICH_SATA_LED* 39,74
40,64 40
40 40
OUT OUT OUT
OUT
40
40,78
28 7 6 5 4 3 1
R9G5
DESIGN NOTE:
OUT
OUT
40
40
OUT
72
ICH_GPIO25_R
ICH_GPIO11_R
IN
ICH_GPIO28_R
BAT_WARN
OUT
SLP_S4_R*
40
OUT
40
40
7,40,74,81,101
32,40,51,56
INTRUDER HEADER
39,41,90
V_3P0_BAT_VREG
IN
OUT
40,72,73
ICH PULLUPS & DECOUPLING
402
ICH_GPIO8_R
R9G11
1 2
10KCH5% 402
J7H2
1 2
5 6
1 2
R9H4
1 2
0 5%
402
1 2
0
402
2X3HDR_3
402
2
20K 402 CH
5%1K CH
R7H12
402
EMPTY
EMPTY
5% CH
R9G4
1 2
0
R9H5
R8J15
INTERNAL VRM CONFIG
5%
EMPTY
R9G3
1 2
0 5%
EMPTY
402
4
DESIGN NOTE:
DEBUG HEADER
12
5%1M CH
1
ICH_RTCRST_PULLUP
5%
SW_ON*
SLP_S4*
RPS_OFF*
R9G6
1 2
5%10K CH
402
TP_J43CP1 AC_OK RPS_OFF*
J7H1
1X2HDR
1 2
HDR
ICH_INTRUDER_HDR*
ICH_RTCRST_PULLUP
C8J8
1.0UF 10V Y5V 603
45
AC_OK
12
20%
C7F10
V_3P3_STBY
29,38..41,55,56,73,74,79,87,88,90,92,93,95,105,106
IN
V_3P0_BAT_VREG
39,41,90
40,81
IN
74
OUT
OUT
IN
V_REF5V
41,74
IN
V_FSB_VTT
7..9,12,17,18,41,87
IN
V_REF5V_SUS
41
IN
*NOTE: PLACE ALL WITHIN 40 MILS OF ICH
IN
OUT OUT
40
IN
AUD_LINK_SYNC_R
40
IN
60
AUD_LINK_BCLK
IN
TERMINATION FOR SOFT AUDIO
R8F10
2
5%33 CH
402
R8F11
2
5%33 CH
402
R9B30
33 5%
402
CH
PLACE CLOSE TO ICHCAD NOTE:
1
1
12
AUD_LINK_SDOAUD_LINK_SDO_R
AUD_LINK_SYNC
AUD_LINK_BCLK_R
.1UF
25V Y5V 603
.1UF 20%
603
C8F11
.1UF
25V Y5V 603
C8H3
.1UF
25V Y5V 603
C8F9
25V Y5V 603
C9H3
12
20%
12
25V
Y5V
D
12
20%
12
20%
12
20%.1UF
C
60
OUT
60
OUT
40
OUT
B
FLIP-LID XTAL HOLDER USES STANDARD XTAL.
XY9H1
SOCKET
1 2
10M
2
1
603 CH
C9G10
15PF 5% 50V NPO 603
39
OUT
39
OUT
CONFIDENTIAL
36
BOM NOTE: USE MODFILE TO
TH
ADD 107930-002 XTAL
ASSM
(32.768KHZ) WITH THIS REF DES MINUS THE "X"
R9G25
[PAGE_TITLE=ICH TERMINATION]
INTEL
ICH_RTCX1
12
5%
ICH_RTCX2
2
C9G8
15PF 5% 50V
1
NPO 603
OUT
OUT
DOCUMENT NUMBER PAGE REV
C77862
2 1
39
39
A
43
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
C
B
VCC3
1 2
4.7KCH5% 402
1 2
8.2KCH5% 402
R8H9
R8H10
DESIGN NOTE: SERIES RESISTORS INTEGRATED INTO ICH:
VALUES VARY BETWEEN 18.7 OHMS - 30.2 OHMS
IDE_RST*
74
IN
ICH_IDE_DDREQ
39
OUT
ICH_IDE_DIOW*
39
IN
ICH_IDE_DIOR*
39
IN
ICH_IDE_IORDY
39
OUT
ICH_IDE_DDACK*
39
IN
ICH_IDE_IRQ
39
OUT
ICH_IDE_DA1
39
IN
ICH_IDE_DA0
39
IN
ICH_IDE_DCS1*
39
IN
ICH_IDE_DCS3*
39
IN
ICH_IDE_DA2
39
IN
39
ICH_IDE_DD[15..0]
IN
R1J7
1 2
33 5% 402 CH
IDE_PRI_RST_R
J6J1
2X20HDR_20
1 2 3 4
7
ICH_IDE_DD7 ICH_IDE_DD8
5 6
6
ICH_IDE_DD6
7 8
5
ICH_IDE_DD5
9 10
4
ICH_IDE_DD4
11 12
3
ICH_IDE_DD3
13 14
2
ICH_IDE_DD2
15 16
1
ICH_IDE_DD1
17 18
0
ICH_IDE_DD0
19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
HDR
8 9
ICH_IDE_DD9
10
ICH_IDE_DD10
11
ICH_IDE_DD11
12
ICH_IDE_DD12
13
ICH_IDE_DD13
14
ICH_IDE_DD14
15
ICH_IDE_DD15
TP_IDE_PRI_32
PRIMARY IDE CONNECTOR
2
C8J3
.047UF 20% 50V
1
EMPTY 603
"X7R" (+/- 10%)
CAD NOTE: PLACE CLOSE TO CONNECTOR PIN
BOM NOTE:
DEFAULT IS BLACK IDE HDR.
FOR WHITE IDE HDR, USE IPN A22253-001
GPIO_DMA66_DETECT_PRI
IDE_PRI_ACT*
R8J3
1 2
15KCH5% 402
D
72
OUT
74
OUT
C
B
A
DESIGN NOTE: DATA LINES SHOULD BE MATCHED TO STROBES (XDIOR*, XIORDY*) WITHIN +/-250MIL STROBES SHOULD BE MATCHED TO THEIR COMPLEMENT WITHIN +/-10MIL
A
[PAGE_TITLE=IDE_SOUTH_BRIDGE]
DOCUMENT NUMBER PAGE REV
C77862
44
4.0
PCI IDE
8 7
INTEL
CONFIDENTIAL
45
36
2 1
<XR_PAGE_TITLE>
CAD NOTE:
OVERLAPPING FOOTPRINTS DO NOT CHANGE TO 402
D
38
38
USB_BACK3*
BI
USB_BACK3
BI
C
38
38
USB_BACK4*
BI
USB_BACK4
BI
R5A6
1 2
0 1A
EMPTY
603
L5B3
90OHM
IND 4PIN
1
2 3
752402-009
R5A7
1 2
1A0
EMPTY
603
603
L5B4
90OHM
IND 4PIN
1
2 3
752402-009
R5A8
1 2
IND
4
603
1A0
EMPTY
1 2
0
IND
R5A9
EMPTY
4
USB_BACK3_R
USB_BACK4_R*
USB_BACK4_R
1A
USB_BACK3_R*
USB_BACK3_R
USB_BACK4_R*
USB_BACK4_R
91,106
IN
106
BI
106
106
BI
106
BI
106
BI
106
BI
BI
106
BI
106
BI
28 7 6 5 4 3 1
DOUBLE STACK USB
VREG_USB_BP_RIGHT
USB_BACK4_R* USB_BACK4_R
USB_BACK3_R* USB_BACK3_R
1 2 3 4
5 6 7 8
J5A2
2 X USB
D
9
10
11
12
EMPTY
C
B
A
B
A
[PAGE_TITLE=USB_BACKPANEL_CONN]
DOCUMENT NUMBER PAGE REV
C77862
45
4.0
8 7
INTEL
CONFIDENTIAL
45
36
2 1
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
D
USB FRONT PANEL HEADER #2
UN-STUFF BYPASS RESISTORS
CAD NOTE:
OVERLAPPING FOOTPRINTS DO NOT CHANGE TO 402
C
38
38
USB_FRONT3*
BI
USB_FRONT3
BI
DO NOT CHANGE TO 402
R9H14
1 2
1A0 CH
603
L9H2
90OHM
2 3
1
IND 4PIN
752402-009
R9H15
1 2
0 1A
CH
603
EMPTY
USB_FRONT3_INDUCTOR*
USB_FRONT3_INDUCTOR
4
B
IN
USB_FRONT34_PWR
47
AND STUFF INDUCTORS ONLY FOR EMI QUALITY ISSUES
FRONT PANEL HEADER2
J9H2
2X5HDR_9
1 2 3 4 5 6 7 8
HDR
2
C9H7
470PF 10% 50V
1
X7R 603
0 1A
805
STUFF FOR FUSE ON FRONT PANEL SUPPORT
R9H9
12
0 1A
805
CH
STUFF FOR FUSE ON MB FRONT PANEL SUPPORT
R9H16
10
EMPTY
USB_OC_FRONT34
12
USB_OC_FRONT34_R*
USB_FRONT4_INDUCTOR*
USB_FRONT4_INDUCTOR
CAD NOTE:
OVERLAPPING FOOTPRINTS
DO NOT CHANGE TO 402
R9J1
1
0
FRONT PANEL
5%
SUPPORT
EMPTY
2
402
OUT
R9H12
1 2
603
L9H1
90OHM
IND 4PIN
1
2 3
752402-009
R9H13
1 2
603
DO NOT CHANGE TO 402
STUFF FOR OPT-P10-GND
47
1A0
CH
EMPTY
4
1A0 CH
USB_FRONT4*
USB_FRONT4
38
BI
38
BI
C
B
A
A
[PAGE_TITLE=USB_FP #2 HEADER]
DOCUMENT NUMBER PAGE REV
C77862
46
4.0
8 7
INTEL
CONFIDENTIAL
45
36
2 1
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
POWER FOR USB FRONT PANEL #1
D
DESIGN NOTE:
STUFFING THERMISTOR ASSUMES FRONT PANEL CARD HAS NO FUSE & DOES NOT PROVIDE OC PROTECTION
R9J3
1
15K 5%
2
CH 402
R9J2
1
10K 5%
2
CH
C
IN
USB_OC_FRONT12_R*
48
402
USB_OC_FRONT12*
38
OUT
85,91,93,94
5VDUAL USB_FRONT12_PWR
IN
1.50
RT9G1
THRMSTR
657448-004
R9G20
8050EMPTY
R9G26
0
805
12
EMPTY
1A
1A
12
12
BOM NOTE:
STUFF FOR PRODUCT WITH FUSE ON FRONT PANEL
48
1
R9G24
1
10K 5%
2
CH 402
C9H2
470UF 20% 10V ALUM
2
RDL
"202008-016"
CAD NOTE:
PLACE DECOUPLING AS CLOSE AS POSSIBLE
TO USB CONNECTOR
OUT
D
C
POWER FOR USB FRONT PANEL #2
B
DESIGN NOTE:
STUFFING THERMISTOR ASSUMES FRONT PANEL CARD HAS NO FUSE & DOES NOT PROVIDE OC PROTECTION
2
R9H11
15K
46
IN
USB_OC_FRONT34_R*
5% CH
402
1
R9H10
1
10K 5%
2
CH 402
USB_OC_FRONT34_BACK56*
38
OUT
5VDUAL
85,91,93,94
IN
A
1.50
RT9H1
657448-004
0
0
805
THRMSTR
R9H2
R9H6
12
EMPTY805
EMPTY
1
R9H7
1
10K 5%
2
CH
12
1A
BOM NOTE:
12
PRODUCT WITH FUSE ON FRONT PANEL
1A
402
C9H5
470UF 20% 10V ALUM
2
RDL
"202008-016"
CAD NOTE:
PLACE DECOUPLING AS CLOSE AS POSSIBLE TO USB CONNECTOR
USB_FRONT34_PWR
46
OUT
B
A
[PAGE_TITLE=USB_FP_HEADER_POWER]
DOCUMENT NUMBER PAGE REV
C77862
47
4.0
8 7
INTEL
CONFIDENTIAL
45
36
2 1
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
D
USB FRONT PANEL HEADER #1
CAD NOTE:
OVERLAPPING FOOTPRINTS
C
38
38
USB_FRONT2*
BI
USB_FRONT2
BI
B
DO NOT CHANGE TO 402
DO NOT CHANGE TO 402
R9G7
1 2
0CH1A
603
L9G1
90OHM
IND 4PIN
2 3
1
EMPTY
752402-009
R9G8
1 2
0 1A
CH
603
USB_FRONT2_INDUCTOR*
USB_FRONT2_INDUCTOR
4
FRONT PANEL HEADER1
J9G3
2X5HDR_9
1 2 3 4 5 6 7 8
2
1
C9G9
470PF
10%
50V
X7R
603
STUFF FOR FUSE ON FRONT PANEL SUPPORT
10
HDR
R9G12
0
805 EMPTY
USB_FRONT1_INDUCTOR*
USB_FRONT1_INDUCTOR
NET_USB_FNT_P10
12
1A
1
2
R9G1
0 5%
EMPTY 402
CAD NOTE:
OVERLAPPING FOOTPRINTS
DO NOT CHANGE TO 402
4
DO NOT CHANGE TO 402
STUFF FOR CUSTOMER FUSED (OPT-P10-GND) FRONT PANEL SUPPORT ONLY
R9G14
1 2
0 1A
603
L9G2
90OHM
IND 4PIN
R9G13
1 2
0 1A
603
C
CH
1
USB_FRONT1*
USB_FRONT1
23
EMPTY
CH
38
BI
38
BI
B
R9G10
IN
USB_FRONT12_PWR
47
A
0
805
STUFF FOR FUSE ON MB SUPPORT
12
1A CH
USB_OC_FRONT12_R*
47
OUT
A
[PAGE_TITLE=USB_FP_HEADER #1]
DOCUMENT NUMBER PAGE REV
C77862
48
4.0
8 7
INTEL
CONFIDENTIAL
45
36
2 1
D
C
B
32,39,50,51,56,74,79
32,39,50,51,56,74
A
<XR_PAGE_TITLE>
50,81
37,50,54,105
37,50,54,105
37,50,54,105
SMB_CLK_RESUME
BI
SMB_DATA_RESUME
BI
28 7 6 5 4 3 1
BACK PANEL SLOT 6
PCI SLOT 1
(CLOSEST TO CPU)
VCC3 VCC +12V -12V VCC VCC3
32,50,51,56..59,90
37,50,54 37,50,54
37,50,105
37
37,50,57,105
37,50,105
37,50,105
37,50,105
V_3P3_PCIVAUX
IN
A1
TRST*
A2
P12V_1
A3
TMS
A4
TDI
A5
P5V_2
P_INTF*
OUT OUT
R8B11
12
SERIRQ
OUT
P_PCIRST*
IN
P_GNT1*
IN
P_PME*
OUT
5%
0
EMPTY402
SERIRQ_PCI1
TP_PCI1_A9
VCC3
R8D3
1
5.6K 5%
CH
2
402
P_FRAME*
BI
P_TRDY*
BI
P_STOP*
BI
P_PAR
BI
R8D6
1 2
5%0 EMPTY
402
1 2
0
402
R8D5
5%
EMPTY
R8D4
1
5.6K 5%
CH
2
402
I_SMB_CLK_RES I_SMB_DATA_RES
0
P_C/BE*0
VCC
RP8E1D
BI
BI
P_AD[31..0]
P_C/BE*[3..0]
4 5
2.7K SM
REQ64A*
.063WIC5%
A6
INTA*
A7
INTC*
A8
P5V_3
A9
RSVD1
A10
P5V_4
A11
RSVD3
A12
GND10
A13
GND16
A14
3.3VAUX
A15
RST*
A16
P5V_6
A17
GNT*
A18
GND5
A19
PME
A20
30
P_AD30
28
P_AD28
26
P_AD26 P_AD27
24
P_AD24
16
P_AD16
22
P_AD22
20
P_AD20 P_AD21
18
P_AD18
16
P_AD16
15
P_AD15
13
P_AD13
11
P_AD11 P_AD12
9
P_AD9
6
P_AD6
4
P_AD4 P_AD5
2
P_AD2
0
P_AD0
AD30
A21
P3_3V
A22
AD28
A23
AD26
A24
GND6
A25
AD24
A26
IDSEL
A27
P3_3V
A28
AD22
A29
AD20
A30
GND9
A31
AD18
A32
AD16
A33
P3_3V
A34
FRAME*
A35
GND13
A36
TRDY*
A37
GND22
A38
STOP*
A39
P3_3V
A40
SMB_CLK
A41
SMB_DAT
A42
GND25
A43
PAR
A44
AD15
A45
P3_3V
A46
AD13
A47
AD11
A48
GND17
A49
AD09 KEY KEY
A52
C_BE0*
A53
P3_3V
A54
AD06
A55
AD04
A56
GND21
A57
AD02
A58
AD00
A59
P5V_8
A60 A61
P5V_12
A62
NC=1,2
P5V_10
J7B1
PCI CONN2_2
B50
A50
B51
A51
ACK64*REQ64*
P5V_9
M12V_1
GND1
P5V_0 P5V_1 INTB* INTD*
PRST1*
RSVD2
PRST2*
GND2 GND3
RSVD5
GND4
GND7 REQ*
P5V_11
AD31 AD29 GND8 AD27 AD25
P3_3V
C_BE3*
AD23
GND12
AD21 AD19
P3_3V
AD17
C_BE2*
GND14 IRDY* P3_3V
DEVSL*
GND15 LOCK* PERR* P3_3V SERR* P3_3V
C_BE1*
AD14
GND23
AD12
AD10 GND24 KEY KEY
AD08
AD07 P3_3V
AD05
AD03 GND19
AD01
P5V_5 P5V_7
TCK
TDO
CLK
CONN
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
TP_PCI1_B4
TP_PCI1_B9 TP_PCI1_B10 TP_PCI1_B11
TP_PCI1_B14
31
P_AD31
29
P_AD29
27 25
P_AD25
23
P_AD23
21 19
P_AD19
17
P_AD17
14
P_AD14
12 10
P_AD10
8
P_AD8
7
P_AD7
5 3
P_AD3
1
P_AD1
3
P_C/BE*3
2
P_C/BE*2
1
P_C/BE*1
VCC
VCC
C7C4
12
20%
.1UF
25V Y5V 603
C8C3
100UF
1 2
20%
25V
ELEC
RDL
P_INTG*P_INTH* P_INTE*
CK_P_33M_S1
P_REQ1*
P_IRDY*
P_DEVSEL*
P_PLOCK* P_PERR*
P_SERR*
TP_RP8_1 TP_RP8_8
50
IN
ACK64*
VCC3
VCC3
C8D9
470UF
1 2
20% 10V
ALUM
RDL
.1UF 20% EMPTY
OUT OUT
IN
OUT
BI
BI
BI
OUT
OUT
RP8E1A
1 8
6 3
SM
C7D6
25V 603
29
ICSM
RP8E1C
VCC3
C7C10
12
.1UF
20% 25V Y5V 603
VCC3
C7C7
12
37,50,54 37,50,54
37,54
37,50,54,105
37,50,54,105
37,50,54
37,50,54,105
37,50,54,105
12
20%
.1UF
25V Y5V 603
D
C
B
.063W2.7K 5%
VCC
.063W2.7KIC5%
A
8 7
[PAGE_TITLE=PCI_CONN_1]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
49
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
BACK PANEL SLOT 5
PCI SLOT 2
D
V_3P3_PCIVAUX
32,49,51,56..59,90
IN
37,49,54 37,49,54
49,81
C
B
32,39,49,51,56,74,79 32,39,49,51,56,74
37,49,57,105
37,49,54,105
37,49,54,105
37,49,54,105
37,49,105
P_INTG*
OUT
P_INTE* P_INTF*
OUT
R8B12
12
5%
0
EMPTY402
37,49,105
37
OUT
IN
IN
OUT
BI
BI
BI
BI BI
BI
SERIRQ
P_PCIRST*
P_GNT2*
P_PME*
P_FRAME*
P_TRDY*
P_STOP*
SMB_CLK_RESUME SMB_DATA_RESUME
P_PAR
VCC
RP8E1B
2 7
SM5%IC
A
37,49,105
37,49,105
P_AD[31..0]
BI
P_C/BE*[3..0]
BI
REQ64B*
.063W2.7K
VCC3 VCC +12V -12V VCC VCC3
A1
TRST*
A2
P12V_1
A3
TMS
A4
TDI
A5
P5V_2
A6
INTA*
A7
INTC*
A8
P5V_3
TP_PCI2_A9
SERIRQ_PCI2
0
P_C/BE*0
A9
RSVD1
A10
P5V_4
A11
RSVD3
A12
GND10
A13
GND16
A14
3.3VAUX
A15
RST*
A16
P5V_6
A17
GNT*
A18
GND5
A19
PME
A20
30
P_AD30
28
P_AD28
26
P_AD26 P_AD27
24
P_AD24
17
P_AD17
22
P_AD22
20
P_AD20 P_AD21
18
P_AD18
16
P_AD16
15
P_AD15
13
P_AD13
11
P_AD11 P_AD12
9
P_AD9
6
P_AD6
4
P_AD4 P_AD5
2
P_AD2
0
P_AD0
AD30
A21
P3_3V
A22
AD28
A23
AD26
A24
GND6
A25
AD24
A26
IDSEL
A27
P3_3V
A28
AD22
A29
AD20
A30
GND9
A31
AD18
A32
AD16
A33
P3_3V
A34
FRAME*
A35
GND13
A36
TRDY*
A37
GND22
A38
STOP*
A39
P3_3V
A40
SMB_CLK
A41
SMB_DAT
A42
GND25
A43
PAR
A44
AD15
A45
P3_3V
A46
AD13
A47
AD11
A48
GND17
A49
AD09 KEY KEY
A52
C_BE0*
A53
P3_3V
A54
AD06
A55
AD04
A56
GND21
A57
AD02
A58
AD00
A59
P5V_8
A60 A61
P5V_12
A62
P5V_10
J8B1
PCI CONN2_2
B50
A50
B51
A51
ACK64*REQ64*
P5V_9
M12V_1
GND1
P5V_0 P5V_1 INTB* INTD*
PRST1*
RSVD2
PRST2*
GND2 GND3
RSVD5
GND4
GND7 REQ*
P5V_11
AD31 AD29 GND8 AD27 AD25
P3_3V
C_BE3*
AD23
GND12
AD21 AD19
P3_3V
AD17
C_BE2*
GND14 IRDY* P3_3V
DEVSL*
GND15 LOCK* PERR* P3_3V SERR* P3_3V
C_BE1*
AD14
GND23
AD12
AD10 GND24 KEY KEY
AD08
AD07 P3_3V
AD05
AD03 GND19
AD01
P5V_5 P5V_7
TCK
TDO
CLK
CONN
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
TP_PCI2_B4
TP_PCI2_B9 TP_PCI2_B10 TP_PCI2_B11
TP_PCI2_B14
31
P_AD31
29
P_AD29
27 25
P_AD25
23
P_AD23
21 19
P_AD19
17
P_AD17
14
P_AD14
12 10
P_AD10
8
P_AD8
7
P_AD7
5 3
P_AD3
1
P_AD1
732431-002NC=1,2
3
P_C/BE*3
2
P_C/BE*2
1
P_C/BE*1
VCC3 VCC
C8D5
12
.1UF
20%
25V
EMPTY
603
VCC
C8B10
12
.1UF 20%
25V
EMPTY
603
CK_P_33M_S2
C8E1
100UF
1 2
20%
ELEC RDL
P_INTH*
P_REQ2*
P_IRDY*
P_DEVSEL*
P_PLOCK* P_PERR*
P_SERR*
ACK64*
20%.1UF
20%
37,49,54 37,49,54
12
12
37,49,54
37,49,54,105
37,49,54,105
37,49,54,105
37,49,54,105
VCC3
VCC3
C8D8
470UF
1 2
ALUM
RDL
C8D4
EMPTY
10V20%
D
12
20%.1UF
25V 603
C
B
VCC3
C8C5
25V
25V
EMPTY
603
VCC3
C8D10
.1UF
25V Y5V 603
OUT OUT
29
IN
37,54
OUT
BI
BI
BI
OUT
OUT
49
OUT
A
8 7
[PAGE_TITLE=PCI_CONN_2]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
50
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
D
BACK PANEL SLOT 4
PCI EXPRESS X1 SLOT 1
BOM NOTE: USE C55845-001
C
FOR X1 CONN
+12V
J9C3
3GIO_X1
B1 B2
32,39,49,50,56,74,79
32,39,49,50,56,74
32,49,50,56..59,90
32,40,43,56
B
38 38
BI
BI
IN OUT
IN IN
SMB_CLK_RESUME
SMB_DATA_RESUME
VCC3
V_3P3_PCIVAUX
WAKE*
HSO_P0_C HSO_N0_C
TP_PCIE_JTAG1_BP_1
TP_PCIE_RSVD_B12_1
TP_PCIE_PRSNT_B16_1
B3 B4 B5 B6 B7 B8
B9 B10 B11
B12 B13 B14 B15 B16 B17 B18
1.0
12V PRSNT1* 12V 12V GND SMCLK SMDAT GND
3.3V JTAG1
3.3VAUX WAKE*
RSVD GND HSOP0 HSON0 GND PRSNT2* GND
KEY
1 OF 1
JTAG2 JTAG3 JTAG4 JTAG5
PWRGD
REFCLK+ REFCLK-
HSIP0 HSIN0
12V
3.3V
3.3V
12V
GND
GND
GND
GND
CONN
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
A12 A13 A14 A15 A16 A17 A18
TP_PCIE_PRSNT_A1_1
TP_PCIE_JTAG2_1 TP_PCIE_JTAG3_1 TP_PCIE_JTAG4_1 TP_PCIE_JTAG5_1
P_RST_SLOTS*
CK_PE_100M_X1_1 CK_PE_100M_X1_1*
HSI_P0 HSI_N0
+12V VCC3
IN
IN IN
OUT OUT
32,74
30 30
38 38
VCC3
.1UF
C9B16
12
20% 25V Y5V 603
C
B
A
A
[ TITLE=PCIE_X1_CONN_2]
DOCUMENT NUMBER PAGE REV
C77862
51
4.0
8 7
INTEL
CONFIDENTIAL
45
36
2 1
28 7 6 5 4 3 1
D
D
BACK PANEL SLOT 3
PCI EXPRESS X1 SLOT 2
BOM NOTE: USE C55845-001
FOR X1 CONN
C
32,39,49..51,53,56,74,79
32,39,49..51,53,56,74
32,49..51,53,56..59,90,99
32,40,43,51,56
38
B
38
BI
BI
IN
OUT
IN IN
SMB_CLK_RESUME
SMB_DATA_RESUME
VCC3
V_3P3_PCIVAUX
WAKE*
HSO_P2_C HSO_N2_C
+12V
B1
12V PRSNT1*
B2
12V
B3
12V
B4
GND
B5
SMCLK
B6
SMDAT
B7
GND
B8
3.3V
B9
JTAG1
B10
3.3VAUX
B11
WAKE*
B12
RSVD
B13
GND
B14
HSOP0
B15
HSON0
B16
GND
B17
PRSNT2*
B18
GND
J8C5
3GIO_X1
1.0
KEY
1 OF 1
JTAG2 JTAG3 JTAG4 JTAG5
PWRGD
REFCLK+ REFCLK-
HSIP0 HSIN0
12V
3.3V
3.3V
12V
GND
GND
GND
GND
CONN
+12V
VCC3
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
A12 A13 A14 A15 A16 A17 A18
P_RST_SLOTS*
CK_PE_100M_X1_2 CK_PE_100M_X1_2*
HSI_P2 HSI_N2
VCC3
C10A4
20%
.1UF
25V Y5V 603
32,51,74
IN
30
IN
30
IN
38
OUT
38
OUT
+12V
C11A1
100UF
12
1 2
20% 25V
ELEC
RDL
C
B
A
DOCUMENT NUMBER PAGE REV
C77862
52
8 7
INTEL
CONFIDENTIAL
45
36
2 1
A
4.0
28 7 6 5 4 3 1
D
C
B
32,39,49..52,56,74,79
32,39,49..52,56,74
A
99 99
37,54,99 37,54,105
37,49,50,57,99,105
37,49,50,54,99,105
37,49,50,54,99,105
37,49,50,54,99,105
BI BI
37,49,50,99,105
SMB_CLK_RESUME
BI
SMB_DATA_RESUME
BI
37,49,50,99,105
37,49,50,99,105
32,49..52,56..59,90,99
IN
OUT OUT
37,49,50,99,105
IN
37
IN
OUT
BI
BI
BI
P_SMB_CLK_SLOT34 P_SMB_DATA_SLOT34
BI
BI
BI
V_3P3_PCIVAUX
P_PCIRST*
P_GNT3* P_PME*
P_FRAME*
P_TRDY*
P_STOP*
P_PAR
R10D1
1 2
5%0 EMPTY
402
VCC
P_AD[31..0]
P_C/BE*[3..0]
P_INTC*
P_INTB*
R10D3
1 2
0
402
R10E3
1 2
2.7K 5%
402 CH
BACK PANEL SLOT 2
PCI SLOT3
VCC3
VCC3
R10D2
1
5.6K 5%
CH
2
402
5%
EMPTY
R10D4
1
5.6K 5%
CH
2
402
REQ64C*
+12V
VCC
A1
TRST*
A2
P12V_1
A3
TMS
A4
TDI
A5
P5V_2
A6
INTA*
A7
INTC*
A8
P5V_3
A9
RSVD1
A10
P5V_4
A11
RSVD3
A12
GND10
A13
GND16
A14
3.3VAUX
A15
RST*
A16
P5V_6
A17
GNT*
A18
GND5
A19
PME
A20
30
P_AD30
28
P_AD28
P_AD26
24
P_AD24
16
P_AD16
22
P_AD22
20
P_AD20
18
P_AD18
16
P_AD16
15
P_AD15
13
P_AD13
11
P_AD11
9
P_AD9
0
P_C/BE*0
6
P_AD6
4
P_AD4
2
P_AD2
0
P_AD0
AD30
A21
P3_3V
A22
AD28
A23
AD26
A24
GND6
A25
AD24
A26
IDSEL
A27
P3_3V
A28
AD22
A29
AD20
A30
GND9
A31
AD18
A32
AD16
A33
P3_3V
A34
FRAME*
A35
GND13
A36
TRDY*
A37
GND22
A38
STOP*
A39
P3_3V
A40
SMB_CLK
A41
SMB_DAT
A42
GND25
A43
PAR
A44
AD15
A45
P3_3V
A46
AD13
A47
AD11
A48
GND17
A49
AD09 KEY KEY
A52
C_BE0*
A53
P3_3V
A54
AD06
A55
AD04
A56
GND21
A57
AD02
A58
AD00
A59
P5V_8
A60 A61
P5V_12
A62
P5V_10
J10B1
PCI CONN2_2
B50
A50
B51
A51
ACK64*REQ64*
P5V_9
M12V_1
GND1
P5V_0 P5V_1 INTB* INTD*
PRST1*
RSVD2
PRST2*
GND2 GND3
RSVD5
GND4
GND7 REQ*
P5V_11
AD31 AD29 GND8 AD27 AD25
P3_3V
C_BE3*
AD23
GND12
AD21 AD19
P3_3V
AD17
C_BE2*
GND14 IRDY* P3_3V
DEVSL*
GND15 LOCK* PERR* P3_3V SERR* P3_3V
C_BE1*
AD14
GND23
AD12
AD10 GND24 KEY KEY
AD08
AD07 P3_3V
AD05
AD03 GND19
AD01
P5V_5 P5V_7
CONN
TCK
TDO
CLK
VCC
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
VCC3-12V
31
P_AD31
29
P_AD29
2726
P_AD27
25
P_AD25
3
23
21 19
17
14
12 10
8 7
5 3
1
P_C/BE*3
P_AD23
P_AD21
P_AD19
P_AD17
2
P_C/BE*2
1
P_C/BE*1
P_AD14
P_AD12
P_AD10
P_AD8
P_AD7
P_AD5
P_AD3
P_AD1
VCC
VCC
C10B3
12
20%
.1UF
25V Y5V 603
C11E1
100UF
1 2
20%
25V
ELEC
RDL
P_INTD* P_INTA*
CK_P_33M_S3
P_REQ3*
P_IRDY*
P_DEVSEL*
P_PLOCK* P_PERR*
P_SERR*
VCC3
VCC3
C11D2
470UF
1 2
20% 10V
ALUM
RDL
C10C1
12
.1UF 20%
25V
EMPTY
603
OUT OUT
29
IN
37,54
OUT
BI
BI
BI
OUT
OUT
37,54,99 37,54
37,49,50,54,99
VCC3
VCC3
37,49,50,54,99,105
37,49,50,54,99,105
37,49,50,54,99,105
37,49,50,54,99,105
C10D1
12
.1UF
20% 25V Y5V 603
C10D3
12
20%
.1UF
25V Y5V 603
D
C
B
A
NC=1,2
49,50,99
ACK64*
IN
8 7
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
53
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
VCC
PCI PULL-UPS
R9D8
37,49,50,105
D
37,49,50,105
37,49,50,105
37,49,50
37,49,50,105
P_SERR*
OUT
R9D4
P_DEVSEL*
OUT
P_IRDY*
OUT
P_PLOCK*
OUT
P_PERR*
OUT
R9D6
2.7K
2.7K 402 CH
12
5% CH402
5%
12
2.7K 5%
R9D7
12
5%
2.7K CH402
R9D2
12
5%
2.7K CH402
D
12
CH402
C
B
37
A
37,105
37
37
37,49,50
37,49,50
37,49,50
37,49,50
P_INTA*
OUT
P_INTB*
OUT
P_INTC*
OUT
P_INTD*
OUT
P_INTE*
OUT
P_INTF*
OUT
P_INTG*
OUT
P_INTH*
OUT
3 6
8.2K
4 5
8.2K
2 7
8.2K SM IC
1 8
8.2K
[MODULE=ICH] [PAGE_TITLE=ICH_PCI_TERMINATION]
8 7
RP9C1C
RP9C1D
RP8B2B
RP8B2A
C
R9D1
37,49,50,105
37,49,50,105
37,49,50,105
37
37
37,50
37,49
37,105
37
VCC3
RP9C1A
1 8
5%8.2K
.063W
IC
SM
.063W5%
ICSM
ICSM
ICSM
RP9C1B
2 7
5%
8.2K SM
.063W5%
8.2K SM
.063W5%
8.2K SM IC
.063W5%
RP8B2D
4 5
RP8B2C
3 6
.063W
IC
5%
.063W
IC
5% .063W
37
P_FRAME*
OUT
P_TRDY*
OUT
P_STOP*
OUT
P_REQ4*
OUT
P_REQ3*
OUT
P_REQ2*
OUT
P_REQ1*
OUT
P_REQ0*
OUT
P_REQ6*
OUT
P_REQ5*
OUT
CONFIDENTIAL
45
36
12
5%
2.7K CH
402
1 8
2.7K SM
4 5
SM
2.7K 5%
2.7K 402
INTEL
R9D5
RP8C1A
RP8C1D
R8E1
R8E2
12
5%2.7K CH402
5%
.063W
IC
5%2.7K
.063W
IC
12
CH402
12
5% CH
R9D3
2.7K 402 CH
RP8C1B
2 7
2.7K SM
RP8C1C
3 6
2.7K 5% .063W SM
R8E3
2.7K
402 CH
DOCUMENT NUMBER PAGE REV
C77862
2 1
12
5%
.063W5%
IC
B
IC
12
5%
A
54
4.0
<XR_PAGE_TITLE>
73,74
LAN_DISABLE*
IN
D
2
1
SMC0402
C8B4
.1UF 20% 16V EMPTY 402
BOM NOTE:
STUFF FOR NWY (A0) EMPTY FOR KINNERETH & B0 NWY
28 7 6 5 4 3 1
D
C
PLTRST*
15,37,56,70,72,73
IN
BOM NOTE:
EMPTY FOR NWY AND KINNERETH STUFF FOR BO NWY
LAN_DISABLE*
73,74
B
IN
R8B6
1 2
0 5%
402 EMPTY
2
C8A19
.1UF 20% 16V
1
EMPTY 402
LAN_DISABLE_NC*
BOM NOTE:
STUFF FOR NWY EMPTY FOR KINNERETH
56
OUT
A
8 7
DESIGN NOTE:
DEFAULT: EMPTY FOR NORTHWAY STUFF FOR KINNERETH
29,38..41,43,56,73,74,79,87,88,90,92,93,95,105,106
IN
LAN_DISABLE*
73,74
IN
V_3P3_STBY
R9F8
1 2
3.3K 5%
402 CH
LAN_KIN_CNTRL_XSTR
R9F7
1 2
470 5%
402 CH
SOT23
1
LAN_KIN_CNTRL
3
Q9F1
MMBT3904 XSTR
2
108969-001
CAD NOTE:
PLACE NEAR ICH
OUT
56
[PAGE_TITLE=BLANK]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
55
C
B
A
4.0
<XR_PAGE_TITLE>
D
BOM NOTE:
STUFF FOR NWY EMPTY FOR KINNERETH
C
B
CAD NOTE:
DEBUG PAD TRACES NEED TO BE ROUTED LIKE THE MDI LINE GOING TO THE RJ45 CONNECTOR
A
BOM NOTE:
STUFF FOR NWY EMPTY FOR KINNERETH
DB7A1
EMPTY
40
OUT
40
OUT
40
OUT
40
IN
40
IN
40
IN
40
OUT
40
IN
8 7
32,49..51,57..59,90
IN
40
OUT
OUT
IN
IN
IN
DEBUG_PAD_C30
EMPTY
ICH_LAN_JRX0
ICH_LAN_JRX1
ICH_LAN_JRX2
ICH_LAN_JRST
ICH_LAN_JTX2
ICH_LAN_JTX1
ICH_LAN_JCLK
ICH_LAN_JTX0
BOM NOTE:
V_3P3_PCIVAUX
LAN_NW_CE*
DEBUG_PAD_C30
DB7A2
EMPTY
DEBUG_PAD_C30
DB8A2
I92
I93
I94
1 2
0 5%
402 CH
1 2
0 5%
402 CH
1 2
0 5%
402 CH
1 2
22 5%
402 CH
1 2
0 5%
402 CH
2
1
R7A23
1 2
1.4K 1%
402 EMPTY
DEBUG_PAD_C30
DB8A1
EMPTY
LAN_NW_S0
LAN_NW_CE*
LAN_NW_SI
R7A26
LAN_NW_SK
R7B1
LAN_NW_ATEST_2P
R7A25
LAN_NW_ATEST_2N
R7A22
LAN_NW_RCMP_1N
R7A24
LAN_NW_RCMP_1P
EMPTY FOR NWY STUFF FOR KINNERETH
SMR0402
R8B5
1K 5%
EMPTY 402
V_3P3_PCIVAUX
32,49..51,57..59,90
IN
BOM NOTE:
STUFF FOR NWY EMPTY FOR KINNERETH
32,49..51,57..59,90
IN
32,39,49..51,74,79
1K 5%
402 EMPTY
V_3P3_PCIVAUX
40
IN
40
IN
40
IN
OUT
OUT
OUT
IN
OUT
HSI_P1_C
38
OUT
HSI_N1_C
38
OUT
HSO_P1_C
38
IN
HSO_N1_C
38
IN
32,40,43,51
15,37,56,70,72,73
32,39,49..51,74
58
CK_PE_100M_LAN
BI
CK_PE_100M_LAN*
BI
WAKE*
OUT
PLTRST*
IN
SMB_DATA_RESUME
IN
SMB_CLK_RESUME
BI
SMB_ALERT_LAN_PU
IN
LAN_NW_EEDI
OUT
LAN_NW_EEDO
IN
LAN_NW_EECS*
OUT
LAN_NW_EESK
OUT
LAN_NW_S0
OUT
LAN_NW_SI
OUT
LAN_NW_SK
IN
LAN_NW_ATEST_2P
IN
LAN_NW_ATEST_2N
IN
LAN_NW_RCMP_1N LAN_NW_RCMP_1P
LAN_NW_ATEST_0P LAN_NW_ATEST_0N
LAN_NW_ATEST_3P LAN_NW_ATEST_3N
LAN_NW_AUXPWR
LAN_DISABLE_R*
TP_ICH_RSMRST_R* TP_LAN_DEV_DISABLE*
LAN_NW_A2
R8A2
1 2
0 5%
603 EMPTY
TP_NWY_M8 TP_NWY_M9
TP_NWY_B6 TP_NWY_B5 TP_NWY_B4 TP_NWY_A4 TP_NWY_C3
TP_NWY_A8 TP_NWY_B8 TP_NWY_C8 TP_NWY_C7
TP_NWY_B1 TP_NWY_B2
R8A3
1 2
30 30
58
58 58
40
40
R8A5
1 2
0 5%
402 EMPTY
VCC3
DEFAULT LAN IS NORTHWAY (GBE)
OPTION IS FOR KINNERETH_R/KINNERETH_R+ (10/100)
D1
C1 G1
F1
J1
H1
P10
P7
M11
P11
N11
M8
M9
A9
B9
B10
C9
P13
N13 M12
M13
L14
L13
N14 M14
B14
B13
L1
K1
C6
A5 P5
A6
B6
B5 B4
A4
C3 A2
A8 B8
C8
C7
B1 B2
PE_TXP PE_TXN PE_RXP PE_RXN
PE_CLKP PE_CLKN
PE_WAKE* PE_RST*
SMB_DATA SMB_CLK SMB_ALRT*
FLB_SD FLB_INTEX
EEDI EED0 EECS* EESK
FLSH_S0 FLSH_CE* FLSH_SI FLSH_SK
RSVD RSVD
RSVD RSVD
IEEE_TEST_P IEEE_TEST*
RSVD RSVD
AUX_PRSNT LAN_DSBL* LAN_PWRGD DEV_DISBL*
RSVD RSVD RSVD RSVD RSVD RSVD SDP0_0 SDP0_1 SDP0_2 SDP0_3
RSVD RSVD
R8A19
1 2
1K 5%
402 EMPTY
KINNERETH-R
SMB_ALERT_LAN_PU
U8A1B
3.0
BGA196
MDI_0P MDI_0N MDI_1P MDI_1N MDI_2P MDI_2N MDI_3P MDI_3N
XTAL_1 XTAL_2
LED_1* LED_0* LED_2* LED_3*
VCC33 VCC33
CTRL_1P0
VSS
CTRL_1P8
VSS
RCMP_PEN RCMP_PEP
RBIASP RBIASN
TEST
NC NC
NC RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
JTDI JTDO JTMS JTCK
DEV_OFF*
T_TESTP T_TESTN
RSVD_GND RSVD_GND
1 of 2
IC
BOM NOTE:
STUFF FOR NWY EMPTY FOR KINNERETH
OUT
45
C13
C14
E13 E14
F13 F14
H13
H14
K14 J14
C11 B11
A12 A10
N2 P2
P3 N3
M1
N1
J2 J3
B12 D11
A13
D10
D12 D14
N10 N9
M10
P9 M7
C5 C4
N7
P4
P6 N4
N5
L7
L3
L2
M5
M4
LAN_MDI0_P LAN_MDI0_N LAN_MDI1_P LAN_MDI1_N LAN_MDI2_P LAN_MDI2_N LAN_MDI3_P LAN_MDI3_N
LAN_X1 LAN_X2
LAN_LED_ACT
LAN_LED_1000
LAN_1P0_CTRL
LAN_1P8_CTRL
LAN_NW_RCMP_0N LAN_NW_RCMP_0P
LAN_NW_RBIAS LAN_NW_RBIAS_VSS
LAN_NW_STRAP1 LAN_NW_STRAP2 LAN_NW_STRAP3 LAN_NW_STRAP4
TP_NWY_N10 TP_NWY_N9 TP_NWY_M10 TP_NWY_P9 TP_NWY_M7 TP_NWY_C5 TP_NWY_C4 TP_NWY_N7
TP_NWY_P4 TP_NWY_P6 TP_NWY_N4
LAN_NWY_N5
LAN_DISABLE_NC*
TP_NWY_L3 TP_NWY_L2
V_3P3_PCIVAUX
R8A13
1 2
1K 5%
603 CH
R8B3
1 2
1K 5%
603 CH
36
V_3P3_PCIVAUX
IN
OUT
OUT
OUT
55
BI BI BI BI BI BI BI BI
IN
BI
BI
IN
59 59 59 59 59 59 59 59
58
58
59
59
32,49..51,57..59,90
58
58
IN
32,49..51,57..59,90
28 7 6 5 4 3 1
LAN_LED_10
LAN_LED_100
BOM NOTE:
STUFF FOR NWY EMPTY FOR KINNERETH
SMR0402
R8A16
1.4K 1%
BOM NOTE:
R7A6
R7A11
1 2
100 5%
402 CH
R7A10
1 2
100 5%
402 CH
R7A8
1 2
100 5%
402 CH
R7A9
1 2
100 5%
402 CH
LAN_NW_ATEST_0P
LAN_NW_ATEST_0N
BOM NOTE:
EMPTY FOR NWY STUFF FOR KINNERETH
STUFF FOR NWY EMPTY FOR KINNERETH
BOM NOTE:
STUFF FOR NWY EMPTY FOR KINNERETH
DOCUMENT NUMBER PAGE REV
R8A17
1 2
1K 5%
402 EMPTY
R7A3
1 2
549 1%
402 CH
R7A4
1 2
619 1%
402 CH
1 2
1K 5%
402 EMPTY
INTEL
CONFIDENTIAL
2 1
BI
BI
12
EMPTY402
LAN_KIN_CNTRL
C77862
59
59
SMR0402
R7A2
1.4K 1% 402
BOM NOTE:
EMPTY FOR NWY STUFF FOR KINNERETH
OUT
OUT
EMPTY
IN
D
12
C
B
55
A
56
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
BGA196
D
LEGEND WAKE ON LAN HEADER
41,66,74,78,81,86,90..95
37,49,50,105
C
IN
BI
Q8D2
MMBT3904
EMPTY
V_5P0_STBY
P_PME*
3
2
1
I_WOL_BJT_BASE
R8D9
1 2
10K 6035%EMPTY
OPT_WOL
OPT_WOL_E
R8D8
1 2
10K 5% 603
OPT_WOL
OPT_WOL
EMPTY
I_WOL_LENOVO
OPT_WOL
OPT_WOL
2
R8D7
100K 5%
EMPTY 603
1
WOL HEADER IS SHROUDED ON ONE SIDE
OPT_WOL
OPT_WOL
J8D1
1X3HDR
1 2 3
EMPTY
665515-003
32,49..51,56,58,59,90
58
58
ADD WOL HEADER CIRCUIT
58,59
B
58,59
IN
IN
IN
IN
IN
V_3P3_PCIVAUX
LAN_V_1P0
LAN_V_1P0
LAN_V_1P8
LAN_V_1P8
F12
G13 H12
G12
H11
J10
J11
K10
K11
L10
E11
E12 J12
K13 L12
P12
A11
A3
A7 D9
N6
N8 L4
E1
E3
G6 H6
H7 H8
J6 J7
J8 J9
K3
K4 K5
K6
K7 K8
K9
L5 L9
D3 G5
H5
J5
VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 NC
VCC10_PHY VCC10_PHY VCC10_PHY VCC10_CLK
VCC10_PE VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10 VCC10
VCC18_PHY VCC18_PHY VCC18_PHY VCC18_PHY VCC18_PHY VCC18_PHY VCC18_PHY
VCC18_PE VCC18_PE VCC18_PLL VCC18_PLL
U8A1A
KINNERETH-R
3.0
D
VSS
A1
VSS
A14
VSS
B3
VSS
B7
VSS
C2
VSS
C10
VSS
D2
VSS
D4
VSS
D5
VSS
D6
VSS
D7
VSS
D8
VSS
C12
VSS
D13
VSS
E2
VSS
E4
VSS
E5
VSS
E6
VSS
E7
VSS
E8
VSS
E9
VSS
E10
VSS
F2
VSS
F3
VSS
F4
VSS
F5
VSS
F6
VSS
F7
VSS
F8
VSS
F9
VSS
F10
VSS
F11
VSS
G2
VSS
G3
VSS
G4
VSS
G7
VSS
G8
VSS
G9
VSS
G10
VSS
G11
VSS
G14
VSS
H2
VSS
H3
VSS
H4
VSS
H9
VSS
H10
VSS
J4
VSS
J13
VSS
K2
VSS
K12
VSS
L6
VSS
L11
VSS
M6
VSS
N12
VSS
P1
VSS
P8
VSS
P14
C
B
NC
L8
NC
M2
NC
M3
A
8 7
45
36
2 of 2
IC
INTEL
DOCUMENT NUMBER PAGE REV
CONFIDENTIAL
2 1
C77862
A
4.0
57
28 7 6 5 4 3 1
BOM NOTE:
STUFF FOR NWY EMPTY FOR KINNERETH
D
LAN_1P0_CTRL
56
IN
IN
V_3P3_PCIVAUX
32,49..51,56,57,59,90
C
SMC0402
BOM NOTE:
STUFF FOR NWY EMPTY FOR KINNERETH
C8A16
6.3V EMPTY 402
20%1UF
SOT223
LAN_1P8_CTRL
56
B
IN
IN
V_3P3_PCIVAUX
32,49..51,56,57,59,90
0603 REQUIREMENT PER DESIGN ENGINEER
BOM NOTE:
EMPTY FOR NWY STUFF FOR KINNERETH
A
V_3P3_PCIVAUX
32,49..51,56,57,59,90
IN
N_C0805
2
1
N_C0805
2
C8A2
C7A6
4.7UF
4.7UF
20%
20%
10V
10V
1
Y5V
Y5V
805
805
DESIGN NOTE: DECOUPLING CAPS SHARE BETWEEN
KINNERETH-R AND NORTHWAY VOLTAGE NETS. SPECIFIC DESIGN MAY REQUIRE MORE DECOUPLING
8 7
2
1
2
1
N_C0805
C8B2
4.7UF 20% 10V EMPTY 805
N_C0805
C7A10
4.7UF
20% 10V Y5V 805
1
1 2
0 1A
603 CH
12
2
1
R7A19
2
1
SMC0402
C6A7
12
20%1UF
6.3V EMPTY 402
SOT223
2
4
Q7A1
1
PBSS5540Z EMPTY
3
N_C0805
2
C6A5
4.7UF 20% 10V
1
EMPTY 805
BOM NOTE:
EMPTY FOR NWY STUFF FOR KINNERETH
0603 REQUIREMENT PER DESIGN ENGINEER
R8A14
LAN_V_1P8_R1
1 2
2 5%
603 EMPTY
2
4
Q8A1
PBSS5540Z EMPTY
3
SMC0402
C8A20
.1UF 20% 16V EMPTY 402
LAN_V_1P0
SMC0402
SMC0402
2
C7A8
C7A14
.1UF
.1UF
20%
20%
16V
16V
1
Y5V
Y5V
402
402
SMC0402
2
C6A3
.1UF 20% 16V
1
EMPTY 402
V_3P3_PCIVAUX
32,49..51,56,57,59,90
IN
N_C0805
2
C8B1
4.7UF 20% 10V
1
Y5V 805
2
1
BI
SMC0402
2
C7A9
.1UF 20% 16V
1
Y5V 402
CAD NOTE: PLACE A 0.1UF CAP NEXT TO
EVERY 4.7 OR 10UF CAP.
SMC0402
C7A1
.1UF 20% 16V Y5V 402
2
1
2
1
57
SMC0402
C8A1
1000PF 10% 50V
CAD NOTE:
EMPTY 402
STUFF FOR NWY EMPTY FOR KINNERETH
LAN_V_1P0
LAN_V_1P8
SMC0402
C7A11
1000PF 10% 50V Y5V 402
R8A6
1 2
0 1A
603 CH
2
1
2
1
SMC0402
C8A18
.1UF 20% 16V Y5V 402
N_C0603
C7A2
22PF 20%
6.3V Y5V 603
32,49..51,56,57,59,90
OUT
VOLTAGE REGULATION - PHY
OUT
N_C0805
2
C8A5
4.7UF 20% 10V
1
Y5V 805
BOM NOTE:
STUFF FOR NWY EMPTY FOR KINNERETH
V_3P3_PCIVAUX
IN
N_C0805
2
C8A9
4.7UF 20% 10V
1
Y5V 805
57
57,59
LAN DECOUPLING
SMC0402
2
C8A13
.1UF 20% 16V
1
Y5V 402
NORTHWAY EEPROM
STUFF THIS EEPROM ONLY WITH NORTHWAY SKUS. PLACE NEAR LAN CONTROLLER. SEE LINK SHOWN BELOW FOR CORRECT P/N IMPLEMENTATION
HTTP://DPSD.INTEL.COM/LMM/LAN/DOCS/EEPROM.DOC
V_3P3_PCIVAUX
32,49..51,56,57,59,90
IN
LAN_NW_EECS*
56
IN
V_3P3_PCIVAUX
32,49..51,56,57,59,90
IN
V_3P3_PCIVAUX
32,49..51,56,57,59,90
IN
56
LAN_NW_EEDI
IN
56
LAN_NW_EESK
IN
56
LAN_NW_EEDO
OUT
1K 5%
402 EMPTY
R6B6
1 2
R6A1
1 2
1K 5%
402 EMPTY
LAN_WP*
LAN_HOLD*
1 3 7
5 6
C14313-001
SOI8
U6B1
AT25160
CS*
VCC WP* HOLD*
SO
SI SCK
GND
EMPTY
SMC0402
2
C6A4
.01UF 20% 16V
1
Y5V
8
402
2
4
D
C
SOI8
U8F1
40
40 40
40
ICH_EE_DIN
IN
ICH_EE_DOUT
OUT
ICH_EE_CS
IN
ICH_EE_CLK
IN
PLACEHOLDER: ICH/KINNERETH EEPROM
BOM NOTE:
EMPTY FOR NWY STUFF FOR KINNERETH
LAN CRYSTAL
45
36
LAN_X1
SMY49S
Y7B1
25.000MHZ
1 2
SM XTAL
LAN_X2
56
IN
INTEL
CONFIDENTIAL
2 1
AT93C46A
3
OUT
1
CSDIDO
2
SK
GND=5 NC=7 VCC=8
VCC=V_3P3_STBY
56
4
6
TP_EEPROM_6
ORG
IC
C74146-001
C7A12
12
22PF
5%
N_C0603
50V NPO 603
N_C0603
C7A13
12
5%
22PF
50V NPO 603
DOCUMENT NUMBER PAGE REV
C77862
B
A
58
4.0
<XR_PAGE_TITLE>
CAD NOTE:
OVERLAP WITH MAGJACK FOOTPRINT * MODEL HAS DIFFERENT PIN ORIENTTION
THAN MAGJACK FOOTPRINT
D
BOM NOTE:
EMPTY EXCEPT FOR USB W/NO-LAN OPTION
91
91
IN
BI BI
IN
BI BI
VREG_USB_BP_LEFT
USB_BACK1_R* USB_BACK1_R
VREG_USB_BP_LEFT
USB_BACK2_R* USB_BACK2_R
LAN CONNECTOR
DEFAULT GIGABIT
MAGJACK SPEED LED
C
100 MBPS GREEN
1000 MBPS YELLOW
A74307-001
10 MBPS OFF
1 2 3 4
5 6 7 8
JA6A1A
2 X USB
1000
IO
USB STACK
VREG_USB_BP_LEFT
91
IN
USB_BACK2_R*
BI
USB_BACK2_R
BI
VREG_USB_BP_LEFT
91
IN
USB_BACK1_R*
BI
USB_BACK1_R
BI
B
LAN_MDI0_P
56
BI
LAN_MDI0_N
56
BI
LAN_MDI1_P
56
BI
LAN_MDI1_N
56
BI
LAN_MDI2_P
56
BI
LAN_MDI2_N
56
BI
LAN_MDI3_P
56
BI
LAN_MDI3_N
56
BI
LAN_LED_ACT
56
IN
LAN_LINK LAN_LED_10
BI
J6A1
2 X USB
1
9 2 3 4
10
5
11 6 7 8
12
EMPTY
DESIGN NOTE:
USE CONNECTOR A74307-001 WITH NORTHWAY USE CONNECTOR A74314-002 WITH KINNERETH-R
A74307-001
1000
JA6A1B
GBE_MAGJACK3_10
10
TD0+
11
TD0-
12
TD1+
13
TD1-
14
TD2+
15
TD2-
16
TD3+
17
TD3-
GND=23..30
A74307-001
1000
JA6A1D
GRN_LED
YLW_LED
SGND
IO
VCT
IO
2122
9
18
A74307-001
1000
JA6A1C
GRN_LED
IO
1920
57,58
IN
CAD NOTE:
PLACE CLOSE TO NWY
BOM NOTE:
STUFF FOR NWY EMPTY FOR KINNERETH
LAN_VCT
SMC0402
2
C6B3
470PF 10% 50V
1
EMPTY 402
LAN_LED_100
LAN_V_1P8
R6B1
1 2
0 5%
402 EMPTY
BOM NOTE:
STUFF FOR NWY EMPTY FOR KINNERETH
OUT
2
1
BI
SMC0402
C8A3
1000PF 10% 50V EMPTY 402
56
56
38
38
38
USB_BACK1*
BI
USB_BACK1
BI
USB_BACK2*
BI
38
USB_BACK2
BI
1
2 3
752402-009
1
2 3
752402-009
STUFFING OPTIONS FOR LED ENABLING
R6A3
1 2
0 5%
402 CH
LAN_LINK
BI
R6A2
1 2
0 5%
402 EMPTY
28 7 6 5 4 3 1
R6B3
1 2
0
1A
EMPTY
603
L6B2
90OHM
IND 4PIN
0 1A
603
603
IND 4PIN
0
603
R6B5
1 2
R6B2
1 2
L6B1
90OHM
R6B4
1 2
EMPTY
EMPTY
EMPTY
1A0
1A
DESIGN NOTE:
DESIGN NOTE:
4
USB_BACK1_R*
USB_BACK1_R
IND
CAD NOTE:
OVERLAPPING FOOTPRINTS DO NOT CHANGE TO 402
4
USB_BACK2_R*
USB_BACK2_R
IND
V_3P3_PCIVAUX
STUFF FOR KINN-R
UNSTUFF FOR KINN-R
LAN_LED_1000
BI
BI
BI
BI
IN
BI
32,49..51,56..58,90
56
D
C
B
CAD NOTE:
LED CAPS SHOULD BE PLACED NEXT TO CONNECTOR
LAN_LED_ACT
56
IN
56
A
56
LAN_MDI0_P
IN
LAN_MDI0_N LAN_MDI1_N
IN
2
1
LAN_MDI0_P_R
C7A3
.1UF 10%
6.3V EMPTY 402
2
1
2
1
R7A5
54.9 1%
CH 402
R7A1
54.9 1%
CH 402
56
56
LAN_MDI1_P
IN
LAN_MDI1_P_R
2
C7A4
.1UF 10%
6.3V
1
EMPTY 402
IN
2
R7A12
54.9 1%
CH 402
1
2
R7A7
54.9 1%
CH 402
1
56
DESIGN NOTE:
NWY:49.9 OHM A36092-045
KINNERTH-R:60.4OHM A36092-120
56
LAN_MDI2_P LAN_MDI3_P
IN
2
LAN_MDI2_P_R
2
C7A5
.1UF 10%
6.3V
1
EMPTY 402
1
2
1
IN
R7A14
49.9 1%
EMPTY 402
R7A13
49.9 1%
EMPTY 402
56
IN
LAN_MDI3_P_R
2
1
56
LAN_MDI3_NLAN_MDI2_N
IN
C7A7
.1UF 10%
6.3V EMPTY 402
2
R7A16
49.9 1%
EMPTY 402
1
2
R7A18
49.9 1%
EMPTY 402
1
LAN_LED_10
56
OUT
DIFFERENTIAL PAIR TERMINATION
8 7
45
36
LED DECOUPLING
SMC0402
2
C6B2
470PF 10% 50V
1
X7R 402
SMC0402
2
C6A6
470PF 10% 50V
1
X7R 402
56
BI
BI
[PAGE_TITLE=LAN CONN]
INTEL
DOCUMENT NUMBER PAGE REV
CONFIDENTIAL
2 1
LAN_LED_100
LAN_LINK
C77862
2
1
2
1
SMC0402
C6B1
470PF 10% 50V X7R 402
SMC0402
C6A8
470PF 10% 50V X7R 402
59
A
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
DEFAULT AUDIO CODEC: AZALIA REALTEK
LINE IN
D
AUD_CODEC_VREF
61
IN
AUD_LINK_BCLK
43
OUT
C
C9B3 10PF
12
50V 5% 402
62
61,62
61,64
61
43
43
40
61
62
62
62
62
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
AUD_SPDIF_OUT
AUD_CDC_SENSE_A
AUD_CDC_SENSE_B
AUD_LINK_SDI2_R
AUD_LINK_SDO
AUD_LINK_SYNC
AUD_LINK_RST*
AUD_PC_BEEP
AUD_CD_IN_L
AUD_CD_GND
AUD_CD_IN_R
AUD_SPDIF_IN
27
6
8
5
10
11
12
18
19
20
47
48
13
34
VREF
BITCLK
SDATAIN
SDATAOUT
SYNC
RESET*
PCBEEP
CDL
CDGND
CDR
SPDIFI/EAPD
SPDIFO
SENSE_A_JD1
SENSE_B_JD2
B
25 26
AVDD1
38
AVDD2
GPIO1
1
DVDD1
9
DVDD2
49
NC
CK_14M_AUD
IN
"COG"
5.6PF EMPTY
C9B1
9%
50V 402
IN
IN
V_5P0_AUD_ANALOG
VDD_IO_CODEC
VCC3
29
61,62,64..66
A
VCC3
R9B10
1 2
0 5%
EMPTY
402
R9B18
1 2
0 5%
402 EMPTY
VDD_IO_CODEC
OUT
U9A1
ALC880
1
VREFOUTCR
VREFOUTBL
VREFOUTCL
VREFOUTBR
VREFOUTEL
VREFOUTFL
C63323-001
AUD_AC97
R9B2
12
1 2
0
5%
EMPTY
402
R9B3
1 2
5%0
EMPTY
402
39
JACKAL
41
JACKAR
21
JACKBL
22
JACKBR
23
JACKCL
24
JACKCR
35
JACKDL
36
JACKDR
14
JACKEL
15
JACKER
16
JACKFL
17
JACKFR
43
JACKGL
44
JACKGR
45
JACKHL
46
JACKHR
37
28
29
32
31
30
33
DCVOL
40
JDREF
AVSS1
42
AVSS2
23
GPIO0
4
DVSS1
7
DVSS2
IC
VSS_CLOCK_CODEC
AUD_PORT_A_L
AUD_PORT_A_R
AUD_PORT_B_L
AUD_PORT_B_R
AUD_PORT_C_L
AUD_PORT_C_R
AUD_PORT_D_L
AUD_PORT_D_R
AUD_PORT_E_L
AUD_PORT_E_R
AUD_PORT_F_L
AUD_PORT_F_R
AUD_PORT_G_L
AUD_PORT_G_R
AUD_PORT_H_L
AUD_PORT_H_R
AUD_VREF_37
AUD_VREF_28
AUD_VREF_29
AUD_VREF_32
AUD_VREF_31
AUD_VREF_30
AUD_VREF_33
AUD_VREF_40
AUD
VSS_CLOCK_CODEC
OUT
64
BI
64
BI
63
BI
63,64
BI
63
BI
63
BI
63,64
BI
63,64
BI
62,64
BI
62,64
BI
61,64
BI
61,64
BI
65
BI
65
BI
61,65
BI
61,65
BI
61,62,65
OUT
61,62,65
OUT
61,65
OUT
OUT
OUT
OUT
OUT
OUT
IN
61,64,65
61,65
61,65
61,64,65
61
DESIGN NOTE: AZALIA:
CMEDIA: CMI9880 REALTEK: ALC880,ALC860
AC97:
CMEDIA: CMI9762+,9780 REALTEK: ALC650,655,658,850, ALC202A
PORT E PORT F
FACING BACK PANEL
ON FRONT PANEL
INTEL
CONFIDENTIAL
8 7
45
36
2 1
PORT C
FRONT / LINE OUT PORT D
MIC IN PORT B
AUDIO CODEC
DOCUMENT NUMBER PAGE REV
C77862
D
C
B
A
60
4.0
<XR_PAGE_TITLE>
AUD_VREF_28
CAD NOTE:
PLACE NEAR ICH PINS
402
AUD
R9A29
1 2
EMPTY
5%0
1 2
33CH5%
402
1 2
4.7K 402
1 2
20K 1%
402
R8A8
1 2
4.7K 402
R9B1
1 2
10K 5% 402
R9B6
1 2
1K 1%
402
R9A23
1 2
5.6K 5%
402
R9A6
1 2
402
R9A43
1 2
0 5%
402
R9A36
1 2
0 5%
402
R9B12
4.7K
R9A48
R9A50
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
402
EMPTY
R9A45
1 2
5%
CH
5%
5%0
5%
EMPTY
402
AUD_LINK_SDI2AUD_LINK_SDI2_R
1 2
0 5%
1 2
402
AUD_VREF_33
AUD_VREF_40
V_5P0_AUD_ANALOG
AUD
AUD_PORT_H_L
AUD_VREF_31
AUD_PORT_F_L
R9A47
AUD_VREF_40
EMPTY
AUD_PORT_F_R
R9A11
AUD_FP_RET_R
5%0
EMPTY
40
OUT
OUT
60,64,65
60
OUT
OUT
60,65
OUT
OUT
OUT
OUT
OUT
60,65
60,64
60
60,64
63,64
OUT
D
60
IN
IN
IN
IN
V_5P0_AUD_ANALOG
IN
AUD_PORT_H_R
OUT
AUD_VREF_37
OUT
AUD_VREF_28
OUT
AUD_JS_B
AUD_JS_C
AUD_JS_D
8 7
60,62,64..66
C
60,65
B
60,62,65
60,62,65
63
A
63
63
60,62,65
IN
AUD_VREF_29
60,65
IN
AUD_VREF_30
60,65
IN IN
IN IN IN IN
AUD_VREF_31
AUD_VREF_32 AUD_VREF_33 AUD_VREF_37 AUD_VREF_40
2
C9A10
1UF 20%
6.3V
1
EMPTY 402
2
60,65
60,64,65 60,64,65 60,62,65 60
1
CAD NOTE:
PLACE NEAR EACH VREF PIN
VREF DECOUPLING
60,62,64..66
AUD_CODEC_VREF
60
OUT
60,62,64..66
60,62,64..66
V_5P0_AUD_ANALOG
IN
V_5P0_AUD_ANALOG
IN
VCC3
2
C9A16
10.0UF 20%
6.3V
1
X5R 805
2
C8A4
10.0UF 20%
6.3V
1
X5R 805
2
C9A23
10.0UF 20%
6.3V
1
X5R 805
2
2
C9B6
C9B2
.1UF
.1UF
10%
10%
6.3V
1
6.3V
1
X5R
X5R
402
402
SUPPLY DECOUPLING
C9A24
1UF 20%
6.3V EMPTY 402
AUD
AUD
AUD
2
1
2
1
2
1
2
1
C9A14
.1UF 10%
6.3V X5R 402
C9A20
.1UF 10%
6.3V X5R 402
C9A17
.1UF 10%
6.3V X5R 402
C9B4
.1UF 10%
6.3V X5R 402
2
1
2
C9A11
1000PF 10%
6.3V
1
EMPTY 402
C9A19
1UF 20%
6.3V EMPTY 402
AUD
VREF SUPPLY
CAD NOTE:
PLACE NEAR PIN 27
ANALOG SUPPLY CAD NOTE:
PLACE NEAR PIN 25
ANALOG SUPPLY CAD NOTE:
PLACE NEAR PIN 38
2
C9A12
1000PF 10%
6.3V
1
EMPTY 402
2
C9A8
1UF 20%
6.3V
1
EMPTY 402
DIGITAL SUPPLY CAD NOTE:
PLACE ONE NEAR PINS 1, 3, 9
45
60,62,64..66
IN
2
C9A13
1UF 20%
6.3V
1
EMPTY 402
AUD AUD
2
C9A9
1UF 20%
6.3V
1
EMPTY 402
63,64
OUT
FRONT PANEL JACK SENSE NETWORK
60,62,64..66
IN
63
BACK PANEL JACK SENSE NETWORK
AUD_SENSE_A
OUT
SPKR
39,72,80
IN
60
IN
DECOUPLING AND
JACK SENSE
36
V_5P0_AUD_ANALOG
AUD_SENSE_B
C9A3
20%4.7UF 10V EMPTY 805
V_5P0_AUD_ANALOG
C8B5
4.7UF
20% 10V EMPTY 805
R9A49
1 2
4.7K
5%
EMPTY
402
AUD
R9B15
1 2
10K 5%
CH
402
AUD_PC_BEEP
28 7 6 5 4 3 1
R9A25
1 2
10K 5%
EMPTY
402
R9A34
1 2
5%0 CH
402
12
"Y5V"
NEED TO CHANGE TO 5K
R9A44
1 2
10K 5%
IF AC97, R9A44 CHANGE TO 1K(A36092-023)
EMPTY
402
R9B11
1 2
AUD_CDC_SENSE_A
5%0 CH
402
12
"Y5V"
C9B5
20%.1UF
16V
1K
402
R9B16
1 2
5%
EMPTY
Y5V 402
402
R9B13
1 2
5%100 CH
INTEL
CONFIDENTIAL
2 1
AUD_CDC_SENSE_B
12
AUD_PC_BEEPAUD_PC_BEEP_PN1
60,64
IN
60,62
IN
60
OUT
PC BEEP
8
5
7
6
RP9F1D
0 5% .063W EMPTY
1
DOCUMENT NUMBER PAGE REV
C77862
SM
4
2
3
61
D
C
B
A
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
C8A17
D
60
60
60
OUT
OUT
OUT
AUD_CD_IN_L
AUD_CD_GND
AUD_CD_IN_R
1UF
6.3V Y5V
603
C8B6
1UF
6.3V Y5V
603
C8A15
1UF
6.3V Y5V
603
20%
20%
20%
12
12
12
1
2
R9B17
4.7K 5%
CH 402
AUD_CD_IN_L_PN1
AUD_CD_GND_PN1
AUD_CD_IN_R_PN1
R8B9
1
4.7K 5%
2
CH 402
1
2
R9B21
4.7K 5%
CH 402
R8B1
1
4.7K 5%
2
CH 402
C
M9B1
IN
AUD_SPDIF_OUT
60
VCC3
R9B23
1 2
10K 5%
402
R9B24
1 2
10K
402
Need to empty if
B
AUD_PORT_A_L60,64
AUD_PORT_A_L
A
60,64
AUD_PORT_E_L
OUT
60,64
AUD_PORT_A_R60,64
OUT
AUD_PORT_E_R
AUD_PORT_A_R
stuff AC97
12
R9B38
5%0 EMPTY
402
12
R9B39
5%0 EMPTY
402
12
R9B36
5%0 EMPTY
402
12
R9B37
5%0 EMPTY
402
1 2
DEFAUL A36096-005,4700PF cap for AZALIA OPTION A36093-001,0 ohm resistor for TRIGEM
EMPTY
5% CH
AUD_LAUXIN_C_L
AUD_RAUXIN_C_L
MULTI
402CH
BOM NOTES:
C9A21
12
1UF
20%
C9A25
6.3V EMPTY
12
603
1UF
20%
6.3V EMPTY 603
STUFF FOR AC97
UNNAMED_62_NCAP_I35_B
12
R9B32
220 4025%CH
DEFAUL A36096-009,100-ohm resistor for AZALIA OPTION A36093-023,10K-ohm resistor for TRIGEM
AUD_LAUXIN_C
R9B9
4.7K 5% 402 EMPTY
1 2
402
402
R9B4
12
4.7K 5% 402 EMPTY
12
BOM NOTES:
R9B7
5%4.7K EMPTY
R9B5
1 2
2
1
5%4.7K EMPTY
R9B31
10K 5%
CH 402
2
1
AUDIO
AUD_PHONE
AUD_LAUXIN_R
AUD_RAUXIN_RAUD_RAUXIN_C
C9B12
220PF 10% 50V Y5V 402
TELE.
ATAPI HEADER
J9C2
1X4HDR
EMPTY
Default
NC=5
J9B1
1X4HDR
1 2 3 4
EMPTY
J8B2
1X3HDR
HDR
1
AUD_PHONE_IN_R AUD_CDC_SENSE_A
2 3 4
AUD_PHONE
AUDIO
R9B33
402
5%0 EMPTY
TEL IN HEADER
AUX IN ATAPI HEADER
8 7
R8B4
1 2
5%
4.7K CH
402
R9B19
1 2
5%4.7K CH
402
R9B22
1 2
4.7KCH5%
402
R9B20
1 2
5%4.7K CH
402
1 2
UNNAMED_62_1X3HDR_I41_IO
3
12
AUD_VREF_37_TEMP
STUFF FOR AC97
45
AUD_CD_IN_L_HDR AUD_CD_GND_HDR
AUD_CD_IN_R_HDR
SPDIF OUT
V_5P0_AUD_ANALOG
C9B14
1 2
1.0UF
10V 20% 603 EMPTY
J9C1
1X4HDR
1 2 3 4
HDR
BLACK
CD IN
ATAPI HEADER
EMPTY
1 2
102276-001
60,61,64..66
IN
AUD_SPDIF_IN_L
J8C2
1X2HDR
1 2
C9C5
.01UF
50V 20% 603 EMPTY
VCC3
1 2
1 2
R9C3
10K
5% 402 EMPTY
R9C4
10K
5% 402 EMPTY
AUD_SPDIF_IN
OUT
60
D
C
B
AUD_PHONE
FIN=AUDIO
12
R9B35
5%0 EMPTY
402
AUD_VREF_37AUD_MONO_OUT_C
IN
AUD_PHONE_IN_C
60,61,65
AUDIO
2
AUD_PHONE_E
R9B34
5.6K 5%
EMPTY 603
1
1 2
C9B15
1.0UF
10V 20% 603 EMPTY
OUT
60,61
A
CD IN AND SPDIF
INTEL
CONFIDENTIAL
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
62
4.0
<XR_PAGE_TITLE>
BOM NOTE:
STUFF FOR AC97 EMPTY FOR AZALIA
D
60
60
C
61,64
60,64
60,64
64
BI
BI
IN
BI
BI
IN
AUD_PORT_C_R
AUD_PORT_C_L
AUD_FP_RET_R
AUD_PORT_D_R
AUD_PORT_D_L
AUD_FP_RET_L
BOM NOTE:
STUFF FOR AC97 EMPTY FOR AZALIA
0
402
0 5%
0 5%
402 CH
0
402 EMPTY
B
60,64
60
BI
BI
AUD_PORT_B_R
AUD_PORT_B_L
A
R4B3
5%
EMPTY
R4B4
CH402
R4A21
R4A24
5%
DESIGN NOTE:
1.0 UF CAPS NEED TO BE X5R; DO NOT CHANGE TO Y5V.
R9A32
1 2
4.7K 5%
402 EMPTY
R9A26
1 2
0 5%
402 CH
R9A20
1 2
0 5%
402 CH
R9A27
1 2
4.7K 5%
402 EMPTY
12
12
12
12
C9A6
NET_AUD_FP_PWR
1 2
1UF
6.3V 20%
DESIGN NOTE:
1.0 UF CAPS NEED TO BE X5R; DO NOT CHANGE TO Y5V.
NET_AUD_PORT_LINE_R_C
NET_AUD_PORT_LINE_L_C
C9A5
NET_AUD_SENSE_B
1 2
1UF
6.3V 20%
DESIGN NOTE:
KEEP AS 100UF
C4B1
1 2
UNNAMED_63_CAPN_I82_A
100UF
20%
6.3V
ALUM
TH
C4B2
1 2
UNNAMED_63_CAPN_I83_A
100UFTH20%
6.3V
ALUM
AUD_FP_PWR
603
EMPTY
C8A6
12
20% 10V X5R 805
12
20% 10V X5R 805
AUD_PORT_LINE_R_C
AUD_PORT_LINE_L_C
4.7UF
C8A10
4.7UF
AUD_SENSE_B
603 EMPTY
AUDIO
AUD_PORT_LINE_R_D AUD_PORT_LINE_R_D
202008-250
AUDIO
AUD_PORT_LINE_L_D AUD_PORT_LINE_L_D
202008-250
64
BI
65
BI
BI
61,64
BI
BI
BI
65
BI
65
65
BI
R8A1
47K 5% 402
R8A10
402 CH
65
65
BI
65
65
BI
R4A17
47K 4025%CH
R4A25
47K 5%
C8A12
12
AUD_PORT_LINE_R_B AUD_PORT_LINE_R_B
4.7UF20% 10V X5R 805
C8A14
12
AUD_PORT_LINE_L_B AUD_PORT_LINE_L_B
20%
4.7UF 10V X5R 805
65
BI
65
BI
65
65
BI
BI
47K 4025%CH
47K 402 CH
AUD_PORT_LINE_R_C
AUD_PORT_LINE_L_C
12
CH
12
5%47K
12
12
CH402
R4A11
12
R4A16
12
5%
BOM NOTE:
FB OPTION: 0.2AMP (693286-014), 0603 RES OPTION: 0 OHM (108506-004), 0603
600
0.2A BROAD
M4A1
1 2
MULTI
600
0.2A BROAD
M4A4
1 2
MULTI
600
0.2A BROAD
M4A6
1 2
MULTI
600
0.2A BROAD
M4A5
1 2
MULTI
600
0.2A BROAD
M4A2
1 2
MULTI
600
0.2A BROAD
M4A3
1 2
MULTI
FB
FB
FB
FB
FB
FB
AUD_R_LINEOUT_C
AUD_L_LINEOUT_C
AUD_R_LINEOUT_D
AUD_L_LINEOUT_D
AUD_R_LINEOUT_B
AUD_L_LINEOUT_B
C4A10
220PF 10%
50V
X7R
402
C4A15
220PF
50V
X7R
402
C4A17
220PF 10%
50V
X7R
402
C4A16
220PF
50V
X7R
402
C4A11
220PF
50V
X7R
402
C4A14
220PF 10%
50V
X7R
402
61
OUT
61
IN
12
12
10%
12
12
10%
12
10%
12
61
OUT
R4A10
1 2
402
61
IN
IF Stuff AC97, CHANGE TO 10K, 5%(A36093-023).
61
20.5K 402
61
IF Stuff AC97, CHANGE TO 10K, 5%(A36093-023).
28 7 6 5 4 3 1
AUD_JS_C
R4A9
1 2
1%
10K
CH
AUD_SENSE_A
402
IF Stuff AC97, CHANGE TO 10K, 5%(A36093-023).
AUD_JACK_GND
AUD_JS_D
1%5.11K CH
AUD_SENSE_A
AUD_JACK_GND
AUD_JS_B
OUT
R4A13
1 2
1% CH
AUD_SENSE_A
IN
AUD_JACK_GND
3 STACK AUDIOJACK_SW
32
35
33
34
1
LINE IN
22
25
23
24
1
AUD_JACK_GND
J4A1B
3 STACK AUDIOJACK_SW
LINE OUT
3 STACK AUDIOJACK_SW
2
5
3
4
1
MIC
J4A1C
J4A1A
JACK
D
TOP
JACK
66
OUT
C
MIDDLE
66
OUT
B
BOTTOM
JACK
66
OUT
A
BACK PANEL PORTS
8 7
AUDIO BACK PANEL
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
63
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
12
R8A18
R9A39
R9A41
R9A37
R8A20
R9B27
R8B2
R9B29
AUD_PORT_1_R_SPLIT
05%
12
402EMPTY
12
4.7K 402
12
0
402
1
AUD_PORT_1_L_SPLIT
12
402EMPTY
12
0
12
12
0
12
AUD_PORT_2_R_SPLIT
0
12
0
402CH
12
AUD_PORT_2_L_SPLIT
0
402
12
402
12
402
AUD_PORT_E_R
60,62
BI
60,61
60,62
60
BI
BI
IN
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
AUD_PORT_A_R
AUD_PORT_F_R
AUD_PORT_F_R
AUD_PORT_B_R
AUD_CDC_SENSE_B
AUD_PORT_E_L
AUD_PORT_F_L
AUD_VREF_32
AUD_VREF_33
AUD_PORT_D_R
AUD_PORT_A_L
AUD_PORT_F_L
AUD_PORT_D_L
60,61
60,63
C
60,61
60,61,65
60,61,65
B
60,63
60
60,61
60,61
60,63
A
CH 402
5% 0
5%
EMPTY
5%
EMPTY
2
5% CH0402
5% 0
EMPTY5%402
5%
EMPTY0402
R9A33
EMPTY5%402
R9A40
EMPTY5%402
R9A38
5%
R9B25
5%
EMPTY
R9B26
5% 0 CH
R9A19
5% 0 EMPTY
C9B13
1 2
100UF
6.3V
ALUM
TH
C9A2
1 2
6.3V
ALUM
TH
C9A1
1 2
100UF
6.3V
ALUM
TH
C9A4
1 2
6.3V
ALUM
TH
20%
202008-250
AUD_PORT_1_L_HDR
AUD_PORT_1_R_HDR
20%100UF
202008-250
20%
AUD_PORT_2_R_HDR
202008-250
AUD_PORT_2_L_HDR
20%100UF
202008-250
65
BI
65 65 65
65
BI
65
65
BI
65
BI
40,43
60..62,65,66
BI
AUD_PORT_1_R_HDR
BI BI IN BI
AUD_SENSE_B
AUD_PORT_2_L_HDR
61,63
OUT
IN
AUD_PORT_1_L_HDR
AUD_PORT_2_R_HDR
65 65 65
65
FP_AUD_DETECT
V_5P0_AUD_ANALOG
R9A21
1 2
5%
47K
CH
402
R9A2
1 2
47K 5%
R8B8
CH
402
1 2
5%CH47K
402
R9A28
1 2
5%47K CH
402
AUD_PORT_1_L_HDR
BI
AUD_PORT_1_R_HDR
BI
AUD_PORT_2_R_HDR
BI
61,63
61,63 63
IN
BI
IN IN
AUD_SENSE_B
AUD_PORT_2_L_HDR
AUD_FP_RET_R
AUD_FP_RET_L
BOM NOTE:
USE IPN 109717-755 FOR YELLOW HDR USE IPN 109717-205 FOR BLACK HDR
2
C8A11
220PF 10% 50V
1
EMPTY 402
R9A51
1 2
R9A46
1 2
0
4025%EMPTY
J8A2
2X5HDR_8
1 2 3 4 5 6 7 9 10
HDR
109717-755
2
2
C9B10
220PF 10% 50V
1
1
EMPTY 402
5%0 CH402
AUD
AUD_FP_RET_R
AUD_FP_RET_L
2
1
R8B10
20.5K 1%
CH 402
OUT
AUD AUD AUD
C9B8
220PF 10% 50V EMPTY 402
2
2
C9B11
M9B9
220PF
220PF
10%
10%
50V
50V
1
1
EMPTY
EMPTY
402
402
2
2
C8B3
220PF 10% 50V
1
1
EMPTY 402
AUD_FP_PWR
63
C8B7
220PF 10% 50V EMPTY 402
63
IN
61,63
OUT
2
1
R9A16
39.2K 1%
CH 402
2
C9A22
0.1U Y5V
1
402
20%
D
C
B
A
8 7
AC HEADER
FRONT PANEL PORTS
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
64
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
FRONT PANEL
CR9A1B
5
AUD_PORT_1_R_DIODE
4
AUD_PORT_1_L_DIODE
CR9A1A
2
AUD_PORT_2_R_DIODE
1
AUD_PORT_2_L_DIODE
R9A4
1 2
4.7K EMPTY
402
R9A1
1 2
1.2K
402
R9A7
1 2
1.2K
402
R9A10
1 2
3.3K EMPTY
402
R9A17
1 2
4.7K 5% EMPTY
402
R9A13
1 2
1.2KCH5%
402
R9A22
1 2
402
R9B28
1 2
4.7K EMPTY
402
5%
AUD_PORT_1_R_HDR
5% CH
AUD_PORT_1_L_HDR
5% CH
5%
AUD_PORT_2_R_HDR
AUD_PORT_2_L_HDR
5%1.2K CH
5%
D
64
OUT
64
OUT
C
64
OUT
64
OUT
B
R4A14
1 2
402
R4A15
1 2
R9A12
1 2
EMPTY
EMPTY
402
EMPTY
5%
402
R8A15
1 2
0
5%0
R8A12
1 2
EMPTY
5%0 CH
5%
3 STACK
BAW56S
SOT363
EMPTY
CR8B1
3
UNNAMED_65_DIOSOT23A_I57_A
.45V
SOT23A
EMPTY
CR4A3B
5
4
AUD_LINE_OUT_R_DIODE
AUD_LINE_OUT_L_DIODE
3
AUD_LINE_OUT_L_VREF_DIODE
1
2
AUD_LINE_IN_R_DIODE
AUD_LINE_IN_L_DIODE
R9A8
1 2
402
R9A3
1 2
1.2K 402
R8A9
1 2
2.2K 402
R8B7
1 2
2.2K 402
R8A11
1 2
1.2K 402
R4A18
1 2
4.7K 5% 402
R4A23
1 2
402
R4A19
1 2
402
R4A20
1 2
4.7K 5% 402
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
5%4.7K
5% CH
5%
5%
5% CH
5%2.2K
5%2.2K
EMPTY FOR AC97
AUD_PORT_LINE_R_C
AUD_PORT_LINE_L_C
AUD_PORT_LINE_R_D
AUD_PORT_LINE_L_D
60
60,61
63
OUT
63
OUT
63
OUT
63
OUT
60..62
60,61,64
60,61
60,61
AUD_PORT_G_R
IN
AUD_VREF_31
IN
AUD_VREF_37
IN
AUD_PORT1_BIAS_DIODE
IN
AUD_VREF_33
IN
AUD_VREF_31
IN
AUD_VREF_30
IN
AUD_PORT2_BIAS_DIODE
IN
402
402
402
R9A14
1 2
0
R9A9
1 2
0
R9A15
1 2
0
1 2
0
402
EMPTY
EMPTY
R9A18
5% CH
3
5%
BAW56S
SOT363
DIO
5%
6
5% CH
BAW56S
SOT363
DIO
D
IN
IN
AUD_VREF_33
AUD_PORT_H_L
AUD_VREF_37
AUD_VREF_29
60,61
60..62
60,61
IN
60,61,64
IN
C
IN
AUD_VREF_37
AUD_VREF_32
AUD_PORT_G_L
0
402
60
60..62
IN
60,61,64
IN
B
AUD_VREF_30
60,61
IN
0 5%
402
TERMINATION/PULL-UPS
R8A7
IN
AUD_VREF_32
AUD_VREF_28
AUD_PORT_H_R
402
R4B2
1 2
5%0 CH
CR4A3A
2
6
BAW56S
SOT363
EMPTY
AUD_MIC1_DIODE_MIC_BIAS
1
AUD_MIC2_DIODE
AUD_MIC1_DIODE
60,61
IN
60,61,64
60..62
IN
A
1 2
4.7K 5% 402
R4A7
1 2
1.2K 402
R4A12
1 2
2.2K 402
R4A22
1 2
2.2K 402
R4B1
1 2
1.2K 402
EMPTY
EMPTY
EMPTY
5% CH
5%
5%
5% CH
AUD_PORT_LINE_R_B
AUD_PORT_LINE_L_B
R9A5
AUD_PORT1_BIAS_DIODE
1 2
0 5%
EMPTY
R9B8
63
OUT
63
OUT
60..62,64,66
V_5P0_AUD_ANALOG
IN
1 2
510 5%
EMPTY
402
UNNAMED_65_CAP-P_I35_A
1
2
C9B7
470.0UF
20% 16V EMPTY RDL
402
402
R9B14
1 2
EMPTY
5%0
AUD_PORT2_BIAS_DIODE
OUT
OUT
A
AUD
TERMINATION/PULL-UPS
8 7
VREF NETWORKS
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
65
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
+12V
41,57,74,78,81,86,90..95
1 2
10K CH 5% 402
IN
R9C8
AUD_12V_CONTROL
2
1
V_5P0_STBY
+12V
2
1
PLACE NEAR TRIPLE -STACK AUDIO CONNECTOR
C9C7
.1UF 20% 16V EMPTY 402
C9C3
1UF 20% 16V EMPTY 805
1
R9A35
1 2
0
EMPTY
603
1
1A
3
2
U9C1
78M05C
Q9C1
FET
AUD
GND
2
OUTIN
EMPTY
3
D
REGULATOR THERMAL TAB SHOULD BE SOLDERED TO A COPPER PAD THAT IS LARGE ENOUGH
C
TO ALLOW 5 TO 10 GROUND VIAS AROUND
THE COMPONENT FOR COOLING
CLOSE TO REGULATOR
B
IN
AUD_JACK_GND
63
PLACE IN TOP LEFT CORNER OF BOARD
V_5P0_AUD_FILTERED
AUD
2
C9A7
.1UF 20% 16V
1
Y5V 402
2
1
C9A15
1.0UF 20% 10V Y5V 603
1
2
C9A18
100UF 20% 25V ELEC RDL
1 2
R9A42
0OHM
EMPTYSM
R9A30
1 2
0OHM
EMPTY
SM
R9A31
1 2
0OHM
SM
EMPTY
V_5P0_AUD_ANALOG
NOTE: LAYOUT SHOULD GO FROM PIN 2 TO CAPS AND THEN THROUGH SEVERAL VIAS TO V_5P0_AUD_ANALOG
AUD
D
C
OUT
60..62,64,65
B
2
C6A1
1.0UF 20% 10V
1
A
Y5V 603
2
R9A24
0
5% CH
402
1
A
PLACE NEXT TO CODEC
GND AT MOUNTING HOLE
8 7
AUD
[PAGE_TITLE=AUDIO_VREG]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
66
4.0
28 7 6 5 4 3 1
D
C
D
C
BLANK
B
B
A
DOCUMENT NUMBER PAGE REV
C77862
67
8 7
INTEL
45
36
CONFIDENTIAL
2 1
A
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
C
D
C
BLANK
B
B
A
DOCUMENT NUMBER PAGE REV
C77862
68
8 7
INTEL
45
36
CONFIDENTIAL
2 1
A
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
C
D
C
BLANK
B
B
A
DOCUMENT NUMBER PAGE REV
C77862
69
8 7
INTEL
45
36
CONFIDENTIAL
2 1
A
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
SECURITY: TPM (TRUSTED PLATFORM MODULE)
D
U8J1
40,72,73
29 40,72,73 15,37,55,56,72,73 40,73
40,73,81
C
BI
IN IN IN IN
BI
L_AD[3..0]
CK_P_33M_TPM L_FRAME*
PLTRST*
LPCPD*
SER_IRQ
I_CLKRUN*
603
R8H12
1 2
1A0
EMPTY
UNNAMED_57_RESN_I86_B
7
3
L_AD3
2
L_AD2
3
1
L_AD1
2
0
L_AD0
8 13 27 26 12 20
9 23
VCC3
R8H13
0 1A
EMPTY 603
108506-004
1
2
TPM_CLKOVD
R8H16
10K 5%
EMPTY 603
202285-073
R8H15
1 2
5%4.7K
EMPTY
1
2
R8H14
4.7K 5%
EMPTY 603
202285-065
603
202285-065
1
2
R8H17
0 1A
EMPTY 603
108506-004
I_BADDR
1
B
2
LAD<3> LAD<2> LAD<1> LAD<0> LCLK LFRAME* LRESET* LPCPD* SERIRQ BADDR CLKOVD CLKRUN*
NC=1,14,15,28 GND=4,10,18,24
A98822-003
SLD9630
VDD_11 VDD_25
PENABLE PACCESS
TESTIO TESTEN
VDDC
VDD_5
EMPTY
VCC3
19 56 11 25
22
PENABLE
21
PACCESS
16
TP_TPM_TESTIO
17
1
2
1
2
R8H20
4.7K 5%
EMPTY 603
202285-065
R8J1
4.7K 5%
EMPTY 603
202285-065
VCC3
J8J1
1X3HDR
1 2 3
TP_NC
EMPTY
OPTION
1-2
NORMAL*
2-3
* = DEFAULT
CAD NOTE: CK_P_33M_TPM SHOULD HAVE 20MIL SPACING P_PCIRST* SHOULD HAVE 20 MIL SPACING LAD<3..0> HAS 5 MIL SPACING BETWEEN OTHER LAD SIGNALS, BUT 10 MILS TO ALL OTHER SIGNALS.
D
C
B
VCC3
1
2
C8D11
.1UF 20% 25V EMPTY 603
202341-002
A
1
2
C8H18
1.0UF 20% 10V EMPTY 603
202341-008
1
C8H13
.1UF 20% 25V
2
EMPTY 603
202341-002
CAD NOTE: PLACE ONE PER POWER PIN NEXT TO PIN.
1
C8J2
.1UF 20% 25V
2
EMPTY 603
202341-002
1
2
C8H15
.1UF 20% 25V EMPTY 603
202341-002
A
TPM (TRUSTED PLATFORM MODULE)
DOCUMENT NUMBER PAGE REV
C77862
70
4.0
8 7
INTEL
CONFIDENTIAL
45
36
2 1
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
BOM NOTE:
FOR M-SITES, USE A36096-008 (.01UF, 0402)
D
J9J1
1X7HDR
SATA
2
TXP
1
GND
4
GND
7
GND
A71107-007
C
1
GND
4
GND
7
GND
A71107-007
B
1
GND
4
GND
7
GND
A71107-007
1
GND
4
A
GND
7
GND
A71107-007
1X7HDR
SATA
1X7HDR
SATA
1X7HDR
SATA
J9J2
J9H3
J9H4
TXN
RXN
RXP
HDR
TXP
TXN
RXN
RXP
HDR
TXP
TXN
RXN
RXP
HDR
TXP
TXN
RXN
RXP
HDR
3 5 6
2 3 5 6
2
3
5
6
2
3
5
6
C9J9
12
10%.01UF
25V
402
C9J10
12
10%
.01UF
25V
402
M9J3
1 2
MULTI
402X7R
M9J4
1 2
MULTI
X7R 402
C8J5
12
.01UF
10%
25V
402
C8J6
12
.01UF
10%
25V
402
M8J3
1 2
MULTI
X7R 402
M8J4
1 2
MULTI
X7R 402
C9H8
12
10%.01UF
25V
402
C9H9
12
.01UF
10%
25V
402
M9J1
1 2
MULTI
402X7R
M9J2
1 2
MULTI
X7R 402
C8H16
12
10%.01UF
25V
402
C8H17
12
10%.01UF
25V
402
M8J1
1 2
MULTI
402X7R
M8J2
1 2
MULTI
402X7R
SATAHDR_TX2PSATAHDR_TX2P_R
X7R
SATAHDR_TX2NSATAHDR_TX2N_R
X7R
SATAHDR_RX2NSATAHDR_RX2N_R
SATAHDR_RX2PSATAHDR_RX2P_R
SATAHDR_TX3PSATAHDR_TX3P_R
X7R
SATAHDR_TX3NSATAHDR_TX3N_R
X7R
SATAHDR_RX3NSATAHDR_RX3N_R
SATAHDR_RX3PSATAHDR_RX3P_R
SATAHDR_TX0PSATAHDR_TX0P_R
X7R
SATAHDR_TX0NSATAHDR_TX0N_R
X7R
SATAHDR_RX0NSATAHDR_RX0N_R
SATAHDR_RX0PSATAHDR_RX0P_R
SATAHDR_TX1PSATAHDR_TX1P_R
X7R
SATAHDR_TX1NSATAHDR_TX1N_R
X7R
SATAHDR_RX1NSATAHDR_RX1N_R
SATAHDR_RX1PSATAHDR_RX1P_R
39
IN
39
IN
39
OUT
39
OUT
39
IN
39
IN
39
OUT
39
OUT
39
IN
39
IN
39
OUT
39
OUT
39
IN
39
IN
39
OUT
39
OUT
D
C
B
A
[PAGE_TITLE=SATA CONNECTORS]
8 7
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
71
4.0
D
C
B
<XR_PAGE_TITLE>
15,40,74
IN
VCC3
FIRMWARE HUB DECOUPLING
VCC3
PWRGD_3V
2 3
+12V
2
R7H16
1K 5%
CH 402
1
PN201W
1
R8H11
1 2
603
EMPTY 102276-001
BIOS_WP
Q7H2
FET
28 7 6 5 4 3 1
RECOVER/CONFIGURE HEADER
JUMPER ON 1-2 *
U8J2
FWH
L_AD[3..0]
BI
17
3
L_AD3
2
L_AD2
1
L_AD1
0
L_AD0
TP_FWH_13
TP_FWH_19
TP_FWH_20
TP_FWH_21
TP_FWH_22
PN_FWH_GPI4
PN_FWH_GPI3
FWH_GPI1_R
GPIO_DMA66_DETECT_PRI
ICH_INIT_33V
TP_FWH_9 TP_FWH_10 TP_FWH_11 TP_FWH_12
EMPTY
ALWAYS EMPTY
MFG MODE PADS
BOARDID[5..0]
4
BOARDID4
DQ4/RFU
DQ5/RFU
DQ6/RFU
DQ7/RFU
RY/BY/RFU
FGPI4
FGPI3
FGPI2
FGPI1
FGPI0
FWH3 FWH2 FWH1 FWH0
INIT
15 14 13
18
19
20
21
2223
30
3
4
5
6
24
9
ID3
10
ID2
11
ID1
12
ID0
J7J2
JUMPER
2
1
BI
JUMPER REMOVED * DEFAULT JUMPER SETTING
2
R8J8
4.7K 5%
CH 402
1
2
1
40,43,73
44
IN
40
IN
R8J4
4.7K 5%
CH 402
2
R8J13
1K 5%
CH 402
1
40,70,73
7
8
29
2
31
1
27
32
25
28
16
26
BOM NOTE:
USING IPN C55248-001
WP
TBL
IC
RST
CLK
FWH4
VPP
VCCA/NC
VCC
VCC
GNDA/NC
GND
GND
5%1K
CH
FWH_WP_C
1
1X2HDR
J8H1
2
PLTRST*
15,37,55,56,70,73
IN
CK_P_33M_FWH
29
IN
L_FRAME*
40,70,73
IN
2
C8H19
.1UF 20% 25V
1
Y5V 603
R8J6
4.7K 4025%CH
12
VCC3
R8J5
4.7KCH5% 402
R8H19
402
FWH_VPP
TP_FWH_29
5%47 CH
12
FWH_WP*
FWH_TBL*
12
FWH_RST*
MODE
NORMAL CONFIGUREJUMPER ON 2-3 RECOVERY
CONFIGURE= SAFE MODE
RECOVERY_CONFIGURE_PULLUP
39,61,80
IN
VCC3
VCC3
2
R7H15
20K 5%
CH 402
1
SPKR
R7H13
1 2
0 5%
EMPTY402
1 2 3
BAT_WARN
J8J4
1X3HDR
HDR
BOM NOTE:
FOR YELLOW JUMPER USE IPN 634479-005
D
C
43
IN
B
IC
2
1
A
2
C8H20
.1UF 20% 25V EMPTY 603
C7H11
.1UF 20% 25V
1
Y5V 603
8 7
2
C7J1
.1UF 20% 25V
1
Y5V 603
A
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
72
4.0
<XR_PAGE_TITLE>
V_3P3_STBY
VCC3
R2J15
1
2
SMSC_VCC3_OR_TPM_HDR
5%
0
BOM NOTE:
PA_FDD_DRVDEN0 PA_FDD_DRVDEN1
PA_FDD_MTR0*
PA_FDD_DS0* PA_FDD_DIR*
PA_FDD_STEP* PA_FDD_WDATA*
PA_FDD_WGATE*
PA_FDD_HDSEL* PA_FDD_INDEX*
PA_FDD_TRK0* PA_FDD_WRTPRT*
PA_FDD_RDATA*
PA_FDD_DSKCHG*
L_AD[3..0]
L_FRAME*
PA_PLTRST*
CK_P_33M_PA
PA_COM_RXD1
PA_COM_TXD1
PA_COM_DSR1* PA_COM_RTS1*
PA_COM_CTS1* PA_COM_DTR1*
PA_COM_RI1*
PA_COM_DCD1*
CK_14M_PA
SUSCLK
STUFF FOR SMSC
0
L_AD0
1
L_AD1
2
L_AD2
3
L_AD3
D
R2J1
R7J2
CH 402
12
5%10K
402CH
12
5%10K
V_3P3_STBY
IN
IO_PME*
VCC3
R1J9
12
10K 5%
402
C
40
15,37,55,56,70,72 40,70
40,70,81
B
A
2
C1J1
.1UF 20% 25V
1
Y5V 603
CH
R1J11
12
10K 5%
402CH
L_DRQ*
OUT
PLTRST*
IN
LPCPD*
IN
SER_IRQ
BI
V_3P3_STBY
IN
2
1
2
C2J6
.1UF 20% 25V
1
Y5V 603
DESIGN NOTE:
SIGNAL QUALITY OPTION
C2J4
.1UF 20% 25V Y5V 603
2
C2J11
.1UF 20% 25V
1
Y5V 603
R8H8
0 5% CH 402
2
C9F10
.1UF 20% 25V
1
Y5V 603
C8H12
.1UF 20% 25V EMPTY
"Y5V"
BOM NOTE:
STUFF ONLY FOR PA3T
402
603
R1J8
1 2
EMPTY
40,70,72
12
2
1
5%1K
78
78
78
78
78
78 78 78
2
C1J5
.1UF 20% 25V
1
Y5V 603
40
OUT
75
OUT
75
OUT
75
OUT
75
OUT
75
OUT
75
OUT
75
OUT
75
OUT
75
OUT
75
IN
75
IN
75
IN
75
IN
75
IN
BI
40,70,72
IN
29
IN
78
IN
78
OUT
78
IN
78
OUT
78
IN
78
OUT
78
IN
78
IN
29
IN
40
IN
PA_COM_RXD2
IN
PA_COM_TXD2
OUT
PA_COM_DSR2*
IN
PA_COM_RTS2*
OUT
PA_COM_CTS2*
IN
PA_COM_DTR2*
OUT
PA_COM_RI2*
IN
PA_COM_DCD2*
IN
VCC3
2
C1J6
.
.1UF 20% 25V
1
Y5V 603
CH 402
SERIAL 1
FAN
V_3P3_STBY<3> V_3P3_STBY<2> V_3P3_STBY<1>
GPIOPS/2PARALLEL
VCC3<5> VCC3<4> VCC3<3> VCC3<2> VCC3<1>
KBDRST*
INITP*
SLCTIN*
ERROR*
STROBE*
GP16/TACH1 GP17/TACH2
PA
SIO
GP10 GP11 GP12 GP13 GP14 GP15
KDAT KCLK MDAT MCLK
GA20M
PD<0> PD<1> PD<2> PD<3> PD<4> PD<5> PD<6> PD<7>
SLCT
BUSY ACK*
ALF*
IRTX2 IRRX2
U1J1A
DRVDEN0 DRVDEN1 MTR0* DS0* DIR* STEP* WDATA* WGATE* HDSEL* INDEX* TRK0* WRTPRT* RDATA* DSKCHG*
IO_PME*
LAD<0> LAD<1> LAD<2> LAD<3>
LFRAME* LDRQ* PCI_RESET* LPCPD* PCI_CLK SER_IRQ
RXD1 TXD1 DSR1* RTS1* CTS1* DTR1*/XOR RI1* DCD1*
CLOCKI14 CLOCKI32
VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1>
RXD2 TXD2 DSR2* RTS2* CTS2* DTR2* RI2* DCD2*
NC=129
PORT ANGELES 1.6
FLOPPY
LPC
CLOCK
SERIAL 2
1 OF 2
C54396-002
22 21 19 18 17 16 15 14 10 20 13 12 11
9
99
62 61 59 57
56 54 63 52 55 53
25 27 24 26 28 30 32 23
65 91
110
96 78 58 46 29
8
119 120 121 122 124 125 118 126
IR HEADER
ADD IR HEADER CIRCUIT
29,38..41,43,55,56,74,79,87,88,90,92,93,95,105,106
IN
VCC3
J2J1
1X3HDR
EMPTY
BOM NOTE:
STUFF ONLY FOR PA3T
PA_KBDATA
PA_KBCLOCK
PA_MSDATA PA_MSCLOCK
PA_LPT_INIT*
PA_LPT_SLCTIN*
PA_LPT_PD[7..0]
PA_LPT_SLCT
PA_LPT_PE
PA_LPT_BUSY PA_LPT_ACK*
PA_LPT_ERR* PA_LPT_ALF*
PA_LPT_STROBE*
TP_CPU_FAN_TACH
TP_ATX_FAN_TACH
1 2 3
OUT
BI
BI BI BI BI
BI
OUT
BI
IN IN IN IN
IN OUT OUT
BOARDID[5..0]
5
BOARDID5
76 76 76 76
77 77
77
77 77 77 77 77 77 77
402
R3J1
1 2
EMPTY
IN
5%2.2K
BI
1-WATT
LAN_OR_FAN*
VCC3
123 60 49 31 6 107 93 76
103
TP_PA_SENSOR_SDA
104
TP_FRONT_FAN_TACH
105
LAN_OR_FAN*
106
TP_CPU_FAN_CTRL
108 109
FNT_REAR_FAN_CTRL_PD
4 3 2 1 7 5
48 47
44
0
PA_LPT_PD0
43
1
PA_LPT_PD1
42
2
PA_LPT_PD2
41
3
PA_LPT_PD3
40
4
PA_LPT_PD4
39
5
PA_LPT_PD5
38
6
PA_LPT_PD6
37
7
PA_LPT_PD7
33 34
PE
35 36 45 50 51
111 112
VCC3
OPT_IR_HDR_E IR_HDR
C2J12
470PF 10% 50V EMPTY 603
12
R2J17
IR_HDR OPT_IR_HDR
603 10K EMPTY 5%
1
2
OPT_IR_HDR_E IR_HDR
C2J10
470PF 10% 50V EMPTY 603
VCC
1
2
OPT_IR_HDR_E
IR_HDR
C2J9
470PF 10% 50V EMPTY 603
NOTE:
PULLS GPIO LOW AT POWERUP SINCE GPIO DEFAULT IS INPUT
128
PA_IRTX2
127
PA_IRRX2
IC
IR_HDR
OPT_IR_HDR
1X5HDR2
102276-006
J1J4
EMPTY
1
3 4 5
1
2
PLACE NEAR DEVICE PINS 6,31,49,60,76,93,107
8 7
45
36
28 7 6 5 4 3 1
BIOS DETECTS ADDRESS WITHOUT STUFFING. GPIO CONFIGURATION STRAP @ POWER-ON
FNT_REAR_FAN_CTRL_PD
OUT
40,43,72
90
OUT
VCC3
R7H5
12
5%10K
CH 402
R7H8
12
10K 5% CH
402
KBRST*
A20GATE
55,74
IN
OUT OUT
R2J12
EMPTY0402
R2J14
CH0402
LAN_DISABLE*
40
40
5%
5%
[PAGE_TITLE=PORT ANGELES (1 OF 2)]
INTEL
CONFIDENTIAL
2 1
R2J9
12
4.7K EMPTY5%402
12
12
LAN_DISABLE*
402
R8A4
1 2
OUT
55,74
5%10K CH
DOCUMENT NUMBER PAGE REV
C77862
73
D
C
B
A
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
32,39,49..51,56,79
C
B
A
32,39,49..51,56
IN
21,25,29
21,25,29
20
20 15,18 15,18
81 81 81
44
7,40,43,81,101
V_3P3_STBY
IN
39
40,88 43
BI BI BI BI
BI BI BI BI
OUT OUT
OUT IN IN
IN
IN IN
SMB_CLK_MAIN SMB_CLK_RESUME SMB_DATA_MAIN SMB_DATA_RESUME
DDCSDA_5V DDCSCL_5V MCH_DDC_DATA MCH_DDC_CLK
GPIO_GRN_BLNK_HDR GPIO_YLW_BLNK_HDR HD_LED* IDE_PRI_ACT* ICH_SATA_LED*
FP_RST*
SLP_S3* SLP_S4*
41,43
44
90,103
8 7
V_3P3_STBY
29,38..41,43,55,56,73,79,87,88,90,92,93,95,105,106
IN
IN
IN
IN
2
R2H5
2.7K 5%
CH 402
1
R2J4
1 2
0
402 EMPTY
CAD NOTE:
PLACE AS CLOSE TO PIN AS POSSIBLE
V_REF5V IDE_RST* BACKFEED_CUT
2
R2H3
2.7K 5%
CH 402
1
5%
BOM NOTE:
NEVER STUFF
V_3P3_STBY
2
C2J3
.1UF 10% 16V
1
X7R 603
VCC VCC
2
R1J1
1K 5%
CH 402
1
IN
2
R1J3
1K 5%
CH 402
1
VCC3
2
R2H6
8.2K 5%
CH 402
1
PA_TESTEN_1
PA_F_CAP
2
1
SCSI_ACT*
C2J2
4.7UF 20% 10V Y5V 805
2
1
R1H7
1K 5%
CH 402
2
R2H4
8.2K 5%
CH 402
1
41,57,66,78,81,86,90..95
87
SMB_CLK_M
88
SMB_CLK_R
89
SMB_DAT_M
90
SMB_DAT_R
116
5V_DDCSDA/GP20
114
5V_DDCSCL/GP21
115
3V_DDCSDA/GP22
113
3V_DDCSCL/GP23
GRN_LED
95
YLW_LED
66
HD_LED*
67
PRIMARY_HD*
68
SECONDARY_HD*
69
SCSI*
75
FPRST*
85
SLP_S3*
86
SLP_S5*
98
TEST_EN1
97
F_CAP
NC=129
OUT
IN
IN
U1J1B
PORT ANGELES 1.6
VGA DDC VT
LED
2 OF 2
C54396-002
SCSI_ACT*
TP_SCSI_ACT_PIN2
POWERPWR SEQ
CDC_DWN_ENAB/GP24*
PWRGD_PLATFORM
BACKFEED_CUT*
LATCHED_BF_CUT
AUD_LINK_RST*
1
2
IN
BOM NOTE:
STUFF FOR PA3.0
V_5P0_STBY
PA
SIO
71
V_5P0_STBY
72
REF_5V_STBY
70
REF_5V
84 82
PWRGD_PS
73
PCIRST_OUT*
74
PCIRST_OUT2*
64
IDE_RSTDRV*
9294
RSMRST*
77 79 80
SCK_BJT_GATE
81
PS_ON*
83
CPU_PRESENT*
100 101 102
CDC_DWN_RST*
117
NC
IC
J1J1
1X2HDR
EMPTY
PWRGD_3V_PA
R2J8
1 2
5%
0
402
EMPTY
2
1
TP_PCIRST_OUT2_R*
TP_SCK_BJT_GATE
PA_102
R1H6
1K 5%
CH 402
DEBUG/EV FEATURE: POWER-ON FORCING HEADER
V_REF5V_SUS_SIO V_REF5V
PWRGD_3V_PA PWRGD_PS
P_RST_SLOTS_R*
IDE_RST* ICH_RSMRST*
BACKFEED_CUT LATCHED_BACKFEED_CUT
PS_ON_SIO* SLOTOCC*
LAN_DISABLE_CTRL*
PA_GPIO12
2
C2J1
1.0UF
STUFF FOR PA3.0, EMPTY FOR PA1.6
20% 10V
1
EMPTY 603
EMPTY THESE FOR PA1.6 OR 3.0
29,38..41,43,55,56,73,79,87,88,90,92,93,95,105,106
IN
45
V_3P3_STBY
100K
402 EMPTY
86
STUFF FOR PA1.6 OR 3.0 EMPTY FOR PA1.5
6
R1H2
LAN_DISABLE*LAN_DISABLE_CTRL*
IN
5%
OUT
402
H_SKTOCC*
12
I_PWRGD_3V_PA
R1H1
0
OUT OUT
OUT
86
IN
OUT OUT
OUT OUT
OUT
IN
OUT
86
IN
1 2
402 EMPTY
2
C1H10
1.0UF 20% 10V
1
EMPTY 603
PS_ON_SIO*
12
5%
CH
36
41
44 39,40,55
89,90
86
R1H5
5%10K
MBT3904DUAL
"Y5V"
41,43
90,103
Q1H1
5
IN
SLOTOCC*
V_5P0_STBY
2
C1J2
.1UF 20% 25V
1
Y5V 603
OUT
D
41,57,66,78,81,86,90..95
55,73
OUT
R1H9
1
0 5%
2
CH 402
SLOTOCC*
C
R1J2
3
4
1 2
33
402 CH
VCC3
2
R1H4
1K 5%
EMPTY 402
1
I_3P3_STBY_74
6
EMPTY
1
2
P_RST_SLOTS*
5%
2
C1J3
47PF 5% 50V
1
COG 402
PWRGD_PS
32,51
OUT
86
IN
OLD PWRGD PATH
PWRGD_PS
2
1
R8J10
0 5%
EMPTY 402
NEEDS TO BE VOLT. DIVIDED DOWN FROM 5V
TO 3.3V
PWRGD_3V
2
R8J9
0 5%
EMPTY 402
1
OUT
B
15,40,72
A
[PAGE_TITLE=PORT ANGELES (2 OF 2)]
INTEL
CONFIDENTIAL
2 1
DOCUMENT NUMBER PAGE REV
C77862
74
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
PLACE NEAR
FDD CONN
C
B
PA_FDD_DRVDEN0
73
IN
PA_FDD_DRVDEN1
73
IN
PA_FDD_INDEX*
73
OUT
PA_FDD_MTR0*
73
IN
PA_FDD_DS0*
73
IN
PA_FDD_DIR*
73
IN
PA_FDD_STEP*
73
IN
PA_FDD_WDATA*
73
IN
PA_FDD_WGATE*
73
IN
PA_FDD_TRK0*
73
OUT
PA_FDD_WRTPRT*
73
OUT
PA_FDD_RDATA*
73
OUT
PA_FDD_HDSEL*
73
IN
PA_FDD_DSKCHG*
73
OUT
VCC
D
2
R2J6
1K 5%
CH 402
2
R2J11
1K 5%
CH 402
1
1
2
1
R2J13
1K 5%
CH 402
2
R2J10
1K 5%
CH 402
1
2
R2J16
1K 5%
CH
1
402
TP_301S
TP_302S
TP_303S
2X17HDR_3_5
1 2
KEY
4
KEY
6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
J4J1
P1 P2
P4
P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34
C
B
HDR
A
A
[PAGE_TITLE=FDD CONN]
DOCUMENT NUMBER PAGE REV
C77862
75
4.0
8 7
INTEL
CONFIDENTIAL
45
36
2 1
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
COMPONENTS ARE DFM29
D
IN
PLACE NEAR
PS/2 CONN
VREG_PS2
123 456
CRP1A1
TVS6_2V
6.2V EMPTY
TP_401S
TP_402S
2
1
TP_403S
TP_404S
C1A7
1UF 20%
6.3V X5R 603
PS2 KEYBOARD
PS2 STACK
1 2 3 4 5 6
7 8 9
10 11 12
J1A1
P1 P2 P3 P4 P5 P6
P7 P8 P9 P10 P11 P12
MOUSE
P13 P14 P15 P16 P17
CONN
749231-001
13 14 15 16 17
2
R1A4
2.7K 5%
CH 402
1
2
R1A3
2.7K 5%
CH 402
1
2
R1A6
2.7K 5%
CH 402
1
2
R1A5
2.7K 5%
CH 402
1
R1A8
402 CH
R1A7
0 5%
402
R1A2
402 CH
R1A1
0 5%
402
12
5%0
12
CH
12
5%0
12
CH
SIO_KBDATA_FB
SIO_KBCLOCK_FB
SIO_MSDATA_FB
SIO_MSCLOCK_FB
2
C1A2
470PF 10% 50V
1
X7R 402
2
C1A3
470PF
2
10%
C1A4
50V
1
470PF
X7R
10%
402
50V
2
1
X7R
C1A1
402
470PF
2
10%
C1A6
50V
1
470PF
X7R
10%
402
50V
1
X7R 402
91
PA_KBDATA
73
BI
PA_KBCLOCK
73
BI
C
PA_MSDATA
73
BI
PA_MSCLOCK
73
BI
B
D
C
B
PLACE AS CLOSE TO PS/2 CONNECTOR AS POSSIBLE
A
DOCUMENT NUMBER PAGE REV
C77862
76
8 7
INTEL
CONFIDENTIAL
45
36
2 1
A
4.0
<XR_PAGE_TITLE>
IN
R3A15
CH 402
R3A6
CH 402
R3A7
R3A8
33 5% CH 402
PA_LPT_ACK* PA_LPT_BUSY PA_LPT_PE PA_LPT_SLCT PA_LPT_ERR*
PA_LPT_PD[7..0]
12
5%33
12
5%33
12
5%33
402CH
12
VCC
SIO_LPT_STROBE_R*
SIO_LPT_ALF_R*
SIO_LPT_INIT_R*
SIO_LPT_SLCTIN_R*
VCC
R2A5
6
PA_LPT_PD6
SIO_LPT_PD5_R
2
R3A2
2.7K 5%
CH 402
1
2
R2A1
10K 5%
CH 402
1
R2A6
R3A11
33CH5%
7
PA_LPT_PD7
2
1
R3A12
33 5%
R2A3
10K 5%
CH 402
R3A9
402CH
R3A14
2
R3A1
2.7K 5%
CH 402
1
0
PA_LPT_PD0
1
PA_LPT_PD1
2
PA_LPT_PD2
3
PA_LPT_PD3
4
PA_LPT_PD4
5
PA_LPT_PD5
2
R2A2
10K 5%
CH 402
1
33 5%
12
CH
2
R2A4
10K 5%
CH 402
1
12
402CH
SIO_LPT_PD3_R
12
5%33
402
2
R3A3
2.7K 5%
CH 402
1
33 CH
402
R3A13
33 5% CH
2
R3A5
10K 5%
CH 402
1
12
SIO_LPT_PD7_R
5%
402
SIO_LPT_PD0_R
12
12
402
2
R3A4
2.7K 5%
CH 402
1
R3A10
33CH5%
SIO_LPT_PD2_R
SIO_LPT_PD4_R
402
PLACE NEAR
2
LPT CONN
C2A14
220PF 10% 50V
1
X7R 402
33CH5%
12
SIO_LPT_PD1_R
2
C2A13
220PF 10% 50V
1
X7R 402
12
SIO_LPT_PD6_R
402
2
C2A11
220PF 10% 50V
1
X7R 402
2
C2A12
220PF 10% 50V
1
X7R 402
2
1
2
C2A10
220PF 10% 50V
1
X7R 402
C2A9
220PF 10% 50V X7R 402
2
C3A12
220PF 10% 50V
1
X7R
C3A13
220PF 10% 50V X7R 402
402
2
1
2
1
2
C3A11
220PF 10% 50V
1
X7R 402
C3A6
220PF 10% 50V X7R 402
2
C3A5
220PF 10% 50V
1
X7R 402
2
C3A10
220PF 10% 50V
1
X7R 402
73
D
C
PA_LPT_STROBE*
73
IN
PA_LPT_ALF*
73
IN
PA_LPT_INIT*
73
IN
PA_LPT_SLCTIN*
73
IN
B
73
OUT
73
OUT
73
OUT
73
OUT
73
OUT
A
28 7 6 5 4 3 1
2
1
2
C3A8
220PF 10% 50V
1
X7R 402
2
C3A7
220PF 10% 50V
1
X7R
C3A9
220PF 10% 50V X7R 402
402
2
1
C3A4
220PF 10% 50V X7R 402
D
C
B
749179-001
J3A2
DSUB 25TALL
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9 22 10 23 11 24 12 25 13
DSUB
GND=26,27,28
A
2
C3A3
220PF 10% 50V
1
X7R 402
8 7
[PAGE_TITLE=LPT CONN]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
77
4.0
<XR_PAGE_TITLE>
DO NOT USE NATIONAL OR GOLDSTAR PARTS OF THIS BASE P/N
D
OUT
PA_COM_CTS1*
73
OUT
PA_COM_RI1*
73
OUT
PA_COM_RTS1*
73
IN
PA_COM_TXD1
73
IN
PA_COM_DTR1*
73
IN
PA_COM_DCD1*
73
OUT
PA_COM_DSR1*
73
OUT
PA_COM_RXD1
73
+12V -12V
C
2
C1H9
.1UF 20% 25V
1
Y5V 603
PLACE DECOUPLING NEAR 232 CNTRL/DRIVER PINS 1, 10, AND 20 RESPECTIVELY
202341-002
2
1
C1H4
.1UF 20% 25V Y5V 603
202341-002
+12V
19 18 17 14 12 16 15 13
1
NOTE DIRECTION
VCC=V_5P0_STBY
U1H1
GD75232S
RY1 RY2 RY3 RY4 RY5
VDD+ VDD-
DY1
DA1
DY2
DA2
DY3
DA3
IC
VCC=20 GND=11
41,57,66,74,81,86,90..95
IN
621111-103
2
RA1
3
RA2
4
RA3
7
RA4
9
RA5
5 6 8 10
V_5P0_STBY
202341-002
-12V
2
1
SIO_COM_DCD1_232 SIO_COM_DSR1_232 SIO_COM_RXD1_232* SIO_COM_RTS1_232 SIO_COM_TXD1_232* SIO_COM_CTS1_232 SIO_COM_DTR1_232
VCC
V_5P0_STBY
IN
41,57,66,74,81,86,90..95
SIO_COM_RI1_232
IN
COM_RI_WAKE*
2
1
C2A8
470PF 10% 50V X7R 402
2
1
C2A7
470PF 10% 50V X7R 402
2
1
C2A6
470PF 10% 50V X7R 402
2
1
C2A3
470PF 10% 50V X7R 402
2
1
C2A1
470PF 10% 50V X7R 402
2
C2A5
470PF 10% 50V
1
X7R 402
2
1
C2A4
470PF 10% 50V X7R 402
2
C2A2
470PF 10% 50V
1
X7R 402
PLACE NEAR CONNECTOR
R8D2
WOM_CTRL
1 2
10K 5%
C9D5
603 EMPTY
.1UF 20% 25V Y5V 603
R8D1
2.2K
5%
1 2
603 EMPTY
3
Q8D1
1
MMBT3904 EMPTY
2
108969-001
COM1 WAKE_ON_MODEM_E
COM_RI_WAKE*
40,43
OUT
41,57,66,74,81,86,90..95
IN
WAKE_ON_MODEM
OPT_WOM_HDR
V_5P0_STBY
J9G2
1X3HDR
EMPTY
1 2 3
28 7 6 5 4 3 1
R2A7
1 2
0 5%
402 EMPTY
R1J6
ENABLE_5V_1
1 2
330 5%
402 EMPTY
R1J10
1 2
330 5%
402 CH
123
1X3HDR
J1J2
HDR
40,43
SERIAL PORT A
J2A1
749218-001
2 ROW
10
1
6
2
7
3
8
4
9
J2A1_GND
5
11
SMC0402
2
C1A5
470PF 10% 50V
1
Y5V 402
1-2 = ENABLE 5V ( DISABLE WOR ) 2-3 = DISABLE 5V ( ENABLE WOR ) 2-3 = DEFAUL
DSUB
D
C
BOM=CORE_COM1
OPT_COM2
COM2
U1G1
73
PA_COM_DCD2* PA_COM_DCD2_232
OUT
73
B
PA_COM_DSR2*
OUT
73
PA_COM_RXD2
OUT
73
PA_COM_CTS2*
OUT
73
PA_COM_RI2*
OUT
73
PA_COM_RTS2*
IN
73
PA_COM_TXD2
IN
73
PA_COM_DTR2*
IN
+12V -12V
A
+12V -12V
COM2_DCPL
OPT_COM2
202341-002
12
C1G4
.1UF 20% 25V EMPTY 603
PLACE NEAR 232'S PINS 1, 10, AND 20 RESPECTIVELY BOM= OPT_COM2
12
19 18 17 14 12 16 15 13
1
NOTE DIRECTION
41,57,66,74,81,86,90..95
COM2_DCPL
OPT_COM2
202341-002
C1G7
.1UF 20% 25V EMPTY 603
GD75232S
RY1 RY2 RY3 RY4 RY5
VDD+ VDD-
DA1 DA2 DA3
VCC=20 GND=11
VCC=V_5P0_STBY
V_5P0_STBY
IN
DY1 DY2 DY3
EMPTY
RA1 RA2 RA3 RA4 RA5
2 3 4 7 9 5 6 8 10
OPT_COM2
202341-002
12
C1H6
.1UF 20% 25V EMPTY 603
COM2_DCPL
12
OPT_COM2
COM2
C1G2
470PF 10% 50V EMPTY 402
ADD COM2 HEADER CIRCUIT
PA_COM_DSR2_232 PA_COM_RXD2_232* PA_COM_CTS2_232 PA_COM_RI2_232 PA_COM_RTS2_232 PA_COM_TXD2_232*
12
OPT_COM2
COM2
C1G3
470PF 10% 50V EMPTY 402
12
OPT_COM2
COM2
C1G5
470PF 10% 50V EMPTY 402
12
C1G11
470PF 10% 50V EMPTY 402
OPT_COM2
COM2
12
OPT_COM2
COM2
C1G9
470PF 10% 50V EMPTY 402
12
OPT_COM2
COM2
C1G6
470PF 10% 50V EMPTY 402
PA_COM_DTR2_232
OPT_COM2
COM2
C1G8
12
470PF 10% 50V EMPTY 402
12
OPT_COM2
COM2
C1G10
470PF 10% 50V EMPTY 402
41,57,66,74,81,86,90..95
R1G4
1 2
0 5%
402 EMPTY
VCC
R1J4
ENABLE_5V_2
1 2
330 5%
402 EMPTY
R1H3
1 2
V_5P0_STBY
IN
330 5%
402 EMPTY
123
1X3HDR
J1H1
EMPTY
[PAGE_TITLE=SERIAL PORT A]
INTEL
CONFIDENTIAL
8 7
45
36
2 1
COM2 OPT_COM2
J1G2
SERIAL PORT
2X5HDR_10
1
P1
2
P2
3
P3
4
P4
5
P5
6
P6
7
P7
8
P8
J2H1_GND
9
P9 KEY
EMPTY
SERIAL PORT B
SMC0402
2
C1G14
470PF 10% 50V
1
EMPTY 402
1-2 = ENABLE 5V ( DISABLE WOR ) 2-3 = DISABLE 5V ( ENABLE WOR ) 2-3 = DEFAUL
DOCUMENT NUMBER PAGE REV
C77862
B
A
78
4.0
<XR_PAGE_TITLE>
HECETA6 WILL BE EMPTY & "SATELLITE" HECETA WILL BE STUFFED IF PORT ANGELES 3.0 IS STUFFED
28 7 6 5 4 3 1
CAD NOTE: SOUTHEAST THERMAL ZONE SENSOR
D
PLACE BELOW DIMMS
3
Q2F1
1
MMBT3904 XSTR
2
108969-001
32,39,49..51,56,74
2
C2F7
100.0PF 5% 50V
1
COG 603
603275-120
C
DEFAULT: HECETA6 CIRCUITRY STUFFED W/PA1.5
B
CAD NOTE:
10MIL TRACE ON SE_ZONE_TDN AND _TDP
6
6
BI IN
OUT
IN
SENSOR_SDA SMB_CLK_RESUME
H_TEMP_RET
H_TEMP_RET_HEC
H_TEMP_SRC
H_TEMP_SRC_HEC SE_ZONE_TDP SE_ZONE_TDN
H6_TAC4_PD
12
R2F34
10K 5%
EMPTY 402
R1F12
1 2
402
R1F9
1 2
402
CPU_FAN_CTRL
5%0 CH
5%CH0
TP_HECETA6_19
TP_V_1P5_CORE
TP_VCCP
TP_SENSOR_SDA
PRELIMINARY
PWM1/NTESTOUT
1
SDA
2
SCL
18
REMOTE1+
17
REMOTE1-/NTESTIN
16
REMOTE2+
15
REMOTE2-
19
VID4
8 9
VID3
7
VID2
6
VID1
5
C58244-001
83
OUT
U2F1
HECETA6
V_3P3_STBY
29,38..41,43,55,56,73,74,87,88,90,92,93,95,105,106
IN
BOM NOTE:
DEFAULT FOR S3 SUPPORT
BOM NOTE:
OPTION FOR "NO-WAKE"
VCCP_IN
3.3SBY
TACH1 TACH2 TACH3 TACH4
2.5V
PWM2 PWM3
D
VCC
2324 22 20
5V
4 21
12V
10 13
11 12
14
3
GNDVID0
IC
R2F22
1 2
5%0 EMPTY
402
VCC3
R2F30
1 2
5%0
402
CH
VCCP V_1P5_CORE
H4_H6_V_3P3STBY
TP_PWM2_H6
FNT_REAR_FAN_CTRL
CPU_FAN_TACH ATX_FAN_TACH FRONT_FAN_TACH REAR_FAN_TACH
H4_H6_V_3P3STBY
2
C2F5
.1UF 20% 25V
1
Y5V 603
H4_H6_V_3P3STBY
IN IN
IN
OUT
IN
OUT
IN IN
R9J10
5.6K 5%
OUT
+12V
97 96
12,15..17,38,39,41,87,88,102
83
83
83 83 83
12
402EMPTY
Stuff R9J10 for uATX
Empty for ATX
C
B
A
BOM NOTE:
OPTION FOR "SATELLITE HECETA" WHEN PORT ANGELES 3.0 IS USED
8 7
A
[PAGE_TITLE=HARDWARE MANAGEMENT: HECETA]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
79
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
BOM NOTE:
STUFF TO DISABLE NO-REBOOT OPTION AT POWER-UP (CONFIGURATION STRAPPING).
SPKR
39,61,72
C
IN
VCC3
2
1
R9C6
1K 5%
EMPTY 402
R9C5
4021KCH
VCC
3
5%
2
C9D1
1000PF 10% 50V
1
EMPTY 603
"X7R"
CORE_SPKR_R
12
Q9D1
1
MMBT3904 XSTR
2
108969-001
SPKR_OUT
2
R9C7
47 5%
EMPTY 402
1
LS9C1
XDCR
1
+
AT-08
2
IN
D
C
DIAGNOSTIC LED (RED)
1
UNNAMED_80_NPN_I32_B
VCC3
2
1
OPT_DIAGLED OPT_DIAGLED
R7G2
220 5%
EMPTY 402
UNNAMED_80_LED_I31_A
716805-005
2
CR7G1
Default EMPTY
OPT_DIAGLED
UNNAMED_80_LED_I31_C
1
OPT_DIAGLED
3
Q7G2
MMBT3904 EMPTY
OPT_DIAGLED
2
OPT_DIAGLED
B
VCC3
OPT_DIAGLED
2
OPT_DIAGLED
R7G4
4.7K 5%
EMPTY 402
1
OPT_DIAGLED
40
ICH_GPO19*
IN
OPT_DIAGLED
1 2
402
R7G3
EMPTY
5%220
A
B
A
8 7
[PAGE_TITLE=SPEAKER_DIAGNOSTIC_LED]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
80
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
R9J6
10KCH5% 402
R9J11
402
12
47,85,91,93,94
IN
12
5%330 CH
VCC
VCC_HDLED_PWR
5VDUAL
R9J12
1 2
0 1A
603
R9J13
1 2
0 1A
603
EMPTY
CH
SIO_IRRX2
VCC3
BOM NOTE: UNSTUFF FOR C
VCC
HD_LED_G*
IN
7,40,43,74,101
FP_RST*
OUT
C
BOM NOTE FOR J9J4:
USE IPN 109717-756 FOR 2X5 MULTI-COLOR HDR
USE IPN 109717-742 FOR 2X5 WHITE HDR
SIO_IRTX2
J9J4
2X8HDR_10_14
1 2 3 4 5 6 7 8
9 11 12 13 15 16
HDR
41,57,66,74,78,86,90..95
SW_ON_R*
VCC
V_5P0_STBY
IN
74
GPIO_YLW_BLNK_HDR
IN
74
GPIO_GRN_BLNK_HDR
IN
OUT
R9J9
12
5%
1K
CH402
R9J8
12
5%1K CH402
49,50
ADD SERIRQ HDR CIRCUIT
1X2HDR
J8C3
1
EMPTY 102276-001
SERIRQ
TP_SERIRQ_TEST
2
SERIRQ SER_IRQ
IN
12
1X2HDR
R8C2
5% EMPTY 402 0
SER_TEMP
J8C1
EMPTY
SERIRQ
1 2
107555-102
D
40,70,73
BI
C
VCC
2
C9J12
470PF 10% 50V
1
EMPTY 402
B
BOM=CORE_STDFNTPNL_E
DESIGN NOTE: STUFF ONLY FOR
ENERGY LAKE, THEN EMPTY 0 OHM BYPASS.
J9J3
1X3HDR2
A
102276-304
1
3
HDR
2
C9J11
470PF 10% 50V
1
EMPTY 402
2
C9J6
470PF 10% 50V
1
EMPTY 402
SB
PWR_LED_E
GPIO_GRN_BLNK_HDR
GPIO_YLW_BLNK_HDR
R1H8
10K 5% 402
A36093-023
EMPTY
602431-005
12
2
C9J3
470PF 10% 50V
1
EMPTY 603
"X7R"
PWR_LED_E
1
UNNAMED_81_NPN_I150_B
IN
IN
2
1
3
Q1J1
MMBT3904 EMPTY
2
C9J4
SB
470PF 10% 50V EMPTY 402
74
74
HD_LED_G*
R1J5
1
0 5%
CH
2
402
2
C9J2
1
HD_LED*
470PF 10% 50V EMPTY 402
2
C9J5
470PF 10% 50V
1
EMPTY 402
OUT
74
IN
DESIGN NOTE:
SHARED WITH LED 1X3 HEADER
IN
2
C9J8
470PF 10% 50V
1
EMPTY 603
SW_ON_R*
2
C9J7
470PF 10% 50V
1
EMPTY 603
B
R9J4
33
402
A36093-005
12
5% CH
SW_ON*
2
C9J1
1.0UF 20% 10V
1
Y5V 603
40,43
OUT
A
DESIGN NOTE:
IF LED HEADER IS NOT PLACED RIGHT NEXT TO FP HEADER, THEN NEED TO ADD A 470UF 0603 CAP TO EACH OF THESE SIGNALS. OTHERWISE, THEY CAN SHARE CAP WITH FP HEADER PINS 2 AND 4...
8 7
[PAGE_TITLE=STD_FRONT_PANEL_HDR]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
81
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
PB MOUNTING HOLES
C
B
LABELS
200956-001; "CE" MARK SHOULD BE COVERED WITH A BLANK LABEL UNTIL CERTIFIED 628492-001; "FCC" MARK SHOULD BE COVERED WITH A BLANK LABEL UNTIL CERTIFIED (SECONDARY SIDE) 622954-001; "C-TICK" MARK SHOULD BE COVERED WITH A BLANK LABEL UNTIL CERTIFIED
LB4F2
EMPTY
LB3F1
LABEL
LABEL
1
A
1
LB4F1
LABEL
1
A19202-001
EMPTY
'KOREAN CERT' SILKSCREEN COVERED UNTIL CERTIFIED
SILK
MAKE EMPTY ON BOM
C69649-001
1375X250_TARGET
CHANGE TO PROJECT ISN ON BOM (MOD-FILE CHANGE): CXXXXX-001
'INTEL-BRANCH"
MAKE EMPTY ON BOM
8 7
J8A1
MTG_HOLE
NC9
J1G1
MTG_HOLE
NC9
J7G1
MTG_HOLE
NC9
J7A1
MTG_HOLE
NC9
J11G1
MTG_HOLE
NC9
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
D
J7J1
9
9
9
MTG_HOLE
NC9
J1B1
MTG_HOLE
NC9
J1J3
MTG_HOLE
NC9
9
EMPTY
9
EMPTY
9
PCI-EXPRESS X16
SPD ADD: ??
PCI-EXPRESS X1
SMBUS MAP
PCI SLOTS
SPD ADD: N/A
C
EMPTY
J9G1
9
MTG_HOLE
NC9
9
LAN TPM
SPD ADD: N/A
HECETA
SPD ADD: N/ASPD ADD: N/A
EMPTY
DIMMS
9
ICH
SMB_CLK/DATA_MAIN
CLOCK PORT ANGELES
DIMMS (2 TIMES)
SMB_CLK/DATA_RESUME
PWRGD_PS
PORT ANGELES
SMB_CLK/DATA_MAIN
SMB_CLK/DATA_RESUME
PCI (2 TIMES) LAN HECETA PORT ANGELES ICH PCI-EXPRESS X16 PCI-EXPRESS X1 SECURITY (TPM)
SPD ADD: A0, A2, A4, A6
CLOCK
SPD ADD: D3 D2
B
A
[PAGE_TITLE=MTG_HOLES/LABELS/SMBUS_MAP]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
82
4.0
<XR_PAGE_TITLE>
D
C
79
IN
B
A
FAN CONTROL
BOM NOTE:
STUFF FOR 3-PIN CONTROLLED FAN
79
CPU_FAN_CTRL
IN
VCC3
2
PA
BOM NOTE:
ALWAYS STUFF. FOR HECETA6 SMBUS ADDRESS
R2F36
2.2K 5%
CH 402
1
FNT_REAR_FAN_CTRL
FAN_FRONT_REAR_NO_CNTL
R2F44
12
5%
0
EMPTY
402
BOM NOTE:
STUFF FOR 4-PIN FAN OR 3-PIN ALWAYS ON
8 7
VCC3
2
FAN_CPU_CNTL
R1F4
2.2K 5%
EMPTY 402
1
FAN_FRONT_REAR_CNTL
R2F35
2.2KCH5% 402
BOM NOTE:
EMPTY FOR 4-PIN FAN OR 3-PIN ALWAYS ON
1
12
FRONT_REAR_XSTR_GATE
79
IN
CPU_DRIVER
FAN_CPU_CNTL
3
Q1F1
EMPTY
2
A50095-001
FAN_FRONT_REAR_CNTL
108969-001
MMBT3904 XSTR
1
CPU_FAN_CTRL
Q2F2
3
2
BOM NOTE:
STUFF FOR 4-PIN FAN OR 3-PIN ALWAYS ON
FAN_CPU_NO_CNTL
FAN_REAR_CNTL
FAN_FRONT_CNTL
R8J2
1 2
220 402
FAN_ATX_CNTL
R10A1
1 2
220
5%
402
EMPTY
FAN_OPT_CNTL
R10J2
1 2
220
5%
402
EMPTY
2
R1F14
0 1A
CH 805
1
R5B6
5% 220 CH
5% CH
1/16W
1/16W
12
402
FRONT_FAN_PWM_R
1/16W
FAN_ATX_CNTL
REAR_ATX2_FAN_PWM_R
FAN_OPT_CNTL
REAR_ATX_FAN_PWM_R
2
C1F4
.1UF 20% 25V
1
EMPTY 603
FAN_CPU_CNTL
FRONT_REAR_FAN_CTRL
FAN_REAR_CNTL
REAR_FAN_PWM_R
FAN_FRONT_CNTL
1
1
1
+12V
3
Q11A1
MMBT3904 EMPTY
2
101416-601
3
Q10J1
MMBT3904 EMPTY
2
108969-001
FAN_CPU
1 2 3
4
CPU_TACH_OUT
1
3
Q8J1
MMBT3904 XSTR
2
101416-601
J1F2
1X4HDR
HDR
3
Q5B1
MMBT3904 XSTR
2
FAN_FRONT_NO_CNTL
+12V
2
1
REAR_FAN_TACH_DRIVER
FRONT_DRIVER
2
R8J7
0 1A
EMPTY 805
1
BOM NOTE:
STUFF FOR 4-PIN FAN OR 3-PIN ALWAYS ON
REAR_ATX2_DRIVER
2
FAN_ATX_NO_CNTL
R11A1
0 1A
EMPTY 805
1
BOM NOTE:
STUFF FOR 4-PIN FAN
REAR_ATX_DRIVER
2
FAN_OPT_NO_CNTL
R10J1
0 1A
EMPTY 805
1
BOM NOTE:
STUFF FOR 4-PIN FAN
FAN_CPU
R1F6
10K 5%
CH 402
15K 402 CH
+12V
2
1
FAN_CPU
R1F5
5%
FAN_REAR_NO_CNTL
2
R5B8
0 1A
EMPTY 805
1
BOM NOTE:
STUFF FOR 4-PIN FAN OR 3-PIN ALWAYS ON
C8J7
.1UF 20% 25V Y5V 603
FAN_FRONT_CNTL
+12V
2
C10A1
.1UF 20% 25V
1
EMPTY 603 FAN_ATX_CNTL
OR 3-PIN ALWAYS ON
+12V
2
C10J2
.1UF 20% 25V
1
EMPTY 603 FAN_OPT_CNTL
OR 3-PIN ALWAYS ON
12
FAN_FRONT
28 7 6 5 4 3 1
CPU ALWAYS-ON FAN
(PLACE BELOW/RIGHT CPU SOCKET)
2
FAN_CPU
R2F37
5.6K 5%
CH 402
1
CPU_FAN_TACH
FAN_CPU
C2F8
.047UF 20% 50V EMPTY
1 2
603
602433-001
+12V
+12V
FAN_REAR
2
C5B3
.1UF 20% 25V
1
Y5V 603
REAR_TACH_OUT
FAN_REAR_CNTL
J8J2
1X4HDR
1 2 3
4
HDR
FRONT_TACH_OUT
2
FAN_REAR
1X4HDR
HDR
R5B5
10K 5%
CH 402
1
FAN_REAR
R5B4
15K 5% 402 CH
J5B2
1 2 3
4
+12V
2
FAN_FRONT
R8J14
10K 5%
CH 402
15K 402
FAN_FRONT
R8J12
12
5% CH
1
REAR CHASSIS FAN
(PLACE ABOVE/RIGHT CPU SOCKET)
12
(PLACE LOWER LEFT CORNER OF PLATFORM)
2
FAN_REAR
R5B7
5.6K 5%
CH 402
1
FRONT CHASSIS FAN
2
FAN_FRONT
R8J11
5.6K 5%
CH 402
1
+12V
FAN_ATX
FAN_OPT
1 2 3
4
1 2 3
4
J11A1
1X4HDR
J10J1
1X4HDR
45
EMPTY
EMPTY
REAR_ATX2_TACH_OUT
REAR_ATX_TACH_OUT
2
+12V
2
FAN_ATX
R10A3
10K 5%
EMPTY 402
1
1
R10J4
10K 5%
EMPTY 402
FAN_OPT
FAN_ATX
R10A2
15K 402
FAN_OPT
R10J3
15K 402
REAR CHASIS FAN #2 -ATX
(PLACE ON FULL ATX PORCH NEAR THE BACK)
12
5% EMPTY
OPTIONAL SITE FOR ATX FAN
(PLACE ON FULL ATX PORCH NEAR THE FRONT) STUFF EITHER REAR FAN #2 OR THIS OPTIONAL SITE
2
FAN_OPT
R10J5
5.6K 5%
EMPTY 402
1
5% EMPTY
36
12
OUT
2
FAN_ATX
R10A4
5.6K 5%
EMPTY 402
1
FAN_OPT
2
C10J3
.047UF 20% 50V
1
EMPTY 603
602433-001
79
BOM NOTE:
USE IPN 201581-103 FOR 3-PIN FAN HEADERS
REAR_FAN_TACH
FAN_REAR
2
C5B4
.047UF 20% 50V
1
EMPTY 603 602433-001
FRONT_FAN_TACH
FAN_FRONT
2
C8J4
.047UF 20% 50V
1
EMPTY 603 602433-001
ATX_FAN_TACH
FAN_ATX
2
C10A2
.047UF 20% 50V
1
EMPTY 603
602433-001
ATX_FAN_TACH
[PAGE_TITLE=FAN CONTROL]
INTEL
DOCUMENT NUMBER
CONFIDENTIAL
2 1
OUT
C77862
D
79
79
OUT
C
B
79
OUT
A
79
OUT
PAGE
REV
83
4.0
<XR_PAGE_TITLE>
VREG_12V_FILTERED (+12V FILTERED FROM 12V POWER-SUPPLY) V_SM_VTT (1.3V DERIVED FROM V_SM) V_SM (2.6V DERIVED FROM 5VDUAL)
D
MCH
X.X (VCCP)
1.5 CORE
2.5 SM
SIO
3.3 (VCC3)
5.0 (VCC)
3.3 STBY (VCC3 STBY)
2.5 STBY
ICH
3.3 (VCC3)
1.5 CORE
C
2.5 STBY
GLUECHIP
3.3 STBY (VCC3_STBY)
3.3 STBY (VCC3_STBY)
5.0 STBY (VCC STBY)
VREG_USB_BP_LEFT (5VDUAL) VREG_USB_BP_RIGHT (5VDUAL) VREG_USB_BP_MID (5VDUAL) VREG_PS2 (5VDUAL) USB_FNT_PWR (5VDUAL) V_3P3_PCI_VAUX (3.3V OR 3.3-STANDBY SOURCE) V_3P3_STBY (3.3V DERIVED FROM 5.0-STANDBY) V_5P0_STBY (5.0V FROM POWER-SUPPLY) V_BAT_VREG_R_CR (3.0V FROM THE BATTERY) V_3P0_BAT_VREG (~3.0V FROM THE BATTERY THROUGH A DIODE) +12V (PLUS 12V FROM POWER-SUPPLY)
-12V (MINUS 12V FROM POWER-SUPPLY) VCC3 (3.3V FROM POWER-SUPPLY) VCC (5.0V FROM POWER-SUPPLY)
28 7 6 5 4 3 1
D
C
5.0 STBY
MARVELL LAN
CK-410
3.3 (VCC3)
3.3 PCIVAUX
HEC6
3.3 STBY (VCC3 STBY)
B
5.0 (VCC)
12
3.3 (VCC3)
B
X.X (VCCP)
1.5 (CORE)
FWH
V_1P5_CORE (NOT CONNECTED) V_1P25_MEMVTT_B (NOT CONNECTED)
A
V_1P3_NOMINAL (NOT CONNECTED) V_1P5_AGP (DERVIVED FROM 1.5V CORE) (NOT CONNECTED) V_12VREG (NOT CONNECTED) V_AGP_VDDQ (DERVIVED FROM 1.5V CORE) (NOT CONNECTED)
A
[PAGE_TITLE=VREG: VOLTAGE DISTRIBUTION]
DOCUMENT NUMBER PAGE REV
C77862
84
4.0
8 7
INTEL
CONFIDENTIAL
45
36
2 1
<XR_PAGE_TITLE>
L5J1
U5J1
1
1UH
CR5J1
1N4148
SOT23 DIO
CR5H1
13
3
HDRV
I_COMP_U5J2
VC
IND
2
I_BOOT_VC
IC
12
5VDUAL_FILTERED
1
C5J6
1200UF 20% 16V ALUM
2
RDL
PLACE + NODE NEAR HIGH-FET DRAIN PLACE GND SIDE CLOSE TO LOW-FET GND
MAY NEED TO CHANGE TO 2200UF 10V (A65154-009)
I_5VDUAL
CAD NOTE:
PLACE CLOSE TO FET
R4J1
0 1A
EMPTY 603
I_IRU_SS
2
C5J4
.1UF 10% 16V
1
X7R 603
KEEP THIS 0603 AND X7R
I_UGATE I_UGATE_R
ISL6520 SAYS USE 0-OHM
ISL6520 SAYS USE 0-OHM
I_LGATE I_LGATE_R
2
C4J3
1UF 20%
16V
1
Y5V
NEED 16V
805
2
C5J5
.1UF 20% 25V
1
TSTART=75*C (MS)
Y5V 603
202341-002
FB_5VDUAL_FILTERED_R
2.2 805 CH
R5J5
0 1A
805
R6J1
12
5%
12
CH
USE FOR ADDITIONAL COMPENSATION
2
1
5 6 7 8
2
R5J2
649 1%
CH 603
1
2
C5J1
10.0UF 20% 10V
1
Y5V
1206
STD38NH02L - 12MOHMS
825 GIVES .8V REF AND 1.817V
287 GIVES 1.25V REF AND 1.803V OUTPUT
R4J3
1.5K 1%
12
R4J2
1A0
EMPTY603
1
G
1
G
12
CH603
I_5VDUAL_FILTERED_RR
2
D
S
3
2
D
S
3
Q6H1
FET
PHASE_NODE_S
Q5J1
FET
STD38NH02L - 12MOHMS
C28887-001
PHASE_NODE_S_R
C28887-001
C4J7
12
.1UF
10%
16V
EMPTY
603
A83634-001
15A PART
2
R6J2
2.2 5%
CH 805
1
PLACE THESE 3 NEAR EACH OTHER
2
C6J2
4700PF 20% 50V
1
Y5V 603
L6J1
1UH
1 2
IND
47,91,93,94
IN
5VDUAL
D
+12V
2
R5J3
0 1A
PLACE NEAR
1 2
R5J4
5%
4021KEMPTY
CONTROLLER VCC
2
C5J7
.1UF 20% 25V
1
Y5V 603
IRU3037/A (IR), RT9209/A (RICHTEK) & APW7037/A (ANPEC) HAVE SAME FOOTPRINT AND PINOUT
A: 400KHZ, VFB=0.8V STD: 200KHZ, VFB=1.25V
ICH_GPO20_R
C5J8
4.7UF 20%
10V
Y5V
805
1 2
R4J6
4021KEMPTY
MBT3906DUAL
2
1
5%
C
EMPTY ALL FOR APW & RT
2
R5J1
15K 5%
CH 603
1
2
1
B
40
I_5VDUAL_FILTERED_R
C5J3
6800PF 20% 50V X7R 603
IN
2
C5J2
470PF 10% 50V
1
EMPTY 603
ICH_GPO21
A
ICH_GPO20
40
IN
I_5VDUAL_U5J2
Q4J1
5
R4J5
EMPTY
20K
5%
402
CH 603
1
ICH_GPO21_R
3
4
2
1
1 2 3 4
DEFAULT STUFFING:
6
1
ICH_GPO20_SW1ICH_GPO20_SW4
2
R4J4
10K 5%
EMPTY 402
1
MMBD4148CC
SOT23C
DIO
ISL6520 (INTERSIL), APW7057 (ANPEC), & RT9202 (RICHTEK) HAVE SAME FOOTPRINT AND PINOUT
IRU3037A
1
FB VCC LDRVSSCOMP GND
IRU3037A
2
EMPTY
CORE PAGEMEMORY OVER-VOLTAGE CONTROL
8 7
45
36
28 7 6 5 4 3 1
V_SM
470UF CAPS
1
C6J1
1000UF 20% 10V ALUM
2
1
C1H1
560.0UF 20% 4V EMPTY
2
RDL
INTEL
CONFIDENTIAL
2 1
RDL
DOCUMENT NUMBER PAGE REV
OUT
THERE ARE SIX
ON PAGE 24
2
C7H7
1
C77862
4.7UF 20% 10V Y5V 805
12,18,19,21,24,25,28,89
2
C7H9
.1UF 20% 25V
1
Y5V 603
85
D
C
B
A
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
C
B
A
CORE PAGE
R3J4
41,57,66,74,78,81,90..95
74
V_5P0_STBY
IN
PS_ON_SIO*
IN
1 2
22KCH5% 402
VCC VCC3 +12V
C4J6
.1UF
25V Y5V 603
C4J1
100UF
1 2
25V20%
ELEC
RDL
12
20%
C2J8
.1UF
25V Y5V 603
C3J2
100UF
1 2
20% 25V ELEC
RDL
12
20%
POWER CONNECTOR DECOUPLING
8 7
VCC3
VCC +12V
D
402
R3J3
1 2
-12V
2
1
C3J4
1UF 20%
6.3V Y5V 402
PS_ON_HEADER*
VCC
2
C3J3
470PF 10% 50V
1
X7R 603
TP_MINUS5V
5%0 CH
13 14 15 16 17 18 19 20 21 22 23 24
J3J1
2X12 PWR
CONN
1 2 3 4 5 6 7 8 9 10 11 12
2X12_DETECT
PWRGD_PS
2
OUT
C2J7
470PF 10% 50V
1
X7R 603
1
C3J6
.1UF 20% 25V
2
Y5V 603
74
OUT
V_5P0_STBY
2
C5J9
.1UF 20% 25V
1
EMPTY 603
OUT
41,57,66,74,78,81,90..95
C
R2J2
1 2
4021KCH
95..98
VREG_12V_POWER
C4J9
2X12_DETECT
IN
+12V
VCC
J5B1
1X4HDR
1
C46288-002
HDR
2 3 4
ICH_GPIO6_1X4_DETECT
12
20%.1UF 25V Y5V 603
VCC3
DESIGN NOTE:
USED TO DETECT 2X12 POWER
1
R7H9
10K 5%
2
CH 402
40
OUT
CONNECTOR
VREG_12V_FILTERED
A27641-001
J4B1
2X2HDR
1 2 3 4
OUT
CONN
V_5P0_STBY
41,57,66,74,78,81,90..95
C8B8
100UF
1 2
20% 25V ELEC
RDL
201307-004201307-004
-12V
C3J5
.1UF 20%
25V Y5V 603
12
IN
1
R3J5
1K 5%
EMPTY
2
402
VREG_MAIN_STBY_LED_R
2
CR3J1
EMPTY
1
2
C4B3
470PF 10% 50V
1
EMPTY 603
"Y5V"
[PAGE_TITLE=STANDARD POWER CONNECTOR]
CONFIDENTIAL
45
36
5%
PA_GPIO12
A27641-001
J4B2
2X2HDR
1 2 3 4
2
R2J3
2.2K 5%
CH 402
1
OUT
OUT
98
EMPTY
2
1
C4B4
470PF 10% 50V EMPTY 603
2
C4B8
470PF 10% 50V
1
EMPTY 603
"Y5V" "Y5V"
INTEL
DOCUMENT NUMBER PAGE REV
C77862
2 1
74
B
A
86
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
VCC3
D
C
B
A
2P5_VREG_CONTROL
88
IN
IN
IN
7..9,12,17,18,41,43
IN
6
IN
BOM NOTE:
DEFAULT EMPTY: ENGINEERING EXPERIMENT
CORE PAGE
8 7
V_3P3_STBY
V_1P5_CORE
V_FSB_VTT
VTT_PKGSENSE
29,38..41,43,55,56,73,74,79,88,90,92,93,95,105,106
19.1K
R5D10
1 2
0
4025%CH
R5D9
1 2
0
4025%EMPTY
7
V_3P3_STBY
IN
R5D12
1 2
0 5%
R5C31
1 2
1% CH
402
VTT_CORE_358_MINUS_PKGSENSE
IN
EMPTY402
V_1P5_CORE_VTT_HOLDOFF*
29,38..41,43,55,56,73,74,79,88,90,92,93,95,105,106
IN
VTT_SEL
MBT3904DUAL
V_3P3_STBY
Q4C1
MBT3904DUAL
5
R5C27
1
2.2K 1%
CH
2
402
2
R5D1
1.37K 1%
CH 402
1
VTT_CORE_358_PLUS_3
2
R5D13
442 1%
CH 402
1
Q5C4
5
1 2
499 1% 402
1 2
2
R4C5
1K EMPTY
1
5% 402
V_3P3_STBY_I_CTRL
3
4
3
4
R5D2
C5D2
1.0UF
10V 20% EMPTY 603
0.8 VOLT SETTING
2
1
CH
+12V
6
EMPTY
1
C5D3
2.2UF 20% 10V Y5V 603
V_1P5_CORE_VTT_HOLDOFF
6
XSTR
1
R4C6
10K 5%
EMPTY 402
2
CAD NOTE:
PLACE DECOUPLING CAP AS CLOSE AS POSSIBLE TO PIN 3 OR 5
12,15,16,88
IN
0.8 VOLT SETTING
0.8 VOLT SETTING
2
VTT_CORE_358_MINUS_6
C5D1
1.0UF
12
10V EMPTY 20% 603
+12V_I
V_2P5_MCH
1 2
2
R5D3
3.01K 5%
EMPTY 402
1
VTT_CORE_358_DRIVER
Q5C6
SOT23 201924-001
EMPTY
4
+12V
1
R5D14
3
D
S
2
D-PAK
1
5%1K CH402
D-PAK
1
Q5D1
FET
VCC3
2
Q5B3
D
S
G
FET
3
FSB_VTT_CORE_INTERMEDIATE
2
Q4C2
D
S
G
FET
3
202289-003
202289-003
C5D6
1
2
220UF 20% 25V ELEC RDL
1
2
C5C9
1UF 20% 16V
1
Y5V 805
U5C1A
8
3
LM358
+
1
VTT_CORE_358_OUT_1
V
2
G
-
IC
4
101299-002
-12V
R5C35
C5D5
1.0UF
12
10V EMPTY
20% 603
1 2
150 402
VTT_CORE_358_NEG_2
R5D7
1 2
82.5
1%
CH
402
C5D4
U5C1B
LM358
IC 101299-002
1 2
1.0UF
10V 20% EMPTY 603
7
VTT_CORE_358_OUT_7
-12V
2
C5C2
1UF 20% 16V
1
Y5V 805
+12V
8
5
+
V
6
G
-
4
R5D6
1%
1K
CH
402
1 2
1% EMPTY
R5C34
1 2
39.2 402
1 2
1KCH5%
402
1
G
R5B16
1% CH
713605-001
Q5B2
D
EMPTY
G
S
3
D2-PAK
SOT404 CAD NOTE:
NO FET HEATSINK
2.25 VOLT SETTING
1
C5C4
22UF 20% 25V ELEC
2
RDL
4
D
G
S
Q4C3
EMPTY
713605-001
1
C5B6
100UF 20% 25V ELEC
2
RDL
1 2
2
2
C5C5
4.7UF 20% 16V
1
Y5V 1206
805 CH
C5C8
.1UF 20% 25V Y5V
1
603
3
CAD NOTE:
OVERLAP SITES FOR D2-PAK (713605-001) WITH D-PAK (202289-003)
V_FSB_VTT
C4D1
1
2
2
C4C2
220UF 20% 25V ELEC
1
2
RDL
C7H5
4.7UF
4.7UF
20%
20%
16V
16V
1
Y5V
Y5V
1206
1206
2
C4B6
4.7UF 20% 16V
1
Y5V 1206
R5D11
2
C4B9
.1UF 20% 25V Y5V
1
603
202341-002
V_2P5_MCH
1A2.2
OUT
CAD NOTE:
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO CENTER OF VTT PLANE
C
12,15,16,88
OUT
B
7..9,12,17,18,41,43
A
[PAGE_TITLE=VREG_FSB]
D
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
87
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
VCC3
IN
R5C36
10K 5%
EMPTY 402
IN
IN
IN
IN
V_2P5_MCH
V_1P5_CORE
V_1P5_CORE
V_2P5_MCH
V_3P3_STBY
2
1
V_3P3_STBY
I_MBT3904
2
C5C11
1UF 20%
6.3V
1
EMPTY 402
C5C7
1UF 20%
6.3V EMPTY 402
MBT3904DUAL
805
Q5C3
MBT3904DUAL
5
Q5C5
5
1 2
10
2
1
2
1
R5C33
5% EMPTY
2
1
R6C29
47K 5%
EMPTY 402
I_MBT3904DUAL_R
3
4
CR5C1
BAT54C
SOT23C
DIO
2P5_MCH_SOURCE1
R5C25
1K 5%
EMPTY 402
2P5_VREG_CONTROL_SOURCE2
3
4
6
1
3
6
1
EMPTY
2
EMPTY
2
C6C18
4.7UF 20% 10V
1
EMPTY 805
VCC3
DESIGN NOTE:
3
Q5C2
1
MMBT2222A EMPTY
2
V_3P3_STBY
29,38..41,43,55,56,73,74,79,87,90,92,93,95,105,106
IN
2
29,38..41,43,55,56,73,74,79,87,90,92,93,95,105,106
IN
STUFF WHEN OTHER SEQUENCING IS REMOVED (EMPTY)
R5C26
1 2
10K
402
V_3P3_STBY
2
1
5% EMPTY
R5C32
10K 5%
EMPTY 402
2
C6C19
.1UF 20% 25V
1
EMPTY 603
R5C30
12
5%
0
EMPTY402
12,15,16,87
D
12,15..17,38,39,41,79,87,102
12,15..17,38,39,41,79,87,102
12,15,16,87
DESIGN NOTE:
KEEP AS 0805; HIGHER CURRENT CARYING SIGNAL.
C
SLP_S3*
40,74
IN
3.3K 402
R5C28
1 2
29,38..41,43,55,56,73,74,79,87,90,92,93,95,105,106
IN
2P5_VREG_CONTROL_GATE1 2P5_VREG_CONTROL_GATE2
5% EMPTY
B
SLP_S3*
40,74
IN
29,38..41,43,55,56,73,74,79,87,90,92,93,95,105,106
12,15..17,38,39,41,79,87,102
V_1P5_CORE
IN
2
A
1
VREG FOR MCH (PROVIDES VOLTAGE TO FILTER)
U6C2
MIC5205
1
5
OUTENIN
3 2
2P5_VREG_GND_STRAP
DESIGN NOTE:
MARGIN CONTROL ON EV DESIGN ON EV PAGES
BYPGND
EMPTY
2P5_VREG_BYPASS
4
A36096-008
1 2
R6C30
0
5%
402 EMPTY
2
1
2P5_VREG_CONTROL
C6D1
.01UF 10% 25V EMPTY 402
D
1 2
V_2P5_MCH
C5C12
10.0UF 20%
6.3V X5R 1206
OUT
C5D11
.1UF 20% 25V Y5V 603
1 2
12,15,16,87
C
87
OUT
B
A
CORE PAGE
8 7
[PAGE_TITLE=VREG_2P5_MCH]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
88
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
C
THIS KEEPS VTT OFF UNTIL NFET IS ACTIVE, OTHERWISE WHEN COMING OUT OF S3
12V WILL RAMP AND THIS RAIL WILL TURN ON WHILE PFET IS STILL ON
5VDUAL_SW_N IS THE SAME SIGNAL THAT CONTROLS THE NFET
B
AND PFET SWITCHOVER FOR
THE 5VDUAL RAIL
74,90
LATCHED_BACKFEED_CUT
IN
12,18,19,21,24,25,28,85
IN
SM_VTT
REGULATION
1/2 V_SM
R7H10
12
5VDUAL_SW_N_R
5%10K
603 CH
1
V_SM
5VDUAL_SW_N_R_STBY_R
3
Q7H1
MMBT3904 XSTR
2
2
1
2
1
R7H11
1.1K 1%
CH 402
R7H4
1.1K 1%
CH 402
D
N-FET 18MOHM - 7A P-FET 70MOHM - 4A
STS7C4F30L
LAYOUT INSIDE
C4J2
1
470UF 20%
10V
2
ALUM
NFET
PFET
V_SM_VTT
RDL
D1 - 8
D1 - 7
D2 - 6
D2 - 5
OUT
1
C2J5
1000UF 20% 10V ALUM
2
TH
C
22..24,26..28
B
S1 - 1
G1 - 2
S2 - 3
+12V
G2 - 4
2
C6H5
0.1UF 20% 10V
1
Y5V
C7H4
0.1UF 20% 10V Y5V 603
C7G14
.01UF 20% 50V EMPTY 603
603
I_V_1P5_CORE
R6G3
1 2
5%1K
603 EMPTY
R7G5
12
5%
0
CH
402
U7H1A
8
3
LM358
+
1
V
2
G
-
R7G6
1K 5%
EMPTY 402
+12V
101299-002IC
4
-12V
2
1
2
1
2
C7H3
1.0UF 20% 10V
1
Y5V 603
I_V_1P5_CORE_R
2
1
BOM NOTE:
MOD FILE CHANGE TO USE IRF7338 (A31520-002)
1 2 3 4 5
U7G1
STS7CF430L
S1 D1 G1 S2 G2
8 7
D1
6
D2 D2
IC
CAD NOTE:
KEEP CLOSE TO FET OUTPUT
2
C6H1
.1UF
20%
1
16V EMPTY 402
A
CORE PAGE
8 7
-12V
5 6
+
V G
-
U7H1B
8
LM358
7
IC 101299-002
4
A
[PAGE_TITLE=VREG_SM_VTT]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
89
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
IN
V_3P3_STBY
R7J1
402 CH
5%1K
D
VREG_VBAT_R
THROUGH-HOLE FLAT BATTERY
A05835-001
C
LATCHED_BACKFEED_CUT
74,89
IN
B
RP9B1B
TP_VREG_LINEAR_RP_2 TP_VREG_LINEAR_RP_7
TP_VREG_LINEAR_RP_8
2 7
5%.063W
2.7K SM
RP9B1C
SPARE SECTIONS
74,103
IN
A
CORE PAGE
8 7
12
XBT7J1
1 2
2PCOIN
2.7K 5%
2.7K 5% SM IC
2.7K
SMIC
36
TP_VREG_LINEAR_RP_1
.063WIC5%
BACKFEED_CUT
I_VREG_VBAT_R
RP9J1C
RP9J1D
BATTERY
41,57,66,74,78,81,86,91..95
36
ICSM
54
IN
VREG_BFEED_R_NU
.063W
MBT3904DUAL
.063W
2.7K SM
2.7KIC5% SM
2
1
V_5P0_STBY
5
41,57,66,74,78,81,86,91..95
RP8B3B
72
RP8B3A
18
CR7J1
V_3P0_BAT_VREG
3
BAT54C
SOT23C
DIO
CAD NOTE: DO NOT PLACE BATTERY NEAR MOUNTING HOLES, GROUND OR VIAS
+12V
4
RP9J2D
2.7K
6
RP9J2C
.063W
2.7K 5%
IC
SM
Q9J1
3
3
4
IN
VREG_BFEED_R
.063WIC5%
VREG_BFEED_RR
.063W
5% .063W IC SM
5
6
1
V_5P0_STBY
MBT3904DUAL
5
0 5%
402
RP9B1D
.063W
XSTR
2.7K 5%
SM
Q8C1
R8C3
VREG_USB_NCH_L
VREG_USB_PCH_L
2
VREG_BFEED_R2_NUVREG_BFEED_RR_NU
+12V
5
IC
4
3
4
EMPTY
12
39,41,43
2
C9H4
1.0UF 20% 10V
1
Y5V 603
PLACE NEAR ICH
OUT
CAD NOTE:
CONTROL SIGNAL FOR 4-DIMM VREG CONTROLLER
OUT
OUT
RP9J1A
18
VREG_BFEED_R1_NU
2
RP9J1B
VREG_BFEED_R2
3
2
.063W5%
IC
27
VREG_USB_NCH_PCI
VREG_USB_PCH_PCI
2.7K .063WIC5% SM
Q3J1
MMBT3904 EMPTY
1
LATCHED_BACKFEED_CUT
OUT
OUT
RP8B3D
54
1-WATT
RP8B3C
SM IC
VREG_BFEED_R1
63
5%2.7K
2.7K SM
2.7KIC5% .063W SM
8
RP9B1A
2.7K 5% .063W IC SM
1
6
XSTR
1
D
C
R9J7
0 5%
402
R9J5
R9C1
0 5%
402
R9C2
0 5%
402
VCC3
VREG
A
B
12
CH
12
5%0 CH402
USB/PS2WAKE
S3, S4, S5
12
EMPTY
12
EMPTY
Q8C2
FDS8958A
1
S1 D1
2
G1
3
S2
4 5
G2
C30363-001
45
VREG_USB_NCH
VREG_USB_PCH
VREG_USB_NCH
VREG_USB_PCH
D1 D2 D2
IC
8 7 6
94
OUT
94
OUT
NOTES:
A
STUFFS3 ONLY
EMPTY
94
OUT
94
OUT
C7C3
1
100UF 20% 25V ELEC
2
RDL
[PAGE_TITLE=PCI VAUX]
B
EMPTY
STUFF
CAD NOTE: PLACE AT PCI SLOTS
2
2
C8C2
.1UF 20% 25V
1
1
EMPTY 603
36
29,38..41,43,55,56,73,74,79,87,88,92,93,95,105,106
IN
V_3P3_STBY
0 2A
2010
R8C1
1 2
DESIGN NOTE: COST REDUCTON EXPERIMENT
TP_VREG_LINEAR2_RP_7
TP_VREG_LINEAR2_RP_3 TP_VREG_LINEAR2_RP_6
V_3P3_PCIVAUX
C7C2
.1UF 20% 25V Y5V 603
2
C9C1
.1UF 20% 25V
1
EMPTY 603
2.7KSM5%IC.063W
1 8
.063W 2.7K
5% IC
SPARE SECTIONS
2
C8C1
.1UF 20% 25V
1
EMPTY 603
INTEL
CONFIDENTIAL
2 1
32,49..51,56..59
OUT
EMPTY
RP9J2B
27
V_3P3_PCIVAUX
TP_VREG_LINEAR2_RP_2
RP9J2A
SM
OUT
32,49..51,56..59
DOCUMENT NUMBER PAGE REV
C77862
90
B
A
4.0
29,38..41,43,55,56,73,74,79,87,88,92,93,95,105,106
IN IN IN
VREG_USB_NCH_L
VREG_USB_PCH_L
VREG_USB_NCH_PCI
VREG_USB_PCH_PCI
VREG_USB_NCH_PCI V_3P3_STBY VREG_USB_PCH_PCI
IN
IN
IN
IN
73
IN
74,89
IN
.063W
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
R6B9
1 2
5%15K
RT1A1
1 2
EMPTY
1.50
2
R6B8
10K 5%
CH 402
1
2
R6B7
10K 5%
CH 402
1
402 CH
1.50
RT5B2
RT1A2
THRMSTR
18273
USB_OUT
EMPTY
1.50
IN
12
6
VREG_PS2_FB
12
V_5P0_STBY
5
RP6B1D
0 5% .063W IC SM
4
47,85,93,94
IN
5VDUAL
657448-004
C
THERMISTOR OPTION (PER CUSTOMER REQUEST):
STUFF SITE AND EMPTY 0 OHM R-PACK
41,57,66,74,78,81,86,90,92..95
USB_OC_BACK_LEFT*
1
C6B5
470UF 20% 10V ALUM
2
RDL
DO NOT CHANGE TO 402 SITE
M1A1
1 2
MULTI
FERRITE BEAD OPTION: A51464-001
603CH
CAD NOTE:
PLACE AS CLOSE AS POSSIBLE TO USB CONNECTOR
VREG_USB_BP_LEFT
2
C6B4
470PF 10% 50V
1
X7R 603
VREG_USB MUST BE SPLIT AMONGST ALL USB CHANNELS. DO NOT DAISY CHAIN
VREG_PS2
DECOUPLING ON CONNECTOR PAGE, PLACED NEAR PS2 CONNECTOR.
38
OUT
59
OUT
76
OUT
B
R5B3
1 2
15KCH5% 402
RT5B3
12
THRMSTR
1.50
657448-004
A
2
R5B2
10K 5%
CH 402
1
2
R5B1
10K 5%
CH 402
1
USB_OC_BACK_RIGHT*
1
C5B1
470UF 20% 10V ALUM
2
RDL
CAD NOTE:
PLACE AS CLOSE AS POSSIBLE TO USB CONNECTOR
VREG_USB_BP_RIGHT
2
C5A5
470PF 10% 50V
1
X7R 603
VREG_USB MUST BE SPLIT AMONGST ALL USB CHANNELS. DO NOT DAISY CHAIN
38
OUT
45,106
OUT
D
C
B
A
8 7
[PAGE_TITLE=USB_BP_RIGHT/LEFT & PS2]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
91
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
CAD NOTE:
OVERLAPPING SITE.
DESIGN NOTE:
DUAL-SITE INCLUDED TO FORCE FOOTPRINT KEEPOUT:
C
B
IN
V_5P0_STBY
41,57,66,74,78,81,86,90,91,93..95
2
1
UN-STUFFED, BUT MAY BE USED IN PRODUCTION DESIGNS.
Pri: C23198-001 Alt: A57605-002
C9D6
1.0UF 20% 10V Y5V 603
715453-002
3
IN
IN
EZ1086
3.3V
U9D1
MC33269
ADJ
ADJ
1
U9D2
I_ADJUST_R
OUT
IC
OUT
OUT
EMPTY
2 4
2
R9D9
274 1%
NOTE:
CH
R9D9: USE 274-ohm , 1%
402
1
EMPTY FOR EZ1086 STUFF FOR MC33269
V_3P3_STBY
29,38..41,43,55,73,74,79,87,88,90,93,95,105,106
C9E1
1
220UF 20% 25V
ELEC
2
RDL
OUT
D
C
B
C9D7
A
1 2
.1UF 20% 25V EMPTY 603
2
R9D10
453
NOTE:
5%
STUFF 453 OHM FOR MC33269 (A36092-301)
CH 402
STUFF 0OHM FOR EZ1086
1
A
CORE PAGE
[PAGE_TITLE=3.3V STANDBY]
DOCUMENT NUMBER PAGE REV
C77862
92
4.0
8 7
INTEL
CONFIDENTIAL
45
36
2 1
<XR_PAGE_TITLE>
STITCHING CAPS
VCC VCC3
D
C7H10
12
20%
.1UF
25V
Y5V
603
+12V
C8B9
.1UF
20%
C
47,85,91,94
25V
Y5V
603
5VDUAL
IN
VCC
12
+12V
C4J8
12
20%
.1UF
25V
Y5V
603
C2F10
.1UF
25V
EMPTY
603
C9F2
.1UF 20%
25V
EMPTY
603
C7B4
1 2
.1UF20% 25V Y5V
603
C7H12
.1UF
25V
EMPTY
603
C6H6
.1UF
25V
EMPTY
603
+12V
V_5P0_STBY
41,57,66,74,78,81,86,90..92,94,95
47,85,91,94
IN
"THMNT ALUM ELEC"
IN
1
2
C9D8
22UF 20% 25V EMPTY RDL
5VDUAL
C9H1
12
20%
.1UF
25V
EMPTY
603
1
C1J4
.1UF 20% 25V
2
Y5V 603
1
C5B2
.1UF 20% 25V
2
Y5V 603
C8F6
.1UF
25V
EMPTY
603
C9D4
.1UF
25V
EMPTY
603
C9C4
.1UF
25V
EMPTY
603
C9E10
.1UF 20%
25V
EMPTY
603
.1UF
EMPTY
C7B3
25V
EMPTY
603
12
20%
12
20%
12
20%
12
C9D2
12
20%
25V
603
12
20%.1UF
12
20%
12
12
20%
12
20%
V_3P3_STBY
29,38..41,43,55,56,73,74,79,87,88,90,92,95,105,106
IN
C7H6
12
20%
.1UF
25V
EMPTY
603
C1G1
12
20%
.1UF
25V
EMPTY
603
C5C6
12
20%
.1UF
25V
EMPTY
603
C8C6
12
.1UF
20%
25V
EMPTY
603
C6B7
12
20%
.1UF
25V
EMPTY
603
C5C10
12
20%.1UF
25V
EMPTY
603
C9E2
12
20%
.1UF
25V
EMPTY
603
28 7 6 5 4 3 1
D
C
VCC3
B
A
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
C9C2
12
20%
.1UF
25V
603
C9H6
12
20%
.1UF
25V
603
C6B6
12
.1UF
20%
25V
603
C9D3
12
.1UF
20%
25V
603
C8J1
12
20%
.1UF
25V
603
C9G3
12
20%
.1UF
25V
603
VCC3
C1J7
.1UF 20%
25V
EMPTY
603
C8D2
.1UF
25V
EMPTY
603
12
12
20%
VCC
1
C6C2
.1UF 20% 25V
2
Y5V 603
FOR HBL_66 TRANSITION
C6B18
EMPTY
EMPTY
20%.1UF
25V
603
C2F9
20%.1UF
25V
603
8 7
VCC
VCC
12
C7G13
12
EMPTY
12
20%
.1UF
25V
603
C8E2
.1UF 20%
25V
Y5V
603
VCC
B
VCC3
EMPTY
EMPTY
C9E3
12
20%.1UF
25V
603
C9C6
12
20%.1UF
25V
603
12
A
ROOM=DCPL_BULK BOM=VREG_DCPL_BULK
[PAGE_TITLE=VREG_DCPL_BULK]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
93
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
SLP_S3#
D
3
1
G
Q9G1
3
GATE
4
SOURCE
5VDUAL
2
D
S
3
STMICRO D40NF3LL 40A - <11MOHMS
Q9H1
PMOSFET
D
S
2
FDC638P
1
D_1
2
D_2
5
D_5
6
D_6
EMPTY
Q5H1
NOTE: .1 INCH COPPER ON
FET
C16435-001
BOM NOTE:
MOD FILE CHANGE TO USE IPN C58707-001
5VDUAL
DRAIN AND SOURCE
OUT
VCC
MIN 100MS MAX 500MS
PWRGD_PS
PWRGD_PS# AND'D W/
C
B
SLP_S3
PWRGD_3V(SIO)
L_BF_CUT#
+12V
USB_NCH
+5VSB
USB_PCH
NFET OFF
PFET ON
120MS
P-CHANNEL
4.5A RDS~50MOHMS FORWARD BODY DIODE D->S
IN
IN
V_5P0_STBY
VREG_USB_PCH
90
IN
VREG_USB_NCH
VCC
1
G
41,57,66,74,78,81,86,90..93,95
90
D
C
47,85,91,93
B
PS_ON#
A
CORE PAGE
8 7
A
[PAGE_TITLE=5VDUAL/USB_BP_MID]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
94
4.0
D
C
B
A
<XR_PAGE_TITLE>
H_VID[5..0]
7
IN
VSS_VRM_SENSE
6,8
IN
VCC_VRM_SENSE
6,8
IN
97 96
VCCP
IN
CAD NOTE:
PLACE AS CLOSE TO SE CORNER OF CPU SOCKET AS POSSIBLE
R1F38
1 2
0OHM
SM
CAD NOTE:
SINGLE POINT CONNECTION BETWEEN GND AND A_GND CLOSE TO CONTROLLER.
DESIGN NOTE:
EMPTY SITE (PADS OVERLAP)
6
LL_ID0
IN
CORE PAGE
8 7
EMPTY
0
402
A_GND
R2F38
1 2
0 5% 402
R1E1
5%
EMPTY
41,57,66,74,78,81,86,90..94
EMPTY
12
603 CH
OUT
V_5P0_STBY
IN
R2F41
1 2
EMPTY402
A36093-024
CAD NOTE:
PLACE AS CLOSE TO SE CORNER OF CPU SOCKET AS POSSIBLE
C2F11
12
VCC_SENSE_FB
10%1200PF 50V X7R 603
R1F29
12
COG
1%931
7
86,96..98
2
C1F13
.1UF 20% 16V
1
EMPTY 402
R1G1
2.7K 5%
EMPTY
402
CPU_SELECT_XSTR_GATE
5%15K
IN
IN IN
SOT23
1
C1F5
270PF 5%
50V
2
1
12
CPU_VREG_COMP_PN1
603
VTT_PWRGD
A_GND VREG_12V_FILTERED
CPU_PSC_XSTR_GATE
2
R1F39
10K 5%
EMPTY 402
1
CPU_TJS_HI
3
Q2F3
MMBT3904 EMPTY
2
108969-001
20KCH1%
402
2
C1F7
.039UF 10% 16V
1
X7R 603
SOT23
1
LOAD_LINE_SELECT
2
1
+12V +12V
2
R1F8
10K 5%
CH 402
1
4
H_VID4
3
H_VID3
2
H_VID2
1
H_VID1
0
H_VID0
5
H_VID5
C1F6
39PF 5%
50V NPO 603
R1F32
2
Q1G1
3
12
2
R1F35
453K 1%
CH 402
1
MMBT3906 EMPTY 101421-601
12
CPU_VREG_COMP
VCCP_12V_PWRGD
VREG_DELAY
VREG_RT VREG_RAMPADJ
2
1
A36092-327
R1F36
221K 1%
CH 402
2
1
R1F33
249K 1%
CH 402
A36092-306
LOAD_LINE_SELECT
R1F43
10K 5%
EMPTY 402
2
C1F9
.1UF 20%
C1F12
.1UF 20% 16V EMPTY 402
16V
1
EMPTY 402
2
1
U1F1
VID4 VID3 VID2 VID1 VID0 VID5 FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ
28 7 6 5 4 3 1
2
C1E4
.1UF 10%
6.3V
1
EMPTY 402
VREG_PWM1_SENSE VREG_PWM2_SENSE VREG_PWM3_SENSE
R1F13
1
113K 1%
CH
2
402
R1G3
2
1
2.2KCH5% 402
PWRGD_3906_5_6
Q1G2B
PWRGD_INT_6_2
+12V
R1E2
1
220K 5%
CH
2
402
D
97
OUT
96
IN
96
IN
97
IN
VTT_OUT
R1F11
1
113K 1%
CH
2
402
R1F45
1
10K 5%
CH
2
402
Q1G2A
6
2
IC
1
IN
R1F10
1
113K 1%
CH
2
402
3
5
IC
4
C
B
A
CPU_VREG_CSCOMP CPU_VREG_CSSUM
C1F1
1800PF 5%
25V
COG
603
C1F2
603
25V
COG
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_OUT
12
12
5%1500PF
VREG_PWM1
VREG_PWM2
R1F27
1 2
402
1
2
C1F8
12
5%
15PF
50V
NPO
603
1
R2F43
EMPTY
2
402 0 5%
I_PWM1_SW2
1%CH37.4K
RT1D1
THRMSTR
A63992-003
402
1
2
1 2
680PF 5%
50V
1 2
603
I_PWM1_SW1
R1F30
1 2
402
CPU_VREG_CSCOMP_THERMISTOR
CAD NOTE:
R1F31
5%CH220K
29,38..41,43,55,73,74,79,87,88,90,92,93,105,106
R2F39
CH 402 0 5%
1 2
2.74K 1%
OUT
C1F10
EMPTY
R1F34
I_PWM1_SW3
1%69.8k CH
PLACE CLOSE TO INDUCTOR
402
EMPTY
IN
1%511K
R1F40
R1F1
1 2
5%56K
EMPTY
603
96
IN
12
CPU_PWRGD_FET_SOURCE
603
3
Q1F2
EMPTY
201924-001
2
VREG_ILIMITVREG_ILIM_R
LOAD_LINE_SELECT
1
SOT23
7
OUT
DESIGN NOTE:
ALWAYS EMPTY ENGINEERING EXPERIMENTAL FEATURE
OUT
V_3P3_STBY
MBT3904DUAL
PWRGD_FET_PN2
1
CH
R1F44
1
22.1K 1%
CH
2
402
C1F11
1.0UF 20% 10V
2
Y5V 603
A_GND
IN
2
R1F7
10 5%
CH 402
1
C1F3
1.0UF 10% 16V X5R 805
1 2
CSCOMP
CSSUM CSREF
ILIMIT
VCC_IN_CPU_VREG
VCC PWM1 PWM2 PWM3 PWM4
SW1
SW2
SW3
SW4
GND
TP_SW4
FAN6019
IC
96 97
VCCP
IN
2
R1F37
150K 1%
CH 402
A_GND
IN
OUT
1
6..8,101
IN
6..8
IN
IN
OUT
R1F21
1 2
0 5%
402
R1F22
1 2
0
402
R1F23
1 2
402
VTT_PWRGD
R1F42
1
10K 5%
CH
2
402
Q1F3
5
96,97
96
VREG_PWM3
CH
5% CH
5%0 CH
29,38..41,43,55,73,74,79,87,88,90,92,93,105,106
3
4
1
2
IN
R1F41
10K 5%
CH 402
PWRGD_3904_2_3
6
1
V_3P3_STBY
2
XSTR
[PAGE_TITLE=VCCP VREG]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
95
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
86,95,97,98
VREG_12V_FILTERED
IN
95
VREG_PWM1
IN
95,97
VREG_ILIMIT
IN
C
86,95,97,98
VREG_12V_FILTERED
IN
B
95
VREG_PWM2
IN
95,97
VREG_ILIMIT
IN
A
1
C4B10
1.0UF 10% 16V
2
X5R 805
1
C1E6
1.0UF 10% 16V
2
X5R 805
1
CR4A1
1N4148 SOT23 DIO
3
201593-001
VREG_1_BST
1
BST
2
IN
3
OD*
4 5
VCC
1
CR1E1
1N4148 SOT23 DIO
3
VREG_2_BST
1
BST
2
IN
3
OD*
4 5
VCC
U4B1
ADP3418
U1E1
ADP3418
DRVH
SW PGND DRVL
DRVH
SW PGND DRVL
2
1
8 7 6
IC
2
1
8 7 6
IC
C4B5
.22UF 10% 16V X7R 805
VREG_PWM1_G_DRV_H_R
VREG_SW1_OUT
1 2
VREG_PWM1_G_DRV_L
2
C4B7
1000PF 10%
6.3V
1
EMPTY 402
C1E5
.22UF 10% 16V X7R 805
VREG_PWM2_G_DRV_H_R
VREG_SW2_OUT
1 2
VREG_PWM2_G_DRV_L
2
C1E2
1000PF 10%
6.3V
1
EMPTY 402
R4B7
805 CH
R1E4
805 CH
VREG_SW1_GND
VREG_SW2_GND
2
C3B1
4.7UF 20% 16V
1
Y5V 1206
L3B1
250NH
1 2
VCCP
1
R3N1
0OHM
EMPTY SM
2
VREG_PWM1_SENSE
2
C1C1
4.7UF 20% 16V
1
Y5V 1206
L1D1
1 2
1
R1R1
0OHM
EMPTY SM
2
VREG_PWM2_SENSE
IND
250NH
IND
VCCP
2
C3B4
4700PF 20% 50V
1
X7R 603
2
R3B2
2.2 5%
CH 805
1
2
C1E3
4700PF 20% 50V
1
X7R 603
2
R1E3
2.2 5%
CH 805
1
OUT
95
OUT
OUT
95
OUT
98 95 79 30 97 96
98 95 79 30 97 96
C66918-001
2
Q3B2
D
1
G
1A2.2
HS
S
FET
3
1
G
C50933-001
2
Q3B1
D
HS
S
EMPTY
3
1
G
C66918-001
2
Q3B3
D
HS
S
FET
3
VREG_PWM1_G_DRV_H
C69459-001
2
Q4B1
D
1
1
1A2.2
LS
S
G
FET
3
2
Q1D1
D
HS
S
G
FET
3
C66918-001
1
G
1
G
C66920-001
2
Q3B4
D
1
LS
S
EMPTY
3
2
Q1C2
D
S
EMPTY
3
C50933-001
HS
G
1
G
C69459-001
2
Q3B5
D
LS
S
FET
3
C66918-001
2
Q1C1
D
HS
S
FET
3
VREG_PWM2_G_DRV_H
C69459-001
2
Q1D2
D
1
LS
S
G
FET
3
1
G
C66920-001
2
Q1D3
D
1
LS
S
EMPTY
3
G
C69459-001
2
Q1E1
D
LS
S
FET
3
D
C
B
A
CORE PAGE
8 7
[PAGE_TITLE=VCCP VREG]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
96
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
86,95,96,98
VREG_12V_FILTERED
IN
1
CR2B1
1N4148
SOT23 DIO
3
VREG_3_BST
ADP3418
1
BST
1
C2B6
1.0UF 10% 16V
2
X5R 805
2
IN
3
OD*
4 5
VCC
C
IN
VREG_ILIMIT
95,96
IN
VREG_PWM3
95
2
C2B4
.22UF 10% 16V
1
X7R
DRVH
PGND DRVL
SW
8 7 6
IC
805
VREG_PWM3_G_DRV_H_R
VREG_SW3_OUT
VREG_PWM3_G_DRV_L
U2B1
2
1
C2B5
1000PF 10%
6.3V EMPTY 402
R2B1
805 CH
1 2
1
G
1A2.2
1
G
2
Q2B2
D
HS
S
FET
3
VREG_PWM3_G_DRV_H
2
Q2B6
D
LS
S
FET
3
C66918-001
C69459-001
C50933-001
2
Q2B3
D
1
G
1
G
HS
EMPTY
Q2B5
EMPTY
LS
C66920-001
1
G
1
G
S
3
2
D
S
3
C66918-001
2
Q2B1
D
HS
S
FET
3
C69459-001
2
Q2B4
D
LS
S
FET
3
VREG_SW3_GND
2
C2B2
4.7UF
20% 16V
1
Y5V 1206
L1B1
250NH
2
1 2
C3B3
4700PF
1
20% 50V
1 2
1
R1N1
X7R
0OHM
603
EMPTY
R3B1
SM
2
2.2
5% CH
805
VREG_PWM3_SENSE
VCCP
IND
OUT
95
OUT
98 95 79 30 96
B
D
C
B
A
A
[PAGE_TITLE=VCCP VREG]
CORE PAGE
8 7
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
97
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
CAD NOTE: PLACE AS MANY 1206 CAPACITORS AS POSSIBLE WITHIN CPU CAVITY
644066-024
D
97 96
VCCP
IN
2
C3D4
10.0UF 20%
6.3V
1
X5R 1206
2
C2D12
10.0UF 20%
6.3V
1
X5R 1206
2
C2D1
10.0UF 20%
6.3V
1
X5R 1206
2
C3D3
10.0UF 20%
6.3V
1
X5R 1206
2
C3D6
10.0UF 20%
6.3V
1
X5R 1206
2
C2D10
10.0UF 20%
6.3V
1
X5R 1206
2
C3D5
10.0UF 20%
6.3V
1
X5R 1206
2
C2D9
10.0UF 20%
6.3V
1
X5R 1206
2
C3D1
10.0UF 20%
6.3V
1
X5R 1206
2
C2D4
10.0UF 20%
6.3V
1
X5R 1206
D
2
C2D3
10UF 20%
6.3V
1
X5R 1206
2
C3D2
10UF 20%
6.3V
1
X5R 1206
2
C2D11
10UF 20%
6.3V
1
X5R 1206
2
C2D2
10UF 20%
6.3V
1
X5R 1206
2
C2D7
10UF 20%
6.3V
1
X5R 1206
2
C2D6
10UF 20%
6.3V
1
X5R 1206
2
C2D5
10UF 20%
6.3V
1
X5R 1206
C
CAD NOTE: PLACE ON TOP (NORTH SIDE) OF SOCKET
B
86
A
IN
1
C1D1
560UF 20%
2.5V ALUM
2
RDL
1
C1D2
560UF 20%
2.5V ALUM
2
RDL
1 2
L4B1
1UH
EMPTY
A83634-001
1
C1E1
560UF 20%
2.5V ALUM
2
RDL
1
C3C3
560UF 20%
2.5V ALUM
2
RDL
1
2
1
C3C2
560UF 20%
2.5V EMPTY
2
RDL
C3B2
1200UF 20% 16V ALUM RDL
1
2
1
C1B2
1200UF 20% 16V ALUM
2
RDL
CAD NOTE: PLACE ON EAST SIDE OF SOCKET
1
C3C1
560UF 20%
2.5V EMPTY RDL
C1C2
560UF 20%
2.5V ALUM
2
RDL
1
2
C2B3
1200UF 20% 16V ALUM RDL
2
C2D8
10UF 20%
6.3V
1
X5R 1206
PLACEMENT NOTE FOR 1206: PLACE 18 INSIDE CPU SOCKET (STUFF ALL)
C
1
C2C1
560UF 20%
2.5V ALUM
2
RDL
1
C2C3
560UF 20%
2.5V ALUM
2
RDL
1
C1B1
1200UF 20% 16V ALUM
2
RDL
1
C2C2
560UF 20%
2.5V ALUM
2
RDL
VREG_12V_FILTEREDVREG_12V_POWER
1
C2B1
1200UF 20% 16V EMPTY
2
RDL
OUT
86,95..97
B
A
CORE PAGE
8 7
A46887-010
[PAGE_TITLE=VCCP VREG DECOUPLING]
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
98
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
29
49,50,53
37,54
VCC3
37,53,54 37,49,50,54
37,49,50,53,54,105
37,49,50,53,54,105
37,49,50,53,54
37,49,50,53,54,105
37,49,50,53,54,105
C11C2
12
.1UF
20%
25V
Y5V
603
C11D1
12
20%
.1UF
25V
Y5V
603
D
C
B
A
VCC
D
BACK PANEL SLOT 1
PCI SLOT4
+12V
VCC3
V_3P3_PCIVAUX
32,49..53,56..59,90
IN
37,49,50,53,105
37
P_INTD*
OUT
P_INTF*
OUT
P_PCIRST*
IN
P_GNT4*
IN
P_PME*
OUT
P_FRAME*
BI
P_TRDY*
BI
P_STOP*
BI
P_SMB_CLK_SLOT34
BI
P_SMB_DATA_SLOT34
BI
P_PAR
BI
37,53,54 37,49,50,54
C
37,49,50,53,57,105
37,49,50,53,54,105
B
53 53
37,49,50,53,54,105
37,49,50,53,54,105
37,49,50,53,105
VCC
R11E1
BI
BI
1 2
2.7K 5%
402 CH
P_AD[31..0]
P_C/BE*[3..0]
A
37,49,50,53,105
37,49,50,53,105
REQ64D*
VCC VCC
J11B1
PCI CONN2_2
A1
TRST*
A2
P12V_1
A3
TMS
A4
TDI
A5
P5V_2
A6
INTA*
A7
INTC*
A8
P5V_3
A9
RSVD1
A10
P5V_4
A11
RSVD3
A12
GND10
A13
GND16
A14
3.3VAUX
A15
RST*
A16
P5V_6
A17
GNT*
A18
GND5
A19
PME
A20
30
P_AD30
28
P_AD28
26
P_AD26
24
P_AD24
17
P_AD17
22
P_AD22
20
P_AD20
18
P_AD18
16
P_AD16
15
P_AD15
13
P_AD13
11
P_AD11
9
P_AD9
P_C/BE*0
6
P_AD6
4
P_AD4 P_AD5
2
P_AD2
0
P_AD0
AD30
A21
P3_3V
A22
AD28
A23
AD26
A24
GND6
A25
AD24
A26
IDSEL
A27
P3_3V
A28
AD22
A29
AD20
A30
GND9
A31
AD18
A32
AD16
A33
P3_3V
A34
FRAME*
A35
GND13
A36
TRDY*
A37
GND22
A38
STOP*
A39
P3_3V
A40
SMB_CLK
A41
SMB_DAT
A42
GND25
A43
PAR
A44
AD15
A45
P3_3V
A46
AD13
A47
AD11
A48
GND17
A49
AD09 KEY KEY
A52
C_BE0*
A53
P3_3V
A54
AD06
A55
AD04
A56
GND21
A57
AD02
A58
AD00
A59
P5V_8
A60 A61
P5V_12
A62
P5V_10
A50 A51
M12V_1
PRST1*
PRST2*
P5V_11
C_BE3*
C_BE2*
DEVSL*
C_BE1*
B50 B51
P5V_9
ACK64*REQ64*
TCK
GND1
TDO P5V_0 P5V_1 INTB* INTD*
RSVD2
GND2 GND3
RSVD5
GND4
CLK
GND7 REQ*
AD31 AD29 GND8 AD27 AD25
P3_3V
AD23
GND12
AD21 AD19
P3_3V
AD17
GND14 IRDY* P3_3V
GND15 LOCK* PERR* P3_3V SERR* P3_3V
AD14
GND23
AD12
AD10 GND24 KEY KEY
AD08
AD07 P3_3V
AD05
AD03 GND19
AD01
P5V_5 P5V_7
CONN
-12V
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
732431-002NC=1,2
VCC3
31
P_AD31
29
P_AD29
27
P_AD27
25
P_AD25
3
23
21 19
17
14
12 10
80 7
5 3
1
P_C/BE*3
P_AD23
P_AD21
P_AD19
P_AD17
2
P_C/BE*2
1
P_C/BE*1
P_AD14
P_AD12
P_AD10
P_AD8
P_AD7
P_AD3
P_AD1
VCC
C11B2
12
20%
.1UF
25V EMPTY 603
C11D3
12
20%
.1UF
25V EMPTY 603
VCC VCC3
C11C3
100UF
1 2
20%
25V
ELEC
RDL
P_INTC* P_INTG*
CK_P_33M_S4
P_REQ4*
P_IRDY*
P_DEVSEL*
P_PLOCK* P_PERR*
P_SERR*
ACK64*
VCC3
VCC3
C11A3
470UF
1 2
20% 10V
ALUM RDL
C11C1
.1UF 20% EMPTY
12
25V 603
OUT OUT
IN
OUT
BI
BI
BI
OUT
OUT
OUT
8 7
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
99
4.0
<XR_PAGE_TITLE>
28 7 6 5 4 3 1
D
D
DMI LAI HEADER
J7U1
A12
BI BI
BI BI
BI BI
BI BI
DMI_ITN_MRN_0 DMI_ITP_MRP_0
DMI_ITN_MRN_1 DMI_ITP_MRP_1
DMI_ITN_MRN_2 DMI_ITP_MRP_2
DMI_ITN_MRN_3 DMI_ITP_MRP_3
11,38 11,38
11,38
C
11,38
11,38 11,38
11,38 11,38
A11 A10
B
3GIO_LAI_X4
A<12> A<11> A<10>
A9
A<9>
A8
A<8>
A7
A<7>
A6
A<6>
A5
A<5>
A4
A<4>
A3
A<3>
A2
A<2>
A1
A<1>
B12
B<12>
B11
B<11>
B10
B<10>
B9
B<9>
B8
B<8>
B7
B<7>
B6
B<6>
B5
B<5>
B4
B<4>
B3
B<3>
B2
B<2>
B1
B<1>
EMPTY
DMI_MTP_IRP_0 DMI_MTN_IRN_0
DMI_MTP_IRP_1 DMI_MTN_IRN_1
DMI_MTP_IRP_2 DMI_MTN_IRN_2
DMI_MTP_IRP_3 DMI_MTN_IRN_3
11,38
BI
11,38
BI
11,38
BI
11,38
BI
11,38
BI
11,38
BI
11,38
BI
11,38
BI
C
B
A
A
[PAGE_TITLE=DMI LAI PORT]
CORE PAGE
DMI = DIRECT MEDIA INTERFACE
8 7
INTEL
CONFIDENTIAL
45
36
2 1
DOCUMENT NUMBER PAGE REV
C77862
100
4.0
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