Intel Cyclone 10 GX FPGA User Manual

Intel® Cyclone® 10 GX FPGA Development Kit User Guide

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Contents

1 Overview......................................................................................................................... 4

1.1 General Development Kit Description.........................................................................4

1.2 Recommended Operating Conditions......................................................................... 6

1.3 Handling the Board................................................................................................. 6

2 Getting Started................................................................................................................ 7

2.1 Installing the Quartus Prime Software....................................................................... 7

2.2 Development Kit Package........................................................................................ 8

2.3 Installing the Intel FPGA Download Cable Driver......................................................... 8

3 Development Kit Setup.................................................................................................. 10

3.1 Setting up the Development Kit.............................................................................. 10

3.2 Default Switch and Jumper Settings........................................................................ 10

4 Development Board Components................................................................................... 12

4.1 Board Overview.................................................................................................... 12

4.2 Cyclone 10 GX FPGA............................................................................................. 15

4.3 MAX 10 System Controller......................................................................................19

4.4 FPGA Configuration............................................................................................... 21

4.5 Status and User I/O Elements.................................................................................23

4.5.1 Switches..................................................................................................23

4.5.2 Pushbuttons............................................................................................. 24

4.5.3 LEDs....................................................................................................... 25

4.6 Clocks................................................................................................................. 26

4.7 Memory...............................................................................................................27

4.7.1 EMIF with DDR3........................................................................................27

4.7.2 QSPI Flash............................................................................................... 27

4.8 Power..................................................................................................................27

4.9 Transceivers Interfaces and Communication Ports......................................................29

4.9.1 Transceiver Channels ................................................................................29

4.9.2 PCIe Interface.......................................................................................... 29

4.9.3 SFP+ Interface......................................................................................... 29

4.9.4 USB3.1 Type-C Interface............................................................................30

4.9.5 FPGA Mezzanine Card (FMC) Interface......................................................... 32

4.9.6 10/100/1000Base-T Ethernet Connector.......................................................37

4.9.7 I2C/PMBUS...............................................................................................38

5 Board Test System......................................................................................................... 40

5.1 Preparing the Board.............................................................................................. 41

5.2 Running the Board Test System.............................................................................. 42

5.3 Using the Board Test System.................................................................................. 42

5.3.1 The Configure Menu.................................................................................. 42

5.3.2 The System Info Tab................................................................................. 43

5.3.3 The GPIO Tab........................................................................................... 45

5.3.4 The EPCQ Tab...........................................................................................46

5.3.5 The XCVR Tab...........................................................................................47

5.3.6 The FMC Tab............................................................................................ 50

5.3.7 The DDR3 Tab.......................................................................................... 53

Intel® Cyclone® 10 GX FPGA Development Kit User Guide 2

Contents

5.3.8 Power Monitor.......................................................................................... 55

5.3.9 Clock Controller........................................................................................ 57

A Additional Information.................................................................................................. 60

A.1 Safety and Regulatory Information..........................................................................60

A.1.1 Safety Warnings....................................................................................... 61

A.1.2 Safety Cautions........................................................................................ 62

A.2 Compliance and Conformity Statements...................................................................64

B Revision History.............................................................................................................65

B.1 User Guide Revision History................................................................................... 65

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1 Overview

The Intel® Cyclone® 10 GX FPGA Development Kit is a complete design environment that includes both hardware and software you need to develop and evaluate the performance and features of the Intel Cyclone 10 GX FPGA device.

1.1 General Development Kit Description

This development kit includes a Intel Cyclone 10 GX FPGA device along with the following components.

Intel Cyclone 10 GX FPGA

• Intel Cyclone 10 GX FPGA device in F780 BGA package

• 780 pin, 29 mm x 29 mm BGA package

• 220K Logic Elements (LEs)

• 12 transceivers capable of 12.5 Gbps data rates

• 284 GPIOs with 118 pairs of LVDS

FPGA Configuration

• Active Serial (ASx4) mode configuration with EPCQ-L

• Fast Passive Parallel (FPP) mode configuration mode by Intel MAX® 10 PFL

• Configuration via PCIe* (CvP) x4 Gen2

Clock Sources

• 50 MHz oscillator, LVCMOS for USB Blaster and Power Intel MAX 10 logic

• 50 MHz oscillator, LVCMOS for PFL control Intel MAX 10 logic

• 24 MHz crystal for USB-Blaster II PHY

• 50 MHz oscillator, LVCMOS for Intel Cyclone 10 GX FPGA core

•

100 MHz oscillator, LVCMOS for Intel Cyclone 10 GX FPGA user_clk

• A programmable oscillator, LVDS for tranceivers: 644.53125 MHz by default, LVDS to FPGA tranceiver

• Programmable clock generator for FPGA logic

— 21.186 MHz LVDS for EMIF, LVDS to FPGA core

— 125 MHz LVDS for transceiver of USB3.1, LVDS to FPGA transceiver

— 125 MHz for Gigabit Ethernet, LVDS to FPGA core

— 100 MHz for FPGA logic, LVCMOS to FPGA core

• 100 MHz for PCIe system to FPGA transceiver

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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1 Overview

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• User-defined reference clock input from FMC card

— 1 for FMC transceiver to FPGA transceiver

— 2 for FMC LA reference to FPGA core

— 2 for FMC clock reference to FPGA core

• One external differential input through SMA, AC coupled

• One single-ended LVCMOS clock output through SMA, DC coupled

Transceiver Interfaces

• 12 transceivers organized in two banks

• 4 channels for PCIe x4 Gen2

• 2 channels for 2 SFP+ supporting 10 GE

• 1 channel for USB3.1 SuperSpeed

• 5 channels for FMC card

Memory Interfaces

• 1 channel of x40 DDR3 @ 933 MHz

Communication Ports

• 10/100/1000Base-T Ethernet port with SGMII (LVDS)

• USB3.1 Type-C supporting SuperSpeed, backward compatible with USB2.0

• 2 SFP+ supporting 10GE

• FMC expansion card:

— 12G SDI: Semtech RDK-12GSRD-ALTRA00 Evaluation Board

— 8G DisplayPort: Bitec FMC DisplayPort Daughter Card

— 6G HDMI 2.0: Bitec FMC HDMI Daughter Card

Pushbuttons

• 3 User Push Buttons

• 1 User Program selecting Pushbutton

• 1 nCONFIG Pushbutton to initiate configuration

• 1 FPGA reset Pushbutton to reset the FPGA logic

Switches

• 4 User DIP Switches

• DIP switch for MSEL

• DIP switch for JTAG chain selection

• DIP switch for clock source selection

Intel® Cyclone® 10 GX FPGA Development Kit User Guide

5

LEDs

• 4 User LEDs

• 1 Power LED

• 1 Config Done LED

• PFL Load/Error LED

• PFL Program Number LED

• Ethernet LEDs

• SFP+ LEDs

Heatsink and Fan

Heatsink with fan

Power

• 12 V power input from ATX 2 x 4 power connector

• 12 V external power adaptor input

• 12 V power input from PCIe system

• On/Off Slide Power Switch

• On-board power measurement and management

• Adjustable FMC+ power regulator

• Power Failure Monitor

• Power-off discharge circuit

1 Overview

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Dimensions

Full height PCIe add-in card 4.376" (Height) x 7" (Length)

Operating Environment

Ambient Temperature: 0° C to 45° C

1.2 Recommended Operating Conditions

• Recommended ambient operating temperature range: 0° C to 45° C

• Maximum ICC load current: 6 Amp

• Maximum ICC load transient percentage: 30%

• Maximum board power consumption: 75 Watts

1.3 Handling the Board

When handling the board, it is important to observe static discharge precautions.

Note:

Note: This development kit should not be operated in a Vibration environment.

Without proper anti-static handling, the board could be damaged. Use anti-static handling precautions when handling the board.

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2 Getting Started

2.1 Installing the Quartus Prime Software

The Intel Quartus® Prime design software is a multiplatform design environment that easily adapts to your specific needs in all phases of FPGA, CPLD, and SoC designs. The Intel Quartus Prime software delivers the highest performance and productivity for Intel FPGAs, CPLDs, and SoCs.

Design software must enable dramatically increased design productivity in order to take advantage of devices with multi-million logic elements with increased capabilities that provide designers with an ideal platform to meet next-generation design opportunities.

The new Intel Quartus Prime Design Suite® design software includes everything needed to design for Intel FPGAs, SoCs and CPLDs from design entry and synthesis to optimization, verification and simulation. The Intel Quartus Prime Design Suite software includes an additional Spectra-Q® engine that is optimized for Intel Stratix

®

10 and future devices. The Spectra-Q engine enables new levels of design productivity for next generation programmable devices with a set of faster and more scalable algorithms, a hierarchical database infrastructure and a unified compiler technology.

Intel Quartus Prime Software

The Intel Quartus Prime Design Suite software is available in three editions based on specific design requirements: Pro, Standard, and Lite Edition.

The Intel Quartus Prime Pro Edition is optimized to support the advanced features in Intel's next generation FPGAs and SoCs.

The Intel Cyclone 10 GX FPGA is only supported on Intel Quartus Prime Pro Edition. There is no paid license fee required for Intel Cyclone 10 GX support in Intel Quartus Prime Pro Edition.

Included in the Intel Quartus Prime Pro Edition are the Intel Quartus Prime software, Nios® II EDS and the MegaCore IP Library.

To install Intel's development tools, download the Intel Quartus Prime Pro Edition software from the Quartus Prime Pro Edition page from the Download Center of Intel's website.

Related Links

Intel Cyclone 10 GX FPGA Development Kit

The Intel Cyclone 10 GX FPGA Development Kit includes embedded Intel FPGA Download Cable circuits for FPGA programming. However, for the host computer and board to communicate, you must install the Intel FPGA Download Cable driver on the host computer.

Installation instructions for the Intel FPGA Download Cable driver for your operating system are available on the Intel website.

Intel® Cyclone® 10 GX FPGA Development Kit User Guide 8

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On the Intel website, navigate to the Cable and Adapter Drivers Information link to locate the table entry for your configuration and click the link to access the instructions.

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3 Development Kit Setup

The instructions in this chapter describe how to setup and configure the development kit

3.1 Setting up the Development Kit

To prepare and apply power to the board, perform the following steps:

The Intel Cyclone 10 GX FPGA Development Kit has two modes of operation:

• Standard PCIe-compliant system:

In this mode, plug the board into an available PCIe slot and connect the standard 2x4 PCIe auxiliary power available from the PC's ATX power supply to the mating connector on the board (J12), and remove any power supply connected to J13. The PCIe slot together with the PCIe power is required to power the entire board with power up to 75 Watt. If ATX power is not connected, ensure that your PCIe system can provide up to 75 Watt of power through the PCIe slot alone. The power switch S14 is ignored when the board is used in the PCIe.

• Stand-alone evaluation board:

In this mode, plug the included power supply into the power adapter connector (J13) and the AC power cord of the power supply into a power outlet. Remove any ATX power supply that is connected from the 2x4 power connector (J12). The power switch S14 will power ON/OFF the board.

3.2 Default Switch and Jumper Settings

This section lists the default factory switch settings for the Intel Cyclone 10 GX FPGA Development Kit

Table 2. DIP Switch Settings

Board Label Switch Default Position Function

S1 S1.1 OPEN/OFF/1 Intel Cyclone 10 GX GX

S1.2 OPEN/OFF/1

S2 S2.1 CLOSE/ON/0 Select clock from Si570 for

S2.2 OPEN/OFF/1 Enable the output of Si570

S3 S3.1 CLOSE/ON/0 Select internal oscillator as

S3.2 CLOSE/ON/0

S5 S5.1 OPEN/OFF/1 Enable FMC card JTAG

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

FPGA MSEL

Si53307's output

the PLL reference of Si5332

continued...

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Board Label Switch Default Position Function

S5.2 OPEN/OFF/1 Enable Intel Cyclone 10 GX

S6 S6.1 OPEN/OFF/1 Reserved, no function

S6.2 OPEN/OFF/1 Reserved, no function

S9 S9.1 OPEN/OFF/1 User available Digital Input 0

S9.2 OPEN/OFF/1 User available Digital Input 1

S15 S15.1 OPEN/OFF/1 User available Digital Input 2

S15.2 OPEN/OFF/1 User available Digital Input 3

FPGA JTAG

defined

Intel® Cyclone® 10 GX FPGA Development Kit User Guide

11

USB 3.1 MUX/DRV

Intel Cyclone 10 GX FPGA

10CX220YF780E5G

Intel FMC LPC+

DDR3 (256M x 40)

EMIF

X40

933 MHz

Micro-USB 2.0

PCI Express

Transceivers X4

Buttons,

Switches, LEDs

X3

EPCQ-L for

Configuration

256 Mbit QSPI

Flash for Nios II

Intel MAX 10

10M08SAU169

On-Board Intel® FPGA

Download Cable II

USB Interface

JTAG Chain

Superspeed Tranceiver

USB 2.0 PHY

ULPI

GigE PHY 88E1111

SGMII LVDS x1

NOR Flash

Intel MAX 10

10M08SAU169 PFL

FPP X16

LVDS X32

CLKIN X2

REFCLK X2

Transceiver X5

USB 3.1

Type C

RJ-45

SFP+

TX/RX

X32

TX/RX A/B

DP/DM

X4

Oscillators

50M, 100M

Programmable

Transceiver X4

SMA Clock In

LVDS

AS X4

SMA Clock Out

LVCMOS

QSPI

SFP+

TX/RX

Updated from JTAG Only

XCVR x1

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4 Development Board Components

This chapter introduces all major components on the Intel Cyclone 10 GX FPGA Development Kit.

4.1 Board Overview

Figure 2. Intel Cyclone 10 GX FPGA Developement Kit Block Diagram

There are four sub-systems in this development kit:

• Intel Cyclone 10 GX FPGA and its peripherals

• Configuration with Intel MAX 10 FPGA

• Timing

• Power Supply

Table 3. Board Components Table

Board Reference Type Description

U1 FPGA Intel Cyclone 10 GX FPGA 10CX220YF780E5G, 220K

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

Featured Devices

Logic Elements, 12 Transceivers, F780 BGA package

continued...

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Board Reference Type Description

U2 FPGA Intel MAX 10 10M08SAU169C8G for On-board Intel

U3 FPGA Intel MAX 10 10M08SAU169C8G for PFL

U49 Voltage Regulator Enpirion® EM2130L-30A Step-Down DC-DC Switching

U50 Voltage Regulator Enpirion EM2130H – 30A Step-Down DC-DC Switching

U51 Voltage Regulator Enpirion ER2120QI - 2A Synchronous Buck

U52 Voltage Regulator Enpirion ER3105DI - 500mA Wide VIN

U53, U54, U55, U60 Voltage Regulator Enpirion EN6337QI - 3A PowerSoC Voltage Mode

U56 Voltage Regulator Enpirion EN6347QI - 4A PowerSoC Voltage Mode

U62 Voltage Regulator Enpirion ER3110DI - 1A Wide VIN

Configuration and Setup Elements

J9 Embedded Intel FPGA Download Cable II Type-B Micro USB Connector for programming and

J11 10-pin header Optional JTAG direct via 10-pin header for external

S1 DIP-SW:

ON/Closed/0 OFF/Open/1

S7

S12

S13 FPGA Reset Push Button Press this button to reset all registers in the FPGA

D23 Power LED (Green) Power Good LED (All power rails are OK)

D13 Configuration Error LED (Red) Config error status Indicator

FPGA PGM_SEL Push Button

FPGA nCONFIG Push Button

Status Elements

FPGA Download Cable II and Power Management

configuration, clock generator control and power monitoring

Converter with Integrated Inductor, featuring Digital Control with PMBus™ v1.2 Compliant Interface, implements FPGA 0.9V Vcc

Converter with Integrated Inductor, Featuring Digital Control with PMBus v1.2 Compliant Interface, implements 3.3V intermediate power bus used by other lower voltage power rails

Regulator with Integrated MOSFETs, implements 5V USB VBUS of USB3.1 Type-C interface

Synchronous Buck Regulator, implements local power supply used by U49 and U50.

Synchronous PWM Buck with Integrated Inductor, implements 1.03V, 1.5V, and 1.8V power rails to FPGA

Synchronous PWM Buck with Integrated Inductor, implements voltage adjustable power rail to FPGA and FMC daughter card

Synchronous Buck Regulator, implements power supply used by U2 and U3.

debugging the FPGA

download cables

Intel Cyclone 10 GX FPGA Configuration Mode

Press this button to cycle through different PFL loads

Press this button to trigger reconfiguration

ON: Detected Power is Good OFF: Detected Power is Bad

ON: FPGA configuration failed OFF: FPGA configured without error

continued...

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Board Reference Type Description

D14 Load LED (Green) Config is loading

ON: FPGA configuration is going on OFF: FPGA configuration has finished

D15 Configuration LED (Green) Config done status Indicator

ON: FPGA configured successfully OFF: FPGA not configured

General User Input/Output

S8, S10, S11 General user push buttons Three user push buttons. Driven low when pressed.

D19, D20, D21, D22 User LEDs Four user LEDs. Illuminates when driven low.

S9, S15 User DIP Switches 4-bit user DIP switches, low when set to ON

Clocks

U11 50 MHz Oscillator 50 MHz crystal oscillator for logic of two Intel MAX 10

Y4 50 MHz Oscillator 50 MHz crystal oscillator for general purpose logic of

Y1 100 MHz Oscillator 100 MHz crystal oscillator for calibration and

Y2 Programmable Oscillator Programmable Oscillator for Intel Cyclone 10 GX

U7 Clock Buffer 2:1 buffer for reference clock

U64 Programmable clock generator Eight channel Programmable clock generator. 4

Transceiver Interfaces

U16 PCIe x4 Golden Finger PCIe Gen2 x4 endpoint

J5, J6 SFP+ Support 10 GE SFP+ module

J7 FMC 5 Transceivers up to 12.5Gbps

J8 USB Type-C Implements USB3.1 and USB2.0

U26 USB 2:1 MUX TI HD3SS3220 USB Type-C DRP Port Controller with

U65 USB Redriver TI USB1002 USB3.1 10 Gbps Dual-Channel Linear

Memory

U12, U13, U14 DDR3 memory ISSI IS43TR16256A-107MBLI 256Mx16 4Gb DDR3

U4 EPCQ-L Flash EPCQ-L 1024

U58 QSPI Flash ISSI IS25WP256D-RHLE, 256Mbit

Power

J12 PCIe ATX 2x4 Auxiliary power supply of PCIe system

J13 DC-input 4-pin DIN power adaptor

S14 Power Switch Slide switch for power input

FPGA devices, 3.3V LVCMOS

Intel Cyclone 10 GX FPGA, 1.8V LVCMOS

configuration of Intel Cyclone 10 GX FPGA, 1.8V LVCMOS

FPGA Transceivers, LVDS

outputs are implemented, default frequencies are 125 MHz, 21.186 MHz, 125 MHz and 100 MHz

SuperSpeed 2:1 MUX

Redriver

SDRAM

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4.2 Cyclone 10 GX FPGA

The target FPGA device this kit is designed to work with is the Intel Cyclone 10 GX 10CX220YF780E5G FPGA. It is the device with the fastest speed, largest resource and biggest package in the Intel Cyclone 10 GX FPGA series.

Table 4. Maximum Resource Availability

Feature Count

FPGA Device 10CX220YF780E5G

Logic Elements (LE) 220K

ALM 80,330

Registers 321,320

Memory - M20K 11,740 Kb

Memory - MLAB 1,690

Variable precision DSP block 192

18 x 19 Multiplier 384

Hard Floating-point Arithmetic Yes

PLL (Fractional Synthesis) 4

PLL (I/O) 6

12.5 Gbps Transceiver 12

GPIO 284

LVDS Pair 118

PCIe Hard IP Block 1

Hard Memory Interfaces 2

Package F780 (29 mm x 29 mm)

The table below presents a summary of the Intel Cyclone 10 GX FPGA I/O resource allocation. I/O Direction is with respect to the FPGA.

Table 5. Cyclone 10 GX FPGA I/O Resources Table

Bank Number Function I/O Type I/O Count Description

Transceiver Clocks

1C

1D

1C/1D

USB_REFCLK

FMC_GBTCLK_M2C

SFP_REFCLK

PCIE_REFCLK

PCIE_TX [0:3]

LVDS input 2 User-defined from

LVDS input 2 644.53125 MHz

LVDS input 2 100 MHz from PCIe,

Transceiver Channels

CML output 8(4p) PCIe Gen2 Transmit

Intel® Cyclone® 10 GX FPGA Development Kit User Guide

2 125 MHz

(adjustable) , AC

FMC, AC

(adjustable), AC

DC

continued...

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Bank Number Function I/O Type I/O Count Description

1C/1D

1D

1C/1D

2A

2L

2J

2A

CSS

2A

CSS

PCIE_RX [0:3]

SFP+_TX [0:1]

SFP+_RX [0:1]

USB31_TX

USB31_RX

FMC_DP_C2M [0:4]

FMC_DP_M2C [0:4]

M10_USB_CLK

C10_REFCLK1

C10_CLK50M

C10_REFCLK2

REFCLK_EMIF

FPGA_RESETn

C10_TCK

C10_TMS

C10_TDI

C10_TDO

C10_CLKUSR

C10_MSEL[0:1]

C10_nSTATUS

C10_CONF_DONE

C10_nCONFIG

C10_CS0n

C10_AS_D [0:3]

C10_DCLK

CML/LVDS input 8(4p) PCIe Gen2 Receive

CML output 4(2p) SFP+ Transmit

CML / LVDS input 4(2p) SFP+ Receive

CML output 2(1p) USB3.1 Trasnsmit

CML/LVDS input 2(1p) USB3.1 Receive

CML output 10(5p) FMC Transmit

CML/LVDS input 10(5p) FMC Receive

Global FPGA Clocks

1.8 V CMOS input 1 30/48 MHz from U2 (MAX10)

LVDS input 2 125 MHz (adjustable)

1.8 V CMOS input 1 50 MHz OSC, free running

LVCMOS input 2 100 MHz (adjustable)

LVDS input 2 21.186 MHz

(adjustable)

Global FPGA Reset

1.8 V CMOS input 1 From U2 (Intel MAX

10)

JTAG

1.8 V CMOS input 1 From U2 (Intel MAX

10)

1.8V CMOS input 1 From U2 (Intel MAX

10)

1.8 V CMOS input 1 From U2 (Intel MAX

10)

1.8 V CMOS input 1 To U2 (Intel MAX 10)

Configuration

1.8 V CMOS input 1 100 MHz, for calibration

1.8 V CMOS input 2 From DIP Switch S1

1.8 V CMOS output 1 To U2/U3 (Intel MAX

10)

1.8 V CMOS output 1 To U2/U3 (Intel MAX

10)

1.8 V CMOS input 1 From U2 (Intel MAX

10)

1.8 V CMOS output 1 To U4 (EPCQ-L)

1.8 V CMOS inout 4 To U4 (EPCQ-L)

1.8 V CMOS inout 1 To U4 (EPCQ-L) for ASx4

continued...

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Bank Number Function I/O Type I/O Count Description

2A

FPP [0:15]

CVP_CONFDONE

M10_USB_DATA [0:7]

2A

M10_USB_ADDR [0:1]

2A

2J

M10_USB_RDn

M10_USB_WRn

M10_USB_RESETn

M10_USB_FULL

M10_USB_EMPTY

M10_USB_Oen

M10_USB_SCL

M10_USB_SDA

DDR3_A [0:14]

DDR3_BA [0:2]

DDR3_RASn

DDR3_CASn

DDR3_WEn

DDR3_CK

DDR3_CKE [0:1]

DDR3_ODT [0:1]

DDR3_CS [0:1]

From U3 (Intel MAX

10) for FPPx16

1.8 V CMOS input 16 From U3 (Intel MAX

10)

1.8 V CMOS output 1 To U2 (Intel MAX 10)

UBII Side Bus

1.8 V CMOS input 8 From U2 (Intel MAX

10)

1.8 V CMOS input 2 From U2 (Intel MAX

10)

1.8 V CMOS input 1 From U2 (Intel MAX

10)

1.8 V CMOS input 1 From U2 (Intel MAX

10)

1.8 V CMOS input 1 From U2 (Intel MAX

10)

1.8 V CMOS output 1 From U2 (Intel MAX

10)

1.8 V CMOS output 1 From U2 (Intel MAX

10)

1.8 V CMOS input 1 From U2 (Intel MAX

10)

1.8 V CMOS input 1 From U2 (Intel MAX

10)

1.8 V CMOS inout 1 From U2 (Intel MAX

10)

EMIF

1.5 V SSTL output 15 To U12/U13/U14 DDR3

1.5 V SSTL output 3 To U12/U13/U14 DDR3

1.5 V SSTL output 1 To U12/U13/U14 DDR3

1.5 V SSTL output 2 To U12/U13/U14 DDR3

continued...

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Bank Number Function I/O Type I/O Count Description

2J

2J/2K

3A/3B

DDR3_RSTn

DDR3_D [0:39]

DDR3_DQS [0:4]

FMC_LA_TX [0:16]

FMC_LA_RX [0:14]

FMC_LA_CC [0:1]

FMCA_CLK_M2C

1.5 V CMOS output 1 To U12/U13/U14 DDR3

1.5 V SSTL inout 40 To U12/U13/U14 DDR3

1.5 V SSTL inout 10 To U12/U13/U14 DDR3

FMC LVDS GPIO

Vadj CMOS inout 34 To J7 (FMC), DC

Vadj CMOS inout 30 To J7 (FMC), DC

Vadj CMOS input 4 From J7 (FMC), DC

[0:1]

3B

3A

2A

2L

PCIe sideband

2L

2A

FMC_PRSN_1V8

FMC_SCL

FMC_SDA

SGMII_TXP/N

ETH_MDC_C10

ETH_MDIO_C10

ETH_INTn_C10

ETH_RESETn_C10

SFP_SCL_0

SFP_SDA_0

SFP_INT_0

SFP_SCL_1

SFP_SDA_1

SFP_INT_1

PCIE_WAKEn

PCIE_SMBCLK

PCIE_SMBDAT

PCIE_PERSTn

Vadj CMOS input 1 From J7 (FMC)

Vadj CMOS output 1 To J7 (FMC)

Vadj CMOS inout 1 To J7 (FMC)

10/100/1000 Base-T

LVDS output 2 To U33 (88E1111

PHY), AC

LVDS input 2 To U33 (88E1111

PHY), AC

1.8 V CMOS output 1 To U33 (88E1111 PHY)

1.8 V CMOS inout 1 To U33 (88E1111 PHY), AC

1.8 V CMOS input 1 To U33 (88E1111 PHY), AC

1.8 V CMOS output 1 To U33 (88E1111 PHY), AC

SFP+ sideband

1.8 V CMOS output 1 To J5 (SFP+ 0)

1.8 V CMOS inout 1 To J5 (SFP+ 0)

1.8 V CMOS input 1 To J5 (SFP+ 0)

1.8 V CMOS output 1 To J6 (SFP+ 1)

1.8 V CMOS inout 1 To J6 (SFP+ 1)

1.8 V CMOS input 1 To J6 (SFP+ 1)

1.8 V CMOS input 1 To golden finger, reserved

1.8 V CMOS output 1 To golden finger

1.8 V CMOS inout 1 To golden finger

1.8 V CMOS input 1 To golden finger

continued...

Intel® Cyclone® 10 GX FPGA Development Kit User Guide 18

4 Development Board Components

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Bank Number Function I/O Type I/O Count Description

2L

USB_D [0:7]

USB_NXT

USB_DIR

USB_STP

USB_CLK

USB_RESETn

USB_SCL

USB_SDA

USB_PWEN

USB_SW_INTn_1.8V

USB_ID_1.8V

C10_QSPI_CSn

C10_QSPI_RESETn

C10_QSPI_CLK

C10_QSPI_D [0:3]

ULPI (USB 2.0)

1.8 V CMOS inout 8 To U32 (USB Transceiver)

1.8 V CMOS input 1 To U32 (USB Transceiver)

1.8 V CMOS output 1 To U32 (USB Transceiver)

1.8 V CMOS output 1 60 MHz, REFCLK for ULPI

1.8 V CMOS output 1 To U32 (USB Transceiver)

USB3.1 sideband

1.8 V CMOS output 1 To U26 (USB3.1 Transceiver Switch)

1.8 V CMOS inout 1 To U26 (USB3.1 Transceiver Switch)

1.8 V CMOS output 1 To U25 (USB3.1 Transceiver Switch)

1.8 V CMOS input 1 To U26 (USB3.1 Transceiver Switch)

QSPI Flash

1.8 V CMOS output 1 To U58 (QSPI Flash)

1.8 V CMOS inout 4 To U58 (QSPI Flash)

4.3 MAX 10 System Controller

The highlights of the Intel MAX 10 devices include:

• Internally stored dual configuration flash

• User flash memory

• Instant on support

• Integrated analog-to-digital converter (ADC)

• Single-chip Nios II soft core processor support

Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

Intel® Cyclone® 10 GX FPGA Development Kit User Guide

19

4 Development Board Components

Table 6. Summary of Features for Intel MAX 10 Devices

Feature Description

Technology 55 nm TSMC Embedded Flash (Flash + SRAM) process technology

Packaging • Low cost, small form factor packages—support multiple packaging

technologies and pin pitches

• Multiple device densities with compatible package footprints for seamless migration between different device densities

• RoHS6-compliant

Core architecture • 4-input look-up table (LUT) and single register logic element (LE)

• LEs arranged in logic array block (LAB)

• Embedded RAM and user flash memory

• Clocks and PLLs

• Embedded multiplier blocks

• General purpose I/Os

Internal memory blocks • M9K—9 kilobits (Kb) memory blocks

• Cascadable blocks to create RAM, dual port, and FIFO functions

User flash memory (UFM) • User accessible non-volatile storage

• High speed operating frequency

• Large memory size

• High data retention

• Multiple interface option

Embedded multiplier blocks • One 18 × 18 or two 9 × 9 multiplier modes

• Cascadable blocks enabling creation of filters, arithmetic functions, and image processing pipelines

ADC • 12-bit successive approximation register (SAR) type

• Up to 16 analog inputs

• Cumulative speed up to 1 million samples per second (MSPS)

• Integrated temperature sensing capability

Clock networks • Global clocks support

• High speed frequency in clock network

Internal oscillator Built-in internal ring oscillator

PLLs • Analog-based

• Low jitter

• High precision clock synthesis

• Clock delay compensation

• Zero delay buffering

• Multiple output taps

General-purpose I/Os (GPIOs) • Multiple I/O standards support

• On-chip termination (OCT)

• Up to 830 megabits per second (Mbps) LVDS receiver, 800 Mbps LVDS transmitter

External memory interface (EMIF) Supports up to 600 Mbps external memory interfaces:

• DDR3, DDR3L, DDR2, LPDDR2

• SRAM (Hardware support only)

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continued...

Intel® Cyclone® 10 GX FPGA Development Kit User Guide 20

Intel Cyclone 10 GX FPGA User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual