Intel Cyclone User Manual

Intel® Cyclone® 10 GX Transceiver PHY User Guide

Updated for Intel® Quartus® Prime Design Suite: 20.1

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Contents

1. Intel® Cyclone® 10 GX Transceiver PHY Overview ......................................................... 7

1.1. Device Transceiver Layout......................................................................................8

1.1.1. Intel Cyclone 10 GX Device Transceiver Layout.............................................. 8

1.1.2. Intel Cyclone 10 GX Device Package Details ................................................10

1.2. Transceiver PHY Architecture Overview.................................................................. 10

1.2.1. Transceiver Bank Architecture....................................................................10

1.2.2. PHY Layer Transceiver Components........................................................... 11

1.2.3. Transceiver Phase-Locked Loops................................................................ 13

1.2.4. Clock Generation Block (CGB)...................................................................14

1.3. Calibration.......................................................................................................... 14

1.4. Intel Cyclone 10 GX Transceiver PHY Overview Revision History................................. 15

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers....................................... 16

2.1. Transceiver Design IP Blocks................................................................................. 16

2.2. Transceiver Design Flow........................................................................................17

2.2.1. Select and Instantiate the PHY IP Core........................................................17

2.2.2. Configure the PHY IP Core.........................................................................19

2.2.3. Generate the PHY IP Core......................................................................... 19

2.2.4. Select the PLL IP Core.............................................................................. 19

2.2.5. Configure the PLL IP Core........................................................................ 20

2.2.6. Generate the PLL IP Core ......................................................................... 21

2.2.7. Reset Controller ......................................................................................21

2.2.8. Create Reconfiguration Logic..................................................................... 21

2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller........................... 22

2.2.10. Connect Datapath ................................................................................ 22

2.2.11. Make Analog Parameter Settings ............................................................. 22

2.2.12. Compile the Design................................................................................ 22

2.2.13. Verify Design Functionality...................................................................... 22

2.3. Cyclone 10 GX Transceiver Protocols and PHY IP Support......................................... 24

2.4. Using the Cyclone 10 GX Transceiver Native PHY IP Core...........................................26

2.4.1. Presets................................................................................................... 28

2.4.2. General and Datapath Parameters .............................................................28

2.4.3. PMA Parameters......................................................................................31

2.4.4. Enhanced PCS Parameters ........................................................................34

2.4.5. Standard PCS Parameters........................................................................ 41

2.4.6. PCS Direct ............................................................................................ 45

2.4.7. Dynamic Reconfiguration Parameters.......................................................... 45

2.4.8. PMA Ports.............................................................................................. 50

2.4.9. Enhanced PCS Ports................................................................................ 53

2.4.10. Standard PCS Ports................................................................................ 62

2.4.11. IP Core File Locations............................................................................. 67

2.4.12. Unused Transceiver Channels...................................................................69

2.5. Interlaken..........................................................................................................70

2.5.1. Metaframe Format and Framing Layer Control Word.....................................71

2.5.2. Interlaken Configuration Clocking and Bonding............................................73

2.5.3. How to Implement Interlaken in Cyclone 10 GX Transceivers......................... 79

2.5.4. Native PHY IP Parameter Settings for Interlaken..........................................82

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Contents

2.6. Ethernet............................................................................................................. 86

2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2....................................... 87

2.6.2. 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants...............................98

2.6.3. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core....................... 108

2.6.4. Acronyms.............................................................................................121

2.7. PCI Express (PIPE)............................................................................................ 122

2.7.1. Transceiver Channel Datapath for PIPE......................................................123

2.7.2. Supported PIPE Features.........................................................................123

2.7.3. How to Connect TX PLLs for PIPE Gen1 and Gen2 Modes............................. 128

2.7.4. How to Implement PCI Express (PIPE) in Cyclone 10 GX Transceivers...........131

2.7.5. Native PHY IP Parameter Settings for PIPE ...............................................131

2.7.6. fPLL IP Parameter Core Settings for PIPE...................................................135

2.7.7. ATX PLL IP Parameter Core Settings for PIPE .............................................137

2.7.8. Native PHY IP Ports for PIPE................................................................... 139

2.7.9. fPLL Ports for PIPE..................................................................................143

2.7.10. ATX PLL Ports for PIPE...........................................................................145

2.7.11. How to Place Channels for PIPE Configurations......................................... 146

2.8. CPRI................................................................................................................149

2.8.1. Transceiver Channel Datapath and Clocking for CPRI...................................149

2.8.2. Supported Features for CPRI ..................................................................151

2.8.3. Word Aligner in Manual Mode for CPRI.......................................................152

2.8.4. How to Implement CPRI in Cyclone 10 GX Transceivers............................... 153

2.8.5. Native PHY IP Parameter Settings for CPRI............................................... 155

2.9. Other Protocols..................................................................................................158

2.9.1. Using the "Basic (Enhanced PCS)" Configuration........................................158

2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of

Standard PCS........................................................................................ 166

2.9.3. How to Implement PCS Direct Transceiver Configuration Rule.......................185

2.10. Simulating the Transceiver Native PHY IP Core..................................................... 186

2.10.1. NativeLink Simulation Flow.................................................................... 187

2.10.2. Scripting IP Simulation..........................................................................192

2.10.3. Custom Simulation Flow........................................................................ 193

2.11. Implementing Protocols in Intel Cyclone 10 GX Transceivers Revision History........... 196

3. PLLs and Clock Networks............................................................................................ 198

3.1. PLLs................................................................................................................. 200

3.1.1. Transmit PLLs Spacing Guidelines when using ATX PLLs and fPLLs................. 200

3.1.2. ATX PLL................................................................................................ 201

3.1.3. fPLL......................................................................................................203

3.1.4. CMU PLL............................................................................................... 206

3.2. Input Reference Clock Sources............................................................................208

3.2.1. Dedicated Reference Clock Pins...............................................................209

3.2.2. Receiver Input Pins.................................................................................209

3.2.3. PLL Cascading as an Input Reference Clock Source..................................... 210

3.2.4. Reference Clock Network.........................................................................210

3.2.5. Global Clock or Core Clock as an Input Reference Clock...............................210

3.3. Transmitter Clock Network..................................................................................210

3.3.1. x1 Clock Lines....................................................................................... 211

3.3.2. x6 Clock Lines....................................................................................... 212

3.3.3. xN Clock Lines....................................................................................... 214

3.4. Clock Generation Block....................................................................................... 216

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3.5. FPGA Fabric-Transceiver Interface Clocking............................................................ 217

3.6. Transmitter Data Path Interface Clocking...............................................................219

3.7. Receiver Data Path Interface Clocking...................................................................220

3.8. Unused/Idle Clock Line Requirements................................................................... 221

3.9. Channel Bonding................................................................................................222

3.9.1. PMA Bonding......................................................................................... 222

3.9.2. PMA and PCS Bonding.............................................................................224

3.9.3. Selecting Channel Bonding Schemes.........................................................225

3.9.4. Skew Calculations.................................................................................. 226

3.10. PLL Feedback and Cascading Clock Network.........................................................226

3.11. Using PLLs and Clock Networks.......................................................................... 231

3.11.1. Non-bonded Configurations....................................................................231

3.11.2. Bonded Configurations.......................................................................... 235

3.11.3. Implementing PLL Cascading..................................................................240

3.11.4. Timing Closure Recommendations...........................................................241

3.12. PLLs and Clock Networks Revision History............................................................241

4. Resetting Transceiver Channels.................................................................................. 243

4.1. When Is Reset Required? ................................................................................... 243

4.2. Transceiver PHY Implementation.......................................................................... 244

4.3. How Do I Reset?................................................................................................ 245

4.3.1. Model 1: Default Model........................................................................... 245

4.3.2. Model 2: Acknowledgment Model..............................................................254

4.3.3. Transceiver Blocks Affected by Reset and Powerdown Signals....................... 258

4.4. Using the Transceiver PHY Reset Controller............................................................259

4.4.1. Parameterizing the Transceiver PHY Reset Controller IP............................... 261

4.4.2. Transceiver PHY Reset Controller Parameters............................................. 261

4.4.3. Transceiver PHY Reset Controller Interfaces............................................... 264

4.4.4. Transceiver PHY Reset Controller Resource Utilization.................................. 267

4.5. Using a User-Coded Reset Controller.....................................................................267

4.5.1. User-Coded Reset Controller Signals......................................................... 268

4.6. Combining Status or PLL Lock Signals .................................................................. 269

4.7. Timing Constraints for Bonded PCS and PMA Channels............................................ 269

4.8. Resetting Transceiver Channels Revision History..................................................... 271

5. Cyclone 10 GX Transceiver PHY Architecture............................................................. 272

5.1. Cyclone 10 GX PMA Architecture......................................................................... 272

5.1.1. Transmitter........................................................................................... 272

5.1.2. Serializer............................................................................................. 272

5.1.3. Transmitter Buffer.................................................................................. 273

5.1.4. Receiver................................................................................................275

5.1.5. Receiver Buffer...................................................................................... 276

5.1.6. Clock Data Recovery (CDR) Unit...............................................................280

5.1.7. Deserializer.......................................................................................... 281

5.1.8. Loopback.............................................................................................. 282

5.2. Cyclone 10 GX Enhanced PCS Architecture........................................................... 283

5.2.1. Transmitter Datapath.............................................................................284

5.2.2. Receiver Datapath.................................................................................291

5.3. Cyclone 10 GX Standard PCS Architecture............................................................ 299

5.3.1. Transmitter Datapath..............................................................................300

5.3.2. Receiver Datapath..................................................................................305

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Contents

5.4. Intel Cyclone 10 GX Transceiver PHY Architecture Revision History............................314

6. Reconfiguration Interface and Dynamic Reconfiguration .......................................... 315

6.1. Reconfiguring Channel and PLL Blocks...................................................................315

6.2. Interacting with the Reconfiguration Interface........................................................316

6.2.1. Reading from the Reconfiguration Interface............................................... 318

6.2.2. Writing to the Reconfiguration Interface.................................................... 318

6.3. Configuration Files............................................................................................. 319

6.4. Multiple Reconfiguration Profiles...........................................................................321

6.5. Embedded Reconfiguration Streamer.................................................................... 322

6.6. Arbitration.........................................................................................................325

6.7. Recommendations for Dynamic Reconfiguration......................................................327

6.8. Steps to Perform Dynamic Reconfiguration............................................................ 328

6.9. Direct Reconfiguration Flow................................................................................. 330

6.10. Native PHY IP or PLL IP Core Guided Reconfiguration Flow..................................... 331

6.11. Reconfiguration Flow for Special Cases................................................................ 333

6.11.1. Switching Transmitter PLL ....................................................................333

6.11.2. Switching Reference Clocks....................................................................335

6.12. Changing PMA Analog Parameters......................................................................338

6.12.1. Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow................. 341

6.12.2. Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow.. 342

6.12.3. Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow...343

6.13. Ports and Parameters........................................................................................346

6.14. Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks...................... 351

6.15. Embedded Debug Features................................................................................ 353

6.15.1. Native PHY Debug Master Endpoint......................................................... 354

6.15.2. Optional Reconfiguration Logic............................................................... 354

6.16. Using Data Pattern Generators and Checkers....................................................... 359

6.16.1. Using PRBS Data Pattern Generator and Checker..................................... 359

6.16.2. Using Pseudo Random Pattern Mode........................................................368

6.17. Timing Closure Recommendations...................................................................... 369

6.18. Unsupported Features.......................................................................................371

6.19. Cyclone 10 GX Transceiver Register Map.............................................................372

6.20. Reconfiguration Interface and Dynamic Reconfiguration Revision History..................372

7. Calibration.................................................................................................................. 373

7.1. Reconfiguration Interface and Arbitration with PreSICE Calibration Engine .................373

7.2. Calibration Registers...........................................................................................375

7.2.1. Avalon Memory-Mapped Interface Arbitration Registers............................... 375

7.2.2. Transceiver Channel Calibration Registers..................................................376

7.2.3. Fractional PLL Calibration Registers...........................................................376

7.2.4. ATX PLL Calibration Registers...................................................................377

7.2.5. Capability Registers................................................................................377

7.2.6. Rate Switch Flag Register........................................................................379

7.3. Power-up Calibration.......................................................................................... 380

7.4. User Recalibration.............................................................................................. 383

7.4.1. Conditions That Require User Recalibration................................................ 383

7.4.2. User Recalibration Sequence ...................................................................384

7.5. Calibration Example............................................................................................385

7.5.1. ATX PLL Recalibration............................................................................. 385

7.5.2. Fractional PLL Recalibration..................................................................... 385

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Contents

7.5.3. CDR/CMU PLL Recalibration..................................................................... 386

7.5.4. PMA Recalibration...................................................................................386

7.6. Calibration Revision History................................................................................. 387

8. Analog Parameter Settings........................................................................................ 388

8.1. Making Analog Parameter Settings using the Assignment Editor................................388

8.2. Updating Quartus Settings File with the Known Assignment.................................... 388

8.3. Analog Parameter Settings List............................................................................389

8.4. Receiver General Analog Settings........................................................................ 390

8.4.1. XCVR_C10_RX_TERM_SEL......................................................................390

8.5. Receiver Analog Equalization Settings.................................................................. 390

8.5.1. CTLE Settings........................................................................................ 391

8.5.2. VGA Settings......................................................................................... 393

8.6. Transmitter General Analog Settings.................................................................... 393

8.6.1. XCVR_C10_TX_TERM_SEL.......................................................................394

8.6.2. XCVR_C10_TX_COMPENSATION_EN........................................................ 394

8.6.3. XCVR_C10_TX_SLEW_RATE_CTRL............................................................395

8.7. Transmitter Pre-Emphasis Analog Settings............................................................395

8.7.1. XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T............................................396

8.7.2. XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T............................................396

8.7.3. XCVR_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP........................................397

8.7.4. XCVR_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP....................................... 397

8.7.5. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T......................... 398

8.7.6. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T......................... 398

8.7.7. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP..................... 399

8.7.8. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP.....................399

8.8. Transmitter VOD Settings....................................................................................400

8.8.1. XCVR_C10_TX_VOD_OUTPUT_SWING_CTRL.............................................400

8.9. Dedicated Reference Clock Settings...................................................................... 401

8.9.1. XCVR_C10_REFCLK_TERM_TRISTATE.......................................................401

8.9.2. XCVR_C10_TX_XTX_PATH_ANALOG_MODE................................................401

8.10. Unused Transceiver Channels Settings.................................................................402

8.11. Analog Parameter Settings Revision History......................................................... 402

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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1. Intel® Cyclone® 10 GX Transceiver PHY Overview

This user guide provides details about the Intel® Cyclone® 10 GX transceiver physical (PHY) layer architecture, PLLs, clock networks, and transceiver PHY IP core. Intel Quartus® Prime Pro Edition software version 17.1 supports the Intel Cyclone 10 GX transceiver PHY IP core. It also provides protocol specific implementation details and describes features such as transceiver reset and dynamic reconfiguration of transceiver channels and PLLs.

Intel’s FPGA Intel Cyclone 10 GX devices offer up to 12 transceiver channels with integrated advanced high speed analog signal conditioning and clock data recovery techniques.

The Intel Cyclone 10 GX devices have transceiver channels that can support data rates up to 12.5 Gbps for chip-to-chip and chip-to-module communication, and up to 6.6 Gbps for backplane communication. You can achieve transmit and receive data rates below 1.0 Gbps with oversampling.

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

ISO 9001:2015 Registered

Core Logic Fabric

M20K Internal Memory Blocks

Transceiver Channels

Hard IP Per Transceiver: Standard PCS, Enhanced PCS

PCI Express Gen2 Hard IP

PLLs

M20K Internal Memory Blocks

Variable Precision DSP Blocks

I/O PLLs

Hard Memory Controllers, General-Purpose I/O Cells, LVDS

M20K Internal Memory BlocksM20K Internal Memory Blocks

Variable Precision DSP Blocks

Core Logic Fabric

I/O PLLs

Hard Memory Controllers, General-Purpose I/O Cells, LVDS

M20K Internal Memory BlocksM20K Internal Memory Blocks

Variable Precision DSP Blocks

1. Intel

Cyclone® 10 GX Transceiver PHY Overview

1.1. Device Transceiver Layout

Figure 1. Intel Cyclone 10 GX FPGA Architecture Block Diagram

The transceiver channels are placed on the left side periphery in Intel Cyclone 10 GX devices.

UG-20070 | 2020.05.15

1.1.1. Intel Cyclone 10 GX Device Transceiver Layout

Intel Cyclone 10 GX devices offer 6-, 10-, or 12-transceiver channel counts. Each transceiver bank has up to six transceiver channels. Intel Cyclone 10 GX devices also have one embedded PCI Express Hard IP block.

The figures below illustrate different transceiver bank layouts for Intel Cyclone 10 GX device variants.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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Transceiver

Bank

GXBL1D

Transceiver

Bank

GXBL1C

Transceiver

Bank

Transceiver

Bank

CH5

CH4 CH3

CH2

CH1 CH0

Transceiver

Bank

Legend:

PCIe Gen1 - Gen2 Hard IP blocks with Configuration via Protocol (CvP) capabilities.

Cyclone 10 GX device with 12 transceiver channels and one PCIe Hard IP block.

PCIe

Gen1 - Gen2

Hard IP

(with CvP)

Transceiver

Bank

GXBL1D

Transceiver

Bank

GXBL1C

Transceiver

Bank

Transceiver

Bank

CH5

CH4 CH3

CH2

CH1 CH0

Transceiver

Bank

Legend:

PCIe Gen1 - Gen2 Hard IP blocks with Configuration via Protocol (CvP) capabilities.

Cyclone 10 GX device with 10 transceiver channels and one PCIe Hard IP block.

PCIe

Gen1 - Gen2

Hard IP

(with CvP)

Transceiver

Bank

GXBL1C Transceiver

Bank

CH5

CH4 CH3

CH2

CH1 CH0

Transceiver

Bank

GXBL1C

Note:

Legend:

PCIe Gen1 - Gen2 Hard IP block with Configuration via Protocol (CvP) capabilities.

Cyclone 10 GX device with six transceiver channels and one PCIe Hard IP block.

PCIe

Gen1 - Gen2

Hard IP (with CvP)

(1)

(1) Only CH5 and CH4 support PCIe Hard IP block with CvP capabilities.

1. Intel® Cyclone® 10 GX Transceiver PHY Overview

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Figure 2. Intel Cyclone 10 GX Devices with 12 Transceiver Channels and One PCIe Hard

IP Block

Figure 3. Intel Cyclone 10 GX Devices with 10 Transceiver Channels and One PCIe Hard

IP Block

Figure 4. Intel Cyclone 10 GX Devices with 6 Transceiver Channels and One PCIe Hard

IP Block

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1. Intel

Cyclone® 10 GX Transceiver PHY Overview

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1.1.2. Intel Cyclone 10 GX Device Package Details

The following tables list package sizes, available transceiver channels, and PCI Express Hard IP blocks for Intel Cyclone 10 GX devices.

Table 1. Package Details for Devices with Transceivers and Hard IP Blocks Located on

the Left Side Periphery of the Device

• Package U484: 19mm x 19mm package; 484 pins.

• Package F672: 27mm x 27mm package; 672 pins.

• Package F780: 29mm x 29mm package; 780 pins.

Device

10CX085 6, 1 6, 1 N/A

10CX105 6, 1 10, 1 12, 1

10CX150 6, 1 10, 1 12, 1

10CX220 6, 1 10, 1 12, 1

U484 F672 F780

Transceiver Count, PCIe Hard IP Block Count

1.2. Transceiver PHY Architecture Overview

A link is defined as a single entity communication port. A link can have one or more transceiver channels. A transceiver channel is synonymous with a transceiver lane.

For example, a 10GBASE-R link has one transceiver channel or lane with a data rate of

10.3125 Gbps. A 40GBASE-R link has four transceiver channels. Each transceiver channel operates at a lane data rate of 10.3125 Gbps. Four transceiver channels give a total collective link bandwidth of 41.25 Gbps (40 Gbps before and after 64B/66B Physical Coding Sublayer (PCS) encoding and decoding).

1.2.1. Transceiver Bank Architecture

The transceiver bank is the fundamental unit that contains all the functional blocks related to the device's high speed serial transceivers.

Each transceiver bank includes four or six transceiver channels in all devices.

The figures below show the transceiver bank architecture with the phase locked loop (PLL) and clock generation block (CGB) resources available in each bank.

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PMA

Channel PLL

(CDR Only)

PCS

Local CGB5

CH5

PMA

Channel PLL

(CMU/CDR)

PCS

Local CGB4

CH4

PMA

Channel PLL

(CDR Only)

PCS

Local CGB3

CH3

PMA

Channel PLL

(CDR Only)

PCS

Local CGB2

CH2

PMA

Channel PLL

(CMU/CDR)

PCS

Local CGB1

CH1

PMA

Channel PLL

(CDR Only)

PCS

Local CGB0

CH0

FPGA Core

Fabric

Clock

Distribution

Network

Six-Channel Transceiver Bank

fPLL1

Master CGB1

Master CGB0

ATX PLL0

ATX

PLL1

fPLL0

Legend:

4-Channel transceiver bank

1. Intel

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Figure 5. Transceiver Bank Architecture

Cyclone® 10 GX Transceiver PHY Overview

Note: This figure is a high level overview of the transceiver bank architecture. For details

1.2.2. PHY Layer Transceiver Components

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about the available clock networks refer to the PLLs and Clock Networks chapter.

Related Information

PLLs and Clock Networks on page 198

Transceivers in Intel Cyclone 10 GX devices support both Physical Medium Attachment (PMA) and Physical Coding Sublayer (PCS) functions at the physical (PHY) layer.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

Standard PCS

Enhanced PCS

PCS Direct

Hard IP

(Optional)

Soft PIPE (Optional)

FPGA Fabric

Transmitter PCS

Transmitter PMA

Serializer

Standard PCS

Enhanced PCS

PCS Direct

Receiver PCS

Receiver PMA

DeserializerCDR

Notes: (1) The FPGA Fabric - PCS and PCS-PMA interface widths are configurable.

(1)

1. Intel® Cyclone® 10 GX Transceiver PHY Overview

A PMA is the transceiver's electrical interface to the physical medium. The transceiver PMA consists of standard blocks such as:

• serializer/deserializer (SERDES)

• clock and data recovery PLL

• analog front end transmit drivers

• analog front end receive buffers

The PCS can be bypassed with a PCS Direct configuration. Both the PMA and PCS blocks are fed by multiple clock networks driven by high performance PLLs. In PCS Direct configuration, the data flow is through the PCS block, but all the internal PCS blocks are bypassed. In this mode, the PCS functionality is implemented in the FPGA fabric.

1.2.2.1. The Transceiver Channel

Figure 6. Transceiver Channel in Full Duplex Mode

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Intel Cyclone 10 GX transceiver channels have three types of PCS blocks that together support continuous data rates between 1.0 Gbps and 10.81344 Gbps.

Table 2. PCS Types Supported by Transceiver Channels

PCS Type Data Rate

Standard PCS 1.0 Gbps to 10.81344 Gbps

Enhanced PCS 1.0 Gbps to 12.5 Gbps

PCS Direct 1.0 Gbps to 12.5 Gbps

Note: The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver.

For transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter. For receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.

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Cyclone® 10 GX Transceiver PHY Overview

1.2.3. Transceiver Phase-Locked Loops

Each transceiver channel in Intel Cyclone 10 GX devices has direct access to three types of high performance PLLs:

• Advanced Transmit (ATX) PLL

• Fractional PLL (fPLL)

• Channel PLL / Clock Multiplier Unit (CMU) PLL

These transceiver PLLs along with the Master or Local Clock Generation Blocks (CGB) drive the transceiver channels.

Related Information

PLLs on page 200

1.2.3.1. Advanced Transmit (ATX) PLL

An advanced transmit (ATX ) PLL is a high performance PLL that only supports integer frequency synthesis. The ATX PLL is the transceiver channel’s primary transmit PLL. It can operate over the full range of supported data rates required for high data rate applications.

Related Information

ATX PLL on page 201

1.2.3.2. Fractional PLL (fPLL)

A fractional PLL (fPLL) is an alternate transmit PLL that generates clock frequencies for up to 12.5 Gbps data rate applications. fPLLs support both integer frequency synthesis and fine resolution fractional frequency synthesis. Unlike the ATX PLL, the fPLL can also be used to synthesize frequencies that can drive the core through the FPGA fabric clock networks.

Related Information

fPLL on page 203

1.2.3.3. Channel PLL (CMU/CDR PLL)

A channel PLL resides locally within each transceiver channel. Its primary function is clock and data recovery in the transceiver channel when the PLL is used in clock data recovery (CDR) mode. The channel PLLs of channel 1 and 4 can be used as transmit PLLs when configured in clock multiplier unit (CMU) mode. The channel PLLs of channel 0, 2, 3, and 5 cannot be configured in CMU mode and therefore cannot be used as transmit PLLs.

Related Information

CMU PLL on page 206

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1.2.4. Clock Generation Block (CGB)

In Intel Cyclone 10 GX devices, there are two types of clock generation blocks (CGBs):

• Master CGB

• Local CGB

Transceiver banks with six transceiver channels have two master CGBs. Master CGB1 is located at the top of the transceiver bank and master CGB0 is located at the bottom of the transceiver bank. The master CGB divides and distributes bonded clocks to a bonded channel group. It also distributes non-bonded clocks to non-bonded channels across the x6/xN clock network.

Each transceiver channel has a local CGB. The local CGB is used for dividing and distributing non-bonded clocks to its own PCS and PMA blocks.

Related Information

Clock Generation Block on page 216

1.3. Calibration

Intel Cyclone 10 GX FPGAs contain a dedicated calibration engine to compensate for process variations. The calibration engine calibrates the analog portion of the transceiver to allow both the transmitter and receiver to operate at optimum performance.

1. Intel

Cyclone® 10 GX Transceiver PHY Overview

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Note:

The CLKUSR pin clocks the calibration engine. All transceiver reference clocks and the

CLKUSR clock must be free running and stable at the start of FPGA configuration to

successfully complete the calibration process and for optimal transceiver performance.

For more information about CLKUSR electrical characteristics, refer to Intel Cyclone 10 GX Device Datasheet. The CLKUSR can also be used as an FPGA configuration clock. For information about configuration requirements for the CLKUSR pin, refer to the

Configuration, Design Security, and Remote System Upgrades in Intel Cyclone 10 GX Devices chapter in the Intel Cyclone 10 GX Core Fabric and General-Purpose I/O Handbook. For more information about calibration, refer to the Calibration chapter. For more information about CLKUSR pin requirements, refer to the Intel Cyclone 10 GX Device Family Pin Connection Guidelines.

Related Information

• Calibration on page 373

• Intel Cyclone 10 GX Device Datasheet

• Configuration, Design Security, and Remote System Upgrades in Intel Cyclone 10

GX Devices

• Intel Cyclone 10 GX Device Family Pin Connection Guidelines

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1.4. Intel Cyclone 10 GX Transceiver PHY Overview Revision History

Document

Version

2017.12.28 Made the following changes:

• Updated the "Intel Cyclone 10 GX Default Settings Preset" Figure.

• Changed the transceiver count back to 6 for 10CX085 package F672 in the "Package Details for Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device" table.

2017.11.06 Made the following changes:

• Changed the description of the ATX PLL in the "Advanced Transmit (ATX) PLL" section.

• Changed the transceiver counts for the F672 package in the "Package Details for Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device" table.

• Changed the description of the Fractional PLL in the "Fractional PLL (fPLL)" section.

• Changed the location of the PCIe Hard IP block in the " Cyclone 10 GX Devices with 12 Transceiver Channels and One PCIe Hard IP Block" figure.

• Changed the location of the PCIe Hard IP block in the " Cyclone 10 GX Devices with 10 Transceiver Channels and One PCIe Hard IP Block" figure.

• Changed the location of the PCIe Hard IP block in the " Cyclone 10 GX Devices with 6 Transceiver Channels and One PCIe Hard IP Block" figure.

2017.05.08 Initial release.

Changes

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Transceiver PLL IP Core

Master/Local

Clock

Generation

Block

Avalon-MM Master

Reset Ports

Analog and Digital

Reset Bus

Reconfiguration

Registers

Avalon-MM

Interface

Non-Bonded and

Bonded Clocks

Transceiver PHY IP Core

(1)

Note:

Transceiver PHY Reset Controller

(2)

Legend:

Intel generated IP block

User created IP block

MAC IP Core /

Data Generator /

Data Analyzer

Parallel Data Bus

Avalon master allows access to Avalon-MM reconfiguration registers via the Avalon Memory Mapped interface. It enables PCS, PMA , and PLL reconfiguration. To access the reconfiguration registers, implement an Avalon master in the FPGA fabric. This faciliates reconfiguration by performing reads and writes through the Avalon-MM interface.

Transceiver PLL IP core provides a clock source to clock networks that drive the transceiver channels. In Cyclone 10 devices, PLL IP Core is separate from the transceiver PHY IP core.

Reset controller is used for resetting the transceiver channels.

This block can be either a MAC IP core, or a frame generator / analyzer or a data generator / analyzer.

Transceiver PHY IP core controls the PCS and PMA configurations and transceiver channels functions for all communication protocols.

(1) The Transceiver PHY IP core can be one of the supported PHY IP Cores ( For example: Native PHY IP Core). (2) You can either design your own reset controller or use the Transceiver PHY Reset Controller.

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2.1. Transceiver Design IP Blocks

Note: Intel Cyclone 10 GX only supported with Intel Quartus Prime Pro Edition 17.1 and

future versions.

Figure 7. Cyclone 10 GX Transceiver Design Fundamental Building Blocks

ISO 9001:2015 Registered

Generate PHY IP Core

Connect Transceiver Datapath to MAC IP Core or to a Data Generator / Analyzer

Select PLL IP Core

Generate the Transceiver PHY Reset Controller

or create your own User-Coded Reset Controller

Compile Design

Verify Design Functionality

Generate PLL IP Core

Configure the PHY IP Core

Select PHY IP Core

Configure the PLL IP Core

Connect PHY IP Core to PLL IP Core, Reset Controller, and connect reconfiguration logic via Avalon-MM interface

Create reconfiguration logic

(if needed)

Make analog parameter settings to I/O pins using the Assignment Editor or updating the Quartus Prime Settings File

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2.2. Transceiver Design Flow

Figure 8. Transceiver Design Flow

2.2.1. Select and Instantiate the PHY IP Core

Select the appropriate PHY IP core to implement your protocol.

Refer to the Cyclone 10 GX Transceiver Protocols and PHY IP Support section to decide which PHY IP to select to implement your protocol.

You can create your Quartus Prime project first, and then instantiate the various IPs required for your design. In this case, specify the location to save your IP HDL files. The current version of the PHY IP does not have the option to set the speed grade. Specify the device family and speed grade when you create the Quartus Prime project.

You can also instantiate the PHY IP directly to evaluate the various features.

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To instantiate a PHY IP:

1. Open the Quartus Prime software.

Click Tools ➤ IP Catalog.

3. At the top of the IP Catalog window, select Cyclone 10 GX device family

In IP Catalog, under Library ➤ Interface Protocols, select the appropriate PHY

IP and then click Add.

5. In the New IP Instance Dialog Box, provide the IP instance name.

6. Select Cyclone 10 GX device family.

7. Select the appropriate device and click OK.

The PHY IP Parameter Editor window opens.

Figure 9. Cyclone 10 GX Transceiver PHY Types

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2.2.2. Configure the PHY IP Core

Configure the PHY IP core by selecting the valid parameters for your design. The valid parameter settings are different for each protocol. Refer to the appropriate protocol's section for selecting valid parameters for each protocol.

2.2.3. Generate the PHY IP Core

After configuring the PHY IP, complete the following steps to generate the PHY IP.

1. Click the Generate HDL button in the Parameter Editor window. The Generation dialog box opens.

In Synthesis options, under Create HDL design for synthesis select Verilog or VHDL.

3. Select appropriate Simulation options depending on the choice of the hardware description language you selected under Synthesis options.

4. In Output Directory, select Clear output directories for selected generation targets if you want to clear any previous IP generation files from the selected output directory.

5. Click Generate.

The Quartus Prime software generates a <phy ip instance name> folder, <phy ip

instance name>_sim folder, <phy ip instance name>.qip file, <phy ip instance name>.qsys file, and <phy ip instance name>.v file or <phy ip instance name>.vhd

file. This <phy ip instance name>.v file is the top level design file for the PHY IP and is placed in the <phy ip instance name>/synth folder. The other folders contain lower level design files used for simulation and compilation.

Related Information

IP Core File Locations on page 67

For more information about IP core file structure

2.2.4. Select the PLL IP Core

Cyclone 10 GX devices have three types of PLL IP cores:

• Advanced Transmit (ATX) PLL IP core.

• Fractional PLL (fPLL) IP core.

• Channel PLL / Clock Multiplier Unit (CMU) PLL IP core.

Select the appropriate PLL IP for your design. For additional details, refer to the PLLs and Clock Networks chapter.

To instantiate a PLL IP:

1. Open the Quartus Prime software.

Click Tools ➤ IP Catalog.

3. At the top of the IP Catalog window, select Cyclone 10 GX device family

In IP Catalog, under Library ➤ Basic Functions ➤ Clocks, PLLs, and Resets

➤ PLL choose the PLL IP ( Cyclone 10 GX fPLL, Cyclone 10 GX Transceiver

ATX PLL, or Cyclone 10 GX Transceiver CMU PLL) you want to include in your design and then click Add.

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5. In the New IP Instance Dialog Box, provide the IP instance name.

6. Select Cyclone 10 GX device family.

7. Select the appropriate device and click OK.

The PLL IP GUI window opens.

Figure 10. Cyclone 10 GX Transceiver PLL Types

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2.2.5. Configure the PLL IP Core

Understand the available PLLs, clock networks, and the supported clocking configurations. Configure the PLL IP to achieve the adequate data rate for your design.

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2.2.6. Generate the PLL IP Core

After configuring the PLL IP core, complete the following steps to generate the PLL IP core.

1. Click the Generate HDL button in the Parameter Editor window. The Generation dialog box opens.

In Synthesis options, under Create HDL design for synthesis select Verilog or VHDL.

3. Select appropriate Simulation options depending on the choice of the hardware description language you selected under Synthesis options.

4. In Output Directory, select Clear output directories for selected generation targets if you want to clear any previous IP generation files from the selected output directory.

5. Click Generate.

The Quartus ® Prime software generates a <pll ip core instance name> folder, <pll ip

core instance name>_sim folder, <pll ip core instance name>.qip file, <pll ip core instance name>.qsys, and <pll ip core instance name>.v file or <pll ip core instance name>.vhd file. The <pll ip core instance name>.v file is the top level design file for

the PLL IP core and is placed in the <pll ip core instance name>/ synth folder. The other folders contain lower level design files used for simulation and compilation.

Related Information

IP Core File Locations on page 67

For more information about IP core file structure

2.2.7. Reset Controller

There are two methods to reset the transceivers in Cyclone 10 GX devices:

• Use the Transceiver PHY Reset Controller.

• Create your own reset controller that follows the recommended reset sequence.

Related Information

Resetting Transceiver Channels on page 243

2.2.8. Create Reconfiguration Logic

Dynamic reconfiguration is the ability to dynamically modify the transceiver channels and PLL settings during device operation. To support dynamic reconfiguration, your design must include an Avalon master that can access the dynamic reconfiguration registers using the Avalon® memory-mapped interface.

The Avalon memory-mapped interface master enables PLL and channel reconfiguration. You can dynamically adjust the PMA parameters, such as differential output voltage swing (Vod), and pre-emphasis settings. This adjustment can be done by writing to the Avalon memory-mapped interface reconfiguration registers through the user generated Avalon memory-mapped interface master.

For detailed information on dynamic reconfiguration, refer to Reconfiguration Interface and Dynamic Reconfiguration chapter.

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2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller

Connect the PHY IP, PLL IP core, and the reset controller. Write the top level module to connect all the IP blocks.

All of the I/O ports for each IP, can be seen in the <phy instance name>.v file or <phy instance name>.vhd, and in the <phy_instance_name>_bb.v file.

For more information about description of the ports, refer to the ports tables in the PLLs, Using the Transceiver Native PHY IP Core, and Resetting Transceiver Channels chapters.

Related Information

• Resetting Transceiver Channels on page 243

• Using the Cyclone 10 GX Transceiver Native PHY IP Core on page 26

• PLLs and Clock Networks on page 198

2.2.10. Connect Datapath

Connect the transceiver PHY layer design to the Media Access Controller (MAC) IP core or to a data generator / analyzer or a frame generator / analyzer.

2.2.11. Make Analog Parameter Settings

Make analog parameter settings to I/O pins using the Assignment Editor or updating the Quartus Prime Settings File.

After verifying your design functionality, make pin assignments and PMA analog parameter settings for the transceiver pins.

1. Assign FPGA pins to all the transceiver and reference clock I/O pins.

2. Set the analog parameters to the transmitter, receiver, and reference clock pins using the Assignment Editor. All of the pin assignments and analog parameters set using the Pin Planner and the Assignment Editor are saved in the <top_level_project_name>.qsf file. You can also directly modify the Quartus Settings File (.qsf) to set PMA analog parameters.

2.2.12. Compile the Design

To compile the transceiver design, add the <phy_instancename>.qip files for all the IP blocks generated using the IP Catalog to the Quartus Prime project library. You can alternatively add the .qsys and .qip variants of the IP cores.

Note: If you add both the .qsys and the .qip file into the Quartus Prime project, the

software generates an error.

2.2.13. Verify Design Functionality

Simulate your design to verify the functionality of your design. For more details, refer to Simulating the Native Transceiver PHY IP Core section.

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Related Information

Intel Quartus Prime Pro Edition Handbook Volume 3: Verification

Information about design simulation and verification.

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2.3. Cyclone 10 GX Transceiver Protocols and PHY IP Support

Table 3. Cyclone 10 GX Transceiver Protocols and PHY IP Support

Protocol Transceiver PHY IP

PCIe Gen2 x1, x2, x4 Native PHY IP (PIPE)

PCIe Gen1 x1, x2, x4 Native PHY IP (PIPE)

1000BASE-X Gigabit

Ethernet

1000BASE-X Gigabit

Ethernet with 1588

10GBASE-R Native PHY IP core Enhanced 10GBASE-R 10GBASE-R Low

10GBASE-R 1588 Native PHY IP core Enhanced 10GBASE-R 1588 10GBASE-R

40GBASE-R Native PHY IP core Enhanced Basic (Enhanced PCS) Low Latency Enhanced

Interlaken (CEI-6G-SR

and CEI-11G-SR)

OTU-1 (2.7G) Native PHY IP core Standard Basic/Custom

(6)

Core

core/Hard IP for PCI

Native PHY IP core Standard GbE GIGE - 1.25 Gbps

Native PHY IP core Standard GbE 1588 GIGE - 1.25 Gbps

Native PHY IP core Enhanced Interlaken Interlaken

Express

(1)

PCS Support Transceiver

Configuration Rule

Standard Gen2 PIPE PCIe PIPE Gen2 x1

Standard Gen1 PIPE User created

(Standard PCS)

Protocol Preset

1588

Latency

PCS

10x12.5Gbps

Interlaken

6x10.3Gbps

Interlaken

1x6.25Gbps

User created

continued...

(2)

(3)

(4)

(5)

(1)

Hard IP for PCI Express is also available as a separate IP core.

(2)

For x2 and x4 modes, select PCIe PIPE Gen2 x8. Then change the number of data channels from 8 to 4.

(3)

For PCIe Gen1 x1 mode, select PCIe PIPE Gen2 x1 mode. Then change the transceiver configuration rule from Gen 2 PIPE to Gen 1 PIPE.

For PCIe Gen1 x2 and x4 mode, select PCIe PIPE Gen2 x8. Then change the transceiver configuration rule from Gen2 PIPE to Gen1 PIPE and number of data channels from 8 to 2 or

(4)

Select the 10GBASE-R preset. Then change the transceiver configuration rule from 10GBASER to 10GBASE-R 1588.

(5)

To implement 40GBASE-R using the Low Latency Enhanced PCS preset, change the number of data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.

(6)

Link training, auto speed negotiation and sequencer functions are not included in the Native PHY IP. The user would have to create soft logic to implement these functions when using Native PHY IP.

A Transmit PCS soft bonding logic required for multi-lane bonding configuration is provided in the design example.

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Protocol Transceiver PHY IP

SONET/SDH STS-192/ STM-64 (10G) via SFP

+/SFF-8431/CEI-11G

SONET/SDH STS-192/ STM-64 (10G) via OIF

SFI-5.1s/SxI-5/

SFI-4.2

SONET STS-96 (5G)

via OIF SFI-5.1s

SONET/SDH STS-48/

STM-16 (2.5G) via

SFP/TFI-5.1

SONET/SDH STS-12/

STM-4 (0.622G) via

SFP/TFI-5.1

SD-SDI/HD-

SDI/3G/6G/12G-SDI

Vx1 Native PHY IP core Standard Basic/Custom

DisplayPort Native PHY IP core Standard Basic/Custom

1.25G/ 2.5G

10G GPON/EPON

2.5G/1.25G GPON/ EPON

8G/4G/2G/1G Fibre

Channel

SDR/DDR Infiniband

x1, x4, x12

SRIO 2.2/1.3 Native PHY IP core Standard Basic/Custom with

CPRI 4.1/OBSAI RP3

v4.1

SAS 3.0 Native PHY IP core Enhanced Basic (Enhanced PCS) User created

Core

Native PHY IP core Enhanced Basic (Enhanced PCS) User created

Native PHY IP core Enhanced Basic/Custom

Native PHY IP core Standard Basic/Custom

Native PHY IP core

Native PHY IP core Standard Basic/Custom

Native PHY IP core Enhanced Basic (Enhanced PCS) User created

Native PHY IP core Standard Basic/Custom

Native PHY IP core Standard CPRI (Auto)/CPRI

(7)

PCS Support Transceiver

Configuration Rule

(Standard PCS)

Standard Basic/Custom

(Standard PCS)

Rate Match(Standard

PCS)

(Manual)

HD/3G SDI NTSC/PAL

SDI multi-rate (up to

DisplayPort Duplex 4

SYMBOLS PER CLOCK

Protocol Preset

SONET/SDH OC-96

SONET/SDH OC-48

SONET/SDH OC-12

12G) RX/TX

SDI triple-rate RX

User created

DisplayPort RX 4

DisplayPort TX 4

User created

Serial Rapid IO 1.25

Gbps

User created

(8)

continued...

(7)

The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver. If transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter. If receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.

(8)

Select CPRI 9.8 Gbps Auto/Manual Mode (Intel Arria® 10 only). Then change the datarate from 9830.4 Mbps to 6144 Mbps.

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Protocol Transceiver PHY IP

SATA 3.0/2.0/1.0 and

SAS 2.0/1.1/1.0

HiGig/HiGig+/HiGig2/

HiGig2+

JESD204A / JESD204B Native PHY IP core Standard and

Custom and other

protocols

Core

Native PHY IP core Standard Basic/Custom

Native PHY IP core Standard and

PCS Support Transceiver

Enhanced

PCS Direct

Configuration Rule

(Standard PCS)

Basic/Custom

(Standard PCS) Basic

(Enhanced PCS)

Basis/Custom

(Standard PCS)

Basic (Enhanced PCS)

Basic/Custom with

Rate Match (Standard

PCS)

PCS Direct

Protocol Preset

SAS Gen2/Gen1.1/

SATA Gen3/Gen2/

User created

2.4. Using the Cyclone 10 GX Transceiver Native PHY IP Core

This section describes the use of the Intel-provided Cyclone 10 GX Transceiver Native PHY IP core. This Native PHY IP core provides direct access to Cyclone 10 GX transceiver PHY features.

Use the Native PHY IP core to configure the transceiver PHY for your protocol

implementation. To instantiate the IP, click Tools ➤ IP Catalog to select your IP core

variation. Use the Parameter Editor to specify the IP parameters and configure the PHY IP for your protocol implementation. To quickly configure the PHY IP, select a preset that matches your protocol configuration as a starting point. Presets are PHY IP configuration settings for various protocols that are stored in the IP Parameter Editor. Presets are explained in detail in the Presets section below.

Gen1

You can also configure the PHY IP by selecting an appropriate Transceiver Configuration Rule. The transceiver configuration rules check the valid combinations of the PCS and PMA blocks in the transceiver PHY layer, and report errors or warnings for any invalid settings.

Use the Native PHY IP core to instantiate the following PCS options:

• Standard PCS

• Enhanced PCS

• PCS Direct

Based on the Transceiver Configuration Rule that you select, the PHY IP core selects the appropriate PCS. The PHY IP core allows you to select all the PCS blocks if you intend to dynamically reconfigure from one PCS to another. Refer to General and Datapath Parameters section for more details on how to enable PCS blocks for dynamic reconfiguration.

After you configure the PHY IP core in the Parameter Editor, click Generate HDL to generate the IP instance. The top level file generated with the IP instance includes all the available ports for your configuration. Use these ports to connect the PHY IP core to the PLL IP core, the reset controller IP core, and to other IP cores in your design.

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Reconfiguration

Registers

Enhanced PCS

Transmit and Receive Clocks

Standard PCS

Transmit

PMA

Receive

PMA

Reset Signals

Transmit Parallel Data

Reconfiguration Interface

Transmit Serial Data

Receive Serial Data

Receive Parallel Data

PCS-Direct

Nios II

Calibration

Calibration Signals

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Figure 11. Native PHY IP Core Ports and Functional Blocks

Figure 12. Native PHY IP Core Parameter Editor

Note: Although the Quartus Prime software provides legality checks, refer to the High-Speed

Serial Transceiver-Fabric Interface Performance for Intel Cyclone 10 GX Devices

section of theIntel Cyclone 10 GX Device Datasheet for the supported FPGA fabric to PCS interface widths and frequency.

Related Information

• Configure the PHY IP Core on page 19

• Interlaken on page 70

• Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 on page 87

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• 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants on page 98

• PCI Express (PIPE) on page 122

• CPRI on page 149

• Using the "Basic (Enhanced PCS)" Configuration on page 158

• Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard

• PMA Parameters on page 31

• Presets on page 28

• General and Datapath Parameters on page 28

• PMA Ports on page 50

• Enhanced PCS Ports on page 53

• Standard PCS Ports on page 62

• How to Place Channels for PIPE Configurations on page 146

• Intel Cyclone 10 GX Device Datasheet

2.4.1. Presets

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PCS on page 166

You can select preset settings for the Native PHY IP core defined for each protocol. Use presets as a starting point to specify parameters for your specific protocol or application.

To apply a preset to the Native PHY IP core, double-click on the preset name. When you apply a preset, all relevant options and parameters are set in the current instance of the Native PHY IP core. For example, selecting the Interlaken preset enables all parameters and ports that the Interlaken protocol requires.

Selecting a preset does not prevent you from changing any parameter to meet the requirements of your design. Any changes that you make are validated by the design rules for the transceiver configuration rules you specified, not the selected preset.

Note: Selecting a preset clears any prior selections user has made so far.

2.4.2. General and Datapath Parameters

You can customize your instance of the Native PHY IP core by specifying parameter values. In the Parameter Editor, the parameters are organized in the following sections for each functional block and feature:

• General, Common PMA Options, and Datapath Options

• TX PMA

• RX PMA

• Standard PCS

• Enhanced PCS

• PCS Direct Datapath

• Dynamic Reconfiguration

• Analog PMA Settings (Optional)

• Generation Options

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Table 4. General, Common PMA Options, and Datapath Options

Parameter Value Description

Message level for rule violations

VCCR_GXB and VCCT_GXB supply voltage for the Transceiver

Transceiver Link Type sr, lr Selects the type of transceiver link. sr-Short Reach (Chip-to-chip

Transceiver configuration rules

PMA configuration rules

Transceiver mode TX/RX Duplex

Number of data channels

Data rate < valid Transceiver data

Enable datapath and interface reconfiguration

error warning

0_9V, 1_0V

User Selection Specifies the valid configuration rules for the transceiver.

Basic SATA/SAS GPON

TX Simplex RX Simplex

1 – <n> Specifies the number of transceiver channels to be implemented.

rate >

On/Off When you turn this option on, you can preconfigure and

Specifies the messaging level for parameter rule violations. Selecting error causes all rule violations to prevent IP generation. Selecting warning displays all rule violations as warnings in the message window and allows IP generation despite the violations.

Selects the VCCR_GXB and VCCT_GXB supply voltage for the Transceiver.

Note: This option is only used for GUI rule validation. Use

Quartus Prime Setting File (.qsf) assignments to set this parameter in your static design.

communication), lr-Long Reach (Backplane communication).

Note: This option is only used for GUI rule validation. Use

Quartus Prime Setting File (.qsf) assignments to set this parameter in your static design.

This parameter specifies the configuration rule against which the Parameter Editor checks your PMA and PCS parameter settings for specific protocols. Depending on the transceiver configuration rule selected, the Parameter Editor validates the parameters and options selected by you and generates error messages or warnings for all invalid settings.

To determine the transceiver configuration rule to be selected for your protocol, refer to Table 3 on page 24 Transceiver Configuration Rule Parameters table for more details about each transceiver configuration rule.

This parameter is used for rule checking and is not a preset. You need to set all parameters for your protocol implementation.

Specifies the configuration rule for PMA. Select Basic for all other protocol modes except for SATA and

GPON . SATA (Serial ATA) can be used only if the Transceiver

configuration rule is set to Basic/Custom (Standard PCS). GPON can be used only if the Transceiver configuration rule is

set to Basic (Enhanced PCS).

Specifies the operational mode of the transceiver.

• TX/RX Duplex : Specifies a single channel that supports both transmission and reception.

• TX Simplex : Specifies a single channel that supports only transmission.

• RX Simplex : Specifies a single channel that supports only reception.

The default is TX/RX Duplex.

The maximum number of channels available, ( <n> ), depends on the package you select.

The default value is 1.

Specifies the data rate in megabits per second (Mbps).

dynamically switch between the Standard PCS, Enhanced PCS, and PCS direct datapaths.

continued...

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Parameter Value Description

The default value is Off.

Enable simplified data interface

Provide separate interface for each channel

On/Off

By default, all 128-bits are ports for the tx_parallel_data and

rx_parallel_data buses are exposed. You must understand the

mapping of data and control signals within the interface. Refer to the Enhanced PCS TX and RX Control Ports section for details about mapping of data and control signals.

When you turn on this option, the Native PHY IP core presents a simplified data and control interface between the FPGA fabric and transceiver. Only the sub-set of the 128-bits that are active for a particular FPGA fabric width are ports.

The default value is Off.

On/Off When selected the Native PHY IP core presents separate data,

reset and clock interfaces for each channel rather than a wide bus.

(9)

Table 5. Transceiver Configuration Rule Parameters

Transceiver Configuration Setting Description

Basic/Custom (Standard PCS) Enforces a standard set of rules within the Standard PCS. Select these rules to

Basic/Custom w /Rate Match (Standard PCS)

CPRI (Auto) Enforces rules required by the CPRI protocol. The receiver word aligner mode is

CPRI (Manual) Enforces rules required by the CPRI protocol. The receiver word aligner mode is

GbE Enforces rules that the 1 Gbps Ethernet (1 GbE) protocol requires.

GbE 1588 Enforces rules for the 1 GbE protocol with support for Precision time protocol

Gen1 PIPE Enforces rules for a Gen1 PCIe ® PIPE interface that you can connect to a soft

Gen2 PIPE Enforces rules for a Gen2 PCIe PIPE interface that you can connect to a soft MAC

Basic (Enhanced PCS) Enforces a standard set of rules within the Enhanced PCS. Select these rules to

Interlaken Enforces rules required by the Interlaken protocol.

10GBASE-R Enforces rules required by the 10GBASE-R protocol.

10GBASE-R 1588 Enforces rules required by the 10GBASE-R protocol with 1588 enabled.

PCS Direct Enforces rules required by the PCS Direct mode. In this configuration the data

implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules.

Enforces a standard set of rules including rules for the Rate Match FIFO within the Standard PCS. Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules.

set to Auto. In Auto mode, the word aligner is set to deterministic latency.

set to Manual. In Manual mode, logic in the FPGA fabric controls the word aligner.

(PTP) as defined in the IEEE 1588 Standard.

MAC and Data Link Layer.

and Data Link Layer.

implement protocols requiring blocks within the Enhanced PCS or protocols not covered by the other configuration rules.

flows through the PCS channel, but all the internal PCS blocks are bypassed. If required, the PCS functionality can be implemented in the FPGA fabric.

(9)

This option cannot be used, if you intend to dynamically reconfigure between PCS datapaths, or reconfigure the interface of the transceiver.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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