Intel Cyclone User Manual

Intel® Cyclone® 10 GX Transceiver PHY User Guide

Updated for Intel® Quartus® Prime Design Suite: 20.1

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1. Intel® Cyclone® 10 GX Transceiver PHY Overview

This user guide provides details about the Intel® Cyclone® 10 GX transceiver physical (PHY) layer architecture, PLLs, clock networks, and transceiver PHY IP core. Intel Quartus® Prime Pro Edition software version 17.1 supports the Intel Cyclone 10 GX transceiver PHY IP core. It also provides protocol specific implementation details and describes features such as transceiver reset and dynamic reconfiguration of transceiver channels and PLLs.

Intel’s FPGA Intel Cyclone 10 GX devices offer up to 12 transceiver channels with integrated advanced high speed analog signal conditioning and clock data recovery techniques.

The Intel Cyclone 10 GX devices have transceiver channels that can support data rates up to 12.5 Gbps for chip-to-chip and chip-to-module communication, and up to 6.6 Gbps for backplane communication. You can achieve transmit and receive data rates below 1.0 Gbps with oversampling.

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

ISO 9001:2015 Registered

Core Logic Fabric

M20K Internal Memory Blocks

Transceiver Channels

Hard IP Per Transceiver: Standard PCS, Enhanced PCS

PCI Express Gen2 Hard IP

PLLs

M20K Internal Memory Blocks

Variable Precision DSP Blocks

I/O PLLs

Hard Memory Controllers, General-Purpose I/O Cells, LVDS

M20K Internal Memory BlocksM20K Internal Memory Blocks

Variable Precision DSP Blocks

Core Logic Fabric

I/O PLLs

Hard Memory Controllers, General-Purpose I/O Cells, LVDS

M20K Internal Memory BlocksM20K Internal Memory Blocks

Variable Precision DSP Blocks

1. Intel

Cyclone® 10 GX Transceiver PHY Overview

1.1. Device Transceiver Layout

Figure 1. Intel Cyclone 10 GX FPGA Architecture Block Diagram

The transceiver channels are placed on the left side periphery in Intel Cyclone 10 GX devices.

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1.1.1. Intel Cyclone 10 GX Device Transceiver Layout

Intel Cyclone 10 GX devices offer 6-, 10-, or 12-transceiver channel counts. Each transceiver bank has up to six transceiver channels. Intel Cyclone 10 GX devices also have one embedded PCI Express Hard IP block.

The figures below illustrate different transceiver bank layouts for Intel Cyclone 10 GX device variants.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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Transceiver

Bank

GXBL1D

Transceiver

Bank

GXBL1C

Transceiver

Bank

Transceiver

Bank

CH5

CH4 CH3

CH2

CH1 CH0

Transceiver

Bank

Legend:

PCIe Gen1 - Gen2 Hard IP blocks with Configuration via Protocol (CvP) capabilities.

Cyclone 10 GX device with 12 transceiver channels and one PCIe Hard IP block.

PCIe

Gen1 - Gen2

Hard IP

(with CvP)

Transceiver

Bank

GXBL1D

Transceiver

Bank

GXBL1C

Transceiver

Bank

Transceiver

Bank

CH5

CH4 CH3

CH2

CH1 CH0

Transceiver

Bank

Legend:

PCIe Gen1 - Gen2 Hard IP blocks with Configuration via Protocol (CvP) capabilities.

Cyclone 10 GX device with 10 transceiver channels and one PCIe Hard IP block.

PCIe

Gen1 - Gen2

Hard IP

(with CvP)

Transceiver

Bank

GXBL1C Transceiver

Bank

CH5

CH4 CH3

CH2

CH1 CH0

Transceiver

Bank

GXBL1C

Note:

Legend:

PCIe Gen1 - Gen2 Hard IP block with Configuration via Protocol (CvP) capabilities.

Cyclone 10 GX device with six transceiver channels and one PCIe Hard IP block.

PCIe

Gen1 - Gen2

Hard IP (with CvP)

(1)

(1) Only CH5 and CH4 support PCIe Hard IP block with CvP capabilities.

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Figure 2. Intel Cyclone 10 GX Devices with 12 Transceiver Channels and One PCIe Hard

IP Block

Figure 3. Intel Cyclone 10 GX Devices with 10 Transceiver Channels and One PCIe Hard

IP Block

Figure 4. Intel Cyclone 10 GX Devices with 6 Transceiver Channels and One PCIe Hard

IP Block

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1.1.2. Intel Cyclone 10 GX Device Package Details

The following tables list package sizes, available transceiver channels, and PCI Express Hard IP blocks for Intel Cyclone 10 GX devices.

Table 1. Package Details for Devices with Transceivers and Hard IP Blocks Located on

the Left Side Periphery of the Device

• Package U484: 19mm x 19mm package; 484 pins.

• Package F672: 27mm x 27mm package; 672 pins.

• Package F780: 29mm x 29mm package; 780 pins.

Device

10CX085 6, 1 6, 1 N/A

10CX105 6, 1 10, 1 12, 1

10CX150 6, 1 10, 1 12, 1

10CX220 6, 1 10, 1 12, 1

U484 F672 F780

Transceiver Count, PCIe Hard IP Block Count

1.2. Transceiver PHY Architecture Overview

A link is defined as a single entity communication port. A link can have one or more transceiver channels. A transceiver channel is synonymous with a transceiver lane.

For example, a 10GBASE-R link has one transceiver channel or lane with a data rate of

10.3125 Gbps. A 40GBASE-R link has four transceiver channels. Each transceiver channel operates at a lane data rate of 10.3125 Gbps. Four transceiver channels give a total collective link bandwidth of 41.25 Gbps (40 Gbps before and after 64B/66B Physical Coding Sublayer (PCS) encoding and decoding).

1.2.1. Transceiver Bank Architecture

The transceiver bank is the fundamental unit that contains all the functional blocks related to the device's high speed serial transceivers.

Each transceiver bank includes four or six transceiver channels in all devices.

The figures below show the transceiver bank architecture with the phase locked loop (PLL) and clock generation block (CGB) resources available in each bank.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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PMA

Channel PLL

(CDR Only)

PCS

Local CGB5

CH5

PMA

Channel PLL

(CMU/CDR)

PCS

Local CGB4

CH4

PMA

Channel PLL

(CDR Only)

PCS

Local CGB3

CH3

PMA

Channel PLL

(CDR Only)

PCS

Local CGB2

CH2

PMA

Channel PLL

(CMU/CDR)

PCS

Local CGB1

CH1

PMA

Channel PLL

(CDR Only)

PCS

Local CGB0

CH0

FPGA Core

Fabric

Clock

Distribution

Network

Six-Channel Transceiver Bank

fPLL1

Master CGB1

Master CGB0

ATX PLL0

ATX

PLL1

fPLL0

Legend:

4-Channel transceiver bank

1. Intel

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Figure 5. Transceiver Bank Architecture

Cyclone® 10 GX Transceiver PHY Overview

Note: This figure is a high level overview of the transceiver bank architecture. For details

1.2.2. PHY Layer Transceiver Components

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about the available clock networks refer to the PLLs and Clock Networks chapter.

Related Information

PLLs and Clock Networks on page 198

Transceivers in Intel Cyclone 10 GX devices support both Physical Medium Attachment (PMA) and Physical Coding Sublayer (PCS) functions at the physical (PHY) layer.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

Standard PCS

Enhanced PCS

PCS Direct

Hard IP

(Optional)

Soft PIPE (Optional)

FPGA Fabric

Transmitter PCS

Transmitter PMA

Serializer

Standard PCS

Enhanced PCS

PCS Direct

Receiver PCS

Receiver PMA

DeserializerCDR

Notes: (1) The FPGA Fabric - PCS and PCS-PMA interface widths are configurable.

(1)

1. Intel® Cyclone® 10 GX Transceiver PHY Overview

A PMA is the transceiver's electrical interface to the physical medium. The transceiver PMA consists of standard blocks such as:

• serializer/deserializer (SERDES)

• clock and data recovery PLL

• analog front end transmit drivers

• analog front end receive buffers

The PCS can be bypassed with a PCS Direct configuration. Both the PMA and PCS blocks are fed by multiple clock networks driven by high performance PLLs. In PCS Direct configuration, the data flow is through the PCS block, but all the internal PCS blocks are bypassed. In this mode, the PCS functionality is implemented in the FPGA fabric.

1.2.2.1. The Transceiver Channel

Figure 6. Transceiver Channel in Full Duplex Mode

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Intel Cyclone 10 GX transceiver channels have three types of PCS blocks that together support continuous data rates between 1.0 Gbps and 10.81344 Gbps.

Table 2. PCS Types Supported by Transceiver Channels

PCS Type Data Rate

Standard PCS 1.0 Gbps to 10.81344 Gbps

Enhanced PCS 1.0 Gbps to 12.5 Gbps

PCS Direct 1.0 Gbps to 12.5 Gbps

Note: The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver.

For transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter. For receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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Cyclone® 10 GX Transceiver PHY Overview

1.2.3. Transceiver Phase-Locked Loops

Each transceiver channel in Intel Cyclone 10 GX devices has direct access to three types of high performance PLLs:

• Advanced Transmit (ATX) PLL

• Fractional PLL (fPLL)

• Channel PLL / Clock Multiplier Unit (CMU) PLL

These transceiver PLLs along with the Master or Local Clock Generation Blocks (CGB) drive the transceiver channels.

Related Information

PLLs on page 200

1.2.3.1. Advanced Transmit (ATX) PLL

An advanced transmit (ATX ) PLL is a high performance PLL that only supports integer frequency synthesis. The ATX PLL is the transceiver channel’s primary transmit PLL. It can operate over the full range of supported data rates required for high data rate applications.

Related Information

ATX PLL on page 201

1.2.3.2. Fractional PLL (fPLL)

A fractional PLL (fPLL) is an alternate transmit PLL that generates clock frequencies for up to 12.5 Gbps data rate applications. fPLLs support both integer frequency synthesis and fine resolution fractional frequency synthesis. Unlike the ATX PLL, the fPLL can also be used to synthesize frequencies that can drive the core through the FPGA fabric clock networks.

Related Information

fPLL on page 203

1.2.3.3. Channel PLL (CMU/CDR PLL)

A channel PLL resides locally within each transceiver channel. Its primary function is clock and data recovery in the transceiver channel when the PLL is used in clock data recovery (CDR) mode. The channel PLLs of channel 1 and 4 can be used as transmit PLLs when configured in clock multiplier unit (CMU) mode. The channel PLLs of channel 0, 2, 3, and 5 cannot be configured in CMU mode and therefore cannot be used as transmit PLLs.

Related Information

CMU PLL on page 206

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

1.2.4. Clock Generation Block (CGB)

In Intel Cyclone 10 GX devices, there are two types of clock generation blocks (CGBs):

• Master CGB

• Local CGB

Transceiver banks with six transceiver channels have two master CGBs. Master CGB1 is located at the top of the transceiver bank and master CGB0 is located at the bottom of the transceiver bank. The master CGB divides and distributes bonded clocks to a bonded channel group. It also distributes non-bonded clocks to non-bonded channels across the x6/xN clock network.

Each transceiver channel has a local CGB. The local CGB is used for dividing and distributing non-bonded clocks to its own PCS and PMA blocks.

Related Information

Clock Generation Block on page 216

1.3. Calibration

Intel Cyclone 10 GX FPGAs contain a dedicated calibration engine to compensate for process variations. The calibration engine calibrates the analog portion of the transceiver to allow both the transmitter and receiver to operate at optimum performance.

1. Intel

Cyclone® 10 GX Transceiver PHY Overview

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Note:

The CLKUSR pin clocks the calibration engine. All transceiver reference clocks and the

CLKUSR clock must be free running and stable at the start of FPGA configuration to

successfully complete the calibration process and for optimal transceiver performance.

For more information about CLKUSR electrical characteristics, refer to Intel Cyclone 10 GX Device Datasheet. The CLKUSR can also be used as an FPGA configuration clock. For information about configuration requirements for the CLKUSR pin, refer to the

Configuration, Design Security, and Remote System Upgrades in Intel Cyclone 10 GX Devices chapter in the Intel Cyclone 10 GX Core Fabric and General-Purpose I/O Handbook. For more information about calibration, refer to the Calibration chapter. For more information about CLKUSR pin requirements, refer to the Intel Cyclone 10 GX Device Family Pin Connection Guidelines.

Related Information

• Calibration on page 373

• Intel Cyclone 10 GX Device Datasheet

• Configuration, Design Security, and Remote System Upgrades in Intel Cyclone 10

GX Devices

• Intel Cyclone 10 GX Device Family Pin Connection Guidelines

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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1.4. Intel Cyclone 10 GX Transceiver PHY Overview Revision History

Document

Version

2017.12.28 Made the following changes:

• Updated the "Intel Cyclone 10 GX Default Settings Preset" Figure.

• Changed the transceiver count back to 6 for 10CX085 package F672 in the "Package Details for Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device" table.

2017.11.06 Made the following changes:

• Changed the description of the ATX PLL in the "Advanced Transmit (ATX) PLL" section.

• Changed the transceiver counts for the F672 package in the "Package Details for Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device" table.

• Changed the description of the Fractional PLL in the "Fractional PLL (fPLL)" section.

• Changed the location of the PCIe Hard IP block in the " Cyclone 10 GX Devices with 12 Transceiver Channels and One PCIe Hard IP Block" figure.

• Changed the location of the PCIe Hard IP block in the " Cyclone 10 GX Devices with 10 Transceiver Channels and One PCIe Hard IP Block" figure.

• Changed the location of the PCIe Hard IP block in the " Cyclone 10 GX Devices with 6 Transceiver Channels and One PCIe Hard IP Block" figure.

2017.05.08 Initial release.

Changes

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

Transceiver PLL IP Core

Master/Local

Clock

Generation

Block

Avalon-MM Master

Reset Ports

Analog and Digital

Reset Bus

Reconfiguration

Registers

Avalon-MM

Interface

Non-Bonded and

Bonded Clocks

Transceiver PHY IP Core

(1)

Note:

Transceiver PHY Reset Controller

(2)

Legend:

Intel generated IP block

User created IP block

MAC IP Core /

Data Generator /

Data Analyzer

Parallel Data Bus

Avalon master allows access to Avalon-MM reconfiguration registers via the Avalon Memory Mapped interface. It enables PCS, PMA , and PLL reconfiguration. To access the reconfiguration registers, implement an Avalon master in the FPGA fabric. This faciliates reconfiguration by performing reads and writes through the Avalon-MM interface.

Transceiver PLL IP core provides a clock source to clock networks that drive the transceiver channels. In Cyclone 10 devices, PLL IP Core is separate from the transceiver PHY IP core.

Reset controller is used for resetting the transceiver channels.

This block can be either a MAC IP core, or a frame generator / analyzer or a data generator / analyzer.

Transceiver PHY IP core controls the PCS and PMA configurations and transceiver channels functions for all communication protocols.

(1) The Transceiver PHY IP core can be one of the supported PHY IP Cores ( For example: Native PHY IP Core). (2) You can either design your own reset controller or use the Transceiver PHY Reset Controller.

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2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

2.1. Transceiver Design IP Blocks

Note: Intel Cyclone 10 GX only supported with Intel Quartus Prime Pro Edition 17.1 and

future versions.

Figure 7. Cyclone 10 GX Transceiver Design Fundamental Building Blocks

ISO 9001:2015 Registered

Generate PHY IP Core

Connect Transceiver Datapath to MAC IP Core or to a Data Generator / Analyzer

Select PLL IP Core

Generate the Transceiver PHY Reset Controller

or create your own User-Coded Reset Controller

Compile Design

Verify Design Functionality

Generate PLL IP Core

Configure the PHY IP Core

Select PHY IP Core

Configure the PLL IP Core

Connect PHY IP Core to PLL IP Core, Reset Controller, and connect reconfiguration logic via Avalon-MM interface

Create reconfiguration logic

(if needed)

Make analog parameter settings to I/O pins using the Assignment Editor or updating the Quartus Prime Settings File

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2.2. Transceiver Design Flow

Figure 8. Transceiver Design Flow

2.2.1. Select and Instantiate the PHY IP Core

Select the appropriate PHY IP core to implement your protocol.

Refer to the Cyclone 10 GX Transceiver Protocols and PHY IP Support section to decide which PHY IP to select to implement your protocol.

You can create your Quartus Prime project first, and then instantiate the various IPs required for your design. In this case, specify the location to save your IP HDL files. The current version of the PHY IP does not have the option to set the speed grade. Specify the device family and speed grade when you create the Quartus Prime project.

You can also instantiate the PHY IP directly to evaluate the various features.

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

To instantiate a PHY IP:

1. Open the Quartus Prime software.

Click Tools ➤ IP Catalog.

3. At the top of the IP Catalog window, select Cyclone 10 GX device family

In IP Catalog, under Library ➤ Interface Protocols, select the appropriate PHY

IP and then click Add.

5. In the New IP Instance Dialog Box, provide the IP instance name.

6. Select Cyclone 10 GX device family.

7. Select the appropriate device and click OK.

The PHY IP Parameter Editor window opens.

Figure 9. Cyclone 10 GX Transceiver PHY Types

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

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2.2.2. Configure the PHY IP Core

Configure the PHY IP core by selecting the valid parameters for your design. The valid parameter settings are different for each protocol. Refer to the appropriate protocol's section for selecting valid parameters for each protocol.

2.2.3. Generate the PHY IP Core

After configuring the PHY IP, complete the following steps to generate the PHY IP.

1. Click the Generate HDL button in the Parameter Editor window. The Generation dialog box opens.

In Synthesis options, under Create HDL design for synthesis select Verilog or VHDL.

3. Select appropriate Simulation options depending on the choice of the hardware description language you selected under Synthesis options.

4. In Output Directory, select Clear output directories for selected generation targets if you want to clear any previous IP generation files from the selected output directory.

5. Click Generate.

The Quartus Prime software generates a <phy ip instance name> folder, <phy ip

instance name>_sim folder, <phy ip instance name>.qip file, <phy ip instance name>.qsys file, and <phy ip instance name>.v file or <phy ip instance name>.vhd

file. This <phy ip instance name>.v file is the top level design file for the PHY IP and is placed in the <phy ip instance name>/synth folder. The other folders contain lower level design files used for simulation and compilation.

Related Information

IP Core File Locations on page 67

For more information about IP core file structure

2.2.4. Select the PLL IP Core

Cyclone 10 GX devices have three types of PLL IP cores:

• Advanced Transmit (ATX) PLL IP core.

• Fractional PLL (fPLL) IP core.

• Channel PLL / Clock Multiplier Unit (CMU) PLL IP core.

Select the appropriate PLL IP for your design. For additional details, refer to the PLLs and Clock Networks chapter.

To instantiate a PLL IP:

1. Open the Quartus Prime software.

Click Tools ➤ IP Catalog.

3. At the top of the IP Catalog window, select Cyclone 10 GX device family

In IP Catalog, under Library ➤ Basic Functions ➤ Clocks, PLLs, and Resets

➤ PLL choose the PLL IP ( Cyclone 10 GX fPLL, Cyclone 10 GX Transceiver

ATX PLL, or Cyclone 10 GX Transceiver CMU PLL) you want to include in your design and then click Add.

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5. In the New IP Instance Dialog Box, provide the IP instance name.

6. Select Cyclone 10 GX device family.

7. Select the appropriate device and click OK.

The PLL IP GUI window opens.

Figure 10. Cyclone 10 GX Transceiver PLL Types

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2.2.5. Configure the PLL IP Core

Understand the available PLLs, clock networks, and the supported clocking configurations. Configure the PLL IP to achieve the adequate data rate for your design.

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2.2.6. Generate the PLL IP Core

After configuring the PLL IP core, complete the following steps to generate the PLL IP core.

1. Click the Generate HDL button in the Parameter Editor window. The Generation dialog box opens.

In Synthesis options, under Create HDL design for synthesis select Verilog or VHDL.

3. Select appropriate Simulation options depending on the choice of the hardware description language you selected under Synthesis options.

4. In Output Directory, select Clear output directories for selected generation targets if you want to clear any previous IP generation files from the selected output directory.

5. Click Generate.

The Quartus ® Prime software generates a <pll ip core instance name> folder, <pll ip

core instance name>_sim folder, <pll ip core instance name>.qip file, <pll ip core instance name>.qsys, and <pll ip core instance name>.v file or <pll ip core instance name>.vhd file. The <pll ip core instance name>.v file is the top level design file for

the PLL IP core and is placed in the <pll ip core instance name>/ synth folder. The other folders contain lower level design files used for simulation and compilation.

Related Information

IP Core File Locations on page 67

For more information about IP core file structure

2.2.7. Reset Controller

There are two methods to reset the transceivers in Cyclone 10 GX devices:

• Use the Transceiver PHY Reset Controller.

• Create your own reset controller that follows the recommended reset sequence.

Related Information

Resetting Transceiver Channels on page 243

2.2.8. Create Reconfiguration Logic

Dynamic reconfiguration is the ability to dynamically modify the transceiver channels and PLL settings during device operation. To support dynamic reconfiguration, your design must include an Avalon master that can access the dynamic reconfiguration registers using the Avalon® memory-mapped interface.

The Avalon memory-mapped interface master enables PLL and channel reconfiguration. You can dynamically adjust the PMA parameters, such as differential output voltage swing (Vod), and pre-emphasis settings. This adjustment can be done by writing to the Avalon memory-mapped interface reconfiguration registers through the user generated Avalon memory-mapped interface master.

For detailed information on dynamic reconfiguration, refer to Reconfiguration Interface and Dynamic Reconfiguration chapter.

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2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller

Connect the PHY IP, PLL IP core, and the reset controller. Write the top level module to connect all the IP blocks.

All of the I/O ports for each IP, can be seen in the <phy instance name>.v file or <phy instance name>.vhd, and in the <phy_instance_name>_bb.v file.

For more information about description of the ports, refer to the ports tables in the PLLs, Using the Transceiver Native PHY IP Core, and Resetting Transceiver Channels chapters.

Related Information

• Resetting Transceiver Channels on page 243

• Using the Cyclone 10 GX Transceiver Native PHY IP Core on page 26

• PLLs and Clock Networks on page 198

2.2.10. Connect Datapath

Connect the transceiver PHY layer design to the Media Access Controller (MAC) IP core or to a data generator / analyzer or a frame generator / analyzer.

2.2.11. Make Analog Parameter Settings

Make analog parameter settings to I/O pins using the Assignment Editor or updating the Quartus Prime Settings File.

After verifying your design functionality, make pin assignments and PMA analog parameter settings for the transceiver pins.

1. Assign FPGA pins to all the transceiver and reference clock I/O pins.

2. Set the analog parameters to the transmitter, receiver, and reference clock pins using the Assignment Editor. All of the pin assignments and analog parameters set using the Pin Planner and the Assignment Editor are saved in the <top_level_project_name>.qsf file. You can also directly modify the Quartus Settings File (.qsf) to set PMA analog parameters.

2.2.12. Compile the Design

To compile the transceiver design, add the <phy_instancename>.qip files for all the IP blocks generated using the IP Catalog to the Quartus Prime project library. You can alternatively add the .qsys and .qip variants of the IP cores.

Note: If you add both the .qsys and the .qip file into the Quartus Prime project, the

software generates an error.

2.2.13. Verify Design Functionality

Simulate your design to verify the functionality of your design. For more details, refer to Simulating the Native Transceiver PHY IP Core section.

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Related Information

Intel Quartus Prime Pro Edition Handbook Volume 3: Verification

Information about design simulation and verification.

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2.3. Cyclone 10 GX Transceiver Protocols and PHY IP Support

Table 3. Cyclone 10 GX Transceiver Protocols and PHY IP Support

Protocol Transceiver PHY IP

PCIe Gen2 x1, x2, x4 Native PHY IP (PIPE)

PCIe Gen1 x1, x2, x4 Native PHY IP (PIPE)

1000BASE-X Gigabit

Ethernet

1000BASE-X Gigabit

Ethernet with 1588

10GBASE-R Native PHY IP core Enhanced 10GBASE-R 10GBASE-R Low

10GBASE-R 1588 Native PHY IP core Enhanced 10GBASE-R 1588 10GBASE-R

40GBASE-R Native PHY IP core Enhanced Basic (Enhanced PCS) Low Latency Enhanced

Interlaken (CEI-6G-SR

and CEI-11G-SR)

OTU-1 (2.7G) Native PHY IP core Standard Basic/Custom

(6)

Core

core/Hard IP for PCI

Native PHY IP core Standard GbE GIGE - 1.25 Gbps

Native PHY IP core Standard GbE 1588 GIGE - 1.25 Gbps

Native PHY IP core Enhanced Interlaken Interlaken

Express

(1)

PCS Support Transceiver

Configuration Rule

Standard Gen2 PIPE PCIe PIPE Gen2 x1

Standard Gen1 PIPE User created

(Standard PCS)

Protocol Preset

1588

Latency

PCS

10x12.5Gbps

Interlaken

6x10.3Gbps

Interlaken

1x6.25Gbps

User created

continued...

(2)

(3)

(4)

(5)

(1)

Hard IP for PCI Express is also available as a separate IP core.

(2)

For x2 and x4 modes, select PCIe PIPE Gen2 x8. Then change the number of data channels from 8 to 4.

(3)

For PCIe Gen1 x1 mode, select PCIe PIPE Gen2 x1 mode. Then change the transceiver configuration rule from Gen 2 PIPE to Gen 1 PIPE.

For PCIe Gen1 x2 and x4 mode, select PCIe PIPE Gen2 x8. Then change the transceiver configuration rule from Gen2 PIPE to Gen1 PIPE and number of data channels from 8 to 2 or

(4)

Select the 10GBASE-R preset. Then change the transceiver configuration rule from 10GBASER to 10GBASE-R 1588.

(5)

To implement 40GBASE-R using the Low Latency Enhanced PCS preset, change the number of data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.

(6)

Link training, auto speed negotiation and sequencer functions are not included in the Native PHY IP. The user would have to create soft logic to implement these functions when using Native PHY IP.

A Transmit PCS soft bonding logic required for multi-lane bonding configuration is provided in the design example.

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Protocol Transceiver PHY IP

SONET/SDH STS-192/ STM-64 (10G) via SFP

+/SFF-8431/CEI-11G

SONET/SDH STS-192/ STM-64 (10G) via OIF

SFI-5.1s/SxI-5/

SFI-4.2

SONET STS-96 (5G)

via OIF SFI-5.1s

SONET/SDH STS-48/

STM-16 (2.5G) via

SFP/TFI-5.1

SONET/SDH STS-12/

STM-4 (0.622G) via

SFP/TFI-5.1

SD-SDI/HD-

SDI/3G/6G/12G-SDI

Vx1 Native PHY IP core Standard Basic/Custom

DisplayPort Native PHY IP core Standard Basic/Custom

1.25G/ 2.5G

10G GPON/EPON

2.5G/1.25G GPON/ EPON

8G/4G/2G/1G Fibre

Channel

SDR/DDR Infiniband

x1, x4, x12

SRIO 2.2/1.3 Native PHY IP core Standard Basic/Custom with

CPRI 4.1/OBSAI RP3

v4.1

SAS 3.0 Native PHY IP core Enhanced Basic (Enhanced PCS) User created

Core

Native PHY IP core Enhanced Basic (Enhanced PCS) User created

Native PHY IP core Enhanced Basic/Custom

Native PHY IP core Standard Basic/Custom

Native PHY IP core

Native PHY IP core Standard Basic/Custom

Native PHY IP core Enhanced Basic (Enhanced PCS) User created

Native PHY IP core Standard Basic/Custom

Native PHY IP core Standard CPRI (Auto)/CPRI

(7)

PCS Support Transceiver

Configuration Rule

(Standard PCS)

Standard Basic/Custom

(Standard PCS)

Rate Match(Standard

PCS)

(Manual)

HD/3G SDI NTSC/PAL

SDI multi-rate (up to

DisplayPort Duplex 4

SYMBOLS PER CLOCK

Protocol Preset

SONET/SDH OC-96

SONET/SDH OC-48

SONET/SDH OC-12

12G) RX/TX

SDI triple-rate RX

User created

DisplayPort RX 4

DisplayPort TX 4

User created

Serial Rapid IO 1.25

Gbps

User created

(8)

continued...

(7)

The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver. If transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter. If receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.

(8)

Select CPRI 9.8 Gbps Auto/Manual Mode (Intel Arria® 10 only). Then change the datarate from 9830.4 Mbps to 6144 Mbps.

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Protocol Transceiver PHY IP

SATA 3.0/2.0/1.0 and

SAS 2.0/1.1/1.0

HiGig/HiGig+/HiGig2/

HiGig2+

JESD204A / JESD204B Native PHY IP core Standard and

Custom and other

protocols

Core

Native PHY IP core Standard Basic/Custom

Native PHY IP core Standard and

PCS Support Transceiver

Enhanced

PCS Direct

Configuration Rule

(Standard PCS)

Basic/Custom

(Standard PCS) Basic

(Enhanced PCS)

Basis/Custom

(Standard PCS)

Basic (Enhanced PCS)

Basic/Custom with

Rate Match (Standard

PCS)

PCS Direct

Protocol Preset

SAS Gen2/Gen1.1/

SATA Gen3/Gen2/

User created

2.4. Using the Cyclone 10 GX Transceiver Native PHY IP Core

This section describes the use of the Intel-provided Cyclone 10 GX Transceiver Native PHY IP core. This Native PHY IP core provides direct access to Cyclone 10 GX transceiver PHY features.

Use the Native PHY IP core to configure the transceiver PHY for your protocol

implementation. To instantiate the IP, click Tools ➤ IP Catalog to select your IP core

variation. Use the Parameter Editor to specify the IP parameters and configure the PHY IP for your protocol implementation. To quickly configure the PHY IP, select a preset that matches your protocol configuration as a starting point. Presets are PHY IP configuration settings for various protocols that are stored in the IP Parameter Editor. Presets are explained in detail in the Presets section below.

Gen1

You can also configure the PHY IP by selecting an appropriate Transceiver Configuration Rule. The transceiver configuration rules check the valid combinations of the PCS and PMA blocks in the transceiver PHY layer, and report errors or warnings for any invalid settings.

Use the Native PHY IP core to instantiate the following PCS options:

• Standard PCS

• Enhanced PCS

• PCS Direct

Based on the Transceiver Configuration Rule that you select, the PHY IP core selects the appropriate PCS. The PHY IP core allows you to select all the PCS blocks if you intend to dynamically reconfigure from one PCS to another. Refer to General and Datapath Parameters section for more details on how to enable PCS blocks for dynamic reconfiguration.

After you configure the PHY IP core in the Parameter Editor, click Generate HDL to generate the IP instance. The top level file generated with the IP instance includes all the available ports for your configuration. Use these ports to connect the PHY IP core to the PLL IP core, the reset controller IP core, and to other IP cores in your design.

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Reconfiguration

Registers

Enhanced PCS

Transmit and Receive Clocks

Standard PCS

Transmit

PMA

Receive

PMA

Reset Signals

Transmit Parallel Data

Reconfiguration Interface

Transmit Serial Data

Receive Serial Data

Receive Parallel Data

PCS-Direct

Nios II

Calibration

Calibration Signals

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Figure 11. Native PHY IP Core Ports and Functional Blocks

Figure 12. Native PHY IP Core Parameter Editor

Note: Although the Quartus Prime software provides legality checks, refer to the High-Speed

Serial Transceiver-Fabric Interface Performance for Intel Cyclone 10 GX Devices

section of theIntel Cyclone 10 GX Device Datasheet for the supported FPGA fabric to PCS interface widths and frequency.

Related Information

• Configure the PHY IP Core on page 19

• Interlaken on page 70

• Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 on page 87

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• 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants on page 98

• PCI Express (PIPE) on page 122

• CPRI on page 149

• Using the "Basic (Enhanced PCS)" Configuration on page 158

• Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard

• PMA Parameters on page 31

• Presets on page 28

• General and Datapath Parameters on page 28

• PMA Ports on page 50

• Enhanced PCS Ports on page 53

• Standard PCS Ports on page 62

• How to Place Channels for PIPE Configurations on page 146

• Intel Cyclone 10 GX Device Datasheet

2.4.1. Presets

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PCS on page 166

You can select preset settings for the Native PHY IP core defined for each protocol. Use presets as a starting point to specify parameters for your specific protocol or application.

To apply a preset to the Native PHY IP core, double-click on the preset name. When you apply a preset, all relevant options and parameters are set in the current instance of the Native PHY IP core. For example, selecting the Interlaken preset enables all parameters and ports that the Interlaken protocol requires.

Selecting a preset does not prevent you from changing any parameter to meet the requirements of your design. Any changes that you make are validated by the design rules for the transceiver configuration rules you specified, not the selected preset.

Note: Selecting a preset clears any prior selections user has made so far.

2.4.2. General and Datapath Parameters

You can customize your instance of the Native PHY IP core by specifying parameter values. In the Parameter Editor, the parameters are organized in the following sections for each functional block and feature:

• General, Common PMA Options, and Datapath Options

• TX PMA

• RX PMA

• Standard PCS

• Enhanced PCS

• PCS Direct Datapath

• Dynamic Reconfiguration

• Analog PMA Settings (Optional)

• Generation Options

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Table 4. General, Common PMA Options, and Datapath Options

Parameter Value Description

Message level for rule violations

VCCR_GXB and VCCT_GXB supply voltage for the Transceiver

Transceiver Link Type sr, lr Selects the type of transceiver link. sr-Short Reach (Chip-to-chip

Transceiver configuration rules

PMA configuration rules

Transceiver mode TX/RX Duplex

Number of data channels

Data rate < valid Transceiver data

Enable datapath and interface reconfiguration

error warning

0_9V, 1_0V

User Selection Specifies the valid configuration rules for the transceiver.

Basic SATA/SAS GPON

TX Simplex RX Simplex

1 – <n> Specifies the number of transceiver channels to be implemented.

rate >

On/Off When you turn this option on, you can preconfigure and

Specifies the messaging level for parameter rule violations. Selecting error causes all rule violations to prevent IP generation. Selecting warning displays all rule violations as warnings in the message window and allows IP generation despite the violations.

Selects the VCCR_GXB and VCCT_GXB supply voltage for the Transceiver.

Note: This option is only used for GUI rule validation. Use

Quartus Prime Setting File (.qsf) assignments to set this parameter in your static design.

communication), lr-Long Reach (Backplane communication).

Note: This option is only used for GUI rule validation. Use

Quartus Prime Setting File (.qsf) assignments to set this parameter in your static design.

This parameter specifies the configuration rule against which the Parameter Editor checks your PMA and PCS parameter settings for specific protocols. Depending on the transceiver configuration rule selected, the Parameter Editor validates the parameters and options selected by you and generates error messages or warnings for all invalid settings.

To determine the transceiver configuration rule to be selected for your protocol, refer to Table 3 on page 24 Transceiver Configuration Rule Parameters table for more details about each transceiver configuration rule.

This parameter is used for rule checking and is not a preset. You need to set all parameters for your protocol implementation.

Specifies the configuration rule for PMA. Select Basic for all other protocol modes except for SATA and

GPON . SATA (Serial ATA) can be used only if the Transceiver

configuration rule is set to Basic/Custom (Standard PCS). GPON can be used only if the Transceiver configuration rule is

set to Basic (Enhanced PCS).

Specifies the operational mode of the transceiver.

• TX/RX Duplex : Specifies a single channel that supports both transmission and reception.

• TX Simplex : Specifies a single channel that supports only transmission.

• RX Simplex : Specifies a single channel that supports only reception.

The default is TX/RX Duplex.

The maximum number of channels available, ( <n> ), depends on the package you select.

The default value is 1.

Specifies the data rate in megabits per second (Mbps).

dynamically switch between the Standard PCS, Enhanced PCS, and PCS direct datapaths.

continued...

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Parameter Value Description

The default value is Off.

Enable simplified data interface

Provide separate interface for each channel

On/Off

By default, all 128-bits are ports for the tx_parallel_data and

rx_parallel_data buses are exposed. You must understand the

mapping of data and control signals within the interface. Refer to the Enhanced PCS TX and RX Control Ports section for details about mapping of data and control signals.

When you turn on this option, the Native PHY IP core presents a simplified data and control interface between the FPGA fabric and transceiver. Only the sub-set of the 128-bits that are active for a particular FPGA fabric width are ports.

The default value is Off.

On/Off When selected the Native PHY IP core presents separate data,

reset and clock interfaces for each channel rather than a wide bus.

(9)

Table 5. Transceiver Configuration Rule Parameters

Transceiver Configuration Setting Description

Basic/Custom (Standard PCS) Enforces a standard set of rules within the Standard PCS. Select these rules to

Basic/Custom w /Rate Match (Standard PCS)

CPRI (Auto) Enforces rules required by the CPRI protocol. The receiver word aligner mode is

CPRI (Manual) Enforces rules required by the CPRI protocol. The receiver word aligner mode is

GbE Enforces rules that the 1 Gbps Ethernet (1 GbE) protocol requires.

GbE 1588 Enforces rules for the 1 GbE protocol with support for Precision time protocol

Gen1 PIPE Enforces rules for a Gen1 PCIe ® PIPE interface that you can connect to a soft

Gen2 PIPE Enforces rules for a Gen2 PCIe PIPE interface that you can connect to a soft MAC

Basic (Enhanced PCS) Enforces a standard set of rules within the Enhanced PCS. Select these rules to

Interlaken Enforces rules required by the Interlaken protocol.

10GBASE-R Enforces rules required by the 10GBASE-R protocol.

10GBASE-R 1588 Enforces rules required by the 10GBASE-R protocol with 1588 enabled.

PCS Direct Enforces rules required by the PCS Direct mode. In this configuration the data

implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules.

Enforces a standard set of rules including rules for the Rate Match FIFO within the Standard PCS. Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules.

set to Auto. In Auto mode, the word aligner is set to deterministic latency.

set to Manual. In Manual mode, logic in the FPGA fabric controls the word aligner.

(PTP) as defined in the IEEE 1588 Standard.

MAC and Data Link Layer.

and Data Link Layer.

implement protocols requiring blocks within the Enhanced PCS or protocols not covered by the other configuration rules.

flows through the PCS channel, but all the internal PCS blocks are bypassed. If required, the PCS functionality can be implemented in the FPGA fabric.

(9)

This option cannot be used, if you intend to dynamically reconfigure between PCS datapaths, or reconfigure the interface of the transceiver.

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2.4.3. PMA Parameters

You can specify values for the following types of PMA parameters:

TX PMA

• TX Bonding Options

• TX PLL Options

• TX PMA Optional Ports

RX PMA

• RX CDR Options

• Equalization

• RX PMA Optional Ports

Table 6. TX Bonding Options

Parameter Value Description

TX channel bonding mode

PCS TX channel bonding master

Actual PCS TX channel bonding master

Not bonded PMA only bonding PMA and PCS bonding

Auto, 0 to <number of channels> -1

0 to <number of channels> -1

Selects the bonding mode to be used for the channels specified. Bonded channels use a single TX PLL to generate a clock that drives multiple channels, reducing channel-to-channel skew. The following options are available:

Not bonded: In a non-bonded configuration, only the high speed serial clock is expected to be connected from the TX PLL to the Native PHY IP core. The low speed parallel clock is generated by the local clock generation block (CGB) present in the transceiver channel. For non-bonded configurations, because the channels are not related to each other and the feedback path is local to the PLL, the skew between channels cannot be calculated.

PMA only bonding: In PMA bonding, the high speed serial clock is routed from the transmitter PLL to the master CGB. The master CGB generates the high speed and low parallel clocks and the local CGB for each channel is bypassed. Refer to the Channel Bonding section for more details.

PMA and PCS bonding : In a PMA and PCS bonded configuration, the local CGB in each channel is bypassed and the parallel clocks generated by the master CGB are used to clock the network. The master CGB generates both the high and low speed clocks. The master channel generates the PCS control signals and distributes to other channels through a control plane block.

The default value is Not bonded. Refer to Channel Bonding section in PLLs and Clock Networks chapter for more details.

Specifies the master PCS channel for PCS bonded configurations. Each Native PHY IP core instance configured with bonding must specify a bonding master. If you select Auto, the Native PHY IP core automatically selects a recommended channel.

The default value is Auto. Refer to the PLLs and Clock Networks chapter for more information about the TX channel bonding master.

This parameter is automatically populated based on your selection for the PCS TX channel bonding master parameter. Indicates the selected master PCS channel for PCS bonded configurations.

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Table 7. TX PLL Options

Parameter Value Description

TX local clock division factor

Number of TX PLL clock inputs per channel

Initial TX PLL clock input selection

1, 2, 4, 8 Specifies the value of the divider available in the transceiver

1, 2, 3 , 4 Specifies the number of TX PLL clock inputs per channel. Use this

0 to <number of TX PLL clock inputs> -1

Table 8. TX PMA Optional Ports

Parameter Value Description

Enable tx_pma_analog_reset_ack port

Enable tx_pma_clkout port On/Off

Enable tx_pma_div_clkout port

tx_pma_div_clkout division factor

Enable tx_pma_iqtxrx_clkout port

Enable tx_pma_elecidle port

Enable rx_seriallpbken port On/Off

On/Off

Disabled, 1, 2, 33, 40, 66

On/Off

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channels to divide the TX PLL output clock to generate the correct frequencies for the parallel and serial clocks.

parameter when you plan to dynamically switch between TX PLL clock sources. Up to four input sources are possible.

Specifies the initially selected TX PLL clock input. This parameter is necessary when you plan to switch between multiple TX PLL clock inputs.

Enables the optional tx_pma_analog_reset_ack output port. This port should not be used for register mode data transfers.

Enables the optional tx_pma_clkout output clock. This is the low speed parallel clock from the TX PMA. The source of this clock is the serializer. It is driven by the PCS/PMA interface block.

Enables the optional tx_pma_div_clkout output clock. This clock is generated by the serializer. You can use this to drive core logic, to drive the FPGA - transceivers interface.

If you select a tx_pma_div_clkout division factor of 1 or 2, this clock output is derived from the PMA parallel clock. If you select a tx_pma_div_clkout division factor of 33, 40, or 66, this clock is derived from the PMA high serial clock. This clock is commonly used when the interface to the TX FIFO runs at a different rate than the PMA parallel clock frequency, such as 66:40 applications.

Selects the division factor for the tx_pma_div_clkout output clock when enabled.

Enables the optional tx_pma_iqtxrx_clkout output clock. This clock can be used to cascade the TX PMA output clock to the input of a PLL.

Enables the tx_pma_elecidle port. When you assert this port, the transmitter is forced into an electrical idle condition. This port has no effect when the transceiver is configured for PCI Express.

Enables the optional rx_seriallpbken control input port. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This is an asynchronous input signal.

(11)

(10)

Table 9. RX CDR Options

Parameter Value Description

Number of CDR reference clocks

(10)

This clock should not be used to clock the FPGA - transceivers interface. This clock may be

1 - 5 Specifies the number of CDR reference clocks. Up to 5 sources are

possible. The default value is 1.

used as a reference clock to an external clock cleaner.

(11)

The default value is Disabled.

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Parameter Value Description

Use this feature when you want to dynamically re-configure CDR reference clock source.

Selected CDR reference clock

Selected CDR reference clock frequency

PPM detector threshold 100

0 to <number of CDR reference clocks> -1

< data rate dependent >

300 500 1000

Specifies the initial CDR reference clock. This parameter determines the available CDR references used.

The default value is 0.

Specifies the CDR reference clock frequency. This value depends on the data rate specified.

Specifies the PPM threshold for the CDR. If the PPM between the incoming serial data and the CDR reference clock, exceeds this threshold value, the CDR loses lock.

The default value is 1000.

Table 10. Equalization

Parameters Value Description

CTLE adaptation mode Manual Specifies the Continuous Time Linear Equalization (CTLE)

operation mode. For manual mode, set the CTLE options through the Assignment

Editor, or modify the Quartus Settings File (.qsf ), or write to the reconfiguration registers using the Avalon Memory-Mapped (Avalon-MM) interface.

Refer to the Continuous Time Linear Equalization (CTLE) section for more details about CTLE architecture. Refer to the How to Enable CTLE section for more details on supported adaptation modes.

Table 11. RX PMA Optional Ports

Parameters Value Description

Enable rx_analog_reset_ack port

Enable rx_pma_clkout port

Enable rx_pma_div_clkout port

rx_pma_div_clkout division factor

Enable rx_pma_iqtxrx_clkout port

(12)

This clock should not be used to clock the FPGA - transceiver interface. This clock may be

On/Off

Disabled, 1, 2, 33, 40, 66

On/Off

Enables the optional rx_analog_reset_ack output. This port should not be used for register mode data transfers.

Enables the optional rx_pma_clkout output clock. This port is the recovered parallel clock from the RX clock data recovery

(12)

(CDR).

Enables the optional rx_pma_div_clkout output clock. The deserializer generates this clock. Use this to drive core logic, to drive the RX PCS-to-FPGA fabric interface, or both.

If you select a rx_pma_div_clkout division factor of 1 or 2, this clock output is derived from the PMA parallel clock. If you select a rx_pma_div_clkout division factor of 33, 40, or 66, this clock is derived from the PMA serial clock. This clock is commonly used when the interface to the RX FIFO runs at a different rate than the PMA parallel clock frequency, such as 66:40 applications.

Selects the division factor for the rx_pma_div_clkout output clock when enabled.

Enables the optional rx_pma_iqtxrx_clkout output clock. This clock can be used to cascade the RX PMA output clock to the input of a PLL.

(13)

used as a reference clock to an external clock cleaner.

(13)

The default value is Disabled.

continued...

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Parameters Value Description

Enable rx_pma_clkslip port

Enable rx_is_lockedtodata port

Enable rx_is_lockedtoref port

Enable rx_set_lockedtodata port and rx_set_lockedtoref ports

Enable rx_seriallpbken port

Enable PRBS (Pseudo Random Bit Sequence) verifier control and status port

On/Off

Enables the optional rx_pma_clkslip control input port. A rising edge on this signal causes the RX serializer to slip the serial data by one clock cycle, or 2 unit intervals (UI).

Enables the optional rx_is_lockedtodata status output port. This signal indicates that the RX CDR is currently in lock to data mode or is attempting to lock to the incoming data stream. This is an asynchronous output signal.

Enables the optional rx_is_lockedtoref status output port. This signal indicates that the RX CDR is currently locked to the CDR reference clock. This is an asynchronous output signal.

Enables the optional rx_set_lockedtodata and

rx_set_lockedtoref control input ports. You can use these

control ports to manually control the lock mode of the RX CDR. These are asynchronous input signals.

Enables the optional rx_seriallpbken control input port. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This is an asynchronous input signal.

Enables the optional rx_prbs_err, rx_prbs_clr, and

rx_prbs_done control ports. These ports control and collect

status from the internal PRBS verifier.

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2.4.4. Enhanced PCS Parameters

This section defines parameters available in the Native PHY IP core GUI to customize the individual blocks in the Enhanced PCS.

The following tables describe the available parameters. Based on the selection of the Transceiver Configuration Rule , if the specified settings violate the protocol standard, the Native PHY IP core Parameter Editor prints error or warning messages.

Note: For detailed descriptions about the optional ports that you can enable or disable, refer

to the Enhanced PCS Ports section.

Table 12. Enhanced PCS Parameters

Parameter Range Description

Enhanced PCS / PMA interface width

FPGA fabric /Enhanced PCS interface width

32, 40, 64 Specifies the interface width between the Enhanced PCS and the

PMA.

32, 40, 64, 66, 67 Specifies the interface width between the Enhanced PCS and the

FPGA fabric. The 66-bit FPGA fabric to PCS interface width uses 64-bits from the

TX and RX parallel data. The block synchronizer determines the block boundary of the 66-bit word, with lower 2 bits from the control bus.

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Parameter Range Description

The 67-bit FPGA fabric to PCS interface width uses the 64-bits from the TX and RX parallel data. The block synchronizer determines the block boundary of the 67-bit word with lower 3 bits from the control bus.

Enable Enhanced PCS low latency mode

Enable RX/TX FIFO double width mode

On/Off Enables the low latency path for the Enhanced PCS. When you turn

on this option, the individual functional blocks within the Enhanced PCS are bypassed to provide the lowest latency path from the PMA through the Enhanced PCS.

On/Off Enables the double width mode for the RX and TX FIFOs. You can

use double width mode to run the FPGA fabric at half the frequency of the PCS.

Table 13. Enhanced PCS TX FIFO Parameters

Parameter Range Description

TX FIFO Mode Phase-Compensation

TX FIFO partially full threshold

TX FIFO partially empty threshold

Enable tx_enh_fifo_full port

10, 11, 12, 13 Specifies the partially full threshold for the Enhanced PCS TX FIFO.

2, 3, 4, 5 Specifies the partially empty threshold for the Enhanced PCS TX

On / Off Enables the tx_enh_fifo_full port. This signal indicates when the

Specifies one of the following modes:

• Phase Compensation: The TX FIFO compensates for the clock

phase difference between the read clock rx_clkout and the write clocks tx_coreclkin or tx_clkout. You can tie

tx_enh_data_valid to 1'b1.

•

tx_control and tx_enh_data_valid are registered at the

FIFO output. Assert tx_enh_data_valid port 1'b1 at all times. The user must connect the write clock tx_coreclkin to the read clock tx_clkout.

• Interlaken: The TX FIFO acts as an elastic buffer. In this mode, there are additional signals to control the data flow into the FIFO. Therefore, the FIFO write clock frequency does not have to be the same as the read clock frequency. You can control writes to the FIFO with tx_enh_data_valid. By monitoring the FIFO flags, you can avoid the FIFO full and empty conditions. The Interlaken frame generator controls reads.

• Basic: The TX FIFO acts as an elastic buffer. This mode allows driving write and read side of FIFO with different clock frequencies. tx_coreclkin or rx_coreclkin must have a minimum frequency of the lane data rate divided by 66. The frequency range for tx_coreclkin or rx_coreclkin is (data rate/32) - (data rate/66). For best results, Intel recommends that tx_coreclkin or rx_coreclkin = (data rate/32). Monitor FIFO flag to control write and read operations. For additional details refer to Enhanced PCS FIFO Operation on page 164 section

• Fast Register: The TX FIFO allows a higher maximum frequency (f expense of higher latency.

Enter the value at which you want the TX FIFO to flag a partially full status.

FIFO. Enter the value at which you want the TX FIFO to flag a partially empty status.

TX FIFO is full. This signal is synchronous to tx_coreclkin.

) between the FPGA fabric and the TX PCS at the

MAX

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Parameter Range Description

Enable tx_enh_fifo_pfull port

Enable tx_enh_fifo_empty port

Enable tx_enh_fifo_pempty port

On / Off Enables the tx_enh_fifo_pfull port. This signal indicates when

the TX FIFO reaches the specified partially full threshold. This signal is synchronous to tx_coreclkin.

On / Off Enables the tx_enh_fifo_empty port. This signal indicates when

the TX FIFO is empty. This signal is synchronous to

tx_coreclkin.

On / Off Enables the tx_enh_fifo_pempty port. This signal indicates when

the TX FIFO reaches the specified partially empty threshold. This signal is synchronous to tx_coreclkin.

Table 14. Enhanced PCS RX FIFO Parameters

Parameter Range Description

RX FIFO Mode Phase-Compensation

10GBASE-R Basic

RX FIFO partially full threshold

RX FIFO partially empty threshold

Enable RX FIFO alignment word deletion (Interlaken)

Enable RX FIFO control word deletion (Interlaken)

18-29 Specifies the partially full threshold for the Enhanced PCS RX

2-10 Specifies the partially empty threshold for the Enhanced PCS RX

On / Off When you turn on this option, all alignment words (sync words),

On / Off When you turn on this option, Interlaken control word removal is

Specifies one of the following modes for Enhanced PCS RX FIFO:

• Phase Compensation: This mode compensates for the clock

phase difference between the read clocks rx_coreclkin or

tx_clkout and the write clock rx_clkout.

•

rx_parallel_data, rx_control, and rx_enh_data_valid are registered at the FIFO output. The

FIFO's read clock rx_coreclkin and write clock rx_clkout are tied together.

• Interlaken: Select this mode for the Interlaken protocol. To implement the deskew process, you must implement an FSM that controls the FIFO operation based on FIFO flags. In this mode the FIFO acts as an elastic buffer.

• 10GBASE-R: In this mode, data passes through the FIFO after block lock is achieved. OS (Ordered Sets) are deleted and Idles are inserted to compensate for the clock difference between the RX PMA clock and the fabric clock of +/- 100 ppm for a maximum packet length of 64000 bytes.

• Basic: In this mode, the RX FIFO acts as an elastic buffer. This mode allows driving write and read side of FIFO with different clock frequencies. tx_coreclkin or rx_coreclkin must have a minimum frequency of the lane data rate divided by

66. The frequency range for tx_coreclkin or

rx_coreclkin is (data rate/32) - (data rate/66). The

gearbox data valid flag controls the FIFO read enable. You can monitor the rx_enh_fifo_pfull and rx_enh_fifo_empty flags to determine whether or not to read from the FIFO. For additional details refer to Enhanced PCS FIFO Operation on page 164.

Note:

FIFO. The default value is 23.

FIFO. The default value is 2.

including the first sync word, are removed after frame synchronization is achieved. If you enable this option, you must also enable control word deletion.

enabled. When the Enhanced PCS RX FIFO is configured in Interlaken mode, enabling this option, removes all control words after frame synchronization is achieved. Enabling this option requires that you also enable alignment word deletion.

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The flags are for Interlaken and Basic modes only. They should be ignored in all other cases.

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Parameter Range Description

Enable rx_enh_data_valid port

On / Off Enables the rx_enh_data_valid port. This signal indicates when

RX data from RX FIFO is valid. This signal is synchronous to

rx_coreclkin.

Enable rx_enh_fifo_full port

Enable rx_enh_fifo_pfull port

Enable rx_enh_fifo_empty port

Enable rx_enh_fifo_pempty port

Enable rx_enh_fifo_del port (10GBASE-R)

Enable rx_enh_fifo_insert port (10GBASE-R)

Enable rx_enh_fifo_rd_en port

Enable rx_enh_fifo_align_val port (Interlaken)

Enable rx_enh_fifo_align_clr port (Interlaken)

On / Off Enables the rx_enh_fifo_full port. This signal indicates when

the RX FIFO is full. This is an asynchronous signal.

On / Off Enables the rx_enh_fifo_pfull port. This signal indicates when

the RX FIFO has reached the specified partially full threshold. This is an asynchronous signal.

On / Off Enables the rx_enh_fifo_empty port. This signal indicates when

the RX FIFO is empty. This signal is synchronous to

rx_coreclkin.

On / Off Enables the rx_enh_fifo_pempty port. This signal indicates

when the RX FIFO has reached the specified partially empty threshold. This signal is synchronous to rx_coreclkin.

On / Off Enables the optional rx_enh_fifo_del status output port. This

signal indicates when a word has been deleted from the rate match FIFO. This signal is only used for 10GBASE-R transceiver configuration rule. This is an asynchronous signal.

On / Off Enables the rx_enh_fifo_insert port. This signal indicates when

a word has been inserted into the rate match FIFO. This signal is only used for 10GBASE-R transceiver configuration rule. This signal is synchronous to rx_coreclkin.

On / Off Enables the rx_enh_fifo_rd_en input port. This signal is

enabled to read a word from the RX FIFO. This signal is synchronous to rx_coreclkin.

On / Off Enables the rx_enh_fifo_align_val status output port. Only

used for Interlaken transceiver configuration rule. This signal is synchronous to rx_clkout.

On / Off Enables the rx_enh_fifo_align_clr input port. Only used for

Interlaken. This signal is synchronous to rx_clkout.

Table 15. Interlaken Frame Generator Parameters

Parameter Range Description

Enable Interlaken frame generator

Frame generator metaframe length

Enable Frame Generator Burst Control

Send Feedback

On / Off Enables the frame generator block of the Enhanced PCS.

5-8192 Specifies the metaframe length of the frame generator. This

metaframe length includes 4 framing control words created by the frame generator.

On / Off Enables frame generator burst. This determines whether the

frame generator reads data from the TX FIFO based on the input of port tx_enh_frame_burst_en.

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Parameter Range Description

Enable tx_enh_frame port

Enable tx_enh_frame_diag_st atus port

Enable tx_enh_frame_burst_e n port

On / Off

Enables the tx_enh_frame status output port. When the Interlaken frame generator is enabled, this signal indicates the beginning of a new metaframe. This is an asynchronous signal.

Enables the tx_enh_frame_diag_status 2-bit input port. When the Interlaken frame generator is enabled, the value of this signal contains the status message from the framing layer diagnostic word. This signal is synchronous to tx_clkout.

Enables the tx_enh_frame_burst_en input port. When burst control is enabled for the Interlaken frame generator, this signal is asserted to control the frame generator data reads from the TX FIFO. This signal is synchronous to tx_clkout.

Table 16. Interlaken Frame Synchronizer Parameters

Parameter Range Description

Enable Interlaken frame synchronizer

Frame synchronizer metaframe length

Enable rx_enh_frame port

Enable rx_enh_frame_lock port

Enable rx_enh_frame_diag_st atus port

On / Off When you turn on this option, the Enhanced PCS frame

synchronizer is enabled.

5-8192 Specifies the metaframe length of the frame synchronizer.

On / Off Enables the rx_enh_frame status output port. When the

Interlaken frame synchronizer is enabled, this signal indicates the beginning of a new metaframe. This is an asynchronous signal.

On / Off Enables the rx_enh_frame_lock output port. When the

Interlaken frame synchronizer is enabled, this signal is asserted to indicate that the frame synchronizer has achieved metaframe delineation. This is an asynchronous output signal.

On / Off Enables therx_enh_frame_diag_status output port. When the

Interlaken frame synchronizer is enabled, this signal contains the value of the framing layer diagnostic word (bits [33:32]). This is a 2 bit per lane output signal. It is latched when a valid diagnostic word is received. This is an asynchronous signal.

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Table 17. Interlaken CRC32 Generator and Checker Parameters

Parameter Range Description

Enable Interlaken TX CRC-32 Generator

Enable Interlaken TX CRC-32 generator error insertion

Enable Interlaken RX CRC-32 checker

Enable rx_enh_crc32_err port

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On / Off When you turn on this option, the TX Enhanced PCS datapath

enables the CRC32 generator function. CRC32 can be used as a diagnostic tool. The CRC contains the entire metaframe including the diagnostic word.

On / Off When you turn on this option, the error insertion of the interlaken

CRC-32 generator is enabled. Error insertion is cycle-accurate. When this feature is enabled, the assertion of tx_control[8] or

tx_err_ins signal causes the CRC calculation during that word is

incorrectly inverted, and thus, the CRC created for that metaframe is incorrect.

On / Off Enables the CRC-32 checker function.

On / Off When you turn on this option, the Enhanced PCS enables the

rx_enh_crc32_err port. This signal is asserted to indicate that

the CRC checker has found an error in the current metaframe. This is an asynchronous signal.

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Table 18. 10GBASE-R BER Checker Parameters

Parameter Range Description

Enable rx_enh_highber port (10GBASE-R)

Enable rx_enh_highber_clr_c nt port (10GBASE-R)

Enable rx_enh_clr_errblk_cou nt port (10GBASE-R)

On / Off Enables the rx_enh_highber port. For 10GBASE-R transceiver

configuration rule, this signal is asserted to indicate a bit error rate higher than 10 -4 . Per the 10GBASE-R specification, this occurs when there are at least 16 errors within 125 μs. This is an asynchronous signal.

On / Off Enables the rx_enh_highber_clr_cnt input port. For the

10GBASE-R transceiver configuration rule, this signal is asserted to clear the internal counter. This counter indicates the number of times the BER state machine has entered the "BER_BAD_SH" state. This is an asynchronous signal.

On / Off Enables the rx_enh_clr_errblk_count input port. For the

10GBASE-R transceiver configuration rule, this signal is asserted to clear the internal counter. This counter indicates the number of the times the RX state machine has entered the RX_E state. This is an asynchronous signal.

Table 19. 64b/66b Encoder and Decoder Parameters

Parameter Range Description

Enable TX 64b/66b encoder (10GBASE-R)

Enable RX 64b/66b decoder (10GBASE-R)

Enable TX sync header error insertion

On / Off When you turn on this option, the Enhanced PCS enables the TX

64b/66b encoder.

On / Off When you turn on this option, the Enhanced PCS enables the RX

64b/66b decoder.

On / Off When you turn on this option, the Enhanced PCS supports cycle-

accurate error creation to assist in exercising error condition testing on the receiver. When error insertion is enabled and the error flag is set, the encoding sync header for the current word is generated incorrectly. If the correct sync header is 2'b01 (control type), 2'b00 is encoded. If the correct sync header is 2'b10 (data type), 2'b11 is encoded.

Table 20. Scrambler and Descrambler Parameters

Parameter Range Description

Enable TX scrambler (10GBASE-R/ Interlaken)

TX scrambler seed (10GBASE-R/ Interlaken)

Enable RX descrambler (10GBASE-R/ Interlaken)

Send Feedback

On / Off Enables the scrambler function. This option is available for the

User-specified 58-bit value

On / Off Enables the descrambler function. This option is available for Basic

Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols. You can enable the scrambler in Basic (Enhanced PCS) mode when the block synchronizer is enabled and with 66:32, 66:40, or 66:64 gear box ratios.

You must provide a non-zero seed for the Interlaken protocol. For a multi-lane Interlaken Transceiver Native PHY IP, the first lane scrambler has this seed. For other lanes' scrambler, this seed is increased by 1 per each lane. The initial seed for 10GBASE-R is 0x03FFFFFFFFFFFFFF. This parameter is required for the 10GBASE-R and Interlaken protocols.

(Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols. You can enable the descrambler in Basic (Enhanced PCS) mode with the block synchronizer enabled and with 66:32, 66:40, or 66:64 gear box ratios.

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Table 21. Interlaken Disparity Generator and Checker Parameters

Parameter Range Description

Enable Interlaken TX disparity generator

Enable Interlaken RX disparity checker

Enable Interlaken TX random disparity bit

On / Off When you turn on this option, the Enhanced PCS enables the

disparity generator. This option is available for the Interlaken protocol.

On / Off When you turn on this option, the Enhanced PCS enables the

disparity checker. This option is available for the Interlaken protocol.

On / Off Enables the Interlaken random disparity bit. When enabled, a

random number is used as disparity bit which saves one cycle of latency.

Table 22. Block Synchronizer Parameters

Parameter Range Description

Enable RX block synchronizer

Enable rx_enh_blk_lock port

On / Off When you turn on this option, the Enhanced PCS enables the RX

On / Off

block synchronizer. This options is available for the Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols.

Enables the rx_enh_blk_lock port. When you enable the block synchronizer, this signal is asserted to indicate that the block delineation has been achieved.

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Table 23. Gearbox Parameters

Parameter Range Description

Enable TX data bitslip On / Off When you turn on this option, the TX gearbox operates in bitslip

Enable TX data polarity inversion

Enable RX data bitslip On / Off When you turn on this option, the Enhanced PCS RX block

Enable RX data polarity inversion

Enable tx_enh_bitslip port

Enable rx_bitslip port On / Off Enables the rx_bitslip port. When RX bit slip is enabled, the

On / Off When you turn on this option, the polarity of TX data is inverted.

On / Off When you turn on this option, the polarity of the RX data is

On / Off Enables the tx_enh_bitslip port. When TX bit slip is enabled,

mode. The tx_enh_bitslip port controls number of bits which TX parallel data slips before going to the PMA.

This allows you to correct incorrect placement and routing on the PCB.

synchronizer operates in bitslip mode. When enabled, the rx_bitslip port is asserted on the rising edge to ensure that RX parallel data from the PMA slips by one bit before passing to the PCS.

inverted. This allows you to correct incorrect placement and routing on the PCB.

this signal controls the number of bits which TX parallel data slips before going to the PMA.

rx_bitslip signal is asserted on the rising edge to ensure that

RX parallel data from the PMA slips by one bit before passing to the PCS. This port is shared between Standard PCS and Enhanced PCS.

Related Information

• Enhanced PCS Ports on page 53

• Cyclone 10 GX Enhanced PCS Architecture on page 283

• Interlaken on page 70

• 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants on page 98

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• Using the "Basic (Enhanced PCS)" Configuration on page 158

2.4.5. Standard PCS Parameters

This section provides descriptions of the parameters that you can specify to customize the Standard PCS.

For specific information about configuring the Standard PCS for these protocols, refer to the sections of this user guide that describe support for these protocols.

Table 24. Standard PCS Parameters

Note: For detailed descriptions of the optional ports that you can enable or disable, refer to the

Parameter Range Description

Standard PCS/PMA interface width

FPGA fabric/Standard TX PCS interface width

FPGA fabric/Standard RX PCS interface width

Enable Standard PCS low latency mode

Standard PCS Ports section.

8, 10, 16, 20 Specifies the data interface width between the Standard PCS and

8, 10, 16, 20, 32, 40 Shows the FPGA fabric to TX PCS interface width. This value is

8, 10, 16, 20, 32, 40 Shows the FPGA fabric to RX PCS interface width. This value is

On / Off Enables the low latency path for the Standard PCS. Some of the

Table 25. Standard PCS FIFO Parameters

Parameter Range Description

TX FIFO mode low_latency

register_fifo

fast_register

RX FIFO mode low_latency

register_fifo

Enable tx_std_pcfifo_full port

On / Off

the transceiver PMA.

determined by the current configuration of individual blocks within the Standard TX PCS datapath.

determined by the current configuration of individual blocks within the Standard RX PCS datapath.

functional blocks within the Standard PCS are bypassed to provide the lowest latency. You cannot turn on this parameter while using the Basic/Custom w/Rate Match (Standard PCS) specified for Transceiver configuration rules.

Specifies the Standard PCS TX FIFO mode. The following modes are available:

• low_latency: This mode adds 2-3 cycles of latency to the TX datapath.

• register_fifo: In this mode the FIFO is replaced by registers to reduce the latency through the PCS. Use this mode for protocols that require deterministic latency, such as CPRI.

• fast_register: This mode allows a higher maximum frequency (f

) between the FPGA fabric and the TX PCS at the expense

MAX

of higher latency.

The following modes are available:

• low_latency: This mode adds 2-3 cycles of latency to the RX datapath.

• register_fifo: In this mode the FIFO is replaced by registers to reduce the latency through the PCS. Use this mode for protocols that require deterministic latency, such as CPRI or

1588.

Enables the tx_std_pcfifo_full port. This signal indicates when the standard TX phase compensation FIFO is full. This signal is synchronous with tx_coreclkin.

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Parameter Range Description

Enable tx_std_pcfifo_empty port

Enable rx_std_pcfifo_full port

Enable rx_std_pcfifo_empty port

On / Off

Enables the tx_std_pcfifo_empty port. This signal indicates when the standard TX phase compensation FIFO is empty. This signal is synchronous with tx_coreclkin.

Enables the rx_std_pcfifo_full port. This signal indicates when the standard RX phase compensation FIFO is full. This signal is synchronous with rx_coreclkin.

Enables the rx_std_pcfifo_empty port. This signal indicates when the standard RX phase compensation FIFO is empty. This signal is synchronous with rx_coreclkin.

Table 26. Byte Serializer and Deserializer Parameters

Parameter Range Description

Enable TX byte serializer

Enable RX byte deserializer

Disabled Serialize x2 Serialize x4

Disabled

Deserialize x2 Deserialize x4

Specifies the TX byte serializer mode for the Standard PCS. The transceiver architecture allows the Standard PCS to operate at double or quadruple the data width of the PMA serializer. The byte serializer allows the PCS to run at a lower internal clock frequency to accommodate a wider range of FPGA interface widths. Serialize x4 is only applicable for PCIe protocol implementation.

Specifies the mode for the RX byte deserializer in the Standard PCS. The transceiver architecture allows the Standard PCS to operate at double or quadruple the data width of the PMA deserializer. The byte deserializer allows the PCS to run at a lower internal clock frequency to accommodate a wider range of FPGA interface widths. Deserialize x4 is only applicable for PCIe protocol implementation.

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Table 27. 8B/10B Encoder and Decoder Parameters

Parameter Range Description

Enable TX 8B/10B encoder

Enable TX 8B/10B disparity control

Enable RX 8B/10B decoder

On / Off When you turn on this option, the Standard PCS enables the TX

8B/10B encoder.

On / Off When you turn on this option, the Standard PCS includes disparity

control for the 8B/10B encoder. You can force the disparity of the 8B/10B encoder using the tx_forcedisp control signal.

On / Off When you turn on this option, the Standard PCS includes the

8B/10B decoder.

Table 28. Rate Match FIFO Parameters

Parameter Range Description

RX rate match FIFO mode Disabled

Basic 10-bit PMA

width

Basic 20-bit PMA

width

GbE

PIPE

PIPE 0 ppm

RX rate match insert/ delete -ve pattern (hex)

User-specified 20 bit

pattern

Specifies the operation of the RX rate match FIFO in the Standard PCS.

Rate Match FIFO in Basic (Single Width) Mode on page 173

Rate Match FIFO Basic (Double Width) Mode on page 175

Rate Match FIFO for GbE on page 92

Transceiver Channel Datapath for PIPE on page 123

Specifies the -ve (negative) disparity value for the RX rate match FIFO as a hexadecimal string.

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Parameter Range Description

RX rate match insert/ delete +ve pattern (hex)

Enable rx_std_rmfifo_full port

Enable rx_std_rmfifo_empty port

User-specified 20 bit

pattern

On / Off

Specifies the +ve (positive) disparity value for the RX rate match FIFO as a hexadecimal string.

Enables the optional rx_std_rmfifo_full port.

Enables the rx_std_rmfifo_empty port.

Table 29. Word Aligner and Bitslip Parameters

Parameter Range Description

Enable TX bitslip On / Off When you turn on this option, the PCS includes the bitslip

Enable tx_std_bitslipboundarysel port

RX word aligner mode bitslip

RX word aligner pattern length 7, 8, 10, 16, 20,

RX word aligner pattern (hex) User-specified Specifies the word alignment pattern in hex.

Number of word alignment patterns to achieve sync

Number of invalid words to lose sync

Number of valid data words to decrement error count

Enable fast sync status reporting for deterministic Latency SM

Enable rx_std_wa_patternalign port

On / Off

manual (PLD

controlled)

synchronous state

machine

deterministic

latency

32, 40

0-255

0-63

0-255

On / Off

function. The outgoing TX data can be slipped by the number of bits specified by the

tx_std_bitslipboundarysel control signal.

Enables the tx_std_bitslipboundarysel control signal.

Specifies the RX word aligner mode for the Standard PCS. The word aligned width depends on the PCS and PMA width, and whether or not 8B/10B is enabled.

Refer to "Word Aligner" for more information.

Specifies the length of the pattern the word aligner uses for alignment.

Refer to "RX Word Aligner Pattern Length" table in "Word Aligner". It shows the possible values of "Rx Word Aligner Pattern Length" in all available word aligner modes.

Specifies the number of valid word alignment patterns that must be received before the word aligner achieves synchronization lock. The default is 3.

Specifies the number of invalid data codes or disparity errors that must be received before the word aligner loses synchronization. The default is 3.

Specifies the number of valid data codes that must be received to decrement the error counter. If the word aligner receives enough valid data codes to decrement the error count to 0, the word aligner returns to synchronization lock.

When enabled, the rx_syncstatus asserts high immediately after the deserializer has completed slipping the bits to achieve word alignment. When it is not selected,

rx_syncstatus asserts after the cycle slip operation is

complete and the word alignment pattern is detected by the PCS (i.e. rx_patterndetect is asserted). This parameter is only applicable when the selected protocol is CPRI (Auto).

Enables the rx_std_wa_patternalign port. When the word aligner is configured in manual mode and when this signal is enabled, the word aligner aligns to next incoming word alignment pattern.

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Parameter Range Description

Enable rx_std_wa_a1a2size port On / Off

Enable rx_std_bitslipboundarysel port

Enable rx_bitslip port On / Off

On / Off

Enables the optional rx_std_wa_a1a2size control input port.

Enables the optional rx_std_bitslipboundarysel status output port.

Enables the rx_bitslip port. This port is shared between the Standard PCS and Enhanced PCS.

Table 30. Bit Reversal and Polarity Inversion

Parameter Range Description

Enable TX bit reversal On / Off When you turn on this option, the 8B/10B Encoder reverses TX

Enable TX byte reversal On / Off When you turn on this option, the 8B/10B Encoder reverses the

Enable TX polarity inversion

Enable tx_polinv port On / Off

Enable RX bit reversal On / Off When you turn on this option, the word aligner reverses RX

Enable rx_std_bitrev_ena port

Enable RX byte reversal On / Off When you turn on this option, the word aligner reverses the byte

Enable rx_std_byterev_ena port

On / Off

On / Off When you turn on this option and assert the

parallel data before transmitting it to the PMA for serialization. The transmitted TX data bit order is reversed. The normal order is LSB to MSB. The reverse order is MSB to LSB. During the operation of the circuit, this setting can be changed through dynamic reconfiguration.

byte order before transmitting data. This function allows you to reverse the order of bytes that were erroneously swapped. The PCS can swap the ordering of either one of the 8- or 10-bit words, when the PCS/PMA interface width is 16 or 20 bits. This option is not valid under certain Transceiver configuration rules.

When you turn on this option, the tx_std_polinv port controls polarity inversion of TX parallel data to the PMA. When you turn on this parameter, you also need to turn on the Enable tx_polinv port.

When you turn on this option, the tx_polinv input control port is enabled. You can use this control port to swap the positive and negative signals of a serial differential link, if they were erroneously swapped during board layout.

parallel data. The received RX data bit order is reversed. The normal order is LSB to MSB. The reverse order is MSB to LSB. This setting can be changed through dynamic reconfiguration.

When you enable Enable RX bit reversal, you must also enable Enable rx_std_bitrev_ena port.

rx_std_bitrev_ena control port, the RX data order is

reversed. The normal order is LSB to MSB. The reverse order is MSB to LSB.

order, before storing the data in the RX FIFO. This function allows you to reverse the order of bytes that are erroneously swapped. The PCS can swap the ordering of either one of the 8- or 10-bit words, when the PCS / PMA interface width is 16 or 20 bits. This option is not valid under certain Transceiver configuration rules.

When you enable Enable RX byte reversal, you must also select the Enable rx_std_byterev_ena port.

rx_std_byterev_ena input control port, the order of the

individual 8- or 10-bit words received from the PMA is swapped.

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Parameter Range Description

Enable RX polarity inversion

Enable rx_polinv port On / Off

Enable rx_std_signaldetect port

On / Off

On / Off When you turn on this option, the optional

When you turn on this option, the rx_std_polinv port inverts the polarity of RX parallel data. When you turn on this parameter, you also need to enable Enable rx_polinv port.

When you turn on this option, the rx_polinv input is enabled. You can use this control port to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout.

rx_std_signaldetect output port is enabled. This signal is

required for the PCI Express protocol. If enabled, the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage that you specified. You can specify the signal detect threshold using a Quartus Prime Assignment Editor or by modifying the Quartus Settings File (.qsf)

Table 31. PCIe Ports

Parameter Range Description

Enable PCIe dynamic datarate switch ports

Enable PCIe pipe_hclk_in and pipe_hclk_out ports

Enable PCIe electrical idle control and status ports

Enable PCIe pipe_rx_polarity port

On / Off

When you turn on this option, the pipe_rate, pipe_sw, and

pipe_sw_done ports are enabled. You should connect these ports

to the PLL IP core instance in multi-lane PCIe Gen2 configurations. The pipe_sw and pipe_sw_done ports are only available for multi-lane bonded configurations.

When you turn on this option, the pipe_hclk_in, and

pipe_hclk_out ports are enabled. These ports must be

connected to the PLL IP core instance for the PCI Express configurations.

When you turn on this option, the pipe_rx_eidleinfersel and

pipe_rx_elecidle ports are enabled. These ports are used for

PCI Express configurations.

When you turn on this option, the pipe_rx_polarity input control port is enabled. You can use this option to control channel signal polarity for PCI Express configurations. When the Standard PCS is configured for PCIe, the assertion of this signal inverts the RX bit polarity. For other Transceiver configuration rules the optional rx_polinv port inverts the polarity of the RX bit stream.

2.4.6. PCS Direct

Table 32. PCS Direct Datapath Parameters

Parameter Range Description

PCS Direct interface width 8, 10, 16, 20, 32, 40, 64 Specifies the data interface width between the PLD and

the transceiver PMA.

2.4.7. Dynamic Reconfiguration Parameters

Dynamic reconfiguration allows you to change the behavior of the transceiver channels and PLLs without powering down the device. Each transceiver channel and PLL includes an Avalon-MM slave interface for reconfiguration. This interface provides direct access to the programmable address space of each channel and PLL. Because each channel and PLL includes a dedicated Avalon-MM slave interface, you can

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dynamically modify channels either concurrently or sequentially. If your system does not require concurrent reconfiguration, you can parameterize the Transceiver Native PHY IP to share a single reconfiguration interface.

You can use dynamic reconfiguration to change many functions and features of the transceiver channels and PLLs. For example, you can change the reference clock input to the TX PLL. You can also change between the Standard and Enhanced datapaths.

To enable Intel Cyclone 10 GX transceiver toolkit capability in the Native PHY IP core, you must enable the following options:

• Enable dynamic reconfiguration

• Enable Native PHY Debug Master Endpoint

• Enable capability registers

• Enable control and status registers

• Enable PRBS (Pseudo Random Binary Sequence) soft accumulators

Table 33. Dynamic Reconfiguration

Parameter Value Description

Enable dynamic reconfiguration

Share reconfiguration interface

Enable Native PHY Debug Master Endpoint

Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE

On/Off When you turn on this option, the dynamic reconfiguration

On/Off When you turn on this option, the Transceiver Native PHY IP

On/Off

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interface is enabled.

presents a single Avalon-MM slave interface for dynamic reconfiguration for all channels. In this configuration, the upper [n-1:10] address bits of the reconfiguration address bus specify the channel. The channel numbers are binary encoded. Address bits [9:0] provide the register offset address within the reconfiguration space for a channel.

includes an embedded Native PHY Debug Master Endpoint (NPDME) that connects internally to the Avalon-MM slave interface for dynamic reconfiguration. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. This option requires you to enable the Share reconfiguration interface option for configurations using more than one channel.

When enabled, the reconfig_waitrequest does not indicate the status of AVMM arbitration with PreSICE. The AVMM arbitration status is reflected in a soft status register bit. This feature requires that the "Enable control and status registers" feature under "Optional Reconfiguration Logic" be enabled.

Table 34. Optional Reconfiguration Logic

Parameter Value Description

Enable capability registers

Set user-defined IP identifier

Enable control and status registers

Enable PRBS (Pseudo Random Binary Sequence) soft accumulators

Intel® Cyclone® 10 GX Transceiver PHY User Guide

On/Off Enables capability registers that provide high level information about the

configuration of the transceiver channel.

User-defined Sets a user-defined numeric identifier that can be read from the

user_identifier offset when the capability registers are enabled.

On/Off Enables soft registers to read status signals and write control signals on the

PHY interface through the embedded debug.

On/Off Enables soft logic for performing PRBS bit and error accumulation when the

hard PRBS generator and checker are used.

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Table 35. Configuration Files

Parameter Value Description

Configuration file prefix

Generate SystemVerilog package file

Generate C header file On/Off When you turn on this option, the Transceiver Native PHY IP

Generate MIF (Memory Initialization File)

Include PMA analog settings in configuration files

<prefix> Here, the file prefix to use for generated configuration files is

specified. Each variant of the Transceiver Native PHY IP should use a unique prefix for configuration files.

On/Off When you turn on this option, the Transceiver Native PHY IP

generates a SystemVerilog package file, reconfig_parameters.sv. This file contains parameters defined with the attribute values required for reconfiguration.

generates a C header file, reconfig_parameters.h. This file contains macros defined with the attribute values required for reconfiguration.

On/Off When you turn on this option, the Transceiver Native PHY IP

generates a MIF, reconfig_parameters.mif. This file contains the attribute values required for reconfiguration in a data format.

On/Off When enabled, the IP allows you to configure the PMA analog

settings that are selected in the Analog PMA settings (Optional) tab. These settings are included in your generated configuration files.

Note: You must still specify the analog settings for your current

configuration using Quartus Prime Setting File (.qsf) assignments in Quartus. This option does not remove the requirement to specify Quartus Prime Setting File (.qsf) assignments for your analog settings. Refer to the Analog

Parameter Settings chapter in the Cyclone 10 GX Transceiver PHY User Guide for details on using the QSF

assignments.

Table 36. Configuration Profiles

Parameter Value Description

Enable multiple reconfiguratio n profiles

Enable embedded reconfiguratio n streamer

Generate reduced reconfiguratio n files

Number of reconfiguratio n profiles

Selected reconfiguratio n profile

(14)

For more information on timing closure, refer to the Reconfiguration Interface and Dynamic

On/Off When enabled, you can use the GUI to store multiple configurations. This information is

used by Quartus to include the necessary timing arcs for all configurations during timing driven compilation. The Native PHY generates reconfiguration files for all of the stored profiles. The Native PHY also checks your multiple reconfiguration profiles for consistency to ensure you can reconfigure between them. Among other things this checks that you have exposed the same ports for each configuration.

On/Off Enables the embedded reconfiguration streamer, which automates the dynamic

reconfiguration process between multiple predefined configuration profiles. This is optional and increases logic utilization. The PHY includes all of the logic and data necessary to dynamically reconfigure between pre-configured profiles.

On/Off When enabled, The Native PHY generates reconfiguration report files containing only the

attributes or RAM data that are different between the multiple configured profiles. The reconfiguration time decreases with the use of reduced .mif files.

1-8 Specifies the number of reconfiguration profiles to support when multiple reconfiguration

profiles are enabled.

0-7 Selects which reconfiguration profile to store/load/clear/refresh, when clicking the

relevant button for the selected profile.

Reconfiguration chapter.

(14)

continued...

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Parameter Value Description

Store configuration to selected profile

Load configuration from selected profile

Clear selected profile

Clear all profiles

Refresh selected profile

- Clicking this button saves or stores the current Native PHY parameter settings to the profile specified by the Selected reconfiguration profile parameter.

- Clicking this button loads the current Native PHY with parameter settings from the stored profile specified by the Selected reconfiguration profile parameter.

- Clicking this button clears or erases the stored Native PHY parameter settings for the profile specified by the Selected reconfiguration profile parameter. An empty profile defaults to the current parameter settings of the Native PHY.

- Clicking this button clears the Native PHY parameter settings for all the profiles.

- Clicking this button is equivalent to clicking the Load configuration from selected profile and Store configuration to selected profile buttons in sequence. This operation loads the Native PHY parameter settings from stored profile specified by the Selected reconfiguration profile parameter and subsequently stores or saves the parameters back to the profile.

Table 37. Analog PMA Settings (Optional) for Dynamic Reconfiguration

Parameter Value Description

TX Analog PMA Settings

Analog Mode (Load Intelrecommended Default settings)

Override Intel-recommended Analog Mode Default settings

Output Swing Level (VOD) 0-31 Selects the transmitter programmable output

Pre-Emphasis First Pre-Tap Polarity

Pre-Emphasis First Pre-Tap Magnitude

Pre-Emphasis Second PreTap Polarity

Pre-Emphasis Second PreTap Magnitude

Cei_11100_lr to xfp_9950 Selects the analog protocol mode to pre-select the

On/Off Enables the option to override the Intel-

Fir_pre_1t_neg Fir_pre_1t_pos

(15)

0-16

Fir_pre_2t_neg Fir_pre_2t_pos

(16)

0-7

TX pin swing settings (VOD, Pre-emphasis, and Slew Rate). After loading the pre-selected values in the GUI, if one or more of the individual TX pin swing settings need to be changed, then enable the option to override the Intel-recommended defaults to individually modify the settings.

recommended settings for the selected TX Analog Mode for one or more TX analog parameters.

differential voltage swing.

Selects the polarity of the first pre-tap for preemphasis.

Selects the magnitude of the first pre-tap for preemphasis

Selects the polarity of the second pre-tap for preemphasis.

Selects the magnitude of the second pre-tap for pre-emphasis.

continued...

(15)

For more information refer to Available Options table in the

XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T section of the Analog Parameter Settings chapter.

(16)

For more information refer to Available Options table in the

XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T section of the Analog Parameter Settings chapter.

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Parameter Value Description

Pre-Emphasis First Post-Tap Polarity

Pre-Emphasis First Post-Tap Magnitude

Pre-Emphasis Second PostTap Polarity

Pre-Emphasis Second PostTap Magnitude

Slew Rate Control

High-Speed Compensation Enable/Disable Enables the power-distribution network (PDN)

On-Chip termination

Fir_post_1t_neg Fir_post_1t_pos

(17)

0-25

Fir_post_2t_neg Fir_post_2t_pos

(18)

0-12

slew_r0 to slew_r5

r_r1

Selects the polarity of the first post-tap for preemphasis

Selects the magnitude of the first post-tap for preemphasis.

Selects the polarity of the second post-tap for preemphasis.

Selects the magnitude of the second post-tap for pre-emphasis

Selects the slew rate of the TX output signal. Valid values span from slowest to the fastest rate.

induced inter-symbol interference (ISI) compensation in the TX driver. When enabled, it reduces the PDN induced ISI jitter, but increases the power consumption.

Selects the on-chip TX differential termination.

r_r2

RX Analog PMA Settings

Override Intel-recommended Default settings

CTLE (Continuous Time Linear Equalizer) mode

DC gain control of high gain mode CTLE

AC Gain Control of High Gain Mode CTLE

Variable Gain Amplifier (VGA) Voltage Swing Select

On-Chip termination

On/Off Enables the option to override the Intel-

recommended settings for one or more RX analog parameters

non_s1_mode Selects the RX high gain mode non_s1_mode for

the Continuous Time Linear Equalizer (CTLE).

No_dc_gain to stg4_gain7

radp_ctle_acgain_4s_0 to radp_ctle_acgain_4s_28

radp_vga_sel_0 to radp_vga_sel_4

R_ext0, r_r1, r_r2

Selects the DC gain of the Continuous Time Linear Equalizer (CTLE) in high gain mode

Selects the AC gain of the Continuous Time Linear Equalizer (CTLE) in high gain mode when CTLE is in manual mode.

Selects the Variable Gain Amplifier (VGA) output voltage swing.

Selects the on-chip RX differential termination.

Table 38. Generation Options

Parameter Value Description

Generate parameter documentation file

(17)

For more information refer to Available Options table in the

On/Off When you turn on this option, generation produces a Comma-

Separated Value (.csv ) file with descriptions of the Transceiver Native PHY IP parameters.

XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP section of the Analog Parameter Settings chapter.

(18)

For more information refer to Available Options table in the

XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP section of the Analog Parameter Settings chapter.

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

2.4.8. PMA Ports

This section describes the PMA and calibration ports for the Cyclone 10 GX Transceiver Native PHY IP core.

The following tables, the variables represent these parameters:

• <n>—The number of lanes

• <d>—The serialization factor

• <s>—The symbol size

• <p>—The number of PLLs

Table 39. TX PMA Ports

Name Direction Clock Domain Description

tx_serial_data[<n>

-1:0]

tx_serial_clk0

tx_bonding_clocks[ <n><6>-1:0]

tx_serial_clk1 tx_serial_clk2 tx_serial_clk3 tx_serial_clk4

tx_analog_reset_ac k

tx_pma_clkout

tx_pma_div_clkout

Input N/A This is the serial data output of the TX PMA.

Input Clock This is the serial clock from the TX PLL. The frequency of this

Input Clock This is a 6-bit bus which carries the low speed parallel clock

Inputs Clocks These are the serial clocks from the TX PLL. The frequency of

Output Asynchronous

Output Clock This clock is the low speed parallel clock from the TX PMA. It

Output Clock

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clock depends on the data rate and clock division factor. This clock is for non bonded channels only. For bonded channels use the tx_bonding_clocks clock TX input.

per channel. These clocks are outputs from the master CGB. Use these clocks for bonded channels only.

Optional Ports

these clocks depends on the data rate and clock division factor. These additional ports are enabled when you specify more than one TX PLL.

Enables the optional tx_pma_analog_reset_ack output. This port should not be used for register mode data transfers

is available when you turn on Enable tx_pma_clkout port in the Transceiver Native PHY IP core Parameter Editor.

If you specify a tx_pma_div_clkout division factor of 1 or 2, this clock output is derived from the PMA parallel clock (low speed parallel clock). If you specify a

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tx_pma_div_clkout division factor of 33, 40, or 66, this

clock is derived from the PMA serial clock. This clock is commonly used when the interface to the TX FIFO runs at a different rate than the PMA parallel clock frequency, such as 66:40 applications.

continued...

(19)

This clock is not to be used to clock the FPGA - transceiver interface. This clock may be used as a reference clock to an external clock cleaner.

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Name Direction Clock Domain Description

tx_pma_iqtxrx_clko ut

tx_pma_elecidle[<n >-1:0]

rx_seriallpbken[<n >-1:0]

Output Clock This port is available if you turn on Enable tx_

pma_iqtxrx_clkout port in the Transceiver Native PHY IP

core Parameter Editor. This output clock can be used to cascade the TX PMA output clock to the input of a PLL.

Input Asynchronous When you assert this signal, the transmitter is forced to

electrical idle. This port has no effect when you configure the transceiver for the PCI Express protocol.

Input Asynchronous This port is available if you turn on Enable rx_seriallpbken

port in the Transceiver Native PHY IP core Parameter Editor. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This signal can be enabled in Duplex or Simplex mode. If enabled in Simplex mode, you must drive the signal on both the TX and RX instances from the same source. Otherwise the design fails compilation.

Table 40. RX PMA Ports

Name Direction Clock Domain Description

rx_serial_data[<n>

-1:0]

rx_cdr_refclk0

rx_cdr_refclk1– rx_cdr_refclk4

rx_analog_reset_ac k

rx_pma_clkout

rx_pma_div_clkout

rx_pma_iqtxrx_clko ut

rx_pma_clkslip

rx_is_lockedtodat a[<n>-1:0]

rx_is_lockedtoref[ <n>-1:0]

Input N/A Specifies serial data input to the RX PMA.

Input Clock Specifies reference clock input to the RX clock data recovery

Input Clock Specifies reference clock inputs to the RX clock data recovery

Output Asynchronous Enables the optional rx_pma_analog_reset_ack output. This

Output Clock This clock is the recovered parallel clock from the RX CDR

Output Clock The deserializer generates this clock. This is used to drive core

Output Clock This port is available if you turn on Enable rx_

Output Clock When asserted, indicates that the deserializer has either

Output

rx_clkout

(CDR) circuitry.

Optional Ports

(CDR) circuitry.

port should not be used for register mode data transfers.

circuitry.

logic, PCS-to-FPGA fabric interface, or both. If you specify a rx_pma_div_clkout division factor of 1 or 2, this clock output is derived from the PMA parallel clock (low speed parallel clock). If you specify a rx_pma_div_clkout division factor of 33, 40, or 66, this clock is derived from the PMA serial clock. This clock is commonly used when the interface to the RX FIFO runs at a different rate than the PMA parallel clock (low speed parallel clock) frequency, such as 66:40 applications.

pma_iqtxrx_clkout port in the Transceiver Native PHY IP core Parameter Editor. This output clock can be used to cascade the RX PMA output clock to the input of a PLL.

skipped one serial bit or paused the serial clock for one cycle to achieve word alignment. As a result, the period of the parallel clock could be extended by 1 unit interval (UI) during the clock slip operation.

When asserted, indicates that the CDR PLL is locked to the incoming data, rx_serial_data.

When asserted, indicates that the CDR PLL is locked to the input reference clock.

continued...

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Name Direction Clock Domain Description

rx_set_locktodata[ <n>-1:0]

rx_set_locktoref[< n>-1:0]

rx_seriallpbken[<n >-1:0]

rx_prbs_done[<n>-1 :0]

rx_prbs_err[<n>-1: 0]

rx_prbs_err_clr[<n >-1:0]

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Input Asynchronous This port provides manual control of the RX CDR circuitry.

Input Asynchronous This port is available if you turn on Enable rx_ seriallpbken

Output

Input

rx_coreclkin

or rx_clkout

rx_coreclkin

or rx_clkout

rx_coreclkin

or rx_clkout

port in the Transceiver Native PHY IP core Parameter Editor. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This signal is enabled in Duplex or Simplex mode. If enabled in Simplex mode, you must drive the signal on both the TX and RX instances from the same source. Otherwise the design fails compilation.

When asserted, indicates the verifier has aligned and captured consecutive PRBS patterns and the first pass through a polynomial is complete.

When asserted, indicates an error only after the

rx_prbs_done signal has been asserted. This signal gets

asserted for three parallel clock cycles for every error that occurs. Errors can only occur once per word.

When asserted, clears the PRBS pattern and deasserts the

rx_prbs_done signal.

Table 41. Calibration Status Ports

Name Direction Clock Domain Description

tx_cal_busy[<n>-1:0]

rx_cal_busy[<n>-1:0]

Output Asynchronous When asserted, indicates that the initial TX

Output Asynchronous When asserted, indicates that the initial RX

Table 42. Reset Ports

Name Direction Clock Domain

tx_analogreset[<n>-1: 0]

tx_digitalreset[<n>-1 :0]

rx_analogreset[<n>-1: 0]

rx_digitalreset[<n>-1 :0]

Input Asynchronous Resets the analog TX portion of the transceiver

Input Asynchronous Resets the digital TX portion of the transceiver

Input Asynchronous Resets the analog RX portion of the transceiver

Input Asynchronous Resets the digital RX portion of the transceiver

calibration is in progress. For both initial and manual recalibration, this signal is asserted during calibration and deasserts after calibration is completed. You must hold the channel in reset until calibration completes.

calibration is in progress. For both initial and manual recalibration, this signal is asserted during calibration and deasserts after calibration is completed.

(20)

PHY.

Description

(20)

Although the reset ports are not synchronous to any clock domain, Intel recommends that you synchronize the reset ports with the system clock.

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reconfig_reset reconfig_clk reconfig_avmm

TX Parallel Data, Control, Clocks

Enhanced PCS TX FIFO Interlaken Frame Generator

Reconfiguration

Registers

TX Enhanced PCS

RX Enhanced PCS

Nios Hard

Calibration IP

TX PMA

Serializer

RX PMA

DeserializerCDR

tx_cal_busy rx_cal_busy

Serial Data

Optional Ports

CDR Control

Serial Data

Clock

Generation

Block

tx_serial_clk0 (from TX PLL)

tx_analog_reset

RX Parallel Data, Control, Clocks Enhanced PCS RX FIFO Interlaken Frame Synchronizer 10GBASE-R BER Checker Bitslip

Bitslip

rx_analog_reset

Clocks

PRBS

Optional Ports

Clocks

Cyclone 10 Transceiver Native PHY

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2.4.9. Enhanced PCS Ports

Figure 13. Enhanced PCS Interfaces

The labeled inputs and outputs to the PMA and PCS modules represent buses, not individual signals.

In the following tables, the variables represent these parameters:

• <n>—The number of lanes

• <d>—The serialization factor

• <s>— The symbol size

• <p>—The number of PLLs

Table 43. Enhanced TX PCS: Parallel Data, Control, and Clocks

Name Direction Clock Domain Description

tx_parallel_data[ <n>128-1:0]

Send Feedback

Input Synchronous to

the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

TX parallel data inputs from the FPGA fabric to the TX PCS. If you select Enable simplified interface in the Transceiver Native PHY IP Parameter Editor, tx_parallel_data includes only the bits required for the configuration you specify.

You must ground the data pins that are not active. For single width configuration, the following bits are active:

• 32-bit FPGA fabric to PCS interface width: tx_parallel_data[31:0]. Ground [127:32].

• 40-bit FPGA fabric to PCS interface width: tx_parallel_data[39:0]. Ground [127:40].

• 64-bit FPGA fabric to PCS interface width: tx_parallel_data[63:0] Ground [127:64].

Intel® Cyclone® 10 GX Transceiver PHY User Guide

continued...

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

Name Direction Clock Domain Description

For double width configuration, the following bits are active:

• 40-bit FPGA fabric to PCS interface width: data[103:64], [39:0]. Ground [127:104], [63:40].

• 64-bit FPGA fabric to PCS interface width: data[127:64], [63:0].

Double-width mode is not supported for 32-bit, 50-bit, and 67bit FPGA fabric to PCS interface widths.

unused_tx_paralle l_data

tx_control[<n><3>

-1:0] or tx_control[<n><18

>-1:0]

unused_tx_contro l[<n> <15>-1:0]

tx_err_ins

tx_coreclkin

tx_clkout

Input

Input Synchronous to

Input

Input Clock The FPGA fabric clock. Drives the write side of the TX FIFO. For

Output Clock This is a parallel clock generated by the local CGB for non

tx_clkout

the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

tx_coreclkin

Port is enabled, when you enable Enable simplified data interface. Connect all of these bits to 0. When Enable simplified data interface is disabled, the unused bits are a

part of tx_parallel_data. Refer to tx_parallel_data to identify the bits you need to ground.

tx_control bits have different functionality depending on the

transceiver configuration rule selected. When Simplified data interface is enabled, the number of bits in this bus changes, as

the unused bits are shown as part of the unused_tx_control port.

Refer to Enhanced PCS TX and RX Control Ports on page 59 section for more details.

This port is enabled when you enable Enable simplified data

interface. Connect all of these bits to 0. When Enable simplified data interface is disabled, the unused bits are a

part of the tx_control. Refer to tx_control to identify the bits you need to ground.

For the Interlaken protocol, you can use this bit to insert the synchronous header and CRC32 errors if you have turned on Enable simplified data interface.

When asserted, the synchronous header for that cycle word is replaced with a corrupted one. A CRC32 error is also inserted if Enable Interlaken TX CRC-32 generator error insertion is turned on. The corrupted sync header is 2'b00 for a control word, and 2'b11 for a data word. For CRC32 error insertion, the word used for CRC calculation for that cycle is incorrectly inverted, causing an incorrect CRC32 in the Diagnostic Word of the Metaframe.

Note that a synchronous header error and a CRC32 error cannot be created for the Framing Control Words because the Frame Control Words are created in the frame generator embedded in TX PCS. Both the synchronous header error and the CRC32 errors are inserted if the CRC-32 error insertion feature is enabled in the Transceiver Native PHY IP GUI.

the Interlaken protocol, the frequency of this clock could be from datarate/67 to datarate/32. Using frequency lower than this range can cause the TX FIFO to underflow and result in data corruption.

bonded configurations, and master CGB for bonded configurations. This clocks the blocks of the TX Enhanced PCS. The frequency of this clock is equal to the datarate divided by PCS/PMA interface width.

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Table 44. Enhanced RX PCS: Parallel Data, Control, and Clocks

Name Direction Clock Domain Description

rx_parallel_data[<n >128-1:0]

unused_rx_parallel_ data

rx_control[<n> <20>-1:0]

unused_rx_control[< n>10-1:0]

rx_coreclkin

rx_clkout

Output Synchronous

to the clock driving the read side of the FIFO (rx_coreclk

in or rx_clkout)

Output

Output Synchronous

rx_clkout

to the clock driving the read side of the FIFO (rx_coreclk

in or rx_clkout)

Output Synchronous

to the clock driving the read side of the FIFO (rx_coreclk

in or rx_clkout)

Input Clock The FPGA fabric clock. Drives the read side of the RX FIFO. For

Output Clock The low speed parallel clock recovered by the transceiver RX

RX parallel data from the RX PCS to the FPGA fabric. If you select, Enable simplified data interface in the Transceiver Native PHY IP GUI, rx_parallel_data includes only the bits required for the configuration you specify. Otherwise, this interface is 128 bits wide.

When FPGA fabric to PCS interface width is 64 bits, the following bits are active for interfaces less than 128 bits. You can leave the unused bits floating or not connected.

• 32-bit FPGA fabric to PCS width: data[31:0].

• 40-bit FPGA fabric to PCS width: data[39:0].

• 64-bit FPGA fabric to PCS width: data[63:0]. When the FPGA fabric to PCS interface width is 128 bits, the

following bits are active:

• 40-bit FPGA fabric to PCS width: data[103:64], [39:0].

• 64-bit FPGA fabric to PCS width: data[127:0].

This signal specifies the unused data when you turn on Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of rx_parallel_data. You can leave the unused data outputs floating or not connected.

Indicates whether the rx_parallel_data bus is control or data.

Refer to the Enhanced PCS TX and RX Control Ports on page 59 section for more details.

These signals only exist when you turn on Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of rx_control. These outputs can be left floating.

Interlaken protocol, the frequency of this clock could be from datarate/67 to datarate/32.

PMA, that clocks the blocks in the RX Enhanced PCS. The frequency of this clock is equal to data rate divided by PCS/PMA interface width.

Table 45. Enhanced PCS TX FIFO

Name Direction Clock Domain Description

tx_enh_data_valid[<n>1:0]

Send Feedback

Input Synchronous to

the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

Assertion of this signal indicates that the TX data is valid. Connect this signal to 1'b1 for 10GBASE-R without 1588. For 10GBASE-R with 1588, you must control this signal based on the gearbox ratio. For Basic and Interlaken, you need to control this port based on TX FIFO flags so that the FIFO does not underflow or overflow.

continued...

Intel® Cyclone® 10 GX Transceiver PHY User Guide

Name Direction Clock Domain Description

tx_enh_fifo_full[<n>-1 :0]

tx_enh_fifo_pfull[<n>1:0]

tx_enh_fifo_empty[<n>1:0]

tx_enh_fifo_pempty[<n>

-1:0]

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

Output Synchronous to

the clock driving the write side of the FIFO (tx_coreclkin or tx_clkout)

Output Synchronous to

the clock driving the write side of the FIFO

tx_coreclkin

or tx_clkout

Output Synchronous to

the clock driving the write side of the FIFO

tx_coreclkin

or tx_clkout

Output Synchronous to

the clock driving the write side of the FIFO

tx_coreclkin

or tx_clkout

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Refer to Enhanced PCS FIFO Operation on page 164 for more details.

Assertion of this signal indicates the TX FIFO is full. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation on page 164 for more details.

This signal gets asserted when the TX FIFO reaches its partially full threshold. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation on page 164 for more details.

When asserted, indicates that the TX FIFO is empty. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation on page 164 for more details.

When asserted, indicates that the TX FIFO has reached its specified partially empty threshold. When you turn this option on, the Enhanced PCS enables the

tx_enh_fifo_pempty port, which is asynchronous. This

signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation on page 164 for more details.

Table 46. Enhanced PCS RX FIFO

Name Direction Clock Domain Description

rx_enh_data_valid[<n>

-1:0]

rx_enh_fifo_full[<n>1:0]

rx_enh_fifo_pfull[<n>

-1:0]

Output Synchronous to

the clock driving the read side of the FIFO

rx_coreclkin

or rx_clkout

the clock driving the read side of the FIFO

rx_coreclkin

or rx_clkout

the clock driving the read side of

When asserted, indicates that rx_parallel_data is valid. Discard invalid RX parallel data whenrx_enh_data_valid signal is low.

This option is available when you select the following parameters:

• Enhanced PCS Transceiver configuration rules specifies Interlaken

• Enhanced PCS Transceiver configuration rules specifies Basic, and RX FIFO mode is Phase

compensation

• Enhanced PCS Transceiver configuration rules specifies Basic, and RX FIFO mode is Register

Refer to Enhanced PCS FIFO Operation on page 164 for more details.

When asserted, indicates that the RX FIFO is full. This signal gets asserted for 2 to 3 clock cycles.Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation on page 164 for more details.

When asserted, indicates that the RX FIFO has reached its specified partially full threshold. This signal gets asserted for 2 to 3 clock cycles. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

continued...

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Name Direction Clock Domain Description

the FIFO

rx_coreclkin

or rx_clkout

rx_enh_fifo_empty[<n>

-1:0]

Output Synchronous to

the clock driving the read side of the FIFO

rx_coreclkin

or rx_clkout

rx_enh_fifo_pempty[<n >-1:0]

Output Synchronous to

the clock driving the read side of the FIFO

rx_coreclkin

or rx_clkout

rx_enh_fifo_del[<n>-1 :0]

Output Synchronous to

the clock driving the read side of the FIFO

rx_coreclkin

or rx_clkout

rx_enh_fifo_insert[<n >-1:0]

Output Synchronous to

the clock driving the read side of the FIFO

rx_coreclkin

or rx_clkout

rx_enh_fifo_rd_en[<n>

-1:0]

Output Synchronous to

the clock driving the read side of the FIFO

rx_coreclkin

or rx_clkout

rx_enh_fifo_align_va l[<n>-1:0]

Input Synchronous to

the clock driving the read side of the FIFO

rx_coreclkin

or rx_clkout

rx_enh_fifo_align_cl r[<n>-1:0]

Input Synchronous to

the clock driving the read side of the FIFO

rx_coreclkin

or rx_clkout

Refer to Enhanced PCS FIFO Operation on page 164 for more details.

When asserted, indicates that the RX FIFO is empty. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation on page 164 for more details.

When asserted, indicates that the RX FIFO has reached its specified partially empty threshold. Because the depth is always constant, you can ignore this signal for the phase compensation mode.

Refer to Enhanced PCS FIFO Operation on page 164 for more details.

When asserted, indicates that a word has been deleted from the RX FIFO. This signal gets asserted for 2 to 3 clock cycles. This signal is used for the 10GBASE-R protocol.

When asserted, indicates that a word has been inserted into the RX FIFO. This signal is used for the 10GBASE-R protocol.

For Interlaken only, when this signal is asserted, a word is read form the RX FIFO. You need to control this signal based on RX FIFO flags so that the FIFO does not underflow or overflow.

When asserted, indicates that the word alignment pattern has been found. This signal is only valid for the Interlaken protocol.

When asserted, the FIFO resets and begins searching for a new alignment pattern. This signal is only valid for the Interlaken protocol. Assert this signal for at least 4 cycles.

Table 47. Interlaken Frame Generator, Synchronizer, and CRC32

Name Direction Clock Domain Description

tx_enh_frame[<n>-1:0]

tx_enh_frame_diag_stat us[<n> 2-1:0]

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Output

Input

tx_clkout

Asserted for 2 or 3 parallel clock cycles to indicate the beginning of a new metaframe.

Drives the lane status message contained in the framing layer diagnostic word (bits[33:32]). This message is inserted into the next diagnostic word generated by the

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continued...

Name Direction Clock Domain Description

tx_enh_frame_burst_en[ <n>-1:0]

rx_enh_frame[<n>-1:0]

rx_enh_frame_lock[<n>1:0]

rx_enh_frame_diag_stat us[2 <n>-1:0]

rx_enh_crc32_err[<n>-1 :0]

Input

Output

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tx_clkout

rx_clkout

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frame generator block. This bus must be held constant for 5 clock cycles before and after the tx_enh_frame pulse. The following encodings are defined:

• Bit[1]: When 1, indicates the lane is operational. When 0, indicates the lane is not operational.

• Bit[0]: When 1, indicates the link is operational. When 0, indicates the link is not operational.

If Enable frame burst is enabled, this port controls frame generator data reads from the TX FIFO to the frame generator. It is latched once at the beginning of each Metaframe. If the value of tx_enh_frame_burst_en is 0, the frame generator does not read data from the TX FIFO for current Metaframe. Instead, the frame generator inserts SKIP words as the payload of Metaframe. When

tx_enh_frame_burst_en is 1, the frame generator reads

data from the TX FIFO for the current Metaframe. This port must be held constant for 5 clock cycles before and after the tx_enh_frame pulse.

When asserted, indicates the beginning of a new received Metaframe. This signal is pulse stretched.

When asserted, indicates the Frame Synchronizer state machine has achieved Metaframe delineation. This signal is pulse stretched.

Drives the lane status message contained in the framing layer diagnostic word (bits[33:32]). This signal is latched when a valid diagnostic word is received in the end of the Metaframe while the frame is locked. The following encodings are defined:

• Bit[1]: When 1, indicates the lane is operational. When 0, indicates the lane is not operational.

• Bit[0]: When 1, indicates the link is operational. When 0, indicates the link is not operational.

When asserted, indicates a CRC error in the current Metaframe. Asserted at the end of current Metaframe. This signal gets asserted for 2 or 3 cycles.

Table 48. 10GBASE-R BER Checker

Name Direction Clock Domain Description

rx_enh_highber[<n>-1:0

Output

rx_clkout

]

rx_enh_highber_clr_cn

Input

rx_clkout

t[<n>-1:0]

rx_enh_clr_errblk_coun

Input

rx_clkout

t[<n>-1:0] (10GBASE-R)

Table 49. Block Synchronizer

Name Direction Clock Domain Description

rx_enh_blk_lock<n>-1:0 ]

Intel® Cyclone® 10 GX Transceiver PHY User Guide

Output

rx_clkout

When asserted, indicates a bit error rate that is greater than 10 -4. For the 10GBASE-R protocol, this BER rate occurs when there are at least 16 errors within 125 µs. This signal gets asserted for 2 to 3 clock cycles.

When asserted, clears the internal counter that indicates the number of times the BER state machine has entered the BER_BAD_SH state.

When asserted the error block counter resets to 0. Assertion of this signal clears the internal counter that counts the number of times the RX state machine has entered the RX_E state.

When asserted, indicates that block synchronizer has achieved block delineation. This signal is used for 10GBASE-R and Interlaken.

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Table 50. Gearbox

Name Direction Clock Domain Description

rx_bitslip[<n>-1:0]

tx_enh_bitslip[<n>-1:0 ]

Input

rx_clkout The rx_parallel_data slips 1 bit for every positive edge

of the rx_bitslip input. Keep the minimum interval between rx_bitslip pulses to at least 20 cycles. The maximum shift is < pcswidth -1> bits, so that if the PCS is 64 bits wide, you can shift 0-63 bits.

rx_clkout

The value of this signal controls the number of bits to slip the tx_parallel_data before passing to the PMA.

2.4.9.1. Enhanced PCS TX and RX Control Ports

This section describes the tx_control and rx_control bit encodings for different protocol configurations.

When Enable simplified data interface is ON, all of the unused ports shown in the tables below, appear as a separate port. For example: It appears as

unused_tx_control/ unused_rx_control port.

Enhanced PCS TX Control Port Bit Encodings

Table 51. Bit Encodings for Interlaken

Name Bit Functionality Description

tx_control

[1:0] Synchronous header The value 2'b01 indicates a data word. The value

[2] Inversion control A logic low indicates that the built-in disparity

[7:3] Unused

[8] Insert synchronous header error or

CRC32

[17:9] Unused

Table 52. Bit Encodings for 10GBASE-R

Name Bit Functionality

tx_control

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[17:8] Unused

XGMII control signal for parallel_data[7:0]

XGMII control signal for parallel_data[15:8]

XGMII control signal for parallel_data[23:16]

XGMII control signal for parallel_data[31:24]

XGMII control signal for parallel_data[39:32]

XGMII control signal for parallel_data[47:40]

XGMII control signal for parallel_data[55:48]

XGMII control signal for parallel_data[63:56]

2'b10 indicates a control word.

generator block in the Enhanced PCS maintains the Interlaken running disparity.

You can use this bit to insert synchronous header error or CRC32 errors. The functionality is similar to tx_err_ins. Refer to tx_err_ins signal description for more details.

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Table 53. Bit Encodings for Basic Single Width Mode

For basic single width mode, the total word length is 66-bit with 64-bit data and 2-bit synchronous header.

Name Bit Functionality Description

tx_control

[1:0] Synchronous header The value 2'b01 indicates a data word. The value

[17:2] Unused

Table 54. Bit Encodings for Basic Double Width Mode

For basic double width mode, the total word length is 66-bit with 128-bit data and 4-bit synchronous header.

Name Bit Functionality Description

tx_control

[1:0] Synchronous header The value 2'b01 indicates a data word. The value

[8:2] Unused

[10:9] Synchronous header The value 2'b01 indicates a data word. The value

[17:11] Unused

Table 55. Bit Encodings for Basic Mode

In this case, the total word length is 67-bit with 64-bit data and 2-bit synchronous header.

Name Bit Functionality Description

tx_control

[1:0] Synchronous header The value 2'b01 indicates a data word. The value

[2] Inversion control A logic low indicates that built-in disparity

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2'b10 indicates a control word.

generator block in the Enhanced PCS maintains the running disparity.

Enhanced PCS RX Control Port Bit Encodings

Table 56. Bit Encodings for Interlaken

Name Bit Functionality Description

rx_control

[1:0] Synchronous header The value 2'b01 indicates a data

[2] Inversion control A logic low indicates that the built-

[3] Payload word location A logic high (1'b1) indicates the

[4] Synchronization word location A logic high (1'b1) indicates the

[5] Scrambler state word location A logic high (1'b1) indicates the

word. The value 2'b10 indicates a control word.

in disparity generator block in the Enhanced PCS maintains the Interlaken running disparity. In the current implementation, this bit is always tied logic low (1'b0).

payload word location in a metaframe.

synchronization word location in a metaframe.

scrambler word location in a metaframe.

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Name Bit Functionality Description

[6] SKIP word location A logic high (1'b1) indicates the

[7] Diagnostic word location A logic high (1'b1) indicates the

[8] Synchronization header error, metaframe error,

[9] Block lock and frame lock status A logic high (1'b1) indicates that

[19:10] Unused

or CRC32 error status

Table 57. Bit Encodings for 10GBASE-R

Name Bit Functionality

rx_control

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[19:8] Unused

XGMII control signal for parallel_data[7:0]

XGMII control signal for parallel_data[15:8]

XGMII control signal for parallel_data[23:16]

XGMII control signal for parallel_data[31:24]

XGMII control signal for parallel_data[39:32]

XGMII control signal for parallel_data[47:40]

XGMII control signal for parallel_data[55:48]

XGMII control signal for parallel_data[63:56]

SKIP word location in a metaframe.

diagnostic word location in a metaframe.

A logic high (1'b1) indicates synchronization header error, metaframe error, or CRC32 error status.

block lock and frame lock have been achieved.

Table 58. Bit Encodings for Basic Single Width Mode

For basic single width mode, the total word length is 66-bit with 64-bit data and 2-bit synchronous header.

Name

rx_control

Bit Functionality Description

[1:0] Synchronous header The value 2'b01 indicates a data word. The value

[7:2] Unused

[9:8] Synchronous header error status The value 2'b01 indicates a data word. The value

[19:10] Unused

Table 59. Bit Encodings for Basic Double Width Mode

For basic double width mode, total word length is 66-bit with 128-bit data, and 4-bit synchronous header.

Name

rx_control

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Bit Functionality Description

[1:0] Synchronous header The value 2'b01 indicates a data word. The

[7:2] Unused

2'b10 indicates a control word.

value 2'b10 indicates a control word.

continued...

Intel® Cyclone® 10 GX Transceiver PHY User Guide

Name Bit Functionality Description

reconfig_reset reconfig_clk reconfig_avmm

Parallel Data, Control, Clocks

TX FIFO 8B/10B Encoder/Decoder

Reconfiguration

Registers

TX Standard PCS

RX Standard PCS

Nios Hard

Calibration IP

TX PMA

Serializer

RX PMA

DeserializerCDR

tx_cal_busy rx_cal_busy

Serial Data

Optional Ports

CDR Control

PCIe

Serial Data

Clock

Generation

Block

tx_serial_clk0 (from TX PLL)

tx_analog_reset

Parallel Data, Control, Clocks RX FIFO Rate Match FIFO Word Aligner & Bitslip PCIe

rx_analog_reset

Clocks

PRBS

Bit & Byte Reversal

Polarity Inversion

PCIe

Optional Ports

Clocks

Cyclone 10 Transceiver Native PHY

[8] Synchronous header error status Active-high status signal that indicates a

[9] Block lock is achieved Active-high status signal indicating when block

[11:10] Synchronous header The value 2'b01 indicates a data word. The

[17:12] Unused

[18] Synchronous header error status Active-high status signal that indicates a

[19] Block lock is achieved Active-high status signal indicating when Block

Table 60. Bit Encodings for Basic Mode

In this case, the total word length is 67-bit with 64-bit data and 2-bit synchronous header.

Name Bit Functionality Description

rx_control

[1:0] Synchronous header The value 2'b01 indicates a data word. The value

[2] Inversion control A logic low indicates that built-in disparity

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synchronous header error.

lock is achieved.

value 2'b10 indicates a control word.

synchronous header error.

Lock is achieved.

2'b10 indicates a control word.

generator block in the Enhanced PCS maintains the running disparity.

2.4.10. Standard PCS Ports

Figure 14. Transceiver Channel using the Standard PCS Ports

Standard PCS ports appears, if either one of the transceiver configuration modes is selected that uses Standard PCS or if Data Path Reconfiguration is selected even if the transceiver configuration is not one of those that uses Standard PCS.

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In the following tables, the variables represent these parameters:

• <n>—The number of lanes

• <w>—The width of the interface

• <d>—The serialization factor

• <s>— The symbol size

• <p>—The number of PLLs

Table 61. TX Standard PCS: Data, Control, and Clocks

Name Direction Clock Domain Description

tx_parallel_data[<n> 128-1:0]

unused_tx_parallel_d ata

tx_coreclkin

tx_clkout

Input

Input Clock The FPGA fabric clock. This clock drives the write port of the

Output Clock This is the parallel clock generated by the local CGB for non

tx_clkout

TX parallel data input from the FPGA fabric to the TX PCS.

This signal specifies the unused data when you turn on Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of

tx_parallel_data. Connect all these bits to 0. If you do

not connect the unused data bits to 0, then TX parallel data may not be serialized correctly by the Native PHY IP core.

TX FIFO.

bonded configurations, and master CGB for bonded configuration. This clocks the tx_parallel_data from the FPGA fabric to the TX PCS.

Table 62. RX Standard PCS: Data, Control, Status, and Clocks

Name Direction Clock Domain Description

rx_parallel_data[<n> 128-1:0]

unused_rx_parallel_da ta

rx_clkout

rx_coreclkin

Output Synchronous

to the clock driving the read side of the FIFO (rx_coreclk

in or rx_clkout)

Output Synchronous

to the clock driving the read side of the FIFO (rx_coreclk

in or rx_clkout)

Output Clock The low speed parallel clock recovered by the transceiver RX

Input Clock RX parallel clock that drives the read side clock of the RX

RX parallel data from the RX PCS to the FPGA fabric. For each 128-bit word of rx_parallel_data, the data bits correspond to rx_parallel_data[7:0] when 8B/10B decoder is enabled and rx_parallel_data[9:0] when 8B/10B decoder is disabled.

This signal specifies the unused data when you turn on Enable simplified data interface. When simplified data interface is not set, the unused bits are a part of

rx_parallel_data. These outputs can be left floating.

PMA, that clocks the blocks in the RX Standard PCS.

FIFO.

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Table 63. Standard PCS FIFO

Name Direction Clock Domain Description

tx_std_pcfifo_full[<n >-1:0]

tx_std_pcfifo_empty[< n>-1:0]

rx_std_pcfifo_full[<n >-1:0]

rx_std_pcfifo_empty[< n>-1:0]

Output Synchronous

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Indicates when the standard TX FIFO is full. to the clock driving the write side of the FIFO (tx_coreclki

n or tx_clkout)

Indicates when the standard TX FIFO is empty. to the clock driving the write side of the FIFO (tx_coreclki

n or tx_clkout)

Indicates when the standard RX FIFO is full. to the clock driving the read side of the FIFO (rx_coreclki

n or rx_clkout)

Indicates when the standard RX FIFO is empty. to the clock driving the read side of the FIFO (rx_coreclki

n or rx_clkout)

Table 64. Rate Match FIFO

Name Direction Clock Domain Description

rx_std_rmfifo_full[<n >-1:0]

rx_std_rmfifo_empty[< n>-1:0]

rx_rmfifostatus[<n>-1 :0]

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Output Asynchronous Rate match FIFO full flag. When asserted the rate match

Output Asynchronous Rate match FIFO empty flag. When asserted, match FIFO is

Output Asynchronous Indicates FIFO status. The following encodings are defined:

FIFO is full. You must synchronize this signal. This port is only used for GigE mode.

empty. You must synchronize this signal. This port is only used for GigE mode.

• 2'b00: Normal operation

•

2'b01: Deletion, rx_std_rmfifo_full = 1

•

2'b10: Insertion, rx_std_rmfifo_empty = 1

•

2'b11: Full. rx_rmfifostatus is a part of

rx_parallel_data. rx_rmfifostatus corresponds

to rx_parallel_data[14:13].

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Table 65. 8B/10B Encoder and Decoder

Name Direction Clock Domain Description

tx_datak

tx_forcedisp[<n>(<w>/ <s>-1:0]

tx_dispval[<n>(<w>/ <s>-1:0]

rx_datak[<n><w>/ <s>-1:0]

rx_errdetect[<n><w>/ <s>-1:0]

rx_disperr[<n><w>/ <s>-1:0]

rx_runningdisp[<n><w> /<s>-1:0]

rx_patterndetect[<n>< w>/<s>-1:0]

Input tx_clkout

tx_datak is exposed if 8B/10B enabled and simplified data

interface is set.When 1, indicates that the 8B/10B encoded word of tx_parallel_data is control. When 0, indicates that the 8B/10B encoded word of tx_parallel_data is data.

tx_datak is a part of tx_parallel_data when simplified

data interface is not set.

Input Asynchronous This signal allows you to force the disparity of the 8B/10B

encoder. When "1", forces the disparity of the output data to the value driven on tx_dispval. When "0", the current running disparity continues. tx_forcedisp is a part of

tx_parallel_data. tx_forcedisp corresponds to tx_parallel_data[9].

Input Asynchronous Specifies the disparity of the data. When 0, indicates positive

disparity, and when 1, indicates negative disparity.

tx_dispval is a part of tx_parallel_data. tx_dispval

corresponds to tx_dispval[10].

Output

rx_clkout rx_datak is exposed if 8B/10B is enabled and simplified

data interface is set. When 1, indicates that the 8B/10B decoded word of rx_parallel_data is control. When 0, indicates that the 8B/10B decoded word of

rx_parallel_data is data. rx_datak is a part of rx_parallel_data when simplified data interface is not

set.

Output Synchronous to

the clock driving the read side of the FIFO (rx_coreclki

n or rx_clkout)

Output Synchronous to

the clock driving the read side of the FIFO (rx_coreclki

When asserted, indicates a code group violation detected on the received code group. Used along with rx_disperr signal to differentiate between code group violation and disparity errors. The following encodings are defined for

rx_errdetect/rx_disperr:

• 2'b00: no error

• 2'b10: code group violation

•

When asserted, indicates a disparity error on the received code group. rx_disperr is a part of rx_parallel_data. For each 128-bit word, rx_disperr corresponds to

rx_parallel_data[11].

n or rx_clkout)

Output Synchronous to

the clock driving the read side of the FIFO (rx_coreclki

n or

When high, indicates that rx_parallel_data was received with negative disparity. When low, indicates that

rx_parallel_data was received with positive disparity. rx_runningdisp is a part of rx_parallel_data. For

each 128 bit word, rx_runningdisp corresponds to

rx_parallel_data[15].

rx_clkout)

Output Asynchronous When asserted, indicates that the programmed word

alignment pattern has been detected in the current word boundary. rx_patterndetect is a part of

2'b11: disparity error. rx_errdetect is a part of

rx_parallel_data. For each 128-bit word, rx_errdetect corresponds to rx_parallel_data[9].

continued...

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Name Direction Clock Domain Description

rx_syncstatus[<n><w>/

Output Asynchronous When asserted, indicates that the conditions required for

<s>-1:0]

Table 66. Word Aligner and Bitslip

Name Direction Clock Domain Description

tx_std_bitslipboundary sel[5 <n>-1:0]

rx_std_bitslipboundary sel[5 <n>-1:0]

rx_std_wa_patternalig n[<n>-1:0]

rx_std_wa_a1a2size[<n>

-1:0]

rx_bitslip[<n>-1:0]

Input Asynchronous Bitslip boundary selection signal. Specifies the number of

Output Asynchronous This port is used in deterministic latency word aligner mode.

Input Synchronous

to rx_clkout

Input Asynchronous Used for the SONET protocol. Assert when the A1 and A2

Input Asynchronous Used when word aligner mode is bitslip mode. When the

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rx_parallel_data. For each 128-bit word, rx_patterndetect corresponds to rx_parallel_data[12].

synchronization are being met. rx_syncstatus is a part of

rx_parallel_data. For each 128-bit word, rx_syncstatus corresponds to rx_parallel_data[10].

bits that the TX bit slipper must slip.

This port reports the number of bits that the RX block

slipped. This port values should be taken into consideration

in either Deterministic Latency Mode or Manual Mode of

Word Aligner.

Active when you place the word aligner in manual mode. In

manual mode, you align words by asserting

rx_std_wa_patternalign. When the PCS-PMA Interface

width is 10 bits, rx_std_wa_patternalign is level

sensitive. For all the other PCS-PMA Interface widths,

rx_std_wa_patternalign is positive edge sensitive.

You can use this port only when the word aligner is

configured in manual or deterministic latency mode.

When the word aligner is in manual mode, and the PCS-PMA

interface width is 10 bits, this is a level sensitive signal. In

this case, the word aligner monitors the input data for the

word alignment pattern, and updates the word boundary

when it finds the alignment pattern.

For all other PCS-PMA interface widths, this signal is edge

sensitive.This signal is internally synchronized inside the

PCS using the PCS parallel clock and should be asserted for

at least 2 clock cycles to allow synchronization.

framing bytes must be detected. A1 and A2 are SONET

backplane bytes and are only used when the PMA data

width is 8 bits.

Word Aligner is in either Manual (PLD controlled),

Synchronous State Machine or Deterministic Latency ,the

rx_bitslip signal is not valid and should be tied to 0.

For every rising edge of the rx_std_bitslip signal, the

word boundary is shifted by 1 bit. Each bitslip removes the

earliest received bit from the received data.

Table 67. Bit Reversal and Polarity Inversion

Name Direction Clock Domain Description

rx_std_byterev_ena[<n>

-1:0]

rx_std_bitrev_ena[<n>1:0]

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Input Asynchronous This control signal is available when the PMA width is 16 or

Input Asynchronous When asserted, enables bit reversal on the RX interface. Bit

20 bits. When asserted, enables byte reversal on the RX interface. Used if the MSB and LSB of the transmitted data are erroneously swapped.

order may be reversed if external transmission circuitry transmits the most significant bit first. When enabled, the

continued...

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Name Direction Clock Domain Description

tx_polinv[<n>-1:0]

rx_polinv[<n>-1:0]

rx_std_signaldetect[<n

Input Asynchronous When asserted, the TX polarity bit is inverted. Only active

Input Asynchronous When asserted, the RX polarity bit is inverted. Only active

Output Asynchronous When enabled, the signal threshold detection circuitry

>-1:0]

2.4.11. IP Core File Locations

When you generate your Transceiver Native PHY IP, the Quartus® Prime software generates the HDL files that define your instance of the IP. In addition, the Quartus Prime software generates an example Tcl script to compile and simulate your design in the ModelSim simulator. It also generates simulation scripts for Synopsys VCS, Aldec Active-HDL, Aldec Riviera-Pro, and Cadence Incisive Enterprise.

receive circuitry receives all words in the reverse order. The bit reversal circuitry operates on the output of the word aligner.

when TX bit polarity inversion is enabled.

when RX bit polarity inversion is enabled.

senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage. You can specify the signal detect threshold using a Quartus Prime Settings File (.qsf) assignment. This signal is required for the PCI Express, SATA and SAS protocols.

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

<your_ip_or_system_name>.qsys - Top-level IP variation file

<your_ip_or_system_name>.sopcinfo

<your_ip_name> - IP core variation files

<your_ip_name>.cmp - VHDL component declaration file

<your_ip_name>_bb - Verilog HDL black-box EDA synthesis file

<your_ip_name>_inst - IP instantiation template file

<your_ip_name>.ppf - XML I/O pin information file

<your_ip_name>.qip - Lists IP synthesis files

<your_ip_name>.sip - Lists files for simulation

<your_ip_name>.v or .vhd - Greybox timing netlist

synth - IP synthesis files

<your_ip_name>.v or .vhd - Top-level IP synthesis file

sim - IP simulation files

<your_ip_name>.v or .vhd - Top-level simulation file

aldec- Simulator setup scripts

<IP subcore> - IP subcore files

sim

cadence - Simulator setup scripts

mentor - Simulator setup scripts

synopsys - Simulator setup scripts

synth

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

Figure 15. Directory Structure for Generated Files

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Table 68. Transceiver Native PHY Files and Directories

<project_dir> The top-level project directory.

<your_ip_name> .v or .vhd The top-level design file.

<your_ip_name> .qip A list of all files necessary for Quartus Prime compilation.

The following table describes the directories and the most important files for the parameterized Transceiver Native PHY IP core and the simulation environment. These files are in clear text.

File Name Description

continued...

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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File Name Description

<your_ip_name> .bsf A Block Symbol File (.bsf) for your Transceiver Native PHY

<project_dir>/<your_ip_name>/ The directory that stores the HDL files that define the

<project_dir>/sim The simulation directory.

<project_dir>/sim/aldec Simulation files for Riviera-PRO simulation tools.

<project_dir>/sim/cadence Simulation files for Cadence simulation tools.

<project_dir>/sim/mentor Simulation files for Mentor simulation tools.

<project_dir>/sim/synopsys Simulation files for Synopsys simulation tools.

<project_dir>/synth The directory that stores files used for synthesis.

instance.

Transceiver Native PHY IP.

The Verilog and VHDL Transceiver Native PHY IP cores have been tested with the following simulators:

• ModelSim SE

• Synopsys VCS MX

• Cadence NCSim

If you select VHDL for your transceiver PHY, only the wrapper generated by the Quartus Prime software is in VHDL. All the underlying files are written in Verilog or SystemVerilog. To enable simulation using a VHDL-only ModelSim license, the underlying Verilog and SystemVerilog files for the Transceiver Native PHY IP are encrypted so that they can be used with the top-level VHDL wrapper without using a mixed-language simulator.

For more information about simulating with ModelSim, refer to the Mentor Graphics ModelSim Support chapter in volume 3 of the Quartus Prime Handbook.

The Transceiver Native PHY IP cores do not support the NativeLink feature in the Quartus Prime software.

Related Information

Mentor Graphics ModelSim Support

2.4.12. Unused Transceiver Channels

To prevent performance degradation of unused transceiver channels over time, the following assignments for RX pins must be added to an Cyclone 10 GX device QSF. You can either use a global assignment or per-pin assignment. For the per-pin assignment, true or complement RX pin can be specified.

set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON

set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to [pin_name (BB6, for example)]

Example of <pin_name> is AF26 (Do not use PIN_AF26)

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

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set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to AF26

Note: This assignment applies to either an RX or a TX pin. If you assign it to both, the fitter

fails.

2.5. Interlaken

Interlaken is a scalable, channelized chip-to-chip interconnect protocol.

The key advantages of Interlaken are scalability and low I/O count compared to earlier protocols such as SPI 4.2. Other key features include flow control, low overhead framing, and extensive integrity checking. Interlaken operates on 64-bit data words and 3 control bits, which are striped round-robin across the lanes. The protocol accepts packets on 256 logical channels and is expandable to accommodate up to 65,536 logical channels. Packets are split into small bursts that can optionally be interleaved. The burst semantics include integrity checking and per logical channel flow control.

The Interlaken interface is supported with 1 to 12 lanes running at data rates up to

12.5 Gbps per lane on Cyclone 10 GX devices. Interlaken is implemented using the Enhanced PCS. The Enhanced PCS has demonstrated interoperability with Interlaken ASSP vendors and third-party IP suppliers.

Cyclone 10 GX devices provide three preset variations for Interlaken in the Cyclone 10 GX Transceiver Native PHY IP Parameter Editor:

• Interlaken 10x12.5 Gbps

• Interlaken 1x6.25 Gbps

• Interlaken 6x10.3 Gbps

Depending on the line rate, the enhanced PCS can use a PMA to PCS interface width of 32, 40, or 64 bits.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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Transmitter Enhanced PCSTransmitter PMA

Receiver PMA

Receiver Enhanced PCS

Gearbox

tx_serial_data

Serializer

Interlaken

Disparity Generator

Scrambler

PRBS

Generator

PRP

Generator

rx_serial_data

Deserializer

CDR

Descrambler

Interlaken

Disparity Checker

Block

Synchronizer

Interlaken

Frame Sync

Gearbox

PRBS

Verifier

Parallel Clock (312.5 MHz)

Parallel Clock

Serial Clock

Parallel and Serial Clocks

Clock Divider

Parallel and Serial Clocks

Clock Generation Block (CGB)

Serial Clock

Serial Clock (6.25 GHz)

(6.25 GHz) = Data rate/2

Input Reference Clock

64 bits data +

3 bits

control

64 bits data +

3 bits

control

ATX PLL

fPLL

CMU PLL

64B/66B Decoder

and RX SM

10GBASE-R

BER Checker

PRP

rx_pma_div_clkout

tx_pma_div_clkout

Verifier

rx_coreclkin

rx_clkout

186.57 MHz to 312.5MHz

Enhanced PCS

TX FIFO

Enhanced PCS

RX FIFO

Interlaken

Frame Generator

Interlaken

CRC32 Generator

Interlaken

CRC32 Checker

64B/66B Encoder

and TX SM

FPGA Fabric

tx_coreclkin

tx_clkout

Div 40

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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Figure 16. Transceiver Channel Datapath and Clocking for Interlaken

This figure assumes the serial data rate is 12.5 Gbps and the PMA width is 40 bits.

Related Information

• Interlaken Protocol Definition v1.2

• Interlaken Look-Aside Protocol Definition, v1.1

2.5.1. Metaframe Format and Framing Layer Control Word

The Enhanced PCS supports programmable metaframe lengths from 5 to 8192 words. However, for stability and performance, Intel recommends you set the frame length to no less than 128 words. In simulation, use a smaller metaframe length to reduce simulation times. The payload of a metaframe could be pure data payload and a Burst/Idle control word from the MAC layer.

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

Diagnostic

Synchronization

Scrambler State

SKP

Control and

Data Words

Diagnostic

Synchronization

Scrambler State

SKP

Metaframe Length

bx10 b011110 h0F678F678F678F6

bx10 b001010 Scrambler State

66 63 58 57 0

bx10 b000111

66 63 58

h21E57h1E48h1E47h1E40h1E h1E h1E

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

Figure 17. Framing Layer Metaframe Format

The framing control words include:

• Synchronization (SYNC)—for frame delineation and lane alignment (deskew)

• Scrambler State (SCRM)—to synchronize the scrambler

• Skip (SKIP)—for clock compensation in a repeater

• Diagnostic (DIAG)—provides per-lane error check and optional status message

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To form a metaframe, the Enhanced PCS frame generator inserts the framing control words and encapsulates the control and data words read from the TX FIFO as the metaframe payload.

Figure 18. Interlaken Synchronization and Scrambler State Words Format

Figure 19. Interlaken Skip Word Format

The DIAG word is comprised of a status field and a CRC-32 field. The 2-bit status is defined by the Interlaken specification as:

• Bit 1 (Bit 33): Lane health

— 1: Lane is healthy

— 0: Lane is not healthy

• Bit 0 (Bit 32): Link health

— 1: Link is healthy

— 0: Link is not healthy

Intel® Cyclone® 10 GX Transceiver PHY User Guide

Send Feedback

bx10 b011001

66 63 58

h000000

57 33

Status

32 31

CRC32

034

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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The tx_enh_frame_diag_status[1:0] input from the FPGA fabric is inserted into the Status field each time a DIAG word is created by the framing generator.

Figure 20. Interlaken Diagnostic Word

2.5.2. Interlaken Configuration Clocking and Bonding

The Cyclone 10 GX Interlaken PHY layer solution is scalable and has flexible data rates. You can implement a single lane link or bond up to 48 lanes together. You can choose a lane data rate up to 12.5 Gbps. You can also choose between different reference clock frequencies, depending on the PLL used to clock the transceiver.

You can use an ATX PLL or fPLL to provide the clock for the transmit channel. An ATX PLL has better jitter performance compared to an fPLL. You can use the CMU PLL to clock only the non-bonded Interlaken transmit channels. However, if you use the CMU PLL, you lose one RX transceiver channel.

For the multi-lane Interlaken interface, TX channels are usually bonded together to minimize the transmit skew between all bonded channels. Currently, xN bonding and PLL feedback compensation bonding schemes are available to support a multi-lane Interlaken implementation. If the system tolerates higher channel-to-channel skew, you can choose to not bond the TX channels.

To implement bonded multi-channel Interlaken, all channels must be placed contiguously. The channels may all be placed in one bank (if not greater than six lanes) or they may span several banks.

Related Information

Using PLLs and Clock Networks on page 231

For more information about implementing PLLs and clocks

2.5.2.1. xN Clock Bonding Scenario

The following figure shows a xN bonding example supporting 10 lanes. Each lane is running at 12.5 Gbps. The first six TX channels reside in one transceiver bank and the other four TX channels reside in the adjacent transceiver bank. The ATX PLL provides the serial clock to the master CGB. The CGB then provides parallel and serial clocks to all of the TX channels inside the same bank and other banks through the xN clock network.

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

Figure 21. 10X12.5 Gbps xN Bonding

Transceiver PLL

Instance (6.25 GHz)

ATX PLL

Native PHY Instance

(10 Ch Bonded 12.5 Gbps)

TX Channel

Transceiver Bank 2

TX Channel

Master

CGB

Transceiver Bank 1

Note: Intel Cyclone 10 GX devices have transceiver channels that can support data rates up to 12.5 Gbps for chip-to-chip and chip-to-module communication, and up to 6.6 Gbps for backplane communication.

TX Channel

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine

Related Information

• Implementing x6/xN Bonding Mode on page 236 For detailed information on xN bonding limitations

• Using PLLs and Clock Networks on page 231 For more information about implementing PLLs and clocks

The Interlaken configuration sets the enhanced PCS TX and RX FIFOs in Interlaken elastic buffer mode. In this mode of operation, TX and RX FIFO control and status port signals are provided to the FPGA fabric. Connect these signals to the MAC layer as

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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required by the protocol. Based on these FIFO status and control signals, you can implement the multi-lane deskew alignment state machine in the FPGA fabric to control the transceiver RX FIFO block.

Note: You must also implement the soft bonding logic to control the transceiver TX FIFO

block.

2.5.2.2.1. TX FIFO Soft Bonding

The MAC layer logic and TX soft bonding logic control the writing of the Interlaken word to the TX FIFO with tx_enh_data_valid (functions as a TX FIFO write enable) by monitoring the TX FIFO flags (tx_fifo_full, tx_fifo_pfull,

tx_fifo_empty, tx_fifo_pempty, and so forth). On the TX FIFO read side, a read

enable is controlled by the frame generator. If tx_enh_frame_burst_en is asserted high, the frame generator reads data from the TX FIFO.

A TX FIFO pre-fill stage must be implemented to perform the TX channel soft bonding. The following figure shows the state of the pre-fill process.

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

Figure 22. TX Soft Bonding Flow

Exit from

tx_digitalreset

Deassert all lanes tx_enh_frame_burst_en

Assert all lanes tx_enh_data_valid

Deassert all lanes

tx_enh_data_valid

All lanes

full?

yes

Any lane

send new frame?

tx_enh_frame

asserted?

yes

All lanes

full?

TX FIFO pre-fill

completed

Wait for extra 16

tx_coreclkin cycles

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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The following figure shows that after deasserting tx_digitalreset, TX soft bonding logic starts filling the TX FIFO until all lanes are full.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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tx_enh_data_valid

tx_digitalreset

tx_enh_fifo_full

tx_enh_fifo_pfull

tx_enh_fifo_empty

tx_enh_fifo_pempty

tx_enh_fifo_cnt

tx_enh_frame

tx_enh_frame_burst_en

3f 00

000000

003f

1... 2... 3... 4... 5... 6... 7... 8... 9... a... b... c... d... e... ffffff

Deassert tx_digitalreset

Deassert burst_en for all Lanes and Fill TX FIFO Until all Lane FIFOs Are Full

tx_enh_data_valid

tx_digitalreset

tx_enh_fifo_full

tx_enh_fifo_pfull

tx_enh_fifo_empty

tx_enh_fifo_pempty

tx_enh_fifo_cnt

tx_enh_frame

tx_enh_frame_burst_en

3f 00

ffffff

After the Pre-fill Stage, Assert burst_en. The Frame Generator Reads Data from the TX FIFO for the Next Metaframe

The User Logic Asserts data_valid to Send Data to the TX FIFO Based on the FIFO Status

The TX FIFO Writes Backpressure

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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Figure 23. TX FIFO Pre-fill (6-lane Interface)

After the TX FIFO pre-fill stage completes, the transmit lanes synchronize and the MAC layer begins to send valid data to the transceiver’s TX FIFO. You must never allow the TX FIFO to overflow or underflow. If it does, you must reset the transceiver and repeat the TX FIFO pre-fill stage.

For a single lane Interlaken implementation, TX FIFO soft bonding is not required. You can begin sending an Interlaken word to the TX FIFO after tx_digitalreset deasserts.

The following figure shows the MAC layer sending valid data to the Native PHY after the pre-fill stage. tx_enh_frame_burst_en is asserted, allowing the frame generator to read data from the TX FIFO. The TX MAC layer can now control

tx_enh_data_valid and write data to the TX FIFO based on the FIFO status signals.

Figure 24. MAC Sending Valid Data (6-lane Interface)

2.5.2.2.2. RX Multi-lane FIFO Deskew State Machine

Add deskew logic at the receiver side to eliminate the lane-to-lane skew created at the transmitter of the link partner, PCB, medium, and local receiver PMA.

Implement a multi-lane alignment deskew state machine to control the RX FIFO

Send Feedback

operation based on available RX FIFO status flags and control signals.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

Exit from

rx_digitalreset

Deassert all Lane’s rx_enh_fifo_rd_en

All Lane’s

rx_enh_fifo_pempty

Deasserted?

yes

All Lane’s

rx_enh_fifo_pfull

Deasserted?

yes

Assert rx_enh_fifo_align_clr for at

least 4 rx_coreclkin Cycles

RX FIFO Deskew

Completed

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

Figure 25. State Flow of the RX FIFO Deskew

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Each lane's rx_enh_fifo_rd_en should remain deasserted before the RX FIFO deskew is completed. After frame lock is achieved (indicated by the assertion of

rx_enh_frame_lock; this signal is not shown in the above state flow), data is

written into the RX FIFO after the first alignment word (SYNC word) is found on that channel. Accordingly, the RX FIFO partially empty flag (rx_enh_fifo_pempty) of that channel is asserted. The state machine monitors the rx_enh_fifo_pempty and

rx_enh_fifo_pfull signals of all channels. If the rx_enh_fifo_pempty signals

from all channels deassert before any channels rx_enh_fifo_pfull assert, which implies the SYNC word has been found on all lanes of the link, the MAC layer can start reading from all the RX FIFO by asserting rx_enh_fifo_rd_en simultaneously. Otherwise, if the rx_enh_fifo_pfull signal of any channel asserts high before the

rx_enh_fifo_pempty signals deassertion on all channels, the state machine needs

to flush the RX FIFO by asserting rx_enh_fifo_align_clr high for 4 cycles and repeating the soft deskew process.

The following figure shows one RX deskew scenario. In this scenario, all of the RX FIFO partially empty lanes are deasserted while the pfull lanes are still deasserted. This indicates the deskew is successful and the FPGA fabric starts reading data from the RX FIFO.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

Send Feedback

rx_enh_data_valid

rx_enh_fifo_rd_en

rx_enh_fifo_full

rx_enh_fifo_pfull

rx_enh_fifo_empty

rx_enh_fifo_pempty

rx_enh_fifo_align_val

rx_enh_frame_lock

rx_enh_fifo_align_clr

00 00

[5]

[4]

[3] [2] [1] [0]

21 3f

21 3f3b

001e

Each Lane Is

Frame-Locked

in a Different

Cycle

After deskew is successful, the user logic asserts rd_en for all lanes to start reading data from the RX FIFO.

data_valid is asserted, indicating that the RX FIFO is outputting valid data.

Deassertion of pempty of all lanes before any lane pfull goes high, which means the deskew is complete.

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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Figure 26. RX FIFO Deskew

2.5.3. How to Implement Interlaken in Cyclone 10 GX Transceivers

You should be familiar with the Interlaken protocol, Enhanced PCS and PMA architecture, PLL architecture, and the reset controller before implementing the Interlaken protocol PHY layer.

Cyclone 10 GX devices provide three preset variations for Interlaken in the IP Parameter Editor:

• Interlaken 1x6.25 Gbps

• Interlaken 6x10.3 Gbps

1. Instantiate the Cyclone 10 GX Transceiver Native PHY IP from the IP Catalog

(Installed IP ➤ Library ➤ Interface Protocols ➤ Transceiver PHY ➤

Cyclone 10 GX Transceiver Native PHY). Refer to Select and Instantiate the PHY IP Core on page 17 for more details.

Send Feedback

2. Select Interlaken from the Transceiver configuration rules list located under Datapath Options, depending on which protocol you are implementing.

3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for

Interlaken Transceiver Configuration Rules.... Or you can use the protocol presets

described in Transceiver Native PHY Presets. You can then modify the settings to meet your specific requirements.

4. Click Generate to generate the Native PHY IP (this is your RTL file).

Intel® Cyclone® 10 GX Transceiver PHY User Guide

reconfig_reset reconfig_clk reconfig_avmm

tx_digital_reset

tx_clkout tx_coreclkin tx_control[17:0] (1) tx_parallel_data[127:0] (1) tx_enh_data_valid tx_enh_frame_burst_en tx_enh_frame_diag_status[1:0] tx_enh_frame tx_enh_fifo_cnt[3:0] tx_enh_fifo_full tx_enh_fifo_pfull tx_enh_fifo_empty tx_enh_fifo_pempty

Reconfiguration

Registers

TX Enhanced PCS

rx_clkout rx_coreclkin rx_parallel_data[127:0] (2) rx_control[19:0] (2) rx_enh_fifo_rd_en rx_enh_data_valid rx_enh_fifo_align_val rx_enh_fifo_align_clr rx_enh_frame rx_enh_fifo_cnt[3:0] rx_enh_fifo_full rx_enh_fifo_pfull rx_enh_fifo_empty rx_enh_fifo_pempty rx_enh_frame_diag_status[1:0] rx_enh_frame_lock rx_enh_crc32_err rx_enh_blk_lock

RX Enhanced PCS

Hard

Calibration Block

TX PMA

Serializer

RX PMA

DeserializerCDR

tx_cal_busy

rx_cal_busy

tx_serial_data

rx_serialloopback

rx_serial_data rx_cdr_refclk0

rx_is_lockedtodata

rx_is_lockedtoref

tx_serial_clk or

tx_bonding_clocks[5:0]

(from TX PLL)

Notes: (1) The width of tx_parallel_data and tx_control depends on whether the simplified interface is enabled or not. If the simplified interface is enabled, then tx_parallel_data = 64 bits and tx_control = 3 bits. The width shown here is without simplified interface. (2) The width of rx_parallel_data and rx_control depends on whether the simplified interface is enabled or not. If the simplified interface is enabled, then rx_parallel_data = 64 bits and rx_control = 10 bits. The width shown here is without simplified interface.

tx_analog_reset

rx_analog_reset

rx_digital_reset

Cyclone 10 Transceiver Native PHY

32/40/64

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

Figure 27. Signals and Ports of Native PHY IP for Interlaken

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5. Configure and instantiate your PLL.

6. Create a transceiver reset controller. You can use your own reset controller or use the Transceiver PHY Reset Controller.

7. Implement a TX soft bonding logic and an RX multi-lane alignment deskew state machine using fabric logic resources for multi-lane Interlaken implementation.

8. Connect the Native PHY IP to the PLL IP and the reset controller.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

Send Feedback

Reset

Controller

PLL IP

Pattern

Generator

Pattern Verifier

TX Soft Bonding

Deskew

Cyclone 10 Transceiver Native PHY

PLL and CGB Reset

TX/RX Analog/Digital Reset

TX FIFO Status

TX Data Stream

RX Data Stream

TX FIFO Control

Control and Status

RX FIFO Status

RX FIFO Control

TX Clocks

12`h000

12`h... 12`hFFF

12`h000

12`hFFF12`h000

12`h000

12`h00012`hFFF

12`hFFF

12`hFFF 12`h000

12`h000

768'h<192_data_char>

36'h<9_kl_char>

12`h000

12`hFFF

12`...

12`h000

12`hFFF

12`h000

12`h000...

12`h000

768'h<192_data_char>

36'h<9_kl_char>

12`h000

12`hFFF

768'h<192_data_char>

36'h<9_kl_char> 12`h000

12`h000

12`hFFF

12`h000

768`h...

pll_locked

tx_analogreset

tx_clkout[0]

tx_clkout

tx_digitalreset

tx_ready[0]

tx_ready

tx_enh_data_valid[0]

tx_enh_data_valid

tx_enh_fifo_full

tx_enh_frame[0]

tx_enh_frame

tx_enh_frame_burst_en[0]

tx_enh_frame_burst_en

tx_parallel_data

tx_control

tx_enh_fifo_empty

tx_enh_fifo_pempty

tx_ready

Asserted

Pre-Fill

Stage

Pre-Fill Completed Assert burst_en for

All Lanes

Send Data Based on FIFO Flags

12`h000

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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Figure 28. Connection Guidelines for an Interlaken PHY Design

This figure shows and example connection for an Interlake PHY design.

For the blue blocks, Intel provides an IP core. The gray blocks use the TX soft bonding logic and RX deskew logic. The white blocks are your test logic or MAC layer logic.

9. Simulate your design to verify its functionality.

Figure 29. 12 Lanes Bonded Interlaken Link, TX Direction

To show more details, three different time segments are shown with the same zoom level.

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

rx_clkout[0]

rx_digitalreset

rx_ready

rx_enh_blk_lock

rx_enh_frame_lock

rx_enh_fifo_pfull[0]

rx_enh_fifo_pfull

rx_enh_fifo_pempty

rx_enh_fifo_align_clr

rx_enh_fifo_align_val

rx_enh_fifi_rd_en

rx_enh_data_valid

rx_parallel_data

rx_control

12`h00012`hFFF

12`h000

12`hFFF

12`h000

12`h000 12`h000

768'h<192_hexadecimal_data_char>

120'h<30_k_char>

12`hFFF

12`h00112`h0...

12`h000

12`hFFF 12`h000

12`h00...

12`h000 12`h000

768'h<192_data_char> 120'h<30_k_char>

12`hFFE

12`h001

12`h000

12`hFFF

12`h000

12`hFFF

12`h000

12`hFFF 12`h000

12`hFFF

12`h00..

12`h000 12`h000

768'h<192_data_ch... 120'h<30_k_char>

12`h000 12`h000

12`hFFF 12`hFFF12`h00..

12`hFFF 12`hFFF

12`h00..

768`h... 120`h90a... 120'h<30...

rx_ready Asserted

12`h00...

12`hFF...

Some Lanes pfull Signal Is Asserted

before All Lanes pempty is Deasserted;

RX Deskew Fails. Need to Realign

Assert align_clr

to Re-Align

All Lanes pfull Low and All Lanes pempty Deasserted

RX Deskew Complete

Start Reading Data

Based on FIFO Flags

12`h00..

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

Figure 30. 12 Lanes Bonded Interlaken Link, RX Direction

To show more details, three different time segments are shown with different zoom level.

2.5.4. Native PHY IP Parameter Settings for Interlaken

This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of parameter values.

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Table 69. General and Datapath Parameters

Parameter Value

Message level for rule violations error

Transceiver configuration rules Interlaken

PMA configuration rules basic

Transceiver mode TX / RX Duplex

Number of data channels 1 to 12

Data rate Up to 12.5 Gbps for GX devices

Enable datapath and interface reconfiguration On / Off

Enable simplified data interface On / Off

Provide separate interface for each channel On / Off

Table 70. TX PMA Parameters

Parameter Value

TX channel bonding mode Not bonded

PCS TX channel bonding master If TX channel bonding mode is set to PMA and PCS

Intel® Cyclone® 10 GX Transceiver PHY User Guide

warning

TX Simplex RX Simplex

(Depending on Enhanced PCS to PMA interface width selection)

PMA-only bonding PMA and PCS bonding

bonding, then: Auto, 0, 1, 2, 3,...,[Number of data channels – 1]

continued...

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Parameter Value

Actual PCS TX channel bonding master If TX channel bonding mode is set to PMA and PCS

TX local clock division factor If TX channel bonding mode is not bonded, then:

Number of TX PLL clock inputs per channel If TX channel bonding mode is not bonded, then:

Initial TX PLL clock input selection 0

Enable tx_pma_clkout port On / Off

Enable tx_pma_div_clkout port On / Off

tx_pma_div_clkout division factor When Enable tx_pma_div_clkout port is On, then:

Enable tx_pma_elecidle port On / Off

Enable rx_seriallpbken port On / Off

bonding, then: 0, 1, 2, 3,...,[Number of data channels – 1]

1, 2, 4, 8

1, 2, 3, 4

Disabled, 1, 2, 33, 40, 66

Table 71. RX PMA Parameters

Parameter Value

Number of CDR reference clocks 1 to 5

Selected CDR reference clock 0 to 4

Selected CDR reference clock frequency Select legal range defined by the Quartus Prime software

PPM detector threshold 100, 300, 500, 1000

CTLE adaptation mode manual,

Enable rx_pma_clkout port On / Off

Enable rx_pma_div_clkout port On / Off

rx_pma_div_clkout division factor When Enable rx_pma_div_clkout port is On, then:

Disabled, 1, 2, 33, 40, 66

Enable rx_pma_clkslip port On / Off

Enable rx_is_lockedtodata port On / Off

Enable rx_is_lockedtoref port On / Off

Enable rx_set_locktodata and rx_set_locktoref ports On / Off

Enable rx_seriallpbken port On / Off

Enable PRBS verifier control and status ports On / Off

Table 72. Enhanced PCS Parameters

Parameter Value

Enhanced PCS / PMA interface width 32, 40, 64

FPGA fabric / Enhanced PCS interface width 67

Enable 'Enhanced PCS' low latency mode Allowed when the PMA interface width is 32 and preset

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variations for data rate is 10.3125 Gbps or 6.25 Gbps; otherwise Off

Intel® Cyclone® 10 GX Transceiver PHY User Guide

continued...

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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Parameter Value

Enable RX/TX FIFO double-width mode Off

TX FIFO mode Interlaken

TX FIFO partially full threshold 8 to 15

TX FIFO partially empty threshold 1 to 8

Enable tx_enh_fifo_full port On / Off

Enable tx_enh_fifo_pfull port On / Off

Enable tx_enh_fifo_empty port On / Off

Enable tx_enh_fifo_pempty port On / Off

RX FIFO mode Interlaken

RX FIFO partially full threshold from 10-29 (no less than pempty_threshold+8)

RX FIFO partially empty threshold 2 to 10

Enable RX FIFO alignment word deletion (Interlaken) On / Off

Enable RX FIFO control word deletion (Interlaken) On / Off

Enable rx_enh_data_valid port On / Off

Enable rx_enh_fifo_full port On / Off

Enable rx_enh_fifo_pfull port On / Off

Enable rx_enh_fifo_empty port On / Off

Enable rx_enh_fifo_pempty port On / Off

Enable rx_enh_fifo_del port (10GBASE-R) Off

Enable rx_enh_fifo_insert port (10GBASE-R) Off

Enable rx_enh_fifo_rd_en port On

Enable rx_enh_fifo_align_val port (Interlaken) On / Off

Enable rx_enh_fifo_align_clr port (Interlaken) On

Table 73. Interlaken Frame Generator Parameters

Parameter Value

Enable Interlaken frame generator On

Frame generator metaframe length 5 to 8192 (Intel recommends a minimum metaframe

length of 128)

Enable frame generator burst control On

Enable tx_enh_frame port On

Enable tx_enh_frame_diag_status port On

Enable tx_enh_frame_burst_en port On

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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Table 74. Interlaken Frame Synchronizer Parameters

Parameter Value

Enable Interlaken frame synchronizer On

Frame synchronizer metaframe length 5 to 8192 (Intel recommends a minimum metaframe

Enable rx_enh_frame port On

Enable rx_enh_frame_lock port On / Off

Enable rx_enh_frame_diag_status port On / Off

length of 128)

Table 75. Interlaken CRC-32 Generator and Checker Parameters

Parameter Value

Enable Interlaken TX CRC-32 generator On

Enable Interlaken TX CRC-32 generator error insertion

Enable Interlaken RX CRC-32 checker On

Enable rx_enh_crc32_err port On / Off

On / Off

Table 76. Scrambler and Descrambler Parameters

Parameter Value

Enable TX scrambler (10GBASE-R / Interlaken) On

TX scrambler seed (10GBASE-R / Interlaken) 0x1 to 0x3FFFFFFFFFFFFFF

Enable RX descrambler (10GBASE-R / Interlaken) On

Table 77. Interlaken Disparity Generator and Checker Parameters

Parameter Value

Enable Interlaken TX disparity generator On

Enable Interlaken RX disparity checker On

Enable Interlaken TX random disparity bit On / Off

Table 78. Block Sync Parameters

Parameter Value

Enable RX block synchronizer On

Enable rx_enh_blk_lock port On / Off

Table 79. Gearbox Parameters

Parameter Value

Enable TX data bitslip Off

Enable TX data polarity inversion On / Off

Enable RX data bitslip Off

continued...

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

Parameter Value

Enable RX data polarity inversion On / Off

Enable tx_enh_bitslip port Off

Enable rx_bitslip port Off

Table 80. Dynamic Reconfiguration Parameters

Parameter Value

Enable dynamic reconfiguration On / Off

Share reconfiguration interface On / Off

Enable Native PHY Debug Master Endpoint On / Off

Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE

Enable capability registers On / Off

Set user-defined IP identifier: 0 to 255

Enable control and status registers On / Off

Enable prbs soft accumulators On / Off

On / Off

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Table 81. Configuration Files Parameters

Parameter Value

Configuration file prefix —

Generate SystemVerilog package file On / Off

Generate C header file On / Off

Generate MIF (Memory Initialization File) On / Off

Include PMA analog settings in configuration files On / Off

Table 82. Configuration Profiles Parameters

Parameter Value

Enable multiple reconfiguration profiles On / Off

Enable embedded reconfiguration streamer On / Off

Generate reduced reconfiguration files On / Off

Number of reconfiguration profiles 1 to 8

Selected reconfiguration profile 1 to 7

2.6. Ethernet

The Ethernet standard comprises many different PHY standards with variations in signal transmission medium and data rates. The 1G/10GbE and 10GBASE-R PHY IP Core enables Ethernet connectivity at 1 Gbps and 10 Gbps.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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Application

Presentation

Session

Transport

Network

Data Link

Physical

OSI

Reference

Model

Layers

Higher Layers

LAN

CSMA/CD

LAYERS

LLC (Logical Link Control)

or other MAC Client

MAC Control (Optional)

Media Access Control (MAC)

Reconciliation

PHY Sublayers

GMII

MDI

PMA

PCS

RECONCILIATION

PMD

Medium

1 Gbps

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Table 83. 1G/10G Data Rates and Transceiver Configuration Rules

Data Rate Transceiver Configuration Rule/IP

1G • Gigabit Ethernet

• Gigabit Ethernet 1588

10G • 10GBASE-R

• 10GBASE-R 1588

1G/10G 1G/10G Ethernet PHY IP

2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2

Gigabit Ethernet (GbE) is a high-speed local area network technology that provides data transfer rates of about 1 Gbps. GbE builds on top of the ethernet protocol, but increases speed tenfold over Fast Ethernet. IEEE 802.3 defines GbE as an intermediate (or transition) layer that interfaces various physical media with the media access control (MAC) in a Gigabit Ethernet system. Gigabit Ethernet PHY shields the MAC layer from the specific nature of the underlying medium and is divided into three sublayers shown in the following figure.

Figure 31. GbE PHY Connection to IEEE 802.3 MAC and RS

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

FIFO (1)

Byte

Deserializer (4)

8B/10B Decoder

Rate Match FIFO (2)

Receiver PMA

Word Aligner

Deserializer

CDR

Receiver Standard PCS

Transmitter Standard PCS

Transmitter PMA

Serializer

tx_serial_data

rx_serial_data

FPGA Fabric

FIFO (1)

Byte Serializer (3)

8B/10B Encoder

PRBS

Generator

TX Bit Slip

Parallel Clock

Serial Clock

Parallel and Serial Clock

Clock Divider

rx_pma_div_clkout

Serial Clock

Clock Generation Block (CGB) (5)

ATX PLL

CMU PLL

fPLL

tx_coreclkin

rx_coreclkin

rx_clkout or tx_clkout

Parallel Clock (Recovered)

Parallel Clock

(From Clock

Divider)

tx_clkout

rx_clkout

PRBS

Verifier

tx_pma_div_clkout

625 MHz

125 MHz

625 MHz

125 MHz

Notes:

1. This block is set in low latency mode for GbE and register_fifo mode for GbE with IEEE 1588v2.

2. The rate match FIFO of the hard PCS is disabled for GbE with IEEE 1588v2 because it is not able to achieve deterministic latency. It is also disabled for Triple-speed Ethernet (TSE) configurations that require an auto-negotiation sequence. The insertion/deletion operation could break the auto-negotiation functionality due to the rate matching of different frequency PPM scenarios.The soft rate match FIFO is constructed in the GbE Serial Gigabit Media Independent Interface (SGMII) IP core.

3. The byte serializer can be enabled or disabled.

4. The byte deserializer can be enabled or disabled.

5. The CGB is in the Native PHY.

125 MHz

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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Figure 32. Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with

IEEE 1588v2

Note: The Native PHY only supports basic PCS functions. The Native PHY does not support

auto-negotiation state machine, collision-detect, and carrier-sense. If required, you must implement these functions in the FPGA fabric or external circuits.

GbE with IEEE 1588v2

GbE with IEEE 1588v2 provides a standard method to synchronize devices on a network. To improve performance, the protocol synchronizes slave clocks to a master clock so that events and time stamps are synchronized in all devices. The protocol enables heterogeneous systems that include clocks of various inherent precision, resolution, and stability to synchronize to a grandmaster clock.

The TX FIFO and RX FIFO are set to register_fifo mode for GbE with IEEE 1588v2.

2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2

Intel® Cyclone® 10 GX Transceiver PHY User Guide

The 8B/10B encoder clocks 8-bit data and 1-bit control identifiers from the transmitter phase compensation FIFO and generates 10-bit encoded data. The 10-bit encoded data is sent to the PMA.

The IEEE 802.3 specification requires GbE to transmit Idle ordered sets (/I/) continuously and repetitively whenever the gigabit media-independent interface (GMII) is Idle. This transmission ensures that the receiver maintains bit and word synchronization whenever there is no active data to be transmitted.

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K28 .5 D14 .3 K 28.5 D 24.0 K28 .5 D15 .8 K 28.5 D 21.5

tx_datain

clock

Dx .y

Dx .y K 28.5 D 5.6 K 28.5 D16 .2 K 28.5 D 16.2 K28 .5

tx_dataout

Ordered Set

D21 .5

/I1/ /I2/ /I2/ /C 2/

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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For the GbE protocol, the transmitter replaces any /Dx.y/ following a /K28.5/ comma with either a /D5.6/ (/I1/ ordered set) or a /D16.2/ (/I2/ ordered set), depending on the current running disparity. The exception is when the data following the /K28.5/ is / D21.5/ (/C1/ ordered set) or /D2.2/ (/C2/) ordered set. If the running disparity before the /K28.5/ is positive, an /I1/ ordered set is generated. If the running disparity is negative, a /I2/ ordered set is generated. The disparity at the end of a /I1/ is the opposite of that at the beginning of the /I1/. The disparity at the end of a /I2/ is the same as the beginning running disparity immediately preceding transmission of the Idle code. This sequence ensures a negative running disparity at the end of an Idle ordered set. A /Kx.y/ following a /K28.5/ does not get replaced.

Note: /D14.3/, /D24.0/, and /D15.8/ are replaced by /D5.6/ or /D16.2/ (for I1 and I2

ordered sets). D21.5 (/C1/) is not replaced.

Figure 33. Idle Ordered-Set Generation Example

Related Information

8B/10B Encoder on page 302

2.6.1.1.1. Reset Condition for 8B/10B Encoder in GbE, GbE with IEEE 1588v2

After deassertion of tx_digitalreset, the transmitters automatically transmit at least three /K28.5/ comma code groups before transmitting user data on the

tx_parallel_data port. This transmission could affect the synchronization state

machine behavior at the receiver.

Depending on when you start transmitting the synchronization sequence, there could be an even or odd number of /Dx.y/ code groups transmitted between the last of the three automatically sent /K28.5/ code groups and the first /K28.5/ code group of the synchronization sequence. If there is an even number of /Dx.y/code groups received between these two /K28.5/ code groups, the first /K28.5/ code group of the synchronization sequence begins at an odd code group boundary. The synchronization state machine treats this as an error condition and goes into the loss of synchronization state.

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

clock

tx_parallel_data

tx_digitalreset

K28.5

xxx

Dx.y

K28.5

K28.5 K28.5Dx.y Dx.y Dx.y

n + 1

n + 2

n + 3

n + 4

Automatically transmitted /K28.5/

User transmitted data

User transmitted synchronization sequence

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

Figure 34. Reset Condition

2.6.1.2. Word Alignment for GbE, GbE with IEEE 1588v2

The word aligner for the GbE and GbE with IEEE 1588v2 protocols is configured in automatic synchronization state machine mode. The Intel Quartus Prime software automatically configures the synchronization state machine to indicate synchronization when the receiver receives three consecutive synchronization ordered sets. A synchronization ordered set is a /K28.5/ code group followed by an odd number of valid /Dx.y/ code groups. The fastest way for the receiver to achieve synchronization is to receive three continuous {/K28.5/, /Dx.y/} ordered sets.

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The GbE PHY IP core signals receiver synchronization status on the rx_syncstatus port of each channel. A high on the rx_syncstatus port indicates that the lane is synchronized; a low on the rx_syncstatus port indicates that the lane has fallen out of synchronization. The receiver loses synchronization when it detects three invalid

code groups separated by less than three valid code groups or when it is reset.

Table 84. Synchronization State Machine Parameter Settings for GbE

Synchronization State Machine Parameter Setting

Number of word alignment patterns to achieve sync 3

Number of invalid data words to lose sync 3

Number of valid data words to decrement error count 3

The following figure shows rx_syncstatus high when three consecutive ordered sets are sent through rx_parallel_data.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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Three Consecutive Ordered Sets Received to Achieve Synchronization

c5 bc 50 bcbc 50 8d8c 00 8c 8drx_parallel_data

rx_datak

rx_syncstatus

rx_patterndetect

rx_disperr

rx_errdetect

rx_datak

rx_parallel_data a4 bc 50 8d a4 bc 50 8d a4 bc 50 508d a4 bc

rx_patterndetect

rx_disperr

rx_errdetect

rx_runningdisp

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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Figure 35. rx_syncstatus High

Related Information

Word Aligner on page 305

2.6.1.3. 8B/10B Decoding for GbE, GbE with IEEE 1588v2

The 8B/10B decoder takes a 10-bit encoded value as input and produces an 8-bit data value and 1-bit control value as output.

Figure 36. Decoding for GbE

Dx.y(0x8d), Dx.y(0xa4), K28.5(0xbc), and Dx.y(0x50) are received at rx_parallel_data. /K28.5/ is set as the word alignment pattern. rx_patterndetect goes high whenever it detects /K28.5/(0xbc). rx_datak is high when bc is received, indicating that the decoded word is a control word. Otherwise, rx_datak is low.

rx_runningdisp is high for 0x8d, indicating that the decoded word has negative disparity and 0xa4 has

positive disparity.

Related Information

8B/10B Decoder on page 311

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

D x .y K 28 . 5

datain

K 28 . 5 D 16 .2

K 28 .5 D 16 .2 D x .y

D 16 .2

F irst /I2 / O rdered S et /I2 / Ordered Se tS econd Third /I2 / O rdered S et

D x .y D x .yK 28 . 5dataout D16 .2

/I2/ SKP Symbol Deleted

D x .y K 28 . 5

datain

K 28 . 5

D 16 .2

K 28 .5 D 16 .2 D x .y

D 16 .2

D x .y K 28 . 5dataout D16 .2 D 1 6 .2

/I2/ SKP Symbol Inserted

First /I2/ Ordered Set Second /I2/ Ordered Set

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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2.6.1.4. Rate Match FIFO for GbE

The rate match FIFO compensates frequency Part-Per-Million (ppm) differences between the upstream transmitter and the local receiver reference clock up to 125 MHz ± 100 ppm difference.

Note: 200 ppm total is only true if calculated as (125 MHz + 100 ppm) - (125 MHz - 100

ppm) = 200 ppm. By contrast, (125 MHz + 0 ppm) - (125 MHz - 200 ppm) supports center-spread clocking, but does not support downstream clocking.

The GbE protocol requires the transmitter to send idle ordered sets /I1/ (/K28.5/ D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps (IPG) adhering to the rules listed in the IEEE 802.3-2008 specification.

The rate match operation begins after the synchronization state machine in the word aligner indicates synchronization is acquired by driving the rx_syncstatus signal high. The rate matcher deletes or inserts both symbols /K28.5/ and /D16.2/ of the /I2/ ordered sets as a pair in the operation to prevent the rate match FIFO from overflowing or underflowing. The rate match operation can insert or delete as many /I2/ ordered sets as necessary.

The following figure shows a rate match deletion operation example where three symbols must be deleted. Because the rate match FIFO can only delete /I2/ ordered sets, it deletes two /I2/ ordered sets (four symbols deleted).

Figure 37. Rate Match FIFO Deletion

The following figure shows an example of rate match FIFO insertion in the case where one symbol must be inserted. Because the rate match FIFO can only insert /I2/ ordered sets, it inserts one /I2/ ordered set (two symbols inserted).

Figure 38. Rate Match FIFO Insertion

rx_std_rmfifo_full and rx_std_rmfifo_empty are forwarded to the FPGA

fabric to indicate rate match FIFO full and empty conditions.

The rate match FIFO does not delete code groups to overcome a FIFO full condition. It asserts the rx_std_rmfifo_full flag for at least two recovered clock cycles to indicate rate match FIFO full. The following figure shows the rate match FIFO full condition when the write pointer is faster than the read pointer.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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2D 2E 2F 30 31 32 33 34 35 36 37 38

tx_parallel_data

rx_parallel_data 04 05 06 07 08 09 0A 0B 0C 0D 0E

rx_std_rmfifo_full

The rx_std_rmfifo_full status flag indicates

that the FIFO is full at this time

1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C

tx_parallel_data

rx_parallel_data 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 00 01

rx_std_rmfifo_empty

The rx_std_rmfifo_empty status flag indicates

that the FIFO is empty at this time

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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Figure 39. Rate Match FIFO Full Condition

The rate match FIFO does not insert code groups to overcome the FIFO empty condition. It asserts the rx_std_rmfifo_empty flag for at least two recovered clock cycles to indicate that the rate match FIFO is empty. The following figure shows the rate match FIFO empty condition when the read pointer is faster than the write pointer.

Figure 40. Rate Match FIFO Empty Condition

In the case of rate match FIFO full and empty conditions, you must assert the

rx_digitalreset signal to reset the receiver PCS blocks.

Related Information

Rate Match FIFO on page 310

2.6.1.5. How to Implement GbE, GbE with IEEE 1588v2 in Intel Cyclone 10 GX Transceivers

You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing the GbE protocol.

1. Instantiate the Intel Cyclone 10 GX Transceiver Native PHY IP from the IP Catalog.

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Intel® Cyclone® 10 GX Transceiver PHY User Guide

Reconfiguration

Registers

NIOS

Hard Calibration IP

TX PMA

Cyclone 10 Transceiver Native PHY

Serializer

tx_serial_data

tx_serial_clk0 (from TX PLL)

rx_cal_busy

tx_cal_busy

rx_serial_data

rx_is_lockedtodata

rx_is_lockedtoref

rx_cdr_refclk0

tx_datak

tx_parallel_data[7:0]

tx_coreclkin

tx_clkout

unused_tx_parallel_data[118:0]

gmii_tx_ctrl

tx_digitalreset

gmii_tx_d[7:0]

reconfig_clk

reconfig_avmm

reconfig_reset

gmii_tx_clk

tx_clkout

RX PMA

TX Standard PCS

RX Standard PCS

Deserializer

Local Clock

Generation

Block

CDR

rx_datak

rx_parallel_data[7:0]

rx_clkout

rx_coreclkin

rx_errdetect

rx_disperr

rx_runningdisp

rx_patterndetect

rx_syncstatus

rx_rmfifostatus

rx_errdetect

rx_disperr

rx_runningdisp

rx_patterndetect

rx_syncstatus

rx_rmfifostatus (1)

unused_rx_parallel_data[111:0]

gmii_rx_ctrl

rx_digitalreset

rx_analogreset

tx_analogreset

gmii_rx_d[7:0]

gmii_rx_clk

Note:

1. rx_rmfifostatus is not available in the GbE with 1588 configuration.

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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Refer to Select and Instantiate the PHY IP Core on page 17.

2. Select GbE or GbE 1588 from the Transceiver configuration rules list located under Datapath Options, depending on which protocol you are implementing.

3. Use the parameter values in the tables in Native PHY IP Parameter Settings for

GbE and GbE with IEEE 1588v2 on page 95 as a starting point. Or, you can use

the protocol presets described in Transceiver Native PHY Presets. Use the GIGE-1.25 Gbps preset for GbE, and the GIGE-1.25 Gbps 1588 preset for GbE

1588. You can then modify the setting to meet your specific requirements.

4. Click Generate to generate the Native PHY IP core top-level RTL file.

Figure 41. Signals and Ports for Native PHY IP Configured for GbE or GbE with IEEE

1588v2

Generating the IP core creates signals and ports based on your parameter settings.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

5. Instantiate and configure your PLL.

6. Instantiate a transceiver reset controller.

You can use your own reset controller or use the Native PHY Reset Controller IP core.

7. Connect the Native PHY IP to the PLL IP and the reset controller. Use the information in the figure below to connect the ports.

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reset

Pattern

Generator

Pattern

Checker

PLL

Reset

Controller

Cyclone 10

Transceiver

Native

PHY

tx_parallel_data

tx_datak

tx_clkout

pll_ref_clk

reset

tx_serial_clk

pll_locked

pll_powerdown (2)

rx_ready

tx_ready

clk

reset

tx_digitalreset

tx_analogreset

rx_digitalreset

rx_analogreset

rx_is_lockedtodata

rx_parallel_data

rx_datak

rx_clkout

tx_serial_data

rx_serial_data

tx_cal_busy

rx_cal_busy

Note:

1. The pll_cal_busy signal is not available when using the CMU PLL.

2. The pll_powerdown signal is not available separately for user control when using the fPLL. The reset controller handles PLL reset for the fPLL.

pll_cal_busy (1)

rx_cdr_refclk

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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Figure 42. Connection Guidelines for a GbE/GbE with IEEE 1588v2 PHY Design

8. Simulate your design to verify its functionality.

2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2

This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of parameter values.

Table 85. General and Datapath Options

The first two sections of the Native PHY [IP] parameter editor for the Native PHY IP provide a list of general and datapath options to customize the transceiver.

Parameter

Message level for rule violations

Transceiver configuration rules

Transceiver mode

Number of data channels 1 to 12

Data rate

Enable datapath and interface reconfiguration On/Off

Enable simplified data interface On/Off

Send Feedback

Value

error

warning

GbE (for GbE)

GbE 1588 (for GbE with IEEE 1588v2)

TX/RX Duplex

TX Simplex RX Simplex

1250 Mbps

Intel® Cyclone® 10 GX Transceiver PHY User Guide

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

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Table 86. TX PMA Parameters

Parameter Value

TX channel bonding mode Not bonded

TX local clock division factor 1, 2, 4, 8

Number of TX PLL clock inputs per channel 1, 2, 3, 4

Initial TX PLL clock input selection 0 to 3

Enable tx_pma_clkout port On/Off

Enable tx_pma_div_clkout port On/Off

tx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66

Enable tx_pma_elecidle port On/Off

Enable rx_seriallpbken port On/Off

Table 87. RX PMA Parameters

Parameter Value

Number of CDR reference Clocks 1 to 5

Selected CDR reference clock 0 to 4

Selected CDR reference clock frequency

PPM detector threshold 100, 300, 500, 1000

CTLE adaptation mode manual

Enable rx_pma_clkout port On/Off

Enable rx_pma_div_clkout port On/Off

rx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66

Enable rx_pma_iqtxrx_clkout port On/Off

Enable rx_pma_clkslip port On/Off

Enable rx_is_lockedtodata port On/Off

Enable rx_is_lockedtoref port On/Off

Enable rx_set_locktodata and rx_set_locktoref ports On/Off

Enable rx_seriallpbken port On/Off

Enable PRBS verifier control and status ports On/Off

Select legal range defined by the Quartus Prime

software

Table 88. Standard PCS Parameters

Parameters Value

Standard PCS / PMA interface width 10

FPGA fabric / Standard TX PCS interface width 8

FPGA fabric / Standard RX PCS interface width 8

Enable Standard PCS low latency mode Off

TX FIFO mode

Intel® Cyclone® 10 GX Transceiver PHY User Guide

register_fifo (for GbE with IEEE 1588v2)

low latency (for GbE)

continued...

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Parameters Value

RX FIFO mode

Enable tx_std_pcfifo_full port On/Off

Enable tx_std_pcfifo_empty port On/Off

Enable rx_std_pcfifo_full port On/Off

Enable rx_std_pcfifo_empty port On/Off

TX byte serializer mode Disabled

RX byte deserializer mode Disabled

Enable TX 8B/10B encoder On

Enable TX 8B/10B disparity control On/Off

Enable RX 8B/10B decoder On

RX rate match FIFO mode

register_fifo (for GbE with IEEE 1588v2)

low latency (for GbE)

gige (for GbE)

disabled (for GbE with IEEE 1588v2)

0x000ab683 (/K28.5/D2.2/) (for GbE)

RX rate match insert / delete -ve pattern (hex)

0x00000000 (disabled for GbE with IEEE

1588v2)

0x000a257c (/K28.5/D16.2/) (for GbE)

RX rate match insert / delete +ve pattern (hex)

Enable rx_std_rmfifo_full port

Enable rx_std_rmfifo_empty port

Enable TX bit slip Off

Enable tx_std_bitslipboundarysel port On/Off

RX word aligner mode Synchronous state machine

RX word aligner pattern length 7

0x00000000 (disabled for GbE with IEEE

1588v2)

On/Off

(option disabled for GbE with IEEE 1588v2)

On/Off

(option disabled for GbE with IEEE 1588v2)

0x000000000000007c (Comma) (for 7-bit

RX word aligner pattern (hex)

Number of word alignment patterns to achieve sync 3

Number of invalid data words to lose sync 3

Number of valid data words to decrement error count 3

Enable fast sync status reporting for deterministic latency SM On/Off

Enable rx_std_wa_patternalign port Off

Enable rx_std_wa_a1a2size port Off

Enable rx_std_bitslipboundarysel port Off

Enable rx_bitslip port Off

Enable TX bit reversal Off

Enable TX byte reversal Off

aligner pattern length), 0x000000000000017c

(/K28.5/) (for 10-bit aligner pattern length)

continued...

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Parameters Value

Enable TX polarity inversion On/Off

Enable tx_polinv port On/Off

Enable RX bit reversal Off

Enable rx_std_bitrev_ena port Off

Enable RX byte reversal Off

Enable rx_std_byterev_ena port Off

Enable RX polarity inversion On/Off

Enable rx_polinv port On/Off

Enable rx_std_signaldetect port On/Off

All options under PCIe Ports Off

2.6.2. 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants

10GBASE-R PHY is the Ethernet-specific physical layer running at a 10.3125-Gbps data rate as defined in Clause 49 of the IEEE 802.3-2008 specification. Cyclone 10 GX transceivers can implement 10GBASE-R variants like 10GBASE-R with IEEE 1588v2.

The 10GBASE-R parallel data interface is the 10 Gigabit Media Independent Interface (XGMII) that interfaces with the Media Access Control (MAC), which has the optional Reconciliation Sub-layer (RS).

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Application

Presentation

Session

Transport

Network

Data Link

Physical

OSI Reference Model Layers

Higher Layers

LAN

CSMA/CD

LAYERS

Logical Link Control (LLC) or other MAC Client

MAC Control (Optional)

Media Access Control (MAC)

Reconciliation

XGMII

10GBASE-R PCS

MDI

10GBASE-R

PHY

Medium

10GBASE-R

(PCS, PMA, PMD)

PMA

PMD

To 10GBASE-R PHY

(Point-to-Point Link)

MDI: Medium Dependent Interface PCS: Physical Coding Sublayer PHY: Physical Layer Device PMA: Physical Medium Attachment

PMD: Physical Medium Dependent XGMII: 10 GB Media Independent Interface

Legend

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Figure 43. 10GBASE-R PHY as Part of the IEEE802.3-2008 Open System Interconnection

(OSI)

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10GBASE-R is a single-channel protocol that runs independently. You can configure the transceivers to implement 10GBASE-R PHY functionality by using the presets of the Native PHY IP. The complete PCS and PHY solutions can be used to interface with a third-party PHY MAC layer as well.

The following 10GBASE-R variants area available from presets:

• 10GBASE-R

• 10GBASE-R Low Latency

• 10GBASE-R Register Mode

Intel recommends that you use the presets for selecting the suitable 10GBASE-R variants directly if you are configuring through the Native PHY IP core.

Intel® Cyclone® 10 GX Transceiver PHY User Guide

Transmitter Enhanced PCSTransmitter PMA

Receiver PMA

Receiver Enhanced PCS

Gearbox

tx_serial_data

Serializer

Interlaken

Disparity Generator

Scrambler

(self sync) mode

Parallel Clock

PRBS

Generator

PRP

Generator

rx_serial_data

Deserializer

CDR

Descrambler

Interlaken

Disparity Checker

Block

Synchronizer

Interlaken

Frame Sync

Gearbox

PRBS Verifier

Parallel Clock

Serial Clock

Parallel and Serial Clocks

Clock Divider

Parallel and Serial Clocks

Clock Generation Block (CGB)

Serial Clock

Input Reference Clock

ATX PLL

fPLL

CMU PLL

64B/66B Decoder

and RX SM

10GBASE-R

BER Checker

PRP

rx_pma_div_clkout

tx_pma_div_clkout

Verifier

rx_coreclkin

rx_clkout

Enhanced PCS

TX FIFO

(3)

Enhanced PCS

RX FIFO

(4)

Interlaken

Frame Generator

Interlaken

CRC32 Generator

Interlaken

CRC32 Checker

64B/66B Encoder

and TX SM

Data &

Control

RX Data & Control

FPGA Fabric

tx_coreclkin

tx_clkout

10.3125 Gbps

5156.25 MHz (data rate/2) (1)

Notes:

1. Value based on the clock division factor chosen.

2. Value calculated as data rate / PCS-PMA interface width.

3. This block is in Phase Compensation mode for the 10GBASE-R configuration and register mode for the 10GBASE-R with 1588 configuration.

4. This block is in 10GBASE-R mode for the 10GBASE-R configuration and register mode for the 10GBASE-R with 1588 configuration.

@ 257.8125 MHz (2)

64 + 8

@ 156.25 MHz from XGMII

64 + 8

@ 156.25 MHz from XGMII

@ 257.8125 MHz (2)

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

Figure 44. Transceiver Channel Datapath and Clocking for 10GBASE-R

UG-20070 | 2020.05.15

10GBASE-R with IEEE 1588v2

When choosing the 10GBASE-R PHY with IEEE 1588v2 mode preset, the hard TX and RX FIFO are set to register mode. The output clock frequency of tx_clkout and

rx_clkout to the FPGA fabric is based on the PCS-PMA interface width. For example,

if the PCS-PMA interface is 40-bit, tx_clkout and rx_clkout run at 10.3125 Gbps/40-bit = 257.8125 MHz.

The 10GBASE-R PHY with IEEE 1588v2 creates the soft TX phase compensation FIFO and the RX clock compensation FIFO in the FPGA core so that the effective XGMII data is running at 156.25 MHz interfacing with the MAC layer.

The IEEE 1588 Precision Time Protocol (PTP) is supported by the preset of the Cyclone 10 GX transceiver Native PHY that configures 10GBASE-R PHY IP in IEEE-1588v2 mode. PTP is used for precise synchronization of clocks in applications such as:

• Distributed systems in telecommunications

• Power generation and distribution

• Industrial automation

• Robotics

• Data acquisition

• Test equipment

• Measurement

Intel® Cyclone® 10 GX Transceiver PHY User Guide

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Intel Cyclone User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

1. Intel® Cyclone® 10 GX Transceiver PHY Overview

1.1. Device Transceiver Layout

1.1.1. Intel Cyclone 10 GX Device Transceiver Layout

1.1.2. Intel Cyclone 10 GX Device Package Details

1.2. Transceiver PHY Architecture Overview

1.2.1. Transceiver Bank Architecture

1.2.2. PHY Layer Transceiver Components

1.2.2.1. The Transceiver Channel

1.2.3. Transceiver Phase-Locked Loops

1.2.3.1. Advanced Transmit (ATX) PLL

1.2.3.2. Fractional PLL (fPLL)

1.2.3.3. Channel PLL (CMU/CDR PLL)

1.2.4. Clock Generation Block (CGB)

1.3. Calibration

1.4. Intel Cyclone 10 GX Transceiver PHY Overview Revision History

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers

2.1. Transceiver Design IP Blocks

2.2. Transceiver Design Flow

2.2.1. Select and Instantiate the PHY IP Core

2.2.2. Configure the PHY IP Core

2.2.3. Generate the PHY IP Core

2.2.4. Select the PLL IP Core

2.2.5. Configure the PLL IP Core

2.2.6. Generate the PLL IP Core

2.2.7. Reset Controller

2.2.8. Create Reconfiguration Logic

2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller

2.2.10. Connect Datapath

2.2.11. Make Analog Parameter Settings

2.2.12. Compile the Design

2.2.13. Verify Design Functionality

2.3. Cyclone 10 GX Transceiver Protocols and PHY IP Support

2.4. Using the Cyclone 10 GX Transceiver Native PHY IP Core

2.4.1. Presets

2.4.2. General and Datapath Parameters

2.4.3. PMA Parameters

2.4.4. Enhanced PCS Parameters

2.4.5. Standard PCS Parameters

2.4.6. PCS Direct

2.4.7. Dynamic Reconfiguration Parameters

2.4.8. PMA Ports

2.4.9. Enhanced PCS Ports

2.4.9.1. Enhanced PCS TX and RX Control Ports

2.4.10. Standard PCS Ports

2.4.11. IP Core File Locations

2.4.12. Unused Transceiver Channels

2.5. Interlaken

2.5.1. Metaframe Format and Framing Layer Control Word

2.5.2. Interlaken Configuration Clocking and Bonding

2.5.2.1. xN Clock Bonding Scenario

2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine

2.5.2.2.1. TX FIFO Soft Bonding

2.5.2.2.2. RX Multi-lane FIFO Deskew State Machine

2.5.3. How to Implement Interlaken in Cyclone 10 GX Transceivers

2.5.4. Native PHY IP Parameter Settings for Interlaken

2.6. Ethernet

2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2

2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2

2.6.1.1.1. Reset Condition for 8B/10B Encoder in GbE, GbE with IEEE 1588v2

2.6.1.2. Word Alignment for GbE, GbE with IEEE 1588v2

2.6.1.3. 8B/10B Decoding for GbE, GbE with IEEE 1588v2

2.6.1.4. Rate Match FIFO for GbE

2.6.1.5. How to Implement GbE, GbE with IEEE 1588v2 in Intel Cyclone 10 GX Transceivers

2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2

2.6.2. 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants