Intel® 8 Series/C220 Series Chipset
Family Platform Controller Hub
(PCH)
Datasheet
May 2014
328904-003
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®
Intel
Anti-Theft Technology (Intel® AT): No system can provide absolute security under all conditions. Requires an enabled chipset, BIOS, firmware and
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Trusted Execution Technology (Intel® TXT): No computer system can provide absolute security under all conditions. Intel® TXT requires a
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®
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Launched Environment (MLE). Intel TXT also requires the system to contain a TPM v1.s. For more information, visit http://www.intel.com/technology/
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detection of system hang
— Timers to detect improper processor reset
— Supports ability to disable external devices
JTAG
— Boundary Scan for testing during board
manufacturing
Serial Peripheral Interface (SPI)
— Supports up to two SPI devices
— Supports 20 MHz, 33 MHz, and 50 MHz SPI
devices
— NEW: Supports Quad IO Fast Read, Quad
Output Fast Read, Dual IO Fast Read
— NEW: Support for TPM over SPI with the
addition of SPI_CS2# chip select pin
— NEW: Supports Serial Flash Discoverable
Parameter (SFDP)
— Support up to two different erase
granularities
Firmware Hub I/F supports BIOS Memory size
up to 8 MB
Low Pin Count (LPC) I/F
— Supports two Master/DMA devices.
— Support for Security Device (Trusted
Platform Module) connected to LPC
Interrupt Controller
— Supports up to eight legacy interrupt pins
— Supports PCI 2.3 Message Signaled
Interrupts
— Two cascaded 8259 with 15 interrupts
— Integrated IO APIC capability with 24
interrupts
— Supports Processor System Bus interrupt
delivery
1.05 V operation with tolerance up to 3.3 V IO
1.05 V Core Voltage
Integrated Voltage Regulators for select power
rails
GPIO
— Open-Drain, Inversion
—GPIO lock down
Intel
Display
®
Flexible Display Interface
— Analog Display (VGA) Interface
— Side band signals AUX CH, DDC and HPD
— Backlight Control and Panel Power
sequencing signals
Package
— 23 mm x 22 mm FCBGA (Desktop Only)
— 20 mm x 20 mm FCBGA (Mobile Only)
Note: Not all features are available on all PCH SKUs.
§ §
40Datasheet
Introduction
1Introduction
1.1About This Manual
This document is intended for Original Equipment Manufacturers and BIOS vendors
creating products based on the Intel® 8 Series/C220 Series Chipset Family Platform
Controller Hub (PCH) (See Section 1.3 for SKU definitions and supported features).
Note:Throughout this document, Platform Controller Hub (PCH) is used as a general term
and refers to all Intel® 8 Series/C220 Series Chipset Family PCH SKUs, unless
specifically noted otherwise.
Note:Throughout this document, the terms “Desktop” and “Desktop Only” refer to
information that is applicable only to Desktop PCH, unless specifically noted otherwise.
Note:Throughout this document, the terms “Server/Workstation” and “Server/Workstation
Only” refers to information that is applicable only to Server/Workstation PCH, unless
specifically noted otherwise.
Note:Throughout this document, the terms “Mobile” and “Mobile Only” refers to information
that is applicable only to the Mobile PCH, unless specifically noted otherwise.
This manual assumes a working knowledge of the vocabulary and principles of PCI
Express*, USB, AHCI, SATA, Intel
®
High Definition Audio (Intel® HD Audio), SMBus,
ACPI and Low Pin Count (LPC). Although some details of these features are described
within this manual, refer to the individual industry specifications listed in Table 1-1 for
the complete details.
All PCI buses, devices, and functions in this manual are abbreviated using the following
nomenclature; Bus:Device:Function. This manual abbreviates buses as Bn, devices as
Dn and functions as Fn. For example Device 31 Function 0 is abbreviated as D31:F0,
Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will
not be used, and can be considered to be Bus 0.
Table 1-1.Industry Specifications (Sheet 1 of 2)
SpecificationLocation
PCI Express* Base Specification, Revision 2.0http://www.pcisig.com/specifications
Chapter 1 introduces the PCH, provides information on the organization of the manual
and gives a general overview of the PCH.
Chapter 2, “Signal Description”
Chapter 2 provides a block diagram of the PCH and a detailed description of each
signal. Signals are arranged according to interface and details are provided as to the
drive characteristics (Input/Output, Open Drain, and so on) of all signals.
Chapter 3, “PCH Pin States”
Chapter 3 provides a complete list of signals, their associated power well, their logic
level in each suspend state, and their logic level before and after reset.
Chapter 4, “PCH and System Clocks”
Chapter 4 provides a list of each clock domain associated with the PCH.
Chapter 5, “Functional Description”
Chapter 5 provides a detailed description of the functions in the PCH.
Chapter 6, “Ballout Definition”
Chapter 6 provides the ball assignment table and the ball-map for the Desktop and
Mobile packages.
Chapter 7, “Package Information”
Chapter 7 provides drawings of the physical dimensions and characteristics of the
Desktop and Mobile packages.
42
Chapter 8, “Electrical Characteristics”
Chapter 8 provides all AC and DC characteristics including detailed timing diagrams.
Datasheet
Introduction
Chapter 9, “Register and Memory Mapping”
Chapter 9 provides an overview of the registers, fixed I/O ranges, variable I/O ranges
and memory ranges decoded by the PCH.
Chapter 10, “Chipset Configuration Registers”
Chapter 10 provides a detailed description of registers and base functionality that is
related to chipset configuration. It contains the root complex register block, which
describes the behavior of the upstream internal link.
Chapter 11, “Gigabit LAN Configuration Registers”
Chapter 11 provides a detailed description of registers that reside in the PCH’s
integrated LAN controller. The integrated LAN Controller resides at Device 25,
Function 0 (D25:F0).
Chapter 12 provides a detailed description of registers that reside in the LPC bridge.
This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers
for many different units within the PCH including DMA, Timers, Interrupts, Processor
Interface, GPIO, Power Management, System Management and RTC.
Chapter 13, “SATA Controller Registers (D31:F2)”
Chapter 13 provides a detailed description of registers that reside in the SATA
controller #1. This controller resides at Device 31, Function 2 (D31:F2).
Chapter 23 provides a detailed description of registers that reside in the Intel ME
controller. The registers reside at Device 22, Function 0 (D22:F0).
1.2Overview
The PCH provides extensive I/O support. Functions and capabilities include:
• PCI Express* Base Specification, Revision 2.0 support for up to eight ports with
transfers up to 5 GT/s
• ACPI Power Management Logic Support, Revision 4.0a
• Enhanced DMA controller, interrupt controller, and timer functions
• Integrated Serial ATA host controllers with independent DMA operation on up to six
ports
• xHCI USB controller provides support for up to 14 USB ports, of which six can be
configured as SuperSpeed USB 3.0 ports.
• Two legacy EHCI USB controllers each provides a USB debug port.
• Flexible I/O, A new architecture to allow some high speed I/O signals to be
configured as PCIe, SATA or USB 3.0.
• Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense
• System Management Bus (SMBus) Specification, Version 2.0 with additional
support for I
•Supports Intel
•Supports Intel
•Supports Intel® Active Management Technology (Intel® AMT)
•Supports Intel
•Supports Intel
• Integrated Clock Controller
•Intel
•Analog VGA Display Interface
• Low Pin Count (LPC) interface
• Firmware Hub (FWH) interface support
• Serial Peripheral Interface (SPI) support
•Intel
•JTAG Boundary Scan support
®
Flexible Display Interface (Intel® FDI)
®
Anti-Theft Technology (Intel® AT)
2
C devices
®
High Definition Audio (Intel® HD Audio)
®
Rapid Storage Technology (Intel® RST)
®
Virtualization Technology for Directed I/O (Intel® VT-d)
®
Trusted Execution Technology (Intel® TXT)
Introduction
Note:Not all functions and capabilities may be available on all SKUs. See Section 1.3 for
details on SKU feature availability.
44
Datasheet
Introduction
1.2.1Capability Overview
The following sub-sections provide an overview of the PCH capabilities.
Direct Media Interface (DMI)
Direct Media Interface (DMI) is the chip-to-chip connection between the processor and
PCH. This high-speed interface integrates advanced priority-based servicing allowing
for concurrent traffic and true isochronous transfer capabilities. Base functionality is
completely software-transparent, permitting current and legacy software to operate
normally.
®
Intel
Intel FDI connects the display engine in the processor with the Analog display interface
on the PCH. The display data for Analog VGA panels from the frame buffer is processed
by the display engine and sent to the PCH through Intel FDI. Intel FDI has two lanes for
display data transfer to the PCH from the processor. Each Intel FDI lane consists of two
differential signal receive pairs supporting a data rate of 2.7 Gb/s.
PCH Display Interface
Flexible Display Interface (Intel® FDI)
The Analog VGA display interface is the only display interface supported on the PCH.
This interface is used to drive legacy CRT panels and advanced LCD VGA panels. The
analog VGA display interface has an integrated RAMDAC 180 MHz, driving a standard
progressive scan analog monitor to a resolution of up to 1920x2000 pixels and 24-bit
color at a 60 Hz refresh rate with reduced blanking.
Analog VGA display interface is in the PCH, although the main display engine is in the
processor. Thus, the Intel FDI is used to send the display data to the PCH. Intel FDI is a
bus that connects the processor and PCH display components. The PCH, upon receiving
the display data, transcodes the data as per the display technology protocol and sends
the data through the DAC to display panel.
The PCH integrates digital display side band signals, even though digital display
interfaces are in the processor. There are three pairs of AUX CH, DDC Clock/Data, and
Hot-Plug Detect Signals on the PCH that correspond to digital display interface/ports B,
C, and D.
The PCH also integrates panel backlight control signals, which are used only when
Embedded DisplayPort* (eDP) is configured on the platform.
PCI Express* Interface
The PCH provides up to 8 PCI Express Root Ports, supporting the PCI Express Base
Specification, Revision 2.0. Each Root Port x1 lane supports up to 5 Gb/s bandwidth in
each direction (10 Gb/s concurrent). PCI Express Root Ports 1–4 or Ports 5–8 can
independently be configured to support multiple port width configurations. See
Section 1.3 for details on feature availability.
Datasheet45
Introduction
Serial ATA (SATA) Controller
The PCH has two integrated SATA host controllers that support independent DMA
operation on up to six ports and support data transfer rates of up to 6.0 Gb/s on all
ports. The SATA controller contains two modes of operation – a legacy mode using I/O
space, and an AHCI mode using memory space. Software that uses legacy mode will
not have AHCI capabilities.
The PCH supports the Serial ATA Specification, Revision 3.0. The PCH also supports
several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification,
Revision 1.0 (AHCI support is required for some elements).
See Section 1.3 for details on feature availability.
Advanced Host Controller Interface (AHCI)
The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a
standardized programming interface for SATA host controllers. Platforms supporting
AHCI may take advantage of performance features such as no master/slave
designation for SATA devices – each device is treated as a master – and hardwareassisted native command queuing. AHCI also provides usability enhancements, such as
Hot-Plug. AHCI requires appropriate software support (such as, an AHCI driver) and for
some features, hardware support in the SATA device or additional platform hardware.
See Section 1.3 for details on SKU feature availability.
®
Intel
Rapid Storage Technology (Intel® RST)
The PCH provides support for Intel Rapid Storage Technology (Intel RST), providing
both AHCI (see above for details on AHCI) and integrated RAID functionality. The RAID
capability provides high-performance RAID 0, 1, 5, and 10 functionality on up to 6
SATA ports of the PCH. Matrix RAID support is provided to allow multiple RAID levels to
be combined on a single set of hard drives, such as RAID 0 and RAID 1 on two disks.
Other RAID features include hot spare support, SMART alerting, and RAID 0 auto
replace. Software components include an Option ROM for pre-boot configuration and
boot functionality, a Microsoft* Windows* compatible driver, and a user interface for
configuration and management of the RAID capability of PCH. See Section 1.3 for
details on SKU feature availability.
®
Intel
Smart Response Technology
Intel Smart Response Technology is a disk caching solution that can provide improved
computer system performance with improved power savings. It allows configuration of
a computer system with the advantage of having HDDs for maximum storage capacity
with system performance at or near SSD performance levels. See Section 1.3 for
details on SKU feature availability.
Low Pin Count (LPC) Interface
The PCH implements an LPC Interface as described in the LPC 1.1 Specification. The
Low Pin Count (LPC) bridge function of the PCH is mapped as PCI D31:F0 and supports
a memory size up to 8 MB, two master/DMA devices, interrupt controllers, timers,
power management, system management, Super I/O, and RTC.
46
Datasheet
Introduction
Serial Peripheral Interface (SPI)
In addition to the standard Dual Output Fast Read mode, the SPI interface in the PCH
supports new Dual I/O Fast Read, Quad I/O Fast Read and Quad Output Fast Read. To
enable the new Quad I/O operation modes, all data transfer signals in the interface are
bidirectional and two new signals (SPI_IO2 and SPI_IO3) have been added to the basic
four-wire interface: Clock, Master Out Slave In (MOSI), Master In Slave Out (MISO)
and active-low chip selects (CS#). The PCH supports three chip selects: SPI_CS0# and
SPI_CS1# are used to access two separate SPI Flash components in Descriptor Mode.
SPI_CS2# is dedicated only to support Trusted Platform Module (TPM) on SPI (TPM can
be configured through PCH soft straps to operate over LPC or SPI, but no more than
1 TPM is allowed in the system). SPI_CS2# may not be used for any purpose other
than TPM.
The SPI Flash Controller supports running instructions at 20 MHz, 33 MHz, and 50 MHz,
and can be used by the PCH for BIOS code, to provide chipset configuration settings,
internal micro-processor code, integrated Gigabit Ethernet MAC/PHY configuration, and
Intel Active Management Technology (Intel
®
AMT) settings. The SPI Flash Controller
supports the Serial Flash Discoverable Parameter (SFDP) JEDEC standard that provides
a consistent way of describing the functional and feature capabilities of serial flash
devices in a standard set of internal parameter tables. The SPI Flash Controller queries
these parameter tables to discover the attributes to enable divergent features from
multiple SPI part vendors, such as Quad I/O Fast Read capabilities or device storage
capacity, among others.
The DMA controller incorporates the logic of two 8237 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-bybyte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any
two of the seven DMA channels can be programmed to support fast Type-F transfers.
Channel 4 is reserved as a generic bus master request.
The PCH supports LPC DMA, which is similar to ISA DMA, through the PCH DMA
controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals
and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and
Increment modes are supported on the LPC interface.
The timer/counter block contains three counters that are equivalent in function to those
found in one 8254 programmable interval timer. These three counters are combined to
provide the system timer function, and speaker tone. The 14.318 MHz oscillator input
provides the clock source for these three counters.
The PCH provides an ISA-compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two 8259 interrupt controllers. The two interrupt
controllers are cascaded so that 14 external and two internal interrupts are possible. In
addition, the PCH supports a serial interrupt scheme.
All of the registers in these modules can be read and restored. This is required to save
and restore system state after power has been removed and restored to the platform.
Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA-compatible Programmable Interrupt controller (PIC)
described in the previous section, the PCH incorporates the Advanced Programmable
Interrupt Controller (APIC).
Datasheet47
Introduction
Universal Serial Bus (USB) Controllers
The PCH contains one eXtensible Host Controller Interface (xHCI) controller and two
Enhanced Host Controller Interface (EHCI) controllers. The xHCI controller is mapped
as PCI D20:F0 and it supports up to 14 USB 2.0 ports of which 6 can be configured as
SuperSpeed (USB 3.0) ports.
EHCI controller 1 (EHCI1) is located at D29:F0 and it supports up to 8 USB 2.0 ports.
EHCI controller 2 (EHCI2) is located at D26:F0 and it supports up to 6 USB 2.0 ports.
One of the USB 2.0 ports in either EHCI controller can be used for a Debug Port (not
available through xHCI).
Note:USB 2.0 differential pairs are numbered starting with 0. USB 3.0 differential pairs are
numbered starting with 1.
Note:Regarding the optional USB Battery Charging Specification 1.x: Intel does not have a
topology for Intel
®
8 Series/C220 Series Chipset Family based platforms that can
accommodate USB battery charging circuits robustly across the large install base of
USB cables and High Speed (HS) devices. As such, Intel does not recommend that
platforms exceed native supply currents defined in the USB specification for USB 2.0
ports.
See Section 1.3 for details on feature availability.
Flexible I/O
The PCH implements Flexible I/O, an architecture to allow some high speed signals to
be configured as SATA, USB 3.0, or PCIe signals. Through soft straps, the functionality
on these multiplexed signals are selected to meet the I/O needs on the platform. See
Section 5.22 for details on Flexible I/O.
Gigabit Ethernet Controller
The Gigabit Ethernet Controller provides a system interface using a PCI function. The
controller provides a full memory-mapped or I/O mapped interface along with a 64-bit
address master support for systems using more than 4 GB of physical memory and
DMA (Direct Memory Addressing) mechanisms for high performance data transfers. Its
bus master capabilities enable the component to process high-level commands and
perform multiple operations. This lowers processor utilization by off-loading
communication tasks from the processor. Two large configurable transmit and receive
FIFOs (up to 20 KB each) help prevent data underruns and overruns while waiting for
bus accesses. This enables the integrated LAN controller to transmit data with
minimum interframe spacing (IFS).
48
The LAN controller can operate at multiple speeds (10/100/1000 MB/s) and in either
full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the
IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a
proprietary collision reduction mechanism. See Section 5.4 for details.
Real Time Clock (RTC)
The PCH contains a Motorola MC146818B-compatible real-time clock with 256 bytes of
battery-backed RAM. The real-time clock performs two key functions – keeping track of
the time of day and storing system data, even when the system is powered down. The
RTC operates on a 32.768-kHz crystal and a 3-V battery.
Datasheet
Introduction
The RTC also supports two lockable memory ranges. By setting bits in the configuration
space, two 8-byte ranges can be locked to read and write accesses. This prevents
unauthorized reading of passwords or other system security information.
The RTC also supports a date alarm that allows for scheduling a wake up event up to
30 days in advance, rather than just 24 hours in advance.
General Purpose I/O (GPIO)
Various general purpose inputs and outputs are provided for custom system design.
The number of inputs and outputs varies depending on PCH configuration.
Enhanced Power Management
The PCH’s power management functions fully support the Advanced Configuration and
Power Interface (ACPI) Specification, Revision 4.0a, and include enhanced clock control
and various low-power (suspend) states (such as Suspend-to-RAM and Suspend-toDisk). A hardware-based thermal management circuit permits software-independent
entrance to low-power states.
®
Intel
Intel
Active Management Technology (Intel® AMT)
®
AMT is a fundamental component of Intel® vPro™ technology. Intel AMT is a set
of advanced manageability features developed as a direct result of IT customer
feedBack gained through Intel market research. With the advent of powerful tools like
the Intel System Defense Utility, the extensive feature set of Intel AMT easily integrates
into any network environment. See Section 1.3 for details on SKU feature availability.
Manageability
®
In addition to Intel
AMT, the PCH integrates several functions designed to manage the
system and lower the total cost of ownership (TCO) of the system. These system
management functions are designed to report errors, diagnose the system, and recover
from system lockups without the aid of an external microcontroller.
• TCO Timer. The PCH’s integrated programmable TCO timer is used to detect
system locks. The first expiration of the timer generates an SMI# that the system
can use to recover from a software lock. The second expiration of the timer causes
a system reset to recover from a hardware lock.
• Processor Present Indicator. The PCH looks for the processor to fetch the first
instruction after reset. If the processor does not fetch the first instruction, the PCH
will reboot the system.
• ECC Error Reporting. When detecting an ECC error, the host controller has the
ability to send one of several messages to the PCH. The host controller can instruct
the PCH to generate either an SMI#, NMI, SERR#, or TCO interrupt.
• Function Disable. The PCH provides the ability to disable the following integrated
functions: LAN, USB, LPC, Intel
HD Audio, SATA, PCI Express* or SMBus. Once
disabled, these functions no longer decode I/O, memory, or PCI configuration
space. Also, no interrupts or power management events are generated from the
disabled functions.
• Intruder Detect. The PCH provides an input signal (INTRUDER#) that can be used
to inform the system in the event of the case being opened. The PCH can be
programmed to generate an SMI# or TCO interrupt due to an active INTRUDER#
signal.
Datasheet49
System Management Bus (SMBus 2.0)
Introduction
The PCH contains an SMBus Host interface that allows the processor to communicate
with SMBus slaves. This interface is compatible with most I
2
C devices. Special I2C
commands are implemented.
The PCH SMBus host controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves). Also, the PCH supports slave
functionality, including the Host Notify protocol. Hence, the host controller supports
eight command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, version 2.0): Quick Command, Send Byte, Receive Byte, Write
Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.
The PCH SMBus also implements hardware-based Packet Error Checking for data
robustness and the Address Resolution Protocol (ARP) to dynamically provide
addresses to all SMBus devices.
®
Intel
High Definition Audio (Intel® HD Audio) Controller
The Intel HD Audio controller is a PCI Express* device, configured as D27:F0. The PCH
Intel HD Audio controller supports up to 4 codecs, such as audio and modem codecs.
The link can operate at either 3.3 V or 1.5 V.
With the support of multi-channel audio stream, 32-bit sample depth, and sample rate
up to 192 kHz, the Intel HD Audio controller provides audio quality that can deliver
Consumer Electronics (such as home audio components, portable audio devices,
Bluetooth* speakers, and so on) levels of audio experience. On the input side, the PCH
adds support for an array of microphones.
®
Intel
Virtualization Technology for Directed I/O (Intel® VT-d)
The PCH provides hardware support for implementation of Intel Virtualization
Technology with Directed I/O (Intel VT-d). Intel
components that support the virtualization of platforms based on Intel Architecture
processors. Intel
VT-d Technology enables multiple operating systems and applications
VT-d Technology consists of technology
to run in independent partitions. A partition behaves like a virtual machine (VM) and
provides isolation and protection across partitions. Each partition is allocated its own
subset of host physical memory.
Joint Test Action Group (JTAG) Boundary-Scan
The PCH implements the industry standard JTAG interface and enables Boundary-Scan.
Boundary-Scan can be used to ensure device connectivity during the board
manufacturing process. The JTAG interface allows system manufacturers to improve
efficiency by using industry available tools to test the PCH on an assembled board.
Since JTAG is a serial interface, it eliminates the need to create probe points for every
pin in an XOR chain. This eases pin breakout and trace routing and simplifies the
interface between the system and a bed-of-nails tester.
Note:The TRST# JTAG signal is an optional signal in the IEEE* 1149 JTAG Specification and is
not implemented in the PCH.
Integrated Clock Controller
The PCH contains an Integrated Clock Controller (ICC) that generates various platform
clocks from a 25 MHz crystal source. The ICC contains PLLs, Modulators, and Dividers
for generating various clocks suited to the platform needs. The ICC supplies up to eight
50
Datasheet
Introduction
100 MHz PCI Express 2.0 Specification compliant clocks, one 100 MHz PCI Express* 3.0
Specification compliant clock for BCLK/DMI, two 100 MHz PCI Express 3.0 Specification
compliant clocks for PEG slots, one 100 MHz PCI Express 3.0 Specification compliant
clock for ITP or a third PEG slot, two 135 MHz differential output clocks for DisplayPort
on the processor, five 33 MHz PCI 2.3 Local Bus Specification compliant single-ended
clocks for LPC/TPM devices and four Flex Clocks that can be configured to various
frequencies that include 14.318 MHz, 33 MHz, and 24/48 MHz for use with SIO, TPM,
EC, LPC, and any other legacy functions.
Serial Over LAN (SOL) Function
This function supports redirection of keyboard and text screens to a terminal window
on a remote console. The keyboard and text redirection enables the control of the client
machine through the network without the need to be physically near that machine. Text
and keyboard redirection allows the remote machine to control and configure a client
system. The SOL function emulates a standard PCI device and redirects the data from
the serial port to the management console using the integrated LAN.
®
Intel
Intel
addition to the features set provided by SOL, Intel KVM technology provides mouse and
graphic redirection across the integrated LAN. Unlike SOL, Intel
KVM Technology
KVM technology provides enhanced capabilities to its predecessor – SOL. In
KVM technology does
not appear as a host accessible PCI device, but is instead almost completely performed
by Intel® AMT Firmware with minimal BIOS interaction. The Intel KVM technology
feature is only available with internal graphics.
IDE-R Function
The IDE-R function is an IDE Redirection interface that provides client connection to
management console ATA/ATAPI devices, such as hard disk drives and optical disk
drives. A remote machine can setup a diagnostic software or operating system
installation image and direct the client to boot an IDE-R session. The IDE-R interface is
the same as the IDE interface; although, the device is not physically connected to the
system and supports the ATA/ATAPI-6 specification. IDE-R does not conflict with any
other type of boot and can, instead, be implemented as a boot device option. The
®
AMT solution will use IDE-R when remote boot is required. The device attached
Intel
through IDE-R is only visible to software during a management boot session. During
normal boot session, the IDE-R controller does not appear as a PCI present device.
Datasheet51
Introduction
1.3Intel® 8 Series/C220 Series Chipset Family PCH
SKU Definition
Table 1-2.Desktop Intel® 8 Series Chipset Family SKUs
SKU Name
®
Feature Set
Intel
Q87
Express
Chipset
Intel®
Q85
Express
Chipset
Flexible I/OYesNo NoYesYesNo
PCI Express* 2.0 Ports8
4
88848
Total number of USB ports141412
• USB 3.0 Capable Ports (SuperSpeed and all USB 2.0
4(6)
7
444(6)
speeds)
• USB 2.0 Only Ports10(8)
Total number of SATA ports4(6)
• SATA Ports (6 Gb/s, 3 Gb/s, and 1.5 Gb/s) 64
9
10810(8)
10
664(6)
12
•SATA Ports (3 Gb/s and 1.5 Gb/s only)022002
VGAYesYesYesYesYesYes
Intel® Wireless Display (WiDi)YesYesYesYesYesYes
Intel® Rapid Storage
Technolo g y
Intel® Anti-Theft Technology
AHCIYesYesYesYesYes No
RAID 0/1/5/10 SupportYesNo NoYesYesNo
Intel® Smart Response
Technology
15
14
YesNo NoYesYesNo
YesYesYesYesYesYes
Intel® Active Management Technology 9.0YesNoNoNoNoNo
1.Contact your local Intel Field Sales Representative for currently available PCH SKUs.
2.Table above shows feature differences between the PCH SKUs. If a feature is not listed in the table it is
considered a Base feature that is included in all SKUs.
3.PCI Legacy Mode may optionally be used allowing external PCI bus support through a PCIe-to-PCI bridge.
See Section 5.2.2 for more details.
4.The number of PCI Express ports available depends on the Flexible I/O configuration. See Section 2.1 and
Tab l e 1 -3 .
Datasheet
Introduction
5.USB 2.0 ports 6 and 7 are disabled on 12 port SKUs.
6.USB 2.0 ports 6,7,12 and 13 are disabled on 10 port SKUs.
7.6 USB 3.0 ports requires High Speed I/O ports 5 and 6 to be configured as USB 3.0. See Section 2.1 and
Tab l e 1 -3 .
8.Only USB 3.0 ports 1 and 2 are enabled.
9.When Flexible I/O ports are configured as USB 3.0, the total number of USB 2.0 only ports reduces in direct
proportion.
10. 6 SATA ports requires High Speed I/O ports 13 and 14 to be configured as SATA. See Section 2.1 and
Tab l e 1 -3 .
11. SATA ports 2 and 3 are disabled on 4 port SKUs.
12. SATA 6 Gb/s support on ports 0,1,2 and 3. SATA ports 0,1,2 and 3 also support 3 Gb/s and 1.5 Gb/s.
13. SATA 6 Gb/s support on ports 0 and 1 only. SATA ports 0 and 1 also support 3 Gb/s and 1.5 Gb/s.
14. Intel
15. Intel
16. Intel
17. Intel
18. Intel
19. Intel
20. Near Field Communication is only supported in All-in-One system designs.
21. Refer to the processor datasheet for additional details on processor features.
®
Smart Response Technology requires an Intel® Core™ processor.
®
Anti-Theft Technology requires an Intel® Core™ processor.
®
Small Business Advantage requires an Intel® Core™ processor.
®
Small Business Advantage with the Intel® H87 Express Chipset requires 5Mb firmware.
®
Rapid Start Technology requires an Intel® Core™ processor.
®
Identity Protection Technology requires an Intel® Core™ processor.
Table 1-3.Intel® 8 Series/C220 Series Chipset Family PCH SKUs Flexible I/O Map
Processor Maximum Number of Independent Displays Supported332
Processor Maximum Number of Memory Channels (Maximum DIMMS per Channel)2 (2)2 (2)2 (1)
Processor and Memory Overclocking
19
DisabledDisabledDisabled
Processor GraphicsEnabledEnabledEnabled
Notes:
1.Contact your local Intel Field Sales Representative for currently available PCH SKUs.
2.Table above shows feature difference between the PCH SKUs. If a feature is not listed in the table, it is
considered a Base feature that is included in all SKUs.
3.PCI Legacy Mode may optionally be used allowing external PCI bus support through a PCIe-to-PCI bridge.
See Section 5.2.2 for more details.
4.Flexible I/O is only available on High Speed I/O ports 5 and 6 which are shared between USB 3.0 and PCI
Express. High Speed I/O ports 13 and 14 are fixed as SATA Gen 2 ports. See Section 2.1 and Ta b l e 1 -5 .
5.The number of PCI Express ports available depends on the Flexible I/O configuration. See Section 2.1 and
Tab l e 1 -5 .
6.6 USB 3.0 ports requires High Speed I/O ports 5 and 6 to be configured as USB 3.0. See Section 2.1 and
Tab l e 1 -5 .
7.USB 3.0 ports 5 and 6 are disabled on the Intel
8.When Flexible I/O ports are configured as USB 3.0, the total number of USB 2.0 only ports reduces in direct
proportion.
9.6 SATA ports requires High Speed I/O ports 13 and 14 to be configured as SATA. See Section 2.1 and
Tab l e 1 -5 .
10. SATA ports 1 and 3 are disabled on 4 port SKUs.
11. SATA 6 Gb/s support on ports 0,1,4 and 5. SATA ports 0,1,4 and 5 also support 3 Gb/s and 1.5 Gb/s. In
order to support 4 SATA 6 Gb/s ports, High Speed I/O ports 13 and 14 must be configured as SATA. See
Section 2.1 and Tab l e 1 - 5.
12. SATA 6 Gb/s support on port 4 and port 5. SATA ports 4 and 5 also support 3 Gb/s and 1.5 Gb/s.
13. Intel
®
Smart Response Technology requires an Intel® Core™ processor.
®
HM86 Express Chipset.
6
9
11
®
8
Express
Mobile
Intel®
HM87
Chipset
5
8
4(6)2(4)
8
10(8)
9
4(6)
11
2(4)
16
Gen 3
(8GT/s)
Mobile
Intel®
HM86
Express
Chipset
5
8
12(10)
10
4
12
2
No
Gen 2
(5GT/s)
4
7
8
54
Datasheet
Introduction
14. Intel
15. Intel
16. Intel
17. Intel
18. Intel
®
Anti-Theft Technology requires an Intel® Core™ processor.
®
Small Business Advantage requires an Intel® Core™ processor.
®
Small Business Advantage with the Intel® HM87 Express Chipset requires 5Mb firmware.
®
Rapid Start Technology requires an Intel® Core™ processor.
®
Identity Protection Technology requires an Intel® Core™ processor.
19. Refer to the processor datasheet for additional details on processor features.
Table 1-5.Intel® 8 Series/C220 Series Chipset Family PCH SKUs Flexible I/O Map
Table 1-6.Server / Workstation Intel® C220 Series Chipset Family SKUs (Sheet 2 of 2)
SKU Name
Feature Set
Processor Features Controlled by PCH SKU
17
Processor PEG Port Bifurcation1x16,
Processor PEG Port Maximum Speed AllowedGen 3
Processor Maximum Number of Independent Displays Supported333
Processor Maximum Number of Memory Channels (Maximum DIMMS per Channel)2 (2)2 (2)2 (2)
Processor and Memory OverclockingDisabledDisabledDisabled
Processor GraphicsDisabledDisabledEnabled
Notes:
1.Contact your local Intel Field Sales Representative for currently available PCH SKUs.
2.Table above shows feature differences between the PCH SKUs. If a feature is not listed in the table, it is
considered a Base feature that is included in all SKUs
3.PCI Legacy Mode may optionally be used allowing external PCI bus support through a PCIe-to-PCI bridge.
See Section 5.2.2 for more details.
4.The number of PCI Express ports available depends on the Flexible I/O configuration. See Section 2.1 and
Tab l e 1 -7 .
5.USB 2.0 ports 6,7,12 and 13 are disabled on 10 port SKUs.
6.USB 2.0 ports 6 and 7 are disabled on 12 port SKUs.
7.Only USB 3.0 ports 1 and 2 are enabled.
8.Only USB 3.0 ports 1,2,5 and 6 are enabled.
9.6 USB 3.0 ports require High Speed I/O ports 5 and 6 to be configured as USB 3.0. See Section 2.1 and
Tab l e 1 -7 .
10. When Flexible I/O ports are configured as USB 3.0, the total number of USB 2.0 only ports reduces in direct
proportion.
11. 6 SATA ports require High Speed I/O ports 13 and 14 to be configured as SATA. See Section 2.1 and
Tab l e 1 -7 .
12. SATA 6 Gb/s support on ports 0 and 1 only. SATA ports 0 and 1 also support 3 Gb/s and 1.5 Gb/s.
13. SATA 6 Gb/s support on ports 0,1,2 and 3. SATA ports 0,1,2 and 3 also support 3 Gb/s and 1.5 Gb/s.
14. Intel
15. Intel
16. Intel
17. Refer to the processor datasheet for additional details on processor features.
®
Smart Response Technology requires an Intel® Core™ processor.
®
Anti-Theft Technology requires an Intel® Core™ processor.
®
Identity Protection Technology requires an Intel® Xeon® processor.
Intel®
C222
Chipset
2x8, 1x8,
2x4
(8GT/s)
Intel®
C224
Chipset
1x16,
2x8, 1x8,
2x4
Gen 3
(8GT/s)
Intel®
C226
Chipset
1x16,
2x8, 1x8,
2x4
Gen 3
(8GT/s)
Table 1-7.Server / Workstation Intel® C220 Series Chipset Family SKUs Flexible I/O
1.Ports listed with NA are not available and are disabled.
PCIe*
Port 5
PCIe*
Port 5
PCIe*
Port 5
PCIe*
Port 6
PCIe*
Port 6
PCIe*
Port 6
PCIe*
Port 7
PCIe*
Port 7
PCIe*
Port 7
PCIe*
Port 8
PCIe*
Port 8
PCIe*
Port 8
SATA
3Gb/s
Port 4
SATA
3Gb/s
Port 4
SATA
6Gb/s
Port 4
PCIe*
Port 1
SATA
3Gb/s
Port 5
SATA
3Gb/s
Port 5
SATA
6Gb/s
Port 5
PCIe*
Port 2
SATA
6Gb/s
Port 0
SATA
6Gb/s
Port 0
SATA
6Gb/s
Port 0
SATA
6Gb/s
Port 1
SATA
6Gb/s
Port 1
SATA
6Gb/s
Port 1
Datasheet
SATA
3Gb/s
Port 2
SATA
6Gb/s
Port 2
SATA
6Gb/s
Port 2
18
SATA
3Gb/s
Port 3
SATA
6Gb/s
Port 3
SATA
6Gb/s
Port 3
Introduction
1.4Device and Revision ID Table
The Revision ID (RID) register is an 8-bit register located at offset 08h in the PCI
header of every PCI/PCIe function. The RID register is used by software to identify a
particular component stepping when a driver change or patch unique to that stepping is
needed.
Table 1-8.PCH Device and Revision ID Table (Sheet 1 of 3)
Device
Function
D31:F2SATA
D31:F5SATA8C08h04hDesktop: Non-AHCI and Non-RAID Mode
D28:F0PCI
D28:F1PCI
D28:F2PCI
D28:F3PCI
Descrip-
tion
1
Express*
Port 1
Express
Port 2
Express
Port 3
Express
Port 4
Dev ID
8C00h04hDesktop: Non-AHCI and Non-RAID Mode.
8C01h04hMobile: Non-AHCI and Non-RAID Mode.
8C02h04hDesktop: AHCI Mode.
8C03h04hMobile: AHCI Mode.
8C04h04hDesktop: RAID Capable
2822h04hDesktop: RAID Capable
8C05h04hMobile: RAID Capable
282Ah04hMobile: RAID Capable
8C06h04hDesktop: RAID Capable
2826h04hServer/Workstation: RAID Capable
8C07h04hMobile: RAID Capable
8C0Eh04hDesktop: RAID 1 Only.
8C0Fh04hMobile: RAID 1 Only.
8C09h04hMobile: Non-AHCI and Non-RAID Mode
8C10h04hDesktop and Mobile (When D28:F0:ECh:bit 1= 0)
244Eh04hDesktop (When D28:F0:ECh:bit 1 = 1)
2448h04hMobile (When D28:F0:ECh:bit 1 = 1)
8C12h04hDesktop and Mobile (When D28:F1:ECh:bit 1 = 0)
244Eh04hDesktop (When D28:F1:ECh:bit 1 = 1)
2448h04hMobile (When D28:F1:ECh:bit 1 = 1)
8C14h04hDesktop and Mobile (When D28:F2:ECh:bit 1 = 0)
244Eh04hDesktop (When D28:F2:ECh:bit 1 = 1)
2448h04hMobile (When D28:F2:ECh:bit 1 = 1)
8C16h04hDesktop and Mobile (When D28:F3:ECh:bit 1 = 0)
244Eh04hDesktop (When D28:F3:ECh:bit 1 = 1)
2448h04hMobile (When D28:F3:ECh:bit 1 = 1)
C1
SRID
Technology, if AIE (D31:F2 Offset 9Ch bit 7) = 0 AND AIES
(D31:F2 Offset 9Ch bit 6) = 0.
Technology, if AIE (D31:F2 Offset 9Ch bit 7) = 0.
if AIE (D31:F2 Offset 9Ch bit 7) = 1.
Technology, if AIE (D31:F2 Offset 9Ch bit 7) = 0 AND AIES
(D31:F2 Offset 9Ch bit 6) = 1.
AIE (D31:F2 Offset 9Ch bit 7) = 1.
(Ports 4 and 5)
(Ports 4 and 5)
Comments
3
if AIE (D31:F2 Offset 9Ch bit 7) = 1.
3
with or without Intel® Smart Response
3
if AIE (D31:F2 Offset 9Ch bit 7) = 1.
3
with or without Intel® Smart Response
3
and Intel® Smart Response Technology,
3
and Intel® Smart Response
3
and Intel® Smart Response Technology, if
Datasheet57
Table 1-8.PCH Device and Revision ID Table (Sheet 2 of 3)
Introduction
Device
Function
D28:F4PCI
D28:F5PCI
D28:F6PCI
D28:F7PCI
D27:F0Intel
D31:F3SMBus8C22h04hDesktop and Mobile - All SKUs.
D31:F6Thermal8C24h04hDesktop and Mobile - All SKUs.
D29:F0USB EHCI #18C26h04hDesktop and Mobile - All SKUs.
D26:F0USB EHCI #28C2Dh04hDesktop and Mobile - All SKUs.
Descrip-
tion
Express
Port 5
Express
Port 6
Express
Port 7
Express
Port 8
®
High
Definition
Audio
Dev ID
8C18h04hDesktop and Mobile (When D28:F4:ECh:bit 1 = 0)
244Eh04hDesktop (When D28:F4:ECh:bit 1 = 1)
2448h04hMobile (When D28:F4:ECh:bit 1 = 1)
8C1Ah04hDesktop and Mobile (When D28:F5:ECh:bit 1 = 0)
244Eh04hDesktop (When D28:F5:ECh:bit 1 = 1)
2448h04hMobile (When D28:F5:ECh:bit 1 = 1)
8C1Ch04hDesktop and Mobile (When D28:F6:ECh:bit 1 = 0)
244Eh04hDesktop (When D28:F6:ECh:bit 1 = 1)
2448h04hMobile (When D28:F6:ECh:bit 1 = 1)
8C1Eh04hDesktop and Mobile (When D28:F7:ECh:bit 1 = 0)
244Eh04hDesktop (When D28:F7:ECh:bit 1 = 1)
2448h04hMobile (When D28:F7:ECh:bit 1 = 1)
8C20h04hDesktop and Mobile - All SKUs.
C1
SRID
Comments
D20:F0USB xHCI8C31h04hDesktop and Mobile - All SKUs.
D25:F0LAN8C33h04hDesktop and Mobile - All SKUs.
D22:F0Intel
D22:F1
D22:F2IDE-R8C3Ch04hDesktop and Mobile - All SKUs.
D22:F3KT8C3Dh04hDesktop and Mobile - All SKUs.
®
ME
Interface
#1
IntelME
Interface
#2
8C3Ah04hDesktop and Mobile - All SKUs.
8C3Bh04hDesktop and Mobile - All SKUs.
58
Datasheet
Introduction
Table 1-8.PCH Device and Revision ID Table (Sheet 3 of 3)
Device
Function
D31:F0LPC8C41h04hLPC Controller (Mobile Full Featured Engineering Sample).
Notes:
1.PCH contains two SATA controllers. The SATA Device ID is dependent upon which SATA mode is selected by
BIOS and what RAID capabilities exist in the SKU.
2.The SATA RAID Controller Device ID is dependent upon the AIE bit setting (bit 7 of D31:F2:Offset 9Ch).
3.SATA Controller 2 (D31:F5) is only visible when D31:F2 CC.SCC =01h.
4.LAN Device ID is loaded from EEPROM. If EEPROM contains either 0000h or FFFFh in the Device ID location,
then 8C33h is used. Refer to the appropriate Intel
Device IDs.
5.For a given stepping, not all SKUs may be available.
6.This table shows the default PCI Express Function Number-to-Root Port mapping. Function numbers for a
given root port are assignable through the “Root Port Function Number and Hide for PCI Express Root
Ports” register (RCBA+0404h).
Descrip-
tion
Dev ID
8C42h04hLPC Controller (Desktop Full Featured Engineering Sample).
8C44h04hLPC Controller (Z87 SKU).
8C46h04hLPC Controller (Z85 SKU).
8C49h04hLPC Controller (HM86 SKU).
8C4Ah04hLPC Controller (H87 SKU).
8C4Bh04hLPC Controller (HM87 SKU).
8C4Ch04hLPC Controller (Q85 SKU).
8C4Eh04hLPC Controller (Q87 SKU).
8C4Fh04hLPC Controller (QM87 SKU).
8C50h04hLPC Controller (B85 SKU).
8C52h04hLPC Controller (C222 SKU).
8C54h04hLPC Controller (C224 SKU).
8C56h04hLPC Controller (C226 SKU).
8C5Ch04hLPC Controller (H81 SKU).
C1
SRID
Comments
®
GbE physical layer Transceiver (PHY) datasheet for LAN
§ §
Datasheet59
2Signal Description
This chapter provides a detailed description of each signal. The signals are arranged in
functional groups according to their associated interface.
The “#” symbol at the end of the signal name indicates that the active, or asserted
state occurs when the signal is at a low voltage level. When “#” is not present, the
signal is asserted when voltage level is high.
The following notations are used to describe the signal type:
IInput Pin.
O Output Pin.
OD OOpen Drain Output Pin.
I/OD Bi-directional Input/Open Drain Output Pin.
I/O Bi-directional Input/Output Pin.
CMOSCMOS buffers. 1.5 V tolerant.
CODCMOS Open Drain buffers. 3.3 V tolerant.
HVCMOS High Voltage CMOS buffers. 3.3 V tolerant.
AAnalog reference or output.
Signal Description
The “Type” for each signal is indicative of the functional operating mode of the signal.
Unless otherwise noted in Section 3.2 or Section 3.3, a signal is considered to be in the
functional operating mode after RTCRST# de-asserts for signals in the RTC well, after
RSMRST# de-asserts for signals in the suspend well, after PWROK asserts for signals in
the core well, after DPWROK asserts for signals in the DeepSx well, after APWROK
asserts for signals in the Active Sleep well.
Note:Core well includes 1.05 V, 1.5 V and 3.3 V rails powering PCH logic and these rails may
Figure 2-1. PCH Interface Signals Block Diagram (not all signals are on all SKUs)
Datasheet61
2.1Flexible I/O
The Intel® 8 Series/C220 Series Chipset Family PCH implements Flexible I/O, a
technology to allow some high speed signals to be configured as PCIe*, USB 3.0, or
SATA signals. There are a total of 18 High Speed I/O Ports in the PCH and, through soft
straps, four of these ports can have their functionality selected to meet the I/O needs
of the platform. Table 2-1 illustrates high speed I/O ports mapping to PCIe, USB 3.0
and SATA signals.
Table 2-1.I/O Flexibility Signal Mapping
High Speed I/
O Ports
1— —
2— —
3— —
4— —
5
6
7
8
9
10
11
12
13—
14—
15———
16———
17———
18———
GbE MapPCIe SignalsUSB 3.0 SignalsSATA Signals
000
(soft strap)
001
(soft strap)
010
(soft strap)
011
(soft strap)
100
(soft strap)
101
(soft strap)
110
(soft strap)
111
(soft strap)
PETp/n1
PERp/n1
PETp/n2
PERp/n2
PETp/n3
PERp/n3
PETp/n4
PERp/n4
PETp/n5
PERp/n5
PETp/n6
PERp/n6
PETp/n7
PERp/n7
PETp/n8
PERp/n8
PETp/n1
PERp/n1
PETp/n2
PERp/n2
Signal Description
USB3Tp/n1
USB3Rp/n1
USB3Tp/n2
USB3Rp/n2
USB3Tp/n5
USB3Rp/n5
USB3Tp/n6
USB3Rp/n6
USB3Tp/n3
USB3Rp/n3
USB3Tp/n4
USB3Rp/n4
——
——
——
——
——
——
—
—
—
—
—
—
—
—
SATA_TXp/n4
SATA_RXp/n4
SATA_TXp/n5
SATA_RXp/n5
SATA_TXp/n0
SATA_RXp/n0
SATA_TXp/n1
SATA_RXp/n1
SATA_TXp/n2
SATA_RXp/n2
SATA_TXp/n3
SATA_RXp/n3
62
Notes:
1.High speed I/O ports 5 and 6 can be configured as either PCIe port 1 and 2 or USB 3.0 port 3 and 4.
2.High speed I/O ports 13 and 14 can be configured as either PCIe port 1 and 2 or SATA port 4 and 5.
3.Maximum of 8 PCIe* ports, 6 USB 3.0 Ports or 6 SATA ports possible. GbE uses the physical interface of
PCIe ports so having 8 PCIe ports + 1 GbE simultaneously does not mean a total of 9 PCIe ports. 8 PCIe
ports + 1 GbE simultaneously is supported (depending on SKU configuration).
4.Refer to Chapter 5.22 for more details.
Datasheet
Signal Description
2.2USB Interface
Note:The USB 2.0 signals in the PCH integrate pull-down resistors and provide an output
driver impedance of 45 that requires no external series resistor. No external pull-up/
pull-down resistors should be added to the USB 2.0 signals. USB ports not needed can
be left floating as No Connect.
Note:The voltage divider formed by the device pull-up and the host pull-down will ensure the
data wire park at a safe voltage level, which is below the VBUS value. This ensures that
the host/hub will not see 5 V at the wire when inter-operating with devices that have
VBUS at 5 V.
Note:All USB 2.0 register addresses throughout the datasheet correspond to the external pin
names. Refer to Table 2-2 to know exactly how the USB pins are mapped to the
different internal ports within the xHCI and EHCI controllers.
Table 2-2.USB Interface Signals (Sheet 1 of 3)
Name
USB2p0
USB2n0
USB2p1
USB2n1
USB2p2
USB2n2
USB2p3
USB2n3
USB2p4
USB2n4
USB2p5
USB2n5
USB2p6
USB2n6
USB2p7
USB2n7
USB2p8
USB2n8
USB2p9
USB2n9
xHCI
Port
EHCI
Port
00I/O
11I/O
22I/O
33I/O
84I/O
95I/O
126I/O
137I/O
48I/O
59I/O
TypeDescription
USB 2.0 Port 0 Transmit/Receive Differential Pair 0:
This USB 2.0 signal pair can be routed to xHCI or EHCI
Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 1 Transmit/Receive Differential Pair 1:
This USB 2.0 signal pair can be routed to xHCI or EHCI
Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 2 Transmit/Receive Differential Pair 2:
This USB 2.0 signal pair can be routed to xHCI or EHCI
Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 3 Transmit/Receive Differential Pair 3:
This USB 2.0 signal pair can be routed to xHCI or EHCI
Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 4 Transmit/Receive Differential Pair 4:
This USB 2.0 signal pair can be routed to xHCI or EHCI
Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 5 Transmit/Receive Differential Pair 5:
This USB 2.0 signal pair can be routed to xHCI or EHCI
Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 6 Transmit/Receive Differential Pair 6:
This USB 2.0 signal pair can be mapped to xHCI or EHCI
Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 7 Transmit/Receive Differential Pair 7:
This USB 2.0 signal pair can be mapped to xHCI or EHCI
Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 8 Transmit/Receive Differential Pair 8:
This USB 2.0 signal pair can be mapped to xHCI or EHCI
Controller 2 through software and should map to a USB
connector with one of the overcurrent OC Pins 4–7.
USB 2.0 Port 9 Transmit/Receive Differential Pair 9:
This USB 2.0 signal pair can be mapped to xHCI or EHCI
Controller 2 through software and should map to a USB
connector with one of the overcurrent OC Pins 4–7.
Datasheet63
Table 2-2.USB Interface Signals (Sheet 2 of 3)
Signal Description
Name
USB2p10
USB2n10
USB2p11
USB2n11
USB2p12
USB2n12
USB2p13
USB2n13
USB3Tp1
USB3Tn1
USB3Rp1
USB3Rn1
USB3Tp2
USB3Tn2
USB3Rp2
USB3Rn2
USB3Tp3
USB3Tn3
USB3Rp3
USB3Rn3
USB3Tp4
USB3Tn4
xHCI
Port
1012I/O
1113I/O
EHCI
Port
610I/O
711I/O
1-O
1-I
2-O
2-I
3-O
3-I
4-O
TypeDescription
USB 2.0 Port 10 Transmit/Receive Differential Pair
10:This USB 2.0 signal pair can be mapped to xHCI or EHCI
Controller 2 through software and should map to a USB
connector with one of the overcurrent OC Pins 4–7.
USB 2.0 Port 11 Transmit/Receive Differential Pair 11:
This USB 2.0 signal pair can be mapped to xHCI or EHCI
Controller 2 through software and should map to a USB
connector with one of the overcurrent OC Pins 4–7.
USB 2.0 Port 12 Transmit/Receive Differential Pair 12:
This USB 2.0 signal pair can be mapped to xHCI or EHCI
Controller 2 through software and should map to a USB
connector with one of the overcurrent OC Pins 4–7.
USB 2.0 Port 13 Transmit/Receive Differential Pair 13:
This USB 2.0 signal pair can be mapped to xHCI or EHCI
Controller 2 through software and should map to a USB
connector with one of the overcurrent OC Pins 4–7.
USB 3.0 Differential Transmit Pair 1: These are USB 3.0based outbound high-speed differential signals, mapped to
High Speed I/O (HSIO) Port #1 and the xHCI Controller. It
should map to a USB connector with one of the OC
(overcurrent) pins 0–7.
USB 3.0 Differential Receive Pair 1: These are USB 3.0based inbound high-speed differential signals, mapped to High
Speed I/O (HSIO) Port #1 and the xHCI Controller. It should
map to a USB connector with one of the OC (overcurrent) pins
0–7.
USB 3.0 Differential Transmit Pair 2: These are USB 3.0based outbound high-speed differential signals, mapped to
High Speed I/O (HSIO) Port #2 and the xHCI Controller. It
should map to a USB connector with one of the OC
(overcurrent) pins 0–7.
USB 3.0 Differential Receive Pair 2: These are USB 3.0based inbound high-speed differential signals, mapped to High
Speed I/O (HSIO) Port #2 and the xHCI Controller. It should
map to a USB connector with one of the OC (overcurrent) pins
0–7.
USB 3.0 Differential Transmit Pair 3: These are USB 3.0based outbound high-speed differential signals, mapped to
High Speed I/O (HSIO) Port 5 and the xHCI Controller. It
should map to a USB connector with one of the OC
(overcurrent) pins 0–7.
Note: Use FITC to set the soft straps that select this port as
USB 3.0 Differential Receive Pair 3: These are USB 3.0based inbound high-speed differential signals, mapped to High
Speed I/O (HSIO) Port 5 and the xHCI Controller. It should
map to a USB connector with one of the OC (overcurrent) pins
0–7.
Note: Use FITC to set the soft straps that select this port as
USB 3.0 Differential Transmit Pair 4: These are USB 3.0based outbound high-speed differential signals, mapped to
High Speed I/O (HSIO) Port #6 and the xHCI Controller. It
should map to a USB connector with one of the OC
(overcurrent) pins 0–7.
Note: Use FITC to set the soft straps that select this port as
USB 3.0 Port 3. Default configuration is PCIe Port 1.
USB 3.0 Port 3. Default configuration is PCIe Port 1.
USB 3.0 Port 4. Default configuration is PCIe Port 2.
USB 3.0 Differential Receive Pair 4: These are USB 3.0-
based inbound high-speed differential signals, mapped to High
Speed I/O (HSIO) Port #6 and the xHCI Controller. It should
map to a USB connector with one of the OC (overcurrent) pins
0–7.
Note: Use FITC to set the soft straps that select this port as
USB 3.0 Differential Transmit Pair 5: These are USB 3.0based outbound high-speed differential signals, mapped to
High Speed I/O (HSIO) Port #3 and the xHCI Controller. It
should map to a USB connector with one of the OC
(overcurrent) pins 0–7.
USB 3.0 Differential Receive Pair 5: These are USB 3.0based inbound high-speed differential signals, mapped to High
Speed I/O (HSIO) Port #3 and the xHCI Controller. It should
map to a USB connector with one of the OC (overcurrent) pins
0–7.
USB 3.0 Differential Transmit Pair 6: These are USB 3.0based outbound high-speed differential signals, mapped to
High Speed I/O (HSIO) Port #4 and the xHCI Controller. It
should map to a USB connector with one of the OC
(overcurrent) pins 0–7.
USB 3.0 Differential Receive Pair 6: These are USB 3.0based inbound high-speed differential signals, mapped to High
Speed I/O (HSIO) Port #4 and the xHCI Controller. It should
map to a USB connector with one of the OC (overcurrent) pins
0–7.
Overcurrent Indicators: These signals set corresponding
bits in the USB controllers to indicate that an overcurrent
condition has occurred.
OC[7:0]# is the default (Native) function for these pins but
they may be configured as GPIOs instead.
Notes:
1.OC pins are 3.3 V tolerant.
2.Sharing of OC pins is required to cover all 14 USB
3.OC[3:0]# should be connected with USB 2.0 ports 0–7
4.OC[7:4]# should be connected with USB 2.0 ports 8–13
USB Resistor Bias: Analog connection point for an external
resistor that is used to set transmit currents and internal load
resistors. It is recommended that a 22.6 Ω ±1% resistor to
ground be connected to this pin.
USB Resistor Bias Complement: Analog connection point
for an external resistor that is used to set transmit currents
and internal load resistors. This signal should be connected
directly to USBRBIAS.
USB 3.0 Port 4. Default configuration is PCIe Port 2.
connectors but no more than 1 OC line may be
connected to a USB connector.
and any 4 of USB 3.0 ports 1–6.
and any 4 of USB 3.0 ports 1–6.
Datasheet65
2.3PCI Express*
Table 2-3.PCI Express* Signals (Sheet 1 of 2)
NameTypeDescription
PCI Express* Differential Transmit Pair 1: These are PCI Express 2.0-based
outbound high-speed differential signals, and can be mapped to either High Speed
I/O (HSIO) Port 5 or HSIO Port 13.
PETp1
PETn1
PERp1
PERn1
PETp2
PETn2
PERp2
PERn2
PETp3
PETn3
PERp3
PERn3
PETp4
PETn4
PERp4
PERn4
PETp5
PETn5
PERp5
PERn5
PETp6
PETn6
PERp6
PERn6
PETp7
PETn7
PERp7
PERn7
Note: GbE can be mapped to PCIe Port 1 if PCIe Port 1 is selected at HSIO Port
O
I
O
I
O
I
O
I
O
I
O
I
O
I
5. GbE cannot be mapped to PCIe Port 1 if PCIe Port 1 is selected at HSIO
Port 13. See Section 5.4 for details on GbE configuration and support.
Note: Use FITC to set the soft straps that select this port as muxed with USB
3.0 Port 3 or muxed with SATA Port 4. FITC does not allow multiplexing
PCIe Port 1 with USB 3.0 Port 3 and SATA Port 4 simultaneously, and it is
not a supported configuration.
PCI Express* Differential Receive Pair 1: These are PCI Express 2.0-based
inbound high-speed differential signals, and can be mapped to HSIO Port 5 or
HSIO Port 13.
Note: GbE can be mapped to PCIe Port 1 if PCIe Port 1 is selected at HSIO Port
5. GbE cannot be mapped to PCIe Port 1 if PCIe Port 1 is selected at HSIO
Port 13. See Section 5.4 for details on GbE configuration and support.
Note: Use FITC to set the soft straps that select this port as muxed with USB
3.0 Port 3 or muxed with SATA Port 4. FITC does not allow multiplexing
PCIe Port 1 with USB 3.0 Port 3 and SATA Port 4 simultaneously, and it is
not a supported configuration.
PCI Express Differential Transmit Pair 2: These are PCI Express 2.0-based
outbound high-speed differential signals, and can be mapped to HSIO Port 6 or
HSIO Port 14.
Note: GbE can be mapped to PCIe Port 2 if PCIe Port 2 is selected at HSIO Port
6. GbE cannot be mapped to PCIe Port 2 if PCIe Port 2 is selected at HSIO
Port 14. See Section 5.4 for details on GbE configuration and support.
Note: Use FITC to set the soft straps that select this port as muxed with USB
3.0 Port 4 or muxed with SATA Port 5. FITC does not allow multiplexing
PCIe Port 2 with USB 3.0 Port 4 and SATA Port 5 simultaneously, and it is
not a supported configuration.
PCI Express Differential Receive Pair 2: These are PCI Express 2.0-based
inbound high-speed differential signals, and can be mapped to HSIO Port 6 or
HSIO Port 14.
Note: GbE can be mapped to PCIe Port 2 if PCIe Port 2 is selected at HSIO Port
6. GbE cannot be mapped to PCIe Port 2 if PCIe Port 2 is selected at HSIO
Port 14. See Section 5.4 for details on GbE configuration and support.
Note: Use FITC to set the soft straps that select this port as muxed with USB
3.0 Port 4 or muxed with SATA Port 5. FITC does not allow multiplexing
PCIe Port 2 with USB 3.0 Port 4 and SATA Port 5 simultaneously, and it is
not a supported configuration.
PCI Express Differential Transmit Pair 3: These are PCI Express 2.0-based
outbound high-speed differential signals, mapped to HSIO Port 7.
PCI Express Differential Receive Pair 3: These are PCI Express 2.0-based
inbound high-speed differential signals, mapped to HSIO Port 7.
PCI Express Differential Transmit Pair 4: These are PCI Express 2.0-based
outbound high-speed differential signals, mapped to HSIO Port 8.
PCI Express* Differential Receive Pair 4: These are PCI Express 2.0-based
outbound high-speed differential signals, mapped to HSIO Port 8.
PCI Express Differential Transmit Pair 5: These are PCI Express 2.0-based
outbound high-speed differential signals, mapped to HSIO Port 9.
PCI Express Differential Receive Pair 5: These are PCI Express 2.0-based
outbound high-speed differential signals, mapped to HSIO Port 9.
PCI Express Differential Transmit Pair 6: These are PCI Express 2.0-based
outbound high-speed differential signals, mapped to HSIO Port 10.
PCI Express Differential Receive Pair 6: These are PCI Express 2.0-based
outbound high-speed differential signals, mapped to HSIO Port 10.
PCI Express Differential Transmit Pair 7: These are PCI Express 2.0-based
outbound high-speed differential signals, mapped to HSIO Port 11.
PCI Express Differential Receive Pair 7: These are PCI Express 2.0-based
outbound high-speed differential signals, mapped to HSIO Port 11.
Signal Description
66
Datasheet
Signal Description
Table 2-3.PCI Express* Signals (Sheet 2 of 2)
NameTypeDescription
PETp8
PETn8
PERp8
PERn8
PCIE_RCOMPI
PCIE_IREFIInternal Reference Voltage: Connect directly to 1.5 V.
PCI Express Differential Transmit Pair 8: These are PCI Express 2.0-based
O
outbound high-speed differential signals, mapped to HSIO Port 12.
PCI Express Differential Receive Pair 8: These are PCI Express 2.0-based
I
outbound high-speed differential signals, mapped to HSIO Port 12.
Impedance Compensation Input: Connected to a 7.5 K (1%) precision
external pull-up resistor to 1.5 V.
2.4Serial ATA Interface
Table 2-4.Serial ATA Interface Signals (Sheet 1 of 2)
NameTypeDescription
SATA_TXp0
SATA_TXn0
SATA_RXp0
SATA_RXn0
SATA_TXp1
SATA_TXn1
SATA_RXp1
SATA_RXn1
SATA_TXp2
SATA_TXn2
SATA_RXp2
SATA_RXn2
SATA_TXp3
SATA_TXn3
SATA_RXp3
SATA_RXn3
SATA_TXp4
SATA_TXn4
SATA_RXp4
SATA_RXn4
Serial ATA Differential Transmit Pair 0: These outbound SATA Port 0 high-speed
differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO
O
Port 15. In compatible mode, SATA Port 0 is the primary master of SATA Controller
1.
Serial ATA Differential Receive Pair 0: These inbound SATA Port 0 high-speed
differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO
I
Port 15. In compatible mode, SATA Port 0 is the primary master of SATA Controller
1.
Serial ATA Differential Transmit Pair 1: These outbound SATA Port 1 high-speed
differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO
O
Port 16. In compatible mode, SATA Port 1 is the secondary master of SATA Controller
1.
Serial ATA Differential Receive Pair 1: These inbound SATA Port 1 high-speed
differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO
I
Port 16. In compatible mode, SATA Port 1 is the secondary master of SATA Controller
1.
Serial ATA Differential Transmit Pair 2: These outbound SATA Port 2 high-speed
O
differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO
Port 17. In compatible mode, SATA Port 2 is the primary slave of SATA Controller 1.
Serial ATA Differential Receive Pair 2: These inbound SATA Port 2 high-speed
I
differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO
Port 17. In compatible mode, SATA Port 2 is the primary slave of SATA Controller 1.
Serial ATA Differential Transmit Pair 3: These outbound SATA Port 3 high-speed
O
differential signals support 1.5Gb/s, 3Gb/s and 6Gb/s, and are mapped to HSIO Port
18. In compatible mode, SATA Port 3 is the secondary slave of SATA Controller 1.
Serial ATA Differential Receive Pair 3: These inbound SATA Port 3 high-speed
differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO
I
Port 18. In compatible mode, SATA Port 3 is the secondary slave of SATA Controller
1.
Serial ATA Differential Transmit Pair 4: These outbound SATA Port 4 high-speed
differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO
Port 13. In compatible mode, SATA Port 4 is the primary master of SATA Controller
O
2.
Note: Use FITC to set the soft straps that select this port as PCIe Port 1. Default
configuration is SATA Port 4.
Serial ATA Differential Receive Pair 4: These inbound SATA Port 4 high-speed
differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO
Port 13. In compatible mode, SATA Port 4 is the primary master of SATA Controller
I
2.
Use FITC to set the soft straps that select this port as PCIe Port 1. Default
Note:
configuration is SATA Port 4.
Datasheet67
Table 2-4.Serial ATA Interface Signals (Sheet 2 of 2)
NameTypeDescription
Serial ATA Differential Transmit Pair 5: These outbound SATA Port 5 high-speed
differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO
SATA_TXp5
SATA_TXn5
SATA_RXp5
SATA_RXn5
SATA0GP /
GPIO21
SATA1GP /
GPIO19
SATA2GP /
GPIO36
SATA3GP /
GPIO37
SATA4GP /
GPIO16
SATA5GP /
GPIO49
SATALED#OD O
SCLOCK /
GPIO22
SLOAD /
GPIO38
SDATAOUT0 /
GPIO39
SDATAOUT1 /
GPIO48
SATA_RCOMPI
SATA_IREFIInternal Reference Voltage: Connect directly to 1.5 V.
Port 14. In compatible mode, SATA Port 5 is the secondary master of SATA Controller
O
2.
Note: Use FITC to set the soft straps that select this port as PCIe Port 2. Default
Serial ATA Differential Receive Pair 5: These inbound SATA Port 5 high-speed
differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO
Port 14. In compatible mode, SATA Port 5 is the secondary master of SATA Controller
I
2.
Note: Use FITC to set the soft straps that select this port as PCIe Port 2. Default
Serial ATA 0 General Purpose: When configured as SATA0GP, this is an input pin
that is used as an interlock switch status indicator for SATA Port 0. Drive the pin to
I
‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open.
The default use of this pin is GPIO21.
Serial ATA 1 General Purpose: When configured as SATA1GP, this is an input pin
that is used as an interlock switch status indicator for SATA Port 1. Drive the pin to
I
‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open.
The default use of this pin is GPIO19.
Serial ATA 2 General Purpose: When configured as SATA2GP, this is an input pin
that is used as an interlock switch status indicator for SATA Port 2. Drive the pin to
I
‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open.
The default use of this pin is GPIO36.
Serial ATA 3 General Purpose: When configured as SATA3GP, this is an input pin
that is used as an interlock switch status indicator for SATA Port 3. Drive the pin to
I
‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open.
The default use of this pin is GPIO37.
Serial ATA 4 General Purpose: When configured as SATA4GP, this is an input pin
that is used as an interlock switch status indicator for SATA Port 4. Drive the pin to
I
‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open.
The default use of this pin is GPIO16.
Serial ATA 5 General Purpose: When configured as SATA5GP, this is an input pin
that is used as an interlock switch status indicator for SATA Port 5. Drive the pin to
I
‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open.
The default use of this pin is GPIO49.
Serial ATA LED: This signal is an open-drain output pin driven during SATA
command activity. It is to be connected to external circuitry that can provide the
current to drive a platform LED. When active, the LED is on. When tri-stated, the
LED is off. An external pull-up resistor to Vcc3_3 is required.
SGPIO Reference Clock: The SATA controller uses rising edges of this clock to
transmit serial data, and the target uses the falling edge of this clock to latch data.
OD O
The SClock frequency supported is 32 kHz.
If SGPIO interface is not used, this signal can be used as GPIO22.
SGPIO Load: The controller drives a ‘1’ at the rising edge of SCLOCK to indicate
either the start or end of a bit stream. A 4-bit vendor specific pattern will be
OD O
transmitted right after the signal assertion.
If SGPIO interface is not used, this signal can be used as GPIO38.
SGPIO Dataout: Driven by the controller to indicate the drive status in the
following sequence: drive 0, 1, 2, 3, 4, 5, 0, 1, 2...
OD O
If SGPIO interface is not used, the signals can be used as GPIO.
Impedance Compensation Input: Connected to a 7.5 K (1%) precision external
pull-up resistor to 1.5 V.
configuration is SATA Port 5.
configuration is SATA Port 5.
Signal Description
68
Datasheet
Signal Description
2.5Clock Signals
Table 2-5.Clock Interface Signals (Sheet 1 of 2)
NameTypeDescription
100 MHz PCIe* 3.0 specification compliant differential output to
CLKOUT_ITPXDP_P
CLKOUT_ITPXDP_N
CLKOUT_DP_P
CLKOUT_DP_N
CLKOUT_DPNS_P
CLKOUT_DPNS_N
CLKIN_DMI_P
CLKIN_DMI_N
CLKOUT_DMI_P
CLKOUT_DMI_N
CLKIN_SATA_P
CLKIN_SATA_N
CLKIN_DOT96_P
CLKIN_DOT96_N
XTAL25_INIConnection for 25 MHz crystal to PCH oscillator circuit
XTAL25_OUTOConnection for 25 MHz crystal to PCH oscillator circuit
REFCLK14INIUnused. Tie signal to GND through a 10 Kresistor.
This Clock can be used for the 3rd PEG slot. Platform Over-clocking
will not be supported when this clock is used for 3rd PEG slot.
135 MHz differential output for DisplayPort reference
O
135 MHz non-spread differential output for DisplayPort reference
O
Unused. Tie each signal to GND through a 10 K resistor.
I
100 MHz PCIe 3.0 specification compliant differential output to
O
processor
Unused. Tie each signal to GND through a 10 Kresistor.
I
Unused. Tie each signal to GND through a 10 Kresistor.
I
100 MHz PCIe 3.0 specification compliant differential output to PCI
O
Express* Graphics device
100 MHz PCIe 3.0 specification compliant differential output to a
O
second PCI Express* Graphics device
Clock Request Signals for PCIe Graphics slots.
Can instead be used as GPIOs
I
Note: External pull-up resistor required if used for CLKREQ#
functionality.
Note: These pins are not available in desktop packages.
100 MHz PCIe 2.0 specification compliant differential output to PCI
O
Express devices
Unused. Tie each signal to GND through a 10 Kresistor.
I
Clock Request Signals for PCI Express 100 MHz Clocks
Can instead by used as GPIOs
I/O
Note: External pull-up resistor required if used for CLKREQ#
functionality.
Clock Request Signals for PCI Express 100 MHz Clocks
Can instead by used as GPIOs
Note: External pull-up resistor required if used for CLKREQ#
I/O
functionality
Note: SMI# is for server/workstation only
Single-Ended, 33 MHz outputs to various connectors/devices. One of
CLKOUT_33MHZ[4:0]O
CLKIN_33MHZLOOPBACKI
these signals must be connected to CLKIN_33MHZLOOPBACK to
function as a 33MHz clock loopback. This allows skew control for
variable lengths of CLKOUT_33MHZ[4:0].
33 MHz clock feedBack input, to reduce skew between PCH on-die 33
MHz clock and 33 MHz clock observed by connected devices.
Datasheet69
Table 2-5.Clock Interface Signals (Sheet 2 of 2)
NameTypeDescription
Configurable as a GPIO or as a programmable output clock which can
be configured as one of the following:
CLKOUTFLEX01 / GPIO64I/O
1
CLKOUTFLEX1
CLKOUTFLEX2
CLKOUTFLEX3
DIFFCLK_BIASREFI/O
ICLK_IREFI/O
Note:
1.It is highly recommended to prioritize 14.31818/24/48 MHz clocks on CLKOUTFLEX1 and CLKOUTFLEX3
outputs. Intel does not recommend configuring the 14.31818/24/48 MHz clocks on CLKOUTFLEX0 and
CLKOUTFLEX2 if more than two 33 MHz clocks in addition to the feedback clock are used on the
CLKOUT_33 MHz outputs.
/ GPIO65I/O
1
/ GPIO66I/O
1
/ GPIO67I/O
• 33 MHz
• 14.31818 MHz
• 48/24 MHz
•DC Output logic ‘0’
Configurable as a GPIO or as a programmable output clock which can
be configured as one of the following:
• 33 MHz
• 14.31818 MHz
• 48/24 MHz
•DC Output logic ‘0’
Configurable as a GPIO or as a programmable output clock that can
be configured as one of the following:
• 33 MHz
• 14.31818 MHz
• 48/24 MHz
•DC Output logic ‘0’
Configurable as a GPIO or as a programmable output clock that can
be configured as one of the following:
• 33 MHz
• 14.31818 MHz
• 48/24 MHz
•DC Output logic ‘0’
Differential Clock Bias Reference: Connected to an external
precision resistor (7.5 KW ±1%) to 1.5 V
Internal Clock Bias Reference: Connect directly to a quiet 1.5 V
supply.
Signal Description
2.6Real Time Clock Interface
Table 2-6.Real Time Clock Interface
NameTypeDescription
RTCX1Special
RTCX2Special
70
Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If no
external crystal is used, then RTCX1 can be driven with the desired clock rate.
Maximum voltage allowed on this pin is 1.2 V.
Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If no
external crystal is used, then RTCX2 must be left floating.
Datasheet
32.768 KHz
Xtal
10M
VCCRTC
RTCX2
RTCX1
Vbatt
1uF
1 K
VccDSW3_3
(see note 3)
C1C2
R1
RTCRST#
1.0 uF
20 K
0.1uF
SRTCRST#
20 K
1.0 uF
Schottky Diodes
Signal Description
2.7External RTC Circuitry
The PCH implements an internal oscillator circuit that is sensitive to step voltage
changes in VccRTC. The following figure shows an example schematic recommended to
ensure correct operation of the PCH RTC.
Figure 2-2. Example External RTC Circuit
2.8Interrupt Interface
Table 2-7.Interrupt Signals
Datasheet71
Notes:
1.The Reference Designators used in this example are arbitrarily assigned.
2.The exact capacitor values and tolerances for C1 and C2 must be based on the crystal maker
recommendations.
3.For platforms not supporting DeepSx, the VccDSW3_3 pins must be connected to the VccSUS3_3 pins.
4.Vbatt is voltage provided by the RTC battery (such as coin cell).
5.VccRTC, RTCX1, RTCX2, RTCRST#, and SRTCRST# are PCH pins.
6.VccRTC powers PCH RTC well.
7.RTCX1 is the input to the internal oscillator.
8.RTCX2 is the amplified feedBack (output) for the external crystal. Important: If a single-ended clock
source, such as an oscillator, is used instead of the crystal to generate the RTC frequency, you must
leave pin RTCX2 floating (no connect).
NameTypeDescription
SERIRQI/ODSerial Interrupt Request: This pin implements the serial interrupt protocol.
PCI Interrupt Requests: In non-APIC mode, the PIRQx# signals can be routed
to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or 15 as described in Section 5.9.6.
PIRQ[D:A]# I/OD
PIRQ[H:E]# /
GPIO[5:2]
Note: PIRQ Interrupts can only be shared if it is configured as level sensitive. They cannot be shared if
configured as edge triggered.
Each PIRQx# line has a separate Route Control register.
In APIC mode, these signals are connected to the internal I/O APIC in the
following fashion: PIRQA# is connected to IRQ16, PIRQB# to IRQ17, PIRQC# to
IRQ18, and PIRQD# to IRQ19. This frees the legacy interrupts.
PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed
to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or 15 as described in Section 5.9.6.
Each PIRQx# line has a separate Route Control register.
I/OD
In APIC mode, these signals are connected to the internal I/O APIC in the
following fashion: PIRQE# is connected to IRQ20, PIRQF# to IRQ21, PIRQG# to
IRQ 22, and PIR QH # t o IRQ23. Th is frees th e l egacy inte rrupts. If no t needed for
interrupts, these signals can be used as GPIO.
Signal Description
2.9Processor Interface
Table 2-8.Processor Interface Signals
NameTypeDescription
Keyboard Controller Reset Processor: The keyboard controller can generate
INIT# to the processor. This saves the external OR gate with the PCH’s other
RCIN#I
PROCPWRGDO
PMSYNCHO
PECII/OPlatform Environment Control Interface: Single-wire, serial bus.
THRMTRIP#I
sources of INIT#. When the PCH detects the assertion of this signal, INIT# is
generated using a VLW message to the processor.
Note: The PCH will ignore RCIN# assertion during transitions to the S3, S4,
and S5 states.
Processor Power Good: This signal should be connected to the processor
UNCOREPWRGOOD input to indicate when the processor power is valid.
Power Management Sync: Provides state information from the PCH to the
processor.
Thermal Trip: When low, this signal indicates that a thermal trip from the
processor occurred, and the PCH will immediately transition to a S5 state. The
PCH will not wait for the processor stop grant cycle since the processor has
overheated.
2.10Direct Media Interface (DMI) to Host Controller
Table 2-9.Direct Media Interface Signals
NameTypeDescription
DMI_TXP0
DMI_TXN0
DMI_RXP0
DMI_RXN0
DMI_TXP1
DMI_TXN1
DMI_RXP1
DMI_RXN1
DMI_TXP2
DMI_TXN2
DMI_RXP2
DMI_RXN2
DMI_TXP3
DMI_TXN3
DMI_RXP3
DMI_RXN3
DMI_RCOMPI
DMI_IREFIInternal Reference Voltage: Connect directly to 1.5 V.
Direct Media Interface Differential Transmit Pair 0: This signal is an output
O
from the PCH to the processor.
Direct Media Interface Differential Receive Pair 0: This signal is an input to
I
the PCH from the processor.
Direct Media Interface Differential Transmit Pair 1: This signal is an output
O
from the PCH to the processor.
Direct Media Interface Differential Receive Pair 1: This signal is an input to
I
the PCH from the processor.
Direct Media Interface Differential Transmit Pair 2: This signal is an output
O
from the PCH to the processor.
Direct Media Interface Differential Receive Pair 2: This signal is an input to
I
the PCH from the processor.
Direct Media Interface Differential Transmit Pair 3: This signal is an output
O
from the PCH to the processor.
Direct Media Interface Differential Receive Pair 3: This signal is an input to
I
the PCH from the processor.
Impedance Compensation Input: Connected to a 7.5 K (1%) precision
external pull-up resistor to 1.5 V.
FDI_INTOUsed for Display interrupts from PCH to processor.
FDI_RCOMPI
FDI_IREFIInternal Reference Voltage: Connected to 1.5 V
FDI Display Link Receive Pair 0
I
FDI Display Link Receive Pair 1
I
Impedance Compensation Input: Connected to an external precision
resistor (7.5 K ±1%) to 1.5 V
2.12Analog Display/VGA DAC Signals
Table 2-11. Analog Display Interface Signals
NameTypeDescription
O
VGA_RED
VGA_GREEN
VGA_BLUE
DAC_IREF
VGA_HSYNC
VGA_VSYNC
VGA_DDC_CLK
VGA_DDC_DATA
VGA_IRTN
I/OAResistor Set: Set point resistor for the internal color palette DAC. A 649
HVCMOS
HVCMOS
I/O
COD
I/O
COD
I/O
COD
RED Analog Video Output: This signal is a VGA Analog video output
A
from the internal color palette DAC.
O
GREEN Analog Video Output: This signal is a VGA Analog video output
A
from the internal color palette DAC.
O
BLUE Analog Video Output: This signal is a VGA Analog video output
A
from the internal color palette DAC.
resistor is required between DAC_IREF and motherboard ground.
O
VGA Horizontal Synchronization: This signal is used as the horizontal
sync (polarity is programmable) or “sync interval”. 2.5 V output
O
VGA Vertical Synchronization: This signal is used as the vertical sync
(polarity is programmable). 2.5 V output.
Monitor Control Clock
Monitor Control Data
Monitor Current Return
2.13Digital Display Signals
Table 2-12. Digital Display Signals (Sheet 1 of 2)
NameTypeDescription
DDPB_AUXPI/OPort B: DisplayPort* Aux
DDPB_AUXNI/OPort B: DisplayPort Aux Complement
DDPB_HPDIPort B: HPD Hot-Plug Detect
DDPB_CTRLCLKI/OPort B: HDMI* Port B Control Clock.
DDPB_CTRLDATAI/OPort B: HDMI Port B Control Data.
DDPC_AUXPI/OPort C: DisplayPort Aux
Datasheet73
Signal Description
Table 2-12. Digital Display Signals (Sheet 2 of 2)
NameTypeDescription
DDPC_AUXNI/OPort C: DisplayPort Aux Complement
DDPC_HPDIPort C: HPD Hot-Plug Detect
DDPC_CTRLCLKI/OPort C:HDMI Port C Control Clock
DDPC_CTRLDATAI/OPort C:HDMI Port C Control Data
DDPD_AUXPI/OPort D: DisplayPort Aux
DDPD_AUXNI/OPort D: DisplayPort Aux Complement
DDPD_HPDIPort D: Hot-Plug Detect
DDPD_CTRLCLKI/OPort D:HDMI Port D Control Clock
DDPD_CTRLDATAI/OPort D:HDMI Port D Control Data
2.14Embedded DisplayPort* (eDP*) Backlight Control
Signals
Note:These signals can be left as No Connect (float) if eDP is not used.
Table 2-13. Embedded DisplayPort* (eDP*) backlight control signals
Name TypeDescription
eDP_VDDENI/O
eDP_BKLTENI/O
eDP_BKLTCTLI/O
eDP* Panel power Enable: Panel power control enable.
This signal is also called VDD_dBL in the CPIS specification and is used
to control the VDC source of the panel logic.
eDP Backlight Enable: Panel backlight enable control for eDP.
This signal is also called ENA_BL in the CPIS specification and is used to
gate power into the backlight circuitry.
eDP Panel Backlight Brightness control: Panel brightness control for
eDP.
This signal also called VARY_BL in the CPIS specification and is used as
the PWM Clock input signal
2.15Intel® High Definition Audio (Intel® HD Audio)
Link
Table 2-14. Intel® High Definition Audio (Intel® HD Audio) Link Signals (Sheet 1 of 2)
NameTypeDescription
®
Intel
HDA_RST#O
HDA_SYNCO
HDA_BCLKO
HDA_SDOO
High Definition Audio Reset: Master hardware reset to external
codec(s).
Intel
High Definition Audio Sync: 48 kHz fixed rate sample sync to the
codec(s). This signal is also used to encode the stream number.
IntelHigh Definition Audio Bit Clock Output: 24.000 MHz serial data
clock generated by the Intel High Definition Audio controller (the PCH).
IntelHigh Definition Audio Serial Data Out: Serial TDM data output to
the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s
for Intel High Definition Audio.
Note: This signal is sampled as a functional strap. See Section 2.18 for
more details. There is a weak integrated pull-down resistor on this
pin.
74
Datasheet
Signal Description
Table 2-14. Intel® High Definition Audio (Intel® HD Audio) Link Signals (Sheet 2 of 2)
NameTypeDescription
Intel High Definition Audio Serial Data In [3:0]: Serial TDM data
inputs from the codecs. The serial input is single-pumped for a bit rate of
HDA_SDI[3:0]I
HDA_DOCK_EN# /
GPIO33
HDA_DOCK_RST# /
GPIO13
24 Mb/s for Intel High Definition Audio. These signals have integrated pulldown resistors, which are always enabled.
Note: During enumeration, the PCH will drive this signal. During normal
operation, the CODEC will drive it.
Intel High Definition Audio Dock Enable: This signal controls the
external Intel HD Audio docking isolation logic. This is an active low signal.
When de-asserted, the external docking switch is in isolate mode. When
asserted, the external docking switch electrically connects the Intel HD
O
Audio dock signals to the corresponding PCH signals.
This signal can instead be used as GPIO33. This signal defaults to GPIO33
mode after PLTRST#. BIOS is responsible for configuring GPIO33 to
HDA_DOCK_EN# mode.
Intel High Definition Audio Dock Reset: This signal is a dedicated
HDA_RST# signal for the codec(s) in the docking station. Aside from
operating independently from the normal HDA_RST# signal, it otherwise
works similarly to the HDA_RST# signal.
O
This signal is shared with GPIO13. This signal defaults to GPIO13 mode
after PLTRST#. BIOS is responsible for configuring GPIO13 to
HDA_DOCK_RST# mode.
2.16Low Pin Count (LPC) Interface
Table 2-15. Low Pin Count (LPC) Interface Signals
NameTypeDescription
LAD[3:0]I/O
LFRAME#OLPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.
LDRQ0#,
LDRQ1# /
GPIO23
LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull-ups are
provided.
LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or
bus master access. These signals are typically connected to an external Super I/O
I
device. An internal pull-up resistor is provided on these signals.
LDRQ1# may optionally be used as GPIO23.
2.17General Purpose I/O Signals
The following table summarizes the GPIOs in the PCH. The control for the GPIO signals
is handled through an independent 128-byte I/O space. The base offset for this space is
selected by the GPIO_BAR register in D31:F0 configuration space. See Section 12.10
for details.
Highlights of GPIO Features
a. GPIO pins powered from DSW: If pin is configured as GPIO then it follows the
SUS well (does not follow DSW) and its content is wiped out when SUS is
removed.
b. Only GPIO[31:0] are blink-capable.
c. When the default of a multiplexed GPIO is Native but the desired functionality is
GPIO, care should be taken to ensure the signal is stable until it is initialized to
GPIO functionality.
Datasheet75
Signal Description
d. Glitch-less Output means the signal is ensured to be stable (no glitch) during
power on and when switching mode of operation from Native to GPIO or GPIO
to Native. Glitch-less Input means the signal has built-in de-glitch protection
that gates the input signal until power has become stable (the input is ignored
during this time).
e. The following GPIOs are capable of generating SMI#, SCI, or NMI: GPIO[60, 57,
56, 43, 27, 22, 21, 19, 17, 15:0].
f.GPIO_USE_SEL[31:0], GPIO_USE_SEL2[63:32] and GPIO_USE_SEL3[75:64]
select whether the pin is selected to function as GPIO (GPIO_USE_SEL[x] = 1)
or Native (GPIO_USE_SEL[x] = 0). However, the PCH Soft Straps (SPI Flash)
take precedence if there is a mismatch with GPIO_USE_SEL.
g. GP_IO_SEL[31:0], GP_IO_SEL[63:32] and GP_IO_SEL[75:64] select whether
the pin is an output (GP_IO_SEL[x] = 0) or an input (GP_IO_SEL[x] = 1). The
value written to or reported in this register is invalid when the pin is programmed
to Native function.
h. If the corresponding GPIO has been set as an input, and GPI_ROUT has been
programmed for NMI functionality, the GPI_NMI_EN[15:0] is used to allow
active-high or active-low NMI events (depending on the polarity selected by
GPI_INV[31:0]).
i.All the GP_RST_SEL registers are only resetable by RSMRST#. GPIO
Configuration registers within the Core Well are reset whenever PWROK is deasserted.
j.GPIO Configuration registers within the Suspend Well are reset when RSMRST#
is asserted, CF9h reset (06h or 0Eh), or SYS_RESET# is asserted. However,
CF9h reset and SYS_RESET# events can be masked from resetting the Suspend
well GPIO by programming appropriate GPIO Reset Select (GPIO_RST_SEL)
registers. See Section 12.10 for details.
k. GPIO24 is an exception to the other GPIO Signals in the Suspend Well and is not
reset by CF9h reset (06h or 0Eh)
Table 2-16. General Purpose I/O Signals (Sheet 1 of 5)
Name
GPIO0CoreGPIYesNoNoMultiplexed with BMBUSY#.
GPIO1CoreGPIYesYesNo
GPIO2
(Note 8)
GPIO3
(Note 8)
GPIO4
(Note 8)
GPIO5
(Note 8)
GPIO6CoreGPIYesYesNo
GPIO7CoreGPIYesYesNo
GPIO8SusGPOYesNoNoUnmultiplexed.
GPIO9SusNativeYesNoNo
Power
Well
CoreGPIYesNoNo
CoreGPIYesNoNo
CoreGPIYesNoNo
CoreGPIYesNoNo
Default
(Note 2)
GPI Event
Glitch-less
InputOutput
Desktop and Mobile: Available as GPIO1 only (Note 4).
Server: Multiplexed with TACH1.
Multiplexed PIRQE#.
Multiplexed PIRQF#.
Multiplexed PIRQG#.
Multiplexed PIRQH#.
Desktop and Mobile: Available as GPIO6 only (Note 4).
Server: Multiplexed with TACH2.
Desktop and Mobile: Available as GPIO7 only (Note 4).
Server: Multiplexed with TACH3.
Multiplexed with OC5#. When configured as GPIO, default
direction is Input (GPI).
Description
76
Datasheet
Signal Description
Table 2-16. General Purpose I/O Signals (Sheet 2 of 5)
Name
GPIO10SusNativeYesNoNo
GPIO11SusNativeYesYesNo
GPIO12
GPIO13
GPIO14SusNativeYesNoNo
GPIO15SusGPOYesNoYesUnmultiplexed.
GPIO16Core GPINoNoNo
GPIO17CoreGPIYesYesNo
GPIO18 Core NativeNoNo No
GPIO19
(Note 5)
GPIO20CoreNativeNoNoNo
GPIO21CoreGPIYesNoNoMultiplexed with SATA0GP.
GPIO22CoreGPIYesNoNoMultiplexed with SCLOCK.
GPIO23CoreNativeNoNoNoMultiplexed with LDRQ1#.
GPIO24
(Note 1)
GPIO25 SusNativeNoNoNo
GPIO26SusNativeNoNoNo
Power
Well
DSW
(Note 9)
Sus
(Note
12)
CoreGPIYesNoNo
SusGPONoNoYes
Default
(Note 2)
NativeYesNoNo
GPI YesNoNo
GPI Event
Glitch-less
InputOutput
Description
Multiplexed with OC6#. When configured as GPIO, default
direction is Input (GPI).
Multiplexed with SMBALERT#. When configured as GPIO,
default direction is Input (GPI).
Multiplexed with LAN_PHY_PWR_CTRL. GPIO / Native
functionality is controlled using soft strap. When
configured as GPIO, default direction is Output (GPO).
(Note 11)
Mobile: Multiplexed with HDA_DOCK_RST#.
Desktop: Available as GPIO13 only (Note 4).
Multiplexed with OC7#. When configured as GPIO, default
direction is Input (GPI).
Multiplexed with SATA4GP.
(Note 11)
Desktop and Mobile: Available as GPIO17 only (Note 4).
Server: Multiplexed with TACH0.
Multiplexed with PCIECLKRQ1#. External pull-up resistor
required for Native function.
When configured as GPIO, default direction is Output
(GPO).
Multiplexed with SATA1GP.
Multiplexed with PCIECLKRQ2#. External pull-up resistor
required for Native function.
When configured as GPIO, default direction is Output
(GPO).
Server: Also available as SMI# (Note 18).
Unmultiplexed.
Multiplexed with PCIECLKRQ3#. External pull-up resistor
required for Native function.
When configured as GPIO, default direction is Output
(GPO).
Multiplexed with PCIECLKRQ4#. External pull-up resistor
required for Native function.
When configured as GPIO, default direction is Output
(GPO).
Datasheet77
Table 2-16. General Purpose I/O Signals (Sheet 3 of 5)
Signal Description
Name
GPIO27
GPIO28SusGPONoNoYesUnmultiplexed.
GPIO29
GPIO30
(Note 9)
GPIO31
(Note 3)
GPIO32CoreGPONoNoNo
GPIO33
(Note 5)
GPIO34CoreGPINoNoNoUnmultiplexed.
GPIO35CoreGPONoNoYes
GPIO36
(Note 5)
GPIO37
(Note 5)
GPIO38CoreGPINoNoNoMultiplexed with SLOAD.
GPIO39CoreGPINoNoNoMultiplexed with SDATAOUT0.
GPIO40SusNativeNoNoNo
Power
Well
DSW
(Note 9)
DSW
(Note 9)
SusNativeNoNoYes
DSW
(Note 9)
CoreGPONoNoNo
CoreGPINoNoNo
CoreGPINoNoNo
Default
(Note 2)
GPINoNoNo
NativeNoNoYes
GPINoNoYes
GPI Event
Glitch-less
InputOutput
Description
Unmultiplexed. Can be configured as wake input to allow
wakes from Deep Sx but, since the pin is shared, the PCH
counts on this pin remaining asserted until PLTRST# deasserts or the PCH may latch the pin assertion as a LAN
wake request.
• Intel LAN Present: This pin is connected to the
LANWAKE# pin on the LAN PHY, is used to signal a ME
or host wake to the PCH. The pin may also be driven
by the platform to cause a host wake, but it must be
de-asserted whenever PLTRST# is de-asserted and
may only be used to wake the host (GPIO27 wake
enable must always be set).
• No Intel LAN Present: This pin does not have a
specific usage model for connection on the board, but
allows the OEM/ODM customers a custom method to
wake from Deep Sx.
Multiplexed with SLP_WLAN#.
GPIO / Native functionality is controlled using soft strap.
When configured as GPIO, default direction is Output
(GPO).
(Note 11, 15)
Multiplexed with SUSPWRDNACK, SUSWARN#.
SUSPWRDNACK mode is the default mode of operation. If
the system supports Deep Sx, then subsequent boots will
default to SUSWARN# mode. (Note 23)
When configured as GPIO, default direction is Input (GPI).
Notes:
1.Toggling this pin at a frequency higher than 10 Hz is
not supported.
2.Desktop: GPIO_USE_SEL[31] is internally hardwired
to a 1b, which means GPIO mode is permanently
selected and cannot be changed.
3.Mobile: This GPIO pin is permanently appropriated
by the ME as MGPIO2 for ACPRESENT function (not
available as a true GPIO).
Desktop: Available as GPIO32 only (Note 4).
Mobile: GPIO_USE_SEL2[0] is internally hardwired to a
0b, which means Native mode is permanently selected
and cannot be changed (not available as GPIO). External
pull-up to Core well is required for CLKRUN#.
Desktop: Available as GPIO33 only (Note 4).
Mobile: Also available as HDA_DOCK_EN#.
Desktop and Mobile: Available as GPIO35 only (Note 4).
Server: Also available as NMI#.
Multiplexed with SATA2GP.
Multiplexed with SATA3GP.
Multiplexed with OC1#.
When configured as GPIO, default direction is Input (GPI).
78
Datasheet
Signal Description
Table 2-16. General Purpose I/O Signals (Sheet 4 of 5)
Name
GPIO41SusNativeNoNoNo
GPIO42SusNativeNoNoNo
GPIO43SusNativeYesNoNo
GPIO44SusNativeNoNoNo
GPIO45SusNativeNoNoNo
GPIO46SusNativeNoNoNo
GPIO47SusNativeNoNoNo
GPIO48Core GPINoNoNoMultiplexed with SDATAOUT1.
GPIO49CoreGPINoYesNo
GPIO50CoreGPINoNoNoUnmultiplexed.
GPIO51
(Note 5)
GPIO52CoreGPINoNoNoUnmultiplexed.
GPIO53
(Note 5)
GPIO54CoreGPINoNoNoUnmultiplexed.
GPIO55
(Note 5)
GPIO56SusNativeYesNoNo
GPIO57SusGPIYesNoYes
GPIO58 SusNativeNoYesNo
GPIO59SusNativeNoNoNo
GPIO60SusNativeYesYesNo
GPIO61SusNativeNoNoYes
GPIO62
(Note 5)
Power
Well
CoreGPONoNoNo
CoreGPONoNoNo
CoreGPONoNoNo
SusNativeNoNoNo
Default
(Note 2)
GPI Event
Glitch-less
InputOutput
Description
Multiplexed with OC2#.
When configured as GPIO, default direction is Input (GPI).
Multiplexed with OC3#.
When configured as GPIO, default direction is Input (GPI).
Multiplexed with OC4#.
When configured as GPIO, default direction is Input (GPI).
Multiplexed with PCIECLKRQ5#. External pull-up resistor
required for Native function.
When configured as GPIO, default direction is Input (GPI).
Multiplexed with PCIECLKRQ6#. External pull-up resistor
required for Native function.
When configured as GPIO, default direction is Input (GPI).
Multiplexed with PCIECLKRQ7#. External pull-up resistor
required for Native function.
When configured as GPIO, default direction is Input (GPI).
Desktop and Server: This pin is not available in the
package as GPIO or Native.
Mobile: Multiplexed with PEG_A_CLKRQ#.
Multiplexed with SATA5GP.
(Note 11)
Unmultiplexed.
Unmultiplexed.
Unmultiplexed.
Desktop and Server: This pin is not available in the
package as GPIO or Native.
Mobile: Multiplexed with PEG_B_CLKRQ#.
Unmultiplexed. Can be re-purposed for NFC interface
input.
(Note 10)
Multiplexed with SML1CLK.
When configured as GPIO, default direction is Input (GPI).
Multiplexed with OC0#.
When configured as GPIO, default direction is Input (GPI).
Multiplexed with SML0ALERT#.
When configured as GPIO, default direction is Input (GPI).
Multiplexed with SUS_STAT#.
When configured as GPIO, default direction is Output
(GPO).
Multiplexed with SUSCLK (Note 13).
When configured as GPIO, default direction is Output
(GPO).
Datasheet79
Table 2-16. General Purpose I/O Signals (Sheet 5 of 5)
Signal Description
Name
GPIO63SusNativeNoNoYes
GPIO64CoreNativeNoNoNo
GPIO65CoreNativeNoNoNo
GPIO66CoreNativeNoNoNo
GPIO67CoreNativeNoNoNo
GPIO68CoreGPINoYesNo
GPIO69CoreGPINoYesNo
GPIO70CoreNativeNoYesNo
GPIO71CoreNativeNoYesNo
GPIO72
GPIO73SusNativeNoNoNo
GPIO74SusNativeNoYesNo
GPIO75SusNativeNoYesNo
Power
Well
DSW
(Note 9)
Default
(Note 2)
NativeNoNoNo
GPI Event
Glitch-less
InputOutput
Description
Multiplexed with SLP_S5#.
When configured as GPIO, default direction is Output
(GPO).
Multiplexed with CLKOUTFLEX0.
When configured as GPIO, default direction is Output
(GPO).
Multiplexed with CLKOUTFLEX1.
When configured as GPIO, default direction is Output
(GPO).
Multiplexed with CLKOUTFLEX2.
When configured as GPIO, default direction is Output
(GPO).
Multiplexed with CLKOUTFLEX3.
When configured as GPIO, default direction is Output
(GPO).
Desktop and Mobile: Available as GPIO68 only (Note 4).
Server: Multiplexed with TACH4.
Desktop and Mobile: Available as GPIO69 only (Note 4).
Server: Multiplexed with TACH5.
Desktop and Mobile: Available as GPIO70 only (Note 4).
Server: Multiplexed with TACH6.
(Note 11)
Desktop and Mobile: Available as GPIO71 only (Note 4).
Server: Multiplexed with TACH7.
(Note 11)
Desktop: Available as GPIO72 only (Note 4).
Mobile: Also available as BATLOW#.
Requires external pull-up resistor to DSW well.
Multiplexed with PCIECLKRQ0#.
External pull-up resistor required for Native function.
When configured as GPIO, default direction is Input (GPI).
Multiplexed with SML1ALERT#/TEMP_ALERT#.
When configured as GPIO, default direction is Input (GPI).
Can be re-purposed for NFC interface input.
(Note 10, 11, 21)
Multiplexed with SML1DATA.
When configured as GPIO, default direction is Input (GPI).
80
Notes:
1.GPIO[24] register bits are not cleared by CF9h reset by default, it is programmable through
GP_RST_SEL[24]
2.Internal pull-up or pull-down may be present when Native functionality is selected. Refer to Tab le 3 -1 for
more details.
3.Internal pull-down resistor may be enabled in Deep Sx mode based on DSX_CFG configuration bit, as
follows: ‘1’ (pin will be driven by platform in Deep Sx) -> Z; - ‘0’ (pin will NOT be driven by platform in
Deep Sx) -> Internal pull-down. Refer to DSX_CFG register (RCBA+3334h) for more details.
4.For pins that are available as GPIO-only: if the power-on default is Native, BIOS is still required to configure
the pin as GPIO by writing to the pin’s GPIO_USE_SEL register, even though the pin is only available as
GPIO.
5.A functional strap also exists on this pin.
6.Glitch-less Inputs are ensured, by circuit design, to de-glitch the input. Glitch-less Outputs are ensured, by
circuit design, to not generate any glitches on the output during power-on.
7.The GPIO pins which are capable of generating NMI message when it is configured as input, its GPI_ROUT
register is configured NMI functionality and its corresponding GPI NMI Enable (GNE) bit is set. NMI event is
positive edge trigger based on the signal and after GPI Inversion logic.
Datasheet
Signal Description
8.When GPIO[5:2] are configured as output GPIOs, they behave in an open drain manner.
9.This SUS well pin will be controlled by DSW logic. GPIO functionality is only available when the SUS well is
powered.
10. GPIO 74 or GPIO 57 can be used for NFC on a platform. The NFC option can be set through FITC in ME
configuration settings.
11. For GPIOs where GPIO versus Native Mode is configured using SPI Soft Strap, the corresponding
GPIO_USE_SEL bits for these GPIOs have no effect. The GPIO_USE_SEL bits for these GPIOs may change
to reflect the Soft-Strap configuration even though GPIO Lockdown Enable (GLE) bit is set.
12. GPIO13 is located in the HDA Suspend well. It can only be used if VccsusHDA is powered.
13. GPIO62 defaults as Native SUSCLK. If this pin is to be configured as GPIO, it is required that the board
ensure that the 32.768 kHz toggle rate does not affect the receiving logic of the pin until it is set as GPIO.
14. When switching from GPIO at logic 1 to the native functionality, the pin must not glitch low.
15. A soft strap (PMC_SOFT_STRAP_2 register[7] GP23MGPIO3_SLPWLAN_SEL) to enable switching between
SLP_WLAN# (default) or GP29/MPGIO3. By default the strap is 0b, which enables the SLP_WLAN# pin
function when sus well is up. When soft strap is loaded and value is 1b, the pin returns to its regular GPIO
or MGPIO mode while SLP_WLAN# function no longer exists. Also take into account of note 11.
16. GPIO72 will default to mobile (native) until determining if this is mobile or desktop/server SKU.
17. GPIO may toggle until after
18. When strapped as SMI#, the pin is automatically configured as open drain. The SMI# function is only
available in server/workstation SKU. The SMI# function is not the same as the SMI# events that the GPIOs
can be configured to generate, as described in GPI_ROUT and ALT_GPI_SMI_EN.
19. N/A
20. N/A
21. The choice of which native mode, SML1ALERT# or TEMP_ALERT#, is determined by a soft strap.
22. N/A
23. SUSPWRDNACK Mode is the default mode of operation. If the system supports DeepSx, then subsequent
boots will default to SUSWARN# mode.
2.18Functional Straps
The PCH implements hardware functional straps that are used to configure specific
functions within the PCH and processor very early in the boot process, before BIOS or
software intervention. Some are sampled at the rising edge of PWROK, while others at
the rising edge of RSMRST# to select configurations (except as noted), and then revert
later to their normal usage. When Descriptor Mode is enabled, the PCH will read Soft
Strap data out of the SPI device prior to the de-assertion of reset to both the Intel
Management Engine and the Host system. In some cases, the soft strap data may
override the hardware functional straps. See Section 5.26.2 for information on
Descriptor Mode.
Datasheet81
Table 2-17. Functional Strap Definitions (Sheet 1 of 3)
Bit11Bit 10Boot BIOS
Destination
01 Reserved
10 Reserved
11 SPI (default)
00LPC
Bit11Bit 10Boot BIOS
Destination
01 Reserved
10 Reserved
11 SPI (default)
00LPC
SignalUsageWhen SampledComment
This signal has a weak internal pull-up.
This field determines the destination of accesses to the BIOS
memory range. Also controllable using Boot BIOS Destination
bit (Chipset Config Registers: Offset 3410h:Bit 10). This strap is
used in conjunction with Boot BIOS Destination Selection 1
strap.
Signal Description
SATA1GP /
GPIO19
GPIO51
SATA2GP /
GPIO36
Boot BIOS Strap
bit 0
(BBS0)
Boot BIOS Strap
bit 1
(BBS1)
DMI RX
Termination
Rising edge of
PWROK
Rising edge of
PWROK
Rising edge of
PWROK
Notes:
1.The internal pull-up is disabled after PLTRST# de-asserts.
2.If option 00 (LPC) is selected, BIOS may still be placed on
LPC, but the platform is required to have SPI flash
connected directly to the PCH SPI bus with a valid
descriptor in order to boot.
3.Boot BIOS Destination Select to LPC/PCI by functional
strap or using Boot BIOS Destination Bit will not affect SPI
accesses initiated by Intel ME or Integrated GbE LAN.
4.See Section 10.1.49 for additional information.
5.This signal is in the Core well.
This signal has a weak internal pull-up.
This field determines the destination of accesses to the BIOS
memory range. Also controllable using Boot BIOS Destination
bit (Chipset Config Registers: Offset 3410h:Bit 11). This strap is
used in conjunction with Boot BIOS Destination Selection 0
strap.
Notes:
1.The internal pull-up is disabled after PLTRST# de-asserts.
2.If option 00 (LPC) is selected, BIOS may still be placed on
LPC, but the platform is required to have SPI flash
connected directly to the PCH's SPI bus with a valid
descriptor in order to boot.
3.Boot BIOS Destination Select to LPC/PCI by functional
strap or using Boot BIOS Destination Bit will not affect SPI
accesses initiated by Intel ME or Integrated GbE LAN.
4.See Section 10.1.49 for additional information.
5.This signal is in the Core well.
This signal has a weak internal pull-down.
This signal only takes effect if DMI is configured in AC-coupled
mode (server/workstation only).
0 = DMI RX is terminated to VSS.
1 = DMI RX is terminated to VCC/2.
Notes:
1.The internal pull-down is disabled after PLTRST# deasserts.
2.If DMI is operating in DC-coupled mode (such as Client
applications), then DMI RX is terminated to VSS and the
value of this strap is ignored by the PCH and does not take
effect.
3.This signal is in the Core well.
82
Datasheet
Signal Description
Table 2-17. Functional Strap Definitions (Sheet 2 of 3)
SignalUsageWhen SampledComment
This signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security (TLS)
cipher suite (no confidentiality).
1 = Enable Intel ME Crypto Transport Layer Security (TLS)
SATA3GP /
GPIO37
HDA_SDOReserved
HDA_DOCK_EN# /
GPIO33
INTVRMEN
GPIO62 / SUSCLK
DSWVRMEN
SPKRNo Reboot
TLS Confidentiality
Integrated VRM
PLL On-Die Voltage
Regulator Enable
DeepSx Well On-
Regulator Enable
Reserved
Enable
Die Voltage
Rising edge of
PWROK
Rising edge of
PWROK
Rising edge of
PWROK
Always
Rising edge of
RSMRST#
Always
Rising edge of
PWROK
cipher suite (with confidentiality). Must be pulled up to
support Intel
Business Advantage) with TLS.
Notes:
1.The internal pull-down is disabled after PLTRST# deasserts.
2.This signal is in the Core well.
This signal has a weak internal pull-down.
Notes:
1.The internal pull-down is disabled after PLTRST# deasserts.
2.This signal is in the Suspend well.
This signal has a weak internal pull-down.
Notes:
1.The internal pull-down is disabled after PLTRST# deasserts.
2.This signal is in the Core well.
This signal does not have an internal resistor; an external
resistor is required.
0 = DCPSUS1, DCPSUS2 and DCPSUS3 are powered from an
external power source (should be connected to an external
VRM). External VR powering option is for Mobile Only;
Desktop/Server/Workstation should not pull the strap low.
1 = Integrated VRMs enabled. DCPSUS1, DCPSUS2 and
DCPSUS3 can be left as No Connect.
Notes:
1.This signal is always sampled.
2.This signal is in the RTC well.
This signal has a weak internal pull-up.
0 = Disable PLL On-Die voltage regulator.
1 = Enable PLL On-Die voltage regulator.
Notes:
1.The internal pull-up is disabled after RSMRST# de-asserts.
2.This signal is in the Suspend well.
This signal does not have an internal resistor; an external
resistor is required.
0 = Disable Integrated DeepSx Well (DSW) On-Die Voltage
Regulator. This mode is only supported for testing
environments.
1 = Enable DSW 3.3 V-to-1.05 V Integrated DeepSx Well
(DSW) On-Die Voltage Regulator. This must always be
pulled high on production boards.
Notes:
1.This signal is always sampled.
2.This signal is in the RTC well.
The signal has a weak internal pull-down.
0 = Disable “No Reboot” mode.
1 = Enable “No Reboot” mode (PCH will disable the TCO Timer
system reboot feature). This function is useful when
running ITP/XDP.
Notes:
1.The internal pull-down is disabled after PLTRST# deasserts.
2.The status of this strap is readable using the NO REBOOT
bit (Chipset Config Registers: RCBA + Offset 3410h:Bit 5).
3.See
4.This signal is in the Core well.
®
Section 10.1.49 for additional information.
AMT with TLS and Intel SBA (Small
Datasheet83
Table 2-17. Functional Strap Definitions (Sheet 3 of 3)
SignalUsageWhen SampledComment
This signal has a weak internal pull-up.
GPIO53Reserved
GPIO55 Top Swap Override
DDPB_CTRLDATAPort B Detected
DDPC_CTRLDATAPort C Detected
DDPD_CTRLDATAPort D Detected
Rising edge of
PWROK
Rising edge of
PWROK
Rising edge of
PWROK
Rising edge of
PWROK
Rising edge of
PWROK
Notes:
1.The internal pull-up is disabled after PLTRST# de-asserts.
2.This signal is in the Core well.
The signal has a weak internal pull-up.
0 = Enable “Top Swap” mode.
1 = Disable “Top Swap” mode.
Notes:
1.The internal pull-up is disabled after PLTRST# de-asserts.
2.Software will not be able to clear the Top Swap mode bit
until the system is rebooted.
3.The status of this strap is readable using the Top Swap bit
(Chipset Config Registers: RCBA + Offset 3414h:Bit 0).
4.This signal is in the Core well.
This signal has a weak internal pull-down.
0 = Port B is not detected.
1 = Port B is detected.
Notes:
1.The internal pull-down is disabled after PLTRST# deasserts.
2.This signal is in the Core well.
This signal has a weak internal pull-down.
0 = Port C is not detected.
1 = Port C is detected.
Notes:
1.The internal pull-down is disabled after PLTRST# deasserts.
2.This signal is in the Core well.
This signal has a weak internal pull-down.
0 = Port D is not detected.
1 = Port D is detected.
Notes:
1.The internal pull-down is disabled after PLTRST# deasserts.
2.This signal is in the Core well.
Signal Description
Note: See Section 3.1 for full details on pull-up/pull-down resistors.
2.19SMBus Interface
Table 2-18. SMBus Interface Signals
NameTypeDescription
SMBDATAI/ODSMBus Data: External pull-up resistor is required.
SMBCLKI/ODSMBus Clock: External pull-up resistor is required.
SMBALERT# /
GPIO11
84
SMBus Alert: This signal is used to wake the system or generate SMI#.
I
This signal may be used as GPIO11.
Datasheet
Signal Description
2.20System Management Interface
Table 2-19. System Management Interface Signals
NameTypeDescription
INTRUDER#I
SML0DATAI/OD
SML0CLKI/OD
SML0ALERT# /
GPIO60
SML1ALERT# /
TEMP_ALERT# /
GPIO74
SML1CLK /
GPIO58
SML1DATA /
GPIO75
Intruder Detect: This signal can be set to disable the system if box detected
open. This signal status is readable, so it can be used like a GPI if the Intruder
Detection is not needed.
System Management Link 0 Data: SMBus link to external PHY. External pullup is required.
System Management Link 0 Clock: SMBus link to external PHY. External
pull-up is required.
SMLink Alert 0: Output of the integrated LAN controller to external PHY.
External pull-up resistor is required.
O OD
This signal can instead be used as GPIO60.
SMLink Alert 1: Alert for the ME SMBus controller to optional Embedded
Controller or BMC. A soft-strap determines the native function SML1ALERT# or
TEMP_ALERT# usage. When soft-strap is 0, function is SML1ALERT#, when
O OD
soft-strap is 1, function is TEMP_ALERT#. This pin can also be set to function as
GPIO74.
External pull-up resistor is required on this pin.
System Management Link 1 Clock: SMBus link to optional Embedded
Controller or BMC. External pull-up resistor is required.
I/OD
This signal can instead be used as GPIO58.
System Management Link 1 Data: SMBus link to optional Embedded
Controller or BMC. External pull-up resistor is required.
I/OD
This signal can instead be used as GPIO75.
2.21Controller Link
Table 2-20. Controller Link Signals
Signal NameTypeDescription
CL_RST#O
CL_CLKI/O
CL_DATAI/O
Controller Link Reset: Controller Link reset that connects to a Wireless
LAN Device supporting Intel Active Management Technology. This signal is in
the Suspend power well.
Controller Link Clock: Bi-directional clock that connects to a Wireless LAN
Device supporting Intel Active Management Technology. This signal is in the
Suspend power well.
Controller Link Data: Bi-directional data that connects to a Wireless LAN
Device supporting Intel Active Management Technology. This signal is in the
Suspend power well.
2.22Serial Peripheral Interface (SPI)
Table 2-21. Serial Peripheral Interface (SPI) Signals (Sheet 1 of 2)
NameTypeDescription
SPI_CLKO
SPI_CS0#O
SPI_CS1# O
SPI Clock: SPI clock signal, during idle the bus owner will drive the clock
signal low. Supported frequencies are 20 MHz, 33 MHz and 50 MHz.
SPI Chip Select 0: Used to select the primary SPI Flash device.
Note: This signal cannot be used for any other type of device than SPI Flash.
SPI Chip Select 1: Used to select an optional secondary SPI Flash device.
Note: SPI_CS0# cannot be used for any other type of device than SPI Flash.
Datasheet85
Table 2-21. Serial Peripheral Interface (SPI) Signals (Sheet 2 of 2)
NameTypeDescription
SPI Chip Select 2: Used to select the TPM device if it is connected to the SPI
SPI_CS2#O
SPI_MOSII/O
SPI_MISOI/O
SPI_IO2I/O
SPI_IO3I/O
interface, it cannot be used for any other type of device than TPM.
Note: TPM can be configured through soft straps to operate over LPC or SPI,
but no more than 1 TPM is allowed in the system.
SPI Master OUT Slave IN: Defaults as a data output pin for PCH in Dual
Output Fast Read mode. Can be configured with a soft strap as a bidirectional
signal (SPI_IO0) to support the new Dual I/O Fast Read, Quad I/O Fast Read
and Quad Output Fast Read modes.
SPI Master IN Slave OUT: Defaults as a data input pin for PCH in Dual Output
Fast Read mode. Can be configured with a soft strap as a bidirectional signal
(SPI_IO1) to support the new Dual I/O Fast Read, Quad I/O Fast Read and
Quad Output Fast Read modes.
SPI Data I/O: A bidirectional signal used to support the new Dual
I/O Fast Read, Quad I/O Fast Read and Quad Output Fast Read modes. This
signal is not used in Dual Output Fast Read mode.
SPI Data I/O: A bidirectional signal used to support the new Dual
I/O Fast Read, Quad I/O Fast Read and Quad Output Fast Read modes. This
signal is not used in Dual Output Fast Read mode.
2.23Manageability Signals
Signal Description
The following signals can be optionally used by the Intel ME supported applications and
appropriately configured by Intel Management Engine Firmware. When configured and
used as a manageability function, the associated host GPIO functionality is no longer
available. If the manageability function is not used in a platform, the signal can be used
as a host General Purpose I/O or a native function.
The manageability signals are referred to as Management Engine GPIO pins (MGPIO
pins), which are GPIO pins that can be controlled through Intel ME FW.
Table 2-22. MGPIO Conversion Table
MGPIOGPIOWellDefault Usage
024SUS–
130SUSSUSWARN# or SUSPWRDNACK
231SUSACPRESENT
329SUSSLP_WLAN#
460SUSSML0ALERT#
557SUSRequired for NFC (assumes GPIO74 is not setup for NFC)
627DSWIntel ME Wake Input
728SUS–
874SUS
916MAINSATA4GP#
1049MAINSATA5GP#
1158SUSSML1CLK
1275SUSSML1DATA
Required for NFC (assumes GPIO 57 is not setup for NFC)
SML1ALERT#/TEMP_ALERT# or
Note:The information in the Default Usage column is not for server platforms. For
information on server manageability signals, see Table 2-24.
86
Datasheet
Signal Description
Table 2-23. Client Manageability Signals
NameType
MGPIO6I/ODSW
Power
Well
Can be configured as a wake input for the Intel ME. This pin is
implemented in the DSW in order to allow wakes from the DeepSx
state. This pin does not have a specific usage model for connection
on the board, but allows the OEM/ODM customers a custom
method to wake from DeepSx.
Description
Table 2-24. Server Manageability Signals
NameType
MGPIO2I/OSUSSMBALERT# signal from PSU to PCH. This signal indicates the
PSU may cause a system shutdown due to a momentary loss of
AC input voltage or an over-temperature condition.
Intel ME Firmware Recovery Mode Strap. These signals are inputs
to the PCH to force Intel ME to stay in recovery boot loader.
Note:See Table 2-22 for the MGPIO conversion table.
2.24Power Management Interface
Table 2-25. Power Management Interface Signals (Sheet 1 of 4)
NameTypeDescription
ACPRESENT: This input pin indicates when the platform is plugged into AC
power or not. In addition to the previous Intel ME to EC communication, the
PCH uses this information to implement the DeepSx policies. For example,
the pl atform m ay be configu re d to enter D ee pSx when in S4 or S5 and only
ACPRESENT
/ GPIO31
APWROKI
BATLOW# / GPIO72I
BMBUSY#
/ GPIO0
CLKRUN# (Mobile
Only) / GPIO32
(Desktop Only)
when running on battery. This is powered by DeepSx Well.
Note: This signal is muxed with GPIO31 but GPIO_USE_SEL[31] is
I
I
I/O
internally hardwired to a 1b, which means GPIO mode is
permanently selected and cannot be changed.
Mobile: This GPIO pin is permanently appropriated by the Intel ME as
MGPIO2 for ACPRESENT function.
Desktop: This pin is only GPIO31, ACPRESENT is not supported.
Active Sleep Well (ASW) Power OK: When asserted, this signal
indicates that power to the ASW sub-system is stable.
Battery Low: This signal is available in Mobile package only. An input from
the battery to indicate that there is insufficient power to boot the system.
Assertion will prevent wake from S3–S5 state. This signal can also be
enabled to cause an SMI# when asserted. For the Mobile package, this
signal is multiplexed with GPIO72. In the Desktop package, this signal is
only available as GPIO72. This signal must be tied high to the VCCDSW3_3,
which will be tied to VccSUS3_3 on DeepSx disabled platforms.
Note: See Table 2-16 for Desktop implementation pin requirements.
Bus Master Busy: Generic bus master activity indication driven into the
PCH. This signal can be configured to set the PM1_STS.BM_STS bit. The
signal can also be configured to assert indications transmitted from the PCH
to the processor using the PMSYNCH pin.
LPC Clock Run: This signal is used to support LPC CLKRUN protocol. It
connects to peripherals that need to request clock restart or prevention of
clock stopping. Not available in Desktop.
Datasheet87
Table 2-25. Power Management Interface Signals (Sheet 2 of 4)
NameTypeDescription
DPWROK: Power OK Indication for the VccDSW3_3 voltage rail. This input
DPWROKI
DRAMPWROK OD O
LAN_PHY_PWR_CT
RL / GPIO12
PLTRST#O
PLTRST_PROC#O
PWRBTN#I
PWROKI
RI#I
RSMRST#I
SLP_A#O
SLP_LAN# O
is tied together with RSMRST# on platforms that do not support DeepSx.
This signal is in the RTC well.
DRAM Power OK: This signal should connect to the processor’s
SM_DRAMPWROK pin. The PCH asserts this pin to indicate when DRAM
power is stable.
This pin requires an external pull-up.
LAN PHY Power Control: LAN_PHY_PWR_CTRL should be connected to
LAN_DISABLE_N on the PHY. PCH will drive LAN_PHY_PWR_CTRL low to put
the PHY into a low power state when functionality is not needed.
O
Notes:
1.LAN_PHY_PWR_CTRL can only be driven low if SLP_LAN# is deasserted.
2.Signal can instead be used as GPIO12.
Platform Reset: The PCH asserts PLTRST# to reset devices on the
platform (such as SIO, FWH, LAN, processor, and so on). The PCH asserts
PLTRST# during power-up and when S/W initiates a hard reset sequence
through the Reset Control register (I/O port CF9h). The PCH drives
PLTRST# active a minimum of 1 ms when initiated through the Reset
Control register (I/O port CF9h).
Note: PLTRST# is in the VccSUS3_3 well.
Platform Reset Processor: A 1.0 V copy of PLTRST# pin. This signal is
the main host platform reset and should directly connect to the processor
pin PLTRSTIN#. No on-board logic is required to level shift the voltage of
this signal.
Power Button: The Power Button will cause SMI# or SCI to indicate a
system request to go to a sleep state. If the system is already in a sleep
state, this signal will cause a wake event. If PWRBTN# is pressed for more
than 4 seconds, this will cause an unconditional transition (power button
override) to the S5 state. Override will occur even if the system is in the
S1–S4 states. This signal has an internal pull-up resistor and has an
internal 16 ms de-bounce on the input. This signal is in the DSW well.
Power OK: When asserted, PWROK is an indication to the PCH that all of
its core power rails have been stable for at least 5 ms. PWROK can be
driven asynchronously. When PWROK is negated, the PCH asserts
PLTRST#.
Notes:
1.It is required that the power rails associated with PCI/PCIe (typically
the 3.3 V, 5 V, and 12 V core well rails) have been valid for 99 ms
prior to PWROK assertion in order to comply with the 100 ms PCI 2.3/
PCIe* 2.0 specification on PLTRST# de-assertion.
2.PWROK must not glitch, even if RSMRST# is low.
Ring Indicate: This signal is an input from a modem. It can be enabled as
a wake event, and this is preserved across power failures.
Resume Well Reset: This signal is used for resetting the resume power
plane logic. This signal must be asserted for at least t201 after the suspend
power wells are valid. When de-asserted, this signal is an indication that
the suspend power wells are stable.
SLP_A#: This signal is used to control power to the active sleep well
(ASW) of the PCH.
LAN Sub-System Sleep Control: When SLP_LAN# is de-asserted, it
indicates that the PHY device must be powered. When SLP_LAN# is
asserted, power can be shut off to the PHY device. SLP_LAN# will always
be de-asserted in S0 and anytime SLP_A# is de-asserted.
Signal Description
88
Datasheet
Signal Description
Table 2-25. Power Management Interface Signals (Sheet 3 of 4)
NameTypeDescription
WLAN Sub-System Sleep Control: When SLP_WLAN# is asserted, power
can be shut off to the external wireless LAN device. SLP_WLAN# will always
SLP_WLAN#/
GPIO29
SLP_S3#O
SLP_S4#O
SLP_S5# / GPIO63 O
SLP_SUS#O
SUSACK#I
SUS_STAT# /
GPIO61
SUSCLK /GPIO62O
SUSWARN# /
SUSPWRDNACK /
GPIO30
will be de-asserted in S0.
Note: The selection between native and GPIO mode is based on a soft
O
O
O
strap. The soft strap default is '0', SLP_WLAN# mode. Even though
the pin is in the deep sleep well (DSW), the native and GPIO
functionality is only available when the SUS well is powered. Set
soft strap to ‘1’ to use the GPIO mode.
S3 Sleep Control: SLP_S3# is for power plane control. This signal shuts
off power to all non-critical systems when in S3 (Suspend To RAM), S4
(Suspend to Disk), or S5 (Soft Off) states.
S4 Sleep Control: SLP_S4# is for power plane control. This signal shuts
power to all non-critical systems when in the S4 (Suspend to Disk) or S5
(Soft Off) state.
Note: This pin must be used to control the DRAM power in order to use
the PCH’s DRAM power-cycling feature.
S5 Sleep Control: SLP_S5# is for power plane control. This signal is used
to shut power off to all non-critical systems when in the S5 (Soft Off)
states.
This pin may also be used as GPIO63.
DeepSx Indication: When asserted (driven low), this signal indicates the
PCH is in DeepSx state where internal Sus power is shut off for enhanced
power saving. When de-asserted (driven high), this signal indicates exit
from DeepSx state and Sus power can be applied to PCH. If DeepSx is not
supported, this pin can be left unconnected.
This pin is in the DSW power well.
SUSACK#: If DeepSx is supported, the EC/motherboard controlling logic
must change SUSACK# to match SUSWARN# once the EC/motherboard
controlling logic has completed the preparations discussed in the
description for the SUSWARN# pin.
Note: SUSACK# is only required to change in response to SUSWARN# if
DeepSx is supported by the platform.
This pin is in the Sus power well.
Suspend Status: This signal is asserted by the PCH to indicate that the
system will be entering a low power state soon. This can be monitored by
devices with memory that need to switch from normal refresh to suspend
refresh mode. It can also be used by other peripherals as an indication that
they should isolate their outputs that may be going to powered-off planes.
This pin may also be used as GPIO61.
Suspend Clock: This clock is an output of the RTC generator circuit to use
by other chips for refresh clock.
This pin may also be used as GPIO62.
SUSWARN#: This pin asserts low when the PCH is planning to enter the
DeepSx power state and remove Suspend power (using SLP_SUS#). The
EC/motherboard controlling logic must observe edges on this pin, preparing
for SUS well power loss on a falling edge and preparing for SUS well related
activity (host/Intel ME wakes and runtime events) on a rising edge.
SUSACK# must be driven to match SUSWARN# once the above preparation
is complete. SUSACK# should be asserted within a minimal amount of time
from SUSWARN# assertion as no wake events are supported if SUSWARN#
is asserted but SUSACK# is not asserted. Platforms supporting DeepSx, but
not wishing to participate in the handshake during wake and DeepSx entry
may tie SUSACK# to SUSWARN#.
This pin may be multiplexed with a GPIO for use in systems that do not
support DeepSx. This pin is multiplexed with SUSPWRDNACK since it is not
needed in DeepSx supported platforms.
Reset type: RSMRST#
This signal is multiplexed with GPIO30 and SUSPWRDNACK.
Datasheet89
Table 2-25. Power Management Interface Signals (Sheet 4 of 4)
NameTypeDescription
SUSPWRDNACK: Active high. Asserted by the PCH on behalf of the Intel
SUSPWRDNACK /
SUSWARN# / GPIO30
SYS_PWROKI
SYS_RESET#I
WAKE#I/OD
ME when it does not require the PCH Suspend well to be powered.
O
Platforms are not expected to use this signal when the PCH’s DeepSx
feature is used.
This signal is multiplexed with GPIO30 and SUSWARN#.
System Power OK: This generic power good input to the PCH is driven
and utilized in a platform-specific manner. While PWROK always indicates
that the core wells of the PCH are stable, SYS_PWROK is used to inform the
PCH that power is stable to some other system component(s) and the
system is ready to start the exit from reset.
System Reset: This signal forces an internal reset after being debounced.
The PCH will reset immediately if the SMBus is idle; otherwise, it will wait
up to 25 ms ±2 ms for the SMBus to idle before forcing a reset on the
system.
PCI Express* Wake Event in Sx: This signal is in DSW and behaves as
an input pin in Sx states. Sideband wake signal on PCI Express asserted by
components requesting wake up.
PCIe OBFF on this pin has been de-featured and is not supported.
2.25Power and Ground Signals
Signal Description
Table 2-26. Power and Ground Signals (Sheet 1 of 2)
NameDescription
DCPRTCDecoupling: This signal is for RTC decoupling only. The signal requires decoupling.
DCPSST
DCPSUS1
DCPSUS2
DCPSUS3
DCPSUSBYPDecoupling: This signal is for decoupling internally generated 1.05 V DeepSx only.
VCC
VCC3_33.3 V supply for core well I/O buffers.
VCCASW
Decoupling: Internally generated 1.5 V powered from Suspend Well. This signal
requires decoupling. Decoupling is required even if this feature is not used.
1.05 V Suspend well power.
If INTVRMEN is strapped high, power to this well is supplied internally and this pin
should be left as no connect.
If INTVRMEN is strapp ed low, pow er t o this well mu st be supplie d by an extern al 1.05 V
suspend rail.
Note: External VR mode applies to Mobile Only.
1.05 V Suspend well power for USB 2.0.
If INTVRMEN is strapped high, power to this well is supplied internally and this pin
should be left as no connect.
If INTVRMEN is strapp ed low, pow er t o this well mu st be supplie d by an extern al 1.05 V
suspend rail.
Note: External VR mode applies to Mobile Only.
1.05 V Suspend well power for USB 3.0.
If INTVRMEN is strapped high, power to this well is supplied internally and these pins
should be left as no connect.
If INTVRMEN is strapp ed low, pow er t o this well mu st be supplie d by an extern al 1.05 V
suspend rail.
Note: External VR mode applies to Mobile Only.
1.05 V supply for core well logic. This power may be shut off in S3, S4, S5, or G3
states.
1.05 V supply for the Active Sleep Well. Provides power to the Intel ME and integrated
LAN. This plane must be on in S0 and other times the Intel ME or integrated LAN is
used.
90
Datasheet
Signal Description
Table 2-26. Power and Ground Signals (Sheet 2 of 2)
NameDescription
3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power is not
VCCRTC
VCCIO
VccSUS3_3
VCCSUSHDASuspend supply for Intel HD Audio. This pin can be either 1.5 or 3.3 V.
VCCVRM
VCCADAC1_5
VCCADACBG3_3
VSSGround.
VCCCLK
VCCCLK3_3
V_PROC_IO
VCCDSW3_3
VCCSPI
VCCUSBPLL
expected to be shut off unless the RTC battery is removed or completely drained.
Note: Implementations should not attempt to clear CMOS by using a jumper to pull
1.05 V supply for I/O buffers. This power may be shut off in S3, S4, S5, Deep Sx or G3
states.
3.3 V supply for suspend well I/O buffers. This power may be shut off in DeepSx or G3
state.
1.5 V supply for internal VRMs. This power may be shut off in S3, S4, S5, Deep Sx, or
G3 states.
1.5 V supply for Display DAC Analog Power. This power may be shut off in S3, S4, S5,
Deep Sx, or G3 states.
3.3 V s upply fo r D isplay D AC Band Gap . This po we r may be s hu t off in S 3, S4, S5, Dee p
Sx, or G3 states.
1.0 5V Analog pow er supply f or interna l c lock PLL. T his power m ay be shut o ff in S3, S4,
S5, Deep Sx, or G3 states.
3.3 V Analog power supply for internal clock PLL. This power may be shut off in S3, S4,
S5, Deep Sx, or G3 states.
1.05V supply for processor interface signals. This power may be shut off in S3, S4, S5,
Deep Sx, or G3 states. Connect to the same supply as the PCH VCCIO; do not tie this
signal to the processor.
3.3 V supply for DeepSx wells. If the platform does not support Deep Sx, then tie to
VccSUS3_3.
3.3 V supply for SPI Controller Logic. This rail must be powered when VccASW is
powered.
Note: This rail can be optionally powered on 3.3 V Suspend power (VccSUS3_3)
1.05V Analog power supply for USB PLL. This power may be shut off in S3, S4, S5,
Deep Sx, or G3 states.
VccRTC low. Clearing CMOS can be done by using a jumper on RTCRST# or
GPI.
based on platform needs.
2.26Thermal Signals
Table 2-27. Thermal Signals (Sheet 1 of 2)
Signal NameTypeDescription
PWM[3:0] OD OFan Pulse Width Modulation Outputs: These signals are Pulse Width
Datasheet91
Modulated duty cycle output signals used for fan control.
These signals are 3.3 V tolerant.
Note: TACH signals used on Server/Workstation Only; not supported on
SST I/OSimple Serial Transport: Single- wir e, ser ia l bu s. C onnec t th is sig nal to SST
PECII/OPlatform Environment Control Interface: Single-wire, serial bus.
TD_IREFI
IFan Tachometer Inputs: Tachometer pulse input signal that is used to
measure fan speed. This signal is connected to the “Sense” signal on the fan.
The signals can instead be used as a GPIO.
Note: TACH signals used on Server/Workstation Only; not supported on
Mobile and Desktop.
compliant devices such as SST thermal sensors or voltage sensors.
Note: TACH signals used on Server/Workstation Only; not supported on
Mobile and Desktop.
Internal Reference Voltage: Thermal sensor low-cap analog reference
bias current. This should be connected to Vss (ground) using an external
resistor of 8.2 K.
2.27Miscellaneous Signals
Signal Description
Table 2-28. Miscellaneous Signals (Sheet 1 of 2)
NameTypeDescription
Internal Voltage Regulator Enable: When pulled high, this signal enables
the internal 1.05 V regulators for the Suspend well in the PCH. This signal must
INTVRMENI
DSWVRMENI
SPKRO
RTCRST#I
SRTCRST#I
SML1ALERT#/
TEMP_ALERT#/
GPIO74
remain asserted for the VRMs to behave properly (no glitches allowed).
This signal must be pulled-up to VCCRTC on desktop platforms and may
optionally be pulled low on mobile platforms if using an external VR for the
VCCSUS rail.
DeepSx Well Internal Voltage Regulator Enable: This signal enables the
internal DSW 1.05 V regulators and must be always pulled-up to VCCRTC.
Speaker: The SPKR signal is the output of counter 2 and is internally “ANDed”
with Port 61h Bit 1 to provide Speaker Data Enable. This signal drives an
external speaker driver device, which in turn drives the system speaker. Upon
PLTRST#, its output state is 0.
Note: SPKR is sampled as a functional strap. There is a weak integrated pull-
down resistor on SPKR pin.
RTC Reset: When asserted, this signal resets register bits in the RTC well.
Notes:
1.Unless CMOS is being cleared (only to be done in the G3 power state), the
RTCRST# input must always be high when all other RTC power planes are
on.
2.In the case where the RTC battery is dead or missing on the platform, the
RTCRST# pin must rise before the DPWROK pin.
Secondary RTC Reset: This signal resets the manageability register bits in
the RTC well when the RTC battery is removed.
Notes:
1.The SRTCRST# input must always be high when all other RTC power
planes are on.
2.In the case where the RTC battery is dead or missing on the platform, the
SRTCRST# pin must rise before the RSMRST# pin.
TEMP_ALERT#: This signal is used to indicate a PCH temperature out of
bounds condition to an external EC, when PCH temperature is greater than
value programmed by BIOS. An external pull-up resistor is required on this
signal.
OD
Note: A soft-strap determines the native function SML1ALERT# or
TEMP_ALERT# usage. When soft-strap is 0, function is SML1ALERT#,
when soft-strap is 1, function is TEMP_ALERT#.
92
Datasheet
Signal Description
Table 2-28. Miscellaneous Signals (Sheet 2 of 2)
NameTypeDescription
GPIO35 / NMI#
(Server /
Workstation Only)
PCIECLKRQ2# /
GPIO20 / SMI#
(Server /
Workstation Only)
PME#I/OD
OD O NMI#: This is an NMI event indication to an external controller (such as a
BMC) on server/workstation platforms.
When operating as NMI event indication pin function (enabled when “NMI SMI
Event Native GPIO Enable” soft strap [PCHSTRP9:bit 16] is set to 1), the pin is
OD (open drain).
OD O SMI#: This is an SMI event indication to an external controller (such as a BMC)
on server/workstation platforms.
When operating as SMI event indication pin function (enabled when “NMI SMI
Event Native GPIO Enable” soft strap [PCHSTRP9:bit 16] is set to 1), the pin is
OD (open drain).
PCI Power Management Event: PCI peripherals drive PME# to wake the
system from low-power states S1–S5. PME# assertion can also be enabled to
generate an SCI from the S0 state. In some cases the PCH may drive PME#
active due to an internal wake event. The PCH will not drive PME# high, but it
will be pulled up to VccSUS3_3 by an internal pull-up resistor.
PME# is still functional and can be used with PCI legacy mode on platforms
using a PCIe-to-PCI bridge. Downstream PCI devices would need to have PME#
routed from the connector to the PCH PME# pin.
2.28Testability Signals
Table 2-29. Testability Signals
NameTypeDescription
JTAG_TCK I
JTAG_TMS I
JTAG_TDI I
JTAG_TDO OD
Note: JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE
Std. 1149.1-2001)
Test Clock Input (TCK): The test clock input provides the clock
for the JTAG test logic.
Test Mode Select (TMS): The signal is decoded by the Test
Access Port (TAP) controller to control test operations.
Test Data Input (TDI): Serial test instructions and data are received by
the test logic at TDI.
Test Data Output (TDO): TDO is the serial output for test
instructions and data from the test logic defined in this standard.
2.29Reserved / Test Pins
Table 2-30. Test Pins (Sheet 1 of 2)
NameDescription
TP1
TP2
TP3 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP4
TP5
TP6
TP7 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP8
TP9
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Datasheet93
Table 2-30. Test Pins (Sheet 2 of 2)
NameDescription
TP10
TP11 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP12
TP13
TP14
TP15 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP16
TP17
TP18
TP19 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP20
TP21
TP22
TP23 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP24
TP25
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Must have a pull-up resistor to VCC3_3. Standard resistor
value in the range of 4.7 K to 15 K
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Signal Description
Note: The Test Point descriptions provided in this table apply to both Desktop and Mobile packages.
§ §
94
Datasheet
PCH Pin States
3PCH Pin States
3.1Integrated Pull-Ups and Pull-Downs
Table 3-1.Integrated Pull-Up and Pull-Down Resistors (Sheet 1 of 2)
1.Simulation data shows that these resistor values can range from 10 k to 45 k.
2.Simulation data shows that these resistor values can range from 9 k to 50 k.
3.Simulation data shows that these resistor values can range from 15 k to 40 k.
4.Simulation data shows that these resistor values can range from 14.25 k to 24.8 k.
5.GPIO16 has two native functions – the 1st native function (SATAP4_PCIEP1_SELECT) is selected if the Flex
I/O soft strap SATAP4_PCIEP1_MODE = 11b and takes precedence over any other assignments to this pin
(that is, if this is selected, writes to GPIO_USE_SEL are ignored). If SATAP4_PCIEP1_MODE is not set to
11b, the GPIO_USE_SEL register can be used to select the 2nd native function (SATA4GP) or GPIO
functionality. Setting SATAP4_PCIEP1_MODE = 11b also enables an internal pull-up resistor in this pin to
allow Flexible I/O selection of SATA Port 4 or PCIe Port 1 to be done based on the type of card installed (If
sampled value = 1, select SATA; if sampled value = 0, select PCIe). The same behavior is true of pin
SATA5GP/GPIO49 when the soft strap SATAP5_PCIEP2_MODE = 11b. Soft straps are handled through FITc.
6.When operating as NMI# event indication pin function, the pin is open drain but the PCH provides an
internal pull-up to ensure the pin does not float.
7.This signal is a PCH functional strap; the pull-up or pull-down on this signal is disabled after it is sampled as
a PCH functional strap.
8.This signal has a weak internal pull-up that is always on.
9.9When operating as SMI# event indication pin function, the pin is open drain but the PCH provides an
internal pull-up to ensure the pin does not float.
10. The pull-down is disabled after the pins are driven strongly to logic 0 when PWROK is asserted.
11. The pull-up or pull-down on this signal is disabled after RSMRST# de-asserts. This pin is not a functional
strap.
12. The internal pull-down on HDA_SYNC and HDA_SDO is enabled during reset.
13. The Controller Link Clock and Data buffers use internal pull-up or pull-down resistors to drive a logical 1 or
0.
14. Termination resistors may be present if signal is enabled (that is, related Port is not disabled). These
resistors appear to be strong pull-downs or pull-ups on the signals.
15. Internal pull-down resistor may be enabled in Deep Sx mode based on DSX_CFG configuration bit, as
follows: ‘1’ (pin will be driven by platform in Deep Sx) -> Z; - ‘0’ (pin will NOT be driven by platform in
Deep Sx) -> Internal pull-down. Refer to DSX_CFG register (RCBA+3334h) for more details.
16. When the interface is in BUS IDLE, the internal pull-down of 10 k is enabled. In normal transmission, a
400 pull-down takes effect, the signal will be overridden to logic 1 with pull-up resistor (37 ) to VCC
1.5 V.
17. This is a 350- normal pull-down, signal will be overridden to logic 1 with pull-up resistor (31 ) to VCC
1.05 V.
18. N/A
19. Regardless of internal pull-up or pull-down, an external pull-up resistor is still required.
20. External pull-up if Intel wired LAN is present (pull-up to SUS/DSW based on deepest wake on LAN support
desired).
21. N/A
22. Weak internal pull-up resistor is enabled when APWROK is de-asserted and is switched to a weak internal
pull-down resistor when APWROK and PLTRST# are both asserted.
23. Signals are tri-stated with weak pull-up resistors when APWROK is de-asserted. SPI_CS1# remains tristated with a weak pull-up resistor when APWROK and PLTRST# are both asserted.
24. Some signals may not be available in all SKUs. Check signal and SKU descriptions.
Pull-down20K1, 10
Pull-up20K3
Pull-up or
Pull-down
Pull-up or
Pull-down
5014
5014
PCH Pin States
96
Datasheet
PCH Pin States
3.2Output Signals Planes and States
Table 3-2 shows the power plane associated with the output and I/O signals, as well as
the state at various times. Within the table, the following terms are used:
“DL”PCH drives low.
“DH”PCH drives high.
“IPU”Internal pull-up.
“IPD”Internal pull-down.
“T”Toggling or signal is transitioning because function not stopping.
“High-Z”Tri-state. PCH not driving the signal high or low.
“Defined”Driven to a level that is defined by the function or external pull-
up/pull-down resistor (will be high or low).
“Off”The power plane is off; PCH is not driving when configured as an
Note:Pin state within table assumes interfaces are idle and default pin configuration for
different power states.
output or sampling when configured as an input.
Signal levels are the same in S3, S4 and S5, except as noted.
In general, PCH suspend well signal states are indeterminate and undefined and may
glitch prior to RSMRST# de-assertion.
PCH core well signal states are indeterminate and undefined and may glitch prior to
PWROK assertion. However, this does not apply to THRMTRIP# as this signal is
determinate and defined prior to PWROK assertion.
DSW indicates PCH Deep Sx Well. This state provides a few wake events and critical
context to allow system to draw minimal power in S3, S4 or S5 states. In general, PCH
DSW signal states are indeterminate, undefined and may glitch prior to DPWROK
assertion. The signals that are determinate and defined prior to DPWROK assertion will
have a note added as a reference.
ASW indicates PCH Active Sleep Well. This power well contains functionality associated
with active usage models while the host system is in Sx.
Datasheet97
PCH Pin States
Table 3-2.Output Signals – Power Plane and States in Desktop, Mobile, and Server
Configurations (Sheet 1 of 4)
Immediately
Signal NamePower Plane During Reset
USB2p/n[13:0]SuspendIPDIPDIPDOff
USB3Tp/n[4:3]
PETp/n[2:1]
24
n[6:5, 2:1]
, USB3Tp/
SuspendIPD
24
Suspend or
Core5
PETp/n[8:3]Core IPD
SATA_TXp/n[3:0]CoreIPU
SATA_TXp/n[5:4]
24
CoreIPU1 IPU1 OffOff
SATALED#CoreHigh-ZHigh-ZOffOff
SCLOCKCoreHigh-ZHigh-ZOffOff
SLOADCoreHigh-ZHigh-ZOffOff
SDATAOUT[1:0]CoreHigh-ZHigh-ZOffOff
CLKOUT_ITPXDP_P/N
Core
T (platform
dependent)
CLKOUT_DP_P/NCoreTTOffOff
CLKOUT_DPNS_P/NCoreTTOffOff
CLKOUT_DMI_P/NCoreTTOffOff
XTAL25_OUTCoreHigh-ZHigh-ZOffOff
CLKOUT_PEG_A_P/NCoreTTOffOff
CLKOUT_PEG_B_P/NCoreTTOffOff
CLKOUT_PCIE_P/N[7:0]CoreTTOffOff
CLKOUT_33MHZ[4:0]CoreTTOffOff
CLKOUTFLEX[3:0]
Core
T (platform
dependent)
DIFFCLK_BIASREF Core High-ZHigh-ZOffOff
ICLK_IREFCoreHigh-ZHigh-ZOffOff
Interrupt Interface
SERIRQCoreHigh-ZHigh-ZOffOff
PIRQ[D:A]#CoreHigh-ZHigh-ZOffOff
PIRQ[H:E]#CoreHigh-ZHigh-ZOffOff
9
NMI#
CoreIPUIPUOffOff
Processor Interface
PROCPWRGDCoreDLDHOffOff
PMSYNCHCoreDLDLOffOff
23
after Reset
23
S3/S4/S5Deep Sx
USB Interface
1
IPD1
S3 High-Z
S4 and S5 Off
PCI Express*
IPD1 IPD1 OffOff
1
IPD1 OffOff
SATA Interface
1
IPU1 OffOff
Clocking Signals
T (platform
dependent)
T (platform
dependent)
OffOff
OffOff
Off
98
Datasheet
PCH Pin States
Table 3-2.Output Signals – Power Plane and States in Desktop, Mobile, and Server
Configurations (Sheet 2 of 4)
Immediately
Signal NamePower Plane During Reset
DMI_TXp/n[3:0]CoreIPU or IPD
®
Intel
Flexible Display Interface (Intel® FDI)
FDI_CSYNCCoreHigh-Z
FDI_INTCoreHigh-Z
Analog Display / VGA DAC Signals
VGA_RED, VGA_GREEN,
VGA_BLUE
CoreHigh-ZHigh-ZOffOff
DAC_IREFCoreHigh-ZDLOffOff
VGA_HSYNCCoreDLDLOffOff
VGA_VSYNCCoreDLDLOffOff
VGA_DDC_CLKCoreHigh-ZHigh-ZOffOff
VGA_DDC_DATACoreHigh-ZHigh-ZOffOff
VGA_IRTNCoreHigh-ZHigh-ZOffOff
Digital Display Interface
DDP[D:B]_AUXP/NCoreIPDIPDOffOff
DDPB_CTRLCLK,
DDPC_CTRLCLK,
CoreHigh-ZHigh-ZOffOff
DDPD_CTRLCLK
DDPB_CTRLDATA,
DDPC_CTRLDATA,
CoreIPD
DDPD_CTRLDATA
eDP_VDD_ENCoreDLDLOffOff
eDP_BKLTENCoreDLDLOffOff
eDP_BKLTCTLCoreDLDLOffOff
®
Intel
High Definition Audio Interface (Intel® HD Audio)
HDA_RST#
HDA_BCLK
HDA_SYNC
HDA_SDO
HDA_DOCK_EN#
HDA_DOCK_RST#
4
,
4
26
,
26
10
10
SuspendDLDLDLOff
SuspendIPDIPDIPDOff
CoreIPDIPDOffOff
Suspend
25
High-ZHigh-Z
LAD[3:0] CoreIPU IPUOffOff
LFRAME# CoreDHDHOffOff
Non-Multiplexed GPIO Signals
5
GPIO8
GPIO15
GPIO24
5, 9
9
SuspendIPUDHDHOff
SuspendDLDLDLOff
SuspendDLDLDLOff
23
DMI
1, 21
2
2
3
LPC Interface
after Reset
IPU or IPD
2
High-Z
2
High-Z
23
1, 21
S3/S4/S5Deep Sx
OffOff
OffOff
OffOff
High-ZOffOff
8
High-Z
8
Off
Datasheet99
PCH Pin States
Table 3-2.Output Signals – Power Plane and States in Desktop, Mobile, and Server
Configurations (Sheet 3 of 4)
Immediately
Signal NamePower Plane During Reset
9
GPIO28
CLKRUN#
SuspendDLDLDLOff
Core
DL (Mobile);
DH (Desktop)
GPIO[53, 51]CoreIPUDHOffOff
GPIO55CoreIPUDLDLOff
SMBCLK, SMBDATASuspendHigh-ZHigh-ZHigh-ZOff
System Management Interface
SML0DATASuspendHigh-ZHigh-ZHigh-ZOff
SML0CLKSuspendHigh-ZHigh-ZHigh-ZOff
SML0ALERT# SuspendHigh-ZHigh-Z
SML1ALERT#SuspendHigh-ZHigh-ZHigh-ZOff
SML1CLKSuspendHigh-ZHigh-ZHigh-ZOff
SML1DATASuspendHigh-ZHigh-ZHigh-ZOff
CL_RST#
CL_CLK
CL_DATA
11
11
11
SuspendDLDHDHOff
SuspendTerminated12Terminated12IPDOff
SuspendTerminated12Terminated12IPDOff
SPI_CLKASWDLDLDLOff
SPI_CS0#ASWDHDHDHOff
SPI_CS1#ASWIPUDHDHOff
SPI_CS2#ASWDHDHDHOff
SPI_MOSIASWIPDDLDLOff
SPI_MISOASWIPUIPUIPUOff
SPI_IO2ASWIPUIPUIPUOff
SPI_IO3ASWIPUIPUIPUOff
Power Management
DRAMPWROK
9
SuspendDLHigh-Z
LAN_PHY_PWR_CTRLDSWDLDLDLDL
PLTRST#SuspendDLDHDLOff
PLTRST_PROC#CoreDLDHDLOff
9, 11
SLP_A#
SLP_LAN#
9
DSWDLDHDHDL
DSWDLDLDL/DH
SLP_WLAN#9 DSWDLDLDL/DH
SLP_S3#
SLP_S4#
9
9
DSWDLDHDLDL
DSWDLDH
23
after Reset
DH (Desktop)
SMBus Interface
Controller Link
SPI Interface
DL (Mobile);
7
23
S3/S4/S5Deep Sx
OffOff
High-ZOff
S3 High-Z,
S4 and S5 DL
16
16
S3 DH,
S4 and S5 DL
DL/DH
DL/DH
DL/DH
Off
16
16
17
100
Datasheet
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