Intel C220 Datasheet

Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH)

Datasheet

May 2014

328904-003

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2 Datasheet

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Contents

1Introduction............................................................................................................ 41

1.1 About This Manual............................................................................................. 41

1.1.1 Chapter Descriptions ............................................................................. 42

1.2 Overview ......................................................................................................... 44

1.2.1 Capability Overview............................................................................... 45

1.3 Intel

1.4 Device and Revision ID Table.............................................................................. 57

2 Signal Description ................................................................................................... 60

2.1 Flexible I/O ...................................................................................................... 62

2.2 USB Interface ................................................................................................... 63

2.3 PCI Express* .................................................................................................... 66

2.4 Serial ATA Interface........................................................................................... 67

2.5 Clock Signals .................................................................................................... 69

2.6 Real Time Clock Interface................................................................................... 70

2.7 External RTC Circuitry........................................................................................ 71

2.8 Interrupt Interface ............................................................................................ 71

2.9 Processor Interface............................................................................................ 72

2.10 Direct Media Interface (DMI) to Host Controller ..................................................... 72

2.11 Intel

2.12 Analog Display/VGA DAC Signals......................................................................... 73

2.13 Digital Display Signals........................................................................................ 73

2.14 Embedded DisplayPort* (eDP*) Backlight Control Signals ....................................... 74

2.15 Intel® High Definition Audio (Intel® HD Audio) Link ............................................... 74

2.16 Low Pin Count (LPC) Interface............................................................................. 75

2.17 General Purpose I/O Signals ............................................................................... 75

2.18 Functional Straps .............................................................................................. 81

2.19 SMBus Interface................................................................................................ 84

2.20 System Management Interface............................................................................ 85

2.21 Controller Link .................................................................................................. 85

2.22 Serial Peripheral Interface (SPI) .......................................................................... 85

2.23 Manageability Signals ........................................................................................ 86

2.24 Power Management Interface.............................................................................. 87

2.25 Power and Ground Signals.................................................................................. 90

2.26 Thermal Signals ................................................................................................ 91

2.27 Miscellaneous Signals ........................................................................................ 92

2.28 Testability Signals ............................................................................................. 93

2.29 Reserved / Test Pins .......................................................................................... 93

3PCH Pin States......................................................................................................... 95

3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 95

3.2 Output Signals Planes and States ........................................................................ 97

3.3 Input and I/O Signals Planes and States............................................................. 102

4 PCH and System Clocks ......................................................................................... 107

4.1 Straps Related to Clock Configuration ................................................................ 107

4.2 Platform Clocking Requirements ........................................................................ 107

4.3 Functional Blocks ............................................................................................ 109

4.4 Clock Configuration Access Overview ................................................................. 111

5 Functional Description........................................................................................... 112

5.1 Flexible I/O .................................................................................................... 112

5.2 PCI-to-PCI Bridge............................................................................................ 113

5.3 PCI Express* Root Ports (D28:F0~F7)................................................................ 113

8 Series/C220 Series Chipset Family PCH SKU Definition ............................... 52

Flexible Display Interface (Intel® FDI) ........................................................ 73

5.2.1 PCI Bus Interface................................................................................ 113

5.2.2 PCI Legacy Mode................................................................................. 113

5.3.1 Supported PCI Express* (PCIe*) Port Configurations................................ 114

5.3.2 Interrupt Generation ........................................................................... 114

5.3.3 Power Management............................................................................. 115

5.3.3.1 S3/S4/S5 Support................................................................. 115

5.3.3.2 Resuming from Suspended State............................................. 115

5.3.3.3 Device Initiated PM_PME Message ........................................... 115

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5.3.3.4 SMI/SCI Generation...............................................................116

5.3.3.5 Latency Tolerance Reporting (LTR) .......................................... 116

5.3.3.6 Opportunistic Buffer Flush/Fill (OBFF)....................................... 116

5.3.4 SERR# Generation...............................................................................116

5.3.5 Hot-Plug............................................................................................. 117

5.3.5.1 Presence Detection ................................................................117

5.3.5.2 SMI/SCI Generation...............................................................117

5.4 Gigabit Ethernet Controller (B0:D25:F0) .............................................................118

5.4.1 GbE PCI Express* Bus Interface ............................................................120

5.4.1.1 Transaction Layer..................................................................120

5.4.1.2 Data Alignment .....................................................................120

5.4.1.3 Configuration Request Retry Status..........................................120

5.4.2 Error Events and Error Reporting ........................................................... 121

5.4.2.1 Data Parity Error ...................................................................121

5.4.2.2 Completion with Unsuccessful Completion Status ....................... 121

5.4.3 Ethernet Interface ............................................................................... 121

5.4.3.1 Intel® Ethernet Network Connection I127LM/V Platform LAN 

Connect Device Interface........................................................121

5.4.4 PCI Power Management........................................................................122

5.4.4.1 Wake Up ..............................................................................122

5.4.5 Configurable LEDs ...............................................................................124

5.4.6 Function Level Reset Support (FLR)........................................................ 125

5.4.6.1 FLR Steps............................................................................. 125

5.5 Low Pin Count (LPC) Bridge (with System and 

Management Functions) (D31:F0)...................................................................... 126

5.5.1 LPC Interface ......................................................................................126

5.5.1.1 LPC Cycle Types ....................................................................127

5.5.1.2 Start Field Definition ..............................................................127

5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR)...................................127

5.5.1.4 Size..................................................................................... 128

5.5.1.5 SYNC ................................................................................... 128

5.5.1.6 SYNC Time-Out .....................................................................128

5.5.1.7 SYNC Error Indication ............................................................129

5.5.1.8 LFRAME# Usage.................................................................... 129

5.5.1.9 I/O Cycles ............................................................................129

5.5.1.10 Bus Master Cycles .................................................................129

5.5.1.11 LPC Power Management .........................................................129

5.5.1.12 Configuration and PCH Implications .........................................130

5.6 DMA Operation (D31:F0) ..................................................................................130

5.6.1 Channel Priority................................................................................... 131

5.6.1.1 Fixed Priority ........................................................................131

5.6.1.2 Rotating Priority ....................................................................131

5.6.2 Address Compatibility Mode ..................................................................131

5.6.3 Summary of DMA Transfer Sizes............................................................ 132

5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count 

by Words .............................................................................132

5.6.4 Autoinitialize.......................................................................................132

5.6.5 Software Commands............................................................................133

5.7 Low Pin Count (LPC) DMA .................................................................................133

5.7.1 Asserting DMA Requests....................................................................... 133

5.7.2 Abandoning DMA Requests ...................................................................134

5.7.3 General Flow of DMA Transfers..............................................................134

5.7.4 Terminal Count ...................................................................................135

5.7.5 Verify Mode ........................................................................................ 135

5.7.6 DMA Request De-assertion....................................................................135

5.7.7 SYNC Field / LDRQ# Rules ....................................................................136

5.8 8254 Timers (D31:F0) ...................................................................................... 136

5.8.1 Timer Programming ............................................................................. 137

5.8.2 Reading from the Interval Timer............................................................ 138

5.8.2.1 Simple Read ......................................................................... 138

5.8.2.2 Counter Latch Command ........................................................ 138

5.8.2.3 Read Back Command .............................................................139

5.9 8259 Programmable Interrupt Controllers (PIC) (D31:F0) ..................................... 139

5.9.1 Interrupt Handling ............................................................................... 140

5.9.1.1 Generating Interrupts ............................................................140

5.9.1.2 Acknowledging Interrupts ....................................................... 140

5.9.1.3 Hardware/Software Interrupt Sequence....................................141

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5.9.2 Initialization Command Words (ICWx).................................................... 141

5.9.2.1 ICW1 .................................................................................. 141

5.9.2.2 ICW2 .................................................................................. 142

5.9.2.3 ICW3 .................................................................................. 142

5.9.2.4 ICW4 .................................................................................. 142

5.9.3 Operation Command Words (OCW)........................................................ 142

5.9.4 Modes of Operation ............................................................................. 143

5.9.4.1 Fully Nested Mode................................................................. 143

5.9.4.2 Special Fully-Nested Mode...................................................... 143

5.9.4.3 Automatic Rotation Mode (Equal Priority Devices)...................... 143

5.9.4.4 Specific Rotation Mode (Specific Priority) .................................. 143

5.9.4.5 Poll Mode ............................................................................. 144

5.9.4.6 Edge and Level Triggered Mode............................................... 144

5.9.4.7 End of Interrupt (EOI) Operations ........................................... 144

5.9.4.8 Normal End of Interrupt......................................................... 144

5.9.4.9 Automatic End of Interrupt Mode............................................. 145

5.9.5 Masking Interrupts .............................................................................. 145

5.9.5.1 Masking on an Individual Interrupt Request.............................. 145

5.9.5.2 Special Mask Mode................................................................ 145

5.9.6 Steering PCI Interrupts........................................................................ 145

5.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 146

5.10.1 Interrupt Handling............................................................................... 146

5.10.2 Interrupt Mapping ............................................................................... 146

5.10.3 PCI / PCI Express* Message-Based Interrupts......................................... 147

5.10.4 IOxAPIC Address Remapping ................................................................ 147

5.10.5 External Interrupt Controller Support..................................................... 147

5.11 Serial Interrupt (D31:F0) ................................................................................. 148

5.11.1 Start Frame........................................................................................ 148

5.11.2 Data Frames ...................................................................................... 148

5.11.3 Stop Frame ........................................................................................ 149

5.11.4 Specific Interrupts Not Supported Using SERIRQ ..................................... 149

5.11.5 Data Frame Format ............................................................................. 149

5.12 Real Time Clock (D31:F0)................................................................................. 150

5.12.1 Update Cycles..................................................................................... 151

5.12.2 Interrupts .......................................................................................... 151

5.12.3 Lockable RAM Ranges .......................................................................... 151

5.12.4 Century Rollover ................................................................................. 151

5.12.5 Clearing Battery-Backed RTC RAM......................................................... 151

5.13 Processor Interface (D31:F0) ............................................................................ 153

5.13.1 Processor Interface Signals and VLW Messages ....................................... 153

5.13.1.1 INIT (Initialization)................................................................ 153

5.13.1.2 FERR# (Numeric Coprocessor Error) ........................................ 153

5.13.1.3 NMI (Non-Maskable Interrupt) ................................................ 154

5.13.1.4 Processor Power Good (PROCPWRGD)...................................... 154

5.13.2 Dual-Processor Issues.......................................................................... 154

5.13.2.1 Usage Differences ................................................................. 154

5.13.3 Virtual Legacy Wire (VLW) Messages ..................................................... 154

5.14 Power Management ......................................................................................... 155

5.14.1 Features ............................................................................................ 155

5.14.2 PCH and System Power States .............................................................. 155

5.14.3 System Power Planes........................................................................... 157

5.14.4 SMI# / SCI Generation ........................................................................ 157

5.14.4.1 PCI Express* SCI.................................................................. 160

5.14.4.2 PCI Express* Hot-Plug........................................................... 160

5.14.5 C-States ............................................................................................ 160

5.14.6 Dynamic 33 MHz Clock Control (Mobile Only).......................................... 160

5.14.6.1 Conditions for Checking the 33 MHz Clock ................................ 161

5.14.6.2 Conditions for Maintaining the 33MHz Clock.............................. 161

5.14.6.3 Conditions for Stopping the 33MHz Clock ................................. 161

5.14.6.4 Conditions for Re-Starting the 33MHz Clock.............................. 161

5.14.6.5 LPC Devices and CLKRUN#..................................................... 161

5.14.7 Sleep States....................................................................................... 162

5.14.7.1 Sleep State Overview ............................................................ 162

5.14.7.2 Initiating Sleep State ............................................................. 162

5.14.7.3 Exiting Sleep States .............................................................. 162

5.14.7.4 PCI Express* WAKE# Signal and PME Event Message................. 164

5.14.7.5 Sx-G3-Sx, Handling Power Failures.......................................... 164

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5.14.8 Event Input Signals and Their Usage......................................................166

5.14.7.6 Deep Sx...............................................................................165

5.14.8.1 PWRBTN# (Power Button) ......................................................166

5.14.8.2 RI# (Ring Indicator) ..............................................................167

5.14.8.3 PME# (PCI Power Management Event) .....................................168

5.14.8.4 SYS_RESET# Signal...............................................................168

5.14.8.5 THRMTRIP# Signal ................................................................168

5.14.9 ALT Access Mode.................................................................................169

5.14.9.1 Write Only Registers with Read Paths in ALT Access Mode ........... 170

5.14.9.2 PIC Reserved Bits..................................................................171

5.14.9.3 Read Only Registers with Write Paths in ALT Access Mode ........... 171

5.14.10 System Power Supplies, Planes, and Signals ...........................................172

5.14.10.1 Power Plane Control with SLP_S3#, 

SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN#.............................172

5.14.10.2 SLP_S4# and Suspend-To-RAM Sequencing .............................. 172

5.14.10.3 PWROK Signal.......................................................................173

5.14.10.4 BATLOW# (Battery Low) (Mobile Only).....................................173

5.14.10.5 SLP_LAN# Pin Behavior..........................................................173

5.14.10.6 SLP_WLAN# Pin Behavior ....................................................... 175

5.14.10.7 SUSPWRDNACK/SUSWARN#/GPIO30 Steady State Pin Behavior ..175

5.14.10.8 RTCRST# and SRTCRST# ....................................................... 176

5.14.11 Legacy Power Management Theory of Operation ......................................176

5.14.11.1 APM Power Management (Desktop Only) ..................................176

5.14.11.2 Mobile APM Power Management (Mobile Only) ........................... 176

5.14.12 Reset Behavior....................................................................................177

5.15 System Management (D31:F0) ..........................................................................178

5.15.1 Theory of Operation.............................................................................179

5.15.1.1 Detecting a System Lockup.....................................................179

5.15.1.2 Handling an Intruder.............................................................. 179

5.15.1.3 Detecting Improper Flash Programming....................................180

5.15.1.4 Heartbeat and Event Reporting using SMLink/SMBus..................180

5.15.2 TCO Modes .........................................................................................180

5.15.2.1 TCO Legacy / Compatible Mode ...............................................180

5.15.2.2 Advanced TCO Mode ..............................................................181

5.16 General Purpose I/O (D31:F0)...........................................................................182

5.16.1 Power Wells........................................................................................182

5.16.2 SMI#, SCI, and NMI Routing.................................................................182

5.16.3 Triggering ..........................................................................................183

5.16.4 GPIO Registers Lockdown .....................................................................183

5.16.5 Serial POST Codes over GPIO................................................................183

5.16.5.1 Theory of Operation...............................................................184

5.16.5.2 Serial Message Format ...........................................................185

5.17 SATA Host Controller (D31:F2, F5)..................................................................... 186

5.17.1 SATA 6 Gb/s Support ........................................................................... 186

5.17.2 SATA Feature Support..........................................................................186

5.17.3 Theory of Operation.............................................................................187

5.17.3.1 Standard ATA Emulation.........................................................187

5.17.3.2 48-Bit LBA Operation .............................................................188

5.17.4 SATA Swap Bay Support.......................................................................188

5.17.5 Hot-Plug Operation .............................................................................. 188

5.17.6 Intel

Rapid Storage Technology (Intel RST®) Configuration..................... 188

5.17.6.1 Intel® Rapid Storage Technology (Intel® RST) RAID Option ROM . 189

5.17.7 Intel® Smart Response Technology........................................................ 189

5.17.8 Power Management Operation...............................................................189

5.17.8.1 Power State Mappings............................................................190

5.17.8.2 Power State Transitions..........................................................190

5.17.8.3 SMI Trapping (APM)...............................................................191

5.17.9 SATA Device Presence..........................................................................191

5.17.10 SATA LED...........................................................................................192

5.17.11 AHCI Operation ................................................................................... 192

5.17.12 SGPIO Signals.....................................................................................193

5.17.12.1 Mechanism ........................................................................... 193

5.17.12.2 Message Format....................................................................194

5.17.12.3 LED Message Type.................................................................194

5.17.12.4 SGPIO Waveform ..................................................................196

5.17.13 External SATA.....................................................................................197

5.18 High Precision Event Timers (HPET)....................................................................197

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5.18.1 Timer Accuracy................................................................................... 197

5.18.2 Interrupt Mapping ............................................................................... 197

5.18.3 Periodic versus Non-Periodic Modes ....................................................... 199

5.18.4 Enabling the Timers............................................................................. 199

5.18.5 Interrupt Levels .................................................................................. 200

5.18.6 Handling Interrupts ............................................................................. 200

5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors............................. 200

5.19 USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. 201

5.19.1 EHC Initialization ................................................................................ 201

5.19.1.1 BIOS Initialization ................................................................. 201

5.19.1.2 Driver Initialization................................................................ 201

5.19.1.3 EHC Resets .......................................................................... 201

5.19.2 Data Structures in Main Memory ........................................................... 201

5.19.3 USB 2.0 Enhanced Host Controller DMA ................................................. 202

5.19.4 Data Encoding and Bit Stuffing.............................................................. 202

5.19.5 Packet Formats................................................................................... 202

5.19.6 USB 2.0 Interrupts and Error Conditions................................................. 202

5.19.6.1 Aborts on USB 2.0-Initiated Memory Reads .............................. 203

5.19.7 USB 2.0 Power Management................................................................. 203

5.19.7.1 Pause Feature ...................................................................... 203

5.19.7.2 Suspend Feature................................................................... 203

5.19.7.3 ACPI Device States................................................................ 203

5.19.7.4 ACPI System States .............................................................. 204

5.19.8 USB 2.0 Legacy Keyboard Operation...................................................... 204

5.19.9 USB 2.0 Based Debug Port ................................................................... 204

5.19.9.1 Theory of Operation ............................................................. 205

5.19.10 EHCI Caching ..................................................................................... 209

5.19.11 Intel® USB Prefetch Based Pause .......................................................... 209

5.19.12 Function Level Reset Support (FLR) ....................................................... 209

5.19.12.1 FLR Steps ............................................................................ 210

5.19.13 USB Overcurrent Protection.................................................................. 210

5.20 Integrated USB 2.0 Rate Matching Hub .............................................................. 211

5.20.1 Overview ........................................................................................... 211

5.20.2 Architecture ....................................................................................... 211

5.21 xHCI Controller (D20:F0) ................................................................................. 212

5.22 SMBus Controller (D31:F3)............................................................................... 212

5.22.1 Host Controller ................................................................................... 213

5.22.1.1 Command Protocols .............................................................. 213

5.22.2 Bus Arbitration ................................................................................... 217

5.22.3 Bus Timing......................................................................................... 217

5.22.3.1 Clock Stretching ................................................................... 217

5.22.3.2 Bus Time Out (The PCH as SMBus Master)................................ 217

5.22.4 Interrupts / SMI# ............................................................................... 217

5.22.5 SMBALERT# ....................................................................................... 218

5.22.6 SMBus CRC Generation and Checking .................................................... 219

5.22.7 SMBus Slave Interface......................................................................... 219

5.22.7.1 Format of Slave Write Cycle ................................................... 220

5.22.7.2 Format of Read Command...................................................... 221

5.22.7.3 Slave Read of RTC Time Bytes ................................................ 222

5.22.7.4 Format of Host Notify Command ............................................. 223

5.23 Thermal Management ...................................................................................... 224

5.23.1 Thermal Sensor .................................................................................. 224

5.23.1.1 Internal Thermal Sensor Operation.......................................... 224

5.23.2 PCH Thermal Throttling........................................................................ 225

5.23.3 Thermal Reporting Over System Management Link 1 Interface (SMLink1) ... 226

5.23.3.1 Block Read Address............................................................... 227

5.23.3.2 Block Read Command............................................................ 227

5.23.3.3 Read Data Format................................................................. 227

5.23.3.4 Thermal Data Update Rate ..................................................... 227

5.23.3.5 Temperature Comparator and Alert ......................................... 228

5.23.3.6 BIOS Set Up......................................................................... 229

5.23.3.7 SMBus Rules ........................................................................ 229

5.23.3.8 Case for Considerations ......................................................... 230

5.24 Intel

High Definition Audio (Intel® HD Audio) Overview (D27:F0) ........................ 232

5.24.1 Intel® High Definition Audio (Intel® HD Audio) Docking (Mobile Only) ........ 232

5.24.1.1 Dock Sequence..................................................................... 232

5.24.1.2 Exiting D3/CRST# When Docked............................................. 233

Datasheet 7

5.24.1.3 Cold Boot/Resume from S3 When Docked................................. 234

5.24.1.4 Undock Sequence..................................................................234

5.24.1.5 Normal Undock .....................................................................234

5.24.1.6 Surprise Undock....................................................................235

5.24.1.7 Interaction between Dock/Undock and Power Management States 235

5.24.1.8 Relationship between HDA_DOCK_RST# and HDA_RST# ............ 235

5.25 Intel® Management Engine (Intel® ME) and Intel® 

Management Engine Firmware (Intel® ME FW) 9.0 ............................................... 236

5.25.1 Intel® Management Engine (Intel® ME) Requirements.............................. 237

5.26 Serial Peripheral Interface (SPI) ........................................................................ 238

5.26.1 SPI Supported Feature Overview ...........................................................238

5.26.1.1 Non-Descriptor Mode .............................................................238

5.26.1.2 Descriptor Mode ....................................................................239

5.26.2 Flash Descriptor .................................................................................. 240

5.26.2.1 Descriptor Master Region........................................................241

5.26.3 Flash Access .......................................................................................241

5.26.3.1 Direct Access Security............................................................242

5.26.3.2 Register Access Security.........................................................242

5.26.4 Serial Flash Device Compatibility Requirements ....................................... 242

5.26.4.1 PCH SPI Based BIOS Requirements.......................................... 242

5.26.4.2 Integrated LAN Firmware SPI Flash Requirements...................... 243

5.26.4.3 Intel® Management Engine Firmware (Intel® ME FW) SPI Flash

Requirements .......................................................................243

5.26.4.4 Hardware Sequencing Requirements ........................................244

5.26.5 Multiple Page Write Usage Model ...........................................................245

5.26.5.1 Soft Flash Protection ..............................................................245

5.26.5.2 BIOS Range Write Protection...................................................246

5.26.5.3 SMI# Based Global Write Protection.........................................246

5.26.6 Flash Device Configurations ..................................................................246

5.26.7 SPI Flash Device Recommended Pinout................................................... 246

5.26.8 Serial Flash Device Package ..................................................................247

5.26.8.1 Common Footprint Usage Model ..............................................247

5.26.8.2 Serial Flash Device Package Recommendations..........................247

5.26.9 PWM Outputs (Server/Workstation Only) ................................................247

5.26.10 TACH Inputs (Server/Workstation Only) ................................................. 248

5.27 Feature Capability Mechanism ........................................................................... 248

5.28 PCH Display Interface and Intel® Flexible Display Interface (Intel® FDI)

Interconnect ...................................................................................................248

5.28.1 Analog Display Interface Characteristics ................................................. 249

5.28.1.1 Integrated RAMDAC...............................................................250

5.28.1.2 DDC (Display Data Channel) ...................................................250

5.28.2 Digital Display Side Band Signals........................................................... 250

5.28.2.1 DisplayPort AUX CH ............................................................... 251

5.28.2.2 DDC (Display Data Channel) ...................................................251

5.28.2.3 Hot-Plug Detect.....................................................................251

5.28.2.4 Map of Digital Display Side Band Signals Per Display 

Configuration ........................................................................251

5.28.2.5 Panel Power Sequencing and Backlight Control ..........................251

5.28.3 Intel

Flexible Display Interface (Intel® FDI) ..........................................252

5.29 Intel® Virtualization Technology (Intel® VT) ........................................................253

5.29.1 Intel® Virtualization Technology (Intel® VT) for 

Directed I/O (Intel® VT-d) Objectives..................................................... 253

5.29.2 Intel® VT-d Features Supported ............................................................253

5.29.3 Support for Function Level Reset (FLR) in PCH......................................... 253

5.29.4 Virtualization Support for PCH IOxAPIC...................................................254

5.29.5 Virtualization Support for High Precision Event Timer (HPET) .....................254

6 Ballout Definition ................................................................................................... 255

6.1 Desktop/Server PCH Ballout .............................................................................. 255

6.2 Mobile PCH Ballout...........................................................................................264

7 Package Information .............................................................................................272

7.1 Desktop/Server PCH Package ............................................................................272

7.1.1 Tape and Reel Pin 1 Placement..............................................................272

7.2 Mobile PCH Package .........................................................................................274

7.2.1 Tape and Reel Pin 1 Placement..............................................................274

8 Datasheet



8 Electrical Characteristics ....................................................................................... 276

8.1 Thermal Specifications ..................................................................................... 276

8.1.1 Storage Specifications and Thermal Design Power (TDP) .......................... 276

8.2 Absolute Maximum Ratings............................................................................... 277

8.3 PCH Power Supply Range ................................................................................. 277

8.4 General DC Characteristics ............................................................................... 278

8.5 Display DC Characteristics ................................................................................ 287

8.6 AC Characteristics ........................................................................................... 288

8.7 Power Sequencing and Reset Signal Timings ....................................................... 299

8.8 Power Management Timing Diagrams................................................................. 303

8.9 AC Timing Diagrams ........................................................................................ 308

8.10 Sequencing Rails Within The Same Well ............................................................. 319

9 Register and Memory Mapping............................................................................... 320

9.1 PCI Devices and Functions................................................................................ 321

9.2 PCI Configuration Map ..................................................................................... 322

9.3 I/O Map ......................................................................................................... 322

9.3.1 Fixed I/O Address Ranges .................................................................... 322

9.3.2 Variable I/O Decode Ranges ................................................................. 324

9.4 Memory Map................................................................................................... 325

9.4.1 Boot-Block Update Scheme .................................................................. 327

10 Chipset Configuration Registers............................................................................. 329

10.1 Chipset Configuration Registers (Memory Space)................................................. 329

10.1.1 RPC—Root Port Configuration Register ................................................... 331

10.1.2 RPFN—Root Port Function Number and Hide for PCI

Express* Root Ports Register ................................................................ 331

10.1.3 FLRSTAT—Function Level Reset Pending Status Register........................... 333

10.1.4 TRSR—Trap Status Register.................................................................. 333

10.1.5 TRCR—Trapped Cycle Register.............................................................. 334

10.1.6 TWDR—Trapped Write Data Register...................................................... 334

10.1.7 IOTRn—I/O Trap Register (0–3)............................................................ 335

10.1.8 V0CTL—Virtual Channel 0 Resource Control Register ................................ 336

10.1.9 V0STS—Virtual Channel 0 Resource Status Register................................. 336

10.1.10 V1CTL—Virtual Channel 1 Resource Control Register ................................ 336

10.1.11 V1STS—Virtual Channel 1 Resource Status Register................................. 337

10.1.12 REC—Root Error Command Register ...................................................... 337

10.1.13 LCAP—Link Capabilities Register............................................................ 337

10.1.14 LCTL—Link Control Register.................................................................. 338

10.1.15 LSTS—Link Status Register................................................................... 338

10.1.16 TCTL—TCO Configuration Register........................................................ 338

10.1.17 D31IP—Device 31 Interrupt Pin Register ................................................ 339

10.1.18 D30IP—Device 30 Interrupt Pin Register ................................................ 339

10.1.19 D29IP—Device 29 Interrupt Pin Register ................................................ 340

10.1.20 D28IP—Device 28 Interrupt Pin Register ................................................ 340

10.1.21 D27IP—Device 27 Interrupt Pin Register ................................................ 341

10.1.22 D26IP—Device 26 Interrupt Pin Register ................................................ 342

10.1.23 D25IP—Device 25 Interrupt Pin Register ................................................ 342

10.1.24 D22IP—Device 22 Interrupt Pin Register ................................................ 342

10.1.25 D20IP—Device 20 Interrupt Pin Register ................................................ 343

10.1.26 D31IR—Device 31 Interrupt Route Register ............................................ 343

10.1.27 D30IR—Device 30 Interrupt Route Register ............................................ 344

10.1.28 D29IR—Device 29 Interrupt Route Register ............................................ 344

10.1.29 D28IR—Device 28 Interrupt Route Register ............................................ 345

10.1.30 D27IR—Device 27 Interrupt Route Register ............................................ 346

10.1.31 D26IR—Device 26 Interrupt Route Register ............................................ 347

10.1.32 D25IR—Device 25 Interrupt Route Register ............................................ 348

10.1.33 D22IR—Device 22 Interrupt Route Register ............................................ 349

10.1.34 D20IR—Device 20 Interrupt Route Register ............................................ 350

10.1.35 OIC—Other Interrupt Control Register.................................................... 351

10.1.36 WADT_AC—Wake Alarm Device Timer – AC Register ................................ 351

10.1.37 WADT_DC—Wake Alarm Device Timer – DC Register ............................... 351

10.1.38 WADT_EXP_AC—Wake Alarm Device Expired Timer – AC

10.1.39 WADT_EXP_DC—Wake Alarm Device Expired Timer – DC

10.1.40 PRSTS—Power and Reset Status Register ............................................... 352

Datasheet 9

10.1.41 PM_CFG—Power Management Configuration Register ...............................353

10.1.42 DEEP_S3_POL—Deep Sx From S3 Power Policies Register .........................355

10.1.43 DEEP_S4_POL—Deep Sx From S4 Power Policies Register .........................355

10.1.44 DEEP_S5_POL—Deep Sx From S5 Power Policies Register .........................355

10.1.45 DSX_CFG—Deep Sx Configuration Register .............................................356

10.1.46 PMSYNC_CFG—PMSYNC Configuration....................................................356

10.1.47 RC—RTC Configuration Register............................................................. 357

10.1.48 HPTC—High Precision Timer Configuration Register ..................................357

10.1.49 GCS—General Control and Status Register ..............................................358

10.1.50 BUC—Backed Up Control Register .......................................................... 359

10.1.51 FD—Function Disable Register ...............................................................359

10.1.52 CG—Clock Gating Register ....................................................................361

10.1.53 FDSW—Function Disable SUS Well Register............................................. 362

10.1.54 DISPBDF—Display Bus, Device and Function

Initialization Register ...........................................................................362

10.1.55 FD2—Function Disable 2 Register...........................................................362

11 Gigabit LAN Configuration Registers ......................................................................363

11.1 Gigabit LAN Configuration Registers 

(Gigabit LAN—D25:F0) ..................................................................................... 363

11.1.1 VID—Vendor Identification Register 

(Gigabit LAN—D25:F0)......................................................................... 364

11.1.2 DID—Device Identification Register 

(Gigabit LAN—D25:F0)......................................................................... 364

11.1.3 PCICMD—PCI Command Register

(Gigabit LAN—D25:F0)......................................................................... 365

11.1.4 PCISTS—PCI Status Register 

(Gigabit LAN—D25:F0)......................................................................... 365

11.1.5 RID—Revision Identification Register 

(Gigabit LAN—D25:F0)......................................................................... 366

11.1.6 CC—Class Code Register 

(Gigabit LAN—D25:F0)......................................................................... 366

11.1.7 CLS—Cache Line Size Register 

(Gigabit LAN—D25:F0)......................................................................... 367

11.1.8 PLT—Primary Latency Timer Register 

(Gigabit LAN—D25:F0)......................................................................... 367

11.1.9 HEADTYP—Header Type Register 

(Gigabit LAN—D25:F0)......................................................................... 367

11.1.10 MBARA—Memory Base Address Register A 

(Gigabit LAN—D25:F0)......................................................................... 367

11.1.11 MBARB—Memory Base Address Register B

(Gigabit LAN—D25:F0)......................................................................... 368

11.1.12 MBARC—Memory Base Address Register C

(Gigabit LAN—D25:F0)......................................................................... 368

11.1.13 SVID—Subsystem Vendor ID Register

(Gigabit LAN—D25:F0)......................................................................... 368

11.1.14 SID—Subsystem ID Register

(Gigabit LAN—D25:F0)......................................................................... 369

11.1.15 ERBA—Expansion ROM Base Address Register

(Gigabit LAN—D25:F0)......................................................................... 369

11.1.16 CAPP—Capabilities List Pointer Register 

(Gigabit LAN—D25:F0)......................................................................... 369

11.1.17 INTR—Interrupt Information Register

(Gigabit LAN—D25:F0)......................................................................... 369

11.1.18 MLMG—Maximum Latency / Minimum Grant Register

(Gigabit LAN—D25:F0)......................................................................... 369

11.1.19 STCL—System Time Control Low Register

(Gigabit LAN—D25:F0)......................................................................... 370

11.1.20 STCH—System Time Control High Register

(Gigabit LAN—D25:F0)......................................................................... 370

11.1.21 LTRCAP—System Time Control High Register

(Gigabit LAN—D25:F0)......................................................................... 370

11.1.22 CLIST1—Capabilities List Register 1

(Gigabit LAN—D25:F0)......................................................................... 371

11.1.23 PMC—PCI Power Management Capabilities Register 

(Gigabit LAN—D25:F0)......................................................................... 371

10 Datasheet



11.1.24 PMCS—PCI Power Management Control and Status

11.1.25 DR—Data Register 

(Gigabit LAN—D25:F0) ........................................................................ 372

11.1.26 CLIST2—Capabilities List Register 2

(Gigabit LAN—D25:F0) ........................................................................ 372

11.1.27 MCTL—Message Control Register

(Gigabit LAN—D25:F0) ........................................................................ 373

11.1.28 MADDL—Message Address Low Register

(Gigabit LAN—D25:F0) ........................................................................ 373

11.1.29 MADDH—Message Address High Register

(Gigabit LAN—D25:F0) ........................................................................ 373

11.1.30 MDAT—Message Data Register

(Gigabit LAN—D25:F0) ........................................................................ 373

11.1.31 FLRCAP—Function Level Reset Capability

(Gigabit LAN—D25:F0) ........................................................................ 374

11.1.32 FLRCLV—Function Level Reset Capability Length and

Version Register (Gigabit LAN—D25:F0)................................................. 374

11.1.33 DEVCTRL—Device Control Register (Gigabit LAN—D25:F0) ....................... 375

11.2 Gigabit LAN Capabilities and Status Registers (CSR)............................................. 375

11.2.1 GBECSR_00—Gigabit Ethernet Capabilities and Status Register 00............. 376

11.2.2 GBECSR_18—Gigabit Ethernet Capabilities and Status Register 18............. 376

11.2.3 GBECSR_20—Gigabit Ethernet Capabilities and Status Register 20............. 376

11.2.4 GBECSR_F00—Gigabit Ethernet Capabilities and Status Register F00 ......... 377

11.2.5 GBECSR_F10—Gigabit Ethernet Capabilities and Status Register F10 ......... 377

11.2.6 GBECSR_5400—Gigabit Ethernet Capabilities and Status Register 5400...... 377

11.2.7 GBECSR_5404—Gigabit Ethernet Capabilities and Status Register 5404...... 377

11.2.8 GBECSR_5800—Gigabit Ethernet Capabilities and Status Register 5800...... 378

11.2.9 GBECSR_5B54—Gigabit Ethernet Capabilities and Status Register 5B54 ..... 378

12 LPC Interface Bridge Registers (D31:F0) ............................................................... 379

12.1 PCI Configuration Registers (LPC I/F—D31:F0).................................................... 379

12.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0)............................. 380

12.1.2 DID—Device Identification Register (LPC I/F—D31:F0) ............................. 380

12.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) ............................... 380

12.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0) ...................................... 381

12.1.5 RID—Revision Identification Register (LPC I/F—D31:F0)........................... 382

12.1.6 PI—Programming Interface Register (LPC I/F—D31:F0)............................ 382

12.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) ................................... 382

12.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0) .................................. 382

12.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0) .......................... 382

12.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0) ................................ 382

12.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0) ........................... 383

12.1.12 CAPP—Capability List Pointer Register (LPC I/F—D31:F0) ......................... 383

12.1.13 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0) ......................... 383

12.1.14 ACPI_CNTL—ACPI Control Register (LPC I/F—D31:F0) ............................. 384

12.1.15 GPIOBASE—GPIO Base Address Register (LPC I/F—D31:F0) ..................... 384

12.1.16 GC—GPIO Control Register (LPC I/F—D31:F0) ........................................ 385

12.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0)............................................................................... 385

12.1.18 SIRQ_CNTL—Serial IRQ Control Register 

(LPC I/F—D31:F0)............................................................................... 386

12.1.19 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register

(LPC I/F—D31:F0)............................................................................... 386

12.1.20 LPC_IBDF—IOxAPIC Bus:Device:Function

(LPC I/F—D31:F0)............................................................................... 387

12.1.21 LPC_HnBDF—HPET n Bus:Device:Function 

(LPC I/F—D31:F0)............................................................................... 387

12.1.22 LPC_I/O_DEC—I/O Decode Ranges Register 

(LPC I/F—D31:F0)............................................................................... 388

12.1.23 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) .............................. 388

12.1.24 GEN1_DEC—LPC I/F Generic Decode Range 1 Register 

(LPC I/F—D31:F0)............................................................................... 389

12.1.25 GEN2_DEC—LPC I/F Generic Decode Range 2 Register 

(LPC I/F—D31:F0)............................................................................... 390

12.1.26 GEN3_DEC—LPC I/F Generic Decode Range 3 Register 

(LPC I/F—D31:F0)............................................................................... 390

Datasheet 11

12.1.27 GEN4_DEC—LPC I/F Generic Decode Range 4 Register 

(LPC I/F—D31:F0) ............................................................................... 391

12.1.28 ULKMC—USB Legacy Keyboard / Mouse

Control Register(LPC I/F—D31:F0).........................................................391

12.1.29 LGMR—LPC I/F Generic Memory Range Register

(LPC I/F—D31:F0) ............................................................................... 392

12.1.30 BIOS_SEL1—BIOS Select 1 Register 

(LPC I/F—D31:F0) ............................................................................... 393

12.1.31 BIOS_SEL2—BIOS Select 2 Register 

(LPC I/F—D31:F0) ............................................................................... 394

12.1.32 BIOS_DEC_EN1—BIOS Decode Enable 

12.1.33 BIOS_CNTL—BIOS Control Register 

(LPC I/F—D31:F0) ............................................................................... 396

12.1.34 FDCAP—Feature Detection Capability ID Register

(LPC I/F—D31:F0) ............................................................................... 396

12.1.35 FDLEN—Feature Detection Capability Length Register

(LPC I/F—D31:F0) ............................................................................... 397

12.1.36 FDVER—Feature Detection Version Register

(LPC I/F—D31:F0) ............................................................................... 397

12.1.37 FVECIDX—Feature Vector Index Register

(LPC I/F—D31:F0) ............................................................................... 397

12.1.38 FVECD—Feature Vector Data Register

(LPC I/F—D31:F0) ............................................................................... 397

12.1.39 Feature Vector Space ........................................................................... 398

12.1.39.1 FVEC0—Feature Vector Register 0............................................ 398

12.1.39.2 FVEC1—Feature Vector Register 1............................................ 399

12.1.39.3 FVEC2—Feature Vector Register 2............................................ 399

12.1.39.4 FVEC3—Feature Vector Register 3............................................ 399

12.1.40 RCBA—Root Complex Base Address Register 

(LPC I/F—D31:F0) ............................................................................... 400

12.2 DMA I/O Registers ........................................................................................... 400

12.2.1 DMABASE_CA—DMA Base and Current Address Registers ......................... 401

12.2.2 DMABASE_CC—DMA Base and Current Count Registers ............................402

12.2.3 DMAMEM_LP—DMA Memory Low Page Registers ......................................402

12.2.4 DMACMD—DMA Command Register........................................................403

12.2.5 DMASTA—DMA Status Register..............................................................403

12.2.6 DMA_WRSMSK—DMA Write Single Mask Register.....................................404

12.2.7 DMACH_MODE—DMA Channel Mode Register .......................................... 404

12.2.8 DMA Clear Byte Pointer Register ............................................................405

12.2.9 DMA Master Clear Register....................................................................405

12.2.10 DMA_CLMSK—DMA Clear Mask Register .................................................405

12.2.11 DMA_WRMSK—DMA Write All Mask Register............................................ 406

12.3 Timer I/O Registers.......................................................................................... 406

12.3.1 TCW—Timer Control Word Register ........................................................407

12.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register .......................... 409

12.3.3 Counter Access Ports Register ...............................................................409

12.4 8259 Interrupt Controller (PIC) Registers ............................................................ 410

12.4.1 Interrupt Controller I/O MAP .................................................................410

12.4.2 ICW1—Initialization Command Word 1 Register .......................................410

12.4.3 ICW2—Initialization Command Word 2 Register .......................................411

12.4.4 ICW3—Master Controller Initialization Command 

Word 3 Register ..................................................................................412

12.4.5 ICW3—Slave Controller Initialization Command 

Word 3 Register ..................................................................................412

12.4.6 ICW4—Initialization Command Word 4 Register .......................................412

12.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)

12.4.8 OCW2—Operational Control Word 2 Register ...........................................413

12.4.9 OCW3—Operational Control Word 3 Register ...........................................414

12.4.10 ELCR1—Master Controller Edge/Level Triggered Register .......................... 415

12.4.11 ELCR2—Slave Controller Edge/Level Triggered Register ............................ 416

12.5 Advanced Programmable Interrupt Controller (APIC) ............................................417

12.5.1 APIC Register Map ............................................................................... 417

12.5.2 IND—Index Register ............................................................................417

12.5.3 DAT—Data Register ............................................................................. 418

12.5.4 EOIR—EOI Register .............................................................................418

12 Datasheet



12.5.5 ID—Identification Register.................................................................... 419

12.5.6 VER—Version Register ......................................................................... 419

12.5.7 REDIR_TBL—Redirection Table Register ................................................. 420

12.6 Real Time Clock Registers................................................................................. 421

12.6.1 I/O Register Address Map..................................................................... 421

12.6.2 Indexed Registers ............................................................................... 422

12.6.2.1 RTC_REGA—Register A .......................................................... 423

12.6.2.2 RTC_REGB—Register B (General Configuration) ........................ 424

12.6.2.3 RTC_REGC—Register C (Flag Register)..................................... 425

12.6.2.4 RTC_REGD—Register D (Flag Register) .................................... 425

12.7 Processor Interface Registers............................................................................ 425

12.7.1 NMI_SC—NMI Status and Control Register.............................................. 426

12.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) 

12.7.3 PORT92—Init Register ......................................................................... 427

12.7.4 COPROC_ERR—Coprocessor Error Register ............................................. 427

12.7.5 RST_CNT—Reset Control Register ......................................................... 427

12.8 Power Management Registers ........................................................................... 428

12.8.1 Power Management PCI Configuration Registers 

(PM—D31:F0)..................................................................................... 428

12.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register 

(PM—D31:F0)....................................................................... 428

12.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register 

(PM—D31:F0)....................................................................... 430

12.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register 

(PM—D31:F0)....................................................................... 431

12.8.1.4 GEN_PMCON_LOCK—General Power Management Configuration 

Lock Register ....................................................................... 434

12.8.1.5 BM_BREAK_EN_2 Register #2 (PM—D31:F0) ............................ 434

12.8.1.6 BM_BREAK_EN Register (PM—D31:F0)..................................... 435

12.8.1.7 GPI_ROUT—GPI Routing Control Register 

(PM—D31:F0)....................................................................... 436

12.8.1.8 GPI_ROUT2—GPI Routing Control Register #2 (PM-D31:F0) ....... 437

12.8.2 APM I/O Decode Register ..................................................................... 437

12.8.2.1 APM_CNT—Advanced Power Management Control Port Register... 437

12.8.2.2 APM_STS—Advanced Power Management Status Port Register .... 438

12.8.3 Power Management I/O Registers.......................................................... 438

12.8.3.1 PM1_STS—Power Management 1 Status Register ...................... 439

12.8.3.2 PM1_EN—Power Management 1 Enable Register........................ 440

12.8.3.3 PM1_CNT—Power Management 1 Control Register..................... 441

12.8.3.4 PM1_TMR—Power Management 1 Timer Register....................... 442

12.8.3.5 GPE0_STS—General Purpose Event 0 Status Register ................ 442

12.8.3.6 GPE0_EN—General Purpose Event 0 Enables Register ................ 445

12.8.3.7 SMI_EN—SMI Control and Enable Register................................ 446

12.8.3.8 SMI_STS—SMI Status Register ............................................... 448

12.8.3.9 ALT_GPI_SMI_EN—Alternate GPI SMI Enable Register ............... 450

12.8.3.10 ALT_GPI_SMI_STS—Alternate GPI SMI Status Register .............. 450

12.8.3.11 GPE_CNTL—General Purpose Control Register ........................... 450

12.8.3.12 DEVACT_STS—Device Activity Status Register .......................... 451

12.8.3.13 PM2_CNT—Power Management 2 Control Register ..................... 452

12.8.3.14 ALT_GPI_SMI_EN2—Alternate GPI SMI Enable 2 Register ........... 452

12.8.3.15 ALT_GPI_SMI_STS2—Alternate GPI SMI Status 2 Register.......... 452

12.9 System Management TCO Registers................................................................... 453

12.9.1 TCO_RLD—TCO Timer Reload and Current Value Register ......................... 454

12.9.2 TCO_DAT_IN—TCO Data In Register...................................................... 454

12.9.3 TCO_DAT_OUT—TCO Data Out Register ................................................. 454

12.9.4 TCO1_STS—TCO1 Status Register......................................................... 454

12.9.5 TCO2_STS—TCO2 Status Register......................................................... 455

12.9.6 TCO1_CNT—TCO1 Control Register........................................................ 456

12.9.7 TCO2_CNT—TCO2 Control Register........................................................ 457

12.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers...................................... 458

12.9.9 TCO_WDCNT—TCO Watchdog Control Register........................................ 458

12.9.10 SW_IRQ_GEN—Software IRQ Generation Register ................................... 458

12.9.11 TCO_TMR—TCO Timer Initial Value Register ........................................... 458

12.10 General Purpose I/O Registers .......................................................................... 459

12.10.1 GPIO_USE_SEL—GPIO Use Select Register ............................................. 460

12.10.2 GP_IO_SEL—GPIO Input/Output Select Register...................................... 460

Datasheet 13

12.10.3 GP_LVL—GPIO Level for Input or Output Register .................................... 460

12.10.4 GPO_BLINK—GPO Blink Enable Register .................................................461

12.10.5 GP_SER_BLINK—GP Serial Blink Register................................................461

12.10.6 GP_SB_CMDSTS—GP Serial Blink Command

Status Register ...................................................................................462

12.10.7 GP_SB_DATA—GP Serial Blink Data Register ...........................................462

12.10.8 GPI_NMI_EN—GPI NMI Enable Register .................................................. 462

12.10.9 GPI_NMI_STS—GPI NMI Status Register.................................................463

12.10.10GPI_INV—GPIO Signal Invert Register.................................................... 463

12.10.11GPIO_USE_SEL2—GPIO Use Select 2 Register.........................................464

12.10.12GP_IO_SEL2—GPIO Input/Output Select 2 Register .................................464

12.10.13GP_LVL2—GPIO Level for Input or Output 2 Register................................465

12.10.14GPIO_USE_SEL3—GPIO Use Select 3 Register.........................................465

12.10.15GP_IO_SEL3—GPIO Input/Output Select 3 Register .................................466

12.10.16GP_LVL3—GPIO Level for Input or Output 3 Register................................466

12.10.17GP_RST_SEL1—GPIO Reset Select Register ............................................466

12.10.18GP_RST_SEL2—GPIO Reset Select Register ............................................467

12.10.19GP_RST_SEL3—GPIO Reset Select Register ............................................467

13 SATA Controller Registers (D31:F2) .......................................................................468

13.1 PCI Configuration Registers (SATA–D31:F2) ........................................................ 468

13.1.1 VID—Vendor Identification Register (SATA—D31:F2)................................469

13.1.2 DID—Device Identification Register (SATA—D31:F2) ................................ 470

13.1.3 PCICMD—PCI Command Register (SATA–D31:F2) ....................................470

13.1.4 PCISTS—PCI Status Register (SATA–D31:F2)..........................................471

13.1.5 RID—Revision Identification Register (SATA—D31:F2) ..............................471

13.1.6 PI—Programming Interface Register (SATA–D31:F2)................................472

13.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h ......... 472

13.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h ......... 472

13.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h ......... 472

13.1.7 SCC—Sub Class Code Register (SATA–D31:F2)........................................473

13.1.8 BCC—Base Class Code Register 

(SATA–D31:F2SATA–D31:F2)................................................................473

13.1.9 PMLT—Primary Master Latency Timer Register 

(SATA–D31:F2)................................................................................... 473

13.1.10 HTYPE—Header Type Register

(SATA–D31:F2)................................................................................... 473

13.1.11 PCMD_BAR—Primary Command Block Base Address

13.1.12 PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F2)................................................................................... 474

13.1.13 SCMD_BAR—Secondary Command Block Base Address

13.1.14 SCNL_BAR—Secondary Control Block Base Address

13.1.15 BAR—Legacy Bus Master Base Address Register

(SATA–D31:F2)................................................................................... 475

13.1.16 ABAR/SIDPBA1—AHCI Base Address Register / Serial ATA

Index Data Pair Base Address (SATA–D31:F2).........................................475

13.1.16.1 When SCC is not 01h .............................................................476

13.1.16.2 When SCC is 01h...................................................................476

13.1.17 SVID—Subsystem Vendor Identification Register 

(SATA–D31:F2)................................................................................... 476

13.1.18 SID—Subsystem Identification Register (SATA–D31:F2) ........................... 477

13.1.19 CAP—Capabilities Pointer Register (SATA–D31:F2) ................................... 477

13.1.20 INT_LN—Interrupt Line Register (SATA–D31:F2) .....................................477

13.1.21 INT_PN—Interrupt Pin Register (SATA–D31:F2).......................................477

13.1.22 IDE_TIM—IDE Timing Register (SATA–D31:F2)........................................ 478

13.1.23 SIDETIM—Slave IDE Timing Register (SATA–D31:F2) ............................... 478

13.1.24 SDMA_CNT—Synchronous DMA Control Register 

(SATA–D31:F2)................................................................................... 478

13.1.25 SDMA_TIM—Synchronous DMA Timing Register 

(SATA–D31:F2)................................................................................... 479

13.1.26 IDE_CONFIG—IDE I/O Configuration Register 

(SATA–D31:F2)................................................................................... 479

13.1.27 PID—PCI Power Management Capability Identification

14 Datasheet



13.1.28 PC—PCI Power Management Capabilities Register 

(SATA–D31:F2) .................................................................................. 480

13.1.29 PMCS—PCI Power Management Control and Status

13.1.30 MSICI—Message Signaled Interrupt Capability

Identification Register (SATA–D31:F2)................................................... 481

13.1.31 MSIMC—Message Signaled Interrupt Message

Control Register (SATA–D31:F2) ........................................................... 481

13.1.32 MSIMA—Message Signaled Interrupt Message

Address Register (SATA–D31:F2) .......................................................... 482

13.1.33 MSIMD—Message Signaled Interrupt Message

Data Register (SATA–D31:F2)............................................................... 483

13.1.34 MAP—Address Map Register (SATA–D31:F2) ........................................... 483

13.1.35 PCS—Port Control and Status Register (SATA–D31:F2) ............................ 483

13.1.36 SCLKCG—SATA Clock Gating Control Register ......................................... 486

13.1.37 SGC—SATA General Configuration Register............................................. 486

13.1.38 SATACR0—SATA Capability Register 0 (SATA–D31:F2) ............................. 487

13.1.39 SATACR1—SATA Capability Register 1 (SATA–D31:F2) ............................. 487

13.1.40 FLRCID—FLR Capability Identification Register (SATA–D31:F2) ................. 488

13.1.41 FLRCLV—FLR Capability Length and Version Register (SATA–D31:F2)......... 488

13.1.42 FLRC—FLR Control Register (SATA–D31:F2) ........................................... 488

13.1.43 ATC—APM Trapping Control Register (SATA–D31:F2) ............................... 489

13.1.44 ATS—APM Trapping Status Register (SATA–D31:F2) ................................ 489

13.1.45 SP—Scratch Pad Register (SATA–D31:F2) .............................................. 489

13.1.46 BFCS—BIST FIS Control/Status Register (SATA–D31:F2).......................... 489

13.1.47 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ....................... 491

13.1.48 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ....................... 491

13.2 Bus Master IDE I/O Registers (D31:F2) .............................................................. 492

13.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2)......................... 493

13.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) .............................. 493

13.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

13.2.4 AIR—AHCI Index Register (D31:F2)....................................................... 494

13.2.5 AIDR—AHCI Index Data Register (D31:F2) ............................................. 495

13.3 Serial ATA Index/Data Pair Superset Registers .................................................... 495

13.3.1 SINDX—Serial ATA Index Register (D31:F2) ........................................... 495

13.3.2 SDATA—Serial ATA Data Register (D31:F2) ............................................ 496

13.3.2.1 PxSSTS—Serial ATA Status Register (D31:F2)........................... 496

13.3.2.2 PxSCTL—Serial ATA Control Register (D31:F2).......................... 497

13.3.2.3 PxSERR—Serial ATA Error Register (D31:F2) ............................ 498

13.4 AHCI Registers (D31:F2).................................................................................. 499

13.4.1 AHCI Generic Host Control Registers (D31:F2) ........................................ 500

13.4.1.1 CAP—Host Capabilities Register (D31:F2) ................................. 500

13.4.1.2 GHC—Global PCH Control Register (D31:F2) ............................. 501

13.4.1.3 IS—Interrupt Status Register (D31:F2).................................... 502

13.4.1.4 PI—Ports Implemented Register (D31:F2) ................................ 503

13.4.1.5 VS—AHCI Version Register (D31:F2) ....................................... 504

13.4.1.6 EM_LOC—Enclosure Management Location Register (D31:F2) ..... 504

13.4.1.7 EM_CTRL—Enclosure Management Control Register (D31:F2) ..... 504

13.4.1.8 CAP2—HBA Capabilities Extended Register ............................... 505

13.4.1.9 RSTF—Intel

RST Feature Capabilities Register......................... 506

13.4.2 Port Registers (D31:F2) ....................................................................... 507

13.4.2.1 PxCLB—Port [5:0] Command List Base Address Register

(D31:F2) ............................................................................. 509

13.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper

32-Bits Register (D31:F2) ...................................................... 510

13.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2)................ 510

13.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits

13.4.2.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2).................. 511

13.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2).................. 512

13.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2)....................... 513

13.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2) .................. 515

13.4.2.9 PxSIG—Port [5:0] Signature Register (D31:F2)......................... 516

13.4.2.10 PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2) ............ 516

13.4.2.11 PxSCTL—Port [5:0] Serial ATA Control Register (D31:F2) ........... 517

13.4.2.12 PxSERR—Port [5:0] Serial ATA Error Register (D31:F2).............. 518

Datasheet 15

13.4.2.13 PxSACT—Port [5:0] Serial ATA Active Register (D31:F2).............519

13.4.2.14 PxCI—Port [5:0] Command Issue Register (D31:F2) .................. 520

14 SATA Controller Registers (D31:F5) .......................................................................521

14.1 PCI Configuration Registers (SATA–D31:F5) ........................................................ 521

14.1.1 VID—Vendor Identification Register (SATA—D31:F5)................................522

14.1.2 DID—Device Identification Register (SATA—D31:F5) ................................ 522

14.1.3 PCICMD—PCI Command Register (SATA–D31:F5) ....................................522

14.1.4 PCISTS—PCI Status Register (SATA–D31:F5)..........................................523

14.1.5 RID—Revision Identification Register (SATA—D31:F5) ..............................524

14.1.6 PI—Programming Interface Register (SATA–D31:F5)................................524

14.1.7 SCC—Sub Class Code Register (SATA–D31:F5)........................................524

14.1.8 BCC—Base Class Code Register 

(SATA–D31:F5SATA–D31:F5)................................................................525

14.1.9 PCMD_BAR—Primary Command Block Base Address

14.1.10 PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F5)................................................................................... 525

14.1.11 SCMD_BAR—Secondary Command Block Base Address

14.1.12 SCNL_BAR—Secondary Control Block Base Address

14.1.13 BAR—Legacy Bus Master Base Address Register

(SATA–D31:F5)................................................................................... 526

14.1.14 SIDPBA—SATA Index/Data Pair Base Address Register 

(SATA–D31:F5)................................................................................... 527

14.1.15 SVID—Subsystem Vendor Identification Register 

(SATA–D31:F5)................................................................................... 527

14.1.16 SID—Subsystem Identification Register (SATA–D31:F5) ........................... 527

14.1.17 CAP—Capabilities Pointer Register (SATA–D31:F5) ................................... 527

14.1.18 INT_LN—Interrupt Line Register (SATA–D31:F5) .....................................528

14.1.19 INT_PN—Interrupt Pin Register (SATA–D31:F5).......................................528

14.1.20 IDE_TIM—IDE Timing Register (SATA–D31:F5)........................................ 528

14.1.21 SDMA_CNT—Synchronous DMA Control Register 

(SATA–D31:F5)................................................................................... 528

14.1.22 SDMA_TIM—Synchronous DMA Timing Register 

(SATA–D31:F5)................................................................................... 529

14.1.23 IDE_CONFIG—IDE I/O Configuration Register 

(SATA–D31:F5)................................................................................... 529

14.1.24 PID—PCI Power Management Capability Identification

14.1.25 PC—PCI Power Management Capabilities Register 

(SATA–D31:F5)................................................................................... 530

14.1.26 PMCS—PCI Power Management Control and Status

14.1.27 MAP—Address Map Register (SATA–D31:F5) ........................................... 531

14.1.28 PCS—Port Control and Status Register (SATA–D31:F5) ............................. 532

14.1.29 SATACR0—SATA Capability Register 0 (SATA–D31:F5) .............................532

14.1.30 SATACR1—SATA Capability Register 1 (SATA–D31:F5) .............................533

14.1.31 FLRCID—FLR Capability ID Register (SATA–D31:F5)................................. 533

14.1.32 FLRCLV—FLR Capability Length and

Value Register (SATA–D31:F5)..............................................................533

14.1.33 FLRCTRL—FLR Control Register (SATA–D31:F5)....................................... 534

14.1.34 ATC—APM Trapping Control Register (SATA–D31:F5) ............................... 534

14.1.35 ATC—APM Trapping Control Register (SATA–D31:F5) ............................... 534

14.2 Bus Master IDE I/O Registers (D31:F5)...............................................................534

14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5) .........................535

14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5) .............................. 536

14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

14.3 Serial ATA Index/Data Pair Superset Registers.....................................................537

14.3.1 SINDX—SATA Index Register (D31:F5)................................................... 537

14.3.2 SDATA—SATA Index Data Register (D31:F5)........................................... 537

14.3.2.1 PxSSTS—Serial ATA Status Register (D31:F5) ........................... 538

14.3.2.2 PxSCTL—Serial ATA Control Register (D31:F5) .......................... 539

14.3.2.3 PxSERR—Serial ATA Error Register (D31:F5).............................540

16 Datasheet



15 EHCI Controller Registers (D29:F0, D26:F0) .......................................................... 541

15.1 USB EHCI Configuration Registers 

(USB EHCI—D29:F0, D26:F0) ........................................................................... 541

15.1.1 VID—Vendor Identification Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 542

15.1.2 DID—Device Identification Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 542

15.1.3 PCICMD—PCI Command Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 542

15.1.4 PCISTS—PCI Status Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 543

15.1.5 RID—Revision Identification Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 544

15.1.6 PI—Programming Interface Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 545

15.1.7 SCC—Sub Class Code Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 545

15.1.8 BCC—Base Class Code Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 545

15.1.9 PMLT—Primary Master Latency Timer Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 545

15.1.10 HEADTYP—Header Type Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 545

15.1.11 MEM_BASE—Memory Base Address Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 546

15.1.12 SVID—USB EHCI Subsystem Vendor ID Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 546

15.1.13 SID—USB EHCI Subsystem ID Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 546

15.1.14 CAP_PTR—Capabilities Pointer Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 547

15.1.15 INT_LN—Interrupt Line Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 547

15.1.16 INT_PN—Interrupt Pin Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 547

15.1.17 PWR_CAPID—PCI Power Management Capability 

Identification Register (USB EHCI—D29:F0, D26:F0) ............................... 547

15.1.18 NXT_PTR1—Next Item Pointer #1 Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 548

15.1.19 PWR_CAP—Power Management Capabilities Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 548

15.1.20 PWR_CNTL_STS—Power Management Control / 

Status Register (USB EHCI—D29:F0, D26:F0)......................................... 549

15.1.21 DEBUG_CAPID—Debug Port Capability ID Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 549

15.1.22 NXT_PTR2—Next Item Pointer #2 Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 550

15.1.23 DEBUG_BASE—Debug Port Base Offset Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 550

15.1.24 USB_RELNUM—USB Release Number Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 550

15.1.25 FL_ADJ—Frame Length Adjustment Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 551

15.1.26 PWAKE_CAP—Port Wake Capability Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 552

15.1.27 PDO—Port Disable Override Register...................................................... 552

15.1.28 RMHDEVR—RMH Device Removable Field Register ................................... 553

15.1.29 LEG_EXT_CAP—USB EHCI Legacy Support Extended

Capability Register (USB EHCI—D29:F0, D26:F0) .................................... 553

15.1.30 LEG_EXT_CS—USB EHCI Legacy Support Extended

15.1.31 SPECIAL_SMI—Intel

Control / Status Register (USB EHCI—D29:F0, D26:F0)............................ 554

Specific USB 2.0 SMI Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 555

15.1.32 OCMAP—Over-Current Mapping Register ................................................ 557

15.1.33 RMHWKCTL—RMH Wake Control Register ............................................... 558

15.1.34 ACCESS_CNTL—Access Control Register 

(USB EHCI—D29:F0, D26:F0)............................................................... 558

Datasheet 17

15.1.35 EHCIIR1—EHCI Initialization Register 1

(USB EHCI—D29:F0, D26:F0) ...............................................................559

15.1.36 FLR_CID—Function Level Reset Capability ID Register

(USB EHCI—D29:F0, D26:F0) ...............................................................559

15.1.37 FLR_NEXT—Function Level Reset Next Capability

Pointer Register (USB EHCI—D29:F0, D26:F0) ........................................559

15.1.38 FLR_CLV—Function Level Reset Capability Length and

Version Register (USB EHCI—D29:F0, D26:F0)........................................559

15.1.39 FLR_CTRL—Function Level Reset Control Register

(USB EHCI—D29:F0, D26:F0) ...............................................................560

15.1.40 FLR_STS—Function Level Reset Status Register

(USB EHCI—D29:F0, D26:F0) ...............................................................560

15.2 Memory-Mapped I/O Registers ..........................................................................561

15.2.1 Host Controller Capability Registers .......................................................561

15.2.1.1 CAPLENGTH—Capability Registers Length Register ..................... 562

15.2.1.2 HCIVERSION—Host Controller Interface Version Number 

15.2.1.3 HCSPARAMS—Host Controller Structural Parameters ..................562

15.2.1.4 HCCPARAMS—Host Controller Capability Parameters 

15.2.2 Host Controller Operational Registers .....................................................564

15.2.2.1 USB2.0_CMD—USB 2.0 Command Register ...............................565

15.2.2.2 USB2.0_STS—USB 2.0 Status Register.....................................567

15.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register...................... 569

15.2.2.4 FRINDEX—Frame Index Register .............................................570

15.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment 

15.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address 

15.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address 

15.2.2.8 CONFIGFLAG—Configure Flag Register .....................................572

15.2.2.9 PORTSC—Port N Status and Control Register .............................572

15.2.3 USB 2.0-Based Debug Port Registers......................................................575

15.2.3.1 CNTL_STS—Control / Status Register .......................................576

15.2.3.2 USBPID—USB PIDs Register.................................................... 577

15.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register ....................... 577

15.2.3.4 CONFIG—Configuration Register.............................................. 578

16 xHCI Controller Registers (D20:F0)........................................................................579

16.1 USB xHCI Configuration Registers 

(USB xHCI—D20:F0)........................................................................................ 579

16.1.1 VID—Vendor Identification Register 

(USB xHCI—D20:F0)............................................................................580

16.1.2 DID—Device Identification Register 

(USB xHCI—D20:F0)............................................................................580

16.1.3 PCICMD—PCI Command Register 

(USB xHCI—D20:F0)............................................................................581

16.1.4 PCISTS—PCI Status Register 

(USB xHCI—D20:F0)............................................................................582

16.1.5 RID—Revision Identification Register 

(USB xHCI—D20:F0)............................................................................583

16.1.6 PI—Programming Interface Register 

(USB xHCI—D20:F0)............................................................................583

16.1.7 SCC—Sub Class Code Register 

(USB xHCI—D20:F0)............................................................................583

16.1.8 BCC—Base Class Code Register 

(USB xHCI—D20:F0)............................................................................583

16.1.9 PMLT—Primary Master Latency Timer Register 

(USB xHCI—D20:F0)............................................................................583

16.1.10 HEADTYP—Header Type Register 

(USB xHCI—D20:F0)............................................................................584

16.1.11 MEM_BASE_L—Memory Base Address Low Register 

(USB xHCI—D20:F0)............................................................................584

16.1.12 MEM_BASE_H—Memory Base Address High Register 

(USB xHCI—D20:F0)............................................................................584

18 Datasheet



16.1.13 SVID—USB xHCI Subsystem Vendor ID Register 

(USB xHCI—D20:F0) ........................................................................... 584

16.1.14 SID—USB xHCI Subsystem ID Register 

(USB xHCI—D20:F0) ........................................................................... 585

16.1.15 CAP_PTR—Capabilities Pointer Register 

(USB xHCI—D20:F0) ........................................................................... 585

16.1.16 INT_LN—Interrupt Line Register 

(USB xHCI—D20:F0) ........................................................................... 585

16.1.17 INT_PN—Interrupt Pin Register 

(USB xHCI—D20:F0) ........................................................................... 585

16.1.18 XHCC—xHC System Bus Configuration Register 

(USB xHCI—D20:F0) ........................................................................... 585

16.1.19 XHCC2—xHC System Bus Configuration Register 2 

(USB xHCI—D20:F0) ........................................................................... 586

16.1.20 SBRN—Serial Bus Release Number

16.1.21 FL_ADJ—Frame Length Adjustment Register 

(USB xHCI—D20:F0) ........................................................................... 587

16.1.22 PWR_CAPID—PCI Power Management Capability ID

16.1.23 NXT_PTR1—Next Item Pointer #1 Register 

(USB xHCI—D20:F0) ........................................................................... 588

16.1.24 PWR_CAP—Power Management Capabilities Register 

(USB xHCI—D20:F0) ........................................................................... 588

16.1.25 PWR_CNTL_STS—Power Management Control / 

Status Register (USB xHCI—D20:F0) ..................................................... 589

16.1.26 MSI_CAPID—Message Signaled Interrupt Capability ID Register 

(USB xHCI—D20:F0) ........................................................................... 589

16.1.27 NEXT_PTR2—Next Item Pointer Register #2

(USB xHCI—D20:F0) ........................................................................... 589

16.1.28 MSI_MCTL—MSI Message Control Register 

(USB xHCI—D20:F0) ........................................................................... 590

16.1.29 MSI_LMAD—MSI Lower Message Address Register 

(USB xHCI—D20:F0) ........................................................................... 590

16.1.30 MSI_UMAD—MSI Upper Message Address Register 

(USB xHCI—D20:F0) ........................................................................... 590

16.1.31 MSI_MD—MSI Message Data Register 

(USB xHCI—D20:F0) ........................................................................... 591

16.1.32 U2OCM1 - XHCI USB2 Overcurrent Mapping Register1 

(USB xHCI—D20:F0) ........................................................................... 591

16.1.33 U2OCM2 - XHCI USB2 Overcurrent Mapping Register 2 

(USB xHCI—D20:F0) ........................................................................... 591

16.1.34 U3OCM1 - XHCI USB3 Overcurrent Pin Mapping 1 

(USB xHCI—D20:F0) ........................................................................... 592

16.1.35 U3OCM2 - XHCI USB3 Overcurrent Pin Mapping 2 

(USB xHCI—D20:F0) ........................................................................... 593

16.1.36 XUSB2PR—xHC USB 2.0 Port Routing Register 

(USB xHCI—D20:F0) ........................................................................... 593

16.1.37 XUSB2PRM—xHC USB 2.0 Port Routing Mask Register 

(USB xHCI—D20:F0) ........................................................................... 594

16.1.38 USB3_PSSEN—USB 3.0 Port SuperSpeed Enable Register 

(USB xHCI—D20:F0) ........................................................................... 594

16.1.39 USB3PRM—USB 3.0 Port Routing Mask Register 

(USB xHCI—D20:F0) ........................................................................... 595

16.1.40 USB2PDO—xHCI USB Port Disable Override Register

(USB xHCI—D20:F0) ........................................................................... 595

16.1.41 USB3PDO—USB3 Port Disable Override

(USB xHCI—D20:F0) ........................................................................... 596

16.2 Memory-Mapped I/O Registers.......................................................................... 596

16.2.1 Host Controller Capability Registers ....................................................... 597

16.2.1.1 CAPLENGTH—Capability Registers Length Register..................... 597

16.2.1.2 HCIVERSION—Host Controller Interface Version Number 

16.2.1.3 HCSPARAMS1—Host Controller Structural Parameters #1 Register597

16.2.1.4 HCSPARAMS2—Host Controller Structural Parameters #2 Register598

16.2.1.5 HCSPARAMS3—Host Controller Structural Parameters #3 Register598

16.2.1.6 HCCPARAMS—Host Controller Capability Parameters Register ..... 599

Datasheet 19

16.2.1.7 dBOFF—Doorbell Offset Register..............................................599

16.2.1.8 RTSOFF—Runtime Register Space Offset Register ...................... 600

16.2.2 Host Controller Operational Registers .....................................................600

16.2.2.1 USB_CMD—USB Command Register.........................................601

16.2.2.2 USB_STS—USB Status Register...............................................602

16.2.2.3 PAGESIZE—Page Size Register ................................................ 603

16.2.2.4 DNCTRL—Device Notification Control Register ...........................603

16.2.2.5 CRCRL—Command Ring Control Low Register ............................ 604

16.2.2.6 CRCRH—Command Ring Control High Register .......................... 605

16.2.2.7 DCBAAPL—Device Context Base Address Array Pointer Low 

16.2.2.8 DCBAAPH—Device Context Base Address Array Pointer High 

16.2.2.9 CONFIG—Configure Register ...................................................605

16.2.2.10 PORTSCNUSB2—Port N Status and Control USB2 Register ........... 606

16.2.2.11 PORTPMSCNUSB2—xHCI Port N Power Management Status and 

Control USB2 Register............................................................610

16.2.2.12 PORTSCNUSB3—xHCI USB 3.0 Port N Status and Control Register611

16.2.2.13 PORTPMSCN—Port N Power Management Status and Control 

USB3 Register....................................................................... 615

16.2.2.14 PORTLIX—USB 3.0 Port X Link Info Register .............................. 616

16.2.3 Host Controller Runtime Registers.......................................................... 616

16.2.3.1 MFINDEX—Microframe Index Register ......................................616

16.2.3.2 IMAN—Interrupter X Management Register ...............................617

16.2.3.3 IMOD—Interrupter X Moderation Register .................................618

16.2.3.4 ERSTSZ—Event Ring Segment Table Size X Register .................. 618

16.2.3.5 ERSTBAL—Event Ring Segment Table Base Address Low X 

16.2.3.6 ERSTBAH—Event Ring Segment Table Base Address High X 

16.2.3.7 ERDPL—Event Ring Dequeue Pointer Low X Register .................. 620

16.2.3.8 ERDPH—Event Ring Dequeue Pointer High X Register ................. 620

16.2.4 Doorbell Registers ...............................................................................620

16.2.4.1 DOORBELL—Doorbell X Register .............................................. 621

17 Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers ....622

17.1 Intel

High Definition Audio (Intel® HD Audio) Controller Registers (D27:F0) .......... 622

17.1.1 Intel® High Definition Audio PCI Configuration Space 

(Intel® High Definition Audio—D27:F0) .................................................. 622

17.1.1.1 VID—Vendor Identification Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 624

17.1.1.2 DID—Device Identification Register

(Intel® High Definition Audio Controller—D27:F0)...................... 624

17.1.1.3 PCICMD—PCI Command Register (Intel

High Definition Audio Controller—D27:F0)...................... 624

17.1.1.4 PCISTS—PCI Status Register

(Intel® High Definition Audio Controller—D27:F0)...................... 625

17.1.1.5 RID—Revision Identification Register

(Intel® High Definition Audio Controller—D27:F0)...................... 625

17.1.1.6 PI—Programming Interface Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 626

17.1.1.7 SCC—Sub Class Code Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 626

17.1.1.8 BCC—Base Class Code Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 626

17.1.1.9 CLS—Cache Line Size Register

(Intel® High Definition Audio Controller—D27:F0)...................... 626

17.1.1.10 LT—Latency Timer Register

(Intel® High Definition Audio Controller—D27:F0)...................... 626

17.1.1.11 HEADTYP—Header Type Register

17.1.1.12 HdBARL—Intel

(Intel® High Definition Audio Controller—D27:F0)...................... 627

High Definition Audio Lower Base Address 

17.1.1.13 HdBARU—Intel® High Definition Audio Upper Base Address 

17.1.1.14 SVID—Subsystem Vendor Identification Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 627

20 Datasheet



17.1.1.15 SID—Subsystem Identification Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 628

17.1.1.16 CAPPTR—Capabilities Pointer Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 628

17.1.1.17 INTLN—Interrupt Line Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 628

17.1.1.18 INTPN—Interrupt Pin Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 628

17.1.1.19 HDCTL—Intel® High Definition Audio Control Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 629

17.1.1.20 DCKCTL—Docking Control Register (Mobile Only) 

(Intel® High Definition Audio Controller—D27:F0) ..................... 629

17.1.1.21 DCKSTS—Docking Status Register (Mobile Only)

(Intel® High Definition Audio Controller—D27:F0) ..................... 629

17.1.1.22 PID—PCI Power Management Capability ID Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 630

17.1.1.23 PC—Power Management Capabilities Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 630

17.1.1.24 PCS—Power Management Control and Status Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 630

17.1.1.25 MID—MSI Capability ID Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 631

17.1.1.26 MMC—MSI Message Control Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 631

17.1.1.27 MMLA—MSI Message Lower Address Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 632

17.1.1.28 MMUA—MSI Message Upper Address Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 632

17.1.1.29 MMD—MSI Message Data Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 632

17.1.1.30 PXID—PCI Express* Capability ID Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 632

17.1.1.31 PXC—PCI Express* Capabilities Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 632

17.1.1.32 DEVCAP—Device Capabilities Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 633

17.1.1.33 DEVC—Device Control Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 633

17.1.1.34 DEVS—Device Status Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 634

17.1.1.35 VCCAP—Virtual Channel Enhanced Capability Header

(Intel® High Definition Audio Controller—D27:F0) ..................... 634

17.1.1.36 PVCCAP1—Port VC Capability Register 1

(Intel® High Definition Audio Controller—D27:F0) ..................... 635

17.1.1.37 PVCCAP2—Port VC Capability Register 2 (Intel

High Definition Audio Controller—D27:F0) ..................... 635

17.1.1.38 PVCCTL—Port VC Control Register

(Intel® High Definition Audio Controller—D27:F0) ..................... 635

17.1.1.39 PVCSTS—Port VC Status Register

(Intel® High Definition Audio Controller—D27:F0) ..................... 635

17.1.1.40 VC0CAP—VC0 Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0) ..................... 636

17.1.1.41 VC0CTL—VC0 Resource Control Register

(Intel® High Definition Audio Controller—D27:F0) ..................... 636

17.1.1.42 VC0STS—VC0 Resource Status Register

(Intel® High Definition Audio Controller—D27:F0) ..................... 636

17.1.1.43 VCiCAP—VCi Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0) ..................... 637

17.1.1.44 VCiCTL—VCi Resource Control Register

(Intel® High Definition Audio Controller—D27:F0) ..................... 637

17.1.1.45 VCiSTS—VCi Resource Status Register (Intel

High Definition Audio Controller—D27:F0) ..................... 637

17.1.1.46 RCCAP—Root Complex Link Declaration Enhanced Capability Header Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 638

17.1.1.47 ESD—Element Self Description Register

(Intel® High Definition Audio Controller—D27:F0) ..................... 638

Datasheet 21

17.1.1.48 L1DESC—Link 1 Description Register

(Intel® High Definition Audio Controller—D27:F0)...................... 638

17.1.1.49 L1ADDL—Link 1 Lower Address Register

(Intel® High Definition Audio Controller—D27:F0)...................... 638

17.1.1.50 L1ADDU—Link 1 Upper Address Register

(Intel® High Definition Audio Controller—D27:F0)...................... 639

17.1.2 Intel® High Definition Audio Memory Mapped Configuration Registers 

(Intel® High Definition Audio D27:F0) ....................................................640

17.1.2.1 GCAP—Global Capabilities Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 643

17.1.2.2 VMIN—Minor Version Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 644

17.1.2.3 VMAJ—Major Version Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 644

17.1.2.4 OUTPAY—Output Payload Capability Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 644

17.1.2.5 INPAY—Input Payload Capability Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 644

17.1.2.6 GCTL—Global Control Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 645

17.1.2.7 WAKEEN—Wake Enable Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 646

17.1.2.8 STATESTS—State Change Status Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 646

17.1.2.9 GSTS—Global Status Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 646

17.1.2.10 GCAP2 Global Capabilities 2 Register

(Intel® High Definition Audio Controller—D27:F0)...................... 647

17.1.2.11 OUTSTRMPAY—Output Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0)...................... 647

17.1.2.12 INSTRMPAY—Input Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0)...................... 647

17.1.2.13 INTCTL—Interrupt Control Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 648

17.1.2.14 INTSTS—Interrupt Status Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 649

17.1.2.15 WALCLK—Wall Clock Counter Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 649

17.1.2.16 SSYNC—Stream Synchronization Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 650

17.1.2.17 CORBLBASE—CORB Lower Base Address Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 650

17.1.2.18 CORBUBASE—CORB Upper Base Address Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 650

17.1.2.19 CORBWP—CORB Write Pointer Register  (Intel

High Definition Audio Controller—D27:F0)...................... 651

17.1.2.20 CORBRP—CORB Read Pointer Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 651

17.1.2.21 CORBCTL—CORB Control Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 651

17.1.2.22 CORBST—CORB Status Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 652

17.1.2.23 CORBSIZE—CORB Size Register 

Intel® High Definition Audio Controller—D27:F0) ....................... 652

17.1.2.24 RIRBLBASE—RIRB Lower Base Address Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 652

17.1.2.25 RIRBUBASE—RIRB Upper Base Address Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 652

17.1.2.26 RIRBWP—RIRB Write Pointer Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 653

17.1.2.27 RINTCNT—Response Interrupt Count Register  (Intel

High Definition Audio Controller—D27:F0)...................... 653

17.1.2.28 RIRBCTL—RIRB Control Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 653

17.1.2.29 RIRBSTS—RIRB Status Register 

(Intel® High Definition Audio Controller—D27:F0)...................... 654

22 Datasheet



17.1.2.30 RIRBSIZE—RIRB Size Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 654

17.1.2.31 IC—Immediate Command Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 654

17.1.2.32 IR—Immediate Response Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 655

17.1.2.33 ICS—Immediate Command Status Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 655

17.1.2.34 DPLBASE—DMA Position Lower Base Address Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 655

17.1.2.35 DPUBASE—DMA Position Upper Base Address Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 656

17.1.2.36 SDCTL—Stream Descriptor Control Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 656

17.1.2.37 SDSTS—Stream Descriptor Status Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 657

17.1.2.38 SDLPIB—Stream Descriptor Link Position in Buffer

17.1.2.39 SDCBL—Stream Descriptor Cyclic Buffer Length Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 658

17.1.2.40 SDLVI—Stream Descriptor Last Valid Index Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 659

17.1.2.41 SDFIFOW—Stream Descriptor FIFO Watermark Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 659

17.1.2.42 ISDFIFOS—Input Stream Descriptor FIFO Size Register

(Intel® High Definition Audio Controller—D27:F0) ..................... 660

17.1.2.43 SDFMT—Stream Descriptor Format Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 660

17.1.2.44 SdBDPL—Stream Descriptor Buffer Descriptor List  Pointer Lower Base Address Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 661

17.1.2.45 SdBDPU—Stream Descriptor Buffer Descriptor List  Pointer Upper Base Address Register 

(Intel® High Definition Audio Controller—D27:F0) ..................... 661

18 SMBus Controller Registers (D31:F3) .................................................................... 662

18.1 PCI Configuration Registers (SMBus—D31:F3)..................................................... 662

18.1.1 VID—Vendor Identification Register (SMBus—D31:F3) ............................. 662

18.1.2 DID—Device Identification Register (SMBus—D31:F3) .............................. 663

18.1.3 PCICMD—PCI Command Register (SMBus—D31:F3)................................. 663

18.1.4 PCISTS—PCI Status Register (SMBus—D31:F3)....................................... 664

18.1.5 RID—Revision Identification Register (SMBus—D31:F3)............................ 664

18.1.6 PI—Programming Interface Register (SMBus—D31:F3)............................. 664

18.1.7 SCC—Sub Class Code Register (SMBus—D31:F3) .................................... 665

18.1.8 BCC—Base Class Code Register (SMBus—D31:F3) ................................... 665

18.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0

18.1.10 SMBMBAR1—D31_F3_SMBus Memory Base Address 1

18.1.11 SMB_BASE—SMBus Base Address Register 

(SMBus—D31:F3) ............................................................................... 666

18.1.12 SVID—Subsystem Vendor Identification Register

(SMBus—D31:F2/F4)........................................................................... 666

18.1.13 SID—Subsystem Identification Register 

(SMBus—D31:F2/F4)........................................................................... 666

18.1.14 INT_LN—Interrupt Line Register (SMBus—D31:F3) .................................. 666

18.1.15 INT_PN—Interrupt Pin Register (SMBus—D31:F3) ................................... 667

18.1.16 HOSTC—Host Configuration Register (SMBus—D31:F3) ............................ 667

18.2 SMBus I/O and Memory Mapped I/O Registers .................................................... 668

18.2.1 HST_STS—Host Status Register (SMBus—D31:F3) .................................. 669

18.2.2 HST_CNT—Host Control Register (SMBus—D31:F3) ................................. 670

18.2.3 HST_CMD—Host Command Register (SMBus—D31:F3) ............................ 671

18.2.4 XMIT_SLVA—Transmit Slave Address Register 

(SMBus—D31:F3) ............................................................................... 671

18.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3).................................... 671

18.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3).................................... 672

Datasheet 23

18.2.7 Host_BLOCK_dB—Host Block Data Byte Register 

(SMBus—D31:F3)................................................................................672

18.2.8 PEC—Packet Error Check (PEC) Register 

(SMBus—D31:F3)................................................................................672

18.2.9 RCV_SLVA—Receive Slave Address Register 

(SMBus—D31:F3)................................................................................673

18.2.10 SLV_DATA—Receive Slave Data Register (SMBus—D31:F3)....................... 673

18.2.11 AUX_STS—Auxiliary Status Register (SMBus—D31:F3) ............................. 673

18.2.12 AUX_CTL—Auxiliary Control Register (SMBus—D31:F3) ............................674

18.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register 

(SMBus—D31:F3)................................................................................674

18.2.14 SMBus_PIN_CTL—SMBus Pin Control Register

(SMBus—D31:F3)................................................................................675

18.2.15 SLV_STS—Slave Status Register (SMBus—D31:F3) ..................................675

18.2.16 SLV_CMD—Slave Command Register (SMBus—D31:F3) ............................676

18.2.17 NOTIFY_DADDR—Notify Device Address Register 

(SMBus—D31:F3)................................................................................676

18.2.18 NOTIFY_DLOW—Notify Data Low Byte Register 

(SMBus—D31:F3)................................................................................676

18.2.19 NOTIFY_DHIGH—Notify Data High Byte Register

(SMBus—D31:F3)................................................................................677

19 PCI Express* Configuration Registers ....................................................................678

19.1 PCI Express* Configuration Registers 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ................................................... 678

19.1.1 VID—Vendor Identification Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................680

19.1.2 DID—Device Identification Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................680

19.1.3 PCICMD—PCI Command Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................681

19.1.4 PCISTS—PCI Status Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................682

19.1.5 RID—Revision Identification Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................683

19.1.6 PI—Programming Interface Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................683

19.1.7 SCC—Sub Class Code Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................683

19.1.8 BCC—Base Class Code Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................683

19.1.9 CLS—Cache Line Size Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................684

19.1.10 PLT—Primary Latency Timer Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................684

19.1.11 HEADTYP—Header Type Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................684

19.1.12 BNUM—Bus Number Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................685

19.1.13 SLT—Secondary Latency Timer Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................685

19.1.14 IOBL—I/O Base and Limit Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................685

19.1.15 SSTS—Secondary Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................686

19.1.16 MBL—Memory Base and Limit Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................687

19.1.17 PMBL—Prefetchable Memory Base and Limit Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................687

19.1.18 PMBU32—Prefetchable Memory Base Upper 32 Bits

19.1.19 PMLU32—Prefetchable Memory Limit Upper 32 Bits

19.1.20 CAPP—Capabilities List Pointer Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................688

19.1.21 INTR—Interrupt Information Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................688

24 Datasheet



19.1.22 BCTRL—Bridge Control Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 689

19.1.23 CLIST—Capabilities List Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 689

19.1.24 XCAP—PCI Express* Capabilities Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 690

19.1.25 DCAP—Device Capabilities Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 690

19.1.26 DCTL—Device Control Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 691

19.1.27 DSTS—Device Status Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 692

19.1.28 LCAP—Link Capabilities Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 692

19.1.29 LCTL—Link Control Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 694

19.1.30 LSTS—Link Status Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 695

19.1.31 SLCAP—Slot Capabilities Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 696

19.1.32 SLCTL—Slot Control Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 697

19.1.33 SLSTS—Slot Status Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 697

19.1.34 RCTL—Root Control Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 698

19.1.35 RSTS—Root Status Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 698

19.1.36 DCAP2—Device Capabilities 2 Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 699

19.1.37 DCTL2—Device Control 2 Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 699

19.1.38 LCTL2—Link Control 2 Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 700

19.1.39 LSTS2—Link Status 2 Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 701

19.1.40 MID—Message Signaled Interrupt Identifiers Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 702

19.1.41 MC—Message Signaled Interrupt Message Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 702

19.1.42 MA—Message Signaled Interrupt Message Address

19.1.43 MD—Message Signaled Interrupt Message Data Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 703

19.1.44 SVCAP—Subsystem Vendor Capability Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 703

19.1.45 SVID—Subsystem Vendor Identification Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 703

19.1.46 PMCAP—Power Management Capability Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 703

19.1.47 PMC—PCI Power Management Capabilities Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 704

19.1.48 PMCS—PCI Power Management Control and Status

19.1.49 MPC2—Miscellaneous Port Configuration Register 2

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 705

19.1.50 MPC—Miscellaneous Port Configuration Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 705

19.1.51 SMSCS—SMI/SCI Status Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 707

19.1.52 RPDCGEN—Root Port Dynamic Clock Gating Enable

19.1.53 PECR3—PCI Express* Configuration Register 3

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 708

19.1.54 PECR4—PCI Express* Configuration Register 4

(PCI Express*—D28:F0/F1/F2/F3/F4/F5)................................................ 708

Datasheet 25

19.1.55 UES—Uncorrectable Error Status Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................710

19.1.56 UEM—Uncorrectable Error Mask Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................711

19.1.57 UEV—Uncorrectable Error Severity Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................712

19.1.58 CES—Correctable Error Status Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................713

19.1.59 CEM—Correctable Error Mask Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................713

19.1.60 AECC—Advanced Error Capabilities and Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................714

19.1.61 RES—Root Error Status Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................714

19.1.62 PECR2—PCI Express* Configuration Register 2 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................715

19.1.63 PEETM—PCI Express* Extended Test Mode Register 

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................715

19.1.64 PEC1—PCI Express* Configuration Register 1

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................................715

20 High Precision Event Timer Registers.....................................................................716

20.1 Memory Mapped Registers ................................................................................ 716

20.1.1 GCAP_ID—General Capabilities and Identification Register ........................ 717

20.1.2 GEN_CONF—General Configuration Register............................................ 718

20.1.3 GINTR_STA—General Interrupt Status Register .......................................718

20.1.4 MAIN_CNT—Main Counter Value Register................................................719

20.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register .................... 719

20.1.6 TIMn_COMP—Timer n Comparator Value Register ....................................721

20.1.7 TIMERn_PROCMSG_ROUT—Timer n Processor Message

Interrupt Rout Register ........................................................................ 722

21 Serial Peripheral Interface (SPI) ........................................................................... 723

21.1 Serial Peripheral Interface Memory Mapped Configuration Registers........................723

21.1.1 BFPR –BIOS Flash Primary Region Register 

(SPI Memory Mapped Configuration Registers) ........................................724

21.1.2 HSFS—Hardware Sequencing Flash Status Register 

(SPI Memory Mapped Configuration Registers) ........................................725

21.1.3 HSFC—Hardware Sequencing Flash Control Register 

(SPI Memory Mapped Configuration Registers) ........................................726

21.1.4 FADDR—Flash Address Register 

(SPI Memory Mapped Configuration Registers) ........................................726

21.1.5 FDATA0—Flash Data 0 Register 

(SPI Memory Mapped Configuration Registers) ........................................727

21.1.6 FDATAN—Flash Data [N] Register 

(SPI Memory Mapped Configuration Registers) ........................................727

21.1.7 FRAP—Flash Regions Access Permissions Register 

(SPI Memory Mapped Configuration Registers) ........................................728

21.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register 

(SPI Memory Mapped Configuration Registers) ........................................728

21.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register 

21.1.10 FREG2—Flash Region 2 (Intel

(SPI Memory Mapped Configuration Registers) ........................................729

ME) Register 

(SPI Memory Mapped Configuration Registers) ........................................729

21.1.11 FREG3—Flash Region 3 (GbE) Register 

(SPI Memory Mapped Configuration Registers) ........................................729

21.1.12 FREG4—Flash Region 4 (Platform Data) Register 

(SPI Memory Mapped Configuration Registers) ........................................730

21.1.13 PR0—Protected Range 0 Register 

(SPI Memory Mapped Configuration Registers) ........................................730

21.1.14 PR1—Protected Range 1 Register 

(SPI Memory Mapped Configuration Registers) ........................................731

21.1.15 PR2—Protected Range 2 Register 

(SPI Memory Mapped Configuration Registers) ........................................731

21.1.16 PR3—Protected Range 3 Register 

(SPI Memory Mapped Configuration Registers) ........................................732

26 Datasheet



21.1.17 PR4—Protected Range 4 Register 

(SPI Memory Mapped Configuration Registers)........................................ 732

21.1.18 SSFS—Software Sequencing Flash Status Register 

(SPI Memory Mapped Configuration Registers)........................................ 733

21.1.19 SSFC—Software Sequencing Flash Control Register 

(SPI Memory Mapped Configuration Registers)........................................ 734

21.1.20 PREOP—Prefix Opcode Configuration Register 

(SPI Memory Mapped Configuration Registers)........................................ 735

21.1.21 OPTYPE—Opcode Type Configuration Register 

(SPI Memory Mapped Configuration Registers)........................................ 735

21.1.22 OPMENU—Opcode Menu Configuration Register 

(SPI Memory Mapped Configuration Registers)........................................ 736

21.1.23 BBAR—BIOS Base Address Configuration Register 

(SPI Memory Mapped Configuration Registers)........................................ 736

21.1.24 FDOC—Flash Descriptor Observability Control Register 

(SPI Memory Mapped Configuration Registers)........................................ 737

21.1.25 FDOD—Flash Descriptor Observability Data Register 

(SPI Memory Mapped Configuration Registers)........................................ 737

21.1.26 AFC—Additional Flash Control Register 

(SPI Memory Mapped Configuration Registers)........................................ 737

21.1.27 LVSCC—Host Lower Vendor Specific Component Capabilities Register 

(SPI Memory Mapped Configuration Registers)........................................ 738

21.1.28 UVSCC—Host Upper Vendor Specific Component Capabilities Register 

(SPI Memory Mapped Configuration Registers)........................................ 739

21.1.29 PTINX—Flash Parameter Table Index Register......................................... 740

21.1.30 PTDATA—Flash Parameter Table Data Register........................................ 740

21.1.31 SRDL—Soft Reset Data Lock Register

(SPI Memory Mapped Configuration Registers)........................................ 740

21.1.32 SRDC—Soft Reset Data Control Register

(SPI Memory Mapped Configuration Registers)........................................ 741

21.1.33 SRD—Soft Reset Data Register

(SPI Memory Mapped Configuration Registers)........................................ 741

21.2 Flash Descriptor Records .................................................................................. 741

21.3 OEM Section ................................................................................................... 741

21.4 GbE SPI Flash Program Registers....................................................................... 742

21.4.1 GLFPR –Gigabit LAN Flash Primary Region Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 743

21.4.2 HSFS—Hardware Sequencing Flash Status Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 743

21.4.3 HSFC—Hardware Sequencing Flash Control Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 744

21.4.4 FADDR—Flash Address Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 745

21.4.5 FDATA0—Flash Data 0 Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 745

21.4.6 FRAP—Flash Regions Access Permissions Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 745

21.4.7 FREG0—Flash Region 0 (Flash Descriptor) Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 746

21.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register 

21.4.9 FREG2—Flash Region 2 (Intel

(GbE LAN Memory Mapped Configuration Registers)................................. 746

ME) Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 746

21.4.10 FREG3—Flash Region 3 (GbE) Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 747

21.4.11 PR0—Protected Range 0 Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 747

21.4.12 PR1—Protected Range 1 Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 748

21.4.13 SSFS—Software Sequencing Flash Status Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 748

21.4.14 SSFC—Software Sequencing Flash Control Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 749

21.4.15 PREOP—Prefix Opcode Configuration Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 750

21.4.16 OPTYPE—Opcode Type Configuration Register 

(GbE LAN Memory Mapped Configuration Registers)................................. 750

Datasheet 27

21.4.17 OPMENU—Opcode Menu Configuration Register 

(GbE LAN Memory Mapped Configuration Registers).................................751

22 Thermal Sensor Registers (D31:F6) .......................................................................752

22.1 PCI Bus Configuration Registers......................................................................... 752

22.1.1 VID—Vendor Identification Register .......................................................752

22.1.2 DID—Device Identification Register........................................................ 753

22.1.3 CMD—Command Register .....................................................................753

22.1.4 STS—Status Register ...........................................................................753

22.1.5 RID—Revision Identification Register...................................................... 754

22.1.6 PI—Programming Interface Register.......................................................754

22.1.7 SCC—Sub Class Code Register ..............................................................754

22.1.8 BCC—Base Class Code Register .............................................................754

22.1.9 CLS—Cache Line Size Register ..............................................................754

22.1.10 LT—Latency Timer Register................................................................... 755

22.1.11 HTYPE—Header Type Register ...............................................................755

22.1.12 TBAR—Thermal Base Register ...............................................................755

22.1.13 TBARH—Thermal Base High DWord Register............................................755

22.1.14 SVID—Subsystem Vendor ID Register .................................................... 756

22.1.15 SID—Subsystem ID Register.................................................................756

22.1.16 CAP_PTR—Capabilities Pointer Register................................................... 756

22.1.17 INTLN—Interrupt Line Register..............................................................756

22.1.18 INTPN—Interrupt Pin Register ...............................................................757

22.1.19 TBARB—BIOS Assigned Thermal Base Address Register ............................ 757

22.1.20 TBARBH—BIOS Assigned Thermal Base High

DWord Register...................................................................................757

22.1.21 PID—PCI Power Management Capability ID Register ................................. 757

22.1.22 PC—Power Management Capabilities Register ..........................................758

22.1.23 PCS—Power Management Control And Status Register .............................. 758

22.2 Thermal Memory Mapped Configuration Registers

(Thermal Sensor – D31:F26).............................................................................759

22.2.1 TEMP—Temperature Register ................................................................759

22.2.2 TSC—Thermal Sensor Control Register ...................................................760

22.2.3 TSS—Thermal Sensor Status Register ....................................................760

22.2.4 TSEL—Thermal Sensor Enable and Lock Register .....................................760

22.2.5 TSREL—Thermal Sensor Reporting Enable and Lock Register .....................761

22.2.6 TSMIC—Thermal Sensor SMI Control Register .........................................761

22.2.7 CTT—Catastrophic Trip Point Register.....................................................761

22.2.8 TAHV—Thermal Alert High Value Register ............................................... 761

22.2.9 TALV—Thermal Alert Low Value Register.................................................762

22.2.10 TL—Throttle Levels Register.................................................................. 762

22.2.11 PHL—PCH Hot Level Register................................................................. 763

22.2.12 PHLC—PHL Control Register ..................................................................763

22.2.13 TAS—Thermal Alert Status Register .......................................................763

22.2.14 TSPIEN—PCI Interrupt Event Enables Register......................................... 763

22.2.15 TSGPEN—General Purpose Event Enables Register ................................... 764

23 Intel

Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])........... 765

23.1 First Intel

Management Engine Interface (Intel® MEI) Configuration Registers 

(Intel® MEI 1—D22:F0)....................................................................................765

23.1.1 PCI Configuration Registers (Intel® MEI 1—D22:F0).................................765

23.1.1.1 VID—Vendor Identification Register 

(Intel® MEI 1—D22:F0)..........................................................766

23.1.1.2 DID—Device Identification Register 

(Intel® MEI 1—D22:F0)..........................................................766

23.1.1.3 PCICMD—PCI Command Register

(Intel® MEI 1—D22:F0)..........................................................766

23.1.1.4 PCISTS—PCI Status Register 

(Intel® MEI 1—D22:F0)..........................................................767

23.1.1.5 RID—Revision Identification Register 

(Intel® MEI 1—D22:F0)..........................................................767

23.1.1.6 CC—Class Code Register  (Intel

MEI 1—D22:F0)..........................................................767

23.1.1.7 HTYPE—Header Type Register 

(Intel® MEI 1—D22:F0)..........................................................768

23.1.1.8 MEI0_MBAR—Intel® MEI 1 MMIO Base Address

(Intel® MEI 1—D22:F0)..........................................................768

28 Datasheet



23.1.1.9 SVID—Subsystem Vendor ID Register

(Intel® MEI 1—D22:F0) ......................................................... 768

23.1.1.10 SID—Subsystem ID Register

(Intel® MEI 1—D22:F0) ......................................................... 768

23.1.1.11 CAPP—Capabilities List Pointer Register 

(Intel® MEI 1—D22:F0) ......................................................... 769

23.1.1.12 INTR—Interrupt Information Register

(Intel® MEI 1—D22:F0) ......................................................... 769

23.1.1.13 HFS—Host Firmware Status Register

(Intel® MEI 1—D22:F0) ......................................................... 769

23.1.1.14 ME_UMA—Intel® Management Engine UMA Register

(Intel® MEI 1—D22:F0) ......................................................... 769

23.1.1.15 GMES—General Intel® ME Status Register

(Intel® MEI 1—D22:F0) ......................................................... 770

23.1.1.16 H_GS—Host General Status Register

(Intel® MEI 1—D22:F0) ......................................................... 770

23.1.1.17 PID—PCI Power Management Capability ID Register

(Intel® MEI 1—D22:F0) ......................................................... 770

23.1.1.18 PC—PCI Power Management Capabilities Register 

(Intel® MEI 1—D22:F0) ......................................................... 770

23.1.1.19 PMCS—PCI Power Management Control and Status

23.1.1.20 GMES2—General Intel® ME Status Register 2

(Intel® MEI 1—D22:F0) ......................................................... 771

23.1.1.21 GMES3—General Intel® ME Status Register 3

(Intel® MEI 1—D22:F0) ......................................................... 771

23.1.1.22 GMES4—General Intel® ME Status Register 4

(Intel® MEI 1—D22:F0) ......................................................... 772

23.1.1.23 GMES5—General Intel® ME Status Register 5

(Intel® MEI 1—D22:F0) ......................................................... 772

23.1.1.24 H_GS2—Host General Status Register 2

(Intel® MEI 1—D22:F0) ......................................................... 772

23.1.1.25 H_GS3—Host General Status Register 3

(Intel® MEI 1—D22:F0) ......................................................... 772

23.1.1.26 MID—Message Signaled Interrupt Identifiers Register

(Intel® MEI 1—D22:F0) ......................................................... 772

23.1.1.27 MC—Message Signaled Interrupt Message Control Register

(Intel® MEI 1—D22:F0) ......................................................... 773

23.1.1.28 MA—Message Signaled Interrupt Message Address Register

(Intel® MEI 1—D22:F0) ......................................................... 773

23.1.1.29 MUA—Message Signaled Interrupt Upper Address Register

(Intel® MEI 1—D22:F0) ......................................................... 773

23.1.1.30 MD—Message Signaled Interrupt Message Data Register

(Intel® MEI 1—D22:F0) ......................................................... 773

23.1.1.31 HIDM—MEI Interrupt Delivery Mode Register (Intel

MEI 1—D22:F0) ......................................................... 774

23.1.1.32 HERES—Intel® MEI Extend Register Status 

(Intel® MEI 1—D22:F0) ......................................................... 774

23.1.1.33 HERX—Intel® MEI Extend Register DWX

(Intel® MEI 1—D22:F0) ......................................................... 774

23.1.2 MEI0_MBAR—Intel® MEI 1 MMIO Registers............................................. 775

23.1.2.1 H_CB_WW—Host Circular Buffer Write Window Register

(Intel® MEI 1 MMIO Register)................................................. 775

23.1.2.2 H_CSR—Host Control Status Register

(Intel® MEI 1 MMIO Register)................................................. 775

23.1.2.3 ME_CB_RW—Intel® ME Circular Buffer Read Window Register

(Intel® MEI 1 MMIO Register)................................................. 776

23.1.2.4 ME_CSR_HA—Intel® ME Control Status Host Access Register

(Intel® MEI 1 MMIO Register)................................................. 776

23.2 Second Intel® Management Engine Interface (Intel

MEI 2) Configuration Registers 

(Intel® MEI 2—D22:F1) ................................................................................... 777

23.2.1 PCI Configuration Registers (Intel® MEI 2—D22:F2) ................................ 777

23.2.1.1 VID—Vendor Identification Register 

(Intel® MEI 2—D22:F1) ......................................................... 778

23.2.1.2 DID—Device Identification Register 

(Intel® MEI 2—D22:F1) ......................................................... 778

Datasheet 29

23.2.1.3 PCICMD—PCI Command Register

(Intel® MEI 2—D22:F1)..........................................................778

23.2.1.4 PCISTS—PCI Status Register 

(Intel® MEI 2—D22:F1)..........................................................779

23.2.1.5 RID—Revision Identification Register 

(Intel® MEI 2—D22:F1)..........................................................779

23.2.1.6 CC—Class Code Register 

(Intel® MEI 2—D22:F1)..........................................................779

23.2.1.7 HTYPE—Header Type Register 

(Intel® MEI 2—D22:F1)..........................................................779

23.2.1.8 MEI1_MBAR—Intel MEI 2 MMIO Base Address

(Intel® MEI 2—D22:F1)..........................................................780

23.2.1.9 SVID—Subsystem Vendor ID Register

(Intel® MEI 2—D22:F1)..........................................................780

23.2.1.10 SID—Subsystem ID Register

(Intel® MEI 2—D22:F1)..........................................................780

23.2.1.11 CAPP—Capabilities List Pointer Register 

(Intel® MEI 2—D22:F1)..........................................................780

23.2.1.12 INTR—Interrupt Information Register

(Intel® MEI 2—D22:F1)..........................................................781

23.2.1.13 HFS—Host Firmware Status Register

(Intel® MEI 2—D22:F1)..........................................................781

23.2.1.14 GMES—General Intel® ME Status Register

(Intel® MEI 2—D22:F1)..........................................................781

23.2.1.15 H_GS—Host General Status Register

(Intel® MEI 2—D22:F1)..........................................................781

23.2.1.16 PID—PCI Power Management Capability ID Register

(Intel® MEI 2—D22:F1)..........................................................781

23.2.1.17 PC—PCI Power Management Capabilities Register 

(Intel® MEI 2—D22:F1)..........................................................782

23.2.1.18 PMCS—PCI Power Management Control and Status

23.2.1.19 GMES2—General Intel® ME Status Register 2

(Intel® MEI 2—D22:F1)..........................................................783

23.2.1.20 GMES3—General Intel® ME Status Register 3

(Intel® MEI 2—D22:F1)..........................................................783

23.2.1.21 GMES4—General Intel® ME Status Register 4

(Intel® MEI 2—D22:F1)..........................................................783

23.2.1.22 GMES5—General Intel® ME Status Register 5

(Intel® MEI 2—D22:F1)..........................................................783

23.2.1.23 H_GS2—Host General Status Register 2

(Intel® MEI 2—D22:F1)..........................................................783

23.2.1.24 H_GS3—Host General Status Register 3

(Intel® MEI 2—D22:F1)..........................................................784

23.2.1.25 MID—Message Signaled Interrupt Identifiers Register (Intel

23.2.1.26 MC—Message Signaled Interrupt Message Control Register

(Intel® MEI 2—D22:F1)..........................................................784

23.2.1.27 MA—Message Signaled Interrupt Message Address Register

(Intel® MEI 2—D22:F1)..........................................................784

23.2.1.28 MUA—Message Signaled Interrupt Upper Address Register

(Intel® MEI 2—D22:F1)..........................................................785

23.2.1.29 MD—Message Signaled Interrupt Message Data Register

(Intel® MEI 2—D22:F1)..........................................................785

23.2.1.30 HIDM—Intel® MEI Interrupt Delivery Mode Register

(Intel® MEI 2—D22:F1)..........................................................785

23.2.1.31 HERES—Intel® MEI Extend Register Status 

(Intel® MEI 2—D22:F1)..........................................................785

23.2.1.32 HERX—Intel® MEI Extend Register DWX

(Intel® MEI 2—D22:F1)..........................................................786

23.2.2 MEI1_MBAR—Intel

23.2.2.1 H_CB_WW—Host Circular Buffer Write Window

(Intel® MEI 2 MMIO Register) .................................................786

23.2.2.2 H_CSR—Host Control Status Register

(Intel® MEI 2 MMIO Register) .................................................787

23.2.2.3 ME_CB_RW—Intel® ME Circular Buffer Read Window Register

(Intel® MEI 2 MMIO Register) .................................................787

MEI 2—D22:F1)..........................................................784

MEI 2 MMIO Registers .............................................786

30 Datasheet



23.2.2.4 ME_CSR_HA—Intel® ME Control Status Host Access Register

(Intel® MEI 2 MMIO Register)................................................. 788

23.3 IDE Redirect IDER Registers (IDER—D22:F2) ...................................................... 789

23.3.1 PCI Configuration Registers (IDER—D22:F2)........................................... 789

23.3.1.1 VID—Vendor Identification Register (IDER—D22:F2).................. 789

23.3.1.2 DID—Device Identification Register (IDER—D22:F2) .................. 790

23.3.1.3 PCICMD—PCI Command Register (IDER—D22:F2)..................... 790

23.3.1.4 PCISTS—PCI Device Status Register (IDER—D22:F2)................. 790

23.3.1.5 RID—Revision Identification Register (IDER—D22:F2) ................ 790

23.3.1.6 CC—Class Codes Register (IDER—D22:F2) ............................... 791

23.3.1.7 CLS—Cache Line Size Register (IDER—D22:F2)......................... 791

23.3.1.8 PCMdBA—Primary Command Block IO Bar 

23.3.1.9 PCTLBA—Primary Control Block Base Address 

23.3.1.10 SCMdBA—Secondary Command Block Base Address

23.3.1.11 SCTLBA—Secondary Control Block base Address 

23.3.1.12 LBAR—Legacy Bus Master Base Address Register 

(IDER—D22:F2).................................................................... 792

23.3.1.13 SVID—Subsystem Vendor ID Register (IDER—D22:F2) .............. 792

23.3.1.14 SID—Subsystem ID Register (IDER—D22:F2) ........................... 793

23.3.1.15 CAPP—Capabilities List Pointer Register 

(IDER—D22:F2).................................................................... 793

23.3.1.16 INTR—Interrupt Information Register 

(IDER—D22:F2).................................................................... 793

23.3.1.17 PID—PCI Power Management Capability ID Register

(IDER—D22:F2).................................................................... 793

23.3.1.18 PC—PCI Power Management Capabilities Register 

(IDER—D22:F2).................................................................... 794

23.3.1.19 PMCS—PCI Power Management Control and Status 

23.3.1.20 MID—Message Signaled Interrupt Capability ID 

23.3.1.21 MC—Message Signaled Interrupt Message Control 

23.3.1.22 MA—Message Signaled Interrupt Message Address 

23.3.1.23 MAU—Message Signaled Interrupt Message Upper 

Address Register (IDER—D22:F2) ........................................... 795

23.3.1.24 MD—Message Signaled Interrupt Message Data 

23.3.2 IDER BAR0 Registers ........................................................................... 796

23.3.2.1 IDEDATA—IDE Data Register (IDER—D22:F2)........................... 797

23.3.2.2 IDEERD1—IDE Error Register DEV1 

(IDER—D22:F2).................................................................... 797

23.3.2.3 IDEERD0—IDE Error Register DEV0 

(IDER—D22:F2).................................................................... 797

23.3.2.4 IDEFR—IDE Features Register 

(IDER—D22:F2).................................................................... 798

23.3.2.5 IDESCIR—IDE Sector Count In Register 

(IDER—D22:F2).................................................................... 798

23.3.2.6 IDESCOR1—IDE Sector Count Out Register Device 1 

23.3.2.7 IDESCOR0—IDE Sector Count Out Register Device 

0 Register (IDER—D22:F2)..................................................... 799

23.3.2.8 IDESNOR0—IDE Sector Number Out Register 

Device 0 Register (IDER—D22:F2) .......................................... 799

23.3.2.9 IDESNOR1—IDE Sector Number Out Register 

Device 1 Register (IDER—D22:F2) .......................................... 799

23.3.2.10 IDESNIR—IDE Sector Number In Register (IDER—D22:F2) ......... 800

23.3.2.11 IDECLIR—IDE Cylinder Low In Register (IDER—D22:F2)............. 800

23.3.2.12 IDCLOR1—IDE Cylinder Low Out Register Device 1 

23.3.2.13 IDCLOR0—IDE Cylinder Low Out Register Device 0 

Datasheet 31

23.3.2.14 IDCHOR0—IDE Cylinder High Out Register Device 0 

23.3.2.15 IDCHOR1—IDE Cylinder High Out Register Device 1 

23.3.2.16 IDECHIR—IDE Cylinder High In Register 

(IDER—D22:F2) ....................................................................802

23.3.2.17 IDEDHIR—IDE Drive/Head In Register 

(IDER—D22:F2) ....................................................................802

23.3.2.18 IDDHOR1—IDE Drive Head Out Register Device 1 

23.3.2.19 IDDHOR0—IDE Drive Head Out Register Device 0 

23.3.2.20 IDESD0R—IDE Status Device 0 Register 

(IDER—D22:F2) ....................................................................803

23.3.2.21 IDESD1R—IDE Status Device 1 Register 

(IDER—D22:F2) ....................................................................804

23.3.2.22 IDECR—IDE Command Register (IDER—D22:F2) .......................805

23.3.3 IDER BAR1 Registers ........................................................................... 805

23.3.3.1 IDDCR—IDE Device Control Register (IDER—D22:F2)................. 805

23.3.3.2 IDASR—IDE Alternate Status Register (IDER—D22:F2)............... 806

23.3.4 IDER BAR4 Registers ........................................................................... 806

23.3.4.1 IDEPBMCR—IDE Primary Bus Master Command 

23.3.4.2 IDEPBMDS0R—IDE Primary Bus Master Device 

Specific 0 Register (IDER—D22:F2)..........................................807

23.3.4.3 IDEPBMSR—IDE Primary Bus Master Status 

23.3.4.4 IDEPBMDS1R—IDE Primary Bus Master Device 

Specific 1 Register (IDER—D22:F2)..........................................808

23.3.4.5 IDEPBMDTPR0—IDE Primary Bus Master Descriptor 

Table Pointer Byte 0 Register (IDER—D22:F2) ........................... 808

23.3.4.6 IDEPBMDTPR1—IDE Primary Bus Master Descriptor 

Table Pointer Byte 1 Register (IDER—D22:F2) ........................... 808

23.3.4.7 IDEPBMDTPR2—IDE Primary Bus Master Descriptor 

Table Pointer Byte 2 Register (IDER—D22:F2) ........................... 808

23.3.4.8 IDEPBMDTPR3—IDE Primary Bus Master Descriptor 

Table Pointer Byte 3 Register (IDER—D22:F2) ........................... 808

23.3.4.9 IDESBMCR—IDE Secondary Bus Master Command 

23.3.4.10 IDESBMDS0R—IDE Secondary Bus Master Device 

Specific 0 Register (IDER—D22:F2)..........................................809

23.3.4.11 IDESBMSR—IDE Secondary Bus Master Status 

23.3.4.12 IDESBMDS1R—IDE Secondary Bus Master Device 

Specific 1 Register (IDER—D22:F2)..........................................810

23.3.4.13 IDESBMDTPR0—IDE Secondary Bus Master Descriptor 

Table Pointer Byte 0 Register (IDER—D22:F2) ........................... 810

23.3.4.14 IDESBMDTPR1—IDE Secondary Bus Master Descriptor 

Table Pointer Byte 1 Register (IDER—D22:F2) ........................... 810

23.3.4.15 IDESBMDTPR2—IDE Secondary Bus Master Descriptor 

Table Pointer Byte 2 Register (IDER—D22:F2) ........................... 810

23.3.4.16 IDESBMDTPR3—IDE Secondary Bus Master Descriptor 

Table Pointer Byte 3 Register (IDER—D22:F2) ........................... 811

23.4 Serial Port for Remote Keyboard and Text (KT) 

Redirection (KT—D22:F3) .................................................................................811

23.4.1 PCI Configuration Registers (KT—D22:F3)............................................... 811

23.4.1.1 VID—Vendor Identification Register (KT—D22:F3) ..................... 812

23.4.1.2 DID—Device Identification Register (KT—D22:F3)......................812

23.4.1.3 CMD—Command Register (KT—D22:F3) ...................................812

23.4.1.4 STS—Device Status Register (KT—D22:F3) ............................... 812

23.4.1.5 RID—Revision ID Register (KT—D22:F3) ..................................813

23.4.1.6 CC—Class Codes Register (KT—D22:F3) ...................................813

23.4.1.7 CLS—Cache Line Size Register (KT—D22:F3) ............................ 813

23.4.1.8 KTIBA—KT IO Block Base Address Register 

(KT—D22:F3) .......................................................................813

23.4.1.9 KTMBA—KT Memory Block Base Address Register 

(KT—D22:F3) .......................................................................814

32 Datasheet



23.4.1.10 SVID—Subsystem Vendor ID Register (KT—D22:F3).................. 814

23.4.1.11 SID—Subsystem ID Register (KT—D22:F3) .............................. 814

23.4.1.12 CAP—Capabilities Pointer Register (KT—D22:F3) ....................... 814

23.4.1.13 INTR—Interrupt Information Register (KT—D22:F3) .................. 815

23.4.1.14 PID—PCI Power Management Capability ID Register 

(KT—D22:F3) ....................................................................... 815

23.4.1.15 PC—PCI Power Management Capabilities ID Register 

(KT—D22:F3) ....................................................................... 815

23.4.1.16 MID—Message Signaled Interrupt Capability ID 

23.4.1.17 MC—Message Signaled Interrupt Message Control 

23.4.1.18 MA—Message Signaled Interrupt Message Address 

23.4.1.19 MAU—Message Signaled Interrupt Message Upper 

Address Register (KT—D22:F3)............................................... 817

23.4.1.20 MD—Message Signaled Interrupt Message Data 

23.4.2 KT IO/Memory Mapped Device Registers ................................................ 817

23.4.2.1 KTRxBR—KT Receive Buffer Register (KT—D22:F3).................... 818

23.4.2.2 KTTHR—KT Transmit Holding Register (KT—D22:F3).................. 818

23.4.2.3 KTDLLR—KT Divisor Latch LSB Register (KT—D22:F3)................ 818

23.4.2.4 KTIER—KT Interrupt Enable Register (KT—D22:F3) ................... 819

23.4.2.5 KTDLMR—KT Divisor Latch MSB Register (KT—D22:F3) .............. 819

23.4.2.6 KTIIR—KT Interrupt Identification Register 

(KT—D22:F3) ....................................................................... 819

23.4.2.7 KTFCR—KT FIFO Control Register (KT—D22:F3)........................ 820

23.4.2.8 KTLCR—KT Line Control Register (KT—D22:F3)......................... 820

23.4.2.9 KTMCR—KT Modem Control Register (KT—D22:F3).................... 821

23.4.2.10 KTLSR—KT Line Status Register (KT—D22:F3) .......................... 821

23.4.2.11 KTMSR—KT Modem Status Register (KT—D22:F3)..................... 822

Figures

2-1 PCH Interface Signals Block Diagram (not all signals are on all SKUs) ......................... 61

2-2 Example External RTC Circuit ................................................................................ 71

4-1 PCH Detailed Clock Diagram................................................................................ 110

5-1 Flexible I/O – High Speed Signal Mapping with PCI Express*, USB 3.0*, and SATA

5-2 Generation of SERR# to Platform......................................................................... 117

5-3 Valid PCI Express* Ports for Platform LAN Connect Device (GbE) Support.................. 118

5-4 LPC Interface Diagram........................................................................................ 126

5-5 PCH DMA Controller ........................................................................................... 130

5-6 DMA Request Assertion through LDRQ#................................................................ 134

5-7 Conceptual Diagram of SLP_LAN#........................................................................ 174

5-8 TCO Legacy/Compatible Mode SMBus Configuration................................................ 180

5-9 Advanced TCO Mode .......................................................................................... 182

5-10 Serial Post over GPIO Reference Circuit ................................................................ 184

5-11 Flow for Port Enable / Device Present Bits ............................................................. 192

5-12 Serial Data transmitted over the SGPIO Interface................................................... 196

5-13 EHCI with USB 2.0 with Rate Matching Hub ........................................................... 211

5-14 PCH Intel

5-15 Flash Descriptor Sections.................................................................................... 240

5-16 PCH Display Architecture .................................................................................... 249

5-17 Analog Port Characteristics.................................................................................. 250

5-18 Panel Power Sequencing ..................................................................................... 252

6-1 Desktop/Server PCH Ballout (Top View - Upper Left) .............................................. 256

6-2 Desktop/Server PCH Ballout (Top View - Lower Left) .............................................. 256

6-3 Desktop/Server PCH Ballout (Top View - Upper Right) ............................................ 257

6-4 Desktop/Server PCH Ballout (Top View - Lower Right) ............................................ 257

6-5 Mobile PCH Ballout (Top View - Upper Left) ........................................................... 264

6-6 Mobile PCH Ballout (Top View - Lower Left) ........................................................... 264

6-7 Mobile PCH Ballout (Top View - Upper Right) ......................................................... 265

6-8 Mobile PCH Ballout (Top View - Lower Right) ......................................................... 265

7-1 Tape and Reel Pin 1 Location............................................................................... 272

7-2 Desktop / Server PCH Package Drawing ................................................................ 273

Ports................................................................................................................ 112

Management Engine (Intel® ME) High-Level Block Diagram..................... 237

Datasheet 33

7-3 Tape and Reel Pin 1 Location ...............................................................................274

7-4 Mobile PCH Package Drawing ............................................................................... 275

8-1 G3 w/RTC Loss to S4/S5 (With Deep Sx Support) Timing Diagram............................303

8-2 G3 w/RTC Loss to S4/S5 (Without Deep Sx Support) Timing Diagram .......................303

8-3 S5 to S0 Timing Diagram ....................................................................................304

8-4 S3/M3 to S0 Timing Diagram...............................................................................305

8-5 S5/M-Off - S5/M3 Timing Diagram........................................................................305

8-6 S0 to S5 Timing Diagram ....................................................................................306

8-7 S3/S4/S5 to Deep Sx to G3 w/ RTC Loss Timing Diagram ........................................307

8-8 G3 to Deep Sx Timing Diagram ............................................................................ 307

8-10 Clock Cycle Time................................................................................................308

8-11 Transmitting Position (Data to Strobe) ..................................................................308

8-9 DRAMPWROK Timing Diagram..............................................................................308

8-12 Clock Timing......................................................................................................309

8-13 Valid Delay from Rising Clock Edge.......................................................................309

8-14 Setup and Hold Times.........................................................................................309

8-15 Float Delay........................................................................................................ 309

8-16 Pulse Width ....................................................................................................... 310

8-17 Output Enable Delay...........................................................................................310

8-18 USB Rise and Fall Times...................................................................................... 310

8-19 USB Jitter .........................................................................................................311

8-20 USB EOP Width.................................................................................................. 311

8-21 SMBus / SMLink Transaction................................................................................ 311

8-22 SMBus / SMLink Timeout.....................................................................................312

8-23 SPI Timings.......................................................................................................312

8-24 Intel® High Definition Audio (Intel® HD Audio) Input and Output Timings.................. 313

8-25 Dual Channel Interface Timings............................................................................313

8-26 Dual Channel Interface Timings............................................................................313

8-27 LVDS Load and Transition Times ..........................................................................314

8-28 Transmitting Position (Data to Strobe) ..................................................................314

8-29 PCI Express* Transmitter Eye.............................................................................. 314

8-30 PCI Express* Receiver Eye ..................................................................................315

8-31 Measurement Points for Differential Waveforms......................................................316

8-32 PCH Test Load ................................................................................................... 317

8-33 Controller Link Receive Timings............................................................................317

8-34 Controller Link Receive Slew Rate.........................................................................317

8-35 PCH Suspend Well Ramp Up/Down Requirement.....................................................317

8-36 Sequencing Requirements between PCH VCCSUS (1.05V) and External USB Vbus ....... 318

8-37 Sequencing Requirements between PCH VCC3_3 and VCC Core Rail.......................... 318

8-38 Sequencing Requirements between PCH VCC1_5 and VCC Core Rail.......................... 318

Tables

1-1 Industry Specifications..........................................................................................41

1-2 Desktop Intel® 8 Series Chipset Family SKUs...........................................................52

1-3 Intel® 8 Series/C220 Series Chipset Family PCH SKUs Flexible I/O Map .......................53

1-4 Mobile Intel® 8 Series Chipset Family SKUs .............................................................54

1-5 Intel® 8 Series/C220 Series Chipset Family PCH SKUs Flexible I/O Map .......................55

1-6 Server / Workstation Intel

1-7 Server / Workstation Intel® C220 Series Chipset Family SKUs Flexible I/O Map ............56

1-8 PCH Device and Revision ID Table ..........................................................................57

2-1 I/O Flexibility Signal Mapping.................................................................................62

2-2 USB Interface Signals ...........................................................................................63

2-3 PCI Express* Signals ............................................................................................66

2-4 Serial ATA Interface Signals...................................................................................67

2-5 Clock Interface Signals .........................................................................................69

2-6 Real Time Clock Interface......................................................................................70

2-7 Interrupt Signals..................................................................................................71

2-8 Processor Interface Signals....................................................................................72

2-9 Direct Media Interface Signals................................................................................72

2-10 Intel® Flexible Display Interface (Intel® FDI) Signals ................................................73

2-11 Analog Display Interface Signals ............................................................................73

2-12 Digital Display Signals ..........................................................................................73

2-13 Embedded DisplayPort* (eDP*) backlight control signals ...........................................74

2-14 Intel

High Definition Audio (Intel® HD Audio) Link Signals .......................................74

2-15 Low Pin Count (LPC) Interface Signals.....................................................................75

2-16 General Purpose I/O Signals ..................................................................................76

34 Datasheet

C220 Series Chipset Family SKUs....................................55



2-17 Functional Strap Definitions................................................................................... 82

2-18 SMBus Interface Signals ....................................................................................... 84

2-19 System Management Interface Signals ................................................................... 85

2-20 Controller Link Signals.......................................................................................... 85

2-21 Serial Peripheral Interface (SPI) Signals.................................................................. 85

2-22 MGPIO Conversion Table....................................................................................... 86

2-23 Client Manageability Signals .................................................................................. 87

2-24 Server Manageability Signals................................................................................. 87

2-25 Power Management Interface Signals ..................................................................... 87

2-26 Power and Ground Signals .................................................................................... 90

2-27 Thermal Signals................................................................................................... 91

2-28 Miscellaneous Signals........................................................................................... 92

2-29 Testability Signals................................................................................................ 93

2-30 Test Pins ............................................................................................................ 93

3-1 Integrated Pull-Up and Pull-Down Resistors............................................................. 95

3-2 Output Signals – Power Plane and States in Desktop, Mobile, and Server Configurations 98

3-3 Input Signals – Power Plane and States in Desktop and Mobile Configurations............ 103

4-1 PCH Clock Inputs............................................................................................... 107

4-2 Clock Outputs ................................................................................................... 108

4-3 PCH PLLs .......................................................................................................... 109

4-4 Modulator Blocks ............................................................................................... 109

5-1 PCI Express* Ports 1 thru 4 - Supported Configurations .......................................... 114

5-2 PCI Express* Ports 5 thru 8 - Supported Configurations .......................................... 114

5-3 MSI versus PCI IRQ Actions................................................................................. 114

5-4 LAN Mode Support ............................................................................................. 121

5-5 LPC Cycle Types Supported................................................................................. 127

5-6 Start Field Bit Definitions .................................................................................... 127

5-7 Cycle Type Bit Definitions ................................................................................... 127

5-8 Transfer Size Bit Definition.................................................................................. 128

5-9 SYNC Bit Definition ............................................................................................ 128

5-10 DMA Transfer Size ............................................................................................. 132

5-11 Address Shifting in 16-Bit I/O DMA Transfers......................................................... 132

5-12 Counter Operating Modes ................................................................................... 138

5-13 Interrupt Controller Connections.......................................................................... 139

5-14 Interrupt Status Registers................................................................................... 140

5-15 Content of Interrupt Vector Byte.......................................................................... 141

5-16 APIC Interrupt Mapping1 .................................................................................... 146

5-17 Stop Frame Explanation...................................................................................... 149

5-18 Data Frame Format............................................................................................ 149

5-19 Configuration Bits Reset by RTCRST# Assertion ..................................................... 152

5-20 INIT# Going Active ............................................................................................ 153

5-21 NMI Sources ..................................................................................................... 154

5-22 General Power States for Systems Using the PCH ................................................... 155

5-23 State Transition Rules for the PCH........................................................................ 156

5-24 System Power Plane........................................................................................... 157

5-25 Causes of SMI and SCI ....................................................................................... 158

5-26 Sleep Types ...................................................................................................... 162

5-27 Causes of Wake Events....................................................................................... 163

5-28 GPI Wake Events ............................................................................................... 164

5-29 Transitions Due to Power Failure.......................................................................... 165

5-30 Supported Deep Sx Policy Configurations .............................................................. 165

5-31 Deep Sx Wake Events ........................................................................................ 166

5-32 Transitions Due to Power Button .......................................................................... 166

5-33 Transitions Due to RI# Signal.............................................................................. 168

5-34 Write Only Registers with Read Paths in ALT Access Mode ....................................... 170

5-35 PIC Reserved Bits Return Values.......................................................................... 171

5-36 Register Write Accesses in ALT Access Mode.......................................................... 172

5-37 SUSPWRDNACK/SUSWARN#/GPIO30 Pin Behavior ................................................. 175

5-38 SUSPWRDNACK during Reset .............................................................................. 175

5-39 Causes of Host and Global Resets ........................................................................ 177

5-40 Event Transitions that Cause Messages................................................................. 181

5-41 SATA Feature Support ........................................................................................ 186

5-42 SATA Features................................................................................................... 187

5-43 Message Format ................................................................................................ 194

5-44 Multi-activity LED Message Type .......................................................................... 195

5-45 Legacy Replacement Routing............................................................................... 198

5-46 EHC Resets ....................................................................................................... 201

Datasheet 35

5-47 Debug Port Behavior........................................................................................... 205

5-48 I2C* Block Read.................................................................................................215

5-49 Enable for SMBALERT# .......................................................................................218

5-50 Enables for SMBus Slave Write and SMBus Host Events...........................................218

5-51 Enables for the Host Notify Command...................................................................218

5-52 Slave Write Registers.......................................................................................... 220

5-53 Command Types ................................................................................................220

5-54 Slave Read Cycle Format.....................................................................................221

5-55 Data Values for Slave Read Registers....................................................................221

5-56 Host Notify Format .............................................................................................223

5-57 PCH Thermal Throttle States (T-states) .................................................................226

5-58 PCH Thermal Throttling Configuration Registers......................................................226

5-59 Region Size versus Erase Granularity of Flash Components ......................................239

5-60 Region Access Control Table ................................................................................241

5-61 Hardware Sequencing Commands and Opcode Requirements ................................... 244

5-62 Flash Protection Mechanism Summary ..................................................................245

5-63 Recommended Pinout for 8-Pin Serial Flash Device ................................................. 246

5-64 Recommended Pinout for 16-Pin Serial Flash Device ...............................................247

6-1 Desktop/Server PCH Ballout By Signal Name.......................................................... 258

6-2 Mobile PCH Ballout by Signal Name....................................................................... 266

8-1 Storage Conditions and Thermal Junction Operating Temperature Limits....................276

8-2 Mobile Thermal Design Power ..............................................................................276

8-3 PCH Absolute Maximum Ratings ...........................................................................277

8-4 PCH Power Supply Range ....................................................................................277

8-5 Measured Silicon I

8-6 Single-Ended Signal DC Characteristics as Inputs or Outputs.................................... 279

(Desktop and Mobile)...........................................................278

8-7 Differential Signal DC Characteristics ....................................................................284

8-8 Other DC Characteristics .....................................................................................286

8-9 Signal Groups.................................................................................................... 287

8-10 CRT DAC Signal Group DC Characteristics: Functional Operating Range

(VccADAC = 3.3 V ±5%).....................................................................................287

8-11 Display Port Auxiliary Signal Group DC Characteristics.............................................288

8-12 PCI Express* Interface Timings............................................................................288

8-13 HDMI* Interface Timings (DDP[D:B][3:0]) ............................................................289

8-14 Intel® SDVO Interface Timings ............................................................................ 289

8-15 DisplayPort* Interface Timings (DDP[D:B][3:0]) .................................................... 290

8-16 DisplayPort* Aux Interface ..................................................................................290

8-17 DDC Characteristics - DDC Signals: VGA_DDC_CLK, VGA_DDC_DATA, DDP[D:B]

_CTRLCLK, DDP[D:B]_CTRLDATA .........................................................................290

8-18 CRT DAC AC Characteristics.................................................................................291

8-19 Clock Timings ....................................................................................................291

8-20 Universal Serial Bus Timing ................................................................................. 294

8-21 SATA Interface Timings.......................................................................................295

8-22 SMBus and SMLink Timing...................................................................................296

8-23 Intel

High Definition Audio (Intel® HD Audio) Timing ............................................ 297

8-24 LPC Timing........................................................................................................ 297

8-25 Miscellaneous Timings.........................................................................................297

8-26 SPI Timings (20 MHz) ......................................................................................... 297

8-27 SPI Timings (33 MHz) ......................................................................................... 298

8-28 SPI Timings (50 MHz) ......................................................................................... 298

8-29 SST Timings (Server/Workstation Only) ................................................................298

8-30 Controller Link Receive Timings............................................................................299

8-31 USB 3.0 Interface Transmit and Receiver Timings...................................................299

8-32 Power Sequencing and Reset Signal Timings .......................................................... 299

8-33 Suspend Well Voltage Ramp Up/Down Requirements ..............................................319

8-34 Core Well Voltage Ramp Up/Down Requirements....................................................319

9-1 PCI Devices and Functions...................................................................................321

9-2 Fixed I/O Ranges Decoded by PCH........................................................................ 322

9-3 Variable I/O Decode Ranges ................................................................................324

9-4 Memory Decode Ranges from Processor Perspective ...............................................325

9-5 SPI Mode Address Swapping................................................................................327

10-1 Chipset Configuration Register Memory Map (Memory Space)................................... 329

11-1 Gigabit LAN Configuration Registers Address Map

(Gigabit LAN—D25:F0)........................................................................................ 363

11-2 Gigabit LAN Capabilities and Status Registers Address Map

(Gigabit LAN—MBARA)........................................................................................375

12-1 LPC Interface PCI Register Address Map (LPC I/F—D31:F0)......................................379

36 Datasheet



12-2 DMA Registers................................................................................................... 400

12-3 PIC Registers .................................................................................................... 410

12-4 APIC Direct Registers ......................................................................................... 417

12-5 APIC Indirect Registers....................................................................................... 417

12-6 RTC I/O Registers .............................................................................................. 421

12-7 RTC (Standard) RAM Bank .................................................................................. 422

12-8 Processor Interface PCI Register Address Map ....................................................... 425

12-9 Power Management PCI Register Address Map (PM—D31:F0)................................... 428

12-10 APM Register Map .............................................................................................. 437

12-11 ACPI and Legacy I/O Register Map ....................................................................... 438

12-12 TCO I/O Register Address Map............................................................................. 453

12-13 Registers to Control GPIO Address Map................................................................. 459

13-1 SATA Controller PCI Register Address Map (SATA–D31:F2)...................................... 468

13-2 Bus Master IDE I/O Register Address Map ............................................................. 492

13-3 AHCI Register Address Map................................................................................. 499

13-4 Generic Host Controller Register Address Map........................................................ 500

13-5 Port [5:0] DMA Register Address Map................................................................... 507

14-1 SATA Controller PCI Register Address Map (SATA–D31:F5)...................................... 521

14-1 Bus Master IDE I/O Register Address Map ............................................................. 534

15-1 USB EHCI PCI Register Address Map (USB EHCI—D29:F0, D26:F0) .......................... 541

15-1 Enhanced Host Controller Capability Registers ....................................................... 561

15-2 Enhanced Host Controller Operational Register Address Map.................................... 564

15-3 Debug Port Register Address Map ........................................................................ 575

16-1 USB xHCI PCI Register Address Map (USB xHCI—D20:F0)....................................... 579

16-1 Enhanced Host Controller Capability Registers ....................................................... 597

16-2 Enhanced Host Controller Operational Register Address Map.................................... 600

16-3 Enhanced Host Controller Operational Register Address Map.................................... 616

17-1 Intel® High Definition Audio (Intel® HD Audio) PCI Register Address Map 

(Intel® High Definition Audio D27:F0)................................................................... 622

17-1 Intel® High Definition Audio Memory Mapped Configuration Registers 

Address Map (Intel® High Definition Audio D27:F0)................................................ 640

18-1 SMBus Controller PCI Register Address Map (SMBus—D31:F3) ................................. 662

18-1 SMBus I/O and Memory Mapped I/O Register Address Map...................................... 668

19-1 PCI Express* Configuration Registers Address Map

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ..................................................... 678

20-1 Memory-Mapped Register Address Map................................................................. 716

21-1 Serial Peripheral Interface (SPI) Register Address Map 

(SPI Memory Mapped Configuration Registers)....................................................... 723

21-1 Gigabit LAN SPI Flash Program Register Address Map 

(GbE LAN Memory Mapped Configuration Registers) ............................................... 742

22-1 Thermal Sensor Register Address Map .................................................................. 752

22-1 Thermal Memory Mapped Configuration Register Address Map ................................. 759

23-1 Intel® MEI 1 Configuration Registers Address Map

(Intel® MEI 1—D22:F0)...................................................................................... 765

23-1 Intel

MEI 1 MMIO Register Address Map ............................................................. 775

23-2 Intel® MEI 2 Configuration Registers Address Map

(Intel® MEI 2—D22:F1)...................................................................................... 777

23-3 Intel® MEI 2 MMIO Register Address Map ............................................................. 786

23-4 IDE Redirect Function IDER Register Address Map .................................................. 789

23-5 IDER BAR0 Register Address Map......................................................................... 796

23-6 IDER BAR1 Register Address Map......................................................................... 805

23-7 IDER BAR4 Register Address Map......................................................................... 806

23-8 Serial Port for Remote Keyboard and Text (KT) Redirection Register 

Address Map ..................................................................................................... 811

23-9 KT IO/Memory Mapped Device Register Address Map.............................................. 817

Datasheet 37

Revision History

Revision

Number

001 • Initial Release. June 2013

• Chapter 1, “Introduction” — Table 1-2, “Desktop Intel® 8 Series Chipset Family SKUs”

— Table 1-4, “Mobile Intel® 8 Series Chipset Family SKUs” — Table 1-6, “Server / Workstation Intel® C220 Series Chipset Family SKUs”

• Chapter 4, “PCH and System Clocks” — Section 4.5.2.1, “OC_WDT_CTL —Overclocking Watchdog Timer Control Register”

• Chapter 5, “Functional Description” — Section 5.3, “PCI Express* Root Ports (D28:F0~F7)”

— Section 5.20.1, “Overview”

• Chapter 8, “Electrical Characteristics” — Section 8.4, “General DC Characteristics”, Tabl e 8 - 5, Ta b le 8 -6

— Table 8-17, “DDC Characteristics - DDC Signals: VGA_DDC_CLK, VGA_DDC_DATA,

DDP[D:B] _CTRLCLK, DDP[D:B]_CTRLDATA”

002

003

— Table 8-19, “Clock Timings” — Figure 8-35, “PCH Suspend Well Ramp Up/Down Requirement” — Table 8-33, “Suspend Well Voltage Ramp Up/Down Requirements”

• Chapter 10, “Chipset Configuration Registers” — Section 10.1.41, “PM_CFG—Power Management Configuration Register”

• Chapter 12, “LPC Interface Bridge Registers (D31:F0)” — Section 12.6.1, “I/O Register Address Map”

— Section 12.8.3.5, “GPE0_STS—General Purpose Event 0 Status Register” — Section 12.10.3, “GP_LVL—GPIO Level for Input or Output Register”

• Chapter 19, “PCI Express* Configuration Registers” — Section 19.1.29, “LCTL—Link Control Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/

F6/F7)”

• Chapter 21, “Serial Peripheral Interface (SPI)” — Section 21.1.29, “PTINX—Flash Parameter Table Index Register”

— Section 21.1.30, “PTDATA—Flash Parameter Table Data Register”

• Chapter 1, “Introduction” — Updated sub-section “Intel® High Definition Audio (Intel® HD Audio) Controller” —Updated Section 1.3, “Intel® 8 Series/C220 Series Chipset Family PCH SKU Definition”

• Chapter 2, “Signal Description” —Corrected Table 2-16, “General Purpose I/O Signals”

• Chapter 5, “Functional Description” —Updated Section 5.3.5, “Hot-Plug”

— Removed Section 5.17.6, “Function Level Reset Support (FLR)”

• Chapter 8, “Electrical Characteristics” — Updated notes for Table 8-4.

• Chapter 9, “Register and Memory Mapping” —Updated Table 9-5, “SPI Mode Address Swapping”

• Chapter 10, “Chipset Configuration Registers” — Corrected SECRR50 bits 27:24 settings for SATA Gen3 Rx Equalization 1 - mSATA 4"-6"

and 6"-8"

— Corrected SECRR54 bits 3:0 settings for SATA Gen2 Rx Equalization 1 - M.2 (NGFF) <2",

2"-4" and 4"-6"

— Changed the Topology name from "iSATA (DT Direct Connect)" to "Internal SATA (Cable

Connect)" for SECRR50, and SECRR54 SATA Rx Equalization 1 tables.

• Chapter 19, “PCI Express* Configuration Registers” —Added Section 19.1.54, “PECR4—PCI Express* Configuration Register 4 (PCI Express*—

D28:F0/F1/F2/F3/F4/F5)”

• Chapter 23, “Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])” —Corrected Table 23-1, “Intel® MEI 1 Configuration Registers Address Map (Intel® MEI

1—D22:F0)”

• Minor updates throughout for clarity.

Description

Revision

September

May 2014

Date

2013

38 Datasheet



Platform Controller Hub Features

 Direct Media Interface

— Up to 20 Gb/s each direction, full duplex. — Transparent to software

 NEW: Flexible IO

— A new architecture that allows some high

speed IO signals to be configured as SATA or USB 3.0 or PCIe

 PCI Express*

— Up to eight PCI Express root ports — Supports PCI Express Rev 2.0 running at up

to 5.0 GT/s

— Ports 1-4 and 5-8 can independently be

configured to support multiple port configurations

— Module based Hot-Plug supported (that is,

ExpressCard*)

— NEW: Latency Tolerance Reporting

 Integrated Serial ATA Host Controller

— Up to six SATA ports — Data transfer rates supported: 6.0 Gb/s,

3.0 Gb/s, and 1.5 Gb/s on all ports

— Integrated AHCI controller

 External SATA support on all ports

— 3.0 Gb/s and 1.5 Gb/s support — Port Disable Capability

 Intel

Rapid Storage Technology (Intel® RST)

— Configures the PCH SATA controller as a

RAID controller supporting RAID 0/1/5/10

 Intel  Intel

Smart Response Technology

High Definition Audio Interface

— PCI Express endpoint — Independent Bus Master logic for eight

general purpose streams: four input and

four output — Support four external Codecs — Supports variable length stream slots — Supports multichannel, 32-bit sample

depth, 192 kHz sample rate output — Provides mic array support — Allows for non-48 kHz sampling output — Support for ACPI Device States —Low Voltage

 Eight TACH signals and Four PWM signals

(Server and Workstation Only)

 Platform Environmental Control Interface

(PECI) and Simple Serial Transport (SST) 1.0 Bus (Server and Workstation Only)

 USB

— xHCI Host Controller, supports up to 6

SuperSpeed USB 3.0 connections and 14 USB 2.0 connections

— More flexibility in pairing USB 3.0 and USB

2.0 signals to the same connector

— Two EHCI Host Controllers, supporting up

to fourteen external USB 2.0 ports

— Support for dynamic power gating and

Intel

Power Management Framework

(PMF) — Per-Port-Disable Capability — Includes up to two USB 2.0 High-speed

Debug Ports — Supports wake-up from sleeping states S1-

 Integrated Gigabit LAN Controller

— Connection utilizes PCI Express pins — Integrated ASF Management Controller — Network security with System Defense — Supports IEEE 802.3 — 10/100/1000 Mbps Ethernet Support — Jumbo Frame Support

 Intel

Active Management Technology with

System Defense

— Network Outbreak Containment Heuristics

 Intel  Intel

 Intel  Power Management Logic

IO Virtualization (Intel® VT-d) Support

Trusted Execution Technology (Intel®

TXT) Support

Anti-Theft Technology (Intel® AT)

— Supports ACPI 4.0a — ACPI-defined power states (processor

driven C states) — ACPI Power Management Timer —SMI# generation — All registers readable/restorable for proper

resume from 0 V core well suspend states — Support for APM-based legacy power

management for non-ACPI

implementations

 Integrated Clock Controller

— Full featured platform clocking without

need for a discrete clock chip — 8 PCIe* 2.0 specification compliant clocks,

4 PCIe 3.0 specification compliant clocks,

five 33 MHz PCI clocks, four Flex Clocks

that can be configured for various

frequencies, and two 135 MHz clocks for

DisplayPort*.

Datasheet 39

 External Glue Integration

— Integrated Pull-down and Series resistors

on USB

 Enhanced DMA Controller

— Two cascaded 8237 DMA controllers —Supports LPC DMA

 SMBus

— Interface speeds of up to 100 kbps — Supports SMBus 2.0 Specification — Host interface allows processor to

communicate using SMBus

— Slave interface allows an internal or

external microcontroller to access system resources

— Supports most two-wire components that

are also I

 SMLink

C compatible

— Provides independent manageability bus

through SMLink0 and SMLink1

— SMLink0 dedicated to LAN PHY and NFC,

operating up to 1 MHz

— SMLink1 dedicated to EC or BMC, operating

up to 100 kHz

 High Precision Event Timers

— Advanced operating system interrupt

scheduling

 Timers Based on 8254

— System timer, Refresh request, Speaker

tone output

 Real-Time Clock

— 256 byte battery-backed CMOS RAM — Integrated oscillator components — Lower Power DC/DC Converter

implementation

 System TCO Reduction Circuits

— Timers to generate SMI# and Reset upon

detection of system hang — Timers to detect improper processor reset — Supports ability to disable external devices

 JTAG

— Boundary Scan for testing during board

manufacturing

 Serial Peripheral Interface (SPI)

— Supports up to two SPI devices — Supports 20 MHz, 33 MHz, and 50 MHz SPI

devices

— NEW: Supports Quad IO Fast Read, Quad

Output Fast Read, Dual IO Fast Read

— NEW: Support for TPM over SPI with the

addition of SPI_CS2# chip select pin

— NEW: Supports Serial Flash Discoverable

Parameter (SFDP)

— Support up to two different erase

granularities

 Firmware Hub I/F supports BIOS Memory size

up to 8 MB

 Low Pin Count (LPC) I/F

— Supports two Master/DMA devices. — Support for Security Device (Trusted

Platform Module) connected to LPC

 Interrupt Controller

— Supports up to eight legacy interrupt pins — Supports PCI 2.3 Message Signaled

Interrupts — Two cascaded 8259 with 15 interrupts — Integrated IO APIC capability with 24

interrupts — Supports Processor System Bus interrupt

delivery

 1.05 V operation with tolerance up to 3.3 V IO  1.05 V Core Voltage  Integrated Voltage Regulators for select power

rails

 GPIO

— Open-Drain, Inversion —GPIO lock down

 Intel  Display

Flexible Display Interface

— Analog Display (VGA) Interface — Side band signals AUX CH, DDC and HPD — Backlight Control and Panel Power

sequencing signals

 Package

— 23 mm x 22 mm FCBGA (Desktop Only) — 20 mm x 20 mm FCBGA (Mobile Only)

Note: Not all features are available on all PCH SKUs.

§ §

40 Datasheet



Introduction

1 Introduction

1.1 About This Manual

This document is intended for Original Equipment Manufacturers and BIOS vendors creating products based on the Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) (See Section 1.3 for SKU definitions and supported features).

Note: Throughout this document, Platform Controller Hub (PCH) is used as a general term

and refers to all Intel® 8 Series/C220 Series Chipset Family PCH SKUs, unless specifically noted otherwise.

Note: Throughout this document, the terms “Desktop” and “Desktop Only” refer to

information that is applicable only to Desktop PCH, unless specifically noted otherwise.

Note: Throughout this document, the terms “Server/Workstation” and “Server/Workstation

Only” refers to information that is applicable only to Server/Workstation PCH, unless specifically noted otherwise.

Note: Throughout this document, the terms “Mobile” and “Mobile Only” refers to information

that is applicable only to the Mobile PCH, unless specifically noted otherwise.

This manual assumes a working knowledge of the vocabulary and principles of PCI Express*, USB, AHCI, SATA, Intel

High Definition Audio (Intel® HD Audio), SMBus, ACPI and Low Pin Count (LPC). Although some details of these features are described within this manual, refer to the individual industry specifications listed in Table 1-1 for the complete details.

All PCI buses, devices, and functions in this manual are abbreviated using the following nomenclature; Bus:Device:Function. This manual abbreviates buses as Bn, devices as Dn and functions as Fn. For example Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be considered to be Bus 0.

Table 1-1. Industry Specifications (Sheet 1 of 2)

Specification Location

PCI Express* Base Specification, Revision 2.0 http://www.pcisig.com/specifications

Low Pin Count Interface Specification, Revision 1.1 (LPC) http://developer.intel.com/design/chipsets/industry/

System Management Bus Specification, Version 2.0 (SMBus) http://www.smbus.org/specs/

PCI Local Bus Specification, Revision 2.3 (PCI) http://www.pcisig.com/specifications

PCI Power Management Specification, Revision 1.2 http://www.pcisig.com/specifications

Universal Serial Bus Specification (USB), Revision 2.0 http://www.usb.org/developers/docs

Universal Serial Bus Specification (USB), Revision 3.0 http://www.usb.org/developers/docs

Advanced Configuration and Power Interface, Version 4.0a (ACPI) http://www.acpi.info/spec.htm

Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 (EHCI)

eXtensible Host Controller Interface for Universal Serial Bus (xHCI), Revision 1.0

lpc.htm

http://developer.intel.com/technology/usb/ehcispec.htm

http://www.intel.com/technology/usb/xhcispec.htm

Datasheet 41

Table 1-1. Industry Specifications (Sheet 2 of 2)

Specification Location

Serial ATA Specification, Revision 3.0 http://www.serialata.org/

Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0 http://www.serialata.org

Serial ATA II Cables and Connectors Volume 2 Gold http://www.serialata.org

Alert Standard Format Specification, Version 1.03 http://www.dmtf.org/standards/asf

IEEE 802.3 Fast Ethernet http://standards.ieee.org/getieee802/

AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) http://T13.org (T13 1410D)

IA-PC HPET (High Precision Event Timers) Specification, Revision 1,0a

Trusted Platform Module (TPM) Specification 1.3 Note: TPM over SPI supports 8 bytes transactions max.

Intel

Virtualization Technology http://www.intel.com/technology/virtualization/

SFF-8485 Specification for Serial GPIO (SGPIO) Bus, Revision 0.7 http://www.intel.com/technology/virtualization/

Advanced Host Controller Interface specification for Serial ATA, Revision 1.3

High Definition Audio Specification, Revision 1.0a http://www.intel.com/standards/hdaudio/

Intel

http://www.intel.com/hardwaredesign/hpetspec_1.pdf

http://www.trustedcomputinggroup.org/specs/TPM

index.htm

http://www.intel.com/technology/serialata/ahci.htm

Introduction

1.1.1 Chapter Descriptions

Chapter 1, “Introduction” 

Chapter 1 introduces the PCH, provides information on the organization of the manual

and gives a general overview of the PCH.

Chapter 2, “Signal Description”

Chapter 2 provides a block diagram of the PCH and a detailed description of each

signal. Signals are arranged according to interface and details are provided as to the drive characteristics (Input/Output, Open Drain, and so on) of all signals.

Chapter 3, “PCH Pin States”

Chapter 3 provides a complete list of signals, their associated power well, their logic

level in each suspend state, and their logic level before and after reset.

Chapter 4, “PCH and System Clocks”

Chapter 4 provides a list of each clock domain associated with the PCH.

Chapter 5, “Functional Description”

Chapter 5 provides a detailed description of the functions in the PCH.

Chapter 6, “Ballout Definition”

Chapter 6 provides the ball assignment table and the ball-map for the Desktop and

Mobile packages.

Chapter 7, “Package Information”

Chapter 7 provides drawings of the physical dimensions and characteristics of the

Desktop and Mobile packages.

Chapter 8, “Electrical Characteristics”

Chapter 8 provides all AC and DC characteristics including detailed timing diagrams.

Datasheet



Introduction

Chapter 9, “Register and Memory Mapping”

Chapter 9 provides an overview of the registers, fixed I/O ranges, variable I/O ranges

and memory ranges decoded by the PCH.

Chapter 10, “Chipset Configuration Registers”

Chapter 10 provides a detailed description of registers and base functionality that is

related to chipset configuration. It contains the root complex register block, which describes the behavior of the upstream internal link.

Chapter 11, “Gigabit LAN Configuration Registers”

Chapter 11 provides a detailed description of registers that reside in the PCH’s

integrated LAN controller. The integrated LAN Controller resides at Device 25, Function 0 (D25:F0).

Chapter 12, “LPC Interface Bridge Registers (D31:F0)”

Chapter 12 provides a detailed description of registers that reside in the LPC bridge.

This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units within the PCH including DMA, Timers, Interrupts, Processor Interface, GPIO, Power Management, System Management and RTC.

Chapter 13, “SATA Controller Registers (D31:F2)”

Chapter 13 provides a detailed description of registers that reside in the SATA

controller #1. This controller resides at Device 31, Function 2 (D31:F2).

Chapter 14, “PCI Configuration Registers (SATA–D31:F5)”

Chapter 14.1 provides a detailed description of registers that reside in the SATA

controller #2. This controller resides at Device 31, Function 5 (D31:F5).

Chapter 15, “EHCI Controller Registers (D29:F0, D26:F0)”

Chapter 15 provides a detailed description of registers that reside in the two EHCI host

controllers. These controllers reside at Device 29, Function 0 (D29:F0) and Device 26, Function 0 (D26:F0).

Chapter 16, “xHCI Controller Registers (D20:F0)”

Chapter 16 provides a detailed description of registers that reside in the xHCI. This

controller resides at Device 20, Function 0 (D20:F0).

Chapter 17, “Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers”

Chapter 17 provides a detailed description of registers that reside in the Intel High

Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0).

Chapter 18, “SMBus Controller Registers (D31:F3)”

Chapter 18 provides a detailed description of registers that reside in the SMBus

controller. This controller resides at Device 31, Function 3 (D31:F3).

Chapter 19, “PCI Express* Configuration Registers”

Chapter 19 provides a detailed description of registers that reside in the PCI Express

controller. This controller resides at Device 28, Functions 0 to 7 (D28:F0-F7).

Chapter 20, “High Precision Event Timer Registers”

Chapter 20 provides a detailed description of registers that reside in the multi-media

timer memory mapped register space.

Chapter 21, “Serial Peripheral Interface (SPI)”

Chapter 21 provides a detailed description of registers that reside in the SPI memory

mapped register space.

Datasheet 43

Chapter 22, “Thermal Sensor Registers (D31:F6)”

Chapter 22 provides a detailed description of registers that reside in the thermal

sensors PCI configuration space. The registers reside at Device 31, Function 6 (D31:F6).

Chapter 23, “Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])”

Chapter 23 provides a detailed description of registers that reside in the Intel ME

controller. The registers reside at Device 22, Function 0 (D22:F0).

1.2 Overview

The PCH provides extensive I/O support. Functions and capabilities include:

• PCI Express* Base Specification, Revision 2.0 support for up to eight ports with transfers up to 5 GT/s

• ACPI Power Management Logic Support, Revision 4.0a

• Enhanced DMA controller, interrupt controller, and timer functions

• Integrated Serial ATA host controllers with independent DMA operation on up to six ports

• xHCI USB controller provides support for up to 14 USB ports, of which six can be configured as SuperSpeed USB 3.0 ports.

• Two legacy EHCI USB controllers each provides a USB debug port.

• Flexible I/O, A new architecture to allow some high speed I/O signals to be configured as PCIe, SATA or USB 3.0.

• Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense

• System Management Bus (SMBus) Specification, Version 2.0 with additional support for I

•Supports Intel

•Supports Intel® Active Management Technology (Intel® AMT)

•Supports Intel

• Integrated Clock Controller

•Intel

•Analog VGA Display Interface

• Low Pin Count (LPC) interface

• Firmware Hub (FWH) interface support

• Serial Peripheral Interface (SPI) support

•Intel

•JTAG Boundary Scan support

Flexible Display Interface (Intel® FDI)

Anti-Theft Technology (Intel® AT)

C devices

High Definition Audio (Intel® HD Audio)

Rapid Storage Technology (Intel® RST)

Virtualization Technology for Directed I/O (Intel® VT-d)

Trusted Execution Technology (Intel® TXT)

Introduction

Note: Not all functions and capabilities may be available on all SKUs. See Section 1.3 for

details on SKU feature availability.

Datasheet



Introduction

1.2.1 Capability Overview

The following sub-sections provide an overview of the PCH capabilities.

Direct Media Interface (DMI)

Direct Media Interface (DMI) is the chip-to-chip connection between the processor and PCH. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software-transparent, permitting current and legacy software to operate normally.

Intel

Intel FDI connects the display engine in the processor with the Analog display interface on the PCH. The display data for Analog VGA panels from the frame buffer is processed by the display engine and sent to the PCH through Intel FDI. Intel FDI has two lanes for display data transfer to the PCH from the processor. Each Intel FDI lane consists of two differential signal receive pairs supporting a data rate of 2.7 Gb/s.

PCH Display Interface

Flexible Display Interface (Intel® FDI)

The Analog VGA display interface is the only display interface supported on the PCH. This interface is used to drive legacy CRT panels and advanced LCD VGA panels. The analog VGA display interface has an integrated RAMDAC 180 MHz, driving a standard progressive scan analog monitor to a resolution of up to 1920x2000 pixels and 24-bit color at a 60 Hz refresh rate with reduced blanking.

Analog VGA display interface is in the PCH, although the main display engine is in the processor. Thus, the Intel FDI is used to send the display data to the PCH. Intel FDI is a bus that connects the processor and PCH display components. The PCH, upon receiving the display data, transcodes the data as per the display technology protocol and sends the data through the DAC to display panel.

The PCH integrates digital display side band signals, even though digital display interfaces are in the processor. There are three pairs of AUX CH, DDC Clock/Data, and Hot-Plug Detect Signals on the PCH that correspond to digital display interface/ports B, C, and D.

The PCH also integrates panel backlight control signals, which are used only when Embedded DisplayPort* (eDP) is configured on the platform.

PCI Express* Interface

The PCH provides up to 8 PCI Express Root Ports, supporting the PCI Express Base Specification, Revision 2.0. Each Root Port x1 lane supports up to 5 Gb/s bandwidth in

each direction (10 Gb/s concurrent). PCI Express Root Ports 1–4 or Ports 5–8 can independently be configured to support multiple port width configurations. See

Section 1.3 for details on feature availability.

Datasheet 45

Introduction

Serial ATA (SATA) Controller

The PCH has two integrated SATA host controllers that support independent DMA operation on up to six ports and support data transfer rates of up to 6.0 Gb/s on all ports. The SATA controller contains two modes of operation – a legacy mode using I/O space, and an AHCI mode using memory space. Software that uses legacy mode will not have AHCI capabilities.

The PCH supports the Serial ATA Specification, Revision 3.0. The PCH also supports several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.0 (AHCI support is required for some elements).

See Section 1.3 for details on feature availability.

Advanced Host Controller Interface (AHCI)

The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a standardized programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices – each device is treated as a master – and hardwareassisted native command queuing. AHCI also provides usability enhancements, such as Hot-Plug. AHCI requires appropriate software support (such as, an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware. See Section 1.3 for details on SKU feature availability.

Intel

Rapid Storage Technology (Intel® RST)

The PCH provides support for Intel Rapid Storage Technology (Intel RST), providing both AHCI (see above for details on AHCI) and integrated RAID functionality. The RAID capability provides high-performance RAID 0, 1, 5, and 10 functionality on up to 6 SATA ports of the PCH. Matrix RAID support is provided to allow multiple RAID levels to be combined on a single set of hard drives, such as RAID 0 and RAID 1 on two disks. Other RAID features include hot spare support, SMART alerting, and RAID 0 auto replace. Software components include an Option ROM for pre-boot configuration and boot functionality, a Microsoft* Windows* compatible driver, and a user interface for configuration and management of the RAID capability of PCH. See Section 1.3 for details on SKU feature availability.

Intel

Smart Response Technology

Intel Smart Response Technology is a disk caching solution that can provide improved computer system performance with improved power savings. It allows configuration of a computer system with the advantage of having HDDs for maximum storage capacity with system performance at or near SSD performance levels. See Section 1.3 for details on SKU feature availability.

Low Pin Count (LPC) Interface

The PCH implements an LPC Interface as described in the LPC 1.1 Specification. The Low Pin Count (LPC) bridge function of the PCH is mapped as PCI D31:F0 and supports a memory size up to 8 MB, two master/DMA devices, interrupt controllers, timers, power management, system management, Super I/O, and RTC.

Datasheet



Introduction

Serial Peripheral Interface (SPI)

In addition to the standard Dual Output Fast Read mode, the SPI interface in the PCH supports new Dual I/O Fast Read, Quad I/O Fast Read and Quad Output Fast Read. To enable the new Quad I/O operation modes, all data transfer signals in the interface are bidirectional and two new signals (SPI_IO2 and SPI_IO3) have been added to the basic four-wire interface: Clock, Master Out Slave In (MOSI), Master In Slave Out (MISO) and active-low chip selects (CS#). The PCH supports three chip selects: SPI_CS0# and SPI_CS1# are used to access two separate SPI Flash components in Descriptor Mode. SPI_CS2# is dedicated only to support Trusted Platform Module (TPM) on SPI (TPM can be configured through PCH soft straps to operate over LPC or SPI, but no more than 1 TPM is allowed in the system). SPI_CS2# may not be used for any purpose other than TPM.

The SPI Flash Controller supports running instructions at 20 MHz, 33 MHz, and 50 MHz, and can be used by the PCH for BIOS code, to provide chipset configuration settings, internal micro-processor code, integrated Gigabit Ethernet MAC/PHY configuration, and Intel Active Management Technology (Intel

AMT) settings. The SPI Flash Controller supports the Serial Flash Discoverable Parameter (SFDP) JEDEC standard that provides a consistent way of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. The SPI Flash Controller queries these parameter tables to discover the attributes to enable divergent features from multiple SPI part vendors, such as Quad I/O Fast Read capabilities or device storage capacity, among others.

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)

The DMA controller incorporates the logic of two 8237 DMA controllers, with seven independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-bybyte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels can be programmed to support fast Type-F transfers. Channel 4 is reserved as a generic bus master request.

The PCH supports LPC DMA, which is similar to ISA DMA, through the PCH DMA controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface.

The timer/counter block contains three counters that are equivalent in function to those found in one 8254 programmable interval timer. These three counters are combined to provide the system timer function, and speaker tone. The 14.318 MHz oscillator input provides the clock source for these three counters.

The PCH provides an ISA-compatible Programmable Interrupt Controller (PIC) that incorporates the functionality of two 8259 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. In addition, the PCH supports a serial interrupt scheme.

All of the registers in these modules can be read and restored. This is required to save and restore system state after power has been removed and restored to the platform.

Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA-compatible Programmable Interrupt controller (PIC) described in the previous section, the PCH incorporates the Advanced Programmable Interrupt Controller (APIC).

Datasheet 47

Introduction

Universal Serial Bus (USB) Controllers

The PCH contains one eXtensible Host Controller Interface (xHCI) controller and two Enhanced Host Controller Interface (EHCI) controllers. The xHCI controller is mapped as PCI D20:F0 and it supports up to 14 USB 2.0 ports of which 6 can be configured as SuperSpeed (USB 3.0) ports.

EHCI controller 1 (EHCI1) is located at D29:F0 and it supports up to 8 USB 2.0 ports. EHCI controller 2 (EHCI2) is located at D26:F0 and it supports up to 6 USB 2.0 ports. One of the USB 2.0 ports in either EHCI controller can be used for a Debug Port (not available through xHCI).

Note: USB 2.0 differential pairs are numbered starting with 0. USB 3.0 differential pairs are

numbered starting with 1.

Note: Regarding the optional USB Battery Charging Specification 1.x: Intel does not have a

topology for Intel

8 Series/C220 Series Chipset Family based platforms that can accommodate USB battery charging circuits robustly across the large install base of USB cables and High Speed (HS) devices. As such, Intel does not recommend that platforms exceed native supply currents defined in the USB specification for USB 2.0 ports.

See Section 1.3 for details on feature availability.

Flexible I/O

The PCH implements Flexible I/O, an architecture to allow some high speed signals to be configured as SATA, USB 3.0, or PCIe signals. Through soft straps, the functionality on these multiplexed signals are selected to meet the I/O needs on the platform. See

Section 5.22 for details on Flexible I/O.

Gigabit Ethernet Controller

The Gigabit Ethernet Controller provides a system interface using a PCI function. The controller provides a full memory-mapped or I/O mapped interface along with a 64-bit address master support for systems using more than 4 GB of physical memory and DMA (Direct Memory Addressing) mechanisms for high performance data transfers. Its bus master capabilities enable the component to process high-level commands and perform multiple operations. This lowers processor utilization by off-loading communication tasks from the processor. Two large configurable transmit and receive FIFOs (up to 20 KB each) help prevent data underruns and overruns while waiting for bus accesses. This enables the integrated LAN controller to transmit data with minimum interframe spacing (IFS).

The LAN controller can operate at multiple speeds (10/100/1000 MB/s) and in either full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism. See Section 5.4 for details.

Real Time Clock (RTC)

The PCH contains a Motorola MC146818B-compatible real-time clock with 256 bytes of battery-backed RAM. The real-time clock performs two key functions – keeping track of the time of day and storing system data, even when the system is powered down. The RTC operates on a 32.768-kHz crystal and a 3-V battery.

Datasheet



Introduction

The RTC also supports two lockable memory ranges. By setting bits in the configuration space, two 8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of passwords or other system security information.

The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than just 24 hours in advance.

General Purpose I/O (GPIO)

Various general purpose inputs and outputs are provided for custom system design. The number of inputs and outputs varies depending on PCH configuration.

Enhanced Power Management

The PCH’s power management functions fully support the Advanced Configuration and Power Interface (ACPI) Specification, Revision 4.0a, and include enhanced clock control

and various low-power (suspend) states (such as Suspend-to-RAM and Suspend-toDisk). A hardware-based thermal management circuit permits software-independent entrance to low-power states.

Intel

Active Management Technology (Intel® AMT)

AMT is a fundamental component of Intel® vPro™ technology. Intel AMT is a set of advanced manageability features developed as a direct result of IT customer feedBack gained through Intel market research. With the advent of powerful tools like the Intel System Defense Utility, the extensive feature set of Intel AMT easily integrates into any network environment. See Section 1.3 for details on SKU feature availability.

Manageability

In addition to Intel

AMT, the PCH integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller.

• TCO Timer. The PCH’s integrated programmable TCO timer is used to detect system locks. The first expiration of the timer generates an SMI# that the system can use to recover from a software lock. The second expiration of the timer causes a system reset to recover from a hardware lock.

• Processor Present Indicator. The PCH looks for the processor to fetch the first instruction after reset. If the processor does not fetch the first instruction, the PCH will reboot the system.

• ECC Error Reporting. When detecting an ECC error, the host controller has the ability to send one of several messages to the PCH. The host controller can instruct the PCH to generate either an SMI#, NMI, SERR#, or TCO interrupt.

• Function Disable. The PCH provides the ability to disable the following integrated functions: LAN, USB, LPC, Intel

HD Audio, SATA, PCI Express* or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts or power management events are generated from the disabled functions.

• Intruder Detect. The PCH provides an input signal (INTRUDER#) that can be used to inform the system in the event of the case being opened. The PCH can be programmed to generate an SMI# or TCO interrupt due to an active INTRUDER# signal.

Datasheet 49

System Management Bus (SMBus 2.0)

Introduction

The PCH contains an SMBus Host interface that allows the processor to communicate with SMBus slaves. This interface is compatible with most I

C devices. Special I2C

commands are implemented.

The PCH SMBus host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). Also, the PCH supports slave functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.

The PCH SMBus also implements hardware-based Packet Error Checking for data robustness and the Address Resolution Protocol (ARP) to dynamically provide addresses to all SMBus devices.

Intel

High Definition Audio (Intel® HD Audio) Controller

The Intel HD Audio controller is a PCI Express* device, configured as D27:F0. The PCH Intel HD Audio controller supports up to 4 codecs, such as audio and modem codecs. The link can operate at either 3.3 V or 1.5 V.

With the support of multi-channel audio stream, 32-bit sample depth, and sample rate up to 192 kHz, the Intel HD Audio controller provides audio quality that can deliver Consumer Electronics (such as home audio components, portable audio devices, Bluetooth* speakers, and so on) levels of audio experience. On the input side, the PCH adds support for an array of microphones.

Intel

Virtualization Technology for Directed I/O (Intel® VT-d)

The PCH provides hardware support for implementation of Intel Virtualization Technology with Directed I/O (Intel VT-d). Intel components that support the virtualization of platforms based on Intel Architecture processors. Intel

VT-d Technology enables multiple operating systems and applications

VT-d Technology consists of technology

to run in independent partitions. A partition behaves like a virtual machine (VM) and provides isolation and protection across partitions. Each partition is allocated its own subset of host physical memory.

Joint Test Action Group (JTAG) Boundary-Scan

The PCH implements the industry standard JTAG interface and enables Boundary-Scan. Boundary-Scan can be used to ensure device connectivity during the board manufacturing process. The JTAG interface allows system manufacturers to improve efficiency by using industry available tools to test the PCH on an assembled board. Since JTAG is a serial interface, it eliminates the need to create probe points for every pin in an XOR chain. This eases pin breakout and trace routing and simplifies the interface between the system and a bed-of-nails tester.

Note: The TRST# JTAG signal is an optional signal in the IEEE* 1149 JTAG Specification and is

not implemented in the PCH.

Integrated Clock Controller

The PCH contains an Integrated Clock Controller (ICC) that generates various platform clocks from a 25 MHz crystal source. The ICC contains PLLs, Modulators, and Dividers for generating various clocks suited to the platform needs. The ICC supplies up to eight

Datasheet



Introduction

100 MHz PCI Express 2.0 Specification compliant clocks, one 100 MHz PCI Express* 3.0 Specification compliant clock for BCLK/DMI, two 100 MHz PCI Express 3.0 Specification compliant clocks for PEG slots, one 100 MHz PCI Express 3.0 Specification compliant clock for ITP or a third PEG slot, two 135 MHz differential output clocks for DisplayPort on the processor, five 33 MHz PCI 2.3 Local Bus Specification compliant single-ended clocks for LPC/TPM devices and four Flex Clocks that can be configured to various frequencies that include 14.318 MHz, 33 MHz, and 24/48 MHz for use with SIO, TPM, EC, LPC, and any other legacy functions.

Serial Over LAN (SOL) Function

This function supports redirection of keyboard and text screens to a terminal window on a remote console. The keyboard and text redirection enables the control of the client machine through the network without the need to be physically near that machine. Text and keyboard redirection allows the remote machine to control and configure a client system. The SOL function emulates a standard PCI device and redirects the data from the serial port to the management console using the integrated LAN.

Intel

Intel addition to the features set provided by SOL, Intel KVM technology provides mouse and graphic redirection across the integrated LAN. Unlike SOL, Intel

KVM Technology

KVM technology provides enhanced capabilities to its predecessor – SOL. In

KVM technology does not appear as a host accessible PCI device, but is instead almost completely performed by Intel® AMT Firmware with minimal BIOS interaction. The Intel KVM technology feature is only available with internal graphics.

IDE-R Function

The IDE-R function is an IDE Redirection interface that provides client connection to management console ATA/ATAPI devices, such as hard disk drives and optical disk drives. A remote machine can setup a diagnostic software or operating system installation image and direct the client to boot an IDE-R session. The IDE-R interface is the same as the IDE interface; although, the device is not physically connected to the system and supports the ATA/ATAPI-6 specification. IDE-R does not conflict with any other type of boot and can, instead, be implemented as a boot device option. The

AMT solution will use IDE-R when remote boot is required. The device attached

Intel through IDE-R is only visible to software during a management boot session. During normal boot session, the IDE-R controller does not appear as a PCI present device.

Datasheet 51

Introduction

1.3 Intel® 8 Series/C220 Series Chipset Family PCH SKU Definition

Table 1-2. Desktop Intel® 8 Series Chipset Family SKUs

SKU Name

Feature Set

Intel

Q87 Express Chipset

Intel®

Q85

Express

Chipset

Flexible I/O YesNo NoYesYesNo

PCI Express* 2.0 Ports 8

88848

Total number of USB ports 14 14 12

• USB 3.0 Capable Ports (SuperSpeed and all USB 2.0

4(6)

4 4 4(6)

speeds)

• USB 2.0 Only Ports 10(8)

Total number of SATA ports 4(6)

• SATA Ports (6 Gb/s, 3 Gb/s, and 1.5 Gb/s) 6 4

10 8 10(8)

6 6 4(6)

•SATA Ports (3 Gb/s and 1.5 Gb/s only) 022002

VGA YesYesYesYesYesYes

Intel® Wireless Display (WiDi) YesYesYesYesYesYes

Intel® Rapid Storage Technolo g y

Intel® Anti-Theft Technology

AHCI YesYesYesYesYes No

RAID 0/1/5/10 Support YesNo NoYesYesNo

Intel® Smart Response Technology

YesNo NoYesYesNo

YesYesYesYesYesYes

Intel® Active Management Technology 9.0 YesNoNoNoNoNo

Intel® Small Business Advantage

Intel Rapid Start Technology

Intel® Identity Protection Technology (Intel® IPT)

Near Field Communication

Yes Yes Yes No Yes

Yes Yes Yes Yes Ye s No

Yes Yes Yes Ye s Yes Yes

ACPI S1 State Support No No No No No No

Processor Features Controlled by PCH SKU

Processor PEG Port Bifurcation 1x16 1x16 1x16 1x16,

Processor PEG Port Maximum Speed Allowed Gen 3

Processor Maximum Number of Independent Displays Supported

Processor Maximum Number of Memory Channels (Maximum DIMMS per Channel)

(8GT/s)

3 3 3 3 3 2

2 (2) 2 (2) 2 (2) 2 (2) 2 (2) 2 (1)

Gen 3

(8GT/s)

Processor and Memory Overclocking Disabled Disabled Disabled Enabled Disabled Disabled

Processor Graphics Enabled Enabled Enabled Enabled Enabled Enabled

Intel®

B85

Express

Chipset

Gen 3

(8GT/s)

Intel®

Z87

Express

Chipset

Intel®

H87

Express

Chipset

Intel®

H81

Express

Chipset

14 14 10

4(6)

10(8)

4(6)

662

1x16 1x16

2x8, 1x8,

2x4

Gen 3

(8GT/s)

Gen 3

(8GT/s)

Gen 2

(5GT/s)

Notes:

1. Contact your local Intel Field Sales Representative for currently available PCH SKUs.

2. Table above shows feature differences between the PCH SKUs. If a feature is not listed in the table it is considered a Base feature that is included in all SKUs.

3. PCI Legacy Mode may optionally be used allowing external PCI bus support through a PCIe-to-PCI bridge. See Section 5.2.2 for more details.

4. The number of PCI Express ports available depends on the Flexible I/O configuration. See Section 2.1 and

Tab l e 1 -3 .

Datasheet



Introduction

5. USB 2.0 ports 6 and 7 are disabled on 12 port SKUs.

6. USB 2.0 ports 6,7,12 and 13 are disabled on 10 port SKUs.

7. 6 USB 3.0 ports requires High Speed I/O ports 5 and 6 to be configured as USB 3.0. See Section 2.1 and

Tab l e 1 -3 .

8. Only USB 3.0 ports 1 and 2 are enabled.

9. When Flexible I/O ports are configured as USB 3.0, the total number of USB 2.0 only ports reduces in direct proportion.

10. 6 SATA ports requires High Speed I/O ports 13 and 14 to be configured as SATA. See Section 2.1 and

Tab l e 1 -3 .

11. SATA ports 2 and 3 are disabled on 4 port SKUs.

12. SATA 6 Gb/s support on ports 0,1,2 and 3. SATA ports 0,1,2 and 3 also support 3 Gb/s and 1.5 Gb/s.

13. SATA 6 Gb/s support on ports 0 and 1 only. SATA ports 0 and 1 also support 3 Gb/s and 1.5 Gb/s.

14. Intel

15. Intel

16. Intel

17. Intel

18. Intel

19. Intel

20. Near Field Communication is only supported in All-in-One system designs.

21. Refer to the processor datasheet for additional details on processor features.

Smart Response Technology requires an Intel® Core™ processor.

Anti-Theft Technology requires an Intel® Core™ processor.

Small Business Advantage requires an Intel® Core™ processor.

Small Business Advantage with the Intel® H87 Express Chipset requires 5Mb firmware.

Rapid Start Technology requires an Intel® Core™ processor.

Identity Protection Technology requires an Intel® Core™ processor.

Table 1-3. Intel® 8 Series/C220 Series Chipset Family PCH SKUs Flexible I/O Map

High Speed I/O Ports

SKU

Port 1Port 2Port 3Port 4Port 5Port 6Port 7Port 8Port 9Port 10Port 11Port 12Port 13Port 14Port 15Port 16Port 17Port

USB

Q87

Q85

B85

Z87

H87

H81

USB

3.0

Port 1

USB

3.0

Port 1

USB

3.0

Port 1

USB

3.0

Port 1

USB

3.0

Port 1

USB

3.0

Port 1

USB

3.0

Port 2

USB

3.0

Port 2

USB

3.0

Port 2

USB

3.0

Port 2

USB

3.0

Port 2

USB

3.0

Port 2

USB

3.0

Port 5

USB

3.0

Port 5

USB

3.0

Port 5

USB

3.0

Port 5

USB

3.0

Port 5

NA NA

USB

3.0

Port 6

USB

3.0

Port 6

USB

3.0

Port 6

USB

3.0

Port 6

USB

3.0

Port 6

3.0

Port 3

PCIe*

Port 1

PCIe*

Port 1

PCIe*

Port 1

USB

3.0

Port 3

PCIe*

Port 1

USB

3.0

Port 3

PCIe*

Port 1

PCIe*

Port 1

USB

3.0

Port 4

PCIe* Port 2

USB

3.0

Port 4

PCIe* Port 2

USB

3.0

Port 4

PCIe* Port 2

PCIe* Port 3

PCIe* Port 4

PCIe* Port 5

PCIe* Port 6

PCIe* Port 7

NA NA

PCIe* Port 8

SATA 6Gb/s Port 4

PCIe* Port 1

SATA 3Gb/s Port 4

SATA 6Gb/s Port 4

PCIe* Port 1

SATA 6Gb/s Port 4

PCIe* Port 1

SATA 3Gb/s Port 4

SATA 6Gb/s Port 5

PCIe* Port 2

SATA 3Gb/s Port 5

SATA 6Gb/s Port 5

PCIe* Port 2

SATA 6Gb/s Port 5

PCIe* Port 2

SATA 3Gb/s Port 5

SATA 6Gb/s Port 0

SATA 6Gb/s Port 1

SATA 6Gb/s Port 2

NA NA

SATA 6Gb/s Port 3

Notes:

1. Ports listed with NA are not available and are disabled.

Datasheet 53

Introduction

Table 1-4. Mobile Intel® 8 Series Chipset Family SKUs

SKU Name

Mobile

Feature Set

Intel

QM87 Express Chipset

Flexible I/O Yes Yes Yes

PCI Express* 2.0 Ports 8

Total number of USB ports 14 14 14

•USB 3.0 Capable Ports (SuperSpeed and all USB 2.0 speeds) 4(6)

•USB 2.0 Only Ports 10(8)

Total number of SATA ports 4(6)

•SATA Ports (6 Gb/s, 3 Gb/s, and 1.5 Gb/s) 2(4)

•SATA Ports (3 Gb/s and 1.5 Gb/s only) 2 2 2

VGA Yes Yes Yes

Intel® Wireless Display (WiDi) Yes Yes Yes

Intel® Rapid Storage Technology AHCI Yes Yes Yes

RAID 0/1/5/10 Support Yes Yes No

Yes Yes N o

Yes Yes Yes

Intel® Anti-Theft Technology

Intel® Smart Response Technology

Intel® Active Management Technology 9.0 Yes N o N o

Intel® Small Business Advantage

Intel Rapid Start Technology

Intel® Identity Protection Technology (Intel® IPT)

Yes Yes

Yes Yes Yes

Near Field Communication Yes Yes Yes

ACPI S1 State Support No No No

Processor Features Controlled by PCH SKU

Processor PEG Port Bifurcation 1x16 1x16 1x16

Processor PEG Port Maximum Speed Allowed Gen 3

(8GT/s)

Processor Maximum Number of Independent Displays Supported 3 3 2

Processor Maximum Number of Memory Channels (Maximum DIMMS per Channel) 2 (2) 2 (2) 2 (1)

Processor and Memory Overclocking

Disabled Disabled Disabled

Processor Graphics Enabled Enabled Enabled

Notes:

1. Contact your local Intel Field Sales Representative for currently available PCH SKUs.

2. Table above shows feature difference between the PCH SKUs. If a feature is not listed in the table, it is considered a Base feature that is included in all SKUs.

3. PCI Legacy Mode may optionally be used allowing external PCI bus support through a PCIe-to-PCI bridge. See Section 5.2.2 for more details.

4. Flexible I/O is only available on High Speed I/O ports 5 and 6 which are shared between USB 3.0 and PCI Express. High Speed I/O ports 13 and 14 are fixed as SATA Gen 2 ports. See Section 2.1 and Ta b l e 1 -5 .

5. The number of PCI Express ports available depends on the Flexible I/O configuration. See Section 2.1 and

Tab l e 1 -5 .

6. 6 USB 3.0 ports requires High Speed I/O ports 5 and 6 to be configured as USB 3.0. See Section 2.1 and

Tab l e 1 -5 .

7. USB 3.0 ports 5 and 6 are disabled on the Intel

8. When Flexible I/O ports are configured as USB 3.0, the total number of USB 2.0 only ports reduces in direct proportion.

9. 6 SATA ports requires High Speed I/O ports 13 and 14 to be configured as SATA. See Section 2.1 and

Tab l e 1 -5 .

10. SATA ports 1 and 3 are disabled on 4 port SKUs.

11. SATA 6 Gb/s support on ports 0,1,4 and 5. SATA ports 0,1,4 and 5 also support 3 Gb/s and 1.5 Gb/s. In order to support 4 SATA 6 Gb/s ports, High Speed I/O ports 13 and 14 must be configured as SATA. See

Section 2.1 and Tab l e 1 - 5.

12. SATA 6 Gb/s support on port 4 and port 5. SATA ports 4 and 5 also support 3 Gb/s and 1.5 Gb/s.

13. Intel

Smart Response Technology requires an Intel® Core™ processor.

HM86 Express Chipset.

Express

Mobile Intel®

HM87

Chipset

4(6) 2(4)

10(8)

4(6)

2(4)

Gen 3

(8GT/s)

Mobile Intel®

HM86

Express

Chipset

12(10)

Gen 2

(5GT/s)

Datasheet



Introduction

14. Intel

15. Intel

16. Intel

17. Intel

18. Intel

Anti-Theft Technology requires an Intel® Core™ processor.

Small Business Advantage requires an Intel® Core™ processor.

Small Business Advantage with the Intel® HM87 Express Chipset requires 5Mb firmware.

Rapid Start Technology requires an Intel® Core™ processor.

Identity Protection Technology requires an Intel® Core™ processor.

19. Refer to the processor datasheet for additional details on processor features.

Table 1-5. Intel® 8 Series/C220 Series Chipset Family PCH SKUs Flexible I/O Map

High Speed I/O Ports

SKU

Port 1Port 2Port 3Port 4Port 5Port 6Port 7Port 8Port 9Port 10Port 11Port 12Port 13Port 14Port 15Port 16Port 17Port

USB

QM87

HM87

HM86

USB

3.0

Port 1

USB

3.0

Port 1

USB

3.0

Port 1

USB

3.0

USB

3.0

USB

3.0

Port 4

PCIe* Port 2

USB

3.0

Port 4

PCIe* Port 2

USB

3.0

Port 4

PCIe* Port 2

PCIe* Port 3

PCIe* Port 4

USB

3.0

Port 2

USB

3.0

Port 2

USB

3.0

Port 2

USB

3.0

Port 5

USB

3.0

Port 5

NA NA

USB

3.0

Port 6

USB

3.0

Port 6

Port 3

PCIe* Port 1

Port 3

PCIe* Port 1

Port 3

PCIe* Port 1

Notes:

1. Ports listed with NA are not available and are disabled.

PCIe* Port 5

PCIe* Port 6

PCIe* Port 7

PCIe* Port 8

SATA 6Gb/s Port 4

PCIe* Port 1

SATA 6Gb/s Port 4

PCIe* Port 1

SATA 6Gb/s Port 4

SATA 6Gb/s Port 5

PCIe* Port 2

SATA 6Gb/s Port 5

PCIe* Port 2

SATA 6Gb/s Port 5

SATA 6Gb/s Port 0

SATA 3Gb/s Port 0

SATA 6Gb/s Port 1

SATA 3Gb/s Port 2

SATA 3Gb/s Port 3

Table 1-6. Server / Workstation Intel® C220 Series Chipset Family SKUs (Sheet 1 of 2)

SKU Name

Feature Set

Intel®

C222

Chipset

Intel

C224

Chipset

Flexible I/O No No Yes

PCI Express* 2.0 Ports 888

Tot a l n u m b er o f U S B p o r t s 10

• USB 3.0 Capable Ports (SuperSpeed and all USB 2.0 speeds) 2

• USB 2.0 Only Ports 8 8 10(8)

Total number of SATA ports 6 6 4(6)

• SATA Ports (6 Gb/s, 3 Gb/s, and 1.5 Gb/s) 2

• SATA Ports (3 Gb/s and 1.5 Gb/s only) 4 2 0

VGA No No Yes

Intel® Wireless Display (WiDi) No No Yes

Intel® Rapid Storage Technology AHCI Yes Ye s Ye s

RAID 0/1/5/10 Support Yes Ye s Ye s

No No Yes

No No No

Intel® Anti-Theft Technology

Intel® Smart Response Technology

Intel® Active Management Technology 9.0 No No Yes

Intel® Small Business Advantage No No No

Intel Rapid Start Technology No No No

Intel® Identity Protection Technology (Intel® IPT)

No No Yes

Near Field Communication No No No

ACPI S1 State Support No No No

Intel

C226

Chipset

4(6)

Datasheet 55

Introduction

Table 1-6. Server / Workstation Intel® C220 Series Chipset Family SKUs (Sheet 2 of 2)

SKU Name

Feature Set

Processor Features Controlled by PCH SKU

Processor PEG Port Bifurcation 1x16,

Processor PEG Port Maximum Speed Allowed Gen 3

Processor Maximum Number of Independent Displays Supported 3 3 3

Processor Maximum Number of Memory Channels (Maximum DIMMS per Channel) 2 (2) 2 (2) 2 (2)

Processor and Memory Overclocking Disabled Disabled Disabled

Processor Graphics Disabled Disabled Enabled

Notes:

1. Contact your local Intel Field Sales Representative for currently available PCH SKUs.

2. Table above shows feature differences between the PCH SKUs. If a feature is not listed in the table, it is considered a Base feature that is included in all SKUs

3. PCI Legacy Mode may optionally be used allowing external PCI bus support through a PCIe-to-PCI bridge. See Section 5.2.2 for more details.

4. The number of PCI Express ports available depends on the Flexible I/O configuration. See Section 2.1 and

Tab l e 1 -7 .

5. USB 2.0 ports 6,7,12 and 13 are disabled on 10 port SKUs.

6. USB 2.0 ports 6 and 7 are disabled on 12 port SKUs.

7. Only USB 3.0 ports 1 and 2 are enabled.

8. Only USB 3.0 ports 1,2,5 and 6 are enabled.

9. 6 USB 3.0 ports require High Speed I/O ports 5 and 6 to be configured as USB 3.0. See Section 2.1 and

Tab l e 1 -7 .

10. When Flexible I/O ports are configured as USB 3.0, the total number of USB 2.0 only ports reduces in direct proportion.

11. 6 SATA ports require High Speed I/O ports 13 and 14 to be configured as SATA. See Section 2.1 and

Tab l e 1 -7 .

12. SATA 6 Gb/s support on ports 0 and 1 only. SATA ports 0 and 1 also support 3 Gb/s and 1.5 Gb/s.

13. SATA 6 Gb/s support on ports 0,1,2 and 3. SATA ports 0,1,2 and 3 also support 3 Gb/s and 1.5 Gb/s.

14. Intel

15. Intel

16. Intel

17. Refer to the processor datasheet for additional details on processor features.

Smart Response Technology requires an Intel® Core™ processor.

Anti-Theft Technology requires an Intel® Core™ processor.

Identity Protection Technology requires an Intel® Xeon® processor.

Intel®

C222

Chipset

2x8, 1x8,

2x4

(8GT/s)

Intel®

C224

Chipset

1x16,

2x8, 1x8,

2x4

Gen 3

(8GT/s)

Intel®

C226

Chipset

1x16,

2x8, 1x8,

2x4

Gen 3

(8GT/s)

Table 1-7. Server / Workstation Intel® C220 Series Chipset Family SKUs Flexible I/O

Map

High Speed I/O Ports

SKU

Port 1Port 2Port 3Port 4Port 5Port 6Port 7Port 8Port 9Port 10Port 11Port 12Port 13Port 14Port 15Port 16Port 17Port

USB

C222

C224

C226

3.0

Port 1

USB

3.0

Port 1

USB

3.0

Port 1

USB

3.0

Port 2

USB

3.0

Port 2

USB

3.0

Port 2

NA NA

USB

3.0

Port 5

USB

3.0

Port 5

USB

3.0

Port 6

USB

3.0

Port 6

PCIe* Port 1

USB

3.0

Port 3

PCIe* Port 1

PCIe* Port 2

USB

3.0

Port 4

PCIe*

Port 2

PCIe* Port 3

PCIe*

Port 4

PCIe* Port 4

Notes:

1. Ports listed with NA are not available and are disabled.

PCIe* Port 5

PCIe* Port 6

PCIe* Port 7

PCIe*

Port 8

PCIe* Port 8

SATA 3Gb/s Port 4

SATA 6Gb/s Port 4

PCIe*

Port 1

SATA 3Gb/s Port 5

SATA 6Gb/s Port 5

PCIe*

Port 2

SATA 6Gb/s Port 0

SATA 6Gb/s Port 1

Datasheet

SATA 3Gb/s Port 2

SATA 6Gb/s Port 2

SATA 3Gb/s Port 3

SATA 6Gb/s Port 3



Introduction

1.4 Device and Revision ID Table

The Revision ID (RID) register is an 8-bit register located at offset 08h in the PCI header of every PCI/PCIe function. The RID register is used by software to identify a particular component stepping when a driver change or patch unique to that stepping is needed.

Table 1-8. PCH Device and Revision ID Table (Sheet 1 of 3)

Device

Function

D31:F2 SATA

D31:F5 SATA 8C08h 04h Desktop: Non-AHCI and Non-RAID Mode 

D28:F0 PCI

D28:F1 PCI

D28:F2 PCI

D28:F3 PCI

Descrip-

tion

Express*

Port 1

Express

Port 2

Express

Port 3

Express

Port 4

Dev ID

8C00h 04h Desktop: Non-AHCI and Non-RAID Mode.

8C01h 04h Mobile: Non-AHCI and Non-RAID Mode.

8C02h 04h Desktop: AHCI Mode.

8C03h 04h Mobile: AHCI Mode.

8C04h 04h Desktop: RAID Capable

2822h 04h Desktop: RAID Capable

8C05h 04h Mobile: RAID Capable

282Ah 04h Mobile: RAID Capable

8C06h 04h Desktop: RAID Capable

2826h 04h Server/Workstation: RAID Capable

8C07h 04h Mobile: RAID Capable

8C0Eh 04h Desktop: RAID 1 Only.

8C0Fh 04h Mobile: RAID 1 Only.

8C09h 04h Mobile: Non-AHCI and Non-RAID Mode 

8C10h 04h Desktop and Mobile (When D28:F0:ECh:bit 1= 0)

244Eh 04h Desktop (When D28:F0:ECh:bit 1 = 1)

2448h 04h Mobile (When D28:F0:ECh:bit 1 = 1)

8C12h 04h Desktop and Mobile (When D28:F1:ECh:bit 1 = 0)

244Eh 04h Desktop (When D28:F1:ECh:bit 1 = 1)

2448h 04h Mobile (When D28:F1:ECh:bit 1 = 1)

8C14h 04h Desktop and Mobile (When D28:F2:ECh:bit 1 = 0)

244Eh 04h Desktop (When D28:F2:ECh:bit 1 = 1)

2448h 04h Mobile (When D28:F2:ECh:bit 1 = 1)

8C16h 04h Desktop and Mobile (When D28:F3:ECh:bit 1 = 0)

244Eh 04h Desktop (When D28:F3:ECh:bit 1 = 1)

2448h 04h Mobile (When D28:F3:ECh:bit 1 = 1)

SRID

Technology, if AIE (D31:F2 Offset 9Ch bit 7) = 0 AND AIES (D31:F2 Offset 9Ch bit 6) = 0.

Technology, if AIE (D31:F2 Offset 9Ch bit 7) = 0.

if AIE (D31:F2 Offset 9Ch bit 7) = 1.

Technology, if AIE (D31:F2 Offset 9Ch bit 7) = 0 AND AIES (D31:F2 Offset 9Ch bit 6) = 1.

AIE (D31:F2 Offset 9Ch bit 7) = 1.

(Ports 4 and 5)

Comments

if AIE (D31:F2 Offset 9Ch bit 7) = 1.

with or without Intel® Smart Response

if AIE (D31:F2 Offset 9Ch bit 7) = 1.

with or without Intel® Smart Response

and Intel® Smart Response Technology,

and Intel® Smart Response

and Intel® Smart Response Technology, if

Datasheet 57

Table 1-8. PCH Device and Revision ID Table (Sheet 2 of 3)

Introduction

Device

Function

D28:F4 PCI

D28:F5 PCI

D28:F6 PCI

D28:F7 PCI

D27:F0 Intel

D31:F3 SMBus 8C22h 04h Desktop and Mobile - All SKUs.

D31:F6 Thermal 8C24h 04h Desktop and Mobile - All SKUs.

D29:F0 USB EHCI #18C26h 04h Desktop and Mobile - All SKUs.

D26:F0 USB EHCI #28C2Dh 04h Desktop and Mobile - All SKUs.

Descrip-

tion

Express

Port 5

Express

Port 6

Express

Port 7

Express

Port 8

High

Definition

Audio

Dev ID

8C18h 04h Desktop and Mobile (When D28:F4:ECh:bit 1 = 0)

244Eh 04h Desktop (When D28:F4:ECh:bit 1 = 1)

2448h 04h Mobile (When D28:F4:ECh:bit 1 = 1)

8C1Ah 04h Desktop and Mobile (When D28:F5:ECh:bit 1 = 0)

244Eh 04h Desktop (When D28:F5:ECh:bit 1 = 1)

2448h 04h Mobile (When D28:F5:ECh:bit 1 = 1)

8C1Ch 04h Desktop and Mobile (When D28:F6:ECh:bit 1 = 0)

244Eh 04h Desktop (When D28:F6:ECh:bit 1 = 1)

2448h 04h Mobile (When D28:F6:ECh:bit 1 = 1)

8C1Eh 04h Desktop and Mobile (When D28:F7:ECh:bit 1 = 0)

244Eh 04h Desktop (When D28:F7:ECh:bit 1 = 1)

2448h 04h Mobile (When D28:F7:ECh:bit 1 = 1)

8C20h 04h Desktop and Mobile - All SKUs.

SRID

Comments

D20:F0 USB xHCI 8C31h 04h Desktop and Mobile - All SKUs.

D25:F0 LAN 8C33h 04h Desktop and Mobile - All SKUs.

D22:F0 Intel

D22:F1

D22:F2 IDE-R 8C3Ch 04h Desktop and Mobile - All SKUs.

D22:F3 KT 8C3Dh 04h Desktop and Mobile - All SKUs.

Interface

Intel ME

Interface

8C3Ah 04h Desktop and Mobile - All SKUs.

8C3Bh 04h Desktop and Mobile - All SKUs.

Datasheet



Introduction

Table 1-8. PCH Device and Revision ID Table (Sheet 3 of 3)

Device

Function

D31:F0 LPC 8C41h 04h LPC Controller (Mobile Full Featured Engineering Sample).

Notes:

1. PCH contains two SATA controllers. The SATA Device ID is dependent upon which SATA mode is selected by BIOS and what RAID capabilities exist in the SKU.

2. The SATA RAID Controller Device ID is dependent upon the AIE bit setting (bit 7 of D31:F2:Offset 9Ch).

3. SATA Controller 2 (D31:F5) is only visible when D31:F2 CC.SCC =01h.

4. LAN Device ID is loaded from EEPROM. If EEPROM contains either 0000h or FFFFh in the Device ID location, then 8C33h is used. Refer to the appropriate Intel Device IDs.

5. For a given stepping, not all SKUs may be available.

6. This table shows the default PCI Express Function Number-to-Root Port mapping. Function numbers for a given root port are assignable through the “Root Port Function Number and Hide for PCI Express Root Ports” register (RCBA+0404h).

Descrip-

tion

Dev ID

8C42h 04h LPC Controller (Desktop Full Featured Engineering Sample).

8C44h 04h LPC Controller (Z87 SKU).

8C46h 04h LPC Controller (Z85 SKU).

8C49h 04h LPC Controller (HM86 SKU).

8C4Ah 04h LPC Controller (H87 SKU).

8C4Bh 04h LPC Controller (HM87 SKU).

8C4Ch 04h LPC Controller (Q85 SKU).

8C4Eh 04h LPC Controller (Q87 SKU).

8C4Fh 04h LPC Controller (QM87 SKU).

8C50h 04h LPC Controller (B85 SKU).

8C52h 04h LPC Controller (C222 SKU).

8C54h 04h LPC Controller (C224 SKU).

8C56h 04h LPC Controller (C226 SKU).

8C5Ch 04h LPC Controller (H81 SKU).

SRID

Comments

GbE physical layer Transceiver (PHY) datasheet for LAN

§ §

Datasheet 59

2 Signal Description

This chapter provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface.

The “#” symbol at the end of the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when voltage level is high.

The following notations are used to describe the signal type:

I Input Pin.

O Output Pin.

OD O Open Drain Output Pin.

I/OD Bi-directional Input/Open Drain Output Pin.

I/O Bi-directional Input/Output Pin.

CMOS CMOS buffers. 1.5 V tolerant.

COD CMOS Open Drain buffers. 3.3 V tolerant.

HVCMOS High Voltage CMOS buffers. 3.3 V tolerant.

A Analog reference or output.

Signal Description

The “Type” for each signal is indicative of the functional operating mode of the signal. Unless otherwise noted in Section 3.2 or Section 3.3, a signal is considered to be in the functional operating mode after RTCRST# de-asserts for signals in the RTC well, after RSMRST# de-asserts for signals in the suspend well, after PWROK asserts for signals in the core well, after DPWROK asserts for signals in the DeepSx well, after APWROK asserts for signals in the Active Sleep well.

Note: Core well includes 1.05 V, 1.5 V and 3.3 V rails powering PCH logic and these rails may

be shut off in S3, S4, S5, and G3 states.

Datasheet



MISC.

Signals

Intel®Flexible

Display

Interface

Power

Mgnt.

Interrupt Interface

PMSYNCH

RCIN#

THRMPTRIP#

PROCPWRGD

Processor

Interface

USB

SERIRQ

PIRQ[D:A]#

PIRQ[H:E]#/GPIO[5:2]

USB[13:0][P,N] OC0#/GPI O59; OC1# /GPIO40 OC2#/GPI O41; OC3# /GPIO42

OC4#/GPIO43; OC5#/GPIO9

OC6#/GPI O10; OC7# /GPIO14

USBRBIAS, USBRBIAS #

USB3[T,R][p,n][6:1]

RTCX1 RTCX2

CLKIN_DM I_[P, N] CLKIN_SATA_[ P,N] CLKIN_ DOT96[P, N]

XTAL25_IN;REF14CLKIN

PCIECLKRQ0#/GPIO73;PCIECLKRQ1#/GPIO18

PCIECLKRQ2#/GPI O20/SMI#;PCI ECLKRQ3#/GPIO25

PCIECLKRQ4#/GPIO26;PCIECLKRQ5#/GPIO44 PCIECLKRQ6#/GPIO45;PCIECLKRQ7#/GPIO46

PEG_A_CLKRQ#/GPIO47;PEG_B_CLKRQ#/GPIO56

RTC

Cloc k Inputs

Misc .

Signals

INTVRMEN, DSWVRMEN

SPKR

SRTCRST#; RTCRST#

GPIO35/NMI#

GPIO24

PME#

General Purpose

I/O

GPIO[72,57,32,28,27,15,8]

PWM[3:0]

TACH7/GPIO71;TACH6/GPIO70; TACH5/GPIO69;TACH4/GPIO68

TACH3/GPIO7; TACH2/GPIO6; TACH1/GPIO1;TACH0/GPIO17

SST

PECI

Direc t Media

Interface

LPC / FWH

Interface

SMBus

Interface

Intel

High

Definition

Audio

System

Mgnt.

LAD[3:0]

LFRAME#

LDRQ0#; LDRQ1#/GPI O23

Seri al ATA

Interface

PCI Express*

Interface

SPI

SPI_IO1

SPI_IO2 SPI_MISO SPI_MOSI

SPI_CS0#; SPI _CS1#;SPI_CS2#

SPI_CLK

JTAG

Controller

Link

Fan

Speed

Control

Clock

Outp uts

CLKOUT_DP_[P,N]

CLKOUT_DMI_[P,N]

XTAL25_OUT

CLKOUT_PEG_A_[P, N];CLKOUT_PEG_B_[ P,N]

CLKOUT_PCIE[7:0]_[P,N]

CLKOUT_ITPXDP_[P, N]

CLKOUT_33MHz[4: 0] CLKOUTFLEX0/GPIO6 4;CLKOUTFLEX1/GPIO6 5 CLKOUTFLEX2/GPIO6 6;CLKOUTFLEX3/GPIO6 7

Analog Displ ay

CL_CLK ; CL_DATA CL_RST#

SATA_TX[P,N] [5:0] SATA_RX[P,N][5:0] SATA_RCOMP SATA_IREF SATALED# SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37 SATA4GP/GPIO16 SATA5GP/GPIO49 SCLOCK/GPIO22, SL OAD/GPIO38 SDATAOUT0/GPIO39, SDATAOUT1/GPIO48

HDA_RST# HDA_SYNC HDA_BCLK HDA_SDO HDA_SDIN[3:0] HDA_DOCK_EN#/HDA_DOCK_RST#

DMI_TX[P,N][3:0] DMI_RX[P,N][3:0] DMI_RCOMP DMI_IREF

SMBDATA; SMBCLK SMBALERT#/GPIO11

INTRUDER#; SML[1:0]DATA;SML[1:0]CLK SML0ALERT#/GPIO60 SML1ALERT#/

TEMP_ALERT#/GPIO74

FDI_RXP[1: 0] FDI_RXN[1:0] FDI_CSYNC FDI_INT FDI_RCOMP FDI_IREF

SUSWARN#/SUSPWRDNACK/GPIO30 DPWROK SYS_RESET# RSMRST# SLP_S3# SLP_S4# SLP_S5#/GPIO6 3 SLP_A# CLKRUN#/GPIO32 PWROK AWROK PWRBTN# RI# WAKE# SUS_STAT#/GPIO6 1 SUSCLK/GPIO62 BATLOW#/GPIO72 PLTRST# BMBUSY#/GPIO0 GPIO34 ACPRESENT/GPIO31 DRAMPWROK LAN_PHY_ PWR_CTRL/G PIO12 SLP_WLAN#/GPIO29 SUSACK# SLP_SUS# PLTRST#

VGA_RED;VGA_GREEN;VGA_BLUE DAC_IREF VGA_HSYNC;VGA_VSYNC VGA_DDC_CLK; VGA_DDC_DATA VGA_IRTN

GPIO50 GPIO52 GPIO54 GPIO51 GPIO53 GPIO55

CLKIN_33MHZLOOPBACK

JTAGTCK JTAGTMS JTAGTDI JTAGTDO

PET[p,n][8:1] PER[p,n] [8:1] PCIE_RCOMP PCIE_IREF

Digi tal

Displ ay

Sideband

Signals

DDP[B:D]_AUX[P,N] DDP[B:D]_HPD DDP[B:D]_CTRLCLK DDP[B:D]_CTRLDATA eDP_BKLTEN eDP_BKLTCTL eDP_VDDEN

Signal Description

Figure 2-1. PCH Interface Signals Block Diagram (not all signals are on all SKUs)

Datasheet 61

2.1 Flexible I/O

The Intel® 8 Series/C220 Series Chipset Family PCH implements Flexible I/O, a technology to allow some high speed signals to be configured as PCIe*, USB 3.0, or SATA signals. There are a total of 18 High Speed I/O Ports in the PCH and, through soft straps, four of these ports can have their functionality selected to meet the I/O needs of the platform. Table 2-1 illustrates high speed I/O ports mapping to PCIe, USB 3.0 and SATA signals.

Table 2-1. I/O Flexibility Signal Mapping

High Speed I/

O Ports

1— —

2— —

3— —

4— —

13 —

14 —

15 — — —

16 — — —

17 — — —

18 — — —

GbE Map PCIe Signals USB 3.0 Signals SATA Signals

000

(soft strap)

001

(soft strap)

010

(soft strap)

011

(soft strap)

100

(soft strap)

101

(soft strap)

110

(soft strap)

111

(soft strap)

PETp/n1

PERp/n1

PETp/n2

PERp/n2

PETp/n3

PERp/n3

PETp/n4

PERp/n4

PETp/n5

PERp/n5

PETp/n6

PERp/n6

PETp/n7

PERp/n7

PETp/n8

PERp/n8

PETp/n1

PERp/n1

PETp/n2

PERp/n2

Signal Description

USB3Tp/n1

USB3Rp/n1

USB3Tp/n2

USB3Rp/n2

USB3Tp/n5

USB3Rp/n5

USB3Tp/n6

USB3Rp/n6

USB3Tp/n3

USB3Rp/n3

USB3Tp/n4

USB3Rp/n4

——

—

SATA_TXp/n4

SATA_RXp/n4

SATA_TXp/n5

SATA_RXp/n5

SATA_TXp/n0

SATA_RXp/n0

SATA_TXp/n1

SATA_RXp/n1

SATA_TXp/n2

SATA_RXp/n2

SATA_TXp/n3

SATA_RXp/n3

Notes:

1. High speed I/O ports 5 and 6 can be configured as either PCIe port 1 and 2 or USB 3.0 port 3 and 4.

2. High speed I/O ports 13 and 14 can be configured as either PCIe port 1 and 2 or SATA port 4 and 5.

3. Maximum of 8 PCIe* ports, 6 USB 3.0 Ports or 6 SATA ports possible. GbE uses the physical interface of PCIe ports so having 8 PCIe ports + 1 GbE simultaneously does not mean a total of 9 PCIe ports. 8 PCIe ports + 1 GbE simultaneously is supported (depending on SKU configuration).

4. Refer to Chapter 5.22 for more details.

Datasheet



Signal Description

2.2 USB Interface

Note: The USB 2.0 signals in the PCH integrate pull-down resistors and provide an output

driver impedance of 45  that requires no external series resistor. No external pull-up/ pull-down resistors should be added to the USB 2.0 signals. USB ports not needed can be left floating as No Connect.

Note: The voltage divider formed by the device pull-up and the host pull-down will ensure the

data wire park at a safe voltage level, which is below the VBUS value. This ensures that the host/hub will not see 5 V at the wire when inter-operating with devices that have VBUS at 5 V.

Note: All USB 2.0 register addresses throughout the datasheet correspond to the external pin

names. Refer to Table 2-2 to know exactly how the USB pins are mapped to the different internal ports within the xHCI and EHCI controllers.

Table 2-2. USB Interface Signals (Sheet 1 of 3)

Name

USB2p0  USB2n0

USB2p1  USB2n1

USB2p2  USB2n2

USB2p3  USB2n3

USB2p4  USB2n4

USB2p5  USB2n5

USB2p6  USB2n6

USB2p7  USB2n7

USB2p8  USB2n8

USB2p9  USB2n9

xHCI

Port

EHCI

Port

00I/O

11I/O

22I/O

33I/O

84I/O

95I/O

12 6 I/O

13 7 I/O

48I/O

59I/O

Type Description

USB 2.0 Port 0 Transmit/Receive Differential Pair 0:

This USB 2.0 signal pair can be routed to xHCI or EHCI Controller 1 through software and should map to a USB connector with one of the overcurrent OC Pins 0-3.

USB 2.0 Port 1 Transmit/Receive Differential Pair 1: This USB 2.0 signal pair can be routed to xHCI or EHCI Controller 1 through software and should map to a USB connector with one of the overcurrent OC Pins 0-3.

USB 2.0 Port 2 Transmit/Receive Differential Pair 2: This USB 2.0 signal pair can be routed to xHCI or EHCI Controller 1 through software and should map to a USB connector with one of the overcurrent OC Pins 0-3.

USB 2.0 Port 3 Transmit/Receive Differential Pair 3: This USB 2.0 signal pair can be routed to xHCI or EHCI Controller 1 through software and should map to a USB connector with one of the overcurrent OC Pins 0-3.

USB 2.0 Port 4 Transmit/Receive Differential Pair 4: This USB 2.0 signal pair can be routed to xHCI or EHCI Controller 1 through software and should map to a USB connector with one of the overcurrent OC Pins 0-3.

USB 2.0 Port 5 Transmit/Receive Differential Pair 5: This USB 2.0 signal pair can be routed to xHCI or EHCI Controller 1 through software and should map to a USB connector with one of the overcurrent OC Pins 0-3.

USB 2.0 Port 6 Transmit/Receive Differential Pair 6: This USB 2.0 signal pair can be mapped to xHCI or EHCI Controller 1 through software and should map to a USB connector with one of the overcurrent OC Pins 0-3.

USB 2.0 Port 7 Transmit/Receive Differential Pair 7: This USB 2.0 signal pair can be mapped to xHCI or EHCI Controller 1 through software and should map to a USB connector with one of the overcurrent OC Pins 0-3.

USB 2.0 Port 8 Transmit/Receive Differential Pair 8: This USB 2.0 signal pair can be mapped to xHCI or EHCI Controller 2 through software and should map to a USB connector with one of the overcurrent OC Pins 4–7.

USB 2.0 Port 9 Transmit/Receive Differential Pair 9: This USB 2.0 signal pair can be mapped to xHCI or EHCI Controller 2 through software and should map to a USB connector with one of the overcurrent OC Pins 4–7.

Datasheet 63

Table 2-2. USB Interface Signals (Sheet 2 of 3)

Signal Description

Name

USB2p10  USB2n10

USB2p11  USB2n11

USB2p12  USB2n12

USB2p13  USB2n13

USB3Tp1 USB3Tn1

USB3Rp1 USB3Rn1

USB3Tp2 USB3Tn2

USB3Rp2 USB3Rn2

USB3Tp3 USB3Tn3

USB3Rp3 USB3Rn3

USB3Tp4 USB3Tn4

xHCI

Port

10 12 I/O

11 13 I/O

EHCI

Port

610I/O

711I/O

1-O

1-I

2-O

2-I

3-O

3-I

4-O

Type Description

USB 2.0 Port 10 Transmit/Receive Differential Pair 10:This USB 2.0 signal pair can be mapped to xHCI or EHCI

Controller 2 through software and should map to a USB connector with one of the overcurrent OC Pins 4–7.

USB 2.0 Port 11 Transmit/Receive Differential Pair 11: This USB 2.0 signal pair can be mapped to xHCI or EHCI Controller 2 through software and should map to a USB connector with one of the overcurrent OC Pins 4–7.

USB 2.0 Port 12 Transmit/Receive Differential Pair 12: This USB 2.0 signal pair can be mapped to xHCI or EHCI Controller 2 through software and should map to a USB connector with one of the overcurrent OC Pins 4–7.

USB 2.0 Port 13 Transmit/Receive Differential Pair 13: This USB 2.0 signal pair can be mapped to xHCI or EHCI Controller 2 through software and should map to a USB connector with one of the overcurrent OC Pins 4–7.

USB 3.0 Differential Transmit Pair 1: These are USB 3.0based outbound high-speed differential signals, mapped to High Speed I/O (HSIO) Port #1 and the xHCI Controller. It should map to a USB connector with one of the OC (overcurrent) pins 0–7.

USB 3.0 Differential Receive Pair 1: These are USB 3.0based inbound high-speed differential signals, mapped to High Speed I/O (HSIO) Port #1 and the xHCI Controller. It should map to a USB connector with one of the OC (overcurrent) pins 0–7.

USB 3.0 Differential Transmit Pair 2: These are USB 3.0based outbound high-speed differential signals, mapped to High Speed I/O (HSIO) Port #2 and the xHCI Controller. It should map to a USB connector with one of the OC (overcurrent) pins 0–7.

USB 3.0 Differential Receive Pair 2: These are USB 3.0based inbound high-speed differential signals, mapped to High Speed I/O (HSIO) Port #2 and the xHCI Controller. It should map to a USB connector with one of the OC (overcurrent) pins 0–7.

USB 3.0 Differential Transmit Pair 3: These are USB 3.0based outbound high-speed differential signals, mapped to High Speed I/O (HSIO) Port 5 and the xHCI Controller. It should map to a USB connector with one of the OC (overcurrent) pins 0–7.

Note: Use FITC to set the soft straps that select this port as

USB 3.0 Differential Receive Pair 3: These are USB 3.0based inbound high-speed differential signals, mapped to High Speed I/O (HSIO) Port 5 and the xHCI Controller. It should map to a USB connector with one of the OC (overcurrent) pins 0–7.

Note: Use FITC to set the soft straps that select this port as

USB 3.0 Differential Transmit Pair 4: These are USB 3.0based outbound high-speed differential signals, mapped to High Speed I/O (HSIO) Port #6 and the xHCI Controller. It should map to a USB connector with one of the OC (overcurrent) pins 0–7.

Note: Use FITC to set the soft straps that select this port as

USB 3.0 Port 3. Default configuration is PCIe Port 1.

USB 3.0 Port 4. Default configuration is PCIe Port 2.

Datasheet



Signal Description

Table 2-2. USB Interface Signals (Sheet 3 of 3)

Name

USB3Rp4 USB3Rn4

USB3Tp5 USB3Tn5

USB3Rp5 USB3Rn5

USB3Tp6 USB3Tn6

USB3Rp6 USB3Rn6

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

USBRBIAS --O

USBRBIAS# --I

xHCI

Port

EHCI

Port

4-I

5-O

5-I

6-O

6-I

--I

Type Description

USB 3.0 Differential Receive Pair 4: These are USB 3.0-

based inbound high-speed differential signals, mapped to High Speed I/O (HSIO) Port #6 and the xHCI Controller. It should map to a USB connector with one of the OC (overcurrent) pins 0–7.

Note: Use FITC to set the soft straps that select this port as

USB 3.0 Differential Transmit Pair 5: These are USB 3.0based outbound high-speed differential signals, mapped to High Speed I/O (HSIO) Port #3 and the xHCI Controller. It should map to a USB connector with one of the OC (overcurrent) pins 0–7.

USB 3.0 Differential Receive Pair 5: These are USB 3.0based inbound high-speed differential signals, mapped to High Speed I/O (HSIO) Port #3 and the xHCI Controller. It should map to a USB connector with one of the OC (overcurrent) pins 0–7.

USB 3.0 Differential Transmit Pair 6: These are USB 3.0based outbound high-speed differential signals, mapped to High Speed I/O (HSIO) Port #4 and the xHCI Controller. It should map to a USB connector with one of the OC (overcurrent) pins 0–7.

USB 3.0 Differential Receive Pair 6: These are USB 3.0based inbound high-speed differential signals, mapped to High Speed I/O (HSIO) Port #4 and the xHCI Controller. It should map to a USB connector with one of the OC (overcurrent) pins 0–7.

Overcurrent Indicators: These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred.

OC[7:0]# is the default (Native) function for these pins but they may be configured as GPIOs instead.

Notes:

1. OC pins are 3.3 V tolerant.

2. Sharing of OC pins is required to cover all 14 USB

3. OC[3:0]# should be connected with USB 2.0 ports 0–7

4. OC[7:4]# should be connected with USB 2.0 ports 8–13

USB Resistor Bias: Analog connection point for an external resistor that is used to set transmit currents and internal load resistors. It is recommended that a 22.6 Ω ±1% resistor to ground be connected to this pin.

USB Resistor Bias Complement: Analog connection point for an external resistor that is used to set transmit currents and internal load resistors. This signal should be connected directly to USBRBIAS.

USB 3.0 Port 4. Default configuration is PCIe Port 2.

connectors but no more than 1 OC line may be connected to a USB connector.

and any 4 of USB 3.0 ports 1–6.

Datasheet 65

2.3 PCI Express*

Table 2-3. PCI Express* Signals (Sheet 1 of 2)

Name Type Description

PCI Express* Differential Transmit Pair 1: These are PCI Express 2.0-based

outbound high-speed differential signals, and can be mapped to either High Speed I/O (HSIO) Port 5 or HSIO Port 13.

PETp1 PETn1

PERp1 PERn1

PETp2 PETn2

PERp2 PERn2

PETp3 PETn3

PERp3 PERn3

PETp4 PETn4

PERp4 PERn4

PETp5 PETn5

PERp5 PERn5

PETp6 PETn6

PERp6 PERn6

PETp7 PETn7

PERp7 PERn7

Note: GbE can be mapped to PCIe Port 1 if PCIe Port 1 is selected at HSIO Port

5. GbE cannot be mapped to PCIe Port 1 if PCIe Port 1 is selected at HSIO Port 13. See Section 5.4 for details on GbE configuration and support.

Note: Use FITC to set the soft straps that select this port as muxed with USB

3.0 Port 3 or muxed with SATA Port 4. FITC does not allow multiplexing PCIe Port 1 with USB 3.0 Port 3 and SATA Port 4 simultaneously, and it is not a supported configuration.

PCI Express* Differential Receive Pair 1: These are PCI Express 2.0-based inbound high-speed differential signals, and can be mapped to HSIO Port 5 or HSIO Port 13.

Note: GbE can be mapped to PCIe Port 1 if PCIe Port 1 is selected at HSIO Port

5. GbE cannot be mapped to PCIe Port 1 if PCIe Port 1 is selected at HSIO Port 13. See Section 5.4 for details on GbE configuration and support.

Note: Use FITC to set the soft straps that select this port as muxed with USB

3.0 Port 3 or muxed with SATA Port 4. FITC does not allow multiplexing PCIe Port 1 with USB 3.0 Port 3 and SATA Port 4 simultaneously, and it is not a supported configuration.

PCI Express Differential Transmit Pair 2: These are PCI Express 2.0-based outbound high-speed differential signals, and can be mapped to HSIO Port 6 or HSIO Port 14.

Note: GbE can be mapped to PCIe Port 2 if PCIe Port 2 is selected at HSIO Port

6. GbE cannot be mapped to PCIe Port 2 if PCIe Port 2 is selected at HSIO Port 14. See Section 5.4 for details on GbE configuration and support.

Note: Use FITC to set the soft straps that select this port as muxed with USB

3.0 Port 4 or muxed with SATA Port 5. FITC does not allow multiplexing PCIe Port 2 with USB 3.0 Port 4 and SATA Port 5 simultaneously, and it is not a supported configuration.

PCI Express Differential Receive Pair 2: These are PCI Express 2.0-based inbound high-speed differential signals, and can be mapped to HSIO Port 6 or HSIO Port 14.

Note: GbE can be mapped to PCIe Port 2 if PCIe Port 2 is selected at HSIO Port

6. GbE cannot be mapped to PCIe Port 2 if PCIe Port 2 is selected at HSIO Port 14. See Section 5.4 for details on GbE configuration and support.

Note: Use FITC to set the soft straps that select this port as muxed with USB

3.0 Port 4 or muxed with SATA Port 5. FITC does not allow multiplexing PCIe Port 2 with USB 3.0 Port 4 and SATA Port 5 simultaneously, and it is not a supported configuration.

PCI Express Differential Transmit Pair 3: These are PCI Express 2.0-based outbound high-speed differential signals, mapped to HSIO Port 7.

PCI Express Differential Receive Pair 3: These are PCI Express 2.0-based inbound high-speed differential signals, mapped to HSIO Port 7.

PCI Express Differential Transmit Pair 4: These are PCI Express 2.0-based outbound high-speed differential signals, mapped to HSIO Port 8.

PCI Express* Differential Receive Pair 4: These are PCI Express 2.0-based outbound high-speed differential signals, mapped to HSIO Port 8.

PCI Express Differential Transmit Pair 5: These are PCI Express 2.0-based outbound high-speed differential signals, mapped to HSIO Port 9.

PCI Express Differential Receive Pair 5: These are PCI Express 2.0-based outbound high-speed differential signals, mapped to HSIO Port 9.

PCI Express Differential Transmit Pair 6: These are PCI Express 2.0-based outbound high-speed differential signals, mapped to HSIO Port 10.

PCI Express Differential Receive Pair 6: These are PCI Express 2.0-based outbound high-speed differential signals, mapped to HSIO Port 10.

PCI Express Differential Transmit Pair 7: These are PCI Express 2.0-based outbound high-speed differential signals, mapped to HSIO Port 11.

PCI Express Differential Receive Pair 7: These are PCI Express 2.0-based outbound high-speed differential signals, mapped to HSIO Port 11.

Signal Description

Datasheet



Signal Description

Table 2-3. PCI Express* Signals (Sheet 2 of 2)

Name Type Description

PETp8 PETn8

PERp8 PERn8

PCIE_RCOMP I

PCIE_IREF I Internal Reference Voltage: Connect directly to 1.5 V.

PCI Express Differential Transmit Pair 8: These are PCI Express 2.0-based

outbound high-speed differential signals, mapped to HSIO Port 12.

PCI Express Differential Receive Pair 8: These are PCI Express 2.0-based

outbound high-speed differential signals, mapped to HSIO Port 12.

Impedance Compensation Input: Connected to a 7.5 K (1%) precision external pull-up resistor to 1.5 V.

2.4 Serial ATA Interface

Table 2-4. Serial ATA Interface Signals (Sheet 1 of 2)

Name Type Description

SATA_TXp0 SATA_TXn0

SATA_RXp0 SATA_RXn0

SATA_TXp1 SATA_TXn1

SATA_RXp1 SATA_RXn1

SATA_TXp2 SATA_TXn2

SATA_RXp2 SATA_RXn2

SATA_TXp3 SATA_TXn3

SATA_RXp3 SATA_RXn3

SATA_TXp4 SATA_TXn4

SATA_RXp4 SATA_RXn4

Serial ATA Differential Transmit Pair 0: These outbound SATA Port 0 high-speed

differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO

Port 15. In compatible mode, SATA Port 0 is the primary master of SATA Controller

Serial ATA Differential Receive Pair 0: These inbound SATA Port 0 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO

Port 15. In compatible mode, SATA Port 0 is the primary master of SATA Controller

Serial ATA Differential Transmit Pair 1: These outbound SATA Port 1 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO

Port 16. In compatible mode, SATA Port 1 is the secondary master of SATA Controller

Serial ATA Differential Receive Pair 1: These inbound SATA Port 1 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO

Port 16. In compatible mode, SATA Port 1 is the secondary master of SATA Controller

Serial ATA Differential Transmit Pair 2: These outbound SATA Port 2 high-speed

differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO Port 17. In compatible mode, SATA Port 2 is the primary slave of SATA Controller 1.

Serial ATA Differential Receive Pair 2: These inbound SATA Port 2 high-speed

differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO Port 17. In compatible mode, SATA Port 2 is the primary slave of SATA Controller 1.

Serial ATA Differential Transmit Pair 3: These outbound SATA Port 3 high-speed

differential signals support 1.5Gb/s, 3Gb/s and 6Gb/s, and are mapped to HSIO Port

18. In compatible mode, SATA Port 3 is the secondary slave of SATA Controller 1.

Serial ATA Differential Receive Pair 3: These inbound SATA Port 3 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO

Port 18. In compatible mode, SATA Port 3 is the secondary slave of SATA Controller

Serial ATA Differential Transmit Pair 4: These outbound SATA Port 4 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO Port 13. In compatible mode, SATA Port 4 is the primary master of SATA Controller

Note: Use FITC to set the soft straps that select this port as PCIe Port 1. Default

configuration is SATA Port 4.

Serial ATA Differential Receive Pair 4: These inbound SATA Port 4 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO Port 13. In compatible mode, SATA Port 4 is the primary master of SATA Controller

Use FITC to set the soft straps that select this port as PCIe Port 1. Default

Note:

configuration is SATA Port 4.

Datasheet 67

Table 2-4. Serial ATA Interface Signals (Sheet 2 of 2)

Name Type Description

Serial ATA Differential Transmit Pair 5: These outbound SATA Port 5 high-speed

differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO

SATA_TXp5 SATA_TXn5

SATA_RXp5 SATA_RXn5

SATA0GP /

GPIO21

SATA1GP /

GPIO19

SATA2GP / GPIO36

SATA3GP / GPIO37

SATA4GP /

GPIO16

SATA5GP / GPIO49

SATALED# OD O

SCLOCK / GPIO22

SLOAD / GPIO38

SDATAOUT0 / GPIO39

SDATAOUT1 / GPIO48

SATA_RCOMP I

SATA_IREF I Internal Reference Voltage: Connect directly to 1.5 V.

Port 14. In compatible mode, SATA Port 5 is the secondary master of SATA Controller

Note: Use FITC to set the soft straps that select this port as PCIe Port 2. Default

Serial ATA Differential Receive Pair 5: These inbound SATA Port 5 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and 6 Gb/s, and are mapped to HSIO Port 14. In compatible mode, SATA Port 5 is the secondary master of SATA Controller

Note: Use FITC to set the soft straps that select this port as PCIe Port 2. Default

Serial ATA 0 General Purpose: When configured as SATA0GP, this is an input pin that is used as an interlock switch status indicator for SATA Port 0. Drive the pin to

‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open. The default use of this pin is GPIO21.

Serial ATA 1 General Purpose: When configured as SATA1GP, this is an input pin that is used as an interlock switch status indicator for SATA Port 1. Drive the pin to

‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open. The default use of this pin is GPIO19.

Serial ATA 2 General Purpose: When configured as SATA2GP, this is an input pin that is used as an interlock switch status indicator for SATA Port 2. Drive the pin to

‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open. The default use of this pin is GPIO36.

Serial ATA 3 General Purpose: When configured as SATA3GP, this is an input pin that is used as an interlock switch status indicator for SATA Port 3. Drive the pin to

‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open. The default use of this pin is GPIO37.

Serial ATA 4 General Purpose: When configured as SATA4GP, this is an input pin that is used as an interlock switch status indicator for SATA Port 4. Drive the pin to

‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open. The default use of this pin is GPIO16.

Serial ATA 5 General Purpose: When configured as SATA5GP, this is an input pin that is used as an interlock switch status indicator for SATA Port 5. Drive the pin to

‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open. The default use of this pin is GPIO49.

Serial ATA LED: This signal is an open-drain output pin driven during SATA command activity. It is to be connected to external circuitry that can provide the current to drive a platform LED. When active, the LED is on. When tri-stated, the LED is off. An external pull-up resistor to Vcc3_3 is required.

SGPIO Reference Clock: The SATA controller uses rising edges of this clock to transmit serial data, and the target uses the falling edge of this clock to latch data.

OD O

The SClock frequency supported is 32 kHz. If SGPIO interface is not used, this signal can be used as GPIO22.

SGPIO Load: The controller drives a ‘1’ at the rising edge of SCLOCK to indicate either the start or end of a bit stream. A 4-bit vendor specific pattern will be

OD O

transmitted right after the signal assertion. If SGPIO interface is not used, this signal can be used as GPIO38.

SGPIO Dataout: Driven by the controller to indicate the drive status in the following sequence: drive 0, 1, 2, 3, 4, 5, 0, 1, 2...

OD O

If SGPIO interface is not used, the signals can be used as GPIO.

Impedance Compensation Input: Connected to a 7.5 K (1%) precision external pull-up resistor to 1.5 V.

configuration is SATA Port 5.

Signal Description

Datasheet



Signal Description

2.5 Clock Signals

Table 2-5. Clock Interface Signals (Sheet 1 of 2)

Name Type Description

100 MHz PCIe* 3.0 specification compliant differential output to

CLKOUT_ITPXDP_P CLKOUT_ITPXDP_N

CLKOUT_DP_P CLKOUT_DP_N

CLKOUT_DPNS_P CLKOUT_DPNS_N

CLKIN_DMI_P CLKIN_DMI_N

CLKOUT_DMI_P CLKOUT_DMI_N

CLKIN_SATA_P CLKIN_SATA_N

CLKIN_DOT96_P CLKIN_DOT96_N

XTAL25_IN I Connection for 25 MHz crystal to PCH oscillator circuit

XTAL25_OUT O Connection for 25 MHz crystal to PCH oscillator circuit

REFCLK14IN I Unused. Tie signal to GND through a 10 Kresistor.

CLKOUT_PEG_A_P CLKOUT_PEG_A_N

CLKOUT_PEG_B_P CLKOUT_PEG_B_N

PEG_A_CLKRQ#/ GPIO47, PEG_B_CLKRQ# / GPIO56

CLKOUT_PCIE_P[7:0] CLKOUT_PCIE_N[7:0]

CLKIN_GND_P CLKIN_GND_N

PCIECLKRQ0# / GPIO73, PCIECLKRQ1# / GPIO18, PCIECLKRQ3# / GPIO25, PCIECLKRQ4# / GPIO26

PCIECLKRQ2# / GPIO20 / SMI#, PCIECLKRQ5# / GPIO44, PCIECLKRQ6# / GPIO45, PCIECLKRQ7# / GPIO46

processor XDP/ITP connector on platform

This Clock can be used for the 3rd PEG slot. Platform Over-clocking will not be supported when this clock is used for 3rd PEG slot.

135 MHz differential output for DisplayPort reference

135 MHz non-spread differential output for DisplayPort reference

Unused. Tie each signal to GND through a 10 K resistor.

100 MHz PCIe 3.0 specification compliant differential output to

processor

Unused. Tie each signal to GND through a 10 Kresistor.

100 MHz PCIe 3.0 specification compliant differential output to PCI

Express* Graphics device

100 MHz PCIe 3.0 specification compliant differential output to a

second PCI Express* Graphics device

Clock Request Signals for PCIe Graphics slots. Can instead be used as GPIOs

Note: External pull-up resistor required if used for CLKREQ#

functionality.

Note: These pins are not available in desktop packages.

100 MHz PCIe 2.0 specification compliant differential output to PCI

Express devices

Unused. Tie each signal to GND through a 10 Kresistor.

Clock Request Signals for PCI Express 100 MHz Clocks Can instead by used as GPIOs

I/O

Note: External pull-up resistor required if used for CLKREQ#

functionality.

Clock Request Signals for PCI Express 100 MHz Clocks Can instead by used as GPIOs

Note: External pull-up resistor required if used for CLKREQ#

I/O

functionality

Note: SMI# is for server/workstation only

Single-Ended, 33 MHz outputs to various connectors/devices. One of

CLKOUT_33MHZ[4:0] O

CLKIN_33MHZLOOPBACK I

these signals must be connected to CLKIN_33MHZLOOPBACK to function as a 33MHz clock loopback. This allows skew control for variable lengths of CLKOUT_33MHZ[4:0].

33 MHz clock feedBack input, to reduce skew between PCH on-die 33 MHz clock and 33 MHz clock observed by connected devices.

Datasheet 69

Table 2-5. Clock Interface Signals (Sheet 2 of 2)

Name Type Description

Configurable as a GPIO or as a programmable output clock which can be configured as one of the following:

CLKOUTFLEX01 / GPIO64 I/O

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

DIFFCLK_BIASREF I/O

ICLK_IREF I/O

Note:

1. It is highly recommended to prioritize 14.31818/24/48 MHz clocks on CLKOUTFLEX1 and CLKOUTFLEX3

outputs. Intel does not recommend configuring the 14.31818/24/48 MHz clocks on CLKOUTFLEX0 and CLKOUTFLEX2 if more than two 33 MHz clocks in addition to the feedback clock are used on the CLKOUT_33 MHz outputs.

/ GPIO65 I/O

/ GPIO66 I/O

/ GPIO67 I/O

• 33 MHz

• 14.31818 MHz

• 48/24 MHz

•DC Output logic ‘0’

Configurable as a GPIO or as a programmable output clock which can be configured as one of the following:

• 33 MHz

• 14.31818 MHz

• 48/24 MHz

•DC Output logic ‘0’

Configurable as a GPIO or as a programmable output clock that can be configured as one of the following:

• 33 MHz

• 14.31818 MHz

• 48/24 MHz

•DC Output logic ‘0’

Configurable as a GPIO or as a programmable output clock that can be configured as one of the following:

• 33 MHz

• 14.31818 MHz

• 48/24 MHz

•DC Output logic ‘0’

Differential Clock Bias Reference: Connected to an external precision resistor (7.5 KW ±1%) to 1.5 V

Internal Clock Bias Reference: Connect directly to a quiet 1.5 V supply.

Signal Description

2.6 Real Time Clock Interface

Table 2-6. Real Time Clock Interface

Name Type Description

RTCX1 Special

RTCX2 Special

Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If no external crystal is used, then RTCX1 can be driven with the desired clock rate. Maximum voltage allowed on this pin is 1.2 V.

Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If no external crystal is used, then RTCX2 must be left floating.

Datasheet



32.768 KHz Xtal

10M

VCCRTC

RTCX2

RTCX1

Vbatt

1uF

1 K 

VccDSW3_3 (see note 3)

C1 C2

RTCRST#

1.0 uF

20 K

0.1uF

SRTCRST#

20 K

1.0 uF

Schottky Diodes

Signal Description

2.7 External RTC Circuitry

The PCH implements an internal oscillator circuit that is sensitive to step voltage changes in VccRTC. The following figure shows an example schematic recommended to ensure correct operation of the PCH RTC.

Figure 2-2. Example External RTC Circuit

2.8 Interrupt Interface

Table 2-7. Interrupt Signals

Datasheet 71

Notes:

1. The Reference Designators used in this example are arbitrarily assigned.

2. The exact capacitor values and tolerances for C1 and C2 must be based on the crystal maker recommendations.

3. For platforms not supporting DeepSx, the VccDSW3_3 pins must be connected to the VccSUS3_3 pins.

4. Vbatt is voltage provided by the RTC battery (such as coin cell).

5. VccRTC, RTCX1, RTCX2, RTCRST#, and SRTCRST# are PCH pins.

6. VccRTC powers PCH RTC well.

7. RTCX1 is the input to the internal oscillator.

8. RTCX2 is the amplified feedBack (output) for the external crystal. Important: If a single-ended clock source, such as an oscillator, is used instead of the crystal to generate the RTC frequency, you must

leave pin RTCX2 floating (no connect).

Name Type Description

SERIRQ I/OD Serial Interrupt Request: This pin implements the serial interrupt protocol.

PCI Interrupt Requests: In non-APIC mode, the PIRQx# signals can be routed

to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or 15 as described in Section 5.9.6.

PIRQ[D:A]# I/OD

PIRQ[H:E]# / GPIO[5:2]

Note: PIRQ Interrupts can only be shared if it is configured as level sensitive. They cannot be shared if

configured as edge triggered.

Each PIRQx# line has a separate Route Control register. In APIC mode, these signals are connected to the internal I/O APIC in the

following fashion: PIRQA# is connected to IRQ16, PIRQB# to IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the legacy interrupts.

PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or 15 as described in Section 5.9.6. Each PIRQx# line has a separate Route Control register.

I/OD

In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQE# is connected to IRQ20, PIRQF# to IRQ21, PIRQG# to IRQ 22, and PIR QH # t o IRQ23. Th is frees th e l egacy inte rrupts. If no t needed for interrupts, these signals can be used as GPIO.

Signal Description

2.9 Processor Interface

Table 2-8. Processor Interface Signals

Name Type Description

Keyboard Controller Reset Processor: The keyboard controller can generate

INIT# to the processor. This saves the external OR gate with the PCH’s other

RCIN# I

PROCPWRGD O

PMSYNCH O

PECI I/O Platform Environment Control Interface: Single-wire, serial bus.

THRMTRIP# I

sources of INIT#. When the PCH detects the assertion of this signal, INIT# is generated using a VLW message to the processor. Note: The PCH will ignore RCIN# assertion during transitions to the S3, S4,

and S5 states.

Processor Power Good: This signal should be connected to the processor UNCOREPWRGOOD input to indicate when the processor power is valid.

Power Management Sync: Provides state information from the PCH to the processor.

Thermal Trip: When low, this signal indicates that a thermal trip from the processor occurred, and the PCH will immediately transition to a S5 state. The PCH will not wait for the processor stop grant cycle since the processor has overheated.

2.10 Direct Media Interface (DMI) to Host Controller

Table 2-9. Direct Media Interface Signals

Name Type Description

DMI_TXP0 DMI_TXN0

DMI_RXP0 DMI_RXN0

DMI_TXP1 DMI_TXN1

DMI_RXP1 DMI_RXN1

DMI_TXP2 DMI_TXN2

DMI_RXP2 DMI_RXN2

DMI_TXP3 DMI_TXN3

DMI_RXP3 DMI_RXN3

DMI_RCOMP I

DMI_IREF I Internal Reference Voltage: Connect directly to 1.5 V.

Direct Media Interface Differential Transmit Pair 0: This signal is an output

from the PCH to the processor.

Direct Media Interface Differential Receive Pair 0: This signal is an input to

the PCH from the processor.

Direct Media Interface Differential Transmit Pair 1: This signal is an output

from the PCH to the processor.

Direct Media Interface Differential Receive Pair 1: This signal is an input to

the PCH from the processor.

Direct Media Interface Differential Transmit Pair 2: This signal is an output

from the PCH to the processor.

Direct Media Interface Differential Receive Pair 2: This signal is an input to

the PCH from the processor.

Direct Media Interface Differential Transmit Pair 3: This signal is an output

from the PCH to the processor.

Direct Media Interface Differential Receive Pair 3: This signal is an input to

the PCH from the processor.

Impedance Compensation Input: Connected to a 7.5 K (1%) precision external pull-up resistor to 1.5 V.

Datasheet



Signal Description

2.11 Intel® Flexible Display Interface (Intel® FDI)

Table 2-10. Intel® Flexible Display Interface (Intel® FDI) Signals

Signal Name Type Description

FDI_RXP0 FDI_RXN0

FDI_RXP1 FDI_RXN1

FDI_CSYNC OFDI Composite synchronization signal

FDI_INT O Used for Display interrupts from PCH to processor.

FDI_RCOMP I

FDI_IREF I Internal Reference Voltage: Connected to 1.5 V

FDI Display Link Receive Pair 0

FDI Display Link Receive Pair 1

Impedance Compensation Input: Connected to an external precision resistor (7.5 K ±1%) to 1.5 V

2.12 Analog Display/VGA DAC Signals

Table 2-11. Analog Display Interface Signals

Name Type Description

VGA_RED

VGA_GREEN

VGA_BLUE

DAC_IREF

VGA_HSYNC

VGA_VSYNC

VGA_DDC_CLK

VGA_DDC_DATA

VGA_IRTN

I/OAResistor Set: Set point resistor for the internal color palette DAC. A 649

HVCMOS

I/O

COD

I/O

COD

I/O

COD

RED Analog Video Output: This signal is a VGA Analog video output

from the internal color palette DAC.

GREEN Analog Video Output: This signal is a VGA Analog video output

from the internal color palette DAC.

BLUE Analog Video Output: This signal is a VGA Analog video output

from the internal color palette DAC.

resistor is required between DAC_IREF and motherboard ground.

VGA Horizontal Synchronization: This signal is used as the horizontal sync (polarity is programmable) or “sync interval”. 2.5 V output

VGA Vertical Synchronization: This signal is used as the vertical sync (polarity is programmable). 2.5 V output.

Monitor Control Clock

Monitor Control Data

Monitor Current Return

2.13 Digital Display Signals

Table 2-12. Digital Display Signals (Sheet 1 of 2)

Name Type Description

DDPB_AUXP I/O Port B: DisplayPort* Aux

DDPB_AUXN I/O Port B: DisplayPort Aux Complement

DDPB_HPD I Port B: HPD Hot-Plug Detect

DDPB_CTRLCLK I/O Port B: HDMI* Port B Control Clock.

DDPB_CTRLDATA I/O Port B: HDMI Port B Control Data.

DDPC_AUXP I/O Port C: DisplayPort Aux

Datasheet 73

Signal Description

Table 2-12. Digital Display Signals (Sheet 2 of 2)

Name Type Description

DDPC_AUXN I/O Port C: DisplayPort Aux Complement

DDPC_HPD I Port C: HPD Hot-Plug Detect

DDPC_CTRLCLK I/O Port C:HDMI Port C Control Clock

DDPC_CTRLDATA I/O Port C:HDMI Port C Control Data

DDPD_AUXP I/O Port D: DisplayPort Aux

DDPD_AUXN I/O Port D: DisplayPort Aux Complement

DDPD_HPD I Port D: Hot-Plug Detect

DDPD_CTRLCLK I/O Port D:HDMI Port D Control Clock

DDPD_CTRLDATA I/O Port D:HDMI Port D Control Data

2.14 Embedded DisplayPort* (eDP*) Backlight Control Signals

Note: These signals can be left as No Connect (float) if eDP is not used.

Table 2-13. Embedded DisplayPort* (eDP*) backlight control signals

Name Type Description

eDP_VDDEN I/O

eDP_BKLTEN I/O

eDP_BKLTCTL I/O

eDP* Panel power Enable: Panel power control enable.

This signal is also called VDD_dBL in the CPIS specification and is used to control the VDC source of the panel logic.

eDP Backlight Enable: Panel backlight enable control for eDP. This signal is also called ENA_BL in the CPIS specification and is used to

gate power into the backlight circuitry.

eDP Panel Backlight Brightness control: Panel brightness control for eDP.

This signal also called VARY_BL in the CPIS specification and is used as the PWM Clock input signal

2.15 Intel® High Definition Audio (Intel® HD Audio) Link

Table 2-14. Intel® High Definition Audio (Intel® HD Audio) Link Signals (Sheet 1 of 2)

Name Type Description

Intel

HDA_RST# O

HDA_SYNC O

HDA_BCLK O

HDA_SDO O

High Definition Audio Reset: Master hardware reset to external

codec(s).

Intel

High Definition Audio Sync: 48 kHz fixed rate sample sync to the

codec(s). This signal is also used to encode the stream number.

Intel High Definition Audio Bit Clock Output: 24.000 MHz serial data clock generated by the Intel High Definition Audio controller (the PCH).

Intel High Definition Audio Serial Data Out: Serial TDM data output to the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s for Intel High Definition Audio.

Note: This signal is sampled as a functional strap. See Section 2.18 for

more details. There is a weak integrated pull-down resistor on this pin.

Datasheet



Signal Description

Table 2-14. Intel® High Definition Audio (Intel® HD Audio) Link Signals (Sheet 2 of 2)

Name Type Description

Intel High Definition Audio Serial Data In [3:0]: Serial TDM data

inputs from the codecs. The serial input is single-pumped for a bit rate of

HDA_SDI[3:0] I

HDA_DOCK_EN# /

GPIO33

HDA_DOCK_RST# / GPIO13

24 Mb/s for Intel High Definition Audio. These signals have integrated pulldown resistors, which are always enabled.

Note: During enumeration, the PCH will drive this signal. During normal

operation, the CODEC will drive it.

Intel High Definition Audio Dock Enable: This signal controls the external Intel HD Audio docking isolation logic. This is an active low signal. When de-asserted, the external docking switch is in isolate mode. When asserted, the external docking switch electrically connects the Intel HD

Audio dock signals to the corresponding PCH signals. This signal can instead be used as GPIO33. This signal defaults to GPIO33

mode after PLTRST#. BIOS is responsible for configuring GPIO33 to HDA_DOCK_EN# mode.

Intel High Definition Audio Dock Reset: This signal is a dedicated HDA_RST# signal for the codec(s) in the docking station. Aside from operating independently from the normal HDA_RST# signal, it otherwise works similarly to the HDA_RST# signal.

This signal is shared with GPIO13. This signal defaults to GPIO13 mode after PLTRST#. BIOS is responsible for configuring GPIO13 to HDA_DOCK_RST# mode.

2.16 Low Pin Count (LPC) Interface

Table 2-15. Low Pin Count (LPC) Interface Signals

Name Type Description

LAD[3:0] I/O

LFRAME# O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.

LDRQ0#, LDRQ1# /

GPIO23

LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull-ups are provided.

LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or bus master access. These signals are typically connected to an external Super I/O

device. An internal pull-up resistor is provided on these signals. LDRQ1# may optionally be used as GPIO23.

2.17 General Purpose I/O Signals

The following table summarizes the GPIOs in the PCH. The control for the GPIO signals is handled through an independent 128-byte I/O space. The base offset for this space is selected by the GPIO_BAR register in D31:F0 configuration space. See Section 12.10 for details.

Highlights of GPIO Features

a. GPIO pins powered from DSW: If pin is configured as GPIO then it follows the

SUS well (does not follow DSW) and its content is wiped out when SUS is removed.

b. Only GPIO[31:0] are blink-capable.

c. When the default of a multiplexed GPIO is Native but the desired functionality is

GPIO, care should be taken to ensure the signal is stable until it is initialized to GPIO functionality.

Datasheet 75

Signal Description

d. Glitch-less Output means the signal is ensured to be stable (no glitch) during

power on and when switching mode of operation from Native to GPIO or GPIO to Native. Glitch-less Input means the signal has built-in de-glitch protection that gates the input signal until power has become stable (the input is ignored during this time).

e. The following GPIOs are capable of generating SMI#, SCI, or NMI: GPIO[60, 57,

56, 43, 27, 22, 21, 19, 17, 15:0].

f. GPIO_USE_SEL[31:0], GPIO_USE_SEL2[63:32] and GPIO_USE_SEL3[75:64]

select whether the pin is selected to function as GPIO (GPIO_USE_SEL[x] = 1) or Native (GPIO_USE_SEL[x] = 0). However, the PCH Soft Straps (SPI Flash) take precedence if there is a mismatch with GPIO_USE_SEL.

g. GP_IO_SEL[31:0], GP_IO_SEL[63:32] and GP_IO_SEL[75:64] select whether

the pin is an output (GP_IO_SEL[x] = 0) or an input (GP_IO_SEL[x] = 1). The value written to or reported in this register is invalid when the pin is programmed to Native function.

h. If the corresponding GPIO has been set as an input, and GPI_ROUT has been

programmed for NMI functionality, the GPI_NMI_EN[15:0] is used to allow active-high or active-low NMI events (depending on the polarity selected by GPI_INV[31:0]).

i. All the GP_RST_SEL registers are only resetable by RSMRST#. GPIO

Configuration registers within the Core Well are reset whenever PWROK is deasserted.

j. GPIO Configuration registers within the Suspend Well are reset when RSMRST#

is asserted, CF9h reset (06h or 0Eh), or SYS_RESET# is asserted. However, CF9h reset and SYS_RESET# events can be masked from resetting the Suspend well GPIO by programming appropriate GPIO Reset Select (GPIO_RST_SEL) registers. See Section 12.10 for details.

k. GPIO24 is an exception to the other GPIO Signals in the Suspend Well and is not

reset by CF9h reset (06h or 0Eh)

Table 2-16. General Purpose I/O Signals (Sheet 1 of 5)

Name

GPIO0 Core GPI Yes No No Multiplexed with BMBUSY#.

GPIO1 Core GPI Yes Yes No

GPIO2

(Note 8)

GPIO3

(Note 8)

GPIO4

(Note 8)

GPIO5

(Note 8)

GPIO6 Core GPI Yes Yes No

GPIO7 Core GPI Yes Yes No

GPIO8 Sus GPO Yes No No Unmultiplexed.

GPIO9 Sus Native Yes No No

Power

Well

Core GPI Yes No No

Default

(Note 2)

GPI Event

Glitch-less

Input Output

Desktop and Mobile: Available as GPIO1 only (Note 4). Server: Multiplexed with TACH1.

Multiplexed PIRQE#.

Multiplexed PIRQF#.

Multiplexed PIRQG#.

Multiplexed PIRQH#.

Desktop and Mobile: Available as GPIO6 only (Note 4). Server: Multiplexed with TACH2.

Desktop and Mobile: Available as GPIO7 only (Note 4). Server: Multiplexed with TACH3.

Multiplexed with OC5#. When configured as GPIO, default direction is Input (GPI).

Description

Datasheet



Signal Description

Table 2-16. General Purpose I/O Signals (Sheet 2 of 5)

Name

GPIO10 Sus Native Yes No No

GPIO11 Sus Native Yes Yes No

GPIO12

GPIO13

GPIO14 Sus Native Yes No No

GPIO15 Sus GPO Yes No Yes Unmultiplexed.

GPIO16 Core GPI No No No

GPIO17 Core GPI Yes Yes No

GPIO18 Core Native No No No

GPIO19

(Note 5)

GPIO20 Core Native No No No

GPIO21 Core GPI Yes No No Multiplexed with SATA0GP.

GPIO22 Core GPI Yes No No Multiplexed with SCLOCK.

GPIO23 Core Native No No No Multiplexed with LDRQ1#.

GPIO24

(Note 1)

GPIO25 Sus Native No No No

GPIO26 Sus Native No No No

Power

Well

DSW

(Note 9)

Sus

(Note

12)

Core GPI Yes No No

Sus GPO No No Yes

Default

(Note 2)

Native Yes No No

GPI Yes No No

GPI Event

Glitch-less

Input Output

Description

Multiplexed with OC6#. When configured as GPIO, default direction is Input (GPI).

Multiplexed with SMBALERT#. When configured as GPIO, default direction is Input (GPI).

Multiplexed with LAN_PHY_PWR_CTRL. GPIO / Native functionality is controlled using soft strap. When configured as GPIO, default direction is Output (GPO).

(Note 11)

Mobile: Multiplexed with HDA_DOCK_RST#. Desktop: Available as GPIO13 only (Note 4).

Multiplexed with OC7#. When configured as GPIO, default direction is Input (GPI).

Multiplexed with SATA4GP. (Note 11)

Desktop and Mobile: Available as GPIO17 only (Note 4). Server: Multiplexed with TACH0.

Multiplexed with PCIECLKRQ1#. External pull-up resistor required for Native function.

When configured as GPIO, default direction is Output (GPO).

Multiplexed with SATA1GP.

Multiplexed with PCIECLKRQ2#. External pull-up resistor required for Native function.

When configured as GPIO, default direction is Output (GPO).

Server: Also available as SMI# (Note 18).

Unmultiplexed.

Multiplexed with PCIECLKRQ3#. External pull-up resistor required for Native function.

When configured as GPIO, default direction is Output (GPO).

Multiplexed with PCIECLKRQ4#. External pull-up resistor required for Native function.

When configured as GPIO, default direction is Output (GPO).

Datasheet 77

Table 2-16. General Purpose I/O Signals (Sheet 3 of 5)

Signal Description

Name

GPIO27

GPIO28 Sus GPO No No Yes Unmultiplexed.

GPIO29

GPIO30

(Note 9)

GPIO31

(Note 3)

GPIO32 Core GPO No No No

GPIO33

(Note 5)

GPIO34 Core GPI No No No Unmultiplexed.

GPIO35 Core GPO No No Yes

GPIO36

(Note 5)

GPIO37

(Note 5)

GPIO38 Core GPI No No No Multiplexed with SLOAD.

GPIO39 Core GPI No No No Multiplexed with SDATAOUT0.

GPIO40 Sus Native No No No

Power

Well

DSW

(Note 9)

DSW

(Note 9)

Sus Native No No Yes

DSW

(Note 9)

Core GPO No No No

Core GPI No No No

Default

(Note 2)

GPI No No No

Native No No Yes

GPI No No Yes

GPI Event

Glitch-less

Input Output

Description

Unmultiplexed. Can be configured as wake input to allow wakes from Deep Sx but, since the pin is shared, the PCH counts on this pin remaining asserted until PLTRST# deasserts or the PCH may latch the pin assertion as a LAN wake request.

• Intel LAN Present: This pin is connected to the LANWAKE# pin on the LAN PHY, is used to signal a ME or host wake to the PCH. The pin may also be driven by the platform to cause a host wake, but it must be de-asserted whenever PLTRST# is de-asserted and may only be used to wake the host (GPIO27 wake enable must always be set).

• No Intel LAN Present: This pin does not have a specific usage model for connection on the board, but allows the OEM/ODM customers a custom method to wake from Deep Sx.

Multiplexed with SLP_WLAN#. GPIO / Native functionality is controlled using soft strap.

When configured as GPIO, default direction is Output (GPO).

(Note 11, 15)

Multiplexed with SUSPWRDNACK, SUSWARN#. SUSPWRDNACK mode is the default mode of operation. If the system supports Deep Sx, then subsequent boots will default to SUSWARN# mode. (Note 23)

When configured as GPIO, default direction is Input (GPI).

Notes:

1. Toggling this pin at a frequency higher than 10 Hz is not supported.

2. Desktop: GPIO_USE_SEL[31] is internally hardwired to a 1b, which means GPIO mode is permanently selected and cannot be changed.

3. Mobile: This GPIO pin is permanently appropriated by the ME as MGPIO2 for ACPRESENT function (not available as a true GPIO).

Desktop: Available as GPIO32 only (Note 4). Mobile: GPIO_USE_SEL2[0] is internally hardwired to a

0b, which means Native mode is permanently selected and cannot be changed (not available as GPIO). External pull-up to Core well is required for CLKRUN#.

Desktop: Available as GPIO33 only (Note 4). Mobile: Also available as HDA_DOCK_EN#.

Desktop and Mobile: Available as GPIO35 only (Note 4). Server: Also available as NMI#.

Multiplexed with SATA2GP.

Multiplexed with SATA3GP.

Multiplexed with OC1#. When configured as GPIO, default direction is Input (GPI).

Datasheet



Signal Description

Table 2-16. General Purpose I/O Signals (Sheet 4 of 5)

Name

GPIO41 Sus Native No No No

GPIO42 Sus Native No No No

GPIO43 Sus Native Yes No No

GPIO44 Sus Native No No No

GPIO45 Sus Native No No No

GPIO46 Sus Native No No No

GPIO47 Sus Native No No No

GPIO48 Core GPI No No No Multiplexed with SDATAOUT1.

GPIO49 Core GPI No Yes No

GPIO50 Core GPI No No No Unmultiplexed.

GPIO51

(Note 5)

GPIO52 Core GPI No No No Unmultiplexed.

GPIO53

(Note 5)

GPIO54 Core GPI No No No Unmultiplexed.

GPIO55

(Note 5)

GPIO56 Sus Native Yes No No

GPIO57 Sus GPI Yes No Yes

GPIO58 Sus Native No Yes No

GPIO59 Sus Native No No No

GPIO60 Sus Native Yes Yes No

GPIO61 Sus Native No No Yes

GPIO62

(Note 5)

Power

Well

Core GPO No No No

Sus Native No No No

Default

(Note 2)

GPI Event

Glitch-less

Input Output

Description

Multiplexed with OC2#. When configured as GPIO, default direction is Input (GPI).

Multiplexed with OC3#. When configured as GPIO, default direction is Input (GPI).

Multiplexed with OC4#. When configured as GPIO, default direction is Input (GPI).

Multiplexed with PCIECLKRQ5#. External pull-up resistor required for Native function.

When configured as GPIO, default direction is Input (GPI).

Multiplexed with PCIECLKRQ6#. External pull-up resistor required for Native function.

When configured as GPIO, default direction is Input (GPI).

Multiplexed with PCIECLKRQ7#. External pull-up resistor required for Native function.

When configured as GPIO, default direction is Input (GPI).

Desktop and Server: This pin is not available in the package as GPIO or Native.

Mobile: Multiplexed with PEG_A_CLKRQ#.

Multiplexed with SATA5GP. (Note 11)

Unmultiplexed.

Desktop and Server: This pin is not available in the package as GPIO or Native.

Mobile: Multiplexed with PEG_B_CLKRQ#.

Unmultiplexed. Can be re-purposed for NFC interface input.

(Note 10)

Multiplexed with SML1CLK. When configured as GPIO, default direction is Input (GPI).

Multiplexed with OC0#. When configured as GPIO, default direction is Input (GPI).

Multiplexed with SML0ALERT#. When configured as GPIO, default direction is Input (GPI).

Multiplexed with SUS_STAT#. When configured as GPIO, default direction is Output

(GPO).

Multiplexed with SUSCLK (Note 13). When configured as GPIO, default direction is Output

(GPO).

Datasheet 79

Table 2-16. General Purpose I/O Signals (Sheet 5 of 5)

Signal Description

Name

GPIO63 Sus Native No No Yes

GPIO64 Core Native No No No

GPIO65 Core Native No No No

GPIO66 Core Native No No No

GPIO67 Core Native No No No

GPIO68 Core GPI No Yes No

GPIO69 Core GPI No Yes No

GPIO70 Core Native No Yes No

GPIO71 Core Native No Yes No

GPIO72

GPIO73 Sus Native No No No

GPIO74 Sus Native No Yes No

GPIO75 Sus Native No Yes No

Power

Well

DSW

(Note 9)

Default

(Note 2)

Native No No No

GPI Event

Glitch-less

Input Output

Description

Multiplexed with SLP_S5#. When configured as GPIO, default direction is Output

(GPO).

Multiplexed with CLKOUTFLEX0. When configured as GPIO, default direction is Output

(GPO).

Multiplexed with CLKOUTFLEX1. When configured as GPIO, default direction is Output

(GPO).

Multiplexed with CLKOUTFLEX2. When configured as GPIO, default direction is Output

(GPO).

Multiplexed with CLKOUTFLEX3. When configured as GPIO, default direction is Output

(GPO).

Desktop and Mobile: Available as GPIO68 only (Note 4). Server: Multiplexed with TACH4.

Desktop and Mobile: Available as GPIO69 only (Note 4). Server: Multiplexed with TACH5.

Desktop and Mobile: Available as GPIO70 only (Note 4). Server: Multiplexed with TACH6.

(Note 11)

Desktop and Mobile: Available as GPIO71 only (Note 4). Server: Multiplexed with TACH7.

(Note 11)

Desktop: Available as GPIO72 only (Note 4). Mobile: Also available as BATLOW#. Requires external pull-up resistor to DSW well.

Multiplexed with PCIECLKRQ0#. External pull-up resistor required for Native function. When configured as GPIO, default direction is Input (GPI).

Multiplexed with SML1ALERT#/TEMP_ALERT#. When configured as GPIO, default direction is Input (GPI).

Can be re-purposed for NFC interface input. (Note 10, 11, 21)

Multiplexed with SML1DATA. When configured as GPIO, default direction is Input (GPI).

Notes:

1. GPIO[24] register bits are not cleared by CF9h reset by default, it is programmable through GP_RST_SEL[24]

2. Internal pull-up or pull-down may be present when Native functionality is selected. Refer to Tab le 3 -1 for

more details.

3. Internal pull-down resistor may be enabled in Deep Sx mode based on DSX_CFG configuration bit, as

follows: ‘1’ (pin will be driven by platform in Deep Sx) -> Z; - ‘0’ (pin will NOT be driven by platform in Deep Sx) -> Internal pull-down. Refer to DSX_CFG register (RCBA+3334h) for more details.

4. For pins that are available as GPIO-only: if the power-on default is Native, BIOS is still required to configure

the pin as GPIO by writing to the pin’s GPIO_USE_SEL register, even though the pin is only available as GPIO.

5. A functional strap also exists on this pin.

6. Glitch-less Inputs are ensured, by circuit design, to de-glitch the input. Glitch-less Outputs are ensured, by

circuit design, to not generate any glitches on the output during power-on.

7. The GPIO pins which are capable of generating NMI message when it is configured as input, its GPI_ROUT

register is configured NMI functionality and its corresponding GPI NMI Enable (GNE) bit is set. NMI event is positive edge trigger based on the signal and after GPI Inversion logic.

Datasheet



Signal Description

8. When GPIO[5:2] are configured as output GPIOs, they behave in an open drain manner.

9. This SUS well pin will be controlled by DSW logic. GPIO functionality is only available when the SUS well is powered.

10. GPIO 74 or GPIO 57 can be used for NFC on a platform. The NFC option can be set through FITC in ME configuration settings.

11. For GPIOs where GPIO versus Native Mode is configured using SPI Soft Strap, the corresponding GPIO_USE_SEL bits for these GPIOs have no effect. The GPIO_USE_SEL bits for these GPIOs may change to reflect the Soft-Strap configuration even though GPIO Lockdown Enable (GLE) bit is set.

12. GPIO13 is located in the HDA Suspend well. It can only be used if VccsusHDA is powered.

13. GPIO62 defaults as Native SUSCLK. If this pin is to be configured as GPIO, it is required that the board ensure that the 32.768 kHz toggle rate does not affect the receiving logic of the pin until it is set as GPIO.

14. When switching from GPIO at logic 1 to the native functionality, the pin must not glitch low.

15. A soft strap (PMC_SOFT_STRAP_2 register[7] GP23MGPIO3_SLPWLAN_SEL) to enable switching between SLP_WLAN# (default) or GP29/MPGIO3. By default the strap is 0b, which enables the SLP_WLAN# pin function when sus well is up. When soft strap is loaded and value is 1b, the pin returns to its regular GPIO or MGPIO mode while SLP_WLAN# function no longer exists. Also take into account of note 11.

16. GPIO72 will default to mobile (native) until determining if this is mobile or desktop/server SKU.

17. GPIO may toggle until after

18. When strapped as SMI#, the pin is automatically configured as open drain. The SMI# function is only available in server/workstation SKU. The SMI# function is not the same as the SMI# events that the GPIOs can be configured to generate, as described in GPI_ROUT and ALT_GPI_SMI_EN.

19. N/A

20. N/A

21. The choice of which native mode, SML1ALERT# or TEMP_ALERT#, is determined by a soft strap.

22. N/A

23. SUSPWRDNACK Mode is the default mode of operation. If the system supports DeepSx, then subsequent boots will default to SUSWARN# mode.

2.18 Functional Straps

The PCH implements hardware functional straps that are used to configure specific functions within the PCH and processor very early in the boot process, before BIOS or software intervention. Some are sampled at the rising edge of PWROK, while others at the rising edge of RSMRST# to select configurations (except as noted), and then revert later to their normal usage. When Descriptor Mode is enabled, the PCH will read Soft Strap data out of the SPI device prior to the de-assertion of reset to both the Intel Management Engine and the Host system. In some cases, the soft strap data may override the hardware functional straps. See Section 5.26.2 for information on Descriptor Mode.

Datasheet 81

Table 2-17. Functional Strap Definitions (Sheet 1 of 3)

Bit11 Bit 10 Boot BIOS

Destination

01 Reserved

10 Reserved

11 SPI (default)

00 LPC

Bit11 Bit 10 Boot BIOS

Destination

01 Reserved

10 Reserved

11 SPI (default)

00 LPC

Signal Usage When Sampled Comment

This signal has a weak internal pull-up. This field determines the destination of accesses to the BIOS

memory range. Also controllable using Boot BIOS Destination bit (Chipset Config Registers: Offset 3410h:Bit 10). This strap is used in conjunction with Boot BIOS Destination Selection 1 strap.

Signal Description

SATA1GP /

GPIO19

GPIO51

SATA2GP /

GPIO36

Boot BIOS Strap

bit 0

(BBS0)

Boot BIOS Strap

bit 1

(BBS1)

DMI RX

Termination

Rising edge of

PWROK

Rising edge of

PWROK

Rising edge of

PWROK

Notes:

1. The internal pull-up is disabled after PLTRST# de-asserts.

2. If option 00 (LPC) is selected, BIOS may still be placed on LPC, but the platform is required to have SPI flash connected directly to the PCH SPI bus with a valid descriptor in order to boot.

3. Boot BIOS Destination Select to LPC/PCI by functional strap or using Boot BIOS Destination Bit will not affect SPI accesses initiated by Intel ME or Integrated GbE LAN.

4. See Section 10.1.49 for additional information.

5. This signal is in the Core well.

This signal has a weak internal pull-up. This field determines the destination of accesses to the BIOS

memory range. Also controllable using Boot BIOS Destination bit (Chipset Config Registers: Offset 3410h:Bit 11). This strap is used in conjunction with Boot BIOS Destination Selection 0 strap.

Notes:

1. The internal pull-up is disabled after PLTRST# de-asserts.

2. If option 00 (LPC) is selected, BIOS may still be placed on LPC, but the platform is required to have SPI flash connected directly to the PCH's SPI bus with a valid descriptor in order to boot.

3. Boot BIOS Destination Select to LPC/PCI by functional strap or using Boot BIOS Destination Bit will not affect SPI accesses initiated by Intel ME or Integrated GbE LAN.

4. See Section 10.1.49 for additional information.

5. This signal is in the Core well.

This signal has a weak internal pull-down. This signal only takes effect if DMI is configured in AC-coupled

mode (server/workstation only). 0 = DMI RX is terminated to VSS.

1 = DMI RX is terminated to VCC/2.

Notes:

1. The internal pull-down is disabled after PLTRST# deasserts.

2. If DMI is operating in DC-coupled mode (such as Client applications), then DMI RX is terminated to VSS and the value of this strap is ignored by the PCH and does not take effect.

3. This signal is in the Core well.

Datasheet



Signal Description

Table 2-17. Functional Strap Definitions (Sheet 2 of 3)

Signal Usage When Sampled Comment

This signal has a weak internal pull-down. 0 = Disable Intel ME Crypto Transport Layer Security (TLS)

cipher suite (no confidentiality).

1 = Enable Intel ME Crypto Transport Layer Security (TLS)

SATA3GP /

GPIO37

HDA_SDO Reserved

HDA_DOCK_EN# /

GPIO33

INTVRMEN

GPIO62 / SUSCLK

DSWVRMEN

SPKR No Reboot

TLS Confidentiality

Integrated VRM

PLL On-Die Voltage

Regulator Enable

DeepSx Well On-

Regulator Enable

Reserved

Enable

Die Voltage

Rising edge of

PWROK

Rising edge of

PWROK

Rising edge of

PWROK

Always

Rising edge of

RSMRST#

Always

Rising edge of

PWROK

cipher suite (with confidentiality). Must be pulled up to support Intel Business Advantage) with TLS.

Notes:

1. The internal pull-down is disabled after PLTRST# deasserts.

2. This signal is in the Core well.

This signal has a weak internal pull-down.

Notes:

1. The internal pull-down is disabled after PLTRST# deasserts.

2. This signal is in the Suspend well.

This signal has a weak internal pull-down.

Notes:

1. The internal pull-down is disabled after PLTRST# deasserts.

2. This signal is in the Core well.

This signal does not have an internal resistor; an external resistor is required.

0 = DCPSUS1, DCPSUS2 and DCPSUS3 are powered from an

external power source (should be connected to an external VRM). External VR powering option is for Mobile Only; Desktop/Server/Workstation should not pull the strap low.

1 = Integrated VRMs enabled. DCPSUS1, DCPSUS2 and

DCPSUS3 can be left as No Connect.

Notes:

1. This signal is always sampled.

2. This signal is in the RTC well.

This signal has a weak internal pull-up. 0 = Disable PLL On-Die voltage regulator.

1 = Enable PLL On-Die voltage regulator.

Notes:

1. The internal pull-up is disabled after RSMRST# de-asserts.

2. This signal is in the Suspend well.

This signal does not have an internal resistor; an external resistor is required.

0 = Disable Integrated DeepSx Well (DSW) On-Die Voltage

Regulator. This mode is only supported for testing environments.

1 = Enable DSW 3.3 V-to-1.05 V Integrated DeepSx Well

(DSW) On-Die Voltage Regulator. This must always be pulled high on production boards.

Notes:

1. This signal is always sampled.

2. This signal is in the RTC well.

The signal has a weak internal pull-down. 0 = Disable “No Reboot” mode.

1 = Enable “No Reboot” mode (PCH will disable the TCO Timer

system reboot feature). This function is useful when running ITP/XDP.

Notes:

1. The internal pull-down is disabled after PLTRST# deasserts.

2. The status of this strap is readable using the NO REBOOT bit (Chipset Config Registers: RCBA + Offset 3410h:Bit 5).

3. See

4. This signal is in the Core well.

Section 10.1.49 for additional information.

AMT with TLS and Intel SBA (Small

Datasheet 83

Table 2-17. Functional Strap Definitions (Sheet 3 of 3)

Signal Usage When Sampled Comment

This signal has a weak internal pull-up.

GPIO53 Reserved

GPIO55 Top Swap Override

DDPB_CTRLDATA Port B Detected

DDPC_CTRLDATA Port C Detected

DDPD_CTRLDATA Port D Detected

Rising edge of

PWROK

Rising edge of

PWROK

Rising edge of

PWROK

Rising edge of

PWROK

Rising edge of

PWROK

Notes:

1. The internal pull-up is disabled after PLTRST# de-asserts.

2. This signal is in the Core well.

The signal has a weak internal pull-up. 0 = Enable “Top Swap” mode.

1 = Disable “Top Swap” mode.

Notes:

1. The internal pull-up is disabled after PLTRST# de-asserts.

2. Software will not be able to clear the Top Swap mode bit until the system is rebooted.

3. The status of this strap is readable using the Top Swap bit (Chipset Config Registers: RCBA + Offset 3414h:Bit 0).

4. This signal is in the Core well.

This signal has a weak internal pull-down. 0 = Port B is not detected.

1 = Port B is detected.

Notes:

1. The internal pull-down is disabled after PLTRST# deasserts.

2. This signal is in the Core well.

This signal has a weak internal pull-down. 0 = Port C is not detected.

1 = Port C is detected.

Notes:

1. The internal pull-down is disabled after PLTRST# deasserts.

2. This signal is in the Core well.

This signal has a weak internal pull-down. 0 = Port D is not detected.

1 = Port D is detected.

Notes:

1. The internal pull-down is disabled after PLTRST# deasserts.

2. This signal is in the Core well.

Signal Description

Note: See Section 3.1 for full details on pull-up/pull-down resistors.

2.19 SMBus Interface

Table 2-18. SMBus Interface Signals

Name Type Description

SMBDATA I/OD SMBus Data: External pull-up resistor is required.

SMBCLK I/OD SMBus Clock: External pull-up resistor is required.

SMBALERT# / GPIO11

SMBus Alert: This signal is used to wake the system or generate SMI#.

This signal may be used as GPIO11.

Datasheet



Signal Description

2.20 System Management Interface

Table 2-19. System Management Interface Signals

Name Type Description

INTRUDER# I

SML0DATA I/OD

SML0CLK I/OD

SML0ALERT# / GPIO60

SML1ALERT# / TEMP_ALERT# / GPIO74

SML1CLK / GPIO58

SML1DATA / GPIO75

Intruder Detect: This signal can be set to disable the system if box detected

open. This signal status is readable, so it can be used like a GPI if the Intruder Detection is not needed.

System Management Link 0 Data: SMBus link to external PHY. External pullup is required.

System Management Link 0 Clock: SMBus link to external PHY. External pull-up is required.

SMLink Alert 0: Output of the integrated LAN controller to external PHY. External pull-up resistor is required.

O OD

This signal can instead be used as GPIO60.

SMLink Alert 1: Alert for the ME SMBus controller to optional Embedded Controller or BMC. A soft-strap determines the native function SML1ALERT# or TEMP_ALERT# usage. When soft-strap is 0, function is SML1ALERT#, when

O OD

soft-strap is 1, function is TEMP_ALERT#. This pin can also be set to function as GPIO74.

External pull-up resistor is required on this pin.

System Management Link 1 Clock: SMBus link to optional Embedded Controller or BMC. External pull-up resistor is required.

I/OD

This signal can instead be used as GPIO58.

System Management Link 1 Data: SMBus link to optional Embedded Controller or BMC. External pull-up resistor is required.

I/OD

This signal can instead be used as GPIO75.

2.21 Controller Link

Table 2-20. Controller Link Signals

Signal Name Type Description

CL_RST# O

CL_CLK I/O

CL_DATA I/O

Controller Link Reset: Controller Link reset that connects to a Wireless

LAN Device supporting Intel Active Management Technology. This signal is in the Suspend power well.

Controller Link Clock: Bi-directional clock that connects to a Wireless LAN Device supporting Intel Active Management Technology. This signal is in the Suspend power well.

Controller Link Data: Bi-directional data that connects to a Wireless LAN Device supporting Intel Active Management Technology. This signal is in the Suspend power well.

2.22 Serial Peripheral Interface (SPI)

Table 2-21. Serial Peripheral Interface (SPI) Signals (Sheet 1 of 2)

Name Type Description

SPI_CLK O

SPI_CS0# O

SPI_CS1# O

SPI Clock: SPI clock signal, during idle the bus owner will drive the clock

signal low. Supported frequencies are 20 MHz, 33 MHz and 50 MHz.

SPI Chip Select 0: Used to select the primary SPI Flash device. Note: This signal cannot be used for any other type of device than SPI Flash.

SPI Chip Select 1: Used to select an optional secondary SPI Flash device. Note: SPI_CS0# cannot be used for any other type of device than SPI Flash.

Datasheet 85

Table 2-21. Serial Peripheral Interface (SPI) Signals (Sheet 2 of 2)

Name Type Description

SPI Chip Select 2: Used to select the TPM device if it is connected to the SPI

SPI_CS2# O

SPI_MOSI I/O

SPI_MISO I/O

SPI_IO2 I/O

SPI_IO3 I/O

interface, it cannot be used for any other type of device than TPM. Note: TPM can be configured through soft straps to operate over LPC or SPI,

but no more than 1 TPM is allowed in the system.

SPI Master OUT Slave IN: Defaults as a data output pin for PCH in Dual Output Fast Read mode. Can be configured with a soft strap as a bidirectional signal (SPI_IO0) to support the new Dual I/O Fast Read, Quad I/O Fast Read and Quad Output Fast Read modes.

SPI Master IN Slave OUT: Defaults as a data input pin for PCH in Dual Output Fast Read mode. Can be configured with a soft strap as a bidirectional signal (SPI_IO1) to support the new Dual I/O Fast Read, Quad I/O Fast Read and Quad Output Fast Read modes.

SPI Data I/O: A bidirectional signal used to support the new Dual  I/O Fast Read, Quad I/O Fast Read and Quad Output Fast Read modes. This signal is not used in Dual Output Fast Read mode.

2.23 Manageability Signals

Signal Description

The following signals can be optionally used by the Intel ME supported applications and appropriately configured by Intel Management Engine Firmware. When configured and used as a manageability function, the associated host GPIO functionality is no longer available. If the manageability function is not used in a platform, the signal can be used as a host General Purpose I/O or a native function.

The manageability signals are referred to as Management Engine GPIO pins (MGPIO pins), which are GPIO pins that can be controlled through Intel ME FW.

Table 2-22. MGPIO Conversion Table

MGPIO GPIO Well Default Usage

024SUS –

130SUS SUSWARN# or SUSPWRDNACK

231SUS ACPRESENT

329SUS SLP_WLAN#

460SUS SML0ALERT#

5 57 SUS Required for NFC (assumes GPIO74 is not setup for NFC)

6 27 DSW Intel ME Wake Input

728SUS –

874SUS

916MAIN SATA4GP#

10 49 MAIN SATA5GP#

11 58 SUS SML1CLK

12 75 SUS SML1DATA

Required for NFC (assumes GPIO 57 is not setup for NFC)

SML1ALERT#/TEMP_ALERT# or

Note: The information in the Default Usage column is not for server platforms. For

information on server manageability signals, see Table 2-24.

Datasheet



Signal Description

Table 2-23. Client Manageability Signals

Name Type

MGPIO6 I/O DSW

Power

Well

Can be configured as a wake input for the Intel ME. This pin is implemented in the DSW in order to allow wakes from the DeepSx state. This pin does not have a specific usage model for connection on the board, but allows the OEM/ODM customers a custom method to wake from DeepSx.

Description

Table 2-24. Server Manageability Signals

Name Type

MGPIO2 I/O SUS SMBALERT# signal from PSU to PCH. This signal indicates the

MGPIO0, MGPIO1, MGPIO2, MGPIO3, MGPIO4, MGPIO5, MGPIO6, MGPIO7, MGPIO8

I/O See

Power

Well

Table 2-22

Description

PSU may cause a system shutdown due to a momentary loss of AC input voltage or an over-temperature condition.

Intel ME Firmware Recovery Mode Strap. These signals are inputs to the PCH to force Intel ME to stay in recovery boot loader.

Note: See Table 2-22 for the MGPIO conversion table.

2.24 Power Management Interface

Table 2-25. Power Management Interface Signals (Sheet 1 of 4)

Name Type Description

ACPRESENT: This input pin indicates when the platform is plugged into AC

power or not. In addition to the previous Intel ME to EC communication, the PCH uses this information to implement the DeepSx policies. For example, the pl atform m ay be configu re d to enter D ee pSx when in S4 or S5 and only

ACPRESENT

/ GPIO31

APWROK I

BATLOW# / GPIO72 I

BMBUSY#

/ GPIO0

CLKRUN# (Mobile Only) / GPIO32 (Desktop Only)

when running on battery. This is powered by DeepSx Well.

Note: This signal is muxed with GPIO31 but GPIO_USE_SEL[31] is

I/O

internally hardwired to a 1b, which means GPIO mode is permanently selected and cannot be changed.

Mobile: This GPIO pin is permanently appropriated by the Intel ME as MGPIO2 for ACPRESENT function.

Desktop: This pin is only GPIO31, ACPRESENT is not supported.

Active Sleep Well (ASW) Power OK: When asserted, this signal indicates that power to the ASW sub-system is stable.

Battery Low: This signal is available in Mobile package only. An input from the battery to indicate that there is insufficient power to boot the system. Assertion will prevent wake from S3–S5 state. This signal can also be enabled to cause an SMI# when asserted. For the Mobile package, this signal is multiplexed with GPIO72. In the Desktop package, this signal is only available as GPIO72. This signal must be tied high to the VCCDSW3_3, which will be tied to VccSUS3_3 on DeepSx disabled platforms.

Note: See Table 2-16 for Desktop implementation pin requirements.

Bus Master Busy: Generic bus master activity indication driven into the PCH. This signal can be configured to set the PM1_STS.BM_STS bit. The signal can also be configured to assert indications transmitted from the PCH to the processor using the PMSYNCH pin.

LPC Clock Run: This signal is used to support LPC CLKRUN protocol. It connects to peripherals that need to request clock restart or prevention of clock stopping. Not available in Desktop.

Datasheet 87

Table 2-25. Power Management Interface Signals (Sheet 2 of 4)

Name Type Description

DPWROK: Power OK Indication for the VccDSW3_3 voltage rail. This input

DPWROK I

DRAMPWROK OD O

LAN_PHY_PWR_CT RL / GPIO12

PLTRST# O

PLTRST_PROC# O

PWRBTN# I

PWROK I

RI# I

RSMRST# I

SLP_A# O

SLP_LAN# O

is tied together with RSMRST# on platforms that do not support DeepSx. This signal is in the RTC well.

DRAM Power OK: This signal should connect to the processor’s SM_DRAMPWROK pin. The PCH asserts this pin to indicate when DRAM power is stable.

This pin requires an external pull-up.

LAN PHY Power Control: LAN_PHY_PWR_CTRL should be connected to LAN_DISABLE_N on the PHY. PCH will drive LAN_PHY_PWR_CTRL low to put the PHY into a low power state when functionality is not needed.

Notes:

1. LAN_PHY_PWR_CTRL can only be driven low if SLP_LAN# is deasserted.

2. Signal can instead be used as GPIO12.

Platform Reset: The PCH asserts PLTRST# to reset devices on the platform (such as SIO, FWH, LAN, processor, and so on). The PCH asserts PLTRST# during power-up and when S/W initiates a hard reset sequence through the Reset Control register (I/O port CF9h). The PCH drives PLTRST# active a minimum of 1 ms when initiated through the Reset Control register (I/O port CF9h).

Note: PLTRST# is in the VccSUS3_3 well.

Platform Reset Processor: A 1.0 V copy of PLTRST# pin. This signal is the main host platform reset and should directly connect to the processor pin PLTRSTIN#. No on-board logic is required to level shift the voltage of this signal.

Power Button: The Power Button will cause SMI# or SCI to indicate a system request to go to a sleep state. If the system is already in a sleep state, this signal will cause a wake event. If PWRBTN# is pressed for more than 4 seconds, this will cause an unconditional transition (power button override) to the S5 state. Override will occur even if the system is in the S1–S4 states. This signal has an internal pull-up resistor and has an internal 16 ms de-bounce on the input. This signal is in the DSW well.

Power OK: When asserted, PWROK is an indication to the PCH that all of its core power rails have been stable for at least 5 ms. PWROK can be driven asynchronously. When PWROK is negated, the PCH asserts PLTRST#.

Notes:

1. It is required that the power rails associated with PCI/PCIe (typically the 3.3 V, 5 V, and 12 V core well rails) have been valid for 99 ms prior to PWROK assertion in order to comply with the 100 ms PCI 2.3/ PCIe* 2.0 specification on PLTRST# de-assertion.

2. PWROK must not glitch, even if RSMRST# is low.

Ring Indicate: This signal is an input from a modem. It can be enabled as a wake event, and this is preserved across power failures.

Resume Well Reset: This signal is used for resetting the resume power plane logic. This signal must be asserted for at least t201 after the suspend power wells are valid. When de-asserted, this signal is an indication that the suspend power wells are stable.

SLP_A#: This signal is used to control power to the active sleep well (ASW) of the PCH.

LAN Sub-System Sleep Control: When SLP_LAN# is de-asserted, it indicates that the PHY device must be powered. When SLP_LAN# is asserted, power can be shut off to the PHY device. SLP_LAN# will always be de-asserted in S0 and anytime SLP_A# is de-asserted.

Signal Description

Datasheet



Signal Description

Table 2-25. Power Management Interface Signals (Sheet 3 of 4)

Name Type Description

WLAN Sub-System Sleep Control: When SLP_WLAN# is asserted, power

can be shut off to the external wireless LAN device. SLP_WLAN# will always

SLP_WLAN#/ GPIO29

SLP_S3# O

SLP_S4# O

SLP_S5# / GPIO63 O

SLP_SUS# O

SUSACK# I

SUS_STAT# / GPIO61

SUSCLK /GPIO62 O

SUSWARN# /

SUSPWRDNACK / GPIO30

will be de-asserted in S0.

Note: The selection between native and GPIO mode is based on a soft

strap. The soft strap default is '0', SLP_WLAN# mode. Even though the pin is in the deep sleep well (DSW), the native and GPIO functionality is only available when the SUS well is powered. Set soft strap to ‘1’ to use the GPIO mode.

S3 Sleep Control: SLP_S3# is for power plane control. This signal shuts off power to all non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.

S4 Sleep Control: SLP_S4# is for power plane control. This signal shuts power to all non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state.

Note: This pin must be used to control the DRAM power in order to use

the PCH’s DRAM power-cycling feature.

S5 Sleep Control: SLP_S5# is for power plane control. This signal is used to shut power off to all non-critical systems when in the S5 (Soft Off) states.

This pin may also be used as GPIO63.

DeepSx Indication: When asserted (driven low), this signal indicates the PCH is in DeepSx state where internal Sus power is shut off for enhanced power saving. When de-asserted (driven high), this signal indicates exit from DeepSx state and Sus power can be applied to PCH. If DeepSx is not supported, this pin can be left unconnected.

This pin is in the DSW power well.

SUSACK#: If DeepSx is supported, the EC/motherboard controlling logic must change SUSACK# to match SUSWARN# once the EC/motherboard controlling logic has completed the preparations discussed in the description for the SUSWARN# pin.

Note: SUSACK# is only required to change in response to SUSWARN# if

DeepSx is supported by the platform.

This pin is in the Sus power well.

Suspend Status: This signal is asserted by the PCH to indicate that the system will be entering a low power state soon. This can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes.

This pin may also be used as GPIO61.

Suspend Clock: This clock is an output of the RTC generator circuit to use by other chips for refresh clock.

This pin may also be used as GPIO62.

SUSWARN#: This pin asserts low when the PCH is planning to enter the DeepSx power state and remove Suspend power (using SLP_SUS#). The EC/motherboard controlling logic must observe edges on this pin, preparing for SUS well power loss on a falling edge and preparing for SUS well related activity (host/Intel ME wakes and runtime events) on a rising edge. SUSACK# must be driven to match SUSWARN# once the above preparation is complete. SUSACK# should be asserted within a minimal amount of time from SUSWARN# assertion as no wake events are supported if SUSWARN# is asserted but SUSACK# is not asserted. Platforms supporting DeepSx, but not wishing to participate in the handshake during wake and DeepSx entry may tie SUSACK# to SUSWARN#.

This pin may be multiplexed with a GPIO for use in systems that do not support DeepSx. This pin is multiplexed with SUSPWRDNACK since it is not needed in DeepSx supported platforms.

Reset type: RSMRST# This signal is multiplexed with GPIO30 and SUSPWRDNACK.

Datasheet 89

Table 2-25. Power Management Interface Signals (Sheet 4 of 4)

Name Type Description

SUSPWRDNACK: Active high. Asserted by the PCH on behalf of the Intel

SUSPWRDNACK /

SUSWARN# / GPIO30

SYS_PWROK I

SYS_RESET# I

WAKE# I/OD

ME when it does not require the PCH Suspend well to be powered.

Platforms are not expected to use this signal when the PCH’s DeepSx feature is used.

This signal is multiplexed with GPIO30 and SUSWARN#.

System Power OK: This generic power good input to the PCH is driven and utilized in a platform-specific manner. While PWROK always indicates that the core wells of the PCH are stable, SYS_PWROK is used to inform the PCH that power is stable to some other system component(s) and the system is ready to start the exit from reset.

System Reset: This signal forces an internal reset after being debounced. The PCH will reset immediately if the SMBus is idle; otherwise, it will wait up to 25 ms ±2 ms for the SMBus to idle before forcing a reset on the system.

PCI Express* Wake Event in Sx: This signal is in DSW and behaves as an input pin in Sx states. Sideband wake signal on PCI Express asserted by components requesting wake up.

PCIe OBFF on this pin has been de-featured and is not supported.

2.25 Power and Ground Signals

Signal Description

Table 2-26. Power and Ground Signals (Sheet 1 of 2)

Name Description

DCPRTC Decoupling: This signal is for RTC decoupling only. The signal requires decoupling.

DCPSST

DCPSUS1

DCPSUS2

DCPSUS3

DCPSUSBYP Decoupling: This signal is for decoupling internally generated 1.05 V DeepSx only.

VCC

VCC3_3 3.3 V supply for core well I/O buffers.

VCCASW

Decoupling: Internally generated 1.5 V powered from Suspend Well. This signal

requires decoupling. Decoupling is required even if this feature is not used.

1.05 V Suspend well power. If INTVRMEN is strapped high, power to this well is supplied internally and this pin

should be left as no connect. If INTVRMEN is strapp ed low, pow er t o this well mu st be supplie d by an extern al 1.05 V

suspend rail.

Note: External VR mode applies to Mobile Only.

1.05 V Suspend well power for USB 2.0. If INTVRMEN is strapped high, power to this well is supplied internally and this pin

should be left as no connect. If INTVRMEN is strapp ed low, pow er t o this well mu st be supplie d by an extern al 1.05 V

suspend rail.

Note: External VR mode applies to Mobile Only.

1.05 V Suspend well power for USB 3.0. If INTVRMEN is strapped high, power to this well is supplied internally and these pins

should be left as no connect. If INTVRMEN is strapp ed low, pow er t o this well mu st be supplie d by an extern al 1.05 V

suspend rail.

Note: External VR mode applies to Mobile Only.

1.05 V supply for core well logic. This power may be shut off in S3, S4, S5, or G3 states.

1.05 V supply for the Active Sleep Well. Provides power to the Intel ME and integrated LAN. This plane must be on in S0 and other times the Intel ME or integrated LAN is used.

Datasheet



Signal Description

Table 2-26. Power and Ground Signals (Sheet 2 of 2)

Name Description

3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power is not

VCCRTC

VCCIO

VccSUS3_3

VCCSUSHDA Suspend supply for Intel HD Audio. This pin can be either 1.5 or 3.3 V.

VCCVRM

VCCADAC1_5

VCCADACBG3_3

VSS Ground.

VCCCLK

VCCCLK3_3

V_PROC_IO

VCCDSW3_3

VCCSPI

VCCUSBPLL

expected to be shut off unless the RTC battery is removed or completely drained.

Note: Implementations should not attempt to clear CMOS by using a jumper to pull

1.05 V supply for I/O buffers. This power may be shut off in S3, S4, S5, Deep Sx or G3 states.

3.3 V supply for suspend well I/O buffers. This power may be shut off in DeepSx or G3 state.

1.5 V supply for internal VRMs. This power may be shut off in S3, S4, S5, Deep Sx, or G3 states.

1.5 V supply for Display DAC Analog Power. This power may be shut off in S3, S4, S5, Deep Sx, or G3 states.

3.3 V s upply fo r D isplay D AC Band Gap . This po we r may be s hu t off in S 3, S4, S5, Dee p Sx, or G3 states.

1.0 5V Analog pow er supply f or interna l c lock PLL. T his power m ay be shut o ff in S3, S4, S5, Deep Sx, or G3 states.

3.3 V Analog power supply for internal clock PLL. This power may be shut off in S3, S4, S5, Deep Sx, or G3 states.

1.05V supply for processor interface signals. This power may be shut off in S3, S4, S5, Deep Sx, or G3 states. Connect to the same supply as the PCH VCCIO; do not tie this signal to the processor.

3.3 V supply for DeepSx wells. If the platform does not support Deep Sx, then tie to VccSUS3_3.

3.3 V supply for SPI Controller Logic. This rail must be powered when VccASW is powered.

Note: This rail can be optionally powered on 3.3 V Suspend power (VccSUS3_3)

1.05V Analog power supply for USB PLL. This power may be shut off in S3, S4, S5, Deep Sx, or G3 states.

VccRTC low. Clearing CMOS can be done by using a jumper on RTCRST# or GPI.

based on platform needs.

2.26 Thermal Signals

Table 2-27. Thermal Signals (Sheet 1 of 2)

Signal Name Type Description

PWM[3:0] OD O Fan Pulse Width Modulation Outputs: These signals are Pulse Width

Datasheet 91

Modulated duty cycle output signals used for fan control. These signals are 3.3 V tolerant.

Note: TACH signals used on Server/Workstation Only; not supported on

Mobile and Desktop.

Table 2-27. Thermal Signals (Sheet 2 of 2)

Signal Name Type Description

TACH0 / GPIO17 TACH1 / GPIO1 TACH2 / GPIO6 TACH3 / GPIO7 TACH4 / GPIO68 TACH5 / GPIO69 TACH6 / GPIO70 TACH7 / GPIO71

SST I/O Simple Serial Transport: Single- wir e, ser ia l bu s. C onnec t th is sig nal to SST

PECI I/O Platform Environment Control Interface: Single-wire, serial bus.

TD_IREF I

I Fan Tachometer Inputs: Tachometer pulse input signal that is used to

measure fan speed. This signal is connected to the “Sense” signal on the fan. The signals can instead be used as a GPIO.

Note: TACH signals used on Server/Workstation Only; not supported on

Mobile and Desktop.

compliant devices such as SST thermal sensors or voltage sensors. Note: TACH signals used on Server/Workstation Only; not supported on

Mobile and Desktop.

Internal Reference Voltage: Thermal sensor low-cap analog reference bias current. This should be connected to Vss (ground) using an external resistor of 8.2 K.

2.27 Miscellaneous Signals

Signal Description

Table 2-28. Miscellaneous Signals (Sheet 1 of 2)

Name Type Description

Internal Voltage Regulator Enable: When pulled high, this signal enables

the internal 1.05 V regulators for the Suspend well in the PCH. This signal must

INTVRMEN I

DSWVRMEN I

SPKR O

RTCRST# I

SRTCRST# I

SML1ALERT#/ TEMP_ALERT#/ GPIO74

remain asserted for the VRMs to behave properly (no glitches allowed). This signal must be pulled-up to VCCRTC on desktop platforms and may

optionally be pulled low on mobile platforms if using an external VR for the VCCSUS rail.

DeepSx Well Internal Voltage Regulator Enable: This signal enables the internal DSW 1.05 V regulators and must be always pulled-up to VCCRTC.

Speaker: The SPKR signal is the output of counter 2 and is internally “ANDed” with Port 61h Bit 1 to provide Speaker Data Enable. This signal drives an external speaker driver device, which in turn drives the system speaker. Upon PLTRST#, its output state is 0.

Note: SPKR is sampled as a functional strap. There is a weak integrated pull-

down resistor on SPKR pin.

RTC Reset: When asserted, this signal resets register bits in the RTC well.

Notes:

1. Unless CMOS is being cleared (only to be done in the G3 power state), the RTCRST# input must always be high when all other RTC power planes are on.

2. In the case where the RTC battery is dead or missing on the platform, the RTCRST# pin must rise before the DPWROK pin.

Secondary RTC Reset: This signal resets the manageability register bits in the RTC well when the RTC battery is removed.

Notes:

1. The SRTCRST# input must always be high when all other RTC power planes are on.

2. In the case where the RTC battery is dead or missing on the platform, the SRTCRST# pin must rise before the RSMRST# pin.

TEMP_ALERT#: This signal is used to indicate a PCH temperature out of bounds condition to an external EC, when PCH temperature is greater than value programmed by BIOS. An external pull-up resistor is required on this signal.

Note: A soft-strap determines the native function SML1ALERT# or

TEMP_ALERT# usage. When soft-strap is 0, function is SML1ALERT#, when soft-strap is 1, function is TEMP_ALERT#.

Datasheet



Signal Description

Table 2-28. Miscellaneous Signals (Sheet 2 of 2)

Name Type Description

GPIO35 / NMI# (Server / Workstation Only)

PCIECLKRQ2# / GPIO20 / SMI#

(Server / Workstation Only)

PME# I/OD

OD O NMI#: This is an NMI event indication to an external controller (such as a

BMC) on server/workstation platforms. When operating as NMI event indication pin function (enabled when “NMI SMI

Event Native GPIO Enable” soft strap [PCHSTRP9:bit 16] is set to 1), the pin is OD (open drain).

OD O SMI#: This is an SMI event indication to an external controller (such as a BMC)

on server/workstation platforms. When operating as SMI event indication pin function (enabled when “NMI SMI

Event Native GPIO Enable” soft strap [PCHSTRP9:bit 16] is set to 1), the pin is OD (open drain).

PCI Power Management Event: PCI peripherals drive PME# to wake the system from low-power states S1–S5. PME# assertion can also be enabled to generate an SCI from the S0 state. In some cases the PCH may drive PME# active due to an internal wake event. The PCH will not drive PME# high, but it will be pulled up to VccSUS3_3 by an internal pull-up resistor.

PME# is still functional and can be used with PCI legacy mode on platforms using a PCIe-to-PCI bridge. Downstream PCI devices would need to have PME# routed from the connector to the PCH PME# pin.

2.28 Testability Signals

Table 2-29. Testability Signals

Name Type Description

JTAG_TCK I

JTAG_TMS I

JTAG_TDI I

JTAG_TDO OD

Note: JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE

Std. 1149.1-2001)

Test Clock Input (TCK): The test clock input provides the clock for the JTAG test logic.

Test Mode Select (TMS): The signal is decoded by the Test Access Port (TAP) controller to control test operations.

Test Data Input (TDI): Serial test instructions and data are received by the test logic at TDI.

Test Data Output (TDO): TDO is the serial output for test instructions and data from the test logic defined in this standard.

2.29 Reserved / Test Pins

Table 2-30. Test Pins (Sheet 1 of 2)

Name Description

TP1

TP2

TP3 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).

TP4

TP5

TP6

TP7 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).

TP8

TP9

Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).

Datasheet 93

Table 2-30. Test Pins (Sheet 2 of 2)

Name Description

TP10

TP11 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).

TP12

TP13

TP14

TP15 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).

TP16

TP17

TP18

TP19 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).

TP20

TP21

TP22

TP23 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).

TP24

TP25

Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).

Intel Reserved Pin: Must have a pull-up resistor to VCC3_3. Standard resistor value in the range of 4.7 K to 15 K

Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).

Signal Description

Note: The Test Point descriptions provided in this table apply to both Desktop and Mobile packages.

§ §

Datasheet



PCH Pin States

3 PCH Pin States

3.1 Integrated Pull-Ups and Pull-Downs

Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 1 of 2)

Signal Resistor Type Nominal Notes

USB2p/n[13:0] Pull-down 15K 4

SATA1GP/GPIO19, SUSCLK/GPIO62, GPIO55, GPIO53, GPIO51,

SATA2GP/GPIO36, SATA3GP/GPIO37, SPKR, DDP[B:D]_CTRLDATA

HDA_DOCK_EN#, HDA_SDO

SATA4GP/GPIO16, SATA5GP/GPIO49

PCIECLKRQ5#/GPIO44, PCIECLKRQ7#/GPIO46, GPIO8

NMI# Pull-up 20K 3, 6, 24

USB3[T/R] [p/n] [6:1] Pull-down 15K 4

HDA_SDI[3:0], HDA_SYNC

SPI_CLK, SPI_CS[2:0]#

SPI_MOSI Pull-up or

SPI_MISO, SPI_IO3, SPI_IO2

PECI Pull-down 350 17

LAD[3:0], LDRQ0#, LDRQ1#

TACH[7:0] Pull-up 20K 3, 19, 24

SST Pull-down 10K 3, 16, 24

PWRBTN# Pull-up 20K 3

WAKE# Pull-down 20K 3, 9, 19

GPIO31 (ACPRESENT) Pull-down 20K 3, 9

SUSACK# Pull-up 20K 2

GPIO27 Pull-down 20K 3, 9, 20

PME# Pull-up 20K 3

CL_CLK, CL_DATA Pull-up/Pull-down 31.25/100 13

Pull-up 20K 3, 7, 24

Pull-down 20K 3, 7

Pull-down 15K 2, 7, 12, 24

Pull-up 20K 3, 5

Pull-up 20K 3, 11

Pull-down 15K 2, 12

Pull-up 20K 3, 23

Pull-down

Pull-up 20K 3, 8

Pull-up 20K 3

20K 3, 22

Datasheet 95

Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 2 of 2)

Signal Resistor Type Nominal Notes

CLKOUT_33MHZ[4:0], CLKOUTFLEX[3:0]/GPIO[67:64]

SMI# Pull-up 20K 3, 9, 24

JTAG_TDI, JTAG_TMS

JTAG_TCK Pull-down 20K 3

PET/R p/n[8:1], USB3T/R p/n[6:1], SATA_TX/RX p/n [6:1]

FDI_RX p/n[1:0], DMI_TX/RX p/n[3:0]

Notes:

1. Simulation data shows that these resistor values can range from 10 k to 45 k.

2. Simulation data shows that these resistor values can range from 9 k to 50 k.

3. Simulation data shows that these resistor values can range from 15 k to 40 k.

4. Simulation data shows that these resistor values can range from 14.25 k to 24.8 k.

5. GPIO16 has two native functions – the 1st native function (SATAP4_PCIEP1_SELECT) is selected if the Flex I/O soft strap SATAP4_PCIEP1_MODE = 11b and takes precedence over any other assignments to this pin (that is, if this is selected, writes to GPIO_USE_SEL are ignored). If SATAP4_PCIEP1_MODE is not set to 11b, the GPIO_USE_SEL register can be used to select the 2nd native function (SATA4GP) or GPIO functionality. Setting SATAP4_PCIEP1_MODE = 11b also enables an internal pull-up resistor in this pin to allow Flexible I/O selection of SATA Port 4 or PCIe Port 1 to be done based on the type of card installed (If sampled value = 1, select SATA; if sampled value = 0, select PCIe). The same behavior is true of pin SATA5GP/GPIO49 when the soft strap SATAP5_PCIEP2_MODE = 11b. Soft straps are handled through FITc.

6. When operating as NMI# event indication pin function, the pin is open drain but the PCH provides an internal pull-up to ensure the pin does not float.

7. This signal is a PCH functional strap; the pull-up or pull-down on this signal is disabled after it is sampled as a PCH functional strap.

8. This signal has a weak internal pull-up that is always on.

9. 9When operating as SMI# event indication pin function, the pin is open drain but the PCH provides an internal pull-up to ensure the pin does not float.

10. The pull-down is disabled after the pins are driven strongly to logic 0 when PWROK is asserted.

11. The pull-up or pull-down on this signal is disabled after RSMRST# de-asserts. This pin is not a functional strap.

12. The internal pull-down on HDA_SYNC and HDA_SDO is enabled during reset.

13. The Controller Link Clock and Data buffers use internal pull-up or pull-down resistors to drive a logical 1 or

14. Termination resistors may be present if signal is enabled (that is, related Port is not disabled). These resistors appear to be strong pull-downs or pull-ups on the signals.

15. Internal pull-down resistor may be enabled in Deep Sx mode based on DSX_CFG configuration bit, as follows: ‘1’ (pin will be driven by platform in Deep Sx) -> Z; - ‘0’ (pin will NOT be driven by platform in Deep Sx) -> Internal pull-down. Refer to DSX_CFG register (RCBA+3334h) for more details.

16. When the interface is in BUS IDLE, the internal pull-down of 10 k is enabled. In normal transmission, a 400  pull-down takes effect, the signal will be overridden to logic 1 with pull-up resistor (37 ) to VCC

1.5 V.

17. This is a 350- normal pull-down, signal will be overridden to logic 1 with pull-up resistor (31 ) to VCC

1.05 V.

18. N/A

19. Regardless of internal pull-up or pull-down, an external pull-up resistor is still required.

20. External pull-up if Intel wired LAN is present (pull-up to SUS/DSW based on deepest wake on LAN support desired).

21. N/A

22. Weak internal pull-up resistor is enabled when APWROK is de-asserted and is switched to a weak internal pull-down resistor when APWROK and PLTRST# are both asserted.

23. Signals are tri-stated with weak pull-up resistors when APWROK is de-asserted. SPI_CS1# remains tristated with a weak pull-up resistor when APWROK and PLTRST# are both asserted.

24. Some signals may not be available in all SKUs. Check signal and SKU descriptions.

Pull-down 20K 1, 10

Pull-up 20K 3

Pull-up or Pull-down

50 14

PCH Pin States

Datasheet



PCH Pin States

3.2 Output Signals Planes and States

Table 3-2 shows the power plane associated with the output and I/O signals, as well as

the state at various times. Within the table, the following terms are used:

“DL” PCH drives low.

“DH” PCH drives high.

“IPU” Internal pull-up.

“IPD” Internal pull-down.

“T” Toggling or signal is transitioning because function not stopping.

“High-Z” Tri-state. PCH not driving the signal high or low.

“Defined” Driven to a level that is defined by the function or external pull-

up/pull-down resistor (will be high or low).

“Off” The power plane is off; PCH is not driving when configured as an

Note: Pin state within table assumes interfaces are idle and default pin configuration for

different power states.

output or sampling when configured as an input.

Signal levels are the same in S3, S4 and S5, except as noted.

In general, PCH suspend well signal states are indeterminate and undefined and may glitch prior to RSMRST# de-assertion.

PCH core well signal states are indeterminate and undefined and may glitch prior to PWROK assertion. However, this does not apply to THRMTRIP# as this signal is determinate and defined prior to PWROK assertion.

DSW indicates PCH Deep Sx Well. This state provides a few wake events and critical context to allow system to draw minimal power in S3, S4 or S5 states. In general, PCH DSW signal states are indeterminate, undefined and may glitch prior to DPWROK assertion. The signals that are determinate and defined prior to DPWROK assertion will have a note added as a reference.

ASW indicates PCH Active Sleep Well. This power well contains functionality associated with active usage models while the host system is in Sx.

Datasheet 97

PCH Pin States

Table 3-2. Output Signals – Power Plane and States in Desktop, Mobile, and Server

Configurations (Sheet 1 of 4)

Immediately

Signal Name Power Plane During Reset

USB2p/n[13:0] Suspend IPD IPD IPD Off

USB3Tp/n[4:3]

PETp/n[2:1]

n[6:5, 2:1]

, USB3Tp/

Suspend IPD

Suspend or

Core5

PETp/n[8:3] Core IPD

SATA_TXp/n[3:0] Core IPU

SATA_TXp/n[5:4]

Core IPU1 IPU1 Off Off

SATALED# Core High-Z High-Z Off Off

SCLOCK Core High-Z High-Z Off Off

SLOAD Core High-Z High-Z Off Off

SDATAOUT[1:0] Core High-Z High-Z Off Off

CLKOUT_ITPXDP_P/N

Core

T (platform

dependent)

CLKOUT_DP_P/N Core T T Off Off

CLKOUT_DPNS_P/N Core T T Off Off

CLKOUT_DMI_P/N Core T T Off Off

XTAL25_OUT Core High-Z High-Z Off Off

CLKOUT_PEG_A_P/N Core T T Off Off

CLKOUT_PEG_B_P/N Core T T Off Off

CLKOUT_PCIE_P/N[7:0] Core T T Off Off

CLKOUT_33MHZ[4:0] Core T T Off Off

CLKOUTFLEX[3:0]

Core

T (platform

dependent)

DIFFCLK_BIASREF Core High-Z High-Z Off Off

ICLK_IREF Core High-Z High-Z Off Off

Interrupt Interface

SERIRQ Core High-Z High-Z Off Off

PIRQ[D:A]# Core High-Z High-Z Off Off

PIRQ[H:E]# Core High-Z High-Z Off Off

NMI#

Core IPU IPU Off Off

Processor Interface

PROCPWRGD Core DL DH Off Off

PMSYNCH Core DL DL Off Off

after Reset

S3/S4/S5 Deep Sx

USB Interface

IPD1

S3 High-Z

S4 and S5 Off

PCI Express*

IPD1 IPD1 Off Off

IPD1 Off Off

SATA Interface

IPU1 Off Off

Clocking Signals

T (platform dependent)

Off Off

Off

Datasheet



PCH Pin States

Table 3-2. Output Signals – Power Plane and States in Desktop, Mobile, and Server

Configurations (Sheet 2 of 4)

Immediately

Signal Name Power Plane During Reset

DMI_TXp/n[3:0] Core IPU or IPD

Intel

Flexible Display Interface (Intel® FDI)

FDI_CSYNC Core High-Z

FDI_INT Core High-Z

Analog Display / VGA DAC Signals

VGA_RED, VGA_GREEN,

VGA_BLUE

Core High-Z High-Z Off Off

DAC_IREF Core High-Z DL Off Off

VGA_HSYNC Core DL DL Off Off

VGA_VSYNC Core DL DL Off Off

VGA_DDC_CLK Core High-Z High-Z Off Off

VGA_DDC_DATA Core High-Z High-Z Off Off

VGA_IRTN Core High-Z High-Z Off Off

Digital Display Interface

DDP[D:B]_AUXP/N Core IPD IPD Off Off

DDPB_CTRLCLK, DDPC_CTRLCLK,

Core High-Z High-Z Off Off

DDPD_CTRLCLK

DDPB_CTRLDATA, DDPC_CTRLDATA,

Core IPD

DDPD_CTRLDATA

eDP_VDD_EN Core DL DL Off Off

eDP_BKLTEN Core DL DL Off Off

eDP_BKLTCTL Core DL DL Off Off

Intel

High Definition Audio Interface (Intel® HD Audio)

HDA_RST#

HDA_BCLK

HDA_SYNC

HDA_SDO

HDA_DOCK_EN#

HDA_DOCK_RST#

Suspend DL DL DL Off

Suspend IPD IPD IPD Off

Core IPD IPD Off Off

Suspend

High-Z High-Z

LAD[3:0] Core IPU IPU Off Off

LFRAME# Core DH DH Off Off

Non-Multiplexed GPIO Signals

GPIO8

GPIO15

GPIO24

5, 9

Suspend IPU DH DH Off

Suspend DL DL DL Off

DMI

1, 21

LPC Interface

after Reset

IPU or IPD

High-Z

1, 21

S3/S4/S5 Deep Sx

Off Off

High-Z Off Off

High-Z

Off

Datasheet 99

PCH Pin States

Table 3-2. Output Signals – Power Plane and States in Desktop, Mobile, and Server

Configurations (Sheet 3 of 4)

Immediately

Signal Name Power Plane During Reset

GPIO28

CLKRUN#

Suspend DL DL DL Off

Core

DL (Mobile);

DH (Desktop)

GPIO[53, 51] Core IPU DH Off Off

GPIO55 Core IPU DL DL Off

SMBCLK, SMBDATA Suspend High-Z High-Z High-Z Off

System Management Interface

SML0DATA Suspend High-Z High-Z High-Z Off

SML0CLK Suspend High-Z High-Z High-Z Off

SML0ALERT# Suspend High-Z High-Z

SML1ALERT# Suspend High-Z High-Z High-Z Off

SML1CLK Suspend High-Z High-Z High-Z Off

SML1DATA Suspend High-Z High-Z High-Z Off

CL_RST#

CL_CLK

CL_DATA

Suspend DL DH DH Off

Suspend Terminated12 Terminated12 IPD Off

SPI_CLK ASW DL DL DL Off

SPI_CS0# ASW DH DH DH Off

SPI_CS1# ASW IPU DH DH Off

SPI_CS2# ASW DH DH DH Off

SPI_MOSI ASW IPD DL DL Off

SPI_MISO ASW IPU IPU IPU Off

SPI_IO2 ASW IPU IPU IPU Off

SPI_IO3 ASW IPU IPU IPU Off

Power Management

DRAMPWROK

Suspend DL High-Z

LAN_PHY_PWR_CTRL DSW DL DL DL DL

PLTRST# Suspend DL DH DL Off

PLTRST_PROC# Core DL DH DL Off

9, 11

SLP_A#

SLP_LAN#

DSW DL DH DH DL

DSW DL DL DL/DH

SLP_WLAN#9 DSW DL DL DL/DH

SLP_S3#

SLP_S4#

DSW DL DH DL DL

DSW DL DH

after Reset

DH (Desktop)

SMBus Interface

Controller Link

SPI Interface

DL (Mobile);

S3/S4/S5 Deep Sx

Off Off

High-Z Off

S3 High-Z,

S4 and S5 DL

S3 DH,

S4 and S5 DL

DL/DH

Off

100

Datasheet

Intel C220 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH)

Revision History

Platform Controller Hub Features

1 Introduction

1.1 About This Manual

1.1.1 Chapter Descriptions

1.2 Overview

1.2.1 Capability Overview

1.3 Intel® 8 Series/C220 Series Chipset Family PCH SKU Definition

1.4 Device and Revision ID Table

2 Signal Description

2.1 Flexible I/O

2.2 USB Interface

2.3 PCI Express*

2.4 Serial ATA Interface

2.5 Clock Signals

2.6 Real Time Clock Interface

2.7 External RTC Circuitry

2.8 Interrupt Interface

2.9 Processor Interface

2.10 Direct Media Interface (DMI) to Host Controller

2.11 Intel® Flexible Display Interface (Intel® FDI)

2.12 Analog Display/VGA DAC Signals

2.13 Digital Display Signals

2.14 Embedded DisplayPort* (eDP*) Backlight Control Signals

2.15 Intel® High Definition Audio (Intel® HD Audio) Link

2.16 Low Pin Count (LPC) Interface

2.17 General Purpose I/O Signals

2.18 Functional Straps

2.19 SMBus Interface

2.20 System Management Interface

2.21 Controller Link

2.22 Serial Peripheral Interface (SPI)

2.23 Manageability Signals

2.24 Power Management Interface

2.25 Power and Ground Signals

2.26 Thermal Signals

2.27 Miscellaneous Signals

2.28 Testability Signals

2.29 Reserved / Test Pins

3 PCH Pin States

3.1 Integrated Pull-Ups and Pull-Downs

3.2 Output Signals Planes and States