Intel C216 Datasheet

Intel® 7 Series / C216 Chipset Family Platform Controller Hub (PCH)

Datasheet

June 2012

Order Number: 326776-003

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2 Datasheet

Contents

1Introduction............................................................................................................ 43

1.1 About This Manual............................................................................................. 43

1.2 Overview ......................................................................................................... 46

1.2.1 Capability Overview ................................................................................ 47

1.3 Intel

2 Signal Description ................................................................................................... 57

2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 59

2.2 PCI Express* .................................................................................................... 59

2.3 PCI Interface .................................................................................................... 60

2.4 Serial ATA Interface........................................................................................... 63

2.5 LPC Interface.................................................................................................... 66

2.6 Interrupt Interface ............................................................................................ 66

2.7 USB Interface ................................................................................................... 67

2.8 Power Management Interface.............................................................................. 69

2.9 Processor Interface............................................................................................ 73

2.10 SMBus Interface................................................................................................ 73

2.11 System Management Interface............................................................................ 74

2.12 Real Time Clock Interface................................................................................... 74

2.13 Miscellaneous Signals ........................................................................................ 75

2.14 Intel

2.15 Controller Link .................................................................................................. 77

2.16 Serial Peripheral Interface (SPI) .......................................................................... 77

2.17 Thermal Signals ................................................................................................ 78

2.18 Testability Signals ............................................................................................. 78

2.19 Clock Signals .................................................................................................... 79

2.20 LVDS Signals .................................................................................................... 81

2.21 Analog Display /VGA DAC Signals ........................................................................ 82

2.22 Intel® Flexible Display Interface (Intel® FDI) ........................................................ 82

2.23 Digital Display Signals........................................................................................ 83

2.24 General Purpose I/O Signals ............................................................................... 85

2.25 Manageability Signals ........................................................................................ 90

2.26 Power and Ground Signals.................................................................................. 90

2.27 Pin Straps ........................................................................................................ 93

2.28 External RTC Circuitry........................................................................................ 97

3PCH Pin States......................................................................................................... 99

3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 99

3.2 Output and I/O Signals Planes and States........................................................... 101

3.3 Power Planes for Input Signals .......................................................................... 113

4 PCH and System Clocks ......................................................................................... 119

4.1 Platform Clocking Requirements ........................................................................ 119

4.2 Functional Blocks ............................................................................................ 122

4.3 Clock Configuration Access Overview ................................................................. 123

4.4 Straps Related to Clock Configuration ................................................................ 123

5 Functional Description........................................................................................... 125

5.1 PCI-to-PCI Bridge (D30:F0) .............................................................................. 125

7 Series / C216 Chipset Family SKU Definition ............................................. 54

High Definition Audio Link ......................................................................... 76

5.1.1 PCI Bus Interface ................................................................................. 125

5.1.2 PCI Bridge As an Initiator ...................................................................... 126

5.1.3 Parity Error Detection and Generation ..................................................... 127

5.1.4 PCIRST#............................................................................................. 128

5.1.5 Peer Cycles ......................................................................................... 128

5.1.2.1 Memory Reads and Writes........................................................ 126

5.1.2.2 I/O Reads and Writes .............................................................. 126

5.1.2.3 Configuration Reads and Writes ................................................ 126

5.1.2.4 Locked Cycles ........................................................................ 126

5.1.2.5 Target / Master Aborts............................................................. 126

5.1.2.6 Secondary Master Latency Timer............................................... 126

5.1.2.7 Dual Address Cycle (DAC)........................................................ 127

5.1.2.8 Memory and I/O Decode to PCI................................................. 127

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5.1.6 PCI-to-PCI Bridge Model ........................................................................ 128

5.1.7 IDSEL to Device Number Mapping ........................................................... 129

5.1.8 Standard PCI Bus Configuration Mechanism.............................................. 129

5.1.9 PCI Legacy Mode ..................................................................................129

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) ..................................... 129

5.2.1 Interrupt Generation ............................................................................. 130

5.2.2 Power Management............................................................................... 130

5.2.2.1 S3/S4/S5 Support ...................................................................130

5.2.2.2 Resuming from Suspended State............................................... 131

5.2.2.3 Device Initiated PM_PME Message ............................................. 131

5.2.2.4 SMI/SCI Generation................................................................. 131

5.2.3 SERR# Generation................................................................................132

5.2.4 Hot-Plug.............................................................................................. 132

5.2.4.1 Presence Detection.................................................................. 132

5.2.4.2 Message Generation ................................................................132

5.2.4.3 Attention Button Detection ....................................................... 133

5.2.4.4 SMI/SCI Generation................................................................. 133

5.3 Gigabit Ethernet Controller (B0:D25:F0) .............................................................134

5.3.1 GbE PCI Express* Bus Interface..............................................................135

5.3.1.1 Transaction Layer....................................................................135

5.3.1.2 Data Alignment....................................................................... 135

5.3.1.3 Configuration Request Retry Status ........................................... 136

5.3.2 Error Events and Error Reporting ............................................................136

5.3.2.1 Data Parity Error .....................................................................136

5.3.2.2 Completion with Unsuccessful Completion Status......................... 136

5.3.3 Ethernet Interface ................................................................................ 136

5.3.3.1 82579 LAN PHY Interface .........................................................136

5.3.4 PCI Power Management .........................................................................137

5.3.4.1 Wake Up ................................................................................137

5.3.5 Configurable LEDs.................................................................................139

5.3.6 Function Level Reset Support (FLR).........................................................140

5.3.6.1 FLR Steps...............................................................................140

5.4 LPC Bridge (with System and Management Functions) (D31:F0).............................140

5.4.1 LPC Interface ....................................................................................... 140

5.4.1.1 LPC Cycle Types......................................................................141

5.4.1.2 Start Field Definition ................................................................142

5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR)..................................... 142

5.4.1.4 Size.......................................................................................142

5.4.1.5 SYNC..................................................................................... 143

5.4.1.6 SYNC Time-Out.......................................................................143

5.4.1.7 SYNC Error Indication ..............................................................143

5.4.1.8 LFRAME# Usage...................................................................... 143

5.4.1.9 I/O Cycles ..............................................................................144

5.4.1.10 Bus Master Cycles ................................................................... 144

5.4.1.11 LPC Power Management ........................................................... 144

5.4.1.12 Configuration and PCH Implications ...........................................144

5.5 DMA Operation (D31:F0) ..................................................................................145

5.5.1 Channel Priority....................................................................................145

5.5.1.1 Fixed Priority ..........................................................................145

5.5.1.2 Rotating Priority......................................................................146

5.5.2 Address Compatibility Mode ...................................................................146

5.5.3 Summary of DMA Transfer Sizes .............................................................146

5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words 146

5.5.4 Autoinitialize ........................................................................................ 147

5.5.5 Software Commands ............................................................................. 147

5.6 LPC DMA ........................................................................................................147

5.6.1 Asserting DMA Requests ........................................................................147

5.6.2 Abandoning DMA Requests.....................................................................148

5.6.3 General Flow of DMA Transfers ...............................................................149

5.6.4 Terminal Count..................................................................................... 149

5.6.5 Verify Mode .........................................................................................149

5.6.6 DMA Request Deassertion ......................................................................149

5.6.7 SYNC Field / LDRQ# Rules .....................................................................150

5.7 8254 Timers (D31:F0) ...................................................................................... 151

5.7.1 Timer Programming ..............................................................................151

5.7.2 Reading from the Interval Timer ............................................................. 152

5.7.2.1 Simple Read ........................................................................... 152

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5.7.2.2 Counter Latch Command.......................................................... 153

5.7.2.3 Read Back Command .............................................................. 153

5.8 8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 154

5.8.1 Interrupt Handling................................................................................ 155

5.8.1.1 Generating Interrupts.............................................................. 155

5.8.1.2 Acknowledging Interrupts ........................................................ 155

5.8.1.3 Hardware/Software Interrupt Sequence ..................................... 156

5.8.2 Initialization Command Words (ICWx)..................................................... 156

5.8.2.1 ICW1 .................................................................................... 156

5.8.2.2 ICW2 .................................................................................... 157

5.8.2.3 ICW3 .................................................................................... 157

5.8.2.4 ICW4 .................................................................................... 157

5.8.3 Operation Command Words (OCW)......................................................... 157

5.8.4 Modes of Operation .............................................................................. 157

5.8.4.1 Fully Nested Mode................................................................... 157

5.8.4.2 Special Fully-Nested Mode........................................................ 158

5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 158

5.8.4.4 Specific Rotation Mode (Specific Priority).................................... 158

5.8.4.5 Poll Mode............................................................................... 158

5.8.4.6 Edge and Level Triggered Mode ................................................ 159

5.8.4.7 End of Interrupt (EOI) Operations ............................................. 159

5.8.4.8 Normal End of Interrupt........................................................... 159

5.8.4.9 Automatic End of Interrupt Mode .............................................. 159

5.8.5 Masking Interrupts ............................................................................... 159

5.8.5.1 Masking on an Individual Interrupt Request................................ 159

5.8.5.2 Special Mask Mode.................................................................. 160

5.8.6 Steering PCI Interrupts ......................................................................... 160

5.9 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 160

5.9.1 Interrupt Handling................................................................................ 160

5.9.2 Interrupt Mapping ................................................................................ 161

5.9.3 PCI/PCI Express* Message-Based Interrupts ............................................ 162

5.9.4 IOxAPIC Address Remapping ................................................................. 162

5.9.5 External Interrupt Controller Support ...................................................... 162

5.10 Serial Interrupt (D31:F0) ................................................................................. 162

5.10.1 Start Frame......................................................................................... 163

5.10.2 Data Frames........................................................................................ 163

5.10.3 Stop Frame ......................................................................................... 163

5.10.4 Specific Interrupts Not Supported Using SERIRQ ...................................... 164

5.10.5 Data Frame Format .............................................................................. 164

5.11 Real Time Clock (D31:F0)................................................................................. 165

5.11.1 Update Cycles...................................................................................... 165

5.11.2 Interrupts ........................................................................................... 166

5.11.3 Lockable RAM Ranges ........................................................................... 166

5.11.4 Century Rollover .................................................................................. 166

5.11.5 Clearing Battery-Backed RTC RAM .......................................................... 166

5.12 Processor Interface (D31:F0) ............................................................................ 168

5.12.1 Processor Interface Signals and VLW Messages ........................................ 168

5.12.1.1 INIT (Initialization) ................................................................. 168

5.12.1.2 FERR# (Numeric Coprocessor Error).......................................... 169

5.12.1.3 NMI (Non-Maskable Interrupt) .................................................. 169

5.12.1.4 Processor Power Good (PROCPWRGD) ....................................... 169

5.12.2 Dual-Processor Issues........................................................................... 169

5.12.2.1 Usage Differences ................................................................... 169

5.12.3 Virtual Legacy Wire (VLW) Messages....................................................... 170

5.13 Power Management ......................................................................................... 170

5.13.1 Features ............................................................................................. 170

5.13.2 PCH and System Power States ............................................................... 171

5.13.3 System Power Planes............................................................................ 173

5.13.4 SMI#/SCI Generation ........................................................................... 173

5.13.4.1 PCI Express* SCI.................................................................... 175

5.13.4.2 PCI Express* Hot-Plug............................................................. 175

5.13.5 C-States ............................................................................................. 176

5.13.6 Dynamic PCI Clock Control (Mobile Only)................................................. 176

5.13.6.1 Conditions for Checking the PCI Clock........................................ 176

5.13.6.2 Conditions for Maintaining the PCI Clock .................................... 176

5.13.6.3 Conditions for Stopping the PCI Clock........................................ 176

5.13.6.4 Conditions for Re-Starting the PCI Clock .................................... 177

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5.13.7 Sleep States ........................................................................................177

5.13.6.5 LPC Devices and CLKRUN# .......................................................177

5.13.7.1 Sleep State Overview...............................................................177

5.13.7.2 Initiating Sleep State ...............................................................177

5.13.7.3 Exiting Sleep States................................................................. 178

5.13.7.4 PCI Express* WAKE# Signal and PME Event Message................... 180

5.13.7.5 Sx-G3-Sx, Handling Power Failures............................................180

5.13.7.6 Deep Sx.................................................................................181

5.13.8 Event Input Signals and Their Usage .......................................................182

5.13.8.1 PWRBTN# (Power Button) ........................................................ 182

5.13.8.2 RI# (Ring Indicator) ................................................................ 184

5.13.8.3 PME# (PCI Power Management Event) .......................................184

5.13.8.4 SYS_RESET# Signal ................................................................184

5.13.8.5 THRMTRIP# Signal .................................................................. 184

5.13.9 ALT Access Mode ..................................................................................185

5.13.9.1 Write Only Registers with Read Paths in ALT Access Mode............. 186

5.13.9.2 PIC Reserved Bits....................................................................188

5.13.9.3 Read Only Registers with Write Paths in ALT Access Mode............. 188

5.13.10System Power Supplies, Planes, and Signals.............................................188

5.13.10.1Power Plane Control with SLP_S3#,

SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN#............................... 188

5.13.10.2SLP_S4# and Suspend-To-RAM Sequencing................................189

5.13.10.3PWROK Signal ........................................................................ 189

5.13.10.4BATLOW# (Battery Low) (Mobile Only).......................................189

5.13.10.5SLP_LAN# Pin Behavior............................................................190

5.13.10.6RTCRST# and SRTCRST# .........................................................190

5.13.10.7SUSPWRDNACK/SUSWARN#/GPIO30 Pin Behavior ......................191

5.13.11Legacy Power Management Theory of Operation .......................................191

5.13.11.1APM Power Management (Desktop Only) ....................................191

5.13.11.2Mobile APM Power Management (Mobile Only) ............................. 192

5.13.12Reset Behavior .....................................................................................192

5.14 System Management (D31:F0) ..........................................................................194

5.14.1 Theory of Operation .............................................................................. 194

5.14.1.1 Detecting a System Lockup....................................................... 194

5.14.1.2 Handling an Intruder ...............................................................194

5.14.1.3 Detecting Improper Flash Programming......................................195

5.14.1.4 Heartbeat and Event Reporting using SMLink/SMBus....................195

5.14.2 TCO Modes ..........................................................................................196

5.14.2.1 TCO Legacy/Compatible Mode...................................................196

5.14.2.2 Advanced TCO Mode................................................................ 197

5.15 General Purpose I/O (D31:F0)...........................................................................198

5.15.1 Power Wells ......................................................................................... 198

5.15.2 SMI# SCI and NMI Routing ....................................................................198

5.15.3 Triggering............................................................................................198

5.15.4 GPIO Registers Lockdown ......................................................................198

5.15.5 Serial POST Codes over GPIO .................................................................199

5.15.5.1 Theory of Operation................................................................. 199

5.15.5.2 Serial Message Format.............................................................200

5.16 SATA Host Controller (D31:F2, F5)..................................................................... 201

5.16.1 SATA 6 Gb/s Support ............................................................................202

5.16.2 SATA Feature Support ...........................................................................202

5.16.3 Theory of Operation .............................................................................. 203

5.16.3.1 Standard ATA Emulation...........................................................203

5.16.3.2 48-Bit LBA Operation ...............................................................203

5.16.4 SATA Swap Bay Support........................................................................203

5.16.5 Hot Plug Operation................................................................................203

5.16.6 Function Level Reset Support (FLR)......................................................... 204

5.16.6.1 FLR Steps...............................................................................204

5.16.7 Intel

5.16.8 Intel

Rapid Storage Technology Configuration.........................................204

5.16.7.1 Intel® Rapid Storage Technology RAID Option ROM .....................205

Smart Response Technology .........................................................205

5.16.9 Power Management Operation ................................................................206

5.16.9.1 Power State Mappings.............................................................. 206

5.16.9.2 Power State Transitions............................................................ 206

5.16.9.3 SMI Trapping (APM).................................................................207

5.16.10SATA Device Presence ........................................................................... 207

5.16.11SATA LED ............................................................................................208

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5.16.12AHCI Operation.................................................................................... 208

5.16.13SGPIO Signals ..................................................................................... 209

5.16.13.1Mechanism ............................................................................ 209

5.16.13.2Message Format ..................................................................... 210

5.16.13.3LED Message Type .................................................................. 210

5.16.13.4SGPIO Waveform.................................................................... 212

5.16.14External SATA...................................................................................... 213

5.17 High Precision Event Timers.............................................................................. 213

5.17.1 Timer Accuracy .................................................................................... 213

5.17.2 Interrupt Mapping ................................................................................ 214

5.17.3 Periodic vs. Non-Periodic Modes ............................................................. 214

5.17.4 Enabling the Timers.............................................................................. 215

5.17.5 Interrupt Levels ................................................................................... 215

5.17.6 Handling Interrupts .............................................................................. 216

5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 216

5.18 USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. 217

5.18.1 EHC Initialization.................................................................................. 217

5.18.1.1 BIOS Initialization................................................................... 217

5.18.1.2 Driver Initialization ................................................................. 217

5.18.1.3 EHC Resets ............................................................................ 217

5.18.2 Data Structures in Main Memory............................................................. 217

5.18.3 USB 2.0 Enhanced Host Controller DMA................................................... 218

5.18.4 Data Encoding and Bit Stuffing............................................................... 218

5.18.5 Packet Formats .................................................................................... 218

5.18.6 USB 2.0 Interrupts and Error Conditions.................................................. 218

5.18.6.1 Aborts on USB 2.0-Initiated Memory Reads ................................ 219

5.18.7 USB 2.0 Power Management.................................................................. 219

5.18.7.1 Pause Feature ........................................................................ 219

5.18.7.2 Suspend Feature..................................................................... 219

5.18.7.3 ACPI Device States ................................................................. 219

5.18.7.4 ACPI System States ................................................................ 220

5.18.8 USB 2.0 Legacy Keyboard Operation....................................................... 220

5.18.9 USB 2.0 Based Debug Port .................................................................... 220

5.18.9.1 Theory of Operation ............................................................... 221

5.18.10EHCI Caching....................................................................................... 225

5.18.11Intel® USB Pre-Fetch Based Pause ......................................................... 225

5.18.12Function Level Reset Support (FLR) ........................................................ 225

5.18.12.1FLR Steps .............................................................................. 225

5.18.13USB Overcurrent Protection ................................................................... 226

5.19 Integrated USB 2.0 Rate Matching Hub .............................................................. 227

5.19.1 Overview ............................................................................................ 227

5.19.2 Architecture......................................................................................... 227

5.20 xHCI Controller (D20:F0) ................................................................................. 227

5.21 SMBus Controller (D31:F3)............................................................................... 228

5.21.1 Host Controller..................................................................................... 228

5.21.1.1 Command Protocols ................................................................ 229

5.21.2 Bus Arbitration..................................................................................... 232

5.21.3 Bus Timing .......................................................................................... 233

5.21.3.1 Clock Stretching ..................................................................... 233

5.21.3.2 Bus Time Out (The PCH as SMBus Master) ................................. 233

5.21.4 Interrupts / SMI#................................................................................. 233

5.21.5 SMBALERT# ........................................................................................ 234

5.21.6 SMBus CRC Generation and Checking...................................................... 234

5.21.7 SMBus Slave Interface .......................................................................... 235

5.21.7.1 Format of Slave Write Cycle ..................................................... 236

5.21.7.2 Format of Read Command........................................................ 237

5.21.7.3 Slave Read of RTC Time Bytes.................................................. 239

5.21.7.4 Format of Host Notify Command ............................................... 240

5.22 Thermal Management ...................................................................................... 241

5.22.1 Thermal Sensor ................................................................................... 241

5.22.1.1 Internal Thermal Sensor Operation............................................ 241

5.22.2 PCH Thermal Throttling ......................................................................... 242

5.22.3 Thermal Reporting Over System Management Link 1 Interface (SMLink1) .... 243

5.22.3.1 Supported Addresses............................................................... 244

5.22.3.2 I

C Write Commands to the Intel® ME ....................................... 245

5.22.3.3 Block Read Command.............................................................. 245

5.22.3.4 Read Data Format................................................................... 247

Datasheet 7

5.22.3.5 Thermal Data Update Rate........................................................247

5.22.3.6 Temperature Comparator and Alert............................................247

5.22.3.7 BIOS Set Up ........................................................................... 249

5.22.3.8 SMBus Rules...........................................................................249

5.22.3.9 Case for Considerations............................................................250

5.23 Intel® High Definition Audio Overview (D27:F0)...................................................252

5.23.1 Intel® High Definition Audio Docking (Mobile Only)....................................252

5.23.1.1 Dock Sequence .......................................................................252

5.23.1.2 Exiting D3/CRST# When Docked ...............................................253

5.23.1.3 Cold Boot/Resume from S3 When Docked...................................254

5.23.1.4 Undock Sequence....................................................................254

5.23.1.5 Normal Undock ....................................................................... 254

5.23.1.6 Surprise Undock...................................................................... 255

5.23.1.7 Interaction between Dock/Undock and Power Management States . 255

5.23.1.8 Relationship between HDA_DOCK_RST# and HDA_RST#..............255

5.24 Intel® ME and Intel® ME Firmware 8.0 ...............................................................256

5.24.1 Intel® ME Requirements ........................................................................257

5.25 Serial Peripheral Interface (SPI) ........................................................................ 258

5.25.1 SPI Supported Feature Overview ............................................................258

5.25.1.1 Non-Descriptor Mode ...............................................................258

5.25.1.2 Descriptor Mode...................................................................... 258

5.25.2 Flash Descriptor ................................................................................... 259

5.25.2.1 Descriptor Master Region ......................................................... 261

5.25.3 Flash Access ........................................................................................262

5.25.3.1 Direct Access Security..............................................................262

5.25.3.2 Register Access Security .......................................................... 262

5.25.4 Serial Flash Device Compatibility Requirements ........................................263

5.25.4.1 PCH SPI Based BIOS Requirements............................................263

5.25.4.2 Integrated LAN Firmware SPI Flash Requirements........................ 263

5.25.4.3 Intel® Management Engine Firmware SPI Flash Requirements ....... 263

5.25.4.4 Hardware Sequencing Requirements.......................................... 264

5.25.5 Multiple Page Write Usage Model............................................................. 265

5.25.5.1 Soft Flash Protection................................................................265

5.25.5.2 BIOS Range Write Protection ....................................................266

5.25.5.3 SMI# Based Global Write Protection........................................... 266

5.25.6 Flash Device Configurations ...................................................................266

5.25.7 SPI Flash Device Recommended Pinout....................................................266

5.25.8 Serial Flash Device Package ...................................................................267

5.25.8.1 Common Footprint Usage Model ................................................267

5.25.8.2 Serial Flash Device Package Recommendations ........................... 267

5.26 Fan Speed Control Signals (Server/Workstation Only)...........................................268

5.26.1 PWM Outputs (Server/Workstation Only) .................................................268

5.26.2 TACH Inputs (Server/Workstation Only)...................................................268

5.27 Feature Capability Mechanism ........................................................................... 268

5.28 PCH Display Interfaces and Intel

Flexible Display Interconnect.............................269

5.28.1 Analog Display Interface Characteristics...................................................270

5.28.1.1 Integrated RAMDAC.................................................................270

5.28.1.2 DDC (Display Data Channel) .....................................................271

5.28.2 Digital Display Interfaces .......................................................................271

5.28.2.1 LVDS (Mobile only)..................................................................271

5.28.2.2 High Definition Multimedia Interface ..........................................273

5.28.2.3 Digital Video Interface* (DVI*) ................................................. 274

5.28.2.4 DisplayPort* ...........................................................................275

5.28.2.5 Embedded DisplayPort* ...........................................................275

5.28.2.6 DisplayPort* Aux Channel......................................................... 275

5.28.2.7 DisplayPort* Hot-Plug Detect (HPD)...........................................276

5.28.2.8 Integrated Audio over HDMI and DisplayPort* .............................276

5.28.2.9 Intel® Serial Digital Video Out (Intel® SDVO).............................. 276

5.28.3 Mapping of Digital Display Interface Signals .............................................277

5.28.4 Multiple Display Configurations ...............................................................279

5.28.5 High-bandwidth Digital Content Protection* (HDCP*).................................281

5.28.6 Intel

Flexible Display Interconnect ........................................................281

5.29 Intel® Virtualization Technology ........................................................................281

5.29.1 Intel® VT-d Objectives ..........................................................................282

5.29.2 Intel® VT-d Features Supported..............................................................282

5.29.3 Support for Function Level Reset (FLR) in PCH.......................................... 282

5.29.4 Virtualization Support for PCH’s IOxAPIC..................................................282

8 Datasheet

5.29.5 Virtualization Support for High Precision Event Timer (HPET)...................... 283

6 Ballout Definition................................................................................................... 285

6.1 Desktop PCH Ballout ........................................................................................ 285

6.2 Mobile PCH Ballout .......................................................................................... 297

6.3 Mobile SFF PCH Ballout .................................................................................... 309

7 Package Information ............................................................................................. 323

7.1 Desktop PCH package ...................................................................................... 323

7.2 Mobile PCH Package......................................................................................... 325

7.3 Mobile SFF PCH Package................................................................................... 327

8 Electrical Characteristics ....................................................................................... 329

8.1 Thermal Specifications ..................................................................................... 329

8.1.1 Desktop Storage Specifications and Thermal Design Power (TDP) ............... 329

8.1.2 Mobile Storage Specifications and Thermal Design Power (TDP) .................. 329

8.2 Absolute Maximum Ratings............................................................................... 330

8.3 PCH Power Supply Range ................................................................................. 331

8.4 General DC Characteristics ............................................................................... 331

8.5 Display DC Characteristics ................................................................................ 344

8.6 AC Characteristics ........................................................................................... 346

8.7 Power Sequencing and Reset Signal Timings ....................................................... 362

8.8 Power Management Timing Diagrams................................................................. 365

8.9 AC Timing Diagrams ........................................................................................ 370

9 Register and Memory Mapping............................................................................... 381

9.1 PCI Devices and Functions................................................................................ 382

9.2 PCI Configuration Map ..................................................................................... 383

9.3 I/O Map ......................................................................................................... 383

9.3.1 Fixed I/O Address Ranges ..................................................................... 383

9.3.2 Variable I/O Decode Ranges .................................................................. 386

9.4 Memory Map................................................................................................... 387

9.4.1 Boot-Block Update Scheme.................................................................... 389

10 Chipset Configuration Registers............................................................................. 391

10.1 Chipset Configuration Registers (Memory Space)................................................. 391

10.1.1 RPC—Root Port Configuration Register .................................................... 393

10.1.2 RPFN—Root Port Function Number and Hide for PCI

Express* Root Ports Register ................................................................. 394

10.1.3 FLRSTAT—Function Level Reset Pending Status Register............................ 395

10.1.4 TRSR—Trap Status Register................................................................... 396

10.1.5 TRCR—Trapped Cycle Register ............................................................... 396

10.1.6 TWDR—Trapped Write Data Register....................................................... 397

10.1.7 IOTRn—I/O Trap Register (0–3) ............................................................. 397

10.1.8 V0CTL—Virtual Channel 0 Resource Control Register ................................. 398

10.1.9 V0STS—Virtual Channel 0 Resource Status Register.................................. 398

10.1.10V1CTL—Virtual Channel 1 Resource Control Register ................................. 399

10.1.11V1STS—Virtual Channel 1 Resource Status Register.................................. 399

10.1.12REC—Root Error Command Register ....................................................... 399

10.1.13LCAP—Link Capabilities Register............................................................. 400

10.1.14LCTL—Link Control Register ................................................................... 400

10.1.15LSTS—Link Status Register.................................................................... 401

10.1.16TCTL—TCO Configuration Register .......................................................... 401

10.1.17D31IP—Device 31 Interrupt Pin Register.................................................. 402

10.1.18D30IP—Device 30 Interrupt Pin Register.................................................. 403

10.1.19D29IP—Device 29 Interrupt Pin Register.................................................. 403

10.1.20D28IP—Device 28 Interrupt Pin Register.................................................. 403

10.1.21D27IP—Device 27 Interrupt Pin Register.................................................. 405

10.1.22D26IP—Device 26 Interrupt Pin Register.................................................. 405

10.1.23D25IP—Device 25 Interrupt Pin Register.................................................. 405

10.1.24D22IP—Device 22 Interrupt Pin Register.................................................. 406

10.1.25D20IP—Device 20 Interrupt Pin Register.................................................. 406

10.1.26D31IR—Device 31 Interrupt Route Register ............................................. 407

10.1.27D29IR—Device 29 Interrupt Route Register ............................................. 408

10.1.28D28IR—Device 28 Interrupt Route Register ............................................. 409

10.1.29D27IR—Device 27 Interrupt Route Register ............................................. 410

10.1.30D26IR—Device 26 Interrupt Route Register ............................................. 411

10.1.31D25IR—Device 25 Interrupt Route Register ............................................. 412

Datasheet 9

10.1.32D22IR—Device 22 Interrupt Route Register.............................................. 413

10.1.33D20IR—Device 20 Interrupt Route Register.............................................. 414

10.1.34OIC—Other Interrupt Control Register .....................................................415

10.1.35PRSTS—Power and Reset Status Register................................................. 416

10.1.36PM_CFG—Power Management Configuration Register................................. 417

10.1.37DEEP_S3_POL—Deep Sx From S3 Power Policies Register .......................... 418

10.1.38DEEP_S4_POL—Deep Sx From S4 Power Policies Register .......................... 418

10.1.39DEEP_S5_POL—Deep Sx From S5 Power Policies Register .......................... 418

10.1.40PMSYNC_CFG—PMSYNC Configuration ..................................................... 419

10.1.41RC—RTC Configuration Register.............................................................. 419

10.1.42HPTC—High Precision Timer Configuration Register ................................... 420

10.1.43GCS—General Control and Status Register ...............................................420

10.1.44BUC—Backed Up Control Register ...........................................................422

10.1.45FD—Function Disable Register ................................................................423

10.1.46CG—Clock Gating Register ..................................................................... 425

10.1.47FDSW—Function Disable SUS Well Register ..............................................426

10.1.48DISPBDF—Display Bus, Device and Function

Initialization Register ............................................................................426

10.1.49FD2—Function Disable 2 Register ............................................................ 427

10.1.50MISCCTL—Miscellaneous Control Register ................................................427

10.1.51USBOCM1—Overcurrent MAP Register 1...................................................428

10.1.52USBOCM2—Overcurrent MAP Register 2...................................................429

10.1.53RMHWKCTL—Rate Matching Hub Wake Control Register.............................430

11 PCI-to-PCI Bridge Registers (D30:F0)....................................................................433

11.1 PCI Configuration Registers (D30:F0) .................................................................433

11.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0)............................. 434

11.1.2 DID— Device Identification Register (PCI-PCI—D30:F0) ............................. 434

11.1.3 PCICMD—PCI Command Register (PCI-PCI—D30:F0).................................434

11.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0) ..........................................435

11.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)............................ 437

11.1.6 CC—Class Code Register (PCI-PCI—D30:F0).............................................437

11.1.7 PMLT—Primary Master Latency Timer Register

(PCI-PCI—D30:F0)................................................................................437

11.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0) .................................438

11.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0) ......................................438

11.1.10SMLT—Secondary Master Latency Timer Register

(PCI-PCI—D30:F0)................................................................................438

11.1.11IOBASE_LIMIT—I/O Base and Limit Register

(PCI-PCI—D30:F0)................................................................................439

11.1.12SECSTS—Secondary Status Register (PCI-PCI—D30:F0) ............................440

11.1.13MEMBASE_LIMIT—Memory Base and Limit Register

(PCI-PCI—D30:F0)................................................................................441

11.1.14PREF_MEM_BASE_LIMIT—Prefetchable Memory Base

and Limit Register (PCI-PCI—D30:F0) .....................................................441

11.1.15PMBU32—Prefetchable Memory Base Upper 32 Bits

11.1.16PMLU32—Prefetchable Memory Limit Upper 32 Bits

11.1.17CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) .......................... 442

11.1.18INTR—Interrupt Information Register (PCI-PCI—D30:F0) ........................... 442

11.1.19BCTRL—Bridge Control Register (PCI-PCI—D30:F0) ...................................443

11.1.20SPDH—Secondary PCI Device Hiding Register

(PCI-PCI—D30:F0)................................................................................444

11.1.21DTC—Delayed Transaction Control Register

(PCI-PCI—D30:F0)................................................................................445

11.1.22BPS—Bridge Proprietary Status Register

(PCI-PCI—D30:F0)................................................................................446

11.1.23BPC—Bridge Policy Configuration Register

(PCI-PCI—D30:F0)................................................................................447

11.1.24SVCAP—Subsystem Vendor Capability Register

(PCI-PCI—D30:F0)................................................................................448

11.1.25SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0) ......................... 448

12 Gigabit LAN Configuration Registers ......................................................................449

12.1 Gigabit LAN Configuration Registers

(Gigabit LAN — D25:F0) ...................................................................................449

10 Datasheet

12.1.1 VID—Vendor Identification Register

(Gigabit LAN—D25:F0).......................................................................... 450

12.1.2 DID—Device Identification Register

(Gigabit LAN—D25:F0).......................................................................... 450

12.1.3 PCICMD—PCI Command Register

(Gigabit LAN—D25:F0).......................................................................... 451

12.1.4 PCISTS—PCI Status Register

(Gigabit LAN—D25:F0).......................................................................... 452

12.1.5 RID—Revision Identification Register