Intel C216 Datasheet

Intel® 7 Series / C216 Chipset Family Platform Controller Hub (PCH)

Datasheet

June 2012

Order Number: 326776-003

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2

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2 Datasheet

Contents

1Introduction............................................................................................................ 43

1.1 About This Manual............................................................................................. 43

1.2 Overview ......................................................................................................... 46

1.2.1 Capability Overview ................................................................................ 47

1.3 Intel

2 Signal Description ................................................................................................... 57

2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 59

2.2 PCI Express* .................................................................................................... 59

2.3 PCI Interface .................................................................................................... 60

2.4 Serial ATA Interface........................................................................................... 63

2.5 LPC Interface.................................................................................................... 66

2.6 Interrupt Interface ............................................................................................ 66

2.7 USB Interface ................................................................................................... 67

2.8 Power Management Interface.............................................................................. 69

2.9 Processor Interface............................................................................................ 73

2.10 SMBus Interface................................................................................................ 73

2.11 System Management Interface............................................................................ 74

2.12 Real Time Clock Interface................................................................................... 74

2.13 Miscellaneous Signals ........................................................................................ 75

2.14 Intel

2.15 Controller Link .................................................................................................. 77

2.16 Serial Peripheral Interface (SPI) .......................................................................... 77

2.17 Thermal Signals ................................................................................................ 78

2.18 Testability Signals ............................................................................................. 78

2.19 Clock Signals .................................................................................................... 79

2.20 LVDS Signals .................................................................................................... 81

2.21 Analog Display /VGA DAC Signals ........................................................................ 82

2.22 Intel® Flexible Display Interface (Intel® FDI) ........................................................ 82

2.23 Digital Display Signals........................................................................................ 83

2.24 General Purpose I/O Signals ............................................................................... 85

2.25 Manageability Signals ........................................................................................ 90

2.26 Power and Ground Signals.................................................................................. 90

2.27 Pin Straps ........................................................................................................ 93

2.28 External RTC Circuitry........................................................................................ 97

3PCH Pin States......................................................................................................... 99

3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 99

3.2 Output and I/O Signals Planes and States........................................................... 101

3.3 Power Planes for Input Signals .......................................................................... 113

4 PCH and System Clocks ......................................................................................... 119

4.1 Platform Clocking Requirements ........................................................................ 119

4.2 Functional Blocks ............................................................................................ 122

4.3 Clock Configuration Access Overview ................................................................. 123

4.4 Straps Related to Clock Configuration ................................................................ 123

5 Functional Description........................................................................................... 125

5.1 PCI-to-PCI Bridge (D30:F0) .............................................................................. 125

®

7 Series / C216 Chipset Family SKU Definition ............................................. 54

®

High Definition Audio Link ......................................................................... 76

5.1.1 PCI Bus Interface ................................................................................. 125

5.1.2 PCI Bridge As an Initiator ...................................................................... 126

5.1.3 Parity Error Detection and Generation ..................................................... 127

5.1.4 PCIRST#............................................................................................. 128

5.1.5 Peer Cycles ......................................................................................... 128

5.1.2.1 Memory Reads and Writes........................................................ 126

5.1.2.2 I/O Reads and Writes .............................................................. 126

5.1.2.3 Configuration Reads and Writes ................................................ 126

5.1.2.4 Locked Cycles ........................................................................ 126

5.1.2.5 Target / Master Aborts............................................................. 126

5.1.2.6 Secondary Master Latency Timer............................................... 126

5.1.2.7 Dual Address Cycle (DAC)........................................................ 127

5.1.2.8 Memory and I/O Decode to PCI................................................. 127

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5.1.6 PCI-to-PCI Bridge Model ........................................................................ 128

5.1.7 IDSEL to Device Number Mapping ........................................................... 129

5.1.8 Standard PCI Bus Configuration Mechanism.............................................. 129

5.1.9 PCI Legacy Mode ..................................................................................129

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) ..................................... 129

5.2.1 Interrupt Generation ............................................................................. 130

5.2.2 Power Management............................................................................... 130

5.2.2.1 S3/S4/S5 Support ...................................................................130

5.2.2.2 Resuming from Suspended State............................................... 131

5.2.2.3 Device Initiated PM_PME Message ............................................. 131

5.2.2.4 SMI/SCI Generation................................................................. 131

5.2.3 SERR# Generation................................................................................132

5.2.4 Hot-Plug.............................................................................................. 132

5.2.4.1 Presence Detection.................................................................. 132

5.2.4.2 Message Generation ................................................................132

5.2.4.3 Attention Button Detection ....................................................... 133

5.2.4.4 SMI/SCI Generation................................................................. 133

5.3 Gigabit Ethernet Controller (B0:D25:F0) .............................................................134

5.3.1 GbE PCI Express* Bus Interface..............................................................135

5.3.1.1 Transaction Layer....................................................................135

5.3.1.2 Data Alignment....................................................................... 135

5.3.1.3 Configuration Request Retry Status ........................................... 136

5.3.2 Error Events and Error Reporting ............................................................136

5.3.2.1 Data Parity Error .....................................................................136

5.3.2.2 Completion with Unsuccessful Completion Status......................... 136

5.3.3 Ethernet Interface ................................................................................ 136

5.3.3.1 82579 LAN PHY Interface .........................................................136

5.3.4 PCI Power Management .........................................................................137

5.3.4.1 Wake Up ................................................................................137

5.3.5 Configurable LEDs.................................................................................139

5.3.6 Function Level Reset Support (FLR).........................................................140

5.3.6.1 FLR Steps...............................................................................140

5.4 LPC Bridge (with System and Management Functions) (D31:F0).............................140

5.4.1 LPC Interface ....................................................................................... 140

5.4.1.1 LPC Cycle Types......................................................................141

5.4.1.2 Start Field Definition ................................................................142

5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR)..................................... 142

5.4.1.4 Size.......................................................................................142

5.4.1.5 SYNC..................................................................................... 143

5.4.1.6 SYNC Time-Out.......................................................................143

5.4.1.7 SYNC Error Indication ..............................................................143

5.4.1.8 LFRAME# Usage...................................................................... 143

5.4.1.9 I/O Cycles ..............................................................................144

5.4.1.10 Bus Master Cycles ................................................................... 144

5.4.1.11 LPC Power Management ........................................................... 144

5.4.1.12 Configuration and PCH Implications ...........................................144

5.5 DMA Operation (D31:F0) ..................................................................................145

5.5.1 Channel Priority....................................................................................145

5.5.1.1 Fixed Priority ..........................................................................145

5.5.1.2 Rotating Priority......................................................................146

5.5.2 Address Compatibility Mode ...................................................................146

5.5.3 Summary of DMA Transfer Sizes .............................................................146

5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words 146

5.5.4 Autoinitialize ........................................................................................ 147

5.5.5 Software Commands ............................................................................. 147

5.6 LPC DMA ........................................................................................................147

5.6.1 Asserting DMA Requests ........................................................................147

5.6.2 Abandoning DMA Requests.....................................................................148

5.6.3 General Flow of DMA Transfers ...............................................................149

5.6.4 Terminal Count..................................................................................... 149

5.6.5 Verify Mode .........................................................................................149

5.6.6 DMA Request Deassertion ......................................................................149

5.6.7 SYNC Field / LDRQ# Rules .....................................................................150

5.7 8254 Timers (D31:F0) ...................................................................................... 151

5.7.1 Timer Programming ..............................................................................151

5.7.2 Reading from the Interval Timer ............................................................. 152

5.7.2.1 Simple Read ........................................................................... 152

4 Datasheet

5.7.2.2 Counter Latch Command.......................................................... 153

5.7.2.3 Read Back Command .............................................................. 153

5.8 8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 154

5.8.1 Interrupt Handling................................................................................ 155

5.8.1.1 Generating Interrupts.............................................................. 155

5.8.1.2 Acknowledging Interrupts ........................................................ 155

5.8.1.3 Hardware/Software Interrupt Sequence ..................................... 156

5.8.2 Initialization Command Words (ICWx)..................................................... 156

5.8.2.1 ICW1 .................................................................................... 156

5.8.2.2 ICW2 .................................................................................... 157

5.8.2.3 ICW3 .................................................................................... 157

5.8.2.4 ICW4 .................................................................................... 157

5.8.3 Operation Command Words (OCW)......................................................... 157

5.8.4 Modes of Operation .............................................................................. 157

5.8.4.1 Fully Nested Mode................................................................... 157

5.8.4.2 Special Fully-Nested Mode........................................................ 158

5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 158

5.8.4.4 Specific Rotation Mode (Specific Priority).................................... 158

5.8.4.5 Poll Mode............................................................................... 158

5.8.4.6 Edge and Level Triggered Mode ................................................ 159

5.8.4.7 End of Interrupt (EOI) Operations ............................................. 159

5.8.4.8 Normal End of Interrupt........................................................... 159

5.8.4.9 Automatic End of Interrupt Mode .............................................. 159

5.8.5 Masking Interrupts ............................................................................... 159

5.8.5.1 Masking on an Individual Interrupt Request................................ 159

5.8.5.2 Special Mask Mode.................................................................. 160

5.8.6 Steering PCI Interrupts ......................................................................... 160

5.9 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 160

5.9.1 Interrupt Handling................................................................................ 160

5.9.2 Interrupt Mapping ................................................................................ 161

5.9.3 PCI/PCI Express* Message-Based Interrupts ............................................ 162

5.9.4 IOxAPIC Address Remapping ................................................................. 162

5.9.5 External Interrupt Controller Support ...................................................... 162

5.10 Serial Interrupt (D31:F0) ................................................................................. 162

5.10.1 Start Frame......................................................................................... 163

5.10.2 Data Frames........................................................................................ 163

5.10.3 Stop Frame ......................................................................................... 163

5.10.4 Specific Interrupts Not Supported Using SERIRQ ...................................... 164

5.10.5 Data Frame Format .............................................................................. 164

5.11 Real Time Clock (D31:F0)................................................................................. 165

5.11.1 Update Cycles...................................................................................... 165

5.11.2 Interrupts ........................................................................................... 166

5.11.3 Lockable RAM Ranges ........................................................................... 166

5.11.4 Century Rollover .................................................................................. 166

5.11.5 Clearing Battery-Backed RTC RAM .......................................................... 166

5.12 Processor Interface (D31:F0) ............................................................................ 168

5.12.1 Processor Interface Signals and VLW Messages ........................................ 168

5.12.1.1 INIT (Initialization) ................................................................. 168

5.12.1.2 FERR# (Numeric Coprocessor Error).......................................... 169

5.12.1.3 NMI (Non-Maskable Interrupt) .................................................. 169

5.12.1.4 Processor Power Good (PROCPWRGD) ....................................... 169

5.12.2 Dual-Processor Issues........................................................................... 169

5.12.2.1 Usage Differences ................................................................... 169

5.12.3 Virtual Legacy Wire (VLW) Messages....................................................... 170

5.13 Power Management ......................................................................................... 170

5.13.1 Features ............................................................................................. 170

5.13.2 PCH and System Power States ............................................................... 171

5.13.3 System Power Planes............................................................................ 173

5.13.4 SMI#/SCI Generation ........................................................................... 173

5.13.4.1 PCI Express* SCI.................................................................... 175

5.13.4.2 PCI Express* Hot-Plug............................................................. 175

5.13.5 C-States ............................................................................................. 176

5.13.6 Dynamic PCI Clock Control (Mobile Only)................................................. 176

5.13.6.1 Conditions for Checking the PCI Clock........................................ 176

5.13.6.2 Conditions for Maintaining the PCI Clock .................................... 176

5.13.6.3 Conditions for Stopping the PCI Clock........................................ 176

5.13.6.4 Conditions for Re-Starting the PCI Clock .................................... 177

Datasheet 5

5.13.7 Sleep States ........................................................................................177

5.13.6.5 LPC Devices and CLKRUN# .......................................................177

5.13.7.1 Sleep State Overview...............................................................177

5.13.7.2 Initiating Sleep State ...............................................................177

5.13.7.3 Exiting Sleep States................................................................. 178

5.13.7.4 PCI Express* WAKE# Signal and PME Event Message................... 180

5.13.7.5 Sx-G3-Sx, Handling Power Failures............................................180

5.13.7.6 Deep Sx.................................................................................181

5.13.8 Event Input Signals and Their Usage .......................................................182

5.13.8.1 PWRBTN# (Power Button) ........................................................ 182

5.13.8.2 RI# (Ring Indicator) ................................................................ 184

5.13.8.3 PME# (PCI Power Management Event) .......................................184

5.13.8.4 SYS_RESET# Signal ................................................................184

5.13.8.5 THRMTRIP# Signal .................................................................. 184

5.13.9 ALT Access Mode ..................................................................................185

5.13.9.1 Write Only Registers with Read Paths in ALT Access Mode............. 186

5.13.9.2 PIC Reserved Bits....................................................................188

5.13.9.3 Read Only Registers with Write Paths in ALT Access Mode............. 188

5.13.10System Power Supplies, Planes, and Signals.............................................188

5.13.10.1Power Plane Control with SLP_S3#,

SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN#............................... 188

5.13.10.2SLP_S4# and Suspend-To-RAM Sequencing................................189

5.13.10.3PWROK Signal ........................................................................ 189

5.13.10.4BATLOW# (Battery Low) (Mobile Only).......................................189

5.13.10.5SLP_LAN# Pin Behavior............................................................190

5.13.10.6RTCRST# and SRTCRST# .........................................................190

5.13.10.7SUSPWRDNACK/SUSWARN#/GPIO30 Pin Behavior ......................191

5.13.11Legacy Power Management Theory of Operation .......................................191

5.13.11.1APM Power Management (Desktop Only) ....................................191

5.13.11.2Mobile APM Power Management (Mobile Only) ............................. 192

5.13.12Reset Behavior .....................................................................................192

5.14 System Management (D31:F0) ..........................................................................194

5.14.1 Theory of Operation .............................................................................. 194

5.14.1.1 Detecting a System Lockup....................................................... 194

5.14.1.2 Handling an Intruder ...............................................................194

5.14.1.3 Detecting Improper Flash Programming......................................195

5.14.1.4 Heartbeat and Event Reporting using SMLink/SMBus....................195

5.14.2 TCO Modes ..........................................................................................196

5.14.2.1 TCO Legacy/Compatible Mode...................................................196

5.14.2.2 Advanced TCO Mode................................................................ 197

5.15 General Purpose I/O (D31:F0)...........................................................................198

5.15.1 Power Wells ......................................................................................... 198

5.15.2 SMI# SCI and NMI Routing ....................................................................198

5.15.3 Triggering............................................................................................198

5.15.4 GPIO Registers Lockdown ......................................................................198

5.15.5 Serial POST Codes over GPIO .................................................................199

5.15.5.1 Theory of Operation................................................................. 199

5.15.5.2 Serial Message Format.............................................................200

5.16 SATA Host Controller (D31:F2, F5)..................................................................... 201

5.16.1 SATA 6 Gb/s Support ............................................................................202

5.16.2 SATA Feature Support ...........................................................................202

5.16.3 Theory of Operation .............................................................................. 203

5.16.3.1 Standard ATA Emulation...........................................................203

5.16.3.2 48-Bit LBA Operation ...............................................................203

5.16.4 SATA Swap Bay Support........................................................................203

5.16.5 Hot Plug Operation................................................................................203

5.16.6 Function Level Reset Support (FLR)......................................................... 204

5.16.6.1 FLR Steps...............................................................................204

®

5.16.7 Intel

5.16.8 Intel

Rapid Storage Technology Configuration.........................................204

5.16.7.1 Intel® Rapid Storage Technology RAID Option ROM .....................205

®

Smart Response Technology .........................................................205

5.16.9 Power Management Operation ................................................................206

5.16.9.1 Power State Mappings.............................................................. 206

5.16.9.2 Power State Transitions............................................................ 206

5.16.9.3 SMI Trapping (APM).................................................................207

5.16.10SATA Device Presence ........................................................................... 207

5.16.11SATA LED ............................................................................................208

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5.16.12AHCI Operation.................................................................................... 208

5.16.13SGPIO Signals ..................................................................................... 209

5.16.13.1Mechanism ............................................................................ 209

5.16.13.2Message Format ..................................................................... 210

5.16.13.3LED Message Type .................................................................. 210

5.16.13.4SGPIO Waveform.................................................................... 212

5.16.14External SATA...................................................................................... 213

5.17 High Precision Event Timers.............................................................................. 213

5.17.1 Timer Accuracy .................................................................................... 213

5.17.2 Interrupt Mapping ................................................................................ 214

5.17.3 Periodic vs. Non-Periodic Modes ............................................................. 214

5.17.4 Enabling the Timers.............................................................................. 215

5.17.5 Interrupt Levels ................................................................................... 215

5.17.6 Handling Interrupts .............................................................................. 216

5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 216

5.18 USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. 217

5.18.1 EHC Initialization.................................................................................. 217

5.18.1.1 BIOS Initialization................................................................... 217

5.18.1.2 Driver Initialization ................................................................. 217

5.18.1.3 EHC Resets ............................................................................ 217

5.18.2 Data Structures in Main Memory............................................................. 217

5.18.3 USB 2.0 Enhanced Host Controller DMA................................................... 218

5.18.4 Data Encoding and Bit Stuffing............................................................... 218

5.18.5 Packet Formats .................................................................................... 218

5.18.6 USB 2.0 Interrupts and Error Conditions.................................................. 218

5.18.6.1 Aborts on USB 2.0-Initiated Memory Reads ................................ 219

5.18.7 USB 2.0 Power Management.................................................................. 219

5.18.7.1 Pause Feature ........................................................................ 219

5.18.7.2 Suspend Feature..................................................................... 219

5.18.7.3 ACPI Device States ................................................................. 219

5.18.7.4 ACPI System States ................................................................ 220

5.18.8 USB 2.0 Legacy Keyboard Operation....................................................... 220

5.18.9 USB 2.0 Based Debug Port .................................................................... 220

5.18.9.1 Theory of Operation ............................................................... 221

5.18.10EHCI Caching....................................................................................... 225

5.18.11Intel® USB Pre-Fetch Based Pause ......................................................... 225

5.18.12Function Level Reset Support (FLR) ........................................................ 225

5.18.12.1FLR Steps .............................................................................. 225

5.18.13USB Overcurrent Protection ................................................................... 226

5.19 Integrated USB 2.0 Rate Matching Hub .............................................................. 227

5.19.1 Overview ............................................................................................ 227

5.19.2 Architecture......................................................................................... 227

5.20 xHCI Controller (D20:F0) ................................................................................. 227

5.21 SMBus Controller (D31:F3)............................................................................... 228

5.21.1 Host Controller..................................................................................... 228

5.21.1.1 Command Protocols ................................................................ 229

5.21.2 Bus Arbitration..................................................................................... 232

5.21.3 Bus Timing .......................................................................................... 233

5.21.3.1 Clock Stretching ..................................................................... 233

5.21.3.2 Bus Time Out (The PCH as SMBus Master) ................................. 233

5.21.4 Interrupts / SMI#................................................................................. 233

5.21.5 SMBALERT# ........................................................................................ 234

5.21.6 SMBus CRC Generation and Checking...................................................... 234

5.21.7 SMBus Slave Interface .......................................................................... 235

5.21.7.1 Format of Slave Write Cycle ..................................................... 236

5.21.7.2 Format of Read Command........................................................ 237

5.21.7.3 Slave Read of RTC Time Bytes.................................................. 239

5.21.7.4 Format of Host Notify Command ............................................... 240

5.22 Thermal Management ...................................................................................... 241

5.22.1 Thermal Sensor ................................................................................... 241

5.22.1.1 Internal Thermal Sensor Operation............................................ 241

5.22.2 PCH Thermal Throttling ......................................................................... 242

5.22.3 Thermal Reporting Over System Management Link 1 Interface (SMLink1) .... 243

5.22.3.1 Supported Addresses............................................................... 244

5.22.3.2 I

2

C Write Commands to the Intel® ME ....................................... 245

5.22.3.3 Block Read Command.............................................................. 245

5.22.3.4 Read Data Format................................................................... 247

Datasheet 7

5.22.3.5 Thermal Data Update Rate........................................................247

5.22.3.6 Temperature Comparator and Alert............................................247

5.22.3.7 BIOS Set Up ........................................................................... 249

5.22.3.8 SMBus Rules...........................................................................249

5.22.3.9 Case for Considerations............................................................250

5.23 Intel® High Definition Audio Overview (D27:F0)...................................................252

5.23.1 Intel® High Definition Audio Docking (Mobile Only)....................................252

5.23.1.1 Dock Sequence .......................................................................252

5.23.1.2 Exiting D3/CRST# When Docked ...............................................253

5.23.1.3 Cold Boot/Resume from S3 When Docked...................................254

5.23.1.4 Undock Sequence....................................................................254

5.23.1.5 Normal Undock ....................................................................... 254

5.23.1.6 Surprise Undock...................................................................... 255

5.23.1.7 Interaction between Dock/Undock and Power Management States . 255

5.23.1.8 Relationship between HDA_DOCK_RST# and HDA_RST#..............255

5.24 Intel® ME and Intel® ME Firmware 8.0 ...............................................................256

5.24.1 Intel® ME Requirements ........................................................................257

5.25 Serial Peripheral Interface (SPI) ........................................................................ 258

5.25.1 SPI Supported Feature Overview ............................................................258

5.25.1.1 Non-Descriptor Mode ...............................................................258

5.25.1.2 Descriptor Mode...................................................................... 258

5.25.2 Flash Descriptor ................................................................................... 259

5.25.2.1 Descriptor Master Region ......................................................... 261

5.25.3 Flash Access ........................................................................................262

5.25.3.1 Direct Access Security..............................................................262

5.25.3.2 Register Access Security .......................................................... 262

5.25.4 Serial Flash Device Compatibility Requirements ........................................263

5.25.4.1 PCH SPI Based BIOS Requirements............................................263

5.25.4.2 Integrated LAN Firmware SPI Flash Requirements........................ 263

5.25.4.3 Intel® Management Engine Firmware SPI Flash Requirements ....... 263

5.25.4.4 Hardware Sequencing Requirements.......................................... 264

5.25.5 Multiple Page Write Usage Model............................................................. 265

5.25.5.1 Soft Flash Protection................................................................265

5.25.5.2 BIOS Range Write Protection ....................................................266

5.25.5.3 SMI# Based Global Write Protection........................................... 266

5.25.6 Flash Device Configurations ...................................................................266

5.25.7 SPI Flash Device Recommended Pinout....................................................266

5.25.8 Serial Flash Device Package ...................................................................267

5.25.8.1 Common Footprint Usage Model ................................................267

5.25.8.2 Serial Flash Device Package Recommendations ........................... 267

5.26 Fan Speed Control Signals (Server/Workstation Only)...........................................268

5.26.1 PWM Outputs (Server/Workstation Only) .................................................268

5.26.2 TACH Inputs (Server/Workstation Only)...................................................268

5.27 Feature Capability Mechanism ........................................................................... 268

5.28 PCH Display Interfaces and Intel

®

Flexible Display Interconnect.............................269

5.28.1 Analog Display Interface Characteristics...................................................270

5.28.1.1 Integrated RAMDAC.................................................................270

5.28.1.2 DDC (Display Data Channel) .....................................................271

5.28.2 Digital Display Interfaces .......................................................................271

5.28.2.1 LVDS (Mobile only)..................................................................271

5.28.2.2 High Definition Multimedia Interface ..........................................273

5.28.2.3 Digital Video Interface* (DVI*) ................................................. 274

5.28.2.4 DisplayPort* ...........................................................................275

5.28.2.5 Embedded DisplayPort* ...........................................................275

5.28.2.6 DisplayPort* Aux Channel......................................................... 275

5.28.2.7 DisplayPort* Hot-Plug Detect (HPD)...........................................276

5.28.2.8 Integrated Audio over HDMI and DisplayPort* .............................276

5.28.2.9 Intel® Serial Digital Video Out (Intel® SDVO).............................. 276

5.28.3 Mapping of Digital Display Interface Signals .............................................277

5.28.4 Multiple Display Configurations ...............................................................279

5.28.5 High-bandwidth Digital Content Protection* (HDCP*).................................281

5.28.6 Intel

®

Flexible Display Interconnect ........................................................281

5.29 Intel® Virtualization Technology ........................................................................281

5.29.1 Intel® VT-d Objectives ..........................................................................282

5.29.2 Intel® VT-d Features Supported..............................................................282

5.29.3 Support for Function Level Reset (FLR) in PCH.......................................... 282

5.29.4 Virtualization Support for PCH’s IOxAPIC..................................................282

8 Datasheet

5.29.5 Virtualization Support for High Precision Event Timer (HPET)...................... 283

6 Ballout Definition................................................................................................... 285

6.1 Desktop PCH Ballout ........................................................................................ 285

6.2 Mobile PCH Ballout .......................................................................................... 297

6.3 Mobile SFF PCH Ballout .................................................................................... 309

7 Package Information ............................................................................................. 323

7.1 Desktop PCH package ...................................................................................... 323

7.2 Mobile PCH Package......................................................................................... 325

7.3 Mobile SFF PCH Package................................................................................... 327

8 Electrical Characteristics ....................................................................................... 329

8.1 Thermal Specifications ..................................................................................... 329

8.1.1 Desktop Storage Specifications and Thermal Design Power (TDP) ............... 329

8.1.2 Mobile Storage Specifications and Thermal Design Power (TDP) .................. 329

8.2 Absolute Maximum Ratings............................................................................... 330

8.3 PCH Power Supply Range ................................................................................. 331

8.4 General DC Characteristics ............................................................................... 331

8.5 Display DC Characteristics ................................................................................ 344

8.6 AC Characteristics ........................................................................................... 346

8.7 Power Sequencing and Reset Signal Timings ....................................................... 362

8.8 Power Management Timing Diagrams................................................................. 365

8.9 AC Timing Diagrams ........................................................................................ 370

9 Register and Memory Mapping............................................................................... 381

9.1 PCI Devices and Functions................................................................................ 382

9.2 PCI Configuration Map ..................................................................................... 383

9.3 I/O Map ......................................................................................................... 383

9.3.1 Fixed I/O Address Ranges ..................................................................... 383

9.3.2 Variable I/O Decode Ranges .................................................................. 386

9.4 Memory Map................................................................................................... 387

9.4.1 Boot-Block Update Scheme.................................................................... 389

10 Chipset Configuration Registers............................................................................. 391

10.1 Chipset Configuration Registers (Memory Space)................................................. 391

10.1.1 RPC—Root Port Configuration Register .................................................... 393

10.1.2 RPFN—Root Port Function Number and Hide for PCI

Express* Root Ports Register ................................................................. 394

10.1.3 FLRSTAT—Function Level Reset Pending Status Register............................ 395

10.1.4 TRSR—Trap Status Register................................................................... 396

10.1.5 TRCR—Trapped Cycle Register ............................................................... 396

10.1.6 TWDR—Trapped Write Data Register....................................................... 397

10.1.7 IOTRn—I/O Trap Register (0–3) ............................................................. 397

10.1.8 V0CTL—Virtual Channel 0 Resource Control Register ................................. 398

10.1.9 V0STS—Virtual Channel 0 Resource Status Register.................................. 398

10.1.10V1CTL—Virtual Channel 1 Resource Control Register ................................. 399

10.1.11V1STS—Virtual Channel 1 Resource Status Register.................................. 399

10.1.12REC—Root Error Command Register ....................................................... 399

10.1.13LCAP—Link Capabilities Register............................................................. 400

10.1.14LCTL—Link Control Register ................................................................... 400

10.1.15LSTS—Link Status Register.................................................................... 401

10.1.16TCTL—TCO Configuration Register .......................................................... 401

10.1.17D31IP—Device 31 Interrupt Pin Register.................................................. 402

10.1.18D30IP—Device 30 Interrupt Pin Register.................................................. 403

10.1.19D29IP—Device 29 Interrupt Pin Register.................................................. 403

10.1.20D28IP—Device 28 Interrupt Pin Register.................................................. 403

10.1.21D27IP—Device 27 Interrupt Pin Register.................................................. 405

10.1.22D26IP—Device 26 Interrupt Pin Register.................................................. 405

10.1.23D25IP—Device 25 Interrupt Pin Register.................................................. 405

10.1.24D22IP—Device 22 Interrupt Pin Register.................................................. 406

10.1.25D20IP—Device 20 Interrupt Pin Register.................................................. 406

10.1.26D31IR—Device 31 Interrupt Route Register ............................................. 407

10.1.27D29IR—Device 29 Interrupt Route Register ............................................. 408

10.1.28D28IR—Device 28 Interrupt Route Register ............................................. 409

10.1.29D27IR—Device 27 Interrupt Route Register ............................................. 410

10.1.30D26IR—Device 26 Interrupt Route Register ............................................. 411

10.1.31D25IR—Device 25 Interrupt Route Register ............................................. 412

Datasheet 9

10.1.32D22IR—Device 22 Interrupt Route Register.............................................. 413

10.1.33D20IR—Device 20 Interrupt Route Register.............................................. 414

10.1.34OIC—Other Interrupt Control Register .....................................................415

10.1.35PRSTS—Power and Reset Status Register................................................. 416

10.1.36PM_CFG—Power Management Configuration Register................................. 417

10.1.37DEEP_S3_POL—Deep Sx From S3 Power Policies Register .......................... 418

10.1.38DEEP_S4_POL—Deep Sx From S4 Power Policies Register .......................... 418

10.1.39DEEP_S5_POL—Deep Sx From S5 Power Policies Register .......................... 418

10.1.40PMSYNC_CFG—PMSYNC Configuration ..................................................... 419

10.1.41RC—RTC Configuration Register.............................................................. 419

10.1.42HPTC—High Precision Timer Configuration Register ................................... 420

10.1.43GCS—General Control and Status Register ...............................................420

10.1.44BUC—Backed Up Control Register ...........................................................422

10.1.45FD—Function Disable Register ................................................................423

10.1.46CG—Clock Gating Register ..................................................................... 425

10.1.47FDSW—Function Disable SUS Well Register ..............................................426

10.1.48DISPBDF—Display Bus, Device and Function

Initialization Register ............................................................................426

10.1.49FD2—Function Disable 2 Register ............................................................ 427

10.1.50MISCCTL—Miscellaneous Control Register ................................................427

10.1.51USBOCM1—Overcurrent MAP Register 1...................................................428

10.1.52USBOCM2—Overcurrent MAP Register 2...................................................429

10.1.53RMHWKCTL—Rate Matching Hub Wake Control Register.............................430

11 PCI-to-PCI Bridge Registers (D30:F0)....................................................................433

11.1 PCI Configuration Registers (D30:F0) .................................................................433

11.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0)............................. 434

11.1.2 DID— Device Identification Register (PCI-PCI—D30:F0) ............................. 434

11.1.3 PCICMD—PCI Command Register (PCI-PCI—D30:F0).................................434

11.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0) ..........................................435

11.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)............................ 437

11.1.6 CC—Class Code Register (PCI-PCI—D30:F0).............................................437

11.1.7 PMLT—Primary Master Latency Timer Register

(PCI-PCI—D30:F0)................................................................................437

11.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0) .................................438

11.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0) ......................................438

11.1.10SMLT—Secondary Master Latency Timer Register

(PCI-PCI—D30:F0)................................................................................438

11.1.11IOBASE_LIMIT—I/O Base and Limit Register

(PCI-PCI—D30:F0)................................................................................439

11.1.12SECSTS—Secondary Status Register (PCI-PCI—D30:F0) ............................440

11.1.13MEMBASE_LIMIT—Memory Base and Limit Register

(PCI-PCI—D30:F0)................................................................................441

11.1.14PREF_MEM_BASE_LIMIT—Prefetchable Memory Base

and Limit Register (PCI-PCI—D30:F0) .....................................................441

11.1.15PMBU32—Prefetchable Memory Base Upper 32 Bits

Register (PCI-PCI—D30:F0) ...................................................................442

11.1.16PMLU32—Prefetchable Memory Limit Upper 32 Bits

Register (PCI-PCI—D30:F0) ...................................................................442

11.1.17CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) .......................... 442

11.1.18INTR—Interrupt Information Register (PCI-PCI—D30:F0) ........................... 442

11.1.19BCTRL—Bridge Control Register (PCI-PCI—D30:F0) ...................................443

11.1.20SPDH—Secondary PCI Device Hiding Register

(PCI-PCI—D30:F0)................................................................................444

11.1.21DTC—Delayed Transaction Control Register

(PCI-PCI—D30:F0)................................................................................445

11.1.22BPS—Bridge Proprietary Status Register

(PCI-PCI—D30:F0)................................................................................446

11.1.23BPC—Bridge Policy Configuration Register

(PCI-PCI—D30:F0)................................................................................447

11.1.24SVCAP—Subsystem Vendor Capability Register

(PCI-PCI—D30:F0)................................................................................448

11.1.25SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0) ......................... 448

12 Gigabit LAN Configuration Registers ......................................................................449

12.1 Gigabit LAN Configuration Registers

(Gigabit LAN — D25:F0) ...................................................................................449

10 Datasheet

12.1.1 VID—Vendor Identification Register

(Gigabit LAN—D25:F0).......................................................................... 450

12.1.2 DID—Device Identification Register

(Gigabit LAN—D25:F0).......................................................................... 450

12.1.3 PCICMD—PCI Command Register

(Gigabit LAN—D25:F0).......................................................................... 451

12.1.4 PCISTS—PCI Status Register

(Gigabit LAN—D25:F0).......................................................................... 452

12.1.5 RID—Revision Identification Register

(Gigabit LAN—D25:F0).......................................................................... 453

12.1.6 CC—Class Code Register

(Gigabit LAN—D25:F0).......................................................................... 453

12.1.7 CLS—Cache Line Size Register

(Gigabit LAN—D25:F0).......................................................................... 453

12.1.8 PLT—Primary Latency Timer Register

(Gigabit LAN—D25:F0).......................................................................... 453

12.1.9 HEADTYP—Header Type Register

(Gigabit LAN—D25:F0).......................................................................... 453

12.1.10MBARA—Memory Base Address Register A

(Gigabit LAN—D25:F0).......................................................................... 454

12.1.11MBARB—Memory Base Address Register B

(Gigabit LAN—D25:F0).......................................................................... 454

12.1.12MBARC—Memory Base Address Register C

(Gigabit LAN—D25:F0).......................................................................... 455

12.1.13SVID—Subsystem Vendor ID Register

(Gigabit LAN—D25:F0).......................................................................... 455

12.1.14SID—Subsystem ID Register

(Gigabit LAN—D25:F0).......................................................................... 455

12.1.15ERBA—Expansion ROM Base Address Register

(Gigabit LAN—D25:F0).......................................................................... 455

12.1.16CAPP—Capabilities List Pointer Register

(Gigabit LAN—D25:F0).......................................................................... 456

12.1.17INTR—Interrupt Information Register

(Gigabit LAN—D25:F0).......................................................................... 456

12.1.18MLMG—Maximum Latency/Minimum Grant Register

(Gigabit LAN—D25:F0).......................................................................... 456

12.1.19CLIST1—Capabilities List Register 1

(Gigabit LAN—D25:F0).......................................................................... 456

12.1.20PMC—PCI Power Management Capabilities Register

(Gigabit LAN—D25:F0).......................................................................... 457

12.1.21PMCS—PCI Power Management Control and Status

Register (Gigabit LAN—D25:F0) ............................................................. 458

12.1.22DR—Data Register

(Gigabit LAN—D25:F0).......................................................................... 459

12.1.23CLIST2—Capabilities List Register 2

(Gigabit LAN—D25:F0).......................................................................... 459

12.1.24MCTL—Message Control Register

(Gigabit LAN—D25:F0).......................................................................... 459

12.1.25MADDL—Message Address Low Register

(Gigabit LAN—D25:F0).......................................................................... 460

12.1.26MADDH—Message Address High Register

(Gigabit LAN—D25:F0).......................................................................... 460

12.1.27MDAT—Message Data Register

(Gigabit LAN—D25:F0).......................................................................... 460

12.1.28FLRCAP—Function Level Reset Capability

(Gigabit LAN—D25:F0).......................................................................... 460

12.1.29FLRCLV—Function Level Reset Capability Length and

Version Register (Gigabit LAN—D25:F0) .................................................. 461

12.1.30DEVCTRL—Device Control Register (Gigabit LAN—D25:F0)......................... 461

12.2 Gigabit LAN Capabilities and Status Registers (CSR)............................................. 462

12.2.1 GBECSR1—Gigabit Ethernet Capabilities and Status Register 1 ................... 462

12.2.2 GBECSR2—Gigabit Ethernet Capabilities and Status Register 2 ................... 463

12.2.3 GBECSR3—Gigabit Ethernet Capabilities and Status Register 3 ................... 463

12.2.4 GBECSR4—Gigabit Ethernet Capabilities and Status Register 4 ................... 463

12.2.5 GBECSR5—Gigabit Ethernet Capabilities and Status Register 5 ................... 464

12.2.6 GBECSR6—Gigabit Ethernet Capabilities and Status Register 6 ................... 464

12.2.7 GBECSR7—Gigabit Ethernet Capabilities and Status Register 7 ................... 464

Datasheet 11

12.2.8 GBECSR8—Gigabit Ethernet Capabilities and Status Register 8.................... 465

12.2.9 GBECSR9—Gigabit Ethernet Capabilities and Status Register 9.................... 465

13 LPC Interface Bridge Registers (D31:F0) ...............................................................467

13.1 PCI Configuration Registers (LPC I/F—D31:F0) ....................................................467

13.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) ..............................468

13.1.2 DID—Device Identification Register (LPC I/F—D31:F0)............................... 468

13.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0).................................469

13.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)........................................ 469

13.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ............................ 470

13.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) ............................. 470

13.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) .....................................470

13.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)....................................471

13.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0) ............................471

13.1.10HEADTYP—Header Type Register (LPC I/F—D31:F0) ..................................471

13.1.11SS—Sub System Identifiers Register (LPC I/F—D31:F0) ............................. 471

13.1.12CAPP—Capability List Pointer Register (LPC I/F—D31:F0) ........................... 472

13.1.13PMBASE—ACPI Base Address Register (LPC I/F—D31:F0) ........................... 472

13.1.14ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0) ............................. 473

13.1.15GPIOBASE—GPIO Base Address Register (LPC I/F — D31:F0) .....................473

13.1.16GC—GPIO Control Register (LPC I/F — D31:F0) ........................................474

13.1.17PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register

(LPC I/F—D31:F0) ................................................................................ 475

13.1.18SIRQ_CNTL—Serial IRQ Control Register

(LPC I/F—D31:F0) ................................................................................ 476

13.1.19PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register

(LPC I/F—D31:F0) ................................................................................ 477

13.1.20LPC_IBDF—IOxAPIC Bus:Device:Function

(LPC I/F—D31:F0) ................................................................................ 477

13.1.21LPC_HnBDF – HPET n Bus:Device:Function

(LPC I/F—D31:F0) ................................................................................ 478

13.1.22LPC_I/O_DEC—I/O Decode Ranges Register

(LPC I/F—D31:F0) ................................................................................ 479

13.1.23LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) ................................480

13.1.24GEN1_DEC—LPC I/F Generic Decode Range 1 Register

(LPC I/F—D31:F0) ................................................................................ 481

13.1.25GEN2_DEC—LPC I/F Generic Decode Range 2 Register

(LPC I/F—D31:F0) ................................................................................ 481

13.1.26GEN3_DEC—LPC I/F Generic Decode Range 3 Register

(LPC I/F—D31:F0) ................................................................................ 482

13.1.27GEN4_DEC—LPC I/F Generic Decode Range 4 Register

(LPC I/F—D31:F0) ................................................................................ 482

13.1.28ULKMC — USB Legacy Keyboard / Mouse

Control Register(LPC I/F—D31:F0) ..........................................................483

13.1.29LGMR — LPC I/F Generic Memory Range Register

(LPC I/F—D31:F0) ................................................................................ 484

13.1.30BIOS_SEL1—BIOS Select 1 Register

(LPC I/F—D31:F0) ................................................................................ 485

13.1.31BIOS_SEL2—BIOS Select 2 Register

(LPC I/F—D31:F0) ................................................................................ 486

13.1.32BIOS_DEC_EN1—BIOS Decode Enable

Register (LPC I/F—D31:F0)....................................................................487

13.1.33BIOS_CNTL—BIOS Control Register

(LPC I/F—D31:F0) ................................................................................ 489

13.1.34FDCAP—Feature Detection Capability ID Register

(LPC I/F—D31:F0) ................................................................................ 490

13.1.35FDLEN—Feature Detection Capability Length Register

(LPC I/F—D31:F0) ................................................................................ 490

13.1.36FDVER—Feature Detection Version Register

(LPC I/F—D31:F0) ................................................................................ 490

13.1.37FVECIDX—Feature Vector Index Register

(LPC I/F—D31:F0) ................................................................................ 490

13.1.38FVECD—Feature Vector Data Register

(LPC I/F—D31:F0) ................................................................................ 491

13.1.39Feature Vector Space ............................................................................491

13.1.39.1FVEC0—Feature Vector Register 0 ............................................. 491

13.1.39.2FVEC1—Feature Vector Register 1 ............................................. 492

12 Datasheet

13.1.39.3FVEC2—Feature Vector Register 2 ............................................. 492

13.1.39.4FVEC3—Feature Vector Register 3 ............................................. 492

13.1.40RCBA—Root Complex Base Address Register

(LPC I/F—D31:F0)................................................................................ 493

13.2 DMA I/O Registers........................................................................................... 494

13.2.1 DMABASE_CA—DMA Base and Current Address Registers .......................... 495

13.2.2 DMABASE_CC—DMA Base and Current Count Registers ............................. 496

13.2.3 DMAMEM_LP—DMA Memory Low Page Registers....................................... 496

13.2.4 DMACMD—DMA Command Register ........................................................ 497

13.2.5 DMASTA—DMA Status Register .............................................................. 497

13.2.6 DMA_WRSMSK—DMA Write Single Mask Register...................................... 498

13.2.7 DMACH_MODE—DMA Channel Mode Register ........................................... 498

13.2.8 DMA Clear Byte Pointer Register............................................................. 499

13.2.9 DMA Master Clear Register .................................................................... 499

13.2.10DMA_CLMSK—DMA Clear Mask Register .................................................. 499

13.2.11DMA_WRMSK—DMA Write All Mask Register ............................................ 500

13.3 Timer I/O Registers ......................................................................................... 500

13.3.1 TCW—Timer Control Word Register......................................................... 501

13.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register........................... 503

13.3.3 Counter Access Ports Register................................................................ 504

13.4 8259 Interrupt Controller (PIC) Registers ........................................................... 504

13.4.1 Interrupt Controller I/O MAP .................................................................. 504

13.4.2 ICW1—Initialization Command Word 1 Register........................................ 505

13.4.3 ICW2—Initialization Command Word 2 Register........................................ 506

13.4.4 ICW3—Master Controller Initialization Command

Word 3 Register ................................................................................... 506

13.4.5 ICW3—Slave Controller Initialization Command

Word 3 Register ................................................................................... 507

13.4.6 ICW4—Initialization Command Word 4 Register........................................ 507

13.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)

Register .............................................................................................. 508

13.4.8 OCW2—Operational Control Word 2 Register............................................ 508

13.4.9 OCW3—Operational Control Word 3 Register............................................ 509

13.4.10ELCR1—Master Controller Edge/Level Triggered Register ........................... 510

13.4.11ELCR2—Slave Controller Edge/Level Triggered Register ............................. 511

13.5 Advanced Programmable Interrupt Controller (APIC)............................................ 512

13.5.1 APIC Register Map................................................................................ 512

13.5.2 IND—Index Register ............................................................................. 512

13.5.3 DAT—Data Register .............................................................................. 513

13.5.4 EOIR—EOI Register .............................................................................. 513

13.5.5 ID—Identification Register..................................................................... 514

13.5.6 VER—Version Register .......................................................................... 514

13.5.7 REDIR_TBL—Redirection Table Register ................................................... 515

13.6 Real Time Clock Registers................................................................................. 517

13.6.1 I/O Register Address Map...................................................................... 517

13.6.2 Indexed Registers ................................................................................ 518

13.6.2.1 RTC_REGA—Register A ............................................................ 519

13.6.2.2 RTC_REGB—Register B (General Configuration) .......................... 520

13.6.2.3 RTC_REGC—Register C (Flag Register) ...................................... 521

13.6.2.4 RTC_REGD—Register D (Flag Register) ...................................... 521

13.7 Processor Interface Registers............................................................................ 522

13.7.1 NMI_SC—NMI Status and Control Register............................................... 522

13.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)

Register .............................................................................................. 523

13.7.3 PORT92—Init Register........................................................................... 523

13.7.4 COPROC_ERR—Coprocessor Error Register .............................................. 523

13.7.5 RST_CNT—Reset Control Register........................................................... 524

13.8 Power Management Registers ........................................................................... 525

13.8.1 Power Management PCI Configuration Registers

(PM—D31:F0)...................................................................................... 525

13.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register

(PM—D31:F0) ........................................................................ 526

13.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register

(PM—D31:F0) ........................................................................ 527

13.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register

(PM—D31:F0) ........................................................................ 528

Datasheet 13

13.8.1.4 GEN_PMCON_LOCK—General Power Management Configuration

Lock Register.......................................................................... 531

13.8.1.5 BM_BREAK_EN_2 Register #2 (PM—D31:F0) ..............................531

13.8.1.6 BM_BREAK_EN Register (PM—D31:F0).......................................532

13.8.1.7 PMIR—Power Management Initialization Register (PM—D31:F0)..... 533

13.8.1.8 GPIO_ROUT—GPIO Routing Control Register

(PM—D31:F0)......................................................................... 533

13.8.2 APM I/O Decode Register....................................................................... 534

13.8.2.1 APM_CNT—Advanced Power Management Control Port Register ..... 534

13.8.2.2 APM_STS—Advanced Power Management Status Port Register ...... 534

13.8.3 Power Management I/O Registers ...........................................................535

13.8.3.1 PM1_STS—Power Management 1 Status Register.........................535

13.8.3.2 PM1_EN—Power Management 1 Enable Register .......................... 538

13.8.3.3 PM1_CNT—Power Management 1 Control Register .......................539

13.8.3.4 PM1_TMR—Power Management 1 Timer Register .........................540

13.8.3.5 GPE0_STS—General Purpose Event 0 Status Register................... 540

13.8.3.6 GPE0_EN—General Purpose Event 0 Enables Register................... 543

13.8.3.7 SMI_EN—SMI Control and Enable Register..................................545

13.8.3.8 SMI_STS—SMI Status Register.................................................. 547

13.8.3.9 ALT_GP_SMI_EN—Alternate GPI SMI Enable Register...................549

13.8.3.10ALT_GP_SMI_STS—Alternate GPI SMI Status Register.................. 550

13.8.3.11GPE_CNTL—General Purpose Control Register .............................550

13.8.3.12DEVACT_STS — Device Activity Status Register...........................551

13.8.3.13PM2_CNT—Power Management 2 Control Register .......................551

13.9 System Management TCO Registers ...................................................................552

13.9.1 TCO_RLD—TCO Timer Reload and Current Value Register...........................552

13.9.2 TCO_DAT_IN—TCO Data In Register .......................................................553

13.9.3 TCO_DAT_OUT—TCO Data Out Register...................................................553

13.9.4 TCO1_STS—TCO1 Status Register........................................................... 553

13.9.5 TCO2_STS—TCO2 Status Register........................................................... 555

13.9.6 TCO1_CNT—TCO1 Control Register .........................................................556

13.9.7 TCO2_CNT—TCO2 Control Register .........................................................557

13.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers .......................................557

13.9.9 TCO_WDCNT—TCO Watchdog Control Register ......................................... 558

13.9.10SW_IRQ_GEN—Software IRQ Generation Register .....................................558

13.9.11TCO_TMR—TCO Timer Initial Value Register .............................................558

13.10 General Purpose I/O Registers........................................................................... 559

13.10.1GPIO_USE_SEL—GPIO Use Select Register...............................................560

13.10.2GP_IO_SEL—GPIO Input/Output Select Register .......................................560

13.10.3GP_LVL—GPIO Level for Input or Output Register...................................... 561

13.10.4GPO_BLINK—GPO Blink Enable Register...................................................561

13.10.5GP_SER_BLINK—GP Serial Blink Register ................................................. 562

13.10.6GP_SB_CMDSTS—GP Serial Blink Command

Status Register.....................................................................................562

13.10.7GP_SB_DATA—GP Serial Blink Data Register ............................................ 563

13.10.8GPI_NMI_EN—GPI NMI Enable Register ...................................................563

13.10.9GPI_NMI_STS—GPI NMI Status Register .................................................. 563

13.10.10GPI_INV—GPIO Signal Invert Register.................................................... 564

13.10.11GPIO_USE_SEL2—GPIO Use Select 2 Register.........................................564

13.10.12GP_IO_SEL2—GPIO Input/Output Select 2 Register .................................565

13.10.13GP_LVL2—GPIO Level for Input or Output 2 Register................................565

13.10.14GPIO_USE_SEL3—GPIO Use Select 3 Register.........................................566

13.10.15GP_IO_SEL3—GPIO Input/Output Select 3 Register .................................566

13.10.16GP_LVL3—GPIO Level for Input or Output 3 Register................................567

13.10.17GP_RST_SEL1 — GPIO Reset Select Register ..........................................567

13.10.18GP_RST_SEL2 — GPIO Reset Select Register ..........................................568

13.10.19GP_RST_SEL3 — GPIO Reset Select Register ..........................................568

14 SATA Controller Registers (D31:F2) .......................................................................569

14.1 PCI Configuration Registers (SATA–D31:F2) ........................................................ 569

14.1.1 VID—Vendor Identification Register (SATA–D31:F2)..................................571

14.1.2 DID—Device Identification Register (SATA–D31:F2) ..................................571

14.1.3 PCICMD—PCI Command Register (SATA–D31:F2) .....................................571

14.1.4 PCISTS — PCI Status Register (SATA–D31:F2) ......................................... 572

14.1.5 RID—Revision Identification Register (SATA–D31:F2) ................................573

14.1.6 PI—Programming Interface Register (SATA–D31:F2) .................................573

14.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h ........... 573

14 Datasheet

14.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h .......... 573

14.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h .......... 574

14.1.7 SCC—Sub Class Code Register (SATA–D31:F2) ........................................ 574

14.1.8 BCC—Base Class Code Register

(SATA–D31:F2SATA–D31:F2) ................................................................ 574

14.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F2).................................................................................... 574

14.1.10HTYPE—Header Type Register

(SATA–D31:F2).................................................................................... 575

14.1.11PCMD_BAR—Primary Command Block Base Address

Register (SATA–D31:F2) ....................................................................... 575

14.1.12PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F2).................................................................................... 575

14.1.13SCMD_BAR—Secondary Command Block Base Address

Register (SATA–D31:F2) ....................................................................... 576

14.1.14SCNL_BAR—Secondary Control Block Base Address

Register (SATA–D31:F2) ....................................................................... 576

14.1.15BAR—Legacy Bus Master Base Address Register

(SATA–D31:F2).................................................................................... 577

14.1.16ABAR/SIDPBA—AHCI Base Address Register/Serial ATA

Index Data Pair Base Address (SATA–D31:F2).......................................... 577

14.1.16.1When SCC is not 01h............................................................... 577

14.1.16.2When SCC is 01h.................................................................... 578

14.1.17SVID—Subsystem Vendor Identification Register

(SATA–D31:F2).................................................................................... 578

14.1.18SID—Subsystem Identification Register (SATA–D31:F2) ............................ 578

14.1.19CAP—Capabilities Pointer Register (SATA–D31:F2).................................... 578

14.1.20INT_LN—Interrupt Line Register (SATA–D31:F2) ...................................... 579

14.1.21INT_PN—Interrupt Pin Register (SATA–D31:F2)........................................ 579

14.1.22IDE_TIM—IDE Timing Register (SATA–D31:F2) ........................................ 579

14.1.23SIDETIM—Slave IDE Timing Register (SATA–D31:F2)................................ 580

14.1.24SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F2).................................................................................... 580

14.1.25SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F2).................................................................................... 580

14.1.26IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F2).................................................................................... 581

14.1.27PID—PCI Power Management Capability Identification

Register (SATA–D31:F2) ....................................................................... 581

14.1.28PC—PCI Power Management Capabilities Register

(SATA–D31:F2).................................................................................... 582

14.1.29PMCS—PCI Power Management Control and Status

Register (SATA–D31:F2) ....................................................................... 582

14.1.30MSICI—Message Signaled Interrupt Capability

Identification Register (SATA–D31:F2) .................................................... 583

14.1.31MSIMC—Message Signaled Interrupt Message

Control Register (SATA–D31:F2) ............................................................ 583

14.1.32MSIMA— Message Signaled Interrupt Message

Address Register (SATA–D31:F2) ........................................................... 585

14.1.33MSIMD—Message Signaled Interrupt Message

Data Register (SATA–D31:F2)................................................................ 585

14.1.34MAP—Address Map Register (SATA–D31:F2) ............................................ 586

14.1.35PCS—Port Control and Status Register (SATA–D31:F2).............................. 587

14.1.36SCLKCG—SATA Clock Gating Control Register .......................................... 589

14.1.37SGC—SATA General Configuration Register.............................................. 590

14.1.38SATACR0—SATA Capability Register 0 (SATA–D31:F2) .............................. 591

14.1.39SATACR1—SATA Capability Register 1 (SATA–D31:F2) .............................. 591

14.1.40FLRCID—FLR Capability ID Register (SATA–D31:F2) ................................. 592

14.1.41FLRCLV—FLR Capability Length and Version Register (SATA–D31:F2) .......... 592

14.1.42FLRC—FLR Control Register (SATA–D31:F2)............................................. 593

14.1.43ATC—APM Trapping Control Register (SATA–D31:F2) ................................ 593

14.1.44ATS—APM Trapping Status Register (SATA–D31:F2) ................................. 594

14.1.45SP—Scratch Pad Register (SATA–D31:F2)................................................ 594

14.1.46BFCS—BIST FIS Control/Status Register (SATA–D31:F2) ........................... 595

14.1.47BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ........................ 597

14.1.48BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ........................ 597

14.2 Bus Master IDE I/O Registers (D31:F2) .............................................................. 598

Datasheet 15

14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) .......................... 599

14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2)................................600

14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Register (D31:F2)................................................................................. 601

14.2.4 AIR—AHCI Index Register (D31:F2) ........................................................601

14.2.5 AIDR—AHCI Index Data Register (D31:F2)............................................... 601

14.3 Serial ATA Index/Data Pair Superset Registers.....................................................602

14.3.1 SINDX—Serial ATA Index Register (D31:F2).............................................602

14.3.2 SDATA—Serial ATA Data Register (D31:F2) ..............................................603

14.3.2.1 PxSSTS—Serial ATA Status Register (D31:F2) .............................603

14.3.2.2 PxSCTL—Serial ATA Control Register (D31:F2) ............................ 604

14.3.2.3 PxSERR—Serial ATA Error Register (D31:F2)...............................605

14.4 AHCI Registers (D31:F2) .................................................................................. 606

14.4.1 AHCI Generic Host Control Registers (D31:F2)..........................................607

14.4.1.1 CAP—Host Capabilities Register (D31:F2) ................................... 607

14.4.1.2 GHC—Global PCH Control Register (D31:F2) ...............................609

14.4.1.3 IS—Interrupt Status Register (D31:F2) ...................................... 610

14.4.1.4 PI—Ports Implemented Register (D31:F2) ..................................611

14.4.1.5 VS—AHCI Version Register (D31:F2)..........................................612

14.4.1.6 EM_LOC—Enclosure Management Location Register (D31:F2)........ 612

14.4.1.7 EM_CTRL—Enclosure Management Control Register (D31:F2)........ 612

14.4.1.8 CAP2—HBA Capabilities Extended Register.................................. 613

14.4.1.9 RSTF—Intel® RST Feature Capabilities Register ...........................614

14.4.2 Port Registers (D31:F2).........................................................................616

14.4.2.1 PxCLB—Port [5:0] Command List Base Address Register

(D31:F2)................................................................................619

14.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper

32-Bits Register (D31:F2) ........................................................619

14.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2).................. 619

14.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits

Register (D31:F2) ...................................................................620

14.4.2.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2) ....................620

14.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2).................... 622

14.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2) ......................... 623

14.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2).....................626

14.4.2.9 PxSIG—Port [5:0] Signature Register (D31:F2) ........................... 626

14.4.2.10PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2) .............. 627

14.4.2.11PxSCTL — Port [5:0] Serial ATA Control Register (D31:F2) ........... 628

14.4.2.12PxSERR—Port [5:0] Serial ATA Error Register (D31:F2) ................ 629

14.4.2.13PxSACT—Port [5:0] Serial ATA Active Register (D31:F2)............... 631

14.4.2.14PxCI—Port [5:0] Command Issue Register (D31:F2) .................... 631

15 SATA Controller Registers (D31:F5) .......................................................................633

15.1 PCI Configuration Registers (SATA–D31:F5) ........................................................ 633

15.1.1 VID—Vendor Identification Register (SATA—D31:F5).................................634

15.1.2 DID—Device Identification Register (SATA—D31:F5) .................................634

15.1.3 PCICMD—PCI Command Register (SATA–D31:F5) .....................................635

15.1.4 PCISTS — PCI Status Register (SATA–D31:F5) ......................................... 636

15.1.5 RID—Revision Identification Register (SATA—D31:F5) ............................... 636

15.1.6 PI—Programming Interface Register (SATA–D31:F5) .................................637

15.1.7 SCC—Sub Class Code Register (SATA–D31:F5).........................................637

15.1.8 BCC—Base Class Code Register

(SATA–D31:F5SATA–D31:F5)................................................................. 637

15.1.9 PMLT—Primary Master Latency Timer Register

(SATA–D31:F5) .................................................................................... 638

15.1.10PCMD_BAR—Primary Command Block Base Address

Register (SATA–D31:F5)........................................................................ 638

15.1.11PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F5) .................................................................................... 638

15.1.12SCMD_BAR—Secondary Command Block Base Address

Register (SATA D31:F5) ........................................................................639

15.1.13SCNL_BAR—Secondary Control Block Base Address

Register (SATA D31:F5) ........................................................................639

15.1.14BAR — Legacy Bus Master Base Address Register

(SATA–D31:F5) .................................................................................... 640

15.1.15SIDPBA — SATA Index/Data Pair Base Address Register

(SATA–D31:F5) .................................................................................... 640

16 Datasheet

15.1.16SVID—Subsystem Vendor Identification Register

(SATA–D31:F5).................................................................................... 641

15.1.17SID—Subsystem Identification Register (SATA–D31:F5) ............................ 641

15.1.18CAP—Capabilities Pointer Register (SATA–D31:F5).................................... 641

15.1.19INT_LN—Interrupt Line Register (SATA–D31:F5) ...................................... 641

15.1.20INT_PN—Interrupt Pin Register (SATA–D31:F5)........................................ 641

15.1.21IDE_TIM—IDE Timing Register (SATA–D31:F5) ........................................ 642

15.1.22SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F5).................................................................................... 642

15.1.23SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F5).................................................................................... 643

15.1.24IDE_CONFIG—IDE I/O Configuration Register

(SATA–D31:F5).................................................................................... 643

15.1.25PID—PCI Power Management Capability Identification

Register (SATA–D31:F5) ....................................................................... 644

15.1.26PC—PCI Power Management Capabilities Register

(SATA–D31:F5).................................................................................... 644

15.1.27PMCS—PCI Power Management Control and Status

Register (SATA–D31:F5) ....................................................................... 645

15.1.28MAP—Address Map Register (SATA–D31:F5) ............................................ 645

15.1.29PCS—Port Control and Status Register (SATA–D31:F5).............................. 646

15.1.30SATACR0— SATA Capability Register 0 (SATA–D31:F5) ............................. 647

15.1.31SATACR1— SATA Capability Register 1 (SATA–D31:F5) ............................. 647

15.1.32FLRCID— FLR Capability ID Register (SATA–D31:F5)................................. 647

15.1.33FLRCLV— FLR Capability Length and

Value Register (SATA–D31:F5)............................................................... 648

15.1.34FLRCTRL— FLR Control Register (SATA–D31:F5)....................................... 648

15.1.35ATC—APM Trapping Control Register (SATA–D31:F5) ................................ 649

15.1.36ATS—APM Trapping Status Register (SATA–D31:F5) ................................. 649

15.2 Bus Master IDE I/O Registers (D31:F5) .............................................................. 649

15.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5).......................... 650

15.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5) ............................... 651

15.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

Register (D31:F5) ................................................................................ 651

15.3 Serial ATA Index/Data Pair Superset Registers .................................................... 652

15.3.1 SINDX—SATA Index Register (D31:F5) ................................................... 652

15.3.2 SDATA—SATA Index Data Register (D31:F5)............................................ 652

15.3.2.1 PxSSTS—Serial ATA Status Register (D31:F5) ............................ 653

15.3.2.2 PxSCTL — Serial ATA Control Register (D31:F5).......................... 654

15.3.2.3 PxSERR—Serial ATA Error Register (D31:F5) .............................. 655

16 EHCI Controller Registers (D29:F0, D26:F0) .......................................................... 657

16.1 USB EHCI Configuration Registers

(USB EHCI—D29:F0, D26:F0) ........................................................................... 657

16.1.1 VID—Vendor Identification Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 658

16.1.2 DID—Device Identification Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 659

16.1.3 PCICMD—PCI Command Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 659

16.1.4 PCISTS—PCI Status Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 660

16.1.5 RID—Revision Identification Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 661

16.1.6 PI—Programming Interface Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 661

16.1.7 SCC—Sub Class Code Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 661

16.1.8 BCC—Base Class Code Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 662

16.1.9 PMLT—Primary Master Latency Timer Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 662

16.1.10HEADTYP—Header Type Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 662

16.1.11MEM_BASE—Memory Base Address Register

(USB EHCI—D29:F0, D26:F0) ................................................................ 663

Datasheet 17

16.1.12SVID—USB EHCI Subsystem Vendor ID Register

(USB EHCI—D29:F0, D26:F0).................................................................663

16.1.13SID—USB EHCI Subsystem ID Register

(USB EHCI—D29:F0, D26:F0).................................................................663

16.1.14CAP_PTR—Capabilities Pointer Register

(USB EHCI—D29:F0, D26:F0).................................................................664

16.1.15INT_LN—Interrupt Line Register

(USB EHCI—D29:F0, D26:F0).................................................................664

16.1.16INT_PN—Interrupt Pin Register

(USB EHCI—D29:F0, D26:F0).................................................................664

16.1.17PWR_CAPID—PCI Power Management Capability ID

Register (USB EHCI—D29:F0, D26:F0) ....................................................664

16.1.18NXT_PTR1—Next Item Pointer #1 Register

(USB EHCI—D29:F0, D26:F0).................................................................665

16.1.19PWR_CAP—Power Management Capabilities Register

(USB EHCI—D29:F0, D26:F0).................................................................665

16.1.20PWR_CNTL_STS—Power Management Control/

Status Register (USB EHCI—D29:F0, D26:F0) ..........................................666

16.1.21DEBUG_CAPID—Debug Port Capability ID Register

(USB EHCI—D29:F0, D26:F0).................................................................667

16.1.22NXT_PTR2—Next Item Pointer #2 Register

(USB EHCI—D29:F0, D26:F0).................................................................667

16.1.23DEBUG_BASE—Debug Port Base Offset Register

(USB EHCI—D29:F0, D26:F0).................................................................667

16.1.24USB_RELNUM—USB Release Number Register

(USB EHCI—D29:F0, D26:F0).................................................................667

16.1.25FL_ADJ—Frame Length Adjustment Register

(USB EHCI—D29:F0, D26:F0).................................................................668

16.1.26PWAKE_CAP—Port Wake Capability Register

(USB EHCI—D29:F0, D26:F0).................................................................669

16.1.27LEG_EXT_CAP—USB EHCI Legacy Support Extended

Capability Register (USB EHCI—D29:F0, D26:F0)......................................669

16.1.28LEG_EXT_CS—USB EHCI Legacy Support Extended

Control / Status Register (USB EHCI—D29:F0, D26:F0) ............................. 670

16.1.29SPECIAL_SMI—Intel Specific USB 2.0 SMI Register

(USB EHCI—D29:F0, D26:F0).................................................................672

16.1.30ACCESS_CNTL—Access Control Register

(USB EHCI—D29:F0, D26:F0).................................................................673

16.1.31EHCIIR1—EHCI Initialization Register 1

(USB EHCI—D29:F0, D26:F0).................................................................673

16.1.32FLR_CID—Function Level Reset Capability ID Register

(USB EHCI—D29:F0, D26:F0).................................................................674

16.1.33FLR_NEXT—Function Level Reset Next Capability

Pointer Register (USB EHCI—D29:F0, D26:F0)..........................................674

16.1.34FLR_CLV—Function Level Reset Capability Length and

Version Register (USB EHCI—D29:F0, D26:F0).........................................674

16.1.35FLR_CTRL—Function Level Reset Control Register

(USB EHCI—D29:F0, D26:F0).................................................................675

16.1.36FLR_STAT—Function Level Reset Status Register

(USB EHCI—D29:F0, D26:F0).................................................................675

16.2 Memory-Mapped I/O Registers ..........................................................................676

16.2.1 Host Controller Capability Registers.........................................................676

16.2.1.1 CAPLENGTH—Capability Registers Length Register .......................677

16.2.1.2 HCIVERSION—Host Controller Interface Version Number

Register .................................................................................677

16.2.1.3 HCSPARAMS—Host Controller Structural Parameters .................... 678

16.2.1.4 HCCPARAMS—Host Controller Capability Parameters

Register .................................................................................679

16.2.2 Host Controller Operational Registers ......................................................680

16.2.2.1 USB2.0_CMD—USB 2.0 Command Register.................................681

16.2.2.2 USB2.0_STS—USB 2.0 Status Register....................................... 683

16.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register........................ 685

16.2.2.4 FRINDEX—Frame Index Register ............................................... 686

16.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment

Register .................................................................................687

16.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address

Register .................................................................................687

18 Datasheet

16.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address

Register................................................................................. 688

16.2.2.8 CONFIGFLAG—Configure Flag Register....................................... 688

16.2.2.9 PORTSC—Port N Status and Control Register .............................. 689

16.2.3 USB 2.0-Based Debug Port Registers ...................................................... 693

16.2.3.1 CNTL_STS—Control/Status Register .......................................... 694

16.2.3.2 USBPID—USB PIDs Register ..................................................... 695

16.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register......................... 696

16.2.3.4 CONFIG—Configuration Register ............................................... 696

17 xHCI Controller Registers (D20:F0) ....................................................................... 697

17.1 USB xHCI Configuration Registers

(USB xHCI—D20:F0) ....................................................................................... 697

17.1.1 VID—Vendor Identification Register

(USB xHCI—D20:F0) ............................................................................ 698

17.1.2 DID—Device Identification Register

(USB xHCI—D20:F0) ............................................................................ 698

17.1.3 PCICMD—PCI Command Register

(USB xHCI—D20:F0) ............................................................................ 699

17.1.4 PCISTS—PCI Status Register

(USB xHCI—D20:F0) ............................................................................ 700

17.1.5 RID—Revision Identification Register

(USB xHCI—D20:F0) ............................................................................ 701

17.1.6 PI—Programming Interface Register

(USB xHCI—D20:F0) ............................................................................ 701

17.1.7 SCC—Sub Class Code Register

(USB xHCI—D20:F0) ............................................................................ 701

17.1.8 BCC—Base Class Code Register

(USB xHCI—D20:F0) ............................................................................ 701

17.1.9 PMLT—Primary Master Latency Timer Register

(USB xHCI—D20:F0) ............................................................................ 702

17.1.10HEADTYP—Header Type Register

(USB xHCI—D20:F0) ............................................................................ 702

17.1.11MEM_BASE_L—Memory Base Address Low Register

(USB xHCI—D20:F0) ............................................................................ 702

17.1.12MEM_BASE_H—Memory Base Address High Register

(USB xHCI—D20:F0) ............................................................................ 703

17.1.13SVID—USB xHCI Subsystem Vendor ID Register

(USB xHCI—D20:F0) ............................................................................ 703

17.1.14SID—USB xHCI Subsystem ID Register

(USB xHCI—D20:F0) ............................................................................ 703

17.1.15CAP_PTR—Capabilities Pointer Register

(USB xHCI—D20:F0) ............................................................................ 703

17.1.16INT_LN—Interrupt Line Register

(USB xHCI—D20:F0) ............................................................................ 704

17.1.17INT_PN—Interrupt Pin Register

(USB xHCI—D20:F0) ............................................................................ 704

17.1.18XHCC—xHC System Bus Configuration Register

(USB xHCI—D20:F0) ............................................................................ 704

17.1.19XHCC2—xHC System Bus Configuration Register 2

(USB xHCI—D20:F0) ............................................................................ 705

17.1.20SBRN—Serial Bus Release Number

Register (USB xHCI—D20:F0) ................................................................ 706

17.1.21FL_ADJ—Frame Length Adjustment Register

(USB xHCI—D20:F0) ............................................................................ 706

17.1.22PWR_CAPID—PCI Power Management Capability ID

Register (USB xHCI—D20:F0) ................................................................ 707

17.1.23NXT_PTR1—Next Item Pointer #1 Register

(USB xHCI—D20:F0) ............................................................................ 707

17.1.24PWR_CAP—Power Management Capabilities Register

(USB xHCI—D20:F0) ............................................................................ 708

17.1.25PWR_CNTL_STS—Power Management Control/

Status Register (USB xHCI—D20:F0) ...................................................... 709

17.1.26MSI_CAPID—Message Signaled Interrupt Capability ID Register

(USB xHCI—D20:F0) ............................................................................ 709

17.1.27NEXT_PTR2— Next Item Pointer Register

(USB xHCI—D20:F0) ............................................................................ 710

Datasheet 19

17.1.28MSI_MCTL— MSI Message Control Register

(USB xHCI—D20:F0).............................................................................710

17.1.29MSI_LMAD—MSI Lower Message Address Register

(USB xHCI—D20:F0).............................................................................710

17.1.30MSI_UMAD—MSI Upper Message Address Register

(USB xHCI—D20:F0).............................................................................711

17.1.31MSI_MD—MSI Message Data Register

(USB xHCI—D20:F0).............................................................................711

17.1.32XOCM—xHC Overcurrent Mapping Register

(USB xHCI—D20:F0).............................................................................712

17.1.33XUSB2PR —xHC USB 2.0 Port Routing Register

(USB xHCI—D20:F0).............................................................................713

17.1.34XUSB2PRM—xHC USB 2.0 Port Routing Mask Register

(USB xHCI—D20:F0).............................................................................713

17.1.35USB3_PSSEN—USB 3.0 Port SuperSpeed Enable Register

(USB xHCI—D20:F0).............................................................................714

17.1.36USB3PRM—USB 3.0 Port Routing Mask Register

(USB xHCI—D20:F0).............................................................................714

17.2 Memory-Mapped I/O Registers ..........................................................................715

17.2.1 Host Controller Capability Registers.........................................................715

17.2.1.1 CAPLENGTH—Capability Registers Length Register .......................716

17.2.1.2 HCIVERSION—Host Controller Interface Version Number

Register .................................................................................716

17.2.1.3 HCSPARAMS1 —Host Controller Structural Parameters #1

Register .................................................................................716

17.2.1.4 HCSPARAMS2—Host Controller Structural Parameters #2

Register .................................................................................717

17.2.1.5 HCSPARAMS3—Host Controller Structural Parameters #3

Register .................................................................................718

17.2.1.6 HCCPARAMS—Host Controller Capability Parameters

Register .................................................................................719

17.2.1.7 DBOFF—Doorbell Offset Register ............................................... 720

17.2.1.8 RTSOFF—Runtime Register Space Offset Register ........................720

17.2.2 Host Controller Operational Registers ......................................................721

17.2.2.1 USB_CMD—USB Command Register...........................................722

17.2.2.2 USB_STS—USB Status Register.................................................724

17.2.2.3 PAGESIZE—PAGESIZE Register .................................................725

17.2.2.4 DNCTRL—Device Notification Control Register .............................725

17.2.2.5 CRCRL—Command Ring Control Low Register.............................. 726

17.2.2.6 CRCRH—Command Ring Control High Register ............................ 727

17.2.2.7 DCBAAPL—Device Context Base Address Array Pointer Low

Register .................................................................................727

17.2.2.8 DCBAAPH—Device Context Base Address Array Pointer High

Register .................................................................................727

17.2.2.9 CONFIG—Configure Register ..................................................... 728

17.2.2.10PORTSCUSB2—xHCI USB 2.0 Port N Status and Control Register ... 728

17.2.2.11PORTPMSCUSB2—xHCI USB 2.0 Port N Power Management

Status and Control Register ......................................................734

17.2.2.12PORTSCUSB3—xHCI USB 3.0 Port N Status and Control Register ... 735

17.2.2.13PORTPMSCUSB3—xHCI USB 3.0 Port N Power Management

Status and Control Register ......................................................740

17.2.2.14PORTLI—xHCI USB 3.0 Port N Link Info Register .........................741

17.2.3 Host Controller Runtime Registers........................................................... 741

17.2.3.1 MFINDEX—Microframe Index Register ........................................741

17.2.3.2 IMAN—Interrupter X Management Register.................................742

17.2.3.3 IMOD—Interrupter X Moderation Register...................................743

17.2.3.4 ERSTSZ—Event Ring Segment Table Size X Register ....................743

17.2.3.5 ERSTBAL—Event Ring Segment Table Base Address Low X

Register .................................................................................744

17.2.3.6 ERSTBAH—Event Ring Segment Table Base Address High X

Register .................................................................................744

17.2.3.7 ERDPL—Event Ring Dequeue Pointer Low X Register .................... 745

17.2.3.8 ERDPH—Event Ring Dequeue Pointer High X Register...................745

17.2.4 Doorbell Registers................................................................................. 746

17.2.4.1 DOORBELL—Doorbell X Register................................................746

20 Datasheet

18 Integrated Intel® High Definition Audio Controller Registers................................. 747

18.1 Intel

®

High Definition Audio Controller Registers (D27:F0).................................... 747

18.1.1 Intel® High Definition Audio PCI Configuration Space

(Intel® High Definition Audio— D27:F0) .................................................. 747

18.1.1.1 VID—Vendor Identification Register

18.1.1.2 DID—Device Identification Register

(Intel

(Intel

®

High Definition Audio Controller—D27:F0) ....................... 749

®

High Definition Audio Controller—D27:F0) ....................... 749

18.1.1.3 PCICMD—PCI Command Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 750

18.1.1.4 PCISTS—PCI Status Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 751

18.1.1.5 RID—Revision Identification Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 751

18.1.1.6 PI—Programming Interface Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 751

18.1.1.7 SCC—Sub Class Code Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 752

18.1.1.8 BCC—Base Class Code Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 752

18.1.1.9 CLS—Cache Line Size Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 752

18.1.1.10LT—Latency Timer Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 752

18.1.1.11HEADTYP—Header Type Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 752

18.1.1.12HDBARL—Intel® High Definition Audio Lower Base Address

Register (Intel®High Definition Audio—D27:F0).......................... 753

18.1.1.13HDBARU—Intel® High Definition Audio Upper Base Address

Register (Intel® High Definition Audio Controller—D27:F0)........... 753

18.1.1.14SVID—Subsystem Vendor Identification Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 753

18.1.1.15SID—Subsystem Identification Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 754

18.1.1.16CAPPTR—Capabilities Pointer Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 754

18.1.1.17INTLN—Interrupt Line Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 754

18.1.1.18INTPN—Interrupt Pin Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 754

18.1.1.19HDCTL—Intel® High Definition Audio Control Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 755

18.1.1.20DCKCTL—Docking Control Register (Mobile Only)

(Intel

®

High Definition Audio Controller—D27:F0) ....................... 755

18.1.1.21DCKSTS—Docking Status Register (Mobile Only)

(Intel® High Definition Audio Controller—D27:F0) ....................... 756

18.1.1.22PID—PCI Power Management Capability ID Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 756

18.1.1.23PC—Power Management Capabilities Register

(Intel

®

High Definition Audio Controller—D27:F0) ....................... 757

18.1.1.24PCS—Power Management Control and Status Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 757

18.1.1.25MID—MSI Capability ID Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 758

18.1.1.26MMC—MSI Message Control Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 758

18.1.1.27MMLA—MSI Message Lower Address Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 759

18.1.1.28MMUA—MSI Message Upper Address Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 759

18.1.1.29MMD—MSI Message Data Register

(Intel

®

High Definition Audio Controller—D27:F0) ....................... 759

18.1.1.30PXID—PCI Express* Capability ID Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 759

18.1.1.31PXC—PCI Express* Capabilities Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 760

Datasheet 21

18.1.1.32DEVCAP—Device Capabilities Register

(Intel® High Definition Audio Controller—D27:F0)........................ 760

18.1.1.33DEVC—Device Control Register

(Intel® High Definition Audio Controller—D27:F0)........................ 761

18.1.1.34DEVS—Device Status Register

(Intel® High Definition Audio Controller—D27:F0)........................ 762

18.1.1.35VCCAP—Virtual Channel Enhanced Capability Header

(Intel® High Definition Audio Controller—D27:F0)........................ 762

18.1.1.36PVCCAP1—Port VC Capability Register 1

(Intel® High Definition Audio Controller—D27:F0)........................ 763

18.1.1.37PVCCAP2 — Port VC Capability Register 2

(Intel® High Definition Audio Controller—D27:F0)........................ 763

18.1.1.38PVCCTL — Port VC Control Register

(Intel® High Definition Audio Controller—D27:F0)........................ 763

18.1.1.39PVCSTS—Port VC Status Register

(Intel® High Definition Audio Controller—D27:F0)........................ 764

18.1.1.40VC0CAP—VC0 Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0)........................ 764

18.1.1.41VC0CTL—VC0 Resource Control Register

(Intel® High Definition Audio Controller—D27:F0)........................ 765

18.1.1.42VC0STS—VC0 Resource Status Register

(Intel® High Definition Audio Controller—D27:F0)........................ 765

18.1.1.43VCiCAP—VCi Resource Capability Register

(Intel® High Definition Audio Controller—D27:F0)........................ 766

18.1.1.44VCiCTL—VCi Resource Control Register

(Intel® High Definition Audio Controller—D27:F0)........................ 766

18.1.1.45VCiSTS—VCi Resource Status Register

(Intel® High Definition Audio Controller—D27:F0)........................ 767

18.1.1.46RCCAP—Root Complex Link Declaration Enhanced
Capability Header Register

(Intel® High Definition Audio Controller—D27:F0)........................ 767

18.1.1.47ESD—Element Self Description Register

(Intel® High Definition Audio Controller—D27:F0)........................ 767

18.1.1.48L1DESC—Link 1 Description Register

(Intel® High Definition Audio Controller—D27:F0)........................ 768

18.1.1.49L1ADDL—Link 1 Lower Address Register

(Intel® High Definition Audio Controller—D27:F0)........................ 768

18.1.1.50L1ADDU—Link 1 Upper Address Register

(Intel® High Definition Audio Controller—D27:F0)........................ 768

18.1.2 Intel® High Definition Audio Memory Mapped Configuration Registers

(Intel® High Definition Audio D27:F0) .....................................................769

18.1.2.1 GCAP—Global Capabilities Register

(Intel® High Definition Audio Controller—D27:F0)........................ 773

18.1.2.2 VMIN—Minor Version Register

(Intel

®

High Definition Audio Controller—D27:F0)........................ 773

18.1.2.3 VMAJ—Major Version Register

(Intel® High Definition Audio Controller—D27:F0)........................ 773

18.1.2.4 OUTPAY—Output Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0)........................ 774

18.1.2.5 INPAY—Input Payload Capability Register

(Intel® High Definition Audio Controller—D27:F0)........................ 774

18.1.2.6 GCTL—Global Control Register

(Intel® High Definition Audio Controller—D27:F0)........................ 775

18.1.2.7 WAKEEN—Wake Enable Register

(Intel® High Definition Audio Controller—D27:F0)........................ 776

18.1.2.8 STATESTS—State Change Status Register

(Intel® High Definition Audio Controller—D27:F0)........................ 776

18.1.2.9 GSTS—Global Status Register

(Intel® High Definition Audio Controller—D27:F0)........................ 777

18.1.2.10OUTSTRMPAY—Output Stream Payload Capability

(Intel

®

High Definition Audio Controller—D27:F0)........................ 777

18.1.2.11INSTRMPAY—Input Stream Payload Capability

(Intel® High Definition Audio Controller—D27:F0)........................ 777

18.1.2.12INTCTL—Interrupt Control Register

(Intel® High Definition Audio Controller—D27:F0)........................ 778

18.1.2.13INTSTS—Interrupt Status Register

(Intel® High Definition Audio Controller—D27:F0)........................ 779

22 Datasheet

18.1.2.14WALCLK—Wall Clock Counter Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 779

18.1.2.15SSYNC—Stream Synchronization Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 780

18.1.2.16CORBLBASE—CORB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 780

18.1.2.17CORBUBASE—CORB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 781

18.1.2.18CORBWP—CORB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 781

18.1.2.19CORBRP—CORB Read Pointer Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 781

18.1.2.20CORBCTL—CORB Control Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 782

18.1.2.21CORBST—CORB Status Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 782

18.1.2.22CORBSIZE—CORB Size Register

Intel® High Definition Audio Controller—D27:F0) ........................ 782

18.1.2.23RIRBLBASE—RIRB Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 783

18.1.2.24RIRBUBASE—RIRB Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 783

18.1.2.25RIRBWP—RIRB Write Pointer Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 783

18.1.2.26RINTCNT—Response Interrupt Count Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 784

18.1.2.27RIRBCTL—RIRB Control Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 784

18.1.2.28RIRBSTS—RIRB Status Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 785

18.1.2.29RIRBSIZE—RIRB Size Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 785

18.1.2.30IC—Immediate Command Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 785

18.1.2.31IR—Immediate Response Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 786

18.1.2.32ICS—Immediate Command Status Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 786

18.1.2.33DPLBASE—DMA Position Lower Base Address Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 787

18.1.2.34DPUBASE—DMA Position Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 787

18.1.2.35SDCTL—Stream Descriptor Control Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 788

18.1.2.36SDSTS—Stream Descriptor Status Register
(Intel

®

High Definition Audio Controller—D27:F0) ....................... 789

18.1.2.37SDLPIB—Stream Descriptor Link Position in Buffer

Register (Intel® High Definition Audio Controller—D27:F0)........... 790

18.1.2.38SDCBL—Stream Descriptor Cyclic Buffer Length Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 790

18.1.2.39SDLVI—Stream Descriptor Last Valid Index Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 791

18.1.2.40SDFIFOW—Stream Descriptor FIFO Watermark Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 791

18.1.2.41ISDFIFOS—Input Stream Descriptor FIFO Size Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 792

18.1.2.42OSDFIFOS—Output Stream Descriptor FIFO Size Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 792

18.1.2.43SDFMT—Stream Descriptor Format Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 793

18.1.2.44SDBDPL—Stream Descriptor Buffer Descriptor List
Pointer Lower Base Address Register

®

(Intel

High Definition Audio Controller—D27:F0) ....................... 794

18.1.2.45SDBDPU—Stream Descriptor Buffer Descriptor List
Pointer Upper Base Address Register

(Intel® High Definition Audio Controller—D27:F0) ....................... 794

Datasheet 23

18.2 Integrated Digital Display Audio Registers, Verb IDs, and Device/Revision IDs .........795

18.2.1 Configuration Default Register ................................................................ 795

18.2.2 Integrated Digital Display Audio Device ID and Revision ID ........................ 799

19 SMBus Controller Registers (D31:F3) .....................................................................801

19.1 PCI Configuration Registers (SMBus—D31:F3) ..................................................... 801

19.1.1 VID—Vendor Identification Register (SMBus—D31:F3) ...............................801

19.1.2 DID—Device Identification Register (SMBus—D31:F3) ............................... 802

19.1.3 PCICMD—PCI Command Register (SMBus—D31:F3) ..................................802

19.1.4 PCISTS—PCI Status Register (SMBus—D31:F3) ........................................ 803

19.1.5 RID—Revision Identification Register (SMBus—D31:F3) .............................803

19.1.6 PI—Programming Interface Register (SMBus—D31:F3) .............................. 804

19.1.7 SCC—Sub Class Code Register (SMBus—D31:F3)...................................... 804

19.1.8 BCC—Base Class Code Register (SMBus—D31:F3)..................................... 804

19.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0

Register (SMBus—D31:F3).....................................................................804

19.1.10SMBMBAR1—D31_F3_SMBus Memory Base Address 1

Register (SMBus—D31:F3).....................................................................805

19.1.11SMB_BASE—SMBus Base Address Register

(SMBus—D31:F3) ................................................................................. 805

19.1.12SVID—Subsystem Vendor Identification Register

(SMBus—D31:F2/F4)............................................................................. 805

19.1.13SID—Subsystem Identification Register

(SMBus—D31:F2/F4)............................................................................. 806

19.1.14INT_LN—Interrupt Line Register (SMBus—D31:F3)....................................806

19.1.15INT_PN—Interrupt Pin Register (SMBus—D31:F3) .....................................806

19.1.16HOSTC—Host Configuration Register (SMBus—D31:F3).............................. 807

19.2 SMBus I/O and Memory Mapped I/O Registers..................................................... 808

19.2.1 HST_STS—Host Status Register (SMBus—D31:F3) ....................................809

19.2.2 HST_CNT—Host Control Register (SMBus—D31:F3)...................................810

19.2.3 HST_CMD—Host Command Register (SMBus—D31:F3) .............................. 812

19.2.4 XMIT_SLVA—Transmit Slave Address Register

(SMBus—D31:F3) ................................................................................. 812

19.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3) .....................................812

19.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3) .....................................812

19.2.7 Host_BLOCK_DB—Host Block Data Byte Register

(SMBus—D31:F3) ................................................................................. 813

19.2.8 PEC—Packet Error Check (PEC) Register

(SMBus—D31:F3) ................................................................................. 813

19.2.9 RCV_SLVA—Receive Slave Address Register

(SMBus—D31:F3) ................................................................................. 814

19.2.10SLV_DATA—Receive Slave Data Register (SMBus—D31:F3) ........................ 814

19.2.11AUX_STS—Auxiliary Status Register (SMBus—D31:F3) ..............................814

19.2.12AUX_CTL—Auxiliary Control Register (SMBus—D31:F3) ............................. 815

19.2.13SMLINK_PIN_CTL—SMLink Pin Control Register

(SMBus—D31:F3) ................................................................................. 815

19.2.14SMBus_PIN_CTL—SMBus Pin Control Register

(SMBus—D31:F3) ................................................................................. 816

19.2.15SLV_STS—Slave Status Register (SMBus—D31:F3) ...................................816

19.2.16SLV_CMD—Slave Command Register (SMBus—D31:F3) ............................. 817

19.2.17NOTIFY_DADDR—Notify Device Address Register

(SMBus—D31:F3) ................................................................................. 817

19.2.18NOTIFY_DLOW—Notify Data Low Byte Register

(SMBus—D31:F3) ................................................................................. 818

19.2.19NOTIFY_DHIGH—Notify Data High Byte Register

(SMBus—D31:F3) ................................................................................. 818

20 PCI Express* Configuration Registers ....................................................................819

20.1 PCI Express* Configuration Registers

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ................................................... 819

20.1.1 VID—Vendor Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................821

20.1.2 DID—Device Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................821

20.1.3 PCICMD—PCI Command Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................822

24 Datasheet

20.1.4 PCISTS—PCI Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 823

20.1.5 RID—Revision Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 824

20.1.6 PI—Programming Interface Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 824

20.1.7 SCC—Sub Class Code Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 824

20.1.8 BCC—Base Class Code Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 824

20.1.9 CLS—Cache Line Size Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 825

20.1.10PLT—Primary Latency Timer Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 825

20.1.11HEADTYP—Header Type Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 825

20.1.12BNUM—Bus Number Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 826

20.1.13SLT—Secondary Latency Timer Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 826

20.1.14IOBL—I/O Base and Limit Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 826

20.1.15SSTS—Secondary Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 827

20.1.16MBL—Memory Base and Limit Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 828

20.1.17PMBL—Prefetchable Memory Base and Limit Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 828

20.1.18PMBU32—Prefetchable Memory Base Upper 32 Bits

Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) .................. 829

20.1.19PMLU32—Prefetchable Memory Limit Upper 32 Bits

Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7) .................. 829

20.1.20CAPP—Capabilities List Pointer Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 829

20.1.21INTR—Interrupt Information Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 830

20.1.22BCTRL—Bridge Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)............................... 831

20.1.23CLIST—Capabilities List Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 832

20.1.24XCAP—PCI Express* Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 832

20.1.25DCAP—Device Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 833

20.1.26DCTL—Device Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 834

20.1.27DSTS—Device Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 835

20.1.28LCAP—Link Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 836

20.1.29LCTL—Link Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 838

20.1.30LSTS—Link Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 839

20.1.31SLCAP—Slot Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 840

20.1.32SLCTL—Slot Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 841

20.1.33SLSTS—Slot Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 842

20.1.34RCTL—Root Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 843

20.1.35RSTS—Root Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 843

20.1.36DCAP2—Device Capabilities 2 Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................................ 844

Datasheet 25

20.1.37DCTL2—Device Control 2 Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................844

20.1.38LCTL2—Link Control 2 Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................845

20.1.39LSTS2—Link Status 2 Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................845

20.1.40MID—Message Signaled Interrupt Identifiers Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................846

20.1.41MC—Message Signaled Interrupt Message Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................846

20.1.42MA—Message Signaled Interrupt Message Address

Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ............................ 846

20.1.43MD—Message Signaled Interrupt Message Data Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................847

20.1.44SVCAP—Subsystem Vendor Capability Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................847

20.1.45SVID—Subsystem Vendor Identification Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................847

20.1.46PMCAP—Power Management Capability Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................847

20.1.47PMC—PCI Power Management Capabilities Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................848

20.1.48PMCS—PCI Power Management Control and Status

Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ............................ 849

20.1.49MPC2—Miscellaneous Port Configuration Register 2

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................850

20.1.50MPC—Miscellaneous Port Configuration Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................851

20.1.51SMSCS—SMI/SCI Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................853

20.1.52RPDCGEN—Root Port Dynamic Clock Gating Enable

Register (PCI Express—D28:F0/F1/F2/F3/F4/F5/F6/F7).............................. 853

20.1.53PECR3—PCI Express* Configuration Register 3

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................854

20.1.54UES—Uncorrectable Error Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................855

20.1.55UEM—Uncorrectable Error Mask Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................856

20.1.56UEV—Uncorrectable Error Severity Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................857

20.1.57CES—Correctable Error Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................858

20.1.58CEM—Correctable Error Mask Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................858

20.1.59AECC—Advanced Error Capabilities and Control Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................859

20.1.60RES—Root Error Status Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................859

20.1.61PEETM—PCI Express* Extended Test Mode Register

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................860

21 High Precision Event Timer Registers.....................................................................861

21.1 Memory Mapped Registers ................................................................................ 861

21.1.1 GCAP_ID—General Capabilities and Identification Register ......................... 863

21.1.2 GEN_CONF—General Configuration Register ............................................. 863

21.1.3 GINTR_STA—General Interrupt Status Register.........................................864

21.1.4 MAIN_CNT—Main Counter Value Register.................................................864

21.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register .....................865

21.1.6 TIMn_COMP—Timer n Comparator Value Register .....................................868

21.1.7 TIMERn_PROCMSG_ROUT—Timer n Processor Message

Interrupt Rout Register..........................................................................869

22 Serial Peripheral Interface (SPI) ........................................................................... 871

22.1 Serial Peripheral Interface Memory Mapped Configuration Registers........................871

22.1.1 BFPR –BIOS Flash Primary Region Register

(SPI Memory Mapped Configuration Registers)..........................................873

26 Datasheet

22.1.2 HSFS—Hardware Sequencing Flash Status Register

(SPI Memory Mapped Configuration Registers) ......................................... 873

22.1.3 HSFC—Hardware Sequencing Flash Control Register

(SPI Memory Mapped Configuration Registers) ......................................... 875

22.1.4 FADDR—Flash Address Register

(SPI Memory Mapped Configuration Registers) ......................................... 875

22.1.5 FDATA0—Flash Data 0 Register

(SPI Memory Mapped Configuration Registers) ......................................... 876

22.1.6 FDATAN—Flash Data [N] Register

(SPI Memory Mapped Configuration Registers) ......................................... 876

22.1.7 FRAP—Flash Regions Access Permissions Register

(SPI Memory Mapped Configuration Registers) ......................................... 877

22.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register

(SPI Memory Mapped Configuration Registers) ......................................... 878

22.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register

(SPI Memory Mapped Configuration Registers) ......................................... 878

22.1.10FREG2—Flash Region 2 (Intel® ME) Register

(SPI Memory Mapped Configuration Registers) ......................................... 879

22.1.11FREG3—Flash Region 3 (GbE) Register

(SPI Memory Mapped Configuration Registers) ......................................... 879

22.1.12FREG4—Flash Region 4 (Platform Data) Register

(SPI Memory Mapped Configuration Registers) ......................................... 880

22.1.13PR0—Protected Range 0 Register

(SPI Memory Mapped Configuration Registers) ......................................... 880

22.1.14PR1—Protected Range 1 Register

(SPI Memory Mapped Configuration Registers) ......................................... 881

22.1.15PR2—Protected Range 2 Register

(SPI Memory Mapped Configuration Registers) ......................................... 881

22.1.16PR3—Protected Range 3 Register

(SPI Memory Mapped Configuration Registers) ......................................... 882

22.1.17PR4—Protected Range 4 Register

(SPI Memory Mapped Configuration Registers) ......................................... 882

22.1.18SSFS—Software Sequencing Flash Status Register

(SPI Memory Mapped Configuration Registers) ......................................... 883

22.1.19SSFC—Software Sequencing Flash Control Register

(SPI Memory Mapped Configuration Registers) ......................................... 884

22.1.20PREOP—Prefix Opcode Configuration Register

(SPI Memory Mapped Configuration Registers) ......................................... 885

22.1.21OPTYPE—Opcode Type Configuration Register

(SPI Memory Mapped Configuration Registers) ......................................... 885

22.1.22OPMENU—Opcode Menu Configuration Register

(SPI Memory Mapped Configuration Registers) ......................................... 886

22.1.23FDOC—Flash Descriptor Observability Control Register

(SPI Memory Mapped Configuration Registers) ......................................... 886

22.1.24FDOD—Flash Descriptor Observability Data Register

(SPI Memory Mapped Configuration Registers) ......................................... 887

22.1.25AFC—Additional Flash Control Register

(SPI Memory Mapped Configuration Registers) ......................................... 887

22.1.26LVSCC— Host Lower Vendor Specific Component Capabilities Register

(SPI Memory Mapped Configuration Registers) ......................................... 887

22.1.27UVSCC— Host Upper Vendor Specific Component Capabilities Register

(SPI Memory Mapped Configuration Registers) ......................................... 889

22.1.28FPB — Flash Partition Boundary Register

(SPI Memory Mapped Configuration Registers) ......................................... 890

22.1.29SRDL — Soft Reset Data Lock Register

(SPI Memory Mapped Configuration Registers) ......................................... 890

22.1.30SRDC — Soft Reset Data Control Register

(SPI Memory Mapped Configuration Registers) ......................................... 891

22.1.31SRD — Soft Reset Data Register

(SPI Memory Mapped Configuration Registers) ......................................... 891

22.2 Flash Descriptor Records .................................................................................. 891

22.3 OEM Section ................................................................................................... 891

22.4 GbE SPI Flash Program Registers....................................................................... 892

22.4.1 GLFPR –Gigabit LAN Flash Primary Region Register

(GbE LAN Memory Mapped Configuration Registers).................................. 893

22.4.2 HSFS—Hardware Sequencing Flash Status Register

(GbE LAN Memory Mapped Configuration Registers).................................. 893

Datasheet 27

22.4.3 HSFC—Hardware Sequencing Flash Control Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 895

22.4.4 FADDR—Flash Address Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 895

22.4.5 FDATA0—Flash Data 0 Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 896

22.4.6 FRAP—Flash Regions Access Permissions Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 896

22.4.7 FREG0—Flash Region 0 (Flash Descriptor) Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 897

22.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 897

22.4.9 FREG2—Flash Region 2 (Intel® ME) Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 897

22.4.10FREG3—Flash Region 3 (GbE) Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 898

22.4.11PR0—Protected Range 0 Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 898

22.4.12PR1—Protected Range 1 Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 899

22.4.13SSFS—Software Sequencing Flash Status Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 900

22.4.14SSFC—Software Sequencing Flash Control Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 901

22.4.15PREOP—Prefix Opcode Configuration Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 902

22.4.16OPTYPE—Opcode Type Configuration Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 902

22.4.17OPMENU—Opcode Menu Configuration Register

(GbE LAN Memory Mapped Configuration Registers) .................................. 903

23 Thermal Sensor Registers (D31:F6) .......................................................................905

23.1 PCI Bus Configuration Registers.........................................................................905

23.1.1 VID—Vendor Identification Register.........................................................906

23.1.2 DID—Device Identification Register ......................................................... 906

23.1.3 CMD—Command Register ......................................................................906

23.1.4 STS—Status Register ............................................................................ 907

23.1.5 RID—Revision Identification Register .......................................................907

23.1.6 PI— Programming Interface Register.......................................................907

23.1.7 SCC—Sub Class Code Register................................................................ 908

23.1.8 BCC—Base Class Code Register ..............................................................908

23.1.9 CLS—Cache Line Size Register................................................................ 908

23.1.10LT—Latency Timer Register.................................................................... 908

23.1.11HTYPE—Header Type Register ................................................................908

23.1.12TBAR—Thermal Base Register ................................................................909

23.1.13TBARH—Thermal Base High DWord Register............................................. 909

23.1.14SVID—Subsystem Vendor ID Register .....................................................909

23.1.15SID—Subsystem ID Register ..................................................................910

23.1.16CAP_PTR—Capabilities Pointer Register .................................................... 910

23.1.17INTLN—Interrupt Line Register ...............................................................910

23.1.18INTPN—Interrupt Pin Register ................................................................910

23.1.19TBARB—BIOS Assigned Thermal Base Address Register .............................911

23.1.20TBARBH—BIOS Assigned Thermal Base High

DWord Register .................................................................................... 911

23.1.21PID—PCI Power Management Capability ID Register .................................. 911

23.1.22PC—Power Management Capabilities Register ........................................... 912

23.1.23PCS—Power Management Control And Status Register ............................... 912

23.2 Thermal Memory Mapped Configuration Registers

(Thermal Sensor – D31:F26).............................................................................913

23.2.1 TSIU—Thermal Sensor In Use Register ....................................................914

23.2.2 TSE—Thermal Sensor Enable Register ..................................................... 914

23.2.3 TSS—Thermal Sensor Status Register......................................................914

23.2.4 TSTR—Thermal Sensor Thermometer Read Register ..................................915

23.2.5 TSTTP—Thermal Sensor Temperature Trip Point Register ...........................915

23.2.6 TSCO—Thermal Sensor Catastrophic Lock-Down Register...........................915

23.2.7 TSES—Thermal Sensor Error Status Register............................................ 916

28 Datasheet

23.2.8 TSGPEN—Thermal Sensor General Purpose Event

Enable Register.................................................................................... 917

23.2.9 TSPC—Thermal Sensor Policy Control Register ......................................... 918

23.2.10PTA—PCH Temperature Adjust Register ................................................... 919

23.2.11TRC—Thermal Reporting Control Register ................................................ 919

23.2.12AE—Alert Enable Register ...................................................................... 920

23.2.13PTL— Processor Temperature Limit Register............................................. 920

23.2.14PTV — Processor Temperature Value Register .......................................... 920

23.2.15TT — Thermal Throttling Register ........................................................... 921

23.2.16PHL — PCH Hot Level Register................................................................ 921

23.2.17TSPIEN—Thermal Sensor PCI Interrupt Enable Register ............................. 922

23.2.18TSLOCK—Thermal Sensor Register Lock Control Register........................... 923

23.2.19TC2—Thermal Compares 2 Register ........................................................ 923

23.2.20DTV—DIMM Temperature Values Register ................................................ 924

23.2.21ITV—Internal Temperature Values Register.............................................. 924

24 Intel® Management Engine Subsystem Registers (D22:F[3:0]) ............................. 925

24.1 First Intel

®

Management Engine Interface (Intel®MEI) Configuration Registers

(Intel® MEI 1 — D22:F0) ................................................................................. 925

24.1.1 PCI Configuration Registers (Intel® MEI 1—D22:F0) ................................. 925

24.1.1.1 VID—Vendor Identification Register

(Intel® MEI 1—D22:F0) ........................................................... 926

24.1.1.2 DID—Device Identification Register

(Intel® MEI 1—D22:F0) ........................................................... 926

24.1.1.3 PCICMD—PCI Command Register

(Intel® MEI 1—D22:F0) ........................................................... 927

24.1.1.4 PCISTS—PCI Status Register

(Intel® MEI 1—D22:F0) ........................................................... 927

24.1.1.5 RID—Revision Identification Register

(Intel® MEI 1—D22:F0) ........................................................... 928

24.1.1.6 CC—Class Code Register

(Intel® MEI 1—D22:F0) ........................................................... 928

24.1.1.7 HTYPE—Header Type Register

(Intel® MEI 1—D22:F0) ........................................................... 928

24.1.1.8 MEI0_MBAR—Intel MEI 1 MMIO Base Address

(Intel® MEI 1—D22:F0) ........................................................... 928

24.1.1.9 SVID—Subsystem Vendor ID Register

(Intel® MEI 1—D22:F0) ........................................................... 929

24.1.1.10SID—Subsystem ID Register

(Intel® MEI 1—D22:F0) ........................................................... 929

24.1.1.11CAPP—Capabilities List Pointer Register

(Intel® MEI 1—D22:F0) ........................................................... 929

24.1.1.12INTR—Interrupt Information Register

(Intel® MEI 1—D22:F0) ........................................................... 929

24.1.1.13HFS—Host Firmware Status Register

(Intel

®

MEI 1—D22:F0) ........................................................... 930

24.1.1.14ME_UMA—Intel® Management Engine UMA Register

(Intel® MEI 1—D22:F0) ........................................................... 930

24.1.1.15GMES—General Intel® ME Status Register

(Intel® MEI 1—D22:F0) ........................................................... 930

24.1.1.16H_GS—Host General Status Register

(Intel® MEI 1—D22:F0) ........................................................... 931

24.1.1.17PID—PCI Power Management Capability ID Register

(Intel® MEI 1—D22:F0) ........................................................... 931

24.1.1.18PC—PCI Power Management Capabilities Register

(Intel® MEI 1—D22:F0) ........................................................... 931

24.1.1.19PMCS—PCI Power Management Control and Status

Register (Intel® MEI 1—D22:F0)............................................... 932

24.1.1.20MID—Message Signaled Interrupt Identifiers Register

(Intel® MEI 1—D22:F0) ........................................................... 932

24.1.1.21MC—Message Signaled Interrupt Message Control Register

(Intel

®

MEI 1—D22:F0) ........................................................... 933

24.1.1.22MA—Message Signaled Interrupt Message Address Register

(Intel® MEI 1—D22:F0) ........................................................... 933

24.1.1.23MUA—Message Signaled Interrupt Upper Address Register

(Intel® MEI 1—D22:F0) ........................................................... 933

Datasheet 29

24.1.1.24MD—Message Signaled Interrupt Message Data Register

(Intel® MEI 1—D22:F0) ...........................................................933

24.1.1.25HIDM—MEI Interrupt Delivery Mode Register

(Intel® MEI 1—D22:F0) ...........................................................934

24.1.1.26HERES—Intel® MEI Extend Register Status

(Intel® MEI 1—D22:F0) ...........................................................934

24.1.1.27HER[1:8]—Intel® MEI Extend Register DWX

(Intel® MEI 1—D22:F0) ...........................................................935

24.1.2 MEI0_MBAR—Intel® MEI 1 MMIO Registers ..............................................935

24.1.2.1 H_CB_WW—Host Circular Buffer Write Window Register

(Intel® MEI 1 MMIO Register) ...................................................935

24.1.2.2 H_CSR—Host Control Status Register

(Intel® MEI 1 MMIO Register) ...................................................936

24.1.2.3 ME_CB_RW—Intel® ME Circular Buffer Read Window Register

(Intel® MEI 1 MMIO Register) ...................................................937

24.1.2.4 ME_CSR_HA—Intel® ME Control Status Host Access Register

(Intel® MEI 1 MMIO Register) ...................................................937

24.2 Second Intel® Management Engine Interface
(Intel® MEI 2) Configuration Registers

(Intel® MEI 2—D22:F1)....................................................................................938

24.2.1 PCI Configuration Registers (Intel® MEI 2—D22:F2).................................. 938

24.2.1.1 VID—Vendor Identification Register

(Intel® MEI 2—D22:F1) ...........................................................939

24.2.1.2 DID—Device Identification Register

(Intel® MEI 2—D22:F1) ...........................................................939

24.2.1.3 PCICMD—PCI Command Register

(Intel® MEI 2—D22:F1) ...........................................................939

24.2.1.4 PCISTS—PCI Status Register

(Intel® MEI 2—D22:F1) ...........................................................940

24.2.1.5 RID—Revision Identification Register

(Intel® MEI 2—D22:F1) ...........................................................940

24.2.1.6 CC—Class Code Register

(Intel® MEI 2—D22:F1) ...........................................................940

24.2.1.7 HTYPE—Header Type Register

(Intel® MEI 2—D22:F1) ...........................................................940

24.2.1.8 MEI1_MBAR—Intel MEI 2 MMIO Base Address

(Intel® MEI 2—D22:F1) ...........................................................941

24.2.1.9 SVID—Subsystem Vendor ID Register

(Intel® MEI 2—D22:F1) ...........................................................941

24.2.1.10SID—Subsystem ID Register

(Intel® MEI 2—D22:F1) ...........................................................941

24.2.1.11CAPP—Capabilities List Pointer Register

(Intel® MEI 2—D22:F1) ...........................................................942

24.2.1.12INTR—Interrupt Information Register
(Intel

®

MEI 2—D22:F1) ...........................................................942

24.2.1.13HFS—Host Firmware Status Register

(Intel® MEI 2—D22:F1) ...........................................................942

24.2.1.14GMES—General Intel® ME Status Register

(Intel® MEI 2—D22:F1) ...........................................................942

24.2.1.15H_GS—Host General Status Register

(Intel® MEI 2—D22:F1) ...........................................................943

24.2.1.16PID—PCI Power Management Capability ID Register

(Intel® MEI 2—D22:F1) ...........................................................943

24.2.1.17PC—PCI Power Management Capabilities Register

(Intel® MEI 2—D22:F1) ...........................................................943

24.2.1.18PMCS—PCI Power Management Control and Status

Register (Intel® MEI 2—D22:F1) ...............................................944

24.2.1.19MID—Message Signaled Interrupt Identifiers Register

(Intel® MEI 2—D22:F1) ...........................................................944

24.2.1.20MC—Message Signaled Interrupt Message Control Register
(Intel

®

MEI 2—D22:F1) ...........................................................945

24.2.1.21MA—Message Signaled Interrupt Message Address Register

(Intel® MEI 2—D22:F1) ...........................................................945

24.2.1.22MUA—Message Signaled Interrupt Upper Address Register

(Intel® MEI 2—D22:F1) ...........................................................945

24.2.1.23MD—Message Signaled Interrupt Message Data Register

(Intel® MEI 2—D22:F1) ...........................................................946

30 Datasheet

24.2.1.24HIDM—Intel® MEI Interrupt Delivery Mode Register

(Intel® MEI 2—D22:F1) ........................................................... 946

24.2.1.25HERES—Intel® MEI Extend Register Status

(Intel® MEI 2—D22:F1) ........................................................... 946

24.2.1.26HER[1:8]—Intel® MEI Extend Register DWX

(Intel® MEI 2—D22:F1) ........................................................... 947

24.2.2 MEI1_MBAR—Intel® MEI 2 MMIO Registers.............................................. 947

24.2.2.1 H_CB_WW—Host Circular Buffer Write Window

(Intel® MEI 2 MMIO Register)................................................... 947

24.2.2.2 H_CSR—Host Control Status Register

(Intel® MEI 2 MMIO Register)................................................... 948

24.2.2.3 ME_CB_RW—Intel® ME Circular Buffer Read Window Register

(Intel® MEI 2 MMIO Register)................................................... 949

24.2.2.4 ME_CSR_HA—Intel® ME Control Status Host Access Register

(Intel® MEI 2 MMIO Register)................................................... 949

24.3 IDE Redirect IDER Registers (IDER — D22:F2) .................................................... 950

24.3.1 PCI Configuration Registers (IDER—D22:F2) ............................................ 950

24.3.1.1 VID—Vendor Identification Register (IDER—D22:F2) ................... 951

24.3.1.2 DID—Device Identification Register (IDER—D22:F2).................... 951

24.3.1.3 PCICMD— PCI Command Register (IDER—D22:F2)...................... 951

24.3.1.4 PCISTS—PCI Device Status Register (IDER—D22:F2)................... 952

24.3.1.5 RID—Revision Identification Register (IDER—D22:F2).................. 952

24.3.1.6 CC—Class Codes Register (IDER—D22:F2) ................................. 952

24.3.1.7 CLS—Cache Line Size Register (IDER—D22:F2) .......................... 952

24.3.1.8 PCMDBA—Primary Command Block IO Bar

Register (IDER—D22:F2) ......................................................... 953

24.3.1.9 PCTLBA—Primary Control Block Base Address

Register (IDER—D22:F2) ......................................................... 953

24.3.1.10SCMDBA—Secondary Command Block Base Address

Register (IDER—D22:F2) ......................................................... 953

24.3.1.11SCTLBA—Secondary Control Block base Address

Register (IDER—D22:F2) ......................................................... 954

24.3.1.12LBAR—Legacy Bus Master Base Address Register

(IDER—D22:F2)...................................................................... 954

24.3.1.13SVID—Subsystem Vendor ID Register (IDER—D22:F2) ................ 954

24.3.1.14SID—Subsystem ID Register (IDER—D22:F2) ............................. 954

24.3.1.15CAPP—Capabilities List Pointer Register

(IDER—D22:F2)...................................................................... 955

24.3.1.16INTR—Interrupt Information Register

(IDER—D22:F2)...................................................................... 955

24.3.1.17PID—PCI Power Management Capability ID Register

(IDER—D22:F2)...................................................................... 955

24.3.1.18PC—PCI Power Management Capabilities Register

(IDER—D22:F2)...................................................................... 956

24.3.1.19PMCS—PCI Power Management Control and Status

Register (IDER—D22:F2) ......................................................... 956

24.3.1.20MID—Message Signaled Interrupt Capability ID

Register (IDER—D22:F2) ......................................................... 957

24.3.1.21MC—Message Signaled Interrupt Message Control

Register (IDER—D22:F2) ......................................................... 957

24.3.1.22MA—Message Signaled Interrupt Message Address

Register (IDER—D22:F2) ......................................................... 957

24.3.1.23MAU—Message Signaled Interrupt Message Upper

Address Register (IDER—D22:F2) ............................................. 957

24.3.1.24MD—Message Signaled Interrupt Message Data

Register (IDER—D22:F2) ......................................................... 958

24.3.2 IDER BAR0 Registers ............................................................................ 958

24.3.2.1 IDEDATA—IDE Data Register (IDER—D22:F2) ............................ 959

24.3.2.2 IDEERD1—IDE Error Register DEV1

(IDER—D22:F2)...................................................................... 959

24.3.2.3 IDEERD0—IDE Error Register DEV0

(IDER—D22:F2)...................................................................... 960

24.3.2.4 IDEFR—IDE Features Register

(IDER—D22:F2)...................................................................... 960

24.3.2.5 IDESCIR—IDE Sector Count In Register

(IDER—D22:F2)...................................................................... 960

Datasheet 31

24.3.2.6 IDESCOR1—IDE Sector Count Out Register Device 1

Register (IDER—D22:F2)..........................................................961

24.3.2.7 IDESCOR0—IDE Sector Count Out Register Device

0 Register (IDER—D22:F2).......................................................961

24.3.2.8 IDESNOR0—IDE Sector Number Out Register

Device 0 Register (IDER—D22:F2).............................................961

24.3.2.9 IDESNOR1—IDE Sector Number Out Register

Device 1 Register (IDER—D22:F2).............................................962

24.3.2.10IDESNIR—IDE Sector Number In Register (IDER—D22:F2) ...........962

24.3.2.11IDECLIR—IDE Cylinder Low In Register (IDER—D22:F2)............... 962

24.3.2.12IDCLOR1—IDE Cylinder Low Out Register Device 1

Register (IDER—D22:F2)..........................................................963

24.3.2.13IDCLOR0—IDE Cylinder Low Out Register Device 0

Register (IDER—D22:F2)..........................................................963

24.3.2.14IDCHOR0—IDE Cylinder High Out Register Device 0

Register (IDER—D22:F2)..........................................................963

24.3.2.15IDCHOR1—IDE Cylinder High Out Register Device 1

Register (IDER—D22:F2)..........................................................964

24.3.2.16IDECHIR—IDE Cylinder High In Register

(IDER—D22:F2) ......................................................................964

24.3.2.17IDEDHIR—IDE Drive/Head In Register

(IDER—D22:F2) ......................................................................964

24.3.2.18IDDHOR1—IDE Drive Head Out Register Device 1

Register (IDER—D22:F2)..........................................................965

24.3.2.19IDDHOR0—IDE Drive Head Out Register Device 0

Register (IDER—D22:F2)..........................................................965

24.3.2.20IDESD0R—IDE Status Device 0 Register

(IDER—D22:F2) ......................................................................966

24.3.2.21IDESD1R—IDE Status Device 1 Register

(IDER—D22:F2) ......................................................................967

24.3.2.22IDECR—IDE Command Register (IDER—D22:F2) ......................... 967

24.3.3 IDER BAR1 Registers............................................................................. 968

24.3.3.1 IDDCR—IDE Device Control Register (IDER—D22:F2)...................968

24.3.3.2 IDASR—IDE Alternate Status Register (IDER—D22:F2).................968

24.3.4 IDER BAR4 Registers............................................................................. 969

24.3.4.1 IDEPBMCR—IDE Primary Bus Master Command

Register (IDER—D22:F2)..........................................................970

24.3.4.2 IDEPBMDS0R—IDE Primary Bus Master Device

Specific 0 Register (IDER—D22:F2) ........................................... 970

24.3.4.3 IDEPBMSR—IDE Primary Bus Master Status

Register (IDER—D22:F2)..........................................................971

24.3.4.4 IDEPBMDS1R—IDE Primary Bus Master Device

Specific 1 Register (IDER—D22:F2) ........................................... 971

24.3.4.5 IDEPBMDTPR0—IDE Primary Bus Master Descriptor

Table Pointer Byte 0 Register (IDER—D22:F2)............................. 971

24.3.4.6 IDEPBMDTPR1—IDE Primary Bus Master Descriptor

Table Pointer Byte 1 Register (IDER—D22:F2)............................. 972

24.3.4.7 IDEPBMDTPR2—IDE Primary Bus Master Descriptor

Table Pointer Byte 2 Register (IDER—D22:F2)............................. 972

24.3.4.8 IDEPBMDTPR3—IDE Primary Bus Master Descriptor

Table Pointer Byte 3 Register (IDER—D22:F2)............................. 972

24.3.4.9 IDESBMCR—IDE Secondary Bus Master Command

Register (IDER—D22:F2)..........................................................972

24.3.4.10IDESBMDS0R—IDE Secondary Bus Master Device

Specific 0 Register (IDER—D22:F2) ........................................... 973

24.3.4.11IDESBMSR—IDE Secondary Bus Master Status

Register (IDER—D22:F2)..........................................................973

24.3.4.12IDESBMDS1R—IDE Secondary Bus Master Device

Specific 1 Register (IDER—D22:F2) ........................................... 973

24.3.4.13IDESBMDTPR0—IDE Secondary Bus Master Descriptor

Table Pointer Byte 0 Register (IDER—D22:F2)............................. 974

24.3.4.14IDESBMDTPR1—IDE Secondary Bus Master Descriptor

Table Pointer Byte 1 Register (IDER—D22:F2)............................. 974

24.3.4.15IDESBMDTPR2—IDE Secondary Bus Master Descriptor

Table Pointer Byte 2 Register (IDER—D22:F2)............................. 974

24.3.4.16IDESBMDTPR3—IDE Secondary Bus Master Descriptor

Table Pointer Byte 3 Register (IDER—D22:F2)............................. 974

32 Datasheet

24.4 Serial Port for Remote Keyboard and Text (KT)

Redirection (KT — D22:F3) ............................................................................... 975

24.4.1 PCI Configuration Registers (KT — D22:F3) ............................................. 975

24.4.1.1 VID—Vendor Identification Register (KT—D22:F3)....................... 975

24.4.1.2 DID—Device Identification Register (KT—D22:F3) ....................... 976

24.4.1.3 CMD—Command Register (KT—D22:F3) .................................... 976

24.4.1.4 STS—Device Status Register (KT—D22:F3) ................................ 976

24.4.1.5 RID—Revision ID Register (KT—D22:F3).................................... 977

24.4.1.6 CC—Class Codes Register (KT—D22:F3) .................................... 977

24.4.1.7 CLS—Cache Line Size Register (KT—D22:F3).............................. 977

24.4.1.8 KTIBA—KT IO Block Base Address Register

(KT—D22:F3)......................................................................... 977

24.4.1.9 KTMBA—KT Memory Block Base Address Register

(KT—D22:F3)......................................................................... 978

24.4.1.10SVID—Subsystem Vendor ID Register (KT—D22:F3).................... 978

24.4.1.11SID—Subsystem ID Register (KT—D22:F3) ................................ 978

24.4.1.12CAP—Capabilities Pointer Register (KT—D22:F3)......................... 978

24.4.1.13INTR—Interrupt Information Register (KT—D22:F3) .................... 979

24.4.1.14PID—PCI Power Management Capability ID Register

(KT—D22:F3)......................................................................... 979

24.4.1.15PC—PCI Power Management Capabilities ID Register

(KT—D22:F3)......................................................................... 979

24.4.1.16MID—Message Signaled Interrupt Capability ID

Register (KT—D22:F3)............................................................. 980

24.4.1.17MC—Message Signaled Interrupt Message Control

Register (KT—D22:F3)............................................................. 980

24.4.1.18MA—Message Signaled Interrupt Message Address

Register (KT—D22:F3)............................................................. 980

24.4.1.19MAU—Message Signaled Interrupt Message Upper

Address Register (KT—D22:F3)................................................. 981

24.4.1.20MD—Message Signaled Interrupt Message Data

Register (KT—D22:F3)............................................................. 981

24.4.2 KT IO/Memory Mapped Device Registers ................................................. 981

24.4.2.1 KTRxBR—KT Receive Buffer Register (KT—D22:F3) ..................... 982

24.4.2.2 KTTHR—KT Transmit Holding Register (KT—D22:F3) ................... 982

24.4.2.3 KTDLLR—KT Divisor Latch LSB Register (KT—D22:F3) ................. 982

24.4.2.4 KTIER—KT Interrupt Enable Register (KT—D22:F3) ..................... 983

24.4.2.5 KTDLMR—KT Divisor Latch MSB Register (KT—D22:F3)................ 983

24.4.2.6 KTIIR—KT Interrupt Identification Register

(KT—D22:F3)......................................................................... 984

24.4.2.7 KTFCR—KT FIFO Control Register (KT—D22:F3).......................... 984

24.4.2.8 KTLCR—KT Line Control Register (KT—D22:F3)........................... 985

24.4.2.9 KTMCR—KT Modem Control Register (KT—D22:F3)...................... 985

24.4.2.10KTLSR—KT Line Status Register (KT—D22:F3)............................ 986

24.4.2.11KTMSR—KT Modem Status Register (KT—D22:F3)....................... 987

Datasheet 33

Figures

2-1 PCH Interface Signals Block Diagram (not all signals are on all SKUs)..........................58

2-2 Example External RTC Circuit.................................................................................97

4-1 PCH High-Level Clock Diagram.............................................................................121

5-1 Generation of SERR# to Platform ......................................................................... 132

5-2 LPC Interface Diagram ........................................................................................141

5-3 PCH DMA Controller............................................................................................145

5-4 DMA Request Assertion through LDRQ# ................................................................148

5-5 TCO Legacy/Compatible Mode SMBus Configuration ................................................196

5-6 Advanced TCO Mode...........................................................................................197

5-7 Serial Post over GPIO Reference Circuit.................................................................199

5-8 Flow for Port Enable / Device Present Bits.............................................................. 208

5-9 Serial Data transmitted over the SGPIO Interface ................................................... 212

5-10 EHCI with USB 2.0 with Rate Matching Hub ...........................................................227

5-11 PCH Intel® Management Engine High-Level Block Diagram ...................................... 257

5-12 Flash Descriptor Sections .................................................................................... 260

5-13 PCH Display Architecture.....................................................................................269

5-14 LVDS Signals and Swing Voltage ..........................................................................271

5-15 LVDS Clock and Data Relationship ........................................................................272

5-16 Panel Power Sequencing ..................................................................................... 273

5-17 HDMI* Overview ................................................................................................274

5-18 DisplayPort* Overview ........................................................................................275

5-19 Intel® SDVO Conceptual Block Diagram ................................................................277

6-1 Desktop PCH Ballout (Top View - Upper Left) ......................................................... 285

6-2 Desktop PCH Ballout (Top View - Lower Left) .........................................................286

6-3 Desktop PCH Ballout (Top View - Upper Right) ....................................................... 287

6-4 Desktop PCH Ballout (Top View - Lower Right) ....................................................... 288

6-5 Mobile PCH Ballout (Top View - Upper Left)............................................................297

6-6 Mobile PCH Ballout (Top View - Lower Left)............................................................298

6-7 Mobile PCH Ballout (Top View - Upper Right).......................................................... 299

6-8 Mobile PCH Ballout (Top View - Lower Right).......................................................... 300

6-9 Mobile SFF PCH Ballout (Top View - Upper Left)......................................................309

6-10 Mobile SFF PCH Ballout (Top View - Lower Left)......................................................310

6-11 Mobile SFF PCH Ballout (Top View - Upper Right).................................................... 311

6-12 Mobile SFF PCH Ballout (Top View - Lower Right).................................................... 312

7-1 Desktop PCH Package Drawing.............................................................................324

7-2 Mobile PCH Package Drawing ...............................................................................326

7-3 Mobile SFF PCH Package Drawing ......................................................................... 328

8-1 G3 w/RTC Loss to S4/S5 (With Deep Sx Support) Timing Diagram............................365

8-2 G3 w/RTC Loss to S4/S5 (Without Deep Sx Support) Timing Diagram .......................365

8-3 S5 to S0 Timing Diagram ....................................................................................366

8-4 S3/M3 to S0 Timing Diagram...............................................................................367

8-5 S5/Moff - S5/M3 Timing Diagram ......................................................................... 367

8-6 S0 to S5 Timing Diagram ....................................................................................368

8-7 S3/S4/S5 to Deep Sx to G3 w/ RTC Loss Timing Diagram ........................................369

8-8 DRAMPWROK Timing Diagram..............................................................................369

8-9 Clock Cycle Time................................................................................................370

8-10 Transmitting Position (Data to Strobe) ..................................................................370

8-11 Clock Timing......................................................................................................370

8-13 Setup and Hold Times.........................................................................................371

8-14 Float Delay........................................................................................................371

8-15 Pulse Width ....................................................................................................... 371

8-12 Valid Delay from Rising Clock Edge.......................................................................371

8-16 Output Enable Delay...........................................................................................372

8-17 USB Rise and Fall Times......................................................................................372

8-18 USB Jitter .........................................................................................................372

8-19 USB EOP Width.................................................................................................. 373

8-20 SMBus/SMLink Transaction..................................................................................373

8-21 SMBus/SMLink Timeout....................................................................................... 373

8-22 SPI Timings.......................................................................................................374

8-23 Intel® High Definition Audio Input and Output Timings............................................ 374

8-24 Dual Channel Interface Timings............................................................................375

8-25 Dual Channel Interface Timings............................................................................375

8-26 LVDS Load and Transition Times ..........................................................................375

8-27 Transmitting Position (Data to Strobe) ..................................................................376

8-28 PCI Express* Transmitter Eye .............................................................................. 376

34 Datasheet

8-29 PCI Express* Receiver Eye.................................................................................. 377

8-30 Measurement Points for Differential Waveforms ..................................................... 378

8-31 PCH Test Load................................................................................................... 379

8-32 Controller Link Receive Timings ........................................................................... 379

8-33 Controller Link Receive Slew Rate ....................................................................... 379

Tables

1-1 Industry Specifications ......................................................................................... 44

1-2 Desktop Intel® 7 Series Chipset Family SKUs .......................................................... 54

1-3 Mobile Intel® 7 Series Chipset Family SKUs............................................................. 55

1-4 Intel® C216 Chipset SKU ...................................................................................... 56

2-1 Direct Media Interface Signals ............................................................................... 59

2-2 PCI Express* Signals............................................................................................ 59

2-3 PCI Interface Signals............................................................................................ 60

2-4 Serial ATA Interface Signals .................................................................................. 63

2-5 LPC Interface Signals ........................................................................................... 66

2-6 Interrupt Signals ................................................................................................. 66

2-7 USB Interface Signals........................................................................................... 67

2-8 Power Management Interface Signals ..................................................................... 69

2-9 Processor Interface Signals ................................................................................... 73

2-10 SM Bus Interface Signals ...................................................................................... 73

2-11 System Management Interface Signals ................................................................... 74

2-12 Real Time Clock Interface ..................................................................................... 74

2-13 Miscellaneous Signals ........................................................................................... 75

2-14 Intel® High Definition Audio Link Signals................................................................. 76

2-15 Controller Link Signals.......................................................................................... 77

2-16 Serial Peripheral Interface (SPI) Signals.................................................................. 77

2-17 Thermal Signals................................................................................................... 78

2-18 Testability Signals................................................................................................ 78

2-19 Clock Interface Signals ......................................................................................... 79

2-20 LVDS Interface Signals ......................................................................................... 81

2-21 Analog Display Interface Signals ............................................................................ 82

2-22 Intel® Flexible Display Interface Signals ................................................................. 82

2-23 Digital Display Interface Signals............................................................................. 83

2-24 General Purpose I/O Signals.................................................................................. 85

2-25 Manageability Signals ........................................................................................... 90

2-26 Power and Ground Signals .................................................................................... 90

2-27 Functional Strap Definitions................................................................................... 93

3-1 Integrated Pull-Up and Pull-Down Resistors............................................................. 99

3-2 Power Plane and States for Output and I/O Signals for Desktop Configurations .......... 101

3-3 Power Plane and States for Output and I/O Signals for Mobile Configurations ............. 107

3-4 Power Plane for Input Signals for Desktop Configurations ........................................ 113

3-5 Power Plane for Input Signals for Mobile Configurations .......................................... 116

4-1 PCH Clock Inputs............................................................................................... 119

4-2 Clock Outputs ................................................................................................... 120

4-3 PCH PLLs .......................................................................................................... 122

4-4 SSC Blocks ....................................................................................................... 123

5-1 PCI Bridge Initiator Cycle Types........................................................................... 126

5-2 Type 1 Address Format....................................................................................... 128

5-3 MSI versus PCI IRQ Actions................................................................................. 130

5-4 LAN Mode Support ............................................................................................. 137

5-5 LPC Cycle Types Supported................................................................................. 141

5-6 Start Field Bit Definitions .................................................................................... 142

5-7 Cycle Type Bit Definitions ................................................................................... 142

5-8 Transfer Size Bit Definition.................................................................................. 142

5-9 SYNC Bit Definition ............................................................................................ 143

5-10 DMA Transfer Size ............................................................................................. 146

5-11 Address Shifting in 16-Bit I/O DMA Transfers......................................................... 147

5-12 Counter Operating Modes ................................................................................... 152

5-13 Interrupt Controller Core Connections................................................................... 154

5-14 Interrupt Status Registers................................................................................... 155

5-15 Content of Interrupt Vector Byte.......................................................................... 155

5-16 APIC Interrupt Mapping1 .................................................................................... 161

5-17 Stop Frame Explanation...................................................................................... 163

5-18 Data Frame Format............................................................................................ 164

5-19 Configuration Bits Reset by RTCRST# Assertion ..................................................... 167

Datasheet 35

5-20 INIT# Going Active.............................................................................................168

5-21 NMI Sources...................................................................................................... 169

5-22 General Power States for Systems Using the PCH ...................................................171

5-23 State Transition Rules for the PCH ........................................................................ 172

5-24 System Power Plane ...........................................................................................173

5-25 Causes of SMI and SCI .......................................................................................174

5-26 Sleep Types....................................................................................................... 178

5-27 Causes of Wake Events ....................................................................................... 178

5-28 GPI Wake Events ...............................................................................................180

5-29 Transitions Due to Power Failure ..........................................................................181

5-30 Supported Deep Sx Policy Configurations...............................................................181

5-31 Deep Sx Wake Events.........................................................................................182

5-32 Transitions Due to Power Button .......................................................................... 183

5-33 Transitions Due to RI# Signal ..............................................................................184

5-34 Write Only Registers with Read Paths in ALT Access Mode........................................186

5-35 PIC Reserved Bits Return Values .......................................................................... 188

5-36 Register Write Accesses in ALT Access Mode ..........................................................188

5-37 SLP_LAN# Pin Behavior ......................................................................................190

5-38 SUSPWRDNACK/SUSWARN#/GPIO30 Steady State Pin Behavior...............................191

5-39 SUSPWRDNACK During Reset .............................................................................. 191

5-40 Causes of Host and Global Resets.........................................................................193

5-41 Event Transitions that Cause Messages .................................................................196

5-42 Multi-activity LED Message Type........................................................................... 211

5-43 Legacy Replacement Routing ...............................................................................214

5-44 Debug Port Behavior...........................................................................................221

5-45 I2C Block Read...................................................................................................231

5-46 Enable for SMBALERT# ....................................................................................... 233

5-47 Enables for SMBus Slave Write and SMBus Host Events...........................................234

5-48 Enables for the Host Notify Command ...................................................................234

5-49 Slave Write Registers.......................................................................................... 236

5-50 Command Types ................................................................................................236

5-51 Slave Read Cycle Format.....................................................................................237

5-52 Data Values for Slave Read Registers.................................................................... 238

5-53 Host Notify Format ............................................................................................. 240

5-54 PCH Thermal Throttle States (T-states) .................................................................243

5-55 PCH Thermal Throttling Configuration Register .......................................................243

5-56 I2C Write Commands to the Intel® ME ..................................................................245

5-57 Block Read Command – Byte Definition................................................................. 246

5-58 Region Size versus Erase Granularity of Flash Components ...................................... 259

5-59 Region Access Control Table ................................................................................261

5-60 Hardware Sequencing Commands and Opcode Requirements ...................................264

5-61 Flash Protection Mechanism Summary ..................................................................265

5-62 Recommended Pinout for 8-Pin Serial Flash Device ................................................. 266

5-63 Recommended Pinout for 16-Pin Serial Flash Device ...............................................267

5-64 Analog Port Characteristics ..................................................................................270

5-65 PCH Supported Audio Formats over HDMI and DisplayPort* .....................................276

5-66 PCH Digital Port Pin Mapping................................................................................ 277

5-67 Display Co-Existence Table..................................................................................279

5-68 Three Display Configurations Supported on Mobile Platforms....................................280

5-69 Three Display Configurations Supported on Desktop Platforms .................................280

6-1 Desktop PCH Ballout By Signal Name.................................................................... 289

6-2 Mobile PCH Ballout By Signal Name ......................................................................301

6-3 Mobile SFF PCH Ballout By Signal Name ................................................................313

8-1 Storage Conditions and Thermal Junction Operating Temperature Limits.................... 329

8-2 Mobile Thermal Design Power ..............................................................................330

8-3 PCH Absolute Maximum Ratings ...........................................................................330

8-4 PCH Power Supply Range ....................................................................................331

8-5 Measured I

8-6 Measured ICC (Mobile Only) .................................................................................332

(Desktop Only)............................................................................... 331

CC

8-7 DC Characteristic Input Signal Association .............................................................334

8-8 DC Input Characteristics .....................................................................................336

8-9 DC Characteristic Output Signal Association ........................................................... 339

8-10 DC Output Characteristics ...................................................................................340

8-11 Other DC Characteristics ..................................................................................... 343

8-12 Signal Groups .................................................................................................... 344

8-13 CRT DAC Signal Group DC Characteristics: Functional Operating Range

(VccADAC = 3.3 V ±5%).....................................................................................344

36 Datasheet

8-14 LVDS Interface: Functional Operating Range (VccALVDS = 1.8 V ±5%) .................... 345

8-15 DisplayPort* Auxiliary Signal Group DC Characteristics ........................................... 345

8-16 PCI Express* Interface Timings ........................................................................... 346

8-17 HDMI* Interface Timings (DDP[D:B][3:0])............................................................ 347

8-18 Intel® SDVO Interface Timings ............................................................................ 347

8-19 DisplayPort* Interface Timings (DDP[D:B][3:0]).................................................... 348

8-20 DisplayPort Aux Interface ................................................................................... 349

8-21 DDC Characteristics

DDC Signals: CRT_DDC_CLK, CRT_DDC_DATA, L_DDC_CLK, L_DDC_DATA,

SDVO_CTRLCLK, SDVO_CTRLDATA, DDP[D:C]_CTRLCLK, DDP[D:C]_CTRLDATA ........ 349

8-22 LVDS Interface AC Characteristics at Various Frequencies ....................................... 350

8-23 CRT DAC AC Characteristics ................................................................................ 351

8-24 Clock Timings.................................................................................................... 352

8-25 PCI Interface Timing .......................................................................................... 356

8-26 Universal Serial Bus Timing................................................................................. 357

8-27 SATA Interface Timings ...................................................................................... 358

8-28 SMBus and SMLink Timing .................................................................................. 358

8-29 Intel® High Definition Audio Timing...................................................................... 359

8-30 LPC Timing ....................................................................................................... 359

8-31 Miscellaneous Timings ........................................................................................ 360

8-32 SPI Timings (20 MHz)......................................................................................... 360

8-33 SPI Timings (33 MHz)......................................................................................... 360

8-34 SPI Timings (50 MHz)......................................................................................... 361

8-35 SST Timings (Server/Workstation Only) ................................................................ 361

8-36 Controller Link Receive Timings ........................................................................... 362

8-37 USB 3.0 Interface Transmit and Receiver Timings .................................................. 362

8-38 Power Sequencing and Reset Signal Timings.......................................................... 362

9-1 PCI Devices and Functions .................................................................................. 382

9-2 Fixed I/O Ranges Decoded by PCH ....................................................................... 384

9-3 Variable I/O Decode Ranges................................................................................ 386

9-4 Memory Decode Ranges from Processor Perspective ............................................... 387

9-5 SPI Mode Address Swapping ............................................................................... 389

10-1 Chipset Configuration Register Memory Map (Memory Space) .................................. 391

11-1 PCI Bridge Register Address Map (PCI-PCI—D30:F0) .............................................. 433

12-1 Gigabit LAN Configuration Registers Address Map

(Gigabit LAN —D25:F0) ...................................................................................... 449

12-2 Gigabit LAN Capabilities and Status Registers Address Map

(Gigabit LAN —MBARA) ...................................................................................... 462

13-1 LPC Interface PCI Register Address Map (LPC I/F—D31:F0) ..................................... 467

13-2 DMA Registers................................................................................................... 494

13-3 PIC Registers .................................................................................................... 504

13-4 APIC Direct Registers ......................................................................................... 512

13-5 APIC Indirect Registers....................................................................................... 512

13-6 RTC I/O Registers .............................................................................................. 517

13-7 RTC (Standard) RAM Bank .................................................................................. 518

13-8 Processor Interface PCI Register Address Map ....................................................... 522

13-9 Power Management PCI Register Address Map (PM—D31:F0)................................... 525

13-10 APM Register Map .............................................................................................. 534

13-11 ACPI and Legacy I/O Register Map ....................................................................... 535

13-12 TCO I/O Register Address Map............................................................................. 552

13-13 Registers to Control GPIO Address Map................................................................. 559

14-1 SATA Controller PCI Register Address Map (SATA–D31:F2)...................................... 569

14-2 Bus Master IDE I/O Register Address Map ............................................................. 598

14-3 AHCI Register Address Map................................................................................. 606

14-4 Generic Host Controller Register Address Map........................................................ 607

14-5 Port [5:0] DMA Register Address Map................................................................... 616

15-1 SATA Controller PCI Register Address Map (SATA–D31:F5)...................................... 633

15-2 Bus Master IDE I/O Register Address Map ............................................................. 649

16-1 USB EHCI PCI Register Address Map (USB EHCI—D29:F0, D26:F0) .......................... 657

16-2 Enhanced Host Controller Capability Registers ....................................................... 676

16-3 Enhanced Host Controller Operational Register Address Map.................................... 680

16-4 Debug Port Register Address Map ........................................................................ 693

17-1 USB xHCI PCI Register Address Map (USB xHCI—D20:F0)....................................... 697

17-2 Enhanced Host Controller Capability Registers ....................................................... 715

17-3 Enhanced Host Controller Operational Register Address Map.................................... 721

17-4 Enhanced Host Controller Operational Register Address Map.................................... 741

Datasheet 37

18-1 Intel® High Definition Audio PCI Register Address Map

(Intel® High Definition Audio D27:F0)...................................................................747

18-2 Intel® High Definition Audio Memory Mapped Configuration Registers

Address Map (Intel® High Definition Audio D27:F0) ................................................769

18-3 Configuration Default..........................................................................................795

18-4 Configuration Data Structure ...............................................................................795

18-5 Port Connectivity................................................................................................ 797

18-6 Location............................................................................................................ 797

18-7 Default Device ...................................................................................................797

18-8 Connection Type ................................................................................................ 798

18-9 Color ................................................................................................................ 798

18-10 Misc .................................................................................................................799

19-1 SMBus Controller PCI Register Address Map (SMBus—D31:F3) .................................801

19-2 SMBus I/O and Memory Mapped I/O Register Address Map ......................................808

20-1 PCI Express* Configuration Registers Address Map

(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)......................................................819

21-1 Memory-Mapped Register Address Map ................................................................. 861

22-1 Serial Peripheral Interface (SPI) Register Address Map

(SPI Memory Mapped Configuration Registers) ....................................................... 871

22-2 Gigabit LAN SPI Flash Program Register Address Map

(GbE LAN Memory Mapped Configuration Registers)................................................892

23-1 Thermal Sensor Register Address Map................................................................... 905

23-2 Thermal Memory Mapped Configuration Register Address Map..................................913

24-1 Intel® MEI 1 Configuration Registers Address Map

(Intel® MEI 1—D22:F0) ......................................................................................925

24-2 Intel® MEI 1 MMIO Register Address Map..............................................................935

24-3 Intel® MEI 2 Configuration Registers Address Map

(Intel® MEI 2—D22:F1) ......................................................................................938

24-4 Intel® MEI 2 MMIO Register Address Map..............................................................947

24-5 IDE Redirect Function IDER Register Address Map ..................................................950

24-6 IDER BAR0 Register Address Map .........................................................................958

24-7 IDER BAR1 Register Address Map .........................................................................968

24-8 IDER BAR4 Register Address Map .........................................................................969

24-9 Serial Port for Remote Keyboard and Text (KT) Redirection Register

Address Map......................................................................................................975

24-10 KT IO/Memory Mapped Device Register Address Map ..............................................981

38 Datasheet

Revision History

Revision Description Date

001 • Initial Release April 2012

®

C216 Chipset Family Platform Controller Hub (PCH)

®

7 Series / C216 Chipset Family SKU Definition

®

Q77, Q75 Express Chipsets

®

QS77, QM77 Express Chipsets

®

7 Series / C216 Chipset Family SKU Definition

002

003

•Added Intel

•Chapter 1
— Updated Section 1.3, Intel

•Chapter 5
— Updated Section 5.28.4, Multiple Display Configurations

•Chapter 10
— Updated Section 10.1.83, FDSW—Function Disable SUS Well Register

— Updated Section 10.1.100, CIR27—Chipset Initialization Register 27

• Added Desktop Intel

• Added Mobile Intel

• Updated Secdtion 1.3, Intel

•Added Section 6.3, Mobile SFF PCH Ballout

•Added Section 7.3, Mobile SFF PCH Package

May 2012

June 2012

Datasheet 39

Platform Controller Hub Features

 Direct Media Interface

— Up to 20 Gb/s each direction, full duplex
— Transparent to software

 PCI Express*

— Up to eight PCI Express root ports
— Supports PCI Express Rev 2.0 running at up

to 5.0 GT/s

— Ports 1–4 and 5–8 can independently be

configured to support eight x1s, two x4s,
two x2s and four x1s, or one x4 and four x1
port widths

— Module based Hot-Plug supported (that is,

ExpressCard*)

 Integrated Serial ATA Host Controller

—Up to six SATA ports
— Data transfer rates up to 6.0 Gb/s

(600 MB/s) on up to two ports

— Data transfer rates up to 3.0 Gb/s

(300 MB/s) and up to 1.5 Gb/s
(150 MB/s) on all ports

— Integrated AHCI controller

 External SATA support on all ports

— 3.0 Gb/s / 1.5 Gb/s support
— Port Disable Capability

 Intel

®

Rapid Storage Technology

— Configures the PCH SATA controller as a

RAID controller supporting RAID 0/1/5/10

 Intel
 Intel

®

Smart Response Technology

®

High Definition Audio Interface

— PCI Express endpoint
— Independent Bus Master logic for eight

general purpose streams: four input and

four output
— Support four external Codecs
— Supports variable length stream slots
— Supports multichannel, 32-bit sample

depth, 192 kHz sample rate output
— Provides mic array support
— Allows for non-48 kHz sampling output
— Support for ACPI Device States
—Low Voltage

 Eight TACH signals and Four PWM signals

(Server and Workstation Only)

 Platform Environmental Control Interface

(PECI) and Simple Serial Transport (SST) 1.0
Bus (Server and Workstation Only)

 USB

— NEW: xHCI Host Controller, supporting up

to 4 SuperSpeed USB 3.0 ports

— Two EHCI Host Controllers, supporting up

to fourteen external USB 2.0 ports
— Two USB 2.0 Rate Matching Hubs
— Per-Port-Disable Capability
— Includes up to two USB 2.0 High-speed

Debug Ports
— Supports wake-up from sleeping states S1–

S4
— Supports legacy Keyboard/Mouse software

 Integrated Gigabit LAN Controller

— Connection utilizes PCI Express pins
— Integrated ASF Management Controller
— Network security with System Defense
— Supports IEEE 802.3
— 10/100/1000 Mbps Ethernet Support
—Jumbo Frame Support

 Intel

®

Active Management Technology with

System Defense

— Network Outbreak Containment Heuristics

 Intel
 Intel
 Intel
 Power Management Logic

®

I/O Virtualization (Intel® VT-d) Support

®

Trusted Execution Technology Support

®

Anti-Theft Technology

— Supports ACPI 4.0a
— ACPI-defined power states (processor

driven C states)
— ACPI Power Management Timer
—SMI# generation
— All registers readable/restorable for proper

resume from 0 V core well suspend states
— Support for APM-based legacy power

management for non-ACPI

implementations

 Integrated Clock Controller

— Full featured platform clocking without

need for a discrete clock chip
— Ten PCIe 2.0 specification compliant clocks,

four 33 MHz PCI clocks, four Flex Clocks

that can be configured for various crystal

replacement frequencies, one 120 MHz

clock for embedded DisplayPort*
— Two isolated PCIe* 2.0 jitter specification

compliant clock domains

40 Datasheet

 External Glue Integration

— Integrated Pull-down and Series resistors

on USB

 Enhanced DMA Controller

— Two cascaded 8237 DMA controllers
— Supports LPC DMA

 PCI Bus Interface (not available on all SKUs)

— Supports PCI Rev 2.3 Specification at

33 MHz
— Four available PCI REQ/GNT pairs
— Support for 64-bit addressing on PCI using

DAC protocol

 SMBus

— Interface speeds of up to 100 kbps
— Flexible SMBus/SMLink architecture to

optimize for ASF
— Provides independent manageability bus

through SMLink interface
— Supports SMBus 2.0 Specification
— Host interface allows processor to

communicate using SMBus
— Slave interface allows an internal or

external microcontroller to access system

resources
— Compatible with most two-wire

components that are also I

 High Precision Event Timers

2

C compatible

— Advanced operating system interrupt

scheduling

 Timers Based on 8254

— System timer, Refresh request, Speaker

tone output

 Real-Time Clock

— 256 byte battery-backed CMOS RAM
— Integrated oscillator components
— Lower Power DC/DC Converter

implementation

 System TCO Reduction Circuits

— Timers to generate SMI# and Reset upon

detection of system hang
— Timers to detect improper processor reset
— Supports ability to disable external devices

 JTAG

 Serial Peripheral Interface (SPI)

— Supports up to two SPI devices
— Supports 20 MHz, 33 MHz, and 50 MHz SPI

devices

— Support up to two different erase

granularities

 Firmware Hub I/F supports BIOS Memory size

up to 8 MB

 Low Pin Count (LPC) I/F

— Supports two Master/DMA devices.
— Support for Security Device (Trusted

Platform Module) connected to LPC

 Interrupt Controller

— Supports up to eight PCI interrupt pins
— Supports PCI 2.3 Message Signaled

Interrupts
— Two cascaded 8259 with 15 interrupts
— Integrated I/O APIC capability with 24

interrupts
— Supports Processor System Bus interrupt

delivery

 1.05 V operation with 1.5/3.3 V I/O

— 5 V tolerant buffers on PCI, USB and

selected Legacy signals

 1.05 V Core Voltage
 Integrated Voltage Regulators for select power

rails

 GPIO

— Open-Drain, Inversion
— GPIO lock down

 Analog Display (VGA)
 Digital Display

— Three Digital Ports capable of supporting

HDMI/DVI, DisplayPort*, and embedded

DisplayPort (eDP*)
— One Digital Port supporting Intel
—LVDS
— Integrated DisplayPort/HDMI Audio
— HDCP Support

 Package

— 27 mm x 27 mm FCBGA (Desktop Only)
— 25 mm x 25 mm FCBGA (Mobile Only)
— 22 mm x 22 mm FCBGA (Mobile SFF Only)

— Boundary Scan for testing during board

manufacturing

Note: Not all features are available on all PCH SKUs. See Section 1.3 for more details.

®

SDVO

§ §

Datasheet 41

42 Datasheet

Introduction

1 Introduction

1.1 About This Manual

This document is intended for Original Equipment Manufacturers and BIOS vendors
creating Intel 7 Series/C216 Chipset Family based products (See Section 1.3 for
currently defined SKUs).

Note: Throughout this document, Platform Controller Hub (PCH) is used as a general term

and refers to all Intel 7 Series/C216 Chipset Family SKUs, unless specifically noted
otherwise.

Note: Throughout this document, the terms “Desktop” and “Desktop Only” refer to

information that is applicable only to the Intel
Express Chipset, Intel
Express Chipset, Intel

®

B75 Express Chipset, Intel® Z77 Express Chipset, Intel® Z75

®

H77 Express Chipset, and Intel® C216 Chipset, unless

®

Q77 Express Chipset, Intel® Q75

specifically noted otherwise.

Note: Throughout this document, the terms “Server/Workstation” and “Server/Workstation

Only” refers to information that is applicable only to the Intel

®

C216 Chipset, unless

specifically noted otherwise.

Note: Throughout this document, the terms “Mobile” and “Mobile Only” refer to information

that is applicable only to the Mobile Intel
Express Chipset, Mobile Intel
Chipset, Mobile Intel

®

Intel

QS77 Express Chipset,unless specifically noted otherwise.

®

HM75 Express Chipset, Intel® HM70 Express Chipset, and Mobile

®

HM77 Express Chipset, Mobile Intel® HM76 Express

Note: Throughout this document, the terms “Small Form Factor Only” and “SFF Only” refer to

information that is applicable only to the Mobile Intel

®

QM77 Express Chipset, Mobile Intel® UM77

®

QS77 Express Chipset, unless

specifically noted otherwise.

This manual assumes a working knowledge of the vocabulary and principles of PCI
Express*, USB, AHCI, SATA, Intel

®

High Definition Audio (Intel® HD Audio), SMBus,
PCI, ACPI and LPC. Although some details of these features are described within this
manual, refer to the individual industry specifications listed in Tab le 1- 1 for the
complete details.

All PCI buses, devices, and functions in this manual are abbreviated using the following
nomenclature; Bus:Device:Function. This manual abbreviates buses as Bn, devices as
Dn and functions as Fn. For example, Device 31 Function 0 is abbreviated as D31:F0,
Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will
not be used, and can be considered to be Bus 0. The PCH’s external PCI bus is typically
Bus 1, but may be assigned a different number depending upon system configuration.

Datasheet 43

Table 1-1. Industry Specifications

PCI Express* Base Specification, Revision 2.0

http://www.pcisig.com/specifications

Low Pin Count Interface Specification, Revision 1.1 (LPC)

http://developer.intel.com/design/chipsets/industry/lpc.htm

System Management Bus Specification, Version 2.0 (SMBus)

http://www.smbus.org/specs/

PCI Local Bus Specification, Revision 2.3 (PCI)

http://www.pcisig.com/specifications

PCI Power Management Specification, Revision 1.2

http://www.pcisig.com/specifications

Universal Serial Bus Specification (USB), Revision 2.0

http://www.usb.org/developers/docs

Advanced Configuration and Power Interface, Version 4.0a (ACPI)

http://www.acpi.info/spec.htm

Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 (EHCI)

http://developer.intel.com/technology/usb/ehcispec.htm

eXtensible Host Controller Interface for Universal Serial Bus (xHCI), Revision 1.0

http://www.intel.com/technology/usb/xhcispec.htm

Serial ATA Specification, Revision 3.0

http://www.serialata.org/

Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0

http://www.serialata.org

Serial ATA II Cables and Connectors Volume 2 Gold

http://www.serialata.org

Alert Standard Format Specification, Version 1.03

http://www.dmtf.org/standards/asf

IEEE 802.3 Fast Ethernet

http://standards.ieee.org/getieee802/

AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6)

http://T13.org (T13 1410D)

IA-PC HPET (High Precision Event Timers) Specification, Revision 1,0a

http://www.intel.com/hardwaredesign/hpetspec_1.pdf

TPM Specification 1.02, Level 2 Revision 103

http://www.trustedcomputinggroup.org/specs/TPM

®

Virtualization Technology

Intel

http://www.intel.com/technology/virtualization/index.htm

SFF-8485 Specification for Serial GPIO (SGPIO) Bus, Revision 0.7

http://www.intel.com/technology/virtualization/index.htm

Advanced Host Controller Interface specification for Serial ATA, Revision 1.3

http://www.intel.com/technology/serialata/ahci.htm

®

High Definition Audio Specification, Revision 1.0a

Intel

http://www.intel.com/standards/hdaudio/

Introduction

Specification / Location

44 Datasheet

Introduction

Chapter 1, “Introduction”

Chapter 1 introduces the PCH and provides information on manual organization and

gives a general overview of the PCH.

Chapter 2, “Signal Description”

Chapter 2 provides a block diagram of the PCH and a detailed description of each

signal. Signals are arranged according to interface and details are provided as to the
drive characteristics (Input/Output, Open Drain, and so on) of all signals.

Chapter 3, “PCH Pin States”

Chapter 3 provides a complete list of signals, their associated power well, their logic

level in each suspend state, and their logic level before and after reset.

Chapter 4, “PCH and System Clocks”

Chapter 4 provides a list of each clock domain associated with the PCH.

Chapter 5, “Functional Description”

Chapter 5 provides a detailed description of the functions in the PCH.

Chapter 6, “Ballout Definition”

Chapter 6 provides the ball assignment table and the ball-map for the Desktop, Mobile

and Mobile SFF packages.

Chapter 7, “Package Information”

Chapter 7 provides drawings of the physical dimensions and characteristics of the

Desktop, Mobile and Mobile SFF packages.

Chapter 8, “Electrical Characteristics”

Chapter 8 provides all AC and DC characteristics including detailed timing diagrams.

Chapter 9, “Register and Memory Mapping”

Chapter 9 provides an overview of the registers, fixed I/O ranges, variable I/O ranges

and memory ranges decoded by the PCH.

Chapter 10, “Chipset Configuration Registers”

Chapter 10 provides a detailed description of registers and base functionality that is

related to chipset configuration. It contains the root complex register block, which
describes the behavior of the upstream internal link.

Chapter 11, “PCI-to-PCI Bridge Registers (D30:F0)”

Chapter 11 provides a detailed description of registers that reside in the PCI-to-PCI

bridge. This bridge resides at Device 30, Function 0 (D30:F0).

Chapter 12, “Gigabit LAN Configuration Registers”

Chapter 12 provides a detailed description of registers that reside in the PCH’s

integrated LAN controller. The integrated LAN Controller resides at Device 25,
Function 0 (D25:F0).

Chapter 13, “LPC Interface Bridge Registers (D31:F0)”

Chapter 13 provides a detailed description of registers that reside in the LPC bridge.

This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers
for many different units within the PCH including DMA, Timers, Interrupts, Processor
Interface, GPIO, Power Management, System Management and RTC.

Chapter 14, “SATA Controller Registers (D31:F2)”

Chapter 14 provides a detailed description of registers that reside in the SATA

controller #1. This controller resides at Device 31, Function 2 (D31:F2).

Chapter 15, “SATA Controller Registers (D31:F5)”

Chapter 15 provides a detailed description of registers that reside in the SATA

controller #2. This controller resides at Device 31, Function 5 (D31:F5).

Chapter 16, “EHCI Controller Registers (D29:F0, D26:F0)”

Chapter 16 provides a detailed description of registers that reside in the two EHCI host

controllers. These controllers reside at Device 29, Function 0 (D29:F0) and Device 26,
Function 0 (D26:F0).

Datasheet 45

Introduction

Chapter 17, “xHCI Controller Registers (D20:F0)”

Chapter 17 provides a detailed description of registers that reside in the xHCI. This

controller resides at Device 20, Function 0 (D20:F0).

Chapter 18, “Integrated Intel® High Definition Audio Controller Registers”

Chapter 18 provides a detailed description of registers that reside in the Intel High

Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0).

Chapter 19, “SMBus Controller Registers (D31:F3)”

Chapter 19 provides a detailed description of registers that reside in the SMBus

controller. This controller resides at Device 31, Function 3 (D31:F3).

Chapter 20, “PCI Express* Configuration Registers”

Chapter 20 provides a detailed description of registers that reside in the PCI Express

controller. This controller resides at Device 28, Functions 0 to 7 (D28:F0–F7).

Chapter 21, “High Precision Event Timer Registers”

Chapter 21 provides a detailed description of registers that reside in the multimedia

timer memory mapped register space.

Chapter 22, “Serial Peripheral Interface (SPI)”

Chapter 22 provides a detailed description of registers that reside in the SPI memory

mapped register space.

Chapter 23, “Thermal Sensor Registers (D31:F6)”

Chapter 23 provides a detailed description of registers that reside in the thermal

sensors PCI configuration space. The registers reside at Device 31, Function 6
(D31:F6).

Chapter 24, “Intel® Management Engine Subsystem Registers (D22:F[3:0])”
Chapter 24 provides a detailed description of registers that reside in the Intel ME

controller. The registers reside at Device 22, Function 0 (D22:F0).

1.2 Overview

The PCH provides extensive I/O support. Functions and capabilities include:

• PCI Express* Base Specification, Revision 2.0 support for up to eight ports with
transfers up to 5 GT/s

• PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations

(supports up to four Req/Gnt pairs)

• ACPI Power Management Logic Support, Revision 4.0a

• Enhanced DMA controller, interrupt controller, and timer functions

• Integrated Serial ATA host controllers with independent DMA operation on up to six
ports

• USB host interface with two EHCI high-speed USB 2.0 Host controllers and two rate
matching hubs provide support for up to fourteen USB 2.0 ports and one xHCI
provides support for up to four SuperSpeed USB 3.0 ports.

• Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense

• System Management Bus (SMBus) Specification, Version 2.0 with additional
support for I

•Supports Intel® High Definition Audio (Intel® HD Audio)

•Supports Intel

•Supports Intel

•Supports Intel® Virtualization Technology for Directed I/O (Intel® VT-d)

•Supports Intel

• Integrated Clock Controller

2

C devices

®

Rapid Storage Technology (Intel® RST)

®

Active Management Technology (Intel® AMT)

®

Trusted Execution Technology (Intel® TXT)

46 Datasheet

Introduction

•Intel® Flexible Display Interconnect (Intel® FDI)

• Analog and digital display interfaces
—Analog VGA
—HDMI
—DVI
— DisplayPort* 1.1, Embedded DisplayPort
—Intel

®

SDVO

— LVDS (Mobile Only)

• Low Pin Count (LPC) interface

• Firmware Hub (FWH) interface support

• Serial Peripheral Interface (SPI) support

•Intel

®

Anti-Theft Technology (Intel® AT)

• JTAG Boundary Scan support

The PCH incorporates a variety of PCI devices and functions separated into logical
devices, as shown in Ta bl e 9- 1.

Note: Not all functions and capabilities may be available on all SKUs. Please see Section 1.3

for details on SKU feature availability.

1.2.1 Capability Overview

The following sub-sections provide an overview of the PCH capabilities.

Direct Media Interface (DMI)

Direct Media Interface (DMI) is the chip-to-chip connection between the processor and
PCH. This high-speed interface integrates advanced priority-based servicing allowing
for concurrent traffic and true isochronous transfer capabilities. Base functionality is
completely software-transparent, permitting current and legacy software to operate
normally.

Intel® Flexible Display Interconnect (FDI)

Intel® FDI connects the display engine in the processor with the display interfaces on
the PCH. The display data from the frame buffer is processed by the display engine and
sent to the PCH where it is transcoded and driven out on the panel. Intel FDI supports
three channels – A, B, and C for display data transfer.

Intel FDI Channel A has 4 lanes, Channel B supports 4 or 2 lanes depending on the
display configuration while Channel C supports 2 lanes. Each of the Intel FDI Channel
lanes uses differential signal supporting 2.7 Gb/s. In case of two display configurations
Intel FDI CH A maps to display pipe A while Intel CH B maps to the second display pipe
B. For three display configurations, Intel FDI CH A maps to display pipe A while Intel
FDI CH B divides into 2 channels - CH B and CH C of 2 lanes each, and Intel FDI CH B
and C maps to display pipes B and C to send the display data from the processor to the
ports.

PCH Display Interface

The PCH integrates the latest display technologies such as HDMI*, DisplayPort*,
Embedded DisplayPort (eDP*), Intel
technologies—Analog Port (VGA) and LVDS (mobile only). The Analog Port and LVDS
Port are dedicated ports on the PCH and the Digital Ports B, C, and D can be configured
to drive HDMI, DVI, or DisplayPort. Digital Port B can also be configured as Intel SDVO
while Digital Port D can be configured as eDP. The HDMI interface supports the HDMI*

1.4a specification while the DisplayPort interface supports the DisplayPort* 1.1a

Datasheet 47

®

SDVO, and DVI along with legacy display

Introduction

specification. The PCH supports High-bandwidth Digital Content Protection for high
definition content playback over digital interfaces. The PCH also integrates audio
codecs for audio support over HDMI and DisplayPort interfaces.

The PCH receives the display data over Intel FDI and transcodes the data as per the
display technology protocol and sends the data through the display interface.

The PCH enables three independent and concurrent display configurations because of
the addition of third display pipe into the display engine.

PCI Express* Interface

The PCH provides up to 8 PCI Express Root Ports, supporting the PCI Express Base
Specification, Revision 2.0. Each Root Port x1 lane supports up to 5 Gb/s bandwidth in

each direction (10 Gb/s concurrent). PCI Express Root Ports 1–4 or Ports 5–8 can
independently be configured to support four x1s, two x2s, one x2 and two x1s, or one
x4 port widths. See Section 1.3 for details on SKU feature availability.

Serial ATA (SATA) Controller

The PCH has two integrated SATA host controllers that support independent DMA
operation on up to six ports and supports data transfer rates of up to 6.0 Gb/s
(600 MB/s) on up to two ports while all ports support rates up to 3.0 Gb/s (300 MB/s)
and up to 1.5 Gb/s (150 MB/s). The SATA controller contains two modes of operation—
a legacy mode using I/O space, and an AHCI mode using memory space. Software that
uses legacy mode will not have AHCI capabilities.

The PCH supports the Serial ATA Specification, Revision 3.0. The PCH also supports
several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification,
Revision 1.0 (AHCI support is required for some elements). See Section 1.3 for details
on SKU feature availability.

AHCI

The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a
standardized programming interface for SATA host controllers. Platforms supporting
AHCI may take advantage of performance features such as no master/slave
designation for SATA devices—each device is treated as a master—and hardware­assisted native command queuing. AHCI also provides usability enhancements such as
Hot-Plug. AHCI requires appropriate software support (such as, an AHCI driver) and for
some features, hardware support in the SATA device or additional platform hardware.
See Section 1.3 for details on SKU feature availability.

Intel® Rapid Storage Technology

The PCH provides support for Intel Rapid Storage Technology, providing both AHCI (see
above for details on AHCI) and integrated RAID functionality. The RAID capability
provides high-performance RAID 0, 1, 5, and 10 functionality on up to 6 SATA ports of
the PCH. Matrix RAID support is provided to allow multiple RAID levels to be combined
on a single set of hard drives, such as RAID 0 and RAID 1 on two disks. Other RAID
features include hot spare support, SMART alerting, and RAID 0 auto replace. Software
components include an Option ROM for pre-boot configuration and boot functionality, a
Microsoft Windows* compatible driver, and a user interface for configuration and
management of the RAID capability of the PCH. See Section 1.3 for details on SKU
feature availability.

48 Datasheet

Introduction

Intel® Smart Response Technology

Intel® Smart Response Technology is a disk caching solution that can provide improved
computer system performance with improved power savings. It allows configuration of
a computer systems with the advantage of having HDDs for maximum storage capacity
with system performance at or near SSD performance levels. See Section 1.3 for
details on SKU feature availability.

PCI Interface

The PCH PCI interface provides a 33 MHz, Revision 2.3 implementation. The PCH
integrates a PCI arbiter that supports up to four external PCI bus masters in addition to
the internal PCH requests. This allows for combinations of up to four PCI down devices
and PCI slots. See Section 1.3 for details on SKU feature availability.

Low Pin Count (LPC) Interface

The PCH implements an LPC Interface as described in the LPC 1.1 Specification. The
Low Pin Count (LPC) bridge function of the PCH resides in PCI Device 31:Function 0. In
addition to the LPC bridge interface function, D31:F0 contains other functional units
including DMA, interrupt controllers, timers, power management, system management,
GPIO, and RTC.

Serial Peripheral Interface (SPI)

The PCH implements an SPI Interface as an alternative interface for the BIOS flash
device. An SPI flash device can be used as a replacement for the FWH, and is required
to support Gigabit Ethernet. The PCH supports up to two SPI flash devices with speeds
up to 50 MHz, using two chip select pins.

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)

The DMA controller incorporates the logic of two 8237 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by­byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any
two of the seven DMA channels can be programmed to support fast Type-F transfers.
Channel 4 is reserved as a generic bus master request.

The PCH supports LPC DMA, which is similar to ISA DMA, through the PCH’s DMA
controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals
and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and
Increment modes are supported on the LPC interface.

The timer/counter block contains three counters that are equivalent in function to those
found in one 8254 programmable interval timer. These three counters are combined to
provide the system timer function, and speaker tone. The 14.31818 MHz oscillator
input provides the clock source for these three counters.

The PCH provides an ISA-Compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two 8259 interrupt controllers. The two interrupt
controllers are cascaded so that 14 external and two internal interrupts are possible. In
addition, the PCH supports a serial interrupt scheme.

All of the registers in these modules can be read and restored. This is required to save
and restore system state after power has been removed and restored to the platform.

Datasheet 49

Introduction

Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA compatible Programmable Interrupt controller (PIC)
described in the previous section, the PCH incorporates the Advanced Programmable
Interrupt Controller (APIC).

Universal Serial Bus (USB) Controllers

The PCH contains up to two Enhanced Host Controller Interface (EHCI) host controllers
that support USB high-speed signaling. High-speed USB 2.0 allows data transfers up to
480 Mb/s, which is up to 40 times faster than full-speed USB. The PCH supports up to
fourteen USB 2.0 ports. All ports are high-speed, full-speed, and low-speed capable.
The PCH also contains an integrated eXtensible Host Controller Interface (xHCI) host
controller that supports up to four USB 3.0 ports. This controller allows data transfers
up to 5 Gb/s. The controller supports SuperSpeed (SS), high-speed (HS), full-speed
(FS), and low-speed (LS) traffic on the bus. See Section 1.3 for details on SKU feature
availability.

Gigabit Ethernet Controller

The Gigabit Ethernet Controller provides a system interface using a PCI function. The
controller provides a full memory-mapped or IO mapped interface along with a 64-bit
address master support for systems using more than 4 GB of physical memory and
DMA (Direct Memory Addressing) mechanisms for high performance data transfers. Its
bus master capabilities enable the component to process high-level commands and
perform multiple operations; this lowers processor utilization by off-loading
communication tasks from the processor. Two large configurable transmit and receive
FIFOs (up to 20 KB each) help prevent data underruns and overruns while waiting for
bus accesses. This enables the integrated LAN controller to transmit data with
minimum interframe spacing (IFS).

The LAN controller can operate at multiple speeds (10/100/1000 MB/s) and in either
full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the
IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a
proprietary collision reduction mechanism. See Section 5.3 for details.

RTC

The PCH contains a Motorola MC146818B-compatible real-time clock with 256 bytes of
battery-backed RAM. The real-time clock performs two key functions—keeping track of
the time of day and storing system data, even when the system is powered down. The
RTC operates on a 32.768 KHz crystal and a 3 V battery.

The RTC also supports two lockable memory ranges. By setting bits in the configuration
space, two 8-byte ranges can be locked to read and write accesses. This prevents
unauthorized reading of passwords or other system security information.

The RTC also supports a date alarm that allows for scheduling a wake up event up to
30 days in advance, rather than just 24 hours in advance.

GPIO

Various general purpose inputs and outputs are provided for custom system design.
The number of inputs and outputs vary depending on PCH configuration.

50 Datasheet

Introduction

Enhanced Power Management

The PCH’s power management functions include enhanced clock control and various
low-power (suspend) states (such as Suspend-to-RAM and Suspend-to-Disk). A
hardware-based thermal management circuit permits software-independent entrance
to low-power states. The PCH contains full support for the Advanced Configuration and
Power Interface (ACPI) Specification, Revision 4.0a.

Intel® Active Management Technology (Intel® AMT)

Intel AMT is a fundamental component of Intel® vPro™ technology. Intel AMT is a set of
advanced manageability features developed as a direct result of IT customer feedback
gained through Intel market research. With the advent of powerful tools like the Intel

®

System Defense Utility, the extensive feature set of Intel AMT easily integrates into any
network environment. See Section 1.3 for details on SKU feature availability.

Manageability

In addition to Intel AMT tThe PCH integrates several functions designed to manage the
system and lower the total cost of ownership (TCO) of the system. These system
management functions are designed to report errors, diagnose the system, and recover
from system lockups without the aid of an external microcontroller.

• TCO Timer. The PCH’s integrated programmable TCO timer is used to detect

system locks. The first expiration of the timer generates an SMI# that the system
can use to recover from a software lock. The second expiration of the timer causes
a system reset to recover from a hardware lock.

• Processor Present Indicator. The PCH looks for the processor to fetch the first

instruction after reset. If the processor does not fetch the first instruction, the PCH
will reboot the system.

• ECC Error Reporting. When detecting an ECC error, the host controller has the

ability to send one of several messages to the PCH. The host controller can instruct
the PCH to generate either an SMI#, NMI, SERR#, or TCO interrupt.

• Function Disable. The PCH provides the ability to disable the following integrated

functions: LAN, USB, LPC, Intel HD Audio, SATA, PCI Express, or SMBus. Once
disabled, these functions no longer decode I/O, memory, or PCI configuration
space. Also, no interrupts or power management events are generated from the
disabled functions.

• Intruder Detect. The PCH provides an input signal (INTRUDER#) that can be

attached to a switch that is activated by the system case being opened. The PCH
can be programmed to generate an SMI# or TCO interrupt due to an active
INTRUDER# signal.

Datasheet 51

System Management Bus (SMBus 2.0)

Introduction

The PCH contains an SMBus Host interface that allows the processor to communicate
with SMBus slaves. This interface is compatible with most I

2

C devices. Special I2C

commands are implemented.

The PCH’s SMBus host controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves). Also, the PCH supports slave
functionality, including the Host Notify protocol. Hence, the host controller supports
eight command protocols of the SMBus interface (see System Management Bus
(SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write
Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.

The PCH’s SMBus also implements hardware-based Packet Error Checking for data
robustness and the Address Resolution Protocol (ARP) to dynamically provide address
to all SMBus devices.

Intel® High Definition Audio Controller

The Intel® High Definition Audio Specification defines a digital interface that can be
used to attach different types of codecs, such as audio and modem codecs. The PCH
Intel® HD Audio controller supports up to 4 codecs. The link can operate at either 3.3 V
or 1.5 V.

With the support of multi-channel audio stream, 32-bit sample depth, and sample rate
up to 192 kHz, the Intel HD Audio controller provides audio quality that can deliver CE
levels of audio experience. On the input side, the PCH adds support for an array of
microphones.

Intel® Virtualization Technology for Directed I/O (Intel VT-d)

The PCH provides hardware support for implementation of Intel Virtualization
Technology with Directed I/O (Intel

®

VT-d). Intel VT-d Technology consists of
technology components that support the virtualization of platforms based on Intel
Architecture processors. Intel VT-d technology enables multiple operating systems and
applications to run in independent partitions. A partition behaves like a virtual machine
(VM) and provides isolation and protection across partitions. Each partition is allocated
its own subset of host physical memory.

JTAG Boundary-Scan

The PCH implements the industry standard JTAG interface and enables Boundary-Scan.
Boundary-Scan can be used to ensure device connectivity during the board
manufacturing process. The JTAG interface allows system manufacturers to improve
efficiency by using industry available tools to test the PCH on an assembled board.
Since JTAG is a serial interface, it eliminates the need to create probe points for every
pin in an XOR chain. This eases pin breakout and trace routing and simplifies the
interface between the system and a bed-of-nails tester.

Note: Contact your local Intel Field Sales Representative for additional information about

JTAG usage on the PCH.

®

52 Datasheet

Introduction

Integrated Clock Controller

The PCH contains a Fully Integrated Clock Controller (ICC) generating various platform
clocks from a 25 MHz crystal source. The ICC contains up to eight PLLs and four Spread
Modulators for generating various clocks suited to the platform needs. The ICC supplies
up to ten 100 MHz PCI Express 2.0 Specification compliant clocks, one 100 MHz BCLK/
DMI to the processor, one 120 MHz for embedded DisplayPort on the processor, four
33 MHz clocks for SIO/EC/LPC/TPM devices and four Flex Clocks that can be configured
to various frequencies that include 14.318 MHz, 27 MHz, 33 MHz and 24/48 MHz for
use with SIO, EC, LPC, and discrete Graphics devices.

SOL Function

This function supports redirection of keyboard and text screens to a terminal window
on a remote console. The keyboard and text redirection enables the control of the client
machine through the network without the need to be physically near that machine. Text
and keyboard redirection allows the remote machine to control and configure a client
system. The SOL function emulates a standard PCI device and redirects the data from
the serial port to the management console using the integrated LAN.

KVM

KVM provides enhanced capabilities to its predecessor – SOL. In addition to the
features set provided by SOL, KVM provides mouse and graphic redirection across the
integrated LAN. Unlike SOL, KVM does not appear as a host accessible PCI device but is
instead almost completely performed by Intel AMT Firmware with minimal BIOS
interaction. The KVM feature is only available with internal graphics.

IDE-R Function

The IDE-R function is an IDE Redirection interface that provides client connection to
management console ATA/ATAPI devices such as hard disk drives and optical disk
drives. A remote machine can setup a diagnostic SW or OS installation image and direct
the client to boot an IDE-R session. The IDE-R interface is the same as the IDE
interface although the device is not physically connected to the system and supports
the ATA/ATAPI-6 specification. IDE-R does not conflict with any other type of boot and
can instead be implemented as a boot device option. The Intel AMT solution will use
IDE-R when remote boot is required. The device attached through IDE-R is only visible
to software during a management boot session. During normal boot session, the IDE-R
controller does not appear as a PCI present device.

Datasheet 53

Introduction

1.3 Intel® 7 Series / C216 Chipset Family SKU Definition

Table 1-2. Desktop Intel® 7 Series Chipset Family SKUs

SKU Name

®

Intel

Feature Set

Q77

Express

Chipset

PCI Express* 2.0 Ports 888888

PCI Interface Yes Yes Yes N o

Tot a l n um be r of U SB p or t s 14 14 1 2

• USB 3.0 Capable Ports (SuperSpeed and all USB

2.0 speeds)

• USB 2.0 Only Ports 10 10 8 10 10 10

444444

Total number of SATA ports 6 6 6 6 6 6

• SATA Ports (6 Gb/s, 3 Gb/s, and 1.5 Gb/s) 2

•SATA Ports (3 Gb/s and 1.5 Gb/s only) 455444

5

HDMI/DVI/VGA/DisplayPort*/eDP* Yes Yes Yes Yes Yes Yes

Integrated Graphics Support Yes Yes Yes Yes Yes Yes

Intel® Wireless Display 3.0

9

Yes Yes Yes Yes Yes Yes

AHCI Yes Yes Yes Yes Yes Yes

Intel® Rapid
Storage Technology

RAID 0/1/5/10 Support Yes No No Yes Yes Yes

Intel® Smart Response
Tec h n ol o g y

Yes N o No Yes No Yes

Intel® Anti-Theft Technology Yes Yes Yes Yes Yes Yes

Intel® Active Management Technology 8.0 YesNoNoNoNoNo

Intel® Small Business Advantage Yes

Intel Rapid Start Technology

8

7

Yes Yes Yes Yes Yes Yes

ACPI S1 State Support Yes Yes Yes Yes Yes Yes

®

Intel

Q75

Express

Chipset

6

1

®

Intel

B75

Express

Chipset

4

6

1

®

Intel

Intel

Z77

Express

Chipset

Express

Chipset

3

14 14 14

5

2

Z75

No

5

2

®

3

Intel

Express

Chipset

H77

3

No

5

2

No YesNoNoNo

®

NOTES:

1. Contact your local Intel Field Sales Representative for currently available PCH SKUs.

2. Table above shows feature differences between the PCH SKUs. If a feature is not listed in

the table it is considered a Base feature that is included in all SKUs

3. PCI Legacy Mode may optionally be used allowing external PCI bus support through a

PCIe-to-PCI bridge. See Section 5.1.9 for more details.

4. USB ports 6 and 7 are disabled.

5. SATA 6 Gb/s support on port 0 and port 1. SATA ports 0 and 1 also support 3 Gb/s and

1.5 Gb/s.

6. SATA 6 Gb/s support on port 0 only. SATA port 0 also supports 3 Gb/s and 1.5 Gb/s.

7. Intel

8. Intel

9. Intel

®

Small Business Advantage with the Intel® Q77 Express Chipset requires an Intel®

Core™ vPro™ processor.

®

Rapid Start Technology requires an appropriate processor be installed in the

platform. See processor collaterals for further details.

®

Wireless Display 3.0 requires a platform with Intel® Core™ Processor with

®

Intel

HD Graphics.

54 Datasheet

Introduction

Table 1-3. Mobile Intel® 7 Series Chipset Family SKUs

SKU Name

Feature Set

Mobile

Intel

QM77
Express
Chipset

®

Mobile

Intel

UM77

Express

Chipset

PCI Express* 2.0 Ports 8 4

PCI Interface

5

No No No No No No No

Tot a l n um be r of U SB p or t s 14 10

• USB 3.0 Capable Ports (SuperSpeed
and all USB 2.0 speeds)

•USB 2.0 Only Ports 10610812610

444402

Total number of SATA ports 6 4

• SATA Ports (6 Gb/s, 3 Gb/s, 1.5 Gb/s) 2

•SATA Ports (3 Gb/s and 1.5 Gb/s only)4344434

11

1

3

10

12

®

6

Mobile

Intel

HM77

Express

Chipset

®

Mobile

®

Intel

HM76

Express

Chipset

Mobile

Intel

HM75

Express

Chipset

®

Express

Chipset

8884

14 12

7

12

7

6664106

11

2

11

2

11

2

Mobile

®

Intel

HM70

4

8

8

9

12

1

Mobile
Intel

QS77

Express

Chipset

14

2

®

8

4

11

HDMI/DVI/SDVO/DisplayPort*/eDP* Yes Yes Yes Yes Yes Yes Yes

VGA/LVDS Yes No Yes Yes Yes Ye s Yes

Integrated Graphics Support Yes Yes Yes Yes Yes Yes Yes

Intel® Wireless Display 3.0

Intel® Rapid
Storage
Tec h n ol o g y

AHCI Yes Yes Yes Yes Yes Yes Yes

RAID 0/1/5/10 Support Yes Yes Yes N o No No Yes

Intel® Smart Response
Technology

16

Yes Yes Yes Yes Yes No Yes

Yes Yes Yes No No No Yes

Intel® Anti-Theft Technology Yes Yes Yes Yes Yes No Yes

Intel® Active Management Technology

8.0

YesNoNoNoNoNoYes

Intel® Small Business Advantage Yes Yes

Intel® Rapid Start Technology

15

Yes Yes Yes Yes Yes Yes Yes

13

Yes

13

No No No Yes

13

13, 14

ACPI S1 State Support Yes Yes Yes Yes Yes Yes Yes

NOTES:

1. Contact your local Intel Field Sales Representative for currently available PCH SKUs.

2. Table above shows feature difference between the PCH SKUs. If a feature is not listed in
the table it is considered a Base feature that is included in all SKUs.

3. PCIe ports 5–8 are not disabled through hardware on this SKU. These ports must be
disabled by BIOS to achieve the specified SKU power targets.

4. PCIe ports 5–8 are disabled on this SKU.

5. PCI Legacy Mode may optionally be used allowing external PCI bus support through a
PCIe-to-PCI bridge. See Section 5.1.9 for more details.

6. USB ports 6,7,12 and 13 are disabled on 10 port SKUs.

7. USB ports 6 and 7 are disabled on 12 port SKUs.

8. USB ports 4, 5, 6,7,12 and 13 are disabled on 8 port SKUs.

9. USB 3.0 ports 3 and 4 are disabled on 2 SuperSpeed port-capable SKUs.

10. SATA ports 1 and 3 are disabled on 4 port SKUs.

11. SATA 6 Gb/s support on port 0 and port 1. SATA ports 0 and 1 also support 3 Gb/s and

1.5 Gb/s.

12. SATA 6 Gb/s support on port 0 only. SATA port 0 also supports 3 Gb/s and 1.5 Gb/s.

13. Available only with 5.0 MB Intel

14. Available only on systems with an Intel

15. Intel

16. Intel

®

Rapid Start Technology requires an appropriate processor be installed in the

platform. See processor collateral for further details.

®

Wireless Display 3.0 requires a platform with Intel® Core™ Processor with

®

Intel

HD Graphics.

®

ME FW Image.

®

Core™ vPro™ processor.

Datasheet 55

Table 1-4. Intel® C216 Chipset SKU

PCI Express* 2.0 Ports 8

PCI Interface Yes

Total number of USB ports 14

• USB 3.0 Capable Ports (SuperSpeed and all USB 2.0 speeds) 4

• USB 2.0 Only Ports 10

Total number of SATA Ports 6

• SATA Ports (6.0 Gb/s & 3.0 Gb/s & 1.5 Gb/s) 2

• SATA Ports (3.0 Gb/s & 1.5 Gb/s only) 4

HDMI*/DVI*/VGA/eDP*/DisplayPort* Yes

Integrated Graphics Support Yes

Intel® Wireless Display 3.0 No

Intel® Rapid Storage
Technology

Intel® Anti-Theft Technology Yes

Intel® Active Management Technology 8.0 Ye s

Intel® Small Business Advantage No

Intel® Rapid Start Technology4 Yes

ACPI S1 State Support No

AHCI Yes

RAID 0/1/5/10 Support Yes

Intel® Smart Response Technology Yes

Feature Set

Introduction

SKU Name

®

Intel

C216

Chipset

3

NOTES:

1. Contact your local Intel Field Sales Representative for currently available PCH SKUs.

2. Table above shows feature differences between the PCH SKUs. If a feature is not listed in
the table, it is considered a Base feature that is included in all SKUs.

3. SATA 6 Gb/s support on port 0 and port 1. SATA ports 0 and 1 also support 3 Gb/s and

1.5 Gb/s.

4. Intel

®

Rapid Start Technology requires an appropriate processor be installed in the

platform. See processor collaterals for further details.

§ §

56 Datasheet

Signal Description

2 Signal Description

This chapter provides a detailed description of each signal. The signals are arranged in
functional groups according to their associated interface.

The “#” symbol at the end of the signal name indicates that the active, or asserted
state occurs when the signal is at a low voltage level. When “#” is not present, the
signal is asserted when at the high voltage level.

The following notations are used to describe the signal type:

I Input Pin

O Output Pin

OD O Open Drain Output Pin.

I/OD Bi-directional Input/Open Drain Output Pin.

I/O Bi-directional Input/Output Pin.

CMOS CMOS buffers. 1.5 V tolerant.

COD CMOS Open Drain buffers. 3.3 V tolerant.

HVCMOS High Voltage CMOS buffers. 3.3 V tolerant.

A Analog reference or output.

The “Type” for each signal is indicative of the functional operating mode of the signal.
Unless otherwise noted in Section 3.2 or Section 3.3, a signal is considered to be in the
functional operating mode after RTCRST# deasserts for signals in the RTC well, after
RSMRST# deasserts for signals in the suspend well, after PWROK asserts for signals in
the core well, after DPWROK asserts for Signals in the Deep Sx well, after APWROK
asserts for Signals in the Active Sleep well.

Datasheet 57

Signal Description

AD[31:0]

C/BE[3:0]#

DEVSEL#

FRAME#

IRDY#
TRDY#
STOP#

PAR
PERR#
REQ0#

REQ1#/GPI O50
REQ2#/GPI O52
REQ3#/GPI O54

GNT0#

GNT1#/GPI O51
GNT2#/GPI O53
GNT3#/GPI O55

SERR#

PME#

CLKIN_PCILOOPBACK

PCIRST#

PLOCK#

PCI

Interface

Intel®Flexible

Display

Interface

Power

Mgnt .

Interrupt
Interface

PMSYNCH

RCIN#

A20GATE

THRMPTRIP#

PROCPWRGD

Processor

Interface

USB

SERIRQ

PIRQ[D:A]#

PIRQ[H:E]#/GPIO[5:2]

USB[13:0][P,N]
OC0#/GPI O59; OC1#/ GPIO40
OC2#/GPI O41; OC3#/ GPIO42

OC4#/GPI O43; OC5#/GP IO9

OC6#/GPI O10; OC7#/ GPIO14

USBRBIAS, USBRBIAS#

USB3[T,R][p,n][4:1]

RTCX1
RTCX2

CLKIN_DMI _[P, N];CLKI N_DMI2_ [P,N]

CLKIN_SAT A_[P, N]/CKSSCD _[P, N]

CLKIN_DOT9 6[P, N]

XTAL25_IN;REF1 4CLKIN

PCIECLKRQ0#/GPIO73;PCIECLKRQ1#/GPIO18

PCIECLKRQ2#/GPIO20/SMI#;PCIECLKRQ3#/GPIO25

PCIECLKRQ4#/GPIO26;PCIECLKRQ5#/GPIO44
PCIECLKRQ6#/GPIO45;PCIECLKRQ7#/GPIO46

PEG_A_CLKRQ# /GPIO47 ;PEG_B_CLK RQ#/GPIO5 6

XCLK_RCOMP

RTC

Cloc k
Inputs

Mis c.

Signals

INTVRMEN, DSWVRMEN

SPKR

SRTCRST#; RTCRST#

INIT3_3V#

TPn

GPIO35/NMI#

GPIO24/PROC_MISSING

General

Purpose

I/O

GPIO[72,57,32,28, 27,15,8]

PECI

Dir ect

Media

Interface

LPC /
FWH

Interface

SMBus

Interface

Intel

®

High

Definit ion

Audio

System

Mgnt .

LAD[3:0]/FWH[3:0]

LFRAME#/FWH4

LDRQ0#; LDRQ1#/GPIO23

Seri al ATA

Interface

PCI Expre ss*

Interface

SPI

SPI_CS0#; SPI _CS1#

SPI_MISO
SPI_MOSI

SPI_CLK

JTAG

Controller

Link

Fan

Speed

Control

Dig ital

Disp lay

Interface

Clock

Outputs

CLKOUT_DP_[ P,N]

CLKOUT_DMI_ [P,N]

XTAL25_OUT

CLKOUT_PEG_A_[P,N]; CLKOUT_PEG_B_[P,N]

CLKOUT_PCI E[7: 0]_[P ,N]

CLKOUT_IT PXDP_[P, N]

CLKOUT_PCI [4:0 ]
CLKOUTFLEX0/GPIO64;CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66;CLKOUTFLEX3/GPIO67

Analog
Disp lay

LVDS

FDI_RX[P,N][7:4]
FDI_RX[P,N[[3:0]
FDI_FSYNC[0:1];FDI_LSYNC[0:1];FDI_INIT

CL_CLK1 ; CL_DATA1
CL_RST1#

PET[p,n][8:1]
PER[p,n][8:1]

SATA[5:0]TX[P,N]
SATA[5:0]RX[P,N]
SATAICOMPO, SATA3COMPO
SATAICOMPI , SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP/GPI O21
SATA1GP/GPI O19
SATA2GP/GPI O36
SATA3GP/GPI O37
SATA4GP/GPI O16
SATA5GP/GPIO49/TEMP_ALERT#
SCLOCK/GPIO22, SLOAD/GPIO38
SDATAOUT0/GPIO39, SDATAOUT1/GPI O48

SUSWARN#/SUSPWRDNACK /GPIO30
DPWROK
SYS_RESET#
RSMRST#
SLP_S3#
SLP_S4#
SLP_S5#/ GPIO63
SLP_A#
CLKRUN#/GPI O32
PWROK
AWROK
PWRBTN#
RI#
WAKE#
SUS_STAT#/ GPIO61
SUSCLK/GPI O62
BATLOW#/GPI O72
PLTRST#
BMBUSY#/GPI O0
STP_PCI# /GPIO3 4
ACPRESENT/GPI O31
DRAMPWROK
LAN_PHY_PWR_CTRL/GPIO12
SLP_LAN#/ GPIO29
SUSACK#

HDA_RST#
HDA_SYNC
HDA_BCLK
HDA_SDO
HDA_SDIN[3:0]
HDA_DOCK_EN#; HDA_DOCK_RST #

DMI[3:0]TX[P,N]
DMI[3:0]RX[P,N]
DMI_ZCOMP
DMI_IRCOMP

SMBDATA; SMBCLK
SMBALERT#/GPIO11

INTRUDER#;
SML[1:0]DATA;SML[1:0]CLK
SML0ALERT#/GPIO60
SML1ALERT#/PC HHOT#/GPIO74

CRT_RED;CRT_GREEN;CRT_ BLUE
DAC_IREF
CRT_HSYNC;CRT_VSYNC
CRT_DDC_CLK;CRT_DDC_DA TA
CRT_IRTN

LVDS[A:B]_DATA[3:0]
LVDS[A:B]_DATA#[3:0]
LVDS[A:B]_CLK;LVDS[A:B]_CLK#
LVD_VREFH;LVD_VREFL; LVD_VBG
LVD_IBG
L_DDC_CLK;L_ DDC_DATA
L_VDDEN;L_BLKTEN;L_BKLTCTL

DDPB_[3:0 ][P,N]
DDPC_[3:0][P,N]
DDPD_[3:0][P,N]
DDP[B: D]_AUX[ P,N]
DDP[B:D] _HPD
SDVO_CTRLCLK;SDVO_CTRL DATA
DDPC_CTRLCLK;DDPC_CTRLDATA
DDPD_CTRLCLK;DDPD_CTRLDATA
SDVO_INT[P, N]
SDVO_TVCLKIN[P,N]
SDVO_STALL[P,N]

JTAGTCK
JTAGTMS
JTAGTDI
JTAGTDO

Figure 2-1. PCH Interface Signals Block Diagram (not all signals are on all SKUs)

58 Datasheet

Signal Description

2.1 Direct Media Interface (DMI) to Host Controller

Table 2-1. Direct Media Interface Signals

Name Type Description

DMI0TXP,
DMI0TXN

DMI0RXP,
DMI0RXN

DMI1TXP,
DMI1TXN

DMI1RXP,
DMI1RXN

DMI2TXP,
DMI2TXN

DMI2RXP,
DMI2RXN

DMI3TXP,
DMI3TXN

DMI3RXP,
DMI3RXN

DMI_ZCOMP I

DMI_IRCOMP O

DMI2RBIAS I/O

O Direct Media Interface Differential Transmit Pair 0

I Direct Media Interface Differential Receive Pair 0

O Direct Media Interface Differential Transmit Pair 1

I Direct Media Interface Differential Receive Pair 1

O Direct Media Interface Differential Transmit Pair 2

I Direct Media Interface Differential Receive Pair 2

O Direct Media Interface Differential Transmit Pair 3

I Direct Media Interface Differential Receive Pair 3

Impedance Compensation Input: Determines DMI input
impedance.

Impedance/Current Compensation Output: Determines DMI
output impedance and bias current.

DMI2RBIAS: Analog connection point for 750 Ω ±1% external
precision resistor.

2.2 PCI Express*

Table 2-2. PCI Express* Signals

Name Type Description

PETp1, PETn1 O PCI Express* Differential Transmit Pair 1

PERp1, PERn1 I PCI Express Differential Receive Pair 1

PETp2, PETn2 O PCI Express Differential Transmit Pair 2

PERp2, PERn2 I PCI Express Differential Receive Pair 2

PETp3, PETn3 O PCI Express Differential Transmit Pair 3

PERp3, PERn3 I PCI Express Differential Receive Pair 3

PETp4, PETn4 O PCI Express Differential Transmit Pair 4

PERp4, PERn4 I PCI Express Differential Receive Pair 4

PETp5, PETn5 O PCI Express Differential Transmit Pair 5

PERp5, PERn5 I PCI Express Differential Receive Pair 5

PETp6, PETn6 O PCI Express Differential Transmit Pair 6

PERp6, PERn6 I PCI Express Differential Receive Pair 6

PETp7, PETn7 O PCI Express Differential Transmit Pair 7

PERp7, PERn7 I PCI Express Differential Receive Pair 7

PETp8, PETn8 O PCI Express Differential Transmit Pair 8

PERp8, PERn8 I PCI Express Differential Receive Pair 8

Datasheet 59

Signal Description

C/BE[3:0]# Command Type

0000b Interrupt Acknowledge
0001b Special Cycle
0010b I/O Read
0011b I/O Write
0110b Memory Read
0111b Memory Write
1010b Configuration Read
1011b Configuration Write
1100b Memory Read Multiple
1110b Memory Read Line
1111b Memory Write and Invalidate

2.3 PCI Interface

Note: The PCI Interface is only available on PCI Interface-enabled SKUs. However, certain PCI

Interface signal functionality is available even on PCI Interface-disabled SKUs, as
described below (see Section 1.3 for full details on SKU definition).

Table 2-3. PCI Interface Signals (Sheet 1 of 3)

Functionality

Name Type Description

PCI Address/Data: AD[31:0] is a multiplexed address and

data bus. During the first clock of a transaction, AD[31:0]

AD[31:0] I/O

contain a physical address (32 bits). During subsequent
clocks, AD[31:0] contain data. The PCH will drive all 0s on
AD[31:0] during the address phase of all PCI Special Cycles.

Bus Command and Byte Enables: The command and
byte enable signals are multiplexed on the same PCI pins.
During the address phase of a transaction, C/BE[3:0]#
define the bus command. During the data phase C/
BE[3:0]# define the Byte Enables.

Available on

PCI Interface-

disabled SKUs

No

C/

BE[3:0]#

DEVSEL# I/O

60 Datasheet

FRAME# I/O

I/O

All command encodings not shown are reserved. The PCH
does not decode reserved values, and therefore will not
respond if a PCI master generates a cycle using one of the
reserved values.

Device Select: The PCH asserts DEVSEL# to claim a PCI
transaction. As an output, the PCH asserts DEVSEL# when a
PCI master peripheral attempts an access to an internal PCH
address or an address destined for DMI (main memory or
graphics). As an input, DEVSEL# indicates the response to
an PCH-initiated transaction on the PCI bus. DEVSEL# is tri­stated from the leading edge of PLTRST#. DEVSEL# remains
tri-stated by the PCH until driven by a target device.

Cycle Frame: The current initiator drives FRAME# to
indicate the beginning and duration of a PCI transaction.
While the initiator asserts FRAME#, data transfers continue.
When the initiator negates FRAME#, the transaction is in the
final data phase. FRAME# is an input to the PCH when the
PCH is the target, and FRAME# is an output from the PCH
when the PCH is the initiator. FRAME# remains tri-stated by
the PCH until driven by an initiator.

No

No

No

Signal Description

Table 2-3. PCI Interface Signals (Sheet 2 of 3)

Name Type Description

Initiator Ready: IRDY# indicates the PCH's ability, as an

initiator, to complete the current data phase of the
transaction. It is used in conjunction with TRDY#. A data
phase is completed on any clock both IRDY# and TRDY# are

IRDY# I/O

TRDY# I/O

STOP# I/O

PAR I/O

PERR# I/O

sampled asserted. During a write, IRDY# indicates the PCH
has valid data present on AD[31:0]. During a read, it
indicates the PCH is prepared to latch data. IRDY# is an
input to the PCH when the PCH is the target and an output
from the PCH when the PCH is an initiator. IRDY# remains
tri-stated by the PCH until driven by an initiator.

Target Ready: TRDY# indicates the PCH's ability as a
target to complete the current data phase of the
transaction. TRDY# is used in conjunction with IRDY#. A
data phase is completed when both TRDY# and IRDY# are
sampled asserted. During a read, TRDY# indicates that the
PCH, as a target, has placed valid data on AD[31:0]. During
a write, TRDY# indicates the PCH, as a target is prepared to
latch data. TRDY# is an input to the PCH when the PCH is
the initiator and an output from the PCH when the PCH is a
target. TRDY# is tri-stated from the leading edge of
PLTRST#. TRDY# remains tri-stated by the PCH until driven
by a target.

Stop: STOP# indicates that the PCH, as a target, is
requesting the initiator to stop the current transaction.
STOP# causes the PCH, as an initiator, to stop the current
transaction. STOP# is an output when the PCH is a target
and an input when the PCH is an initiator.

Calculated/Checked Parity: PAR uses “even” parity
calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. “Even”
parity means that the PCH counts the number of ones within
the 36 bits plus PAR and the sum is always even. The PCH
always calculates PAR on 36 bits regardless of the valid byte
enables. The PCH generates PAR for address and data
phases and only ensures PAR to be valid one PCI clock after
the corresponding address or data phase. The PCH drives
and tri-states PAR identically to the AD[31:0] lines except
that the PCH delays PAR by exactly one PCI clock. PAR is an
output during the address phase (delayed one clock) for all
PCH initiated transactions. PAR is an output during the data
phase (delayed one clock) when the PCH is the initiator of a
PCI write transaction, and when it is the target of a read
transaction. PCH checks parity when it is the target of a PCI
write transaction. If a parity error is detected, the PCH will
set the appropriate internal status bits, and has the option
to generate an NMI# or SMI#.

Parity Error: An external PCI device drives PERR# when it
receives data that has a parity error. The PCH drives PERR#
when it detects a parity error. The PCH can either generate
an NMI# or SMI# upon detecting a parity error (either
detected internally or reported using the PERR# signal).

Functionality

Available on
PCI Interface­disabled SKUs

No

No

No

No

No

Datasheet 61

Table 2-3. PCI Interface Signals (Sheet 3 of 3)

Name Type Description

PCI Requests: The PCH supports up to 4 masters on the

REQ0#

REQ1#/

GPIO50

REQ2#/

GPIO52

REQ3#/

GPIO54

GNT0#

GNT1#/

GPIO51

GNT2#/

GPIO53

GNT3#/

GPIO55

CLKIN_PCI
LOOPBACK

PCIRST# O

PLOCK# I/O

SERR# I/OD

PME# I/OD

PCI bus.
REQ[3:1]# pins can instead be used as GPIO.

NOTES:

I

1. External pull-up resistor is required. When used as
native functionality, the pull-up resistor may be to
either 3.3 V or 5.0 V per PCI specification. When used
as GPIO or not used at all, the pull-up resistor should
be to the Vcc3_3 rail.

PCI Grants: The PCH supports up to 4 masters on the PCI
bus.

GNT[3:1]# pins can instead be used as GPIO.
Pull-up resistors are not required on these signals. If pull-

O

ups are used, they should be tied to the Vcc3_3 power rail.

NOTES:

1. GNT[3:1]#/GPIO[55,53,51] are sampled as a
functional strap. See Section 2.27 for details.

PCI Clock: This is a 33 MHz clock feedback input to reduce
skew between PCH PCI clock and clock observed by

I

connected PCI devices. This signal must be connected to
one of the pins in the group CLKOUT_PCI[4:0]

PCI Reset: This is the Secondary PCI Bus reset signal. It is
a logical OR of the primary interface PLTRST# signal and the
state of the Secondary Bus Reset bit of the Bridge Control
register (D30:F0:3Eh, bit 6).

PCI Lock: This signal indicates an exclusive bus operation
and may require multiple transactions to complete. PCH
asserts PLOCK# when it performs non-exclusive
transactions on the PCI bus. PLOCK# is ignored when PCI
masters are granted the bus.

System Error: SERR# can be pulsed active by any PCI
device that detects a system error condition. Upon sampling
SERR# active, the PCH has the ability to generate an NMI,
SMI#, or interrupt.

PCI Power Management Event: PCI peripherals drive
PME# to wake the system from low-power states S1–S5.
PME# assertion can also be enabled to generate an SCI
from the S0 state. In some cases the PCH may drive PME#
active due to an internal wake event. The PCH will not drive
PME# high, but it will be pulled up to VccSus3_3 by an
internal pull-up resistor.

On SKUs that do not have native PCI functionality, PME# is
still functional and can be used with PCI legacy mode on
platforms using a PCIe-to-PCI bridge. Downstream PCI
devices would need to have PME# routed from the
connector to the PCH PME# pin.

Signal Description

Functionality

Available on

PCI Interface-

disabled SKUs

No

(GPIO only)

No

(GPIO and strap

only)

Yes

No

No

No

Yes

62 Datasheet

Signal Description

2.4 Serial ATA Interface

Table 2-4. Serial ATA Interface Signals (Sheet 1 of 3)

Name Type Description

Serial ATA 0 Differential Transmit Pairs: These are outbound

SATA0TXP

SATA0TXN

SATA0RXP

SATA0RXN

SATA1TXP

SATA1TXN

SATA1RXP

SATA1RXN

SATA2TXP

SATA2TXN

high-speed differential signals to Port 0.

O

In compatible mode, SATA Port 0 is the primary master of SATA
Controller 1.

Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s.

Serial ATA 0 Differential Receive Pair: These are inbound high­speed differential signals from Port 0.

I

In compatible mode, SATA Port 0 is the primary master of SATA
Controller 1.

Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s.

Serial ATA 1 Differential Transmit Pair: These are outbound
high-speed differential signals to Port 1.

O

In compatible mode, SATA Port 1 is the secondary master of SATA
Controller 1.

Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s.

Serial ATA 1 Differential Receive Pair: These are inbound high­speed differential signals from Port 1.

I

In compatible mode, SATA Port 1 is the secondary master of SATA
Controller 1.

Supports up to 6 Gb/s, 3 Gb/s, and 1.5 Gb/s.

Serial ATA 2 Differential Transmit Pair: These are outbound
high-speed differential signals to Port 2.

In compatible mode, SATA Port 2 is the primary slave of SATA
Controller 1.

O

Supports up to 3 Gb/s and 1.5 Gb/s.

NOTE: SATA Port 2 may not be available in all PCH SKUs.

Serial ATA 2 Differential Receive Pair: These are inbound high-

speed differential signals from Port 2.

SATA2RXP

SATA2RXN

SATA3TXP

SATA3TXN

Datasheet 63

In compatible mode, SATA Port 2 is the primary slave of SATA
Controller 1

I

Supports up to 3 Gb/s and 1.5 Gb/s.

NOTE: SATA Port 2 may not be available in all PCH SKUs.

Serial ATA 3 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 3
In compatible mode, SATA Port 3 is the secondary slave of SATA

Controller 1

O

Supports up to 3 Gb/s and 1.5 Gb/s.

NOTE: SATA Port 3 may not be available in all PCH SKUs.

Table 2-4. Serial ATA Interface Signals (Sheet 2 of 3)

Name Type Description

Serial ATA 3 Differential Receive Pair: These are inbound high-

speed differential signals from Port 3.

SATA3RXP
SATA3RXN

SATA4TXP

SATA4TXN

SATA4RXP
SATA4RXN

SATA5TXP

SATA5TXN

SATA5RXP
SATA5RXN

SATAICOMPO O

SATAICOMPI I

SATA0GP /

GPIO21

SATA1GP /

GPIO19

SATA2GP /

GPIO36

In compatible mode, SATA Port 3 is the secondary slave of SATA
Controller 1

I

Supports up to 3 Gb/s and 1.5 Gb/s.

NOTE: SATA Port 3 may not be available in all PCH SKUs.

Serial ATA 4 Differential Transmit Pair: These are outbound

high-speed differential signals to Port 4.

O

In compatible mode, SATA Port 4 is the primary master of SATA
Controller 2.

Supports up to 3 Gb/s and 1.5 Gb/s.

Serial ATA 4 Differential Receive Pair: These are inbound high­speed differential signals from Port 4.

I

In compatible mode, SATA Port 4 is the primary master of SATA
Controller 2.

Supports up to 3 Gb/s and 1.5 Gb/s.

Serial ATA 5 Differential Transmit Pair: These are outbound
high-speed differential signals to Port 5.

O

In compatible mode, SATA Port 5 is the secondary master of SATA
Controller 2.

Supports up to 3 Gb/s and 1.5 Gb/s.

Serial ATA 5 Differential Receive Pair: These are inbound high­speed differential signals from Port 5.

I

In compatible mode, SATA Port 5 is the secondary master of SATA
Controller 2.

Supports up to 3 Gb/s and 1.5 Gb/s.

Serial ATA Compensation Output: Connected to an external
precision resistor to VccCore. Must be connected to SATAICOMPI
on the board.

Serial ATA Compensation Input: Connected to SATAICOMPO on
the board.

Serial ATA 0 General Purpose: This is an input pin which can be
configured as an interlock switch corresponding to SATA Port 0.
When used as an interlock switch status indication, this signal
should be drive to ‘0’ to indicate that the switch is closed and to ‘1’

I

to indicate that the switch is open.
If interlock switches are not required, this pin can be configured as

GPIO21.

Serial ATA 1 General Purpose: Same function as SATA0GP,
except for SATA Port 1.

I

If interlock switches are not required, this pin can be configured as
GPIO19.

Serial ATA 2 General Purpose: Same function as SATA0GP,
except for SATA Port 2.

I

If interlock switches are not required, this pin can be configured as
GPIO36.

Signal Description

64 Datasheet

Signal Description

Table 2-4. Serial ATA Interface Signals (Sheet 3 of 3)

Name Type Description

Serial ATA 3 General Purpose: Same function as SATA0GP,

SATA3GP /

GPIO37

SATA4GP /

GPIO16 /

SATA5GP /

GPIO49 /

TEMP_ALERT#

SATALED# OD O

SCLOCK/

GPIO22

SLOAD/GPIO38 OD O

SDATAOUT0/

GPIO39

SDATAOUT1/

GPIO48

SATA3RBIAS I/O

SATA3COMPI I

SATA3RCOMPO O

OD O

OD O

except for SATA Port 3.

I

If interlock switches are not required, this pin can be configured as
GPIO37.

Serial ATA 4 General Purpose: Same function as SATA0GP,
except for SATA Port 4.

I

If interlock switches are not required, this pin can be configured as
GPIO16.

Serial ATA 5 General Purpose: Same function as SATA0GP,
except for SATA Port 5.

I

If interlock switches are not required, this pin can be configured as
GPIO49 or TEMP_ALERT#.

Serial ATA LED: This signal is an open-drain output pin driven
during SATA command activity. It is to be connected to external
circuitry that can provide the current to drive a platform LED. When
active, the LED is on. When tri-stated, the LED is off. An external
pull-up resistor to Vcc3_3 is required.

SGPIO Reference Clock: The SATA controller uses rising edges of
this clock to transmit serial data, and the target uses the falling
edge of this clock to latch data. The SClock frequency supported is
32 kHz.

If SGPIO interface is not used, this signal can be used as GPIO22.

SGPIO Load: The controller drives a ‘1’ at the rising edge of
SCLOCK to indicate either the start or end of a bit stream. A 4-bit
vendor specific pattern will be transmitted right after the signal
assertion.

If SGPIO interface is not used, this signal can be used as GPIO38.

SGPIO Dataout: Driven by the controller to indicate the drive
status in the following sequence: drive 0, 1, 2, 3, 4, 5, 0, 1, 2...

If SGPIO interface is not used, the signals can be used as GPIO.

SATA3 RBIAS: Analog connection point for a 750 Ω ±1% external
precision resistor.

Impedance Compensation Input: Connected to a 50 Ω (1%)
precision external pull-up resistor to VccIO.

Impedance/Current Compensation Output: Connected to a
50 Ω (1%) precision external pull-up resistor to VccIO

Datasheet 65

2.5 LPC Interface

Table 2-5. LPC Interface Signals

Name Type Description

LAD[3:0] I/O

LFRAME# O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.

LDRQ0#,

LDRQ1# /

GPIO23

LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull­ups are provided.

LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to
request DMA or bus master access. These signals are typically connected
to an external Super I/O device. An internal pull-up resistor is provided on

I

these signals.
LDRQ1# may optionally be used as GPIO23.

2.6 Interrupt Interface

Table 2-6. Interrupt Signals

Name Type Description

SERIRQ I/OD

PIRQ[D:A]# I/OD

PIRQ[H:E]# /

GPIO[5:2]

I/OD

Serial Interrupt Request: This pin implements the serial interrupt
protocol.

PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can
be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in Section 5.8.6. Each PIRQx# line has a separate Route
Control register.

In APIC mode, these signals are connected to the internal I/O APIC in
the following fashion: PIRQA# is connected to IRQ16, PIRQB# to
IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the
legacy interrupts.

These signals are 5 V tolerant.

PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can
be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in Section 5.8.6. Each PIRQx# line has a separate Route
Control register.

In APIC mode, these signals are connected to the internal I/O APIC in
the following fashion: PIRQE# is connected to IRQ20, PIRQF# to
IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the
legacy interrupts. If not needed for interrupts, these signals can be
used as GPIO.

These signals are 5 V tolerant.

Signal Description

NOTE: PIRQ Interrupts can only be shared if it is configured as level sensitive. They cannot be

shared if configured as edge triggered.

66 Datasheet

Signal Description

2.7 USB Interface

Table 2-7. USB Interface Signals (Sheet 1 of 2)

Name Type Description

Universal Serial Bus Port [1:0] Differential: These differential pairs

USBP0P,

USBP0N,

USBP1P,
USBP1N

USBP2P,

USBP2N,

USBP3P,
USBP3N

USBP4P,

USBP4N,

USBP5P,
USBP5N

USBP6P,

USBP6N,

USBP7P,
USBP7N

USBP8P,

USBP8N,

USBP9P,
USBP9N

USBP10P,

USBP10N,

USBP11P,
USBP11N

USBP12P,

USBP12N,

USBP13P,
USBP13N

are used to transmit Data/Address/Command signals for ports 0 and 1.
These ports can be routed to EHCI Controller 1.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [3:2] Differential: These differential pairs
are used to transmit data/address/command signals for ports 2 and 3.
These ports can be routed to EHCI Controller 1.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [5:4] Differential: These differential pairs
are used to transmit Data/Address/Command signals for ports 4 and 5.
These ports can be routed to EHCI Controller 1.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [7:6] Differential: These differential pairs
are used to transmit Data/Address/Command signals for ports 6 and 7.
These ports can be routed to EHCI Controller 1.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [9:8] Differential: These differential pairs
are used to transmit Data/Address/Command signals for ports 8 and 9.
These ports can be routed to EHCI Controller 2.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [11:10] Differential: These differential
pairs are used to transmit Data/Address/Command signals for ports 10
and 11. These ports can be routed to EHCI Controller 2.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Universal Serial Bus Port [13:12] Differential: These differential
pairs are used to transmit Data/Address/Command signals for ports 13
and 12. These ports can be routed to EHCI Controller 2.

I/O

NOTE: No external resistors are required on these signals. The PCH

integrates 15 kΩ pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.

Datasheet 67

Table 2-7. USB Interface Signals (Sheet 2 of 2)

Name Type Description

USB3Tp4,

USB3Tn4

USB3Rp4,

USB3Rn4

USB3Tp3,

USB3Tn3

USB3Rp3,

USB3Rn3

USB3Tp2,

USB3Tn2

USB3Rp2,

USB3Rn2

USB3Tp1,

USB3Tn1

USB3Rp1,

USB3Rn1

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43

OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

USBRBIAS O

USBRBIAS# I

USB 3.0 Differential Transmit Pair 4

O

These are outbound SuperSpeed differential signals to USB 3.0 Port 4.

USB 3.0 Differential Receive Pair 4

I

These are inbound SuperSpeed differential signals from USB 3.0 Port 4.

USB 3.0 Differential Transmit Pair 3

O

These are outbound SuperSpeed differential signals to USB 3.0 Port 3.

USB 3.0 Differential Receive Pair 3

I

These are inbound SuperSpeed differential signals from USB 3.0 Port 3.

USB 3.0 Differential Transmit Pair 2

O

These are outbound SuperSpeed differential signals to USB 3.0 Port 2.

USB 3.0 Differential Receive Pair 2

I

These are inbound SuperSpeed differential signals from USB 3.0 Port 2.

USB 3.0 Differential Transmit Pair 1

O

These are outbound SuperSpeed differential signals to USB 3.0 Port 1.

USB 3.0 Differential Receive Pair 1

I

These are inbound SuperSpeed differential signals from USB 3.0 Port 1.

Overcurrent Indicators: These signals set corresponding bits in the
USB controllers to indicate that an overcurrent condition has occurred.

OC[7:0]# may optionally be used as GPIOs.

NOTES:

I

1. OC# pins are not 5 V tolerant.

2. Depending on platform configuration, sharing of OC# pins may be
required.

3. OC[3:0]# can only be used for EHCI Controller 1

4. OC[4:7]# can only be used for EHCI Controller 2

USB Resistor Bias: Analog connection point for an external resistor.
Used to set transmit currents and internal load resistors.

USB Resistor Bias Complement: Analog connection point for an
external resistor. Used to set transmit currents and internal load
resistors.

Signal Description

68 Datasheet

Signal Description

2.8 Power Management Interface

Table 2-8. Power Management Interface Signals (Sheet 1 of 4)

Name Type Description

ACPRESENT: This input pin indicates when the platform is plugged

into AC power or not. In addition to the previous Intel

ACPRESENT

(Mobile Only)

/ GPIO31

APWROK I

BATLOW#

(Mobile Only)

/ GPIO72

BMBUSY#

/ GPIO0

CLKRUN#

(Mobile Only)

/ GPIO32

(Desktop Only)

DPWROK I

DRAMPWROK OD O

LAN_PHY_PW

R_CTRL /

GPIO12

PLTRST# O

communication, the PCH uses this information to implement the Deep
Sx policies. For example, the platform may be configured to enter

I

Deep Sx when in S3, S4, or S5 and only when running on battery. This
is powered by Deep Sx Well.

This signal is muxed with GPIO31.

Active Sleep Well (ASW) Power OK: When asserted, indicates that
power to the ASW sub-system is stable.

Battery Low: An input from the battery to indicate that there is
insufficient power to boot the system. Assertion will prevent wake
from S3–S5 state. This signal can also be enabled to cause an SMI#

I

when asserted.

NOTE: See Tab l e 2 . 24 for Desktop implementation pin requirements.

Bus Master Busy: Generic bus master activity indication driven into

the PCH. Can be configured to set the PM1_STS.BM_STS bit. Can also

I

be configured to assert indications transmitted from the PCH to the
processor using the PMSYNCH pin.

PCI Clock Run: Used to support PCI CLKRUN protocol. Connects to

I/O

peripherals that need to request clock restart or prevention of clock
stopping.

DPWROK: Power OK Indication for the VccDSW3_3 voltage rail. This
input is tied together with RSMRST# on platforms that do not support
Deep Sx.

This signal is in the RTC well.

DRAM Power OK: This signal should connect to the processor’s
SM_DRAMPWROK pin. The PCH asserts this pin to indicate when DRAM
power is stable.

This pin requires an external pull-up resistor.

LAN PHY Power Control: LAN_PHY_PWR_CTRL should be connected
to LAN_DISABLE_N on the PHY. PCH will drive LAN_PHY_PWR_CTRL
low to put the PHY into a low power state when functionality is not
needed.

O

NOTES:

1. LAN_PHY_PWR_CTRL can only be driven low if SLP_LAN# is
deasserted.

2. Signal can instead be used as GPIO12.

Platform Reset: The PCH asserts PLTRST# to reset devices on the
platform (such as SIO, FWH, LAN, processor, and so on). The PCH
asserts PLTRST# during power-up and when S/W initiates a hard reset
sequence through the Reset Control register (I/O Register CF9h). The
PCH drives PLTRST# active a minimum of 1 ms when initiated through
the Reset Control register (I/O Register CF9h).
NOTE: PLTRST# is in the VccSus3_3 well.

®

ME to EC

Datasheet 69

Table 2-8. Power Management Interface Signals (Sheet 2 of 4)

Name Type Description

Power Button: The Power Button will cause SMI# or SCI to indicate a

system request to go to a sleep state. If the system is already in a
sleep state, this signal will cause a wake event. If PWRBTN# is pressed
for more than 4 seconds, this will cause an unconditional transition
(power button override) to the S5 state. Override will occur even if the

PWRBTN# I

PWRBTN# I

PWROK I

RI# I

RSMRST# I

SLP_A# O

SLP_LAN# /

GPIO29

SLP_S3#

system is in the S1–S4 states. This signal has an internal pull-up
resistor and has an internal 16 ms de-bounce on the input. This signal
is in the DSW well.
NOTE: Upon entry to S5 due to a power button override, if Deep Sx is

enabled and conditions are met per Section 5.13.7.6, the
system will transition to Deep Sx.

Power Button: The Power Button will cause SMI# or SCI to indicate a
system request to go to a sleep state. If the system is already in a
sleep state, this signal will cause a wake event. If PWRBTN# is pressed
for more than 4 seconds, this will cause an unconditional transition
(power button override) to the S5 state. Override will occur even if the
system is in the S1–S4 states. This signal has an internal pull-up
resistor and has an internal 16 ms de-bounce on the input. This signal
is in the DSW well.

Power OK: When asserted, PWROK is an indication to the PCH that all
of its core power rails have been stable for 10 ms. PWROK can be
driven asynchronously. When PWROK is negated, the PCH asserts
PLTRST#.

NOTES:

1. It is required that the power rails associated with PCI/PCIe
typically the 3.3 V, 5 V, and 12 V core well rails) have been valid
for 99 ms prior to PWROK assertion in order to comply with the
100 ms PCI 2.3/PCIe 1.1 specification on PLTRST# deassertion.

2. PWROK must not glitch, even if RSMRST# is low.

Ring Indicate: This signal is an input from a modem. It can be
enabled as a wake event, and this is preserved across power failures.

Resume Well Reset: This signal is used for resetting the resume
power plane logic. This signal must be asserted for at least t201 after
the suspend power wells are valid. When deasserted, this signal is an
indication that the suspend power wells are stable.

SLP_A#: Used to control power to the active sleep well (ASW) of the
PCH.

LAN Sub-System Sleep Control: When SLP_LAN# is deasserted, it
indicates that the PHY device must be powered. When SLP_LAN# is
asserted, power can be shut off to the PHY device. SLP_LAN# will
always be deasserted in S0 and anytime SLP_A# is deasserted.

A SLP_LAN#/GPIO Select soft strap can be used for systems NOT

O

using SLP_LAN# functionality to revert to GPIO29 usage. When soft
strap is 0 (default), pin function will be SLP_LAN#. When soft strap is
set to 1, the pin returns to its regular GPIO mode.

The pin behavior is summarized in Section 5.13.10.5.

S3 Sleep Control: SLP_S3# is for power plane control. This signal

O

shuts off power to all non-critical systems when in S3 (Suspend To
RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.

Signal Description

70 Datasheet

Signal Description

Table 2-8. Power Management Interface Signals (Sheet 3 of 4)

Name Type Description

S4 Sleep Control: SLP_S4# is for power plane control. This signal

shuts power to all non-critical systems when in the S4 (Suspend to
Disk) or S5 (Soft Off) state.

SLP_S4# O

SLP_S5# /

GPIO63

SLP_SUS# O

STP_PCI# /

GPIO34

SUSACK# I

SUS_STAT# /

GPIO61

SUSCLK /

GPIO62

NOTE: This pin must be used to control the DRAM power in order to

S5 Sleep Control: SLP_S5# is for power plane control. This signal is

used to shut power off to all non-critical systems when in the S5 (Soft

O

Off) states.
Pin may also be used as GPIO63.

Deep Sx Indication: When asserted (low), this signal indicates PCH
is in Deep Sx state where internal Sus power is shut off for enhanced
power saving. When deasserted (high), this signal indicates exit from
Deep Sx state and Sus power can be applied to PCH.

If Deep Sx is not supported, then this pin can be left unconnected.
This pin is in the DSW power well.

Stop PCI Clock: This signal is an output to the clock generator for it

O

to turn off the PCI clock.

SUSACK#: If Deep Sx is supported, the EC/motherboard controlling
logic must change SUSACK# to match SUSWARN# once the EC/
motherboard controlling logic has completed the preparations
discussed in the description for the SUSWARN# pin.
NOTE: SUSACK# is only required to change in response to

This pin is in the Sus power well.

Suspend Status: This signal is asserted by the PCH to indicate that
the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal
refresh to suspend refresh mode. It can also be used by other

O

peripherals as an indication that they should isolate their outputs that
may be going to powered-off planes.

Pin may also be used as GPIO61.

Suspend Clock: This clock is an output of the RTC generator circuit to
use by other chips for refresh clock.

O

Pin may also be used as GPIO62.

use the PCH’s DRAM power-cycling feature. Refer to

Chapter 5.13.10.2 for details

SUSWARN# if Deep Sx is supported by the platform.

Datasheet 71

Table 2-8. Power Management Interface Signals (Sheet 4 of 4)

Name Type Description

SUSWARN#: This pin asserts low when the PCH is planning to enter

the Deep Sx power state and remove Suspend power (using
SLP_SUS#). The EC/motherboard controlling logic must observe
edges on this pin, preparing for SUS well power loss on a falling edge
and preparing for SUS well related activity (host/Intel ME wakes and
runtime events) on a rising edge. SUSACK# must be driven to match
SUSWARN# once the above preparation is complete. SUSACK# should

SUSWARN# /

SUSPWRDNACK

/ GPIO30

SUSPWRDNA

CK (Mobile

Only)/

SUSWARN# /

GPIO30

SYS_PWROK I

SYS_RESET# I

WAKE# I

be asserted within a minimal amount of time from SUSWARN#
assertion as no wake events are supported if SUSWARN# is asserted

O

but SUSACK# is not asserted. Platforms supporting Deep Sx, but not
wishing to participate in the handshake during wake and Deep Sx
entry may tie SUSACK# to SUSWARN#.

This pin may be multiplexed with a GPIO for use in systems that do
not support Deep Sx. This pin is muxed with SUSPWRDNACK since it is
not needed in Deep Sx supported platforms.

Reset type: RSMRST#
This signal is multiplexed with GPIO30 and SUSPWRDNACK.

SUSPWRDNACK: Active high. Asserted by the PCH on behalf of the
Intel ME when it does not require the PCH Suspend well to be
powered.

O

Platforms are not expected to use this signal when the PCH’s Deep Sx
feature is used.

This signal is multiplexed with GPIO30 and SUSWARN#.

System Power OK: This generic power good input to the PCH is
driven and utilized in a platform-specific manner. While PWROK always
indicates that the core wells of the PCH are stable, SYS_PWROK is
used to inform the PCH that power is stable to some other system
component(s) and the system is ready to start the exit from reset.

System Reset: This pin forces an internal reset after being
debounced. The PCH will reset immediately if the SMBus is idle;
otherwise, it will wait up to 25 ms ±2 ms for the SMBus to idle before
forcing a reset on the system.

PCI Express* Wake Event: Sideband wake signal on PCI Express
asserted by components requesting wake up.

Signal Description

72 Datasheet

Signal Description

2.9 Processor Interface

Table 2-9. Processor Interface Signals

Name Type Description

Keyboard Controller Reset Processor: The keyboard controller

can generate INIT# to the processor. This saves the external OR gate
with the PCH’s other sources of INIT#. When the PCH detects the

RCIN# I

A20GATE I

PROCPWRGD O

PMSYNCH O

THRMTRIP# I

assertion of this signal, INIT# is generated using a VLW message to
the processor.
NOTE: The PCH will ignore RCIN# assertion during transitions to the

S3, S4, and S5 states.

A20 Gate: Functionality reserved. A20M# functionality is not
supported. This pin requires external pull-up.

Processor Power Good: This signal should be connected to the
processor’s UNCOREPWRGOOD input to indicate when the processor
power is valid.

Power Management Sync: This signal provides state information
from the PCH to the processor.

Thermal Trip: When low, this signal indicates that a thermal trip
from the processor occurred, and the PCH will immediately transition
to a S5 state. The PCH will not wait for the processor stop grant cycle
since the processor has overheated.

2.10 SMBus Interface

Table 2-10. SM Bus Interface Signals

Name Type Description

SMBDATA I/OD SMBus Data: External pull-up resistor is required.

SMBCLK I/OD SMBus Clock: External pull-up resistor is required.

SMBALERT# /

GPIO11

SMBus Alert: This signal is used to wake the system or generate
SMI#.

I

This signal may be used as GPIO11.

Datasheet 73

2.11 System Management Interface

Table 2-11. System Management Interface Signals

Name Type Description

Intruder Detect: This signal can be set to disable the system if box

INTRUDER# I

SML0DATA I/OD

SML0CLK I/OD

SML0ALERT# /

GPIO60

SML1ALERT# /

PCHHOT# /

GPIO74

SML1CLK /

GPIO58

SML1DATA /

GPIO75

O OD

O OD

detected open. This signal’s status is readable, so it can be used like a
GPI if the Intruder Detection is not needed.

System Management Link 0 Data: SMBus link to external PHY.
External pull-up is required.

System Management Link 0 Clock: SMBus link to external PHY.
External pull-up is required.

SMLink Alert 0: Output of the integrated LAN controller to external
PHY. External pull-up resistor is required.

This signal can instead be used as GPIO60.

SMLink Alert 1: Alert for the ME SMBus controller to optional
Embedded Controller or BMC. External pull-up resistor is required.

This signal can instead be used as PCHHOT# or GPIO74.

NOTE: A soft strap determines the native function SML1ALERT# or

PCHHOT# usage. When soft strap is 0, function is
SML1ALERT#; when soft strap is 1, function is PCHHOT#.

System Management Link 1 Clock: SMBus link to optional
Embedded Controller or BMC. External pull-up resistor is required.

I/OD

This signal can instead be used as GPIO58.

System Management Link 1 Data: SMBus link to optional
Embedded Controller or BMC. External pull-up resistor is required.

I/OD

This signal can instead be used as GPIO75.

Signal Description

2.12 Real Time Clock Interface

Table 2-12. Real Time Clock Interface

Name Type Description

RTCX1 Special

RTCX2 Special

74 Datasheet

Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If
no external crystal is used, then RTCX1 can be driven with the desired
clock rate.

Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If
no external crystal is used, then RTCX2 should be left floating.

Signal Description

2.13 Miscellaneous Signals

Table 2-13. Miscellaneous Signals (Sheet 1 of 2)

Name Type Description

Internal Voltage Regulator Enable: This signal enables the

internal 1.05 V regulators when pulled high.

INTVRMEN I

DSWVRMEN I

SPKR O

RTCRST# I

SRTCRST# I

SML1ALERT#/

PCHHOT#/

GPIO74

INIT3_3V# O

GPIO35 / NMI#

(Server /

Worksta tion

Only)

OD O

This signal must be always pulled-up to VccRTC on desktop platforms
and may optionally be pulled low on mobile platforms if using an
external VR for the DcpSus rail.
NOTE: See VccCore signal description for behavior when INTVRMEN

is sampled low (external VR mode).

Deep Sx Well Internal Voltage Regulator Enable: This signal
enables the internal DSW 1.05 V regulators.

This signal must be always pulled-up to VccRTC.

Speaker: The SP KR signal is the output of counter 2 and is internally
“ANDed” with Port 61h Bit 1 to provide Speaker Data Enable. This
signal drives an external speaker driver device, which in turn drives
the system speaker. Upon PLTRST#, its output state is 0.
NOTE: SPKR is sampled as a functional strap. See Section 2.27 for

more details. There is a weak integrated pull-down resistor on
SPKR pin.

RTC Reset: When asserted, this signal resets register bits in the RTC
well.

NOTES:

1. Unless CMOS is being cleared (only to be done in the G3
power state), the RTCRST# input must always be high when
all other RTC power planes are on.

2. In the case where the RTC battery is dead or missing on the
platform, the RTCRST# pin must rise before the DPWROK pin.

Secondary RTC Reset: This signal resets the manageability register
bits in the RTC well when the RTC battery is removed.

NOTES:

1. The SRTCRST# input must always be high when all other RTC
power planes are on.

2. In the case where the RTC battery is dead or missing on the
platform, the SRTCRST# pin must rise before the RSMRST#
pin.

PCHHOT#: This signal is used to indicate a PCH temperature out of
bounds condition to an external EC, when PCH temperature is greater
than value programmed by BIOS. An external pull-up resistor is
required on this signal.

OD

NOTE: A soft strap determines the native function SML1ALERT# or

PCHHOT# usage. When soft strap is 0, function is
SML1ALERT#, when soft strap is 1, function is PCHHOT#.

Initialization 3.3 V: INIT3_3V# is asserted by the PCH for 16 PCI
clocks to reset the processor. This signal is intended for Firmware
Hub.

NMI#: This is an NMI event indication to an external controller ( su ch
as a BMC) on server/workstation platforms.

When operating as NMI event indication pin function (enabled when
"NMI SMI Event Native GPIO Enable" soft strap [PCHSTRP9:bit 16] is
set to 1), the pin is OD (open drain).

Datasheet 75

Table 2-13. Miscellaneous Signals (Sheet 2 of 2)

Name Type Description

PCIECLKRQ2# /
GPIO20 / SMI#

(Server /

Worksta tion

Only)

OD O

SMI#: This is an SMI event indication to an external controller (such
as a BMC) on server/workstation platforms.

When operating as SMI event indication pin function (enabled when
"NMI SMI Event Native GPIO Enable" soft strap [PCHSTRP9:bit 16] is
set to 1), the pin is OD (open drain).

2.14 Intel® High Definition Audio Link

Table 2-14. Intel® High Definition Audio Link Signals (Sheet 1 of 2)

Name Type Description

®

Intel

HDA_RST# O

HDA_SYNC O

HDA_BCLK O

HDA_SDO O

HDA_SDIN[3:0] I

High Definition Audio Reset: Master hardware reset to

external codec(s).

Intel

High Definition Audio Sync: 48 kHz fixed rate sample

sync to the codec(s). Also used to encode the stream number.

NOTE: This signal is sampled as a functional strap. See

Section 2.27 for more details. There is a weak integrated

pull-down resistor on this pin.

Intel High Definition Audio Bit Clock Output: 24.000 MHz
serial data clock generated by the Intel High Definition Audio
controller (the PCH).

Intel High Definition Audio Serial Data Out: Serial TDM data
output to the codec(s). This serial output is double-pumped for a
bit rate of 48 Mb/s for Intel High Definition Audio.

NOTE: This signal is sampled as a functional strap. See

Section 2.27 for more details. There is a weak integrated

pull-down resistor on this pin.

Intel High Definition Audio Serial Data In [3:0]: Serial TDM
data inputs from the codecs. The serial input is single-pumped
for a bit rate of 24 Mb/s for Intel High Definition Audio. These
signals have integrated pull-down resistors, which are always
enabled.

Signal Description

NOTE: During enumeration, the PCH will drive this signal. During

normal operation, the CODEC will drive it.

Intel High Definition Audio Dock Enable: This signal controls
the external Intel HD Audio docking isolation logic. This is an

HDA_DOCK_EN#

(Mobile Only)

/GPIO33

76 Datasheet

active low signal. When deasserted the external docking switch is
in isolate mode. When asserted the external docking switch

O

electrically connects the Intel HD Audio dock signals to the
corresponding PCH signals.

This signal can instead be used as GPIO33.

Signal Description

Table 2-14. Intel® High Definition Audio Link Signals (Sheet 2 of 2)

Name Type Description

Intel High Definition Audio Dock Reset: This signal is a

dedicated HDA_RST# signal for the codec(s) in the docking

HDA_DOCK_RST#

(Mobile Only)

/ GPIO13

station. Aside from operating independently from the normal
HDA_RST# signal, it otherwise works similarly to the HDA_RST#

O

signal.
This signal is shared with GPIO13. This signal defaults to GPIO13

mode after PLTRST#. BIOS is responsible for configuring GPIO13
to HDA_DOCK_RST# mode.

2.15 Controller Link

Table 2-15. Controller Link Signals

Signal Name Type Description

CL_RST1# O

CL_CLK1 I/O

CL_DATA1 I/O

Controller Link Reset: Controller Link reset that connects to a

Wireless LAN Device supporting Intel Active Management
Tec h no lo g y.

Controller Link Clock: Bi-directional clock that connects to a
Wireless LAN Device supporting Intel Active Management
Tec h no lo g y.

Controller Link Data: Bi-directional data that connects to a
Wireless LAN Device supporting Intel Active Management
Tec h no lo g y.

2.16 Serial Peripheral Interface (SPI)

Table 2-16. Serial Peripheral Interface (SPI) Signals

Name Type Description

SPI_CS0# O SPI Chip Select 0: Used as the SPI bus request signal.

SPI_CS1# OSPI Chip Select 1: Used as the SPI bus request signal.

SPI_MISO I SPI Master IN Slave OUT: Data input pin for PCH.

SPI_MOSI I/O SPI Master OUT Slave IN: Data output pin for PCH.

SPI_CLK O

SPI Clock: SPI clock signal, during idle the bus owner will drive the

clock signal low. 17.86 MHz and 31.25 MHz.

Datasheet 77

2.17 Thermal Signals

Table 2-17. Thermal Signals

Signal Name Type Description

PWM[3:0]

(Server/

Worksta tion

Usage Only); Not

available in

Mobile &

Desktop)

TACH0 / GPIO17

TACH1 / GPIO1
TACH2 / GPIO6

TACH3 / GPIO7
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71

(TACH* signals

used on Server/

Worksta tion

Only; not

available in

Mobile &

Desktop)

SST (Server/

Worksta tion

Usage Only; not

available in

Mobile &

Desktop)

PECI I/O

OD O

I

I/O

Signal Description

Fan Pulse Width Modulation Outputs: Pulse Width Modulated
duty cycle output signals used for fan control.

These signals are 5 V tolerant.

Fan Tachometer Inputs: Tachometer pulse input signal that is
used to measure fan speed. This signal is connected to the “Sense”
signal on the fan.

Can instead be used as a GPIO.

Simple Serial Transport: Single-wire, serial bus. Connect to SST
compliant devices such as SST thermal sensors or voltage sensors.

Platform Environment Control Interface: Single-wire, serial
bus.

2.18 Testability Signals

Table 2-18. Testability Signals

Name Type Description

JTAG_TCK I

JTAG_TMS I

JTAG_TDI I

JTAG_TDO OD

NOTE: JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary-Scan

Architecture (IEEE Std. 1149.1-2001)

78 Datasheet

Test Clock Input (TCK): The test clock input provides the clock
for the JTAG test logic.

Test Mode Select (TMS): The signal is decoded by the Test
Access Port (TAP) controller to control test operations.

Test Data Input (TDI): Serial test instructions and data are
received by the test logic at TDI.

Test Data Output (TDO): TDO is the serial output for test
instructions and data from the test logic defined in this standard.

Signal Description

2.19 Clock Signals

Table 2-19. Clock Interface Signals (Sheet 1 of 2)

Name Type Description

CLKOUT_ITPXDP_P,

CLKOUT_ITPXDP_N

CLKOUT_DP_P,

CLKOUT_DP_N

CLKIN_DMI_P,

CLKIN_DMI_N

CLKOUT_DMI_P,

CLKOUT_DMI_N

CLKIN_SATA_P,

CLKIN_SATA_N

CLKIN_DOT96_P,

CLKIN_DOT96_N

XTAL25_IN I Connection for 25 MHz crystal to PCH oscillator circuit.

XTAL25_OUT O Connection for 25 MHz crystal to PCH oscillator circuit.

REFCLK14IN I

CLKOUT_PEG_A_P,

CLKOUT_PEG_A_N

CLKOUT_PEG_B_P,

CLKOUT_PEG_B_N

PEG_A_CLKRQ# /

GPIO47 (Mobile Only),

PEG_B_CLKRQ# /

GPIO56

(Mobile Only)

CLKOUT_PCIE[7:0]_P,

CLKOUT_PCIE[7:0]_N

CLKIN_GND0_P,

CLKIN_GND0_N (Desktop

Only) CLKIN_GND1_P,

CLKIN_GND1_N

PCIECLKRQ0# / GPIO73,
PCIECLKRQ1# / GPIO18,
PCIECLKRQ3# / GPIO25,

PCIECLKRQ4# / GPIO26

(all the above CLKRQ#

signals are Mobile Only)

PCIECLKRQ2# / GPIO20

/ SMI#,
PCIECLKRQ5# / GPIO44,
PCIECLKRQ6# / GPIO45,

PCIECLKRQ7# / GPIO46

(SMI# above is server/

workstation only)

100 MHz Differential output to processor XDP/ITP

O

connector on platform

O 120 MHz Differential output for DisplayPort reference

Unused.

I

NOTE: External pull-down input termination is required.

100 MHz PCIe Gen2 specification jitter tolerant

O

differential output to processor.

Unused.

I

NOTE: External pull-down input termination is required.

Unused.

I

NOTE: External pull-down input termination is required.

Unused.
NOTE: External pull-down input termination is required

100 MHz Gen2 PCIe specification differential output to

O

PCI Express* Graphics device

100 MHz Gen2 PCIe specification differential output to a

O

second PCI Express Graphics device

Clock Request Signals for PCIe Graphics SLOTS
Can instead by used as GPIOs

I

NOTE: External pull-up resistor required if used for

100 MHz PCIe Gen2 specification differential output to

O

PCI Express devices

Requires external pull-down termination (can be shared

I

between P and N signals of the differential pair).

Clock Request Signals for PCI Express 100 MHz clocks
Can instead by used as GPIOs

I

NOTE: External pull-up resistor required if used for

Clock Request Signals for PCI Express 100 MHz Clocks
Can instead by used as GPIOs

I

NOTE: External pull-up resistor required if used for

CLKREQ# functionality.

CLKREQ# functionality.

CLKREQ# functionality.

Datasheet 79

Table 2-19. Clock Interface Signals (Sheet 2 of 2)

Name Type Description

Single-Ended, 33 MHz outputs to PCI connectors/
devices. One of these signals must be connected to

CLKOUT_PCI[4:0] O

CLKIN_PCILOOPBACK I

CLKOUTFLEX0

1

/ GPIO64 O

CLKOUTFLEX11 / GPIO65 O

CLKOUTFLEX21 / GPIO66 O

CLKOUTFLEX31 / GPIO67 O

XCLK_RCOMP I/O

CLKIN_PCILOOPBACK to function as a PCI clock

loopback. This allows skew control for variable lengths of
CLKOUT_PCI[4:0].

33 MHz PCI clock feedback input, to reduce skew
between PCH on-die PCI clock and PCI clock observed by
connected PCI devices

Configurable as a GPIO or as a programmable output
clock which can be configured as one of the following:

• 33 MHz

• 27 MHz (SSC/Non-SSC)

• 48/24 MHz

• 14.318 MHz

•DC Output logic ‘0’

Configurable as a GPIO or as a programmable output
clock which can be configured as one of the following:

• Non functional and unsupported clock output value (Default)

• 27 MHz (SSC/Non-SSC)

• 14.318 MHz output to SIO/EC

• 48/24 MHz

•DC Output logic ‘0’

Configurable as a GPIO or as a programmable output
clock which can be configured as one of the following:

• 33 MHz

• 25 MHz

• 27 MHz (SSC/Non-SSC)

• 48/24 MHz

• 14.318 MHz

•DC Output logic ‘0’

Configurable as a GPIO or as a programmable output
clock which can be configured as one of the following:

• 27 MHz (SSC/Non SSC)

• 14.318 MHz output to SIO

• 48/24 MHz (Default)

•DC Output logic ‘0’

Differential clock buffer Impedance
Compensation: Connected to an external precision

resistor (90.9 Ω ±1%) to VccDIFFCLKN

Signal Description

NOTE:

1. It is highly recommended to prioritize 27/14.318/24/48 MHz clocks on CLKOUTFLEX1 and
CLKOUTFLEX3 outputs. Intel does not recommend configuring the 27/14.318/24/48 MHz
clocks on CLKOUTFLEX0 and CLKOUTFLEX2 if more than 2x 33 MHz clocks in addition to the
Feedback clock are used on the CLKOUT_PCI outputs.

80 Datasheet

Signal Description

2.20 LVDS Signals

All signals are Mobile Only, except as noted that are also available in Desktop.

Table 2-20. LVDS Interface Signals

Name Type Description

LVDSA_DATA[3:0] O LVDS Channel A differential data output – positive

LVDSA_DATA#[3:0] O LVDS Channel A differential data output – negative

LVDSA_CLK O LVDS Channel A differential clock output – positive

LVDSA_CLK# O LVDS Channel A differential clock output – negative

LVDSB_DATA[3:0] O LVDS Channel B differential data output – positive

LVDSB_DATA#[3:0] O LVDS Channel B differential data output – negative

LVDSB_CLK O LVDS Channel B differential clock output – positive

LVDSB_CLK# O LVDS Channel B differential clock output – negative

L_DDC_CLK I/O EDID support for flat panel display

L_DDC_DATA I/O EDID support for flat panel display

L_CTRL_CLK I/O

L_CTRL_DATA I/O

L_VDD_EN (available

in Desktop)

L_BKLTEN (available in

Desktop)

L_BKLTCTL (available

in Desktop)

LVDS_VREFH O Test mode voltage reference.

LVDS_VREFL O Test mode voltage reference.

LVD_IBG I LVDS reference current.

LVD_VBG O Test mode voltage reference.

Control signal (clock) for external SSC clock chip control –
optional

Control signal (data) for external SSC clock chip control –
optional

LVDS Panel Power Enable: Panel power control enable
control for LVDS or embedded DisplayPort*.

O

This signal is also called VDD_DBL in the CPIS specification
and is used to control the VDC source to the panel logic.

LVDS Backlight Enable: Panel backlight enable control for
LVDS or embedded DisplayPort.

O

This signal is also called ENA_BL in the CPIS specification
and is used to gate power into the backlight circuitry.

Panel Backlight Brightness Control: Panel brightness
control for LVDS or embedded DisplayPort.

O

This signal is also called VARY_BL in the CPIS specification
and is used as the PWM Clock input signal.

Datasheet 81

2.21 Analog Display /VGA DAC Signals

Table 2-21. Analog Display Interface Signals

Name Type Description

O

VGA_RED

VGA_GREEN

VGA_BLUE

DAC_IREF

VGA_HSYNC

VGA_VSYNC

VGA_DDC_CLK

VGA_DDC_DATA

VGA_IRTN

I/O

HVCMOS

HVCMOS

I/O

COD

I/O

COD

I/O

COD

RED Analog Video Output: This signal is a VGA Analog video
output from the internal color palette DAC.

A

O

GREEN Analog Video Output: This signal is a VGA Analog
video output from the internal color palette DAC.

A

O

BLUE Analog Video Output: This signal is a VGA Analog video
output from the internal color palette DAC.

A

Resistor Set: Set point resistor for the internal color palette
DAC. A 1 kΩ 1% resistor is required between DAC_IREF and

A

motherboard ground.

VGA Horizontal Synchronization: This signal is used as the

O

horizontal sync (polarity is programmable) or “sync interval”.

2.5 V output

O

VGA Vertical Synchronization: This signal is used as the
vertical sync (polarity is programmable). 2.5 V output.

Monitor Control Clock

Monitor Control Data

Monitor Interrupt Return

Signal Description

2.22 Intel® Flexible Display Interface (Intel® FDI)

Table 2-22. Intel® Flexible Display Interface Signals

Signal Name Type Description

FDI_RXP[3:0] I Display Link 1 positive data in

FDI_RXN[3:0] I Display Link 1 negative data in

FDI_FSYNC[0] ODisplay Link 1 Frame sync

FDI_LSYNC[0] O Display Link 1 Line sync

FDI_RXP[7:4] I Display Link 2 positive data in

FDI_RXN[7:4] I Display Link 2 negative data in

FDI_FSYNC[1] ODisplay Link 2 Frame sync

FDI_LSYNC[1] O Display Link 2 Line sync

FDI_INT O Used for Display interrupts from PCH to processor.

82 Datasheet

Signal Description

2.23 Digital Display Signals

Table 2-23. Digital Display Interface Signals (Sheet 1 of 3)

Name Type Description

Port B: Capable of Intel

Intel SDVO

DDPB_[0]P: red
DDPB_[1]P: green
DDPB_[2]P: blue
DDPB_[3]P: clock

HDMI / DVI Port B Data and Clock Lines

DDPB_[3:0]P O

DDPB_[3:0]N O

DDPB_AUXP I/O Port B: DisplayPort Aux

DDPB_AUXN I/O Port B: DisplayPort Aux Complement

DDPB_HPD I Port B: TMDSB_HPD Hot Plug Detect

SDVO_CTRLCLK I/O Port B: HDMI Control Clock. Shared with port B Intel SDVO

SDVO_CTRLDATA I/O Port B: HDMI Control Data. Shared with Port B Intel SDVO

SDVO_INTP I SDVO_INTP: Serial Digital Video Input Interrupt

SDVO_INTN I SDVO_INTN: Serial Digital Video Input Interrupt Complement

SDVO_TVCLKINP I

DDPB_[0]P: TMDSB_DATA2
DDPB_[1]P: TMDSB_DATA1
DDPB_[2]P: TMDSB_DATA0
DDPB_[3]P: TMDSB_CLK

DisplayPort Port B

DDPB_[0]P: DisplayPort Lane 0
DDPB_[1]P: DisplayPort Lane 1
DDPB_[2]P: DisplayPort Lane 2
DDPB_[3]P: DisplayPort Lane 3

Port B: Capable of Intel SDVO / HDMI / DVI / DisplayPort

Intel SDVO

DDPB_[0]N: red complement
DDPB_[1]N: green complement
DDPB_[2]N: blue complement
DDPB_[3]N: clock complement

HDMI/ DVI Port B Data and Clock Line Complements

DDPB_[0]N: TMDSB_DATA2B
DDPB_[1]N: TMDSB_DATA1B
DDPB_[2]N: TMDSB_DATA0B
DDPB_[3]N: TMDSB_CLKB

DisplayPort Port B

DDPB_[0]N: DisplayPort Lane 0 complement
DDPB_[1]N: DisplayPort Lane 1 complement
DDPB_[2]N: DisplayPort Lane 2 complement
DDPB_[3]N: DisplayPort Lane 3 complement

SDVO_TVCLKINP: Serial Digital Video TVOUT Synchronization
Clock

®

SDVO / HDMI / DVI / DisplayPort

Datasheet 83

Table 2-23. Digital Display Interface Signals (Sheet 2 of 3)

Name Type Description

SDVO_TVCLKINN I

SDVO_STALLP I SDVO_STALLP: Serial Digital Video Field Stall

SDVO_STALLN I SDVO_STALLN: Serial Digital Video Field Stall Complement

DDPC_[3:0]P O

DDPC_[3:0]N O

DDPC_AUXP I/O Port C: DisplayPort Aux

DDPC_AUXN I/O Port C: DisplayPort Aux Complement

DDPC_HPD I Port C: TMDSC_HPD Hot Plug Detect

DDPC_CTRLCLK I/O HDMI Port C Control Clock

DDPC_CTRLDATA I/O HDMI Port C Control Data

DDPD_[3:0]P O

SDVO_TVCLKINN: Serial Digital Video TVOUT Synchronization

Clock Complement

Port C: Capable of HDMI / DVI / DP

HDMI / DVI Port C Data and Clock Lines

DDPC_[0]P: TMDSC_DATA2
DDPC_[1]P: TMDSC_DATA1
DDPC_[2]P: TMDSC_DATA0
DDPC_[3]P: TMDSC_CLK

DisplayPort Port C

DDPC_[0]P: DisplayPort Lane 0
DDPC_[1]P: DisplayPort Lane 1
DDPC_[2]P: DisplayPort Lane 2
DDPC_[3]P: DisplayPort Lane 3

Port C: Capable of HDMI / DVI / DisplayPort

HDMI / DVI Port C Data and Clock Line Complements

DDPC_[0]N: TMDSC_DATA2B
DDPC_[1]N: TMDSC_DATA1B
DDPC_[2]N: TMDSC_DATA0B
DDPC_[3]N: TMDSC_CLKB

DisplayPort Port C Complements

DDPC_[0]N: Lane 0 complement
DDPC_[1]N: Lane 1 complement
DDPC_[2]N: Lane 2 complement
DDPC_[3]N: Lane 3 complement

Port D: Capable of HDMI / DVI / DP

HDMI / DVI Port D Data and Clock Lines

DDPD_[0]P: TMDSC_DATA2
DDPD_[1]P: TMDSC_DATA1
DDPD_[2]P: TMDSC_DATA0
DDPD_[3]P: TMDSC_CLK

DisplayPort Port D

DDPD_[0]P: DisplayPort Lane 0
DDPD_[1]P: DisplayPort Lane 1
DDPD_[2]P: DisplayPort Lane 2
DDPD_[3]P: DisplayPort Lane 3

Signal Description

84 Datasheet

Signal Description

Table 2-23. Digital Display Interface Signals (Sheet 3 of 3)

Name Type Description

Port D: Capable of HDMI / DVI / DisplayPort

HDMI / DVI Port D Data and Clock Line Complements

DDPD_[0]N: TMDSC_DATA2B
DDPD_[1]N: TMDSC_DATA1B
DDPD_[2]N: TMDSC_DATA0B

DDPD_[3:0]N O

DDPD_AUXP I/O Port D: DisplayPort Aux

DDPD_AUXN I/O Port D: DisplayPort Aux Complement

DDPD_HPD I Port D: TMDSD_HPD Hot Plug Detect

DDPD_CTRLCLK I/O HDMI Port D Control Clock

DDPD_CTRLDATA I/O HDMI Port D Control Data

DDPD_[3]N: TMDSC_CLKB

DisplayPort Port D Complements

DDPD_[0]N: Lane 0 complement
DDPD_[1]N: Lane 1 complement
DDPD_[2]N: Lane 2 complement
DDPD_[3]N: Lane 3 complement

2.24 General Purpose I/O Signals

Notes:

1. GPIO Configuration registers within the Core Well are reset whenever PWROK is
deasserted.

2. GPIO Configuration registers within the Suspend Well are reset when RSMRST# is
asserted, CF9h reset (06h or 0Eh), or SYS_RESET# is asserted. However, CF9h
reset and SYS_RESET# events can be masked from resetting the Suspend well
GPIO by programming appropriate GPIO Reset Select (GPIO_RST_SEL) registers.

3. GPIO24 is an exception to the other GPIO Signals in the Suspend Well and is not
reset by CF9h reset (06h or 0Eh)

Table 2-24. General Purpose I/O Signals (Sheet 1 of 5)

Glitch

Name Type

GPIO75 I/O 3.3 V Suspend Native No No No Multiplexed with SML1DATA

GPIO74 I/O 3.3 V Suspend Native No No No

GPIO73

(Mobile Only)

Toler-

ance

I/O 3.3 V Suspend Native No No No Multiplexed with PCIECLKRQ0#

Power

Well

Default

Blink

Capa-

bility

Protection

during

Power-On

Sequence

GPI

Event

Support

Description

Multiplexed with SML1ALERT#/
PCHHOT#

11

11

Datasheet 85

Signal Description

Table 2-24. General Purpose I/O Signals (Sheet 2 of 5)

Glitch

Name Type

Toler-

ance

Power

Well

Default

Blink

Capa-

bility

Protection

during

Power-On

Sequence

Native

(Mobile

GPIO72 I/O 3.3 V Suspend

Only)

GPI

No No No

(Desktop

Only)

GPIO[71:70] I/O 3.3 V Core Native No No No

GPIO[69:68] I/O 3.3 V Core GPI No No No

GPIO67 I/O 3.3 V Core Native No No No Multiplexed with CLKOUTFLEX3

GPIO66 I/O 3.3 V Core Native No No No Multiplexed with CLKOUTFLEX2

GPIO65 I/O 3.3 V Core Native No No No Multiplexed with CLKOUTFLEX1

GPIO64 I/O 3.3 V Core Native No No No Multiplexed with CLKOUTFLEX0

GPIO63 I/O 3.3 V Suspend Native No Yes No Multiplexed with SLP_S5#

GPIO62 I/O 3.3 V Suspend Native No No No Multiplexed with SUSCLK

GPIO61 I/O 3.3 V Suspend Native No Yes No Multiplexed with SUS_STAT#

GPIO60 I/O 3.3 V Suspend Native No No No Multiplexed with SML0ALERT#

GPIO59 I/O 3.3 V Suspend Native No No No Multiplexed with OC0#

GPIO58 I/O 3.3 V Suspend Native No No No Multiplexed with SML1CLK

GPIO57 I/O 3.3 V Suspend GPI No Yes No Unmultiplexed

GPIO56

(Mobile Only)

GPIO55

I/O 3.3 V Suspend Native No No No

9

I/O 3.3 V Core Native No No No

GPIO54 I/O 5.0 V Core Native No No No

9

GPIO53

I/O 3.3 V Core Native No No No

GPIO52 I/O 5.0 V Core Native No No No

9

GPIO51

I/O 3.3 V Core Native No No No

GPIO50 I/O 5.0 V Core Native No No No

GPIO49 I/O 3.3 V Core GPI No No No

GPI

Event

Support

Description

Mobile: Multiplexed with
BATLOW#.

Desktop: Unmultiplexed;
requires pull-up resistor

Desktop: Multiplexed with
TACH[ 7:6]

Mobile: Used as GPIO only

Desktop: Multiplexed with
TACH[ 5:4]

Mobile: Used as GPIO only

11

Mobile: Multiplexed with
PEG_B_CLKRQ#

Desktop: Multiplexed with GNT3#
Mobile: Used as GPIO only

Desktop: Multiplexed with

11

REQ3#

.

Mobile: Used as GPIO only

Desktop: Multiplexed with GNT2#
Mobile: Used as GPIO only

Desktop: Multiplexed with

11

REQ2#

.

Mobile: Used as GPIO only

Desktop: Multiplexed with GNT1#
Mobile: Used as GPIO only

Desktop: Multiplexed with

11

REQ1#

.

Mobile: Used as GPIO only

Multiplexed with SATA5GP and
TEMP_ALERT#

4

.

86 Datasheet

Signal Description

Table 2-24. General Purpose I/O Signals (Sheet 3 of 5)

Glitch

Name Type

Toler-

ance

Power

Well

Default

Blink

Capa-

bility

Protection

during

Power-On

Sequence

GPIO48 I/O 3.3 V Core GPI No No No Multiplexed with SDATAOUT1.

GPIO47

(Mobile Only)

I/O 3.3 V Suspend Native No No No Multiplexed with PEG_A_CLKRQ#

GPIO46 I/O 3.3 V Suspend Native No No No Multiplexed with PCIECLKRQ7#

GPIO45 I/O 3.3 V Suspend Native No No No Multiplexed with PCIECLKRQ6#

GPIO44 I/O 3.3 V Suspend Native No No No Multiplexed with PCIECLKRQ5#

GPIO[43:40] I/O 3.3 V Suspend Native No No No Multiplexed with OC[4:1]#

GPIO39 I/O 3.3 V Core GPI No No No Multiplexed with SDATAOUT0.

GPIO38 I/O 3.3 V Core GPI No No No Multiplexed with SLOAD.

9

GPIO37

GPIO36

I/O 3.3 V Core GPI No No No Multiplexed with SATA3GP.

9

I/O 3.3 V Core GPI No No No Multiplexed with SATA2GP.

GPIO35 I/O 3.3 V Core GPO No No No Multiplexed with NMI#.

GPIO34 I/O 3.3 V Core GPI No No No Multiplexed with STP_PCI#

GPIO33 I/O 3.3 V Core GPO No No No

13

GPO,

Native

(Mobile

No No No

only)

GPI Yes Yes No

GPIO32

(not

available in

I/O 3.3 V Core

Mobile)

GPIO31 I/O 3.3 V DSW

GPIO30 I/O 3.3 V Suspend Native Yes Yes No

GPIO29 I/O 3.3 V Suspend Native Yes Yes No

GPIO28

9

I/O 3.3 V Suspend GPO Yes No No Unmultiplexed

GPI

Event

Support

Description

Mobile: Multiplexed with
HDA_DOCK_EN# (Mobile Only)

Desktop: Used as GPIO only

Unmultiplexed (Desktop Only)
Mobile Only: Used as CLKRUN#,

unavailable as GPIO

4

.

Multiplexed with
ACPRESENT(Mobile Only)

Desktop: Used as GPIO31 only.
Unavailable as ACPRESENT

Multiplexed with SUSPWRDNACK,
SUSWARN#

Desktop: Can be configured as
SUSWARN# or GPIO30 only.
Cannot be used as
SUSPWRDNACK.

Mobile: Used as SUSPWRDNACK,
SUSWARN#, or GPIO30

Multiplexed with SLP_LAN#
Pin usage as GPIO is determined

by SLP_LAN#/GPIO Select Soft-

10

strap

. Soft-strap value is not
preserved for this signal in the
Sx/Moff state and the pin will
return to its native functionality
(SLP_LAN#).

11

.

4

.

6

.

Datasheet 87

Signal Description

Table 2-24. General Purpose I/O Signals (Sheet 4 of 5)

Glitch

Name Type

Toler-

ance

Power

Well

Default

Blink

Capa-

bility

Protection

during

Power-On

Sequence

GPIO27 I/O 3.3 V DSW

GPIO26

(Mobile Only)

GPIO25

(Mobile Only)

I/O 3.3 V Suspend Native Yes No No

I/O 3.3 V Suspend Native Yes No No

13

GPI Yes No No

GPIO24 I/O 3.3 V Suspend GPO Yes Yes No

GPIO23 I/O 3.3 V Core Native Yes No No Multiplexed with LDRQ1#.

GPIO22 I/O 3.3 V Core GPI Yes No No Multiplexed with SCLOCK

GPIO21 I/O 3.3 V Core GPI Yes No No Multiplexed with SATA0GP

GPIO20 I/O 3.3 V Core Native Yes No No

GPIO18

9

I/O 3.3 V Core GPI Yes No No Multiplexed with SATA1GP

I/O 3.3 V Core Native Yes

7

No No

GPIO19

(Mobile Only)

GPIO17 I/O 3.3 V Core GPI Yes No No

GPIO16 I/O 3.3 V Core GPI Yes No No Multiplexed with SATA4GP

GPIO15

9

I/O 3.3 V Suspend GPO Yes No Yes

GPIO14 I/O 3.3 V Suspend Native Yes No Yes

GPIO13 I/O

3.3 V
or

1.5 V

12

HDA

Suspend

GPI Yes No Yes

GPIO12 I/O 3.3 V Suspend Native Yes No Yes

GPIO11 I/O 3.3 V Suspend Native Yes No Yes

GPIO10 I/O 3.3 V Suspend Native Yes No Yes

GPIO9 I/O 3.3 V Suspend Native Yes No Yes

GPI

Event

Support

2

2

2

2

2

2

2

Description

Unmultiplexed. Can be
configured as wake input to allow
wakes from Deep Sx. This GPIO
has no GPIO functionality in the
Deep Sx states other than wake
from Deep Sx if this option has
been configured.

Mobile: Multiplexed with
PCIECLKRQ4#

Mobile: Multiplexed with
PCIECLKRQ3#

Desktop: Can be used as
PROC_MISSING configured using
Intel ME firmware.

Mobile: Unmultiplexed
NOTE: GPIO24 configuration

register bits are cleared
by RSMRST# and not
cleared by CF9h reset
event.

Multiplexed with PCIECLKRQ2#,
SMI#

Mobile: Multiplexed with
PCIECLKRQ1#

Desktop: Multiplexed with
TACH0 .

Mobile: Used as GPIO17 only.

Unmultiplexed

Multiplexed with OC7#

Multiplexed with
HDA_DOCK_RST# (Mobile

4

Only)

.

Desktop: Used as GPIO only

Multiplexed with
LAN_PHY_PWR_CTRL. GPIO /
Functionality controlled using soft

8,14

strap

Multiplexed with SMBALERT#11.

Multiplexed with OC6#11.

Multiplexed with OC5#11.

88 Datasheet

Signal Description

Table 2-24. General Purpose I/O Signals (Sheet 5 of 5)

Glitch

Name Type

Toler-

ance

Power

Well

Default

Blink

Capa-

bility

Protection

during

Power-On

Sequence

GPIO8 I/O 3.3 V Suspend GPO Yes No Yes

GPIO[7:6] I/O 3.3 V Core GPI Yes No Yes

GPIO[5:2] I/OD 5 V Core GPI Yes No Yes

GPIO1 I/O 3.3 V Core GPI Yes No Yes

GPIO0 I/O 3.3 V Core GPI Yes No Yes

NOTES:

1. All GPIOs can be configured as either input or output.

2. GPI[15:0] can be configured to cause a SMI# or SCI. A GPI can be routed to either an SMI#
or an SCI, but not both.

3. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO
signals are not driven high into powered-down planes. Also, external devices should not be
driving powered down GPIOs high. Some GPIOs may be connected to pins on devices that
exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power
(PWROK low) or a Power Button Override event will result in the PCH driving a pin to a logic
1 to another device that is powered down.

4. The functionality that is multiplexed with the GPIO may not be used in desktop configuration.

5. When this signal is configured as GPO the output stage is an open drain.

6. In an Intel

®

ME disabled system, GPIO31 may be used as ACPRESENT from the EC.

7. GPIO18 will toggle at a frequency of approximately 1 Hz when the signal is programmed as a
GPIO (when configured as an output) by BIOS.

8. For GPIOs where GPIO vs. Native Mode is configured using SPI Soft Strap, the corresponding
GPIO_USE_SEL bits for these GPIOs have no effect. The GPIO_USE_SEL bits for these GPIOs
may change to reflect the Soft-Strap configuration even though GPIO Lockdown Enable (GLE)
bit is set.

9. These pins are used as Functional straps. See Section 2.27 for more details.

10. Once Soft-strap is set to GPIO mode, this pin will default to GP Input. When Soft-strap is
SLP_LAN# usage and if Host BIOS does not configure as GP Output for SLP_LAN# control,
SLP_LAN# behavior will be based on the setting of the RTC backed SLP_LAN# Default Bit
(D31:F0:A4h:Bit 8).

11. When the multiplexed GPIO is used as GPIO functionality, care should be taken to ensure the
signal is stable in its inactive state of the native functionality, immediately after reset until it
is initialized to GPIO functionality.

12. GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Voltage tolerance on the signal is
the same as VccSusHDA.

13. GPIO functionality is only available when the Suspend well is powered although pin is in
DSW.

14. GPIO will assume its native functionality until the soft strap is loaded after which time the
functionality will be determined by the soft strap setting.

GPI

Event

Support

Description

2

Unmultiplexed

Multiplexed with TACH[3:2].

2

Mobile: Used as GPIO[7:6] only.

2

Multiplexed PIRQ[H:E]#5.

Multiplexed with TACH1.

2

Mobile: Used as GPIO1 only.

2

Multiplexed with BMBUSY#

Datasheet 89

2.25 Manageability Signals

The following signals can be optionally used by Intel Management Engine supported
applications and appropriately configured by Intel Management Engine firmware. When
configured and used as a manageability function, the associated host GPIO
functionality is no longer available. If the manageability function is not used in a
platform, the signal can be used as a host General Purpose I/O or a native function.

Table 2-25. Manageability Signals

Name Type Description

SUSWARN# /

SUSPWRDNACK

(Mobile Only)

/ GPIO30

ACPRESENT

(Mobile Only) /

GPIO31

SATA5GP / GPIO49

/ TEMP_ALERT#

GPIO24 /

PROC_MISSING

(Desktop Only)

I/O

I/O

I/O

I/O

Used by Intel
supported platforms or as SUSPWRDNACK in non Deep Sx state
supported platforms.
NOTE: This signal is in the Suspend power well.

Input signal from the Embedded Controller (EC) on Mobile
systems to indicate AC power source or the system battery.
Active High indicates AC power.
NOTE: This signal is in the Deep Sx power well.

Used as an alert (active low) to indicate to the external
controller (such as EC or SIO) that temperatures are out of
range for the PCH or Graphics/Memory Controller or the
processor core.
NOTE: This signal is in the Core power well.

Used to indicate Processor Missing to the Intel Management
Engine.
NOTE: This signal is in the Suspend power well.

Signal Description

®

ME as either SUSWARN# in Deep Sx state

NOTE: SLP_LAN# may also be configured by Intel® ME FW in Sx/Moff. Please refer to SLP_LAN#/

GPIO29 signal description for details.

2.26 Power and Ground Signals

Table 2-26. Power and Ground Signals (Sheet 1 of 3)

Name Description

DcpRTC

DcpSST

DcpSus

DcpSusByp

Decoupling: This signal is for RTC decoupling only. This signal requires

decoupling.

Decoupling: Internally generated 1.5 V powered off of Suspend Well. This
signal requires decoupling. Decoupling is required even if this feature is not
used.

1.05 V Suspend well power.
Internal VR mode (INTVRMEN sampled high): Well generated internally. Pins

should be left No Connect
External VR mode (INTVRMEN sampled low): Well supplied externally. Pins

should be powered by 1.05 Suspend power supply. Decoupling capacitors are
required.
NOTE: External VR mode applies to Mobile Only.

Internally generated 1.05 V Deep Sx well power. This rail should not be
supplied externally.
NOTE: No decoupling capacitors should be used on this rail.

90 Datasheet

Signal Description

Table 2-26. Power and Ground Signals (Sheet 2 of 3)

Name Description

V5REF

V5REF_Sus

VccCore

Vcc3_3

VccASW

VccDMI

VccDIFFCLKN

VccRTC

VccIO

VccSus3_3

VccSusHDA Suspend supply for Intel

VccVRM 1.5 V/1.8 V supply for internal PLL and VRMs

VccDFTERM

VccADPLLA

VccADPLLB

VccADAC

Vss Grounds.

VccAClk

VccAPLLEXP

VccAPLLDMI2

Reference for 5 V tolerance on core well inputs. This power may be shut off in
S3, S4, S5, or G3 states.

Reference for 5 V tolerance on suspend well inputs. This power is not
expected to be shut off unless the system is unplugged.

1.05 V supply for core well logic. This power may be shut off in S3, S4, S5 or
G3 states.
NOTE: In external VR mode (INTVRMEN sampled low), the voltage level of

VccCore may be indeterminate while DcpSus (1.05 V Suspend Well
Power) supply ramps and prior to PWROK assertion.

3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4,
S5, or G3 states.

1.05 V supply for the Active Sleep Well. Provides power to the Intel
integrated LAN. This plane must be on in S0 and other times the Intel ME or
integrated LAN is used.

Power supply for DMI.

1.05 V or 1.0 V based on the processor V
respective processor documentation to find the appropriate voltage level.

1.05 V supply for Differential Clock Buffers. This power is supplied by the core
well.

3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power
is not exp ecte d to be sh ut off un les s the RTC battery is removed or completely
drained.
NOTE: Implementations should not attempt to clear CMOS by using a jumper

to pull VccRTC low. Clearing CMOS can be done by using a jumper on
RTCRST# or GPI.

1.05 V supply for core well I/O buffers. This power may be shut off in S3, S4,
S5, or G3 states.

3.3 V supply for suspend well I/O buffers. This power may be shut off in the
Deep Sx or G3 states.

®

HD Audio. This pin can be either 1.5 or 3.3 V.

1.8 V or 3.3 V supply for DF_TVS. This pin should be pulled up to 1.8 V or 3.3
V core.

1.05 V supply for Display PLL A Analog Power. This power is supplied by the
core well.

1.05 V supply for Display PLL B Analog Power. This power is supplied by the
core well.

3.3 V supply for Display DAC Analog Power. This power is supplied by the core
well.

1.05 V Analog power supply for internal clock PLL. This power is supplied by
the core well.
NOTE: This pin can be left as no connect

1.05 V Analog Power for DMI. This power is supplied by the core well.
NOTE: This pin can be left as no connect

1.05 V Analog Power for internal PLL. This power is supplied by core well.
NOTE: This pin can be left as no connect

voltage. Please refer to the

CCIO

®

ME and

Datasheet 91

Table 2-26. Power and Ground Signals (Sheet 3 of 3)

Name Description

1.05 V analog power supply for the FDI PLL. This power is supplied by core

VccAFDIPLL

VccAPLLSATA

VccALVDS

(Mobile Only)

VccTXLVDS

(Mobile Only)

V_PROC_IO

VccDSW3_3

VccSPI

VccSSC

VccClkDMI 1.05 V supply for DMI differential clock buffer

well.
NOTE: This pin can be left as no connect

1.05 V analog power supply for SATA PLL. This power is supplied by core well.
This rail requires an LC filter when power is supplied from an external VR.
NOTE: This pin can be left as no connect

3.3 V Analog power supply for LVDS, This power is supplied by core well.

1.8 V I/O power supply for LVDS. This power is supplied by core well.

Powered by the same supply as the processor I/O voltage. This supply is used
to drive the processor interface signals. Please refer to the respective
processor documentation to find the appropriate voltage level.

3.3 V supply for Deep Sx wells. If platform does not support Deep Sx then tie
to VccSus3_3.

3.3 V supply for SPI Controller Logic. This rail must be powered when VccASW
is powered.
NOTE: This rail can be optionally powered on 3.3 V Suspend power

(VccSus3_3) based on platform needs.

1.05 V supply for Integrated Clock Spread Modulators. This power is supplied
by core well.

Signal Description

92 Datasheet

Signal Description

2.27 Pin Straps

The following signals are used for static configuration. They are sampled at the rising
edge of PWROK to select configurations (except as noted), and then revert later to their
normal usage. To invoke the associated mode, the signal should be driven at least four
PCI clocks prior to the time it is sampled.

The PCH implements Soft Straps, which are used to configure specific functions within
the PCH and processor very early in the boot process before BIOS or SW intervention.
When Descriptor Mode is enabled, the PCH will read Soft Strap data out of the SPI
device prior to the deassertion of reset to both the Intel Management Engine and the
Host system. Please refer to Section 5.25.2 for information on Descriptor Mode

Table 2-27. Functional Strap Definitions (Sheet 1 of 4)

Signal Usage

SPKR No Reboot

INIT3_3V# Reserved

GNT3# / GPIO55

INTVRMEN

Top - B lo c k S w a p

Override

Integrated

1.05 V VRM

Enable /Disable

When

Sampled

Rising edge of

PWROK

Rising edge of

PWROK

Rising edge of

PWROK

Always

Comment

The signal has a weak internal pull-down. Note: the
internal pull-down is disabled after PLTRST# deasserts. If
the signal is sampled high, this indicates that the system
is strapped to the “No Reboot” mode (PCH will disable the
TCO Timer system reboot feature). The status of this
strap is readable using the NO REBOOT bit (Chipset
Config Registers: Offset 3410h:Bit 5).

This signal has a weak internal pull-up.

NOTES:

1. This signal should not be pulled low.

2. The internal pull-up is disabled after PLTRST#
deasserts.

The signal has a weak internal pull-up. If the signal is
sampled low, this indicates that the system is strapped to
the “top-block swap” mode.

The status of this strap is readable using the Top Swap bit
(Chipset Config Registers: Offset 3414h:Bit 0).

NOTES:

1. The internal pull-up is disabled after PLTRST#
deasserts.

2. Software will not be able to clear the Top Swap bit
until the system is rebooted without GNT3#/
GPIO55 being pulled down.

Integrated 1.05 V VRMs is enabled when high
External VR power source is used for DcpSus when

sampled low.

NOTES:

1. External VR powering option is for Mobile Only. Other

systems should not pull the strap low.

2. See VccCore signal description for behavior when

INTVRMEN is sampled low (external VR mode).

Datasheet 93

Table 2-27. Functional Strap Definitions (Sheet 2 of 4)

Bit11

(BBS1)

Bit 10

(BBS0)

Boot BIOS

Destination

01 Reserved
10 PCI
11 SPI
00 LPC

Signal Description

Signal Usage

Boot BIOS Strap

GNT1#/GPIO51

bit 1

BBS1

When

Sampled

Rising edge of

PWROK

Comment

This Signal has a weak internal pull-up.
This field determines the destination of accesses to the

BIOS memory range. Also controllable using Boot BIOS
Destination bit (Chipset Config Registers: Offset
3410h:Bit 11). This strap is used in conjunction with Boot
BIOS Destination Selection 0 strap.

NOTES:

1. If option 00 (LPC) is selected, BIOS may still be
placed on LPC, but all platforms are required to have
SPI flash connected directly to the PCH's SPI bus with
a valid descriptor in order to boot.

2. Booting to PCI is intended for debut/testing only.
Boot BIOS Destination Select to LPC/PCI by
functional strap or using Boot BIOS Destination Bit
will not affect SPI accesses initiated by Intel

®

ME or

Integrated GbE LAN.

3. PCI Boot BIOS destination is not supported on PCI
Interface-disabled SKUs.

4. The internal pull-up is disabled after PLTRST#
deasserts.

94 Datasheet

Signal Description

Bit11

(BBS1)

Bit 10

(BBS0)

Boot BIOS

Destination

01 Reserved
10 PCI
11 SPI
00 LPC

Table 2-27. Functional Strap Definitions (Sheet 3 of 4)

Signal Usage

Boot BIOS Strap

SATA1GP/GPIO19

GNT2#/ GPIO53

Work stat io n

HDA_SDO Reserved

bit 0

BBS0

ESI Strap

(Server/

Only)

When

Sampled

Rising edge of

PWROK

Rising edge of

PWROK

Rising edge of

PWROK

Comment

This Signal has a weak internal pull-up.
This field determines the destination of accesses to the

BIOS memory range. Also controllable using Boot BIOS
Destination bit (Chipset Config Registers: Offset
3410h:Bit 10). This strap is used in conjunction with Boot
BIOS Destination Selection 1 strap.

NOTES:

1. If option 00 (LPC) is selected, BIOS may still be
placed on LPC, but all platforms are required to have
SPI flash connected directly to the PCH's SPI bus with
a valid descriptor in order to boot.

2. Booting to PCI is intended for debut/testing only.
Boot BIOS Destination Select to LPC/PCI by
functional strap or using Boot BIOS Destination Bit
will not affect SPI accesses initiated by Intel ME or
Integrated GbE LAN.

3. PCI Boot BIOS destination is not supported on PCI
Interface-disabled SKUs.

4. The internal pull-up is disabled after PLTRST#
deasserts.

This Signal has a weak internal pull-up.
Tying this strap low configures DMI for ESI compatible

operation.

NOTES:

1. The internal pull-up is disabled after PLTRST#

deasserts.

2. ESI compatible mode is for server platforms only.

This signal should not be pulled low for desktop
and mobile.

Signal has a weak internal pull-down.
NOTE: The weak internal pull-down is disabled after

PLTRST# deasserts.

DF_TVS

GPIO28

Datasheet 95

DMI and FDI Tx/

Rx Termination

Voltage

On-Die PLL

Voltage

Regulator

Rising edge

of PWROK

Rising edge of

RSMRST# pin

This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after PLTRST#

deasserts.

This signal has a weak internal pull-up.
The On-Die PLL voltage regulator is enabled when

sampled high. When sampled low the On-Die PLL Voltage
Regulator is disabled.
NOTE: The internal pull-up is disabled after RSMRST#

deasserts.

Table 2-27. Functional Strap Definitions (Sheet 4 of 4)

Signal Description

Signal Usage

On-Die PLL

HDA_SYNC

GPIO15 Reserved

L_DDC_DATA LVDS Detected

SDVO_CTRLDATA Port B Detected

DDPC_CTRLDATA Port C Detected

DDPD_CTRLDATA Port D Detected

DSWVRMEN

SATA2GP/GPIO36 Reserved

SATA3GP/GPIO37 Reserved

Volta ge

Regulator

Voltage Select

Deep Sx Well

On-Die Voltage

Regulator Enable

When

Sampled

Rising edge of

RSMRST# pin

Rising edge of

RSMRST# pin

Rising edge of

PWROK

Rising edge of

PWROK

Rising edge of

PWROK

Rising edge of

PWROK

Always

Rising edge of

PWROK

Rising edge of

PWROK

Comment

This signal has a weak internal pull-down.
On Die PLL VR is supplied by 1.5 V from VccVRM when

sampled high, 1.8 V from VccVRM when sampled low.

This signal has a weak internal pull-down.
NOTE: A strong pull-up may be needed for GPIO

functionality.

When ‘1’- LVDS is detected; When ‘0’- LVDS is not
detected.
NOTE: This signal has a weak internal pull-down. The

internal pull-down is disabled after PLTRST#
deasserts.

When ‘1’- Port B is detected; When ‘0’- Port B is not
detected

This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after PLTRST#

deasserts.

When ‘1’- Port C is detected; When ‘0’- Port C is not
detected

This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after PLTRST#

deasserts.

When ‘1’- Port D is detected; When ‘0’- Port D is not
detected

This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after PLTRST#

deasserts.

If strap is sampled high, the Integrated Deep Sx Well
(DSW) On-Die VR mode is enabled.

This signal has a weak internal pull-down.

NOTES:

1. The internal pull-down is disabled after PLTRST#
deasserts.

2. This signal should not be pulled high when strap is
sampled.

This signal has a weak internal pull-down.

NOTES:

1. The internal pull-down is disabled after PLTRST#
deasserts.

2. This signal should not be pulled high when strap is
sampled.

NOTE: See Section 3.1 for full details on pull-up/pull-down resistors.

96 Datasheet

Signal Description

32.768 KHz
Xtal

10MΩ

VCCRTC

RTCX2

RTCX1

Vbatt

1uF

1 K Ω

VccDSW3_3
(see note 3)

C1 C2

R1

RTCRST#

1.0 uF

20 KΩ

0.1uF

SRTCRST#

20 KΩ

1.0 uF

Schottky Diodes

2.28 External RTC Circuitry

The PCH implements an internal oscillator circuit that is sensitive to step voltage
changes in VccRTC. Figure 2-2 shows an example schematic recommended to ensure
correct operation of the PCH RTC.

Figure 2-2. Example External RTC Circuit

NOTES:

1. The exact capacitor values for C1 and C2 must be based on the crystal maker
recommendations.

2. Reference designators are arbitrarily assigned.

3. For platforms not supporting Deep Sx, the VccDSW3_3 pins will be connected to the

VccSus3_3 pins.

4. Vbatt is voltage provided by the RTC battery (such as coin cell).

5. VccRTC, RTCX1, RTCX2, RTCRST#, and SRTCRST# are PCH pins.

6. VccRTC powers PCH RTC well.

7. RTCX1 is the input to the internal oscillator.

8. RTCX2 is the amplified feedback for the external crystal.

§ §

Datasheet 97

Signal Description

98 Datasheet

PCH Pin States

3 PCH Pin States

3.1 Integrated Pull-Ups and Pull-Downs

Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 1 of 2)

Signal Resistor Type Nominal Notes

CL_CLK1

CL_DATA1

CLKOUTFLEX[3:0]/GPIO[67:64] Pull-down 20K 1, 10

GPIO15 Pull-down 20K 3

HDA_SDIN[3:0] Pull-down 20K 2

HDA_SYNC, HDA_SDO Pull-down 20K 2, 5

GNT[3:1]#/GPIO[55,53,51] Pull-up 20K 3, 6, 7

GPIO8 Pull-up 20K 3, 12

LAD[3:0]# / FWH[3:0]# Pull-up 20K 3

LDRQ0#, LDRQ1# / GPIO23 Pull-up 20K 3

DF_TVS Pull-down 20k 8

PME# Pull-up 20K 3

INIT3_3V# Pull-up 20K 3

PWRBTN# Pull-up 20K 3

SPI_MOSI Pull-down 20K 3

SPI_MISO Pull-up 20K 3

SPKR Pull-down 20K 3, 9

TACH[7:0]/GPIO[71:68,7,6,1,17] Pull-up 20K

USB[13:0] [P,N] Pull-down 20K 4

DDP[D:C]_CRTLDATA Pull-down 20K 3, 9

SDVO_CTRLDATA,L_DDC_DATA Pull-down 20K 3, 9

SDVO_INTP, SDVO_INTN Pull-down 50 18

SDVO_TVCLKINP, SDVO_TVCLKINN Pull-down 50 18

SDVO_STALLP, SDVO_STALLN Pull-down 50 18

BATLOW#/GPIO72 Pull-up 20K 3

CLKOUT_PCI[4:0] Pull-down 20K 1, 10

GPIO27 Pull-up 20K 3, 14

JTAG_TDI, JTAG_TMS Pull-up 20K 1, 11

JTAG_TCK Pull-down 20K 1, 11

GPIO28 Pull-up 20K 3, 12

SATA[3:2]GP/GPIO[37:36] Pull-down 20K

Pull-up/Pull-

down

Pull-up/Pull-

down

32/100 8, 13

32/100 8, 13

3 (only on

TACH[7:0])

3, 9

Datasheet 99

Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 2 of 2)

Signal Resistor Type Nominal Notes

ACPRESENT/GPIO31 Pull-down 20K 3, 15

PCIECLKRQ5#/GPIO44 Pull-up 20K 1, 12

SST (Server/Workstation Only) Pull-down 10K 16

PCIECLKRQ7#/GPIO46 Pull-up 20K 1, 12

SATA1GP/GPIO19 Pull-up 20K 3, 9

SUSACK# Pull-up 20K 3

PECI Pull-down 350 17

NOTES:

1. Simulation data shows that these resistor values can range from 10 kΩ to 40 kΩ.

2. Simulation data shows that these resistor values can range from 9 kΩ to 50 kΩ.

3. Simulation data shows that these resistor values can range from 15 kΩ to 40 kΩ.

4. Simulation data shows that these resistor values can range from 14.25 kΩ to 24.8 kΩ.

5. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function.

6. The pull-up on this signal is not enabled when PCIRST# is high.

7. The pull-up on this signal is not enabled when PWROK is low.

8. Simulation data shows that these resistor values can range from 15 kΩ to 31 kΩ.

9. The pull-up or pull-down is not active when PLTRST# is NOT asserted.

10. The pull-down is enabled when PWROK is low.

11. External termination is also required on these signals for JTAG enabling.

12. Pull-up is disabled after RSMRST# is deasserted.

13. The Controller Link Clock and Data buffers use internal pull-up or pull-down resistors to
drive a logical 1 or 0.

14. Pull-up is enabled only in Deep Sx state.

15. Pull-down is enabled only in Deep Sx state.

16. When the interface is in BUS IDLE, the Internal Pull-down of 10 kΩ is enabled. In normal
transmission, a 400 Ω pull-down takes effect, the signal will be override to logic 1 with a
pull-up resistor (37 Ω) to VCC 1.5 V.

17. This is a 350-Ω normal pull-down, signal will be overridden to logic 1 with pull-up resistor
(31 Ω) to VCC 1.05 V.

18. Internal pull-down serves as Rx termination and is enabled after PLTRST# deasserts.

PCH Pin States

100 Datasheet