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life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoev er for conflicts or incompatibilities arising from future
changes to them.
®
The Intel
deviate from published specifications. Current characterized errata are available on request.
Intel processor numbers are not a measure of performance. Processor numb ers differentia te features withi n each processo r family,
not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor
numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to
represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not
necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.
Xeon® Processor 5600 Series may contain design defects or errors known as errata which may cause the product to
Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technologyenabled chipset, BIOS and operating system. Performance will va ry de pe ndi ng on the specific hardware and software y ou use. For
more information including details on which processors support HT Technology, see
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting
operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device
drivers and applications enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software
configurations. Consult with your system vendor for more information.
Intel® AES-NI requires a computer system with an AES-NI enabled processor, as well as non-Intel software to execute the
instructions in the correct sequence. AES-NI is available on select Intel® processors. For availability, consult your reseller or
system manufacturer. For more information, see http://software.intel.com/en-us/articles/intel-advanced-encryption-standardinstructions-aes-ni/
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor
(VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary
depending on hardware and software configur ations and may re quire a BIOS update. S oftware applicatio ns may not be compatible
with all operating systems. Please check with your application vendor.
Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost
Technology performance varies depending on hardware, software and overall system configuration. Check with your PC
manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see www.intel.com.
Enhanced Intel SpeedStep® Technology. See the http://processorfinder.intel.com or contact your Intel representative for more
information.
Intel, Xeon, Intel 64, Enhanced Intel SpeedStep Technology, and the Intel logo are trademarks of Intel Corporation in the U .S. and
other countries.
9-1PWM Fan Frequency Specifications For 4-Pin Active Thermal Solution......................181
9-2Fan Specifications For 4-Pin Active Thermal Solution.............................................181
9-3Fan Cable Connector P in Out for 4-Pin Active Thermal Solution ..............................181
8Intel® Xeon® Processor 5600 Series Datasheet Volume 1
Revision History
Revision
Number
-001• Initial ReleaseMarch 2010
-002• Added Section 1.5: Statement of VolatilityJune 2011
DescriptionDate
§
Intel® Xeon® Processor 5600 Series Datasheet Volume 19
10Intel® Xeon® Processor 5600 Series Datasheet Volume 1
Introduction
1Introduction
The Intel® Xeon® processor 5600 series is a server/workstation multi-core processor
based on 32 nm process technology. The processors feature two Intel® QuickPath
Interconnect point-to-point links capable of up to 6.4 GT/s, up to 12 MB of shared
cache, and an Integrated Memory Controller. The processors are optimized for
performance with the power efficiencies of a low-power microarchitecture to enable
smaller, quieter systems.
This datasheet provides DC and AC electrical specifications, signal integrity, differential
signaling specifications, pinout and signal definitions, package mechanical
specifications and thermal requirements, and additional features pertinent to
implementation and operation of the processor.
The Intel Xeon processor 5600 series features a range of Thermal Design Power (TDP)
envelopes from 40W TDP up to 130W TDP, and is segmented into multiple platforms:
• 2-Socket Frequency Optimized Server/Workstation Platforms support a 130 W
Thermal Design Power (TDP) SKU and up to 6 core support. These platforms
provide optimal overall performance and reliability, in addition to high-end graphics
support.
• 2-Socket Advanced Server/Workstation Platforms support a 95 W Thermal Design
Power (TDP) SKU. These platforms provide optimal overall performance featuring
up to 6 core support.
• 2-Socket Standard Server/Workstation Platforms support 80 W TDP processor
SKUs supporting up to 6 cores. These platforms provide optimal performance per
watt for rack-optimized platforms.
• Low Power Platforms implement 60 W TDP (up to 6 cores) and 40 W TDP (up to 4
cores) processor SKU’s. These processors are intended for dual-processor server
blades and embedded servers.
• 1-Socket Workstation Platforms support Intel® Xeon® Processor W3680. These
platforms enable a wide range of options for either the performance, power, or cost
sensitive customer.
• Platforms supporting Higher Case Temperature Low-Voltage Processors with 60 W
TDP (up to 6 cores) and 40 W TDP (up to 4 cores). The higher case temperatures
are intended to meet the short-term thermal profile requirements of NEBS Level 3.
These 2-socket processors are ideal for thermally-constrained form factors in
embedded servers, communications and storage markets. Specifications denoted
as LV-60W apply to the Intel® Xeon® Processor L5638. Specifications denoted as
LV-40W apply to the Intel® Xeon® Processor L5618.
®
Note:All references to “chipset” in this document pertain to the Intel
Intel® Xeon® Processor 5600 Series Datasheet Volume 111
®
5500 chipset.
Intel
Intel is committed to delivering processors for both server and workstation platforms
that maximize performance while meeting all Intel Quality and Reliability goals. The
product’s reliability assessment is based on a datasheet compliant system and
reference use condition. Intel utilizes a broad set of use condition assumptions (that is,
percentage of time in active vs. inactive operation, non-operating conditions, and the
number of power cycles per year) to ensure proper operation over the life of the
5520 chipset and the
product. The reference use condition differs between workstation and server processor
SKU’s. Implementing processors outside of reference use conditions may affect
reliability performance.
1.1Processor Features
Introduction
.
Table 1-1 provides an overview the Intel Xeon processor 5600 series feature set.
Table 1-1.Intel® Xeon® Processor 5600 Series Feature Set Overview
FeatureIntel® Xeon® Processor 5600 Series
Cache SizesInstruction Cache: 32 kB
12 MB Last-Level Cache shared among all cores
Data Transfer Rate (GT/s)Two full-width Intel® QuickPath Interconnect links;
Memory SupportIntegrated Memory Controller supports up to 3 channels of
DDR3 Memory Speed (MHz)800, 1066, 1333
Multi-Core SupportUp to 6 cores per processor (package)
®
Intel
Hyper-Threading Technology2 threads per core
Dual Processor SupportUp to 2 processor sockets per platform
Package1366-land FC-LGA
DDR3 or DDR3L memory, with up to 3 DIMMs per channel
Data Cache: 32 kB
256 kB Mid-Level Cache per core
Up to 6.40 GT/s in each direction
The Intel Xeon processor 5600 series support all the existing Streaming SIMD
Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and Streaming SIMD
Extensions 4 (SSE4) instructions. Additionally, Intel Xeon processor 5600 series
support Intel® AES New Instructions (Intel® AES-NI).
The Intel Xeon processor 5600 series support Direct Cache Access (DCA). DCA enables
supported I/O adapter to pre-fetch data from memory to the processor cache, thereby
avoiding cache misses and improving application response times.
These processors support a maximum physical address size of 40 bits. Also supported
is IA-32e paging which adds support for 1 GB (2
4 kB page size support for linear to physical address translation.
Finally, these processors support several advanced technologies including Execute
Disable Bit, Intel
Various new component and platform capabilities are available with the implementation
of Intel Xeon processor 5600 series.
New memory subsystem capabilities include Low Voltage DDR3 (DDR3L) DIMM support
for power optimization. The Intel Xeon processor 5600 series also add features to
provide improved manageability of memory channels. The DDR_THERM2# signal has
been added to support high-temperature DIMMs and their 2X refresh requirements.
12Intel
30
) page size in addition to 2 MB and
®
Xeon® Processor 5600 Series Datasheet Volume 1
Introduction
Intel Xeon processor 5600 series are based on a low-power microarchitecture that
supports operation within various C-states. Additionally, six execution cores and power
management coordination logic are optimized to manage C-state support at both the
execution core and package levels. An Intel Turbo Boost Technology optimization
feature is supported on these processors for improved energy efficiency.
®
Trusted Execution Technology (Intel® TXT) is also supported and represents a
Intel
set of enhanced hardware components designed to help protect sensitive information
from software-based attacks. Features include capabilities in the microprocessor,
chipset, I/O subsystems, and other platform components. When coupled with suitably
enabled operating systems and applications, Intel TXT helps protect the confidentiality
and integrity of data in the face of increasingly hostile security environment.
1.3Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low voltage level. For example, when RESET# is low,
a reset has been requested.
A ‘_N’ and ‘_P’ after a signal name refers to a differential pair.
Commonly used terms are explained here for clarification:
• 1366-land FC-LGA package — The Intel Xeon processor 5600 series is available
in a Flip-Chip Land Grid Array (FC-LGA) package, consisting of processor mounted
on a land grid array substrate with an integrated heat spreader (IHS).
• DDR3 — Double Data Rate 3 synchronous dynamic random access memory
(SDRAM) is the DDR memory standard, developed as the successor to DDR2
SDRAM.
• Enhanced Intel SpeedStep
Technology allows the operating system to reduce power consumption when
performance is not needed.
• Execute Disable Bit — Execute Disable allows memory to be marked as
executable or non-executable, when combined with a supporting operating system.
If code attempts to run in non-executable memory the processor raises an error to
the operating system. This feature can prevent some classes of viruses or worms
that exploit buffer over run vulnerabilities and can thus help improve the overall
security of the system. See the IntelDeveloper's Manuals for more detailed information.
• Functional Operation — Refers to the normal operating conditions in which all
processor specifications, including DC, AC, signal quality , m echanical, and thermal,
are satisfied.
• Integrated Memory Controller (IMC) — This is a memory controller that is
integrated in the processor die. Intel Xeon processor 5600 series can support up to
3 channels of DDR3, DDR3L memory , with up to 3 DIMMs per channel. Please refer
to Intel Plan of Record for supported DIMM types, densities and configurations.
®
• Intel
faster than the marked frequency if the part is operating under power,
temperature, and current specification limits of the Thermal Design Power (TDP).
This results in increased performance of both single and multi-threaded
applications.
• Intel
extensions to Intel processors and chipsets that, with appropriate software,
enhance the platform security capabilities.
Turbo Boost Technology - A way to automatically run the processor core
®
Trusted Execution Technology - A highly versatile set of hardware
®
Technology — Enhanced Intel SpeedStep®
®
64 and IA-32 Architecture Software
Intel® Xeon® Processor 5600 Series Datasheet Volume 113
Introduction
• Intel® QuickPath Interconnect (Intel® QPI) — A cache-coherent, links-based
interconnect specification for Intel processors, chipsets, and I/O bridge
components.
• Intel® 64 Architecture — An enhancement to Intel's IA-32 architec ture, allowing
the processor to execute operating systems and applications written to take
advantage of Intel
®
64.
• Intel® Virtualization Technology (Intel® VT) — A set of hardware
enhancements to Intel server and client platforms that can improve virtualization
solutions. VT provides a foundation for widely-deployed virtualization solutions and
enables more robust hardware assisted virtualization solution.
• Integrated Heat Spreader (IHS) — A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
• Jitter — Any timing variation of a transition edge or edges from the defined Unit
Interval (UI).
• LGA1366 Socket — The 1366-land FC-LGA package mates with the system board
through this surface mount, 1366-contact socket.
• Network Equipment Building System (NEBS) — The most common set of
environmental design guidelines applied to telecommunications equipment in the
United States.
• Serve r SKU — A processor Stock Keeping Unit (SKU) to be installed in either
server or workstation platforms. Electrical, power and thermal specifications for
these SKU’s are based on specific use condition assumptions. Server processors
may be further categorized as Frequency Optimized, Advanced, Standard and Low
Power SKUs. For further details on use condition assumptions, please refer to the
latest Product Release Qualification (PRQ) Report available via your Customer
Quality Engineer (CQE) contact.
• Storage Conditions — Refers to a non-operational state. The processor may be
installed in a platform, in a tray , or loose. Processors ma y be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased, or receive any clocks.
• Unit Interval (UI) — Signaling convention that is binary and unidirectional. In
this binary signaling, one bit is sent for every edge of the forwarded clock, whether
it be a rising edge or a falling edge. If a number of edges are collected at instances
, t2, tn,...., tk then the UI at instance “n” is defined as:
t
1
UI n = t n - t
• Workstation SKU — A processor SKU to be installed in workstation platforms
only. Electrical, power and thermal specifications for these processors have been
developed based on Intel’s reliability goals at a reference use condition. In addition,
the processor validation and production test conditions have been optimized based
on these conditions. Operating “Workstation” processors in a server environment or
other application, could impact reliability performance, which means Intel’s
reliability goals may not be met. For further details on use condition assumptions or
reliability performance, please refer to the latest Product Release Qualification
(PRQ) Report available via your Customer Quality Engineer (CQE) contact.
14Intel
n - 1
®
Xeon® Processor 5600 Series Datasheet Volume 1
Introduction
1.4References
Platform designers are strongly encouraged to maintain familiarity with the most up-todate revisions of processor and platform collateral.
Table 1-2.References
Advanced Configuration and Power Interface Specificationwww.acpi.info.
Compact Electronics Bay Specification: A Server System
Infrastructure (SSI) Specification for Value Servers and Workstations
Electronics Bay Specification for 2008 Servers and Workstation
Entry-Level Electronics-Bay Specifications: A Server System
Infrastructure (SSI) Specification for Entry Pedestal Servers and
Workstations
Thin Electronics Bay Specification: A Server System Infrastructure
(SSI) Specification for Rack-Optimized Servers
®
Intel
64 and IA-32 Architecture Software Developer's Manual
• Volume 1: Basic Architecture
• Volume 2A: Instruction Set Reference, A-M
• Volume 2B: Instruction Set Reference, N-Z
• Volume 3A: System Programming Guide, Part 1
• Volume 3B: Systems Programming Guide, Part 2
®
64 and IA-32 Architectures Optimization Reference Manual2489661
Intel
®
Intel
Xeon® Processor 5600 Series Datasheet, Volume 23233701
®
Intel
Xeon® Processor 5500/5600 Series Thermal/Mechanical
Design Guide
DocumentLocation / Document#1Notes
www.ssiforum.org
1
253665
253666
253667
253668
253669
3213231
Notes:
1.Document is available publicly at http://www.intel.com.
1.5Statement of Volatility
No Intel Xeon processor 5600 series product family processors retain any end user data
when powered down and/or when the parts are physically removed from the socket.
§
Intel® Xeon® Processor 5600 Series Datasheet Volume 115
Introduction
16Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
T
X
R
X
R
TT
R
TT
R
TT
R
TT
Signal
Signal
2Electrical Specifications
2.1Processor Signaling
The Intel Xeon processor 5600 series include 1366 lands, which utilize various signaling
technologies. Signals are grouped by electrical characteristics and buffer type into
various signal groups. These include Intel QuickPath Interconnect, DDR3 (Reference
Clock, Command, Control, and Data), Platform Environmental Control Interface (PECI),
Processor Sideband, System Reference Clock, Test Access Port (TAP), and Power/Other
signals. Refer to Table 2-5 for details.
2.1.1Intel® QuickPath Interconnect
The Intel Xeon processor 5600 series provide two Intel QuickPath Interconnect ports
for high speed serial transfer between other enabled components. Each port consists of
two uni-directional links (for transmit and receive). A differential signaling scheme is
utilized, which consists of opposite-polarity (D_P, D_N) signal pairs.
On-die termination (ODT) is included on the processor silicon and terminated to V
Intel chipsets also provide ODT, thus eliminating the need to terminate on the system
board. Figure 2-1 illustrates the active ODT.
Figure 2-1. Active ODT for a Differential Link Example
2.1.2DDR3 Signal Groups
The memory interface utilizes DDR3 technology, which consists of numerous signal
groups. These include: Reference Clocks, Command Signals, Control Signals, and Data
Signals. Each group consists of numerous signals, which may utilize various signaling
technologies. Please refer to Table 2-5 for further details.
2.1.3Platform Environmental Control Interface (PECI)
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and chipset components to external thermal monitoring devices. The
processor contains a Digital Thermal Sensor (DTS) that reports a relative die
temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Temperature sensors located throughout the die are implemented as analog-to-digital
converters calibrated at the factory. PECI provides an interface for external devices to
read processor temperature, perform processor manageability functions, and manage
processor interface tuning and diagnostics. Please refer to Section 7.3 for processor
specific implementation details for PECI.
SS
.
Intel® Xeon® Processor 5600 Series Datasheet Volume 117
Electrical Specifications
Minimum V
P
Maximum V
P
Minimum V
N
Maximum V
N
PECI High Range
PECI Low Range
Valid Input
Signal Range
Minimum
Hysteresis
V
TTD
PECI Ground
The PECI interface operates at a nominal voltage set by V
specifications shown in Table 2-13 is used with devices normally operating from a V
interface supply.
2.1.3.1Input Device Hysteresis
The PECI client and host input buffers must use a Schmitt-triggered input design for
improved noise immunity. Pl ease refer to Figure 2-2 and Table 2-13.
Figure 2-2. Input Device Hysteresis
. The set of DC electrical
TTD
TTD
2.1.4Processor Sideband Signals
Intel Xeon processor 5600 series include sideband signals that provide a variety of
functions. Details can be found in Table 2-5.
All Asynchronous Processor Sideband signals are required to be asserted/deasserted
for at least eight BCLKs in order for the processor to recognize the proper signal state.
See Table 2-18 and Table 2-26 for DC and AC specifications, respectively. Refer to
Section 3 for applicable signal integrity specifications.
2.1.5System Reference Clock
The processor core, processor uncore, Intel QuickPath Interconnect link, and DDR3
memory interface frequencies are generated from BCLK_DP and BCLK_DN signals.
There is no direct link between core frequency and Intel QuickPath Interconnect link
frequency (for example, no core frequency to Intel QuickPath Interconnect multiplier).
The processor maximum core frequency, Intel QuickPath Interconnect link frequency
and DDR memory frequency are set during manufacturing. It is possible to override the
processor core frequency setting using software. This permits operation at lower core
frequencies than the factory set maximum core frequency.
The processor core frequency is configured during reset by using values stored within
the device during manufacturing. The stored value sets the lowest core multiplier at
which the particular processor can operate. If higher speeds are desired, the
appropriate ratio can be configured via the IA32_PERF_CTL MSR (MSR 199h); Bits
[15:0].
18Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK_DP, BCLK_DN input, with exceptions
for spread spectrum clocking. DC specifications for the BCLK_DP, BCLK_DN inputs are
provided in Table 2-14 and AC specifications in Table 2-22. These specifications must
be met while also meeting the associated signal quality specifications outlined in
Section 3.
2.1.6Test Access Port (TAP) Signals
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Similar considerations must be made for
TCK, TDO, TMS, and TRST#. Two copies of each signal may be required with each
driving a different voltage level.
Processor TAP signal DC specifications can be found in Table 2-18. AC specifications are
located in Table 2-27.
Note:While TDI, TMS and TRST# do not include On-Die Termination (OD T), these signals are
weakly pulled-up via a 1-5 kΩ resistor to V
TT
.
Note:While TCK does not include ODT, this signal is weakly pulled-down via a
1-5 kΩ resistor to V
SS
.
2.1.7Power / Other Signals
Processors also include various other signals including power/ground, sense points, and
analog inputs. Details can be found in Table 2-5.
Table 2-1 outlines the required voltage supplies necessary to support Intel Xeon
processor 5600 series.
Table 2-1. Processor Power Supply Voltages
Power RailNominal VoltageNotes
V
CC
V
CCPLL
V
DDQ
V
, V
TTA
TTD
See Table 2-9;
Figure 2-3
1.80 V
1.50 V
1.35 V
See Table 2-11;
Figure 2-10
1
Each processor includes a dedicated VR11.1 regulator.
Each processor includes dedicated V
Each processor and DDR3 / DDR3L stack shares a dedicated voltage
regulator. It is expected that regulators will support both 1.50 and
1.35 V.
Each processor includes a dedicated VR11.0 regulator.
= V
+ V
V
TT
TTA
VID range is 1.025-1.2000 V; 20 mV offset (see Table 2-4); V
represents a typical voltage. V
31.5 mV offset from V
; P1V1_Vtt is VID[4:2] controlled,
TTD
TT_MIN
(typ).
TT
and PLL circuits.
CCPLL
and V
TT_MAX
loadlines represent a
TT
Note:
1.Refer to Table 2-8 for voltage and current specifications.
2.1.7.1Power and Ground Lands
For clean on-chip power distribution, processors include lands for all required voltage
supplies. These include:
Intel® Xeon® Processor 5600 Series Datasheet Volume 119
Electrical Specifications
•210 each VCC (271 ea. VSS) lands must be supplied with the voltage determined by
the VID[7:0] signals. Table 2-2 defines the voltage level associated with each core
VID pattern. Table 2-9 and Figure 2-3 represent V
•3 each V
lands, connected to a 1.8 V supply, power the Phase Lock Loop (PLL)
CCPLL
static and transient limits.
CC
clock generation circuitry. An on-die PLL filter solution is implemented within the
processor.
• 45 eac h V
(17 ea. VSS) lands, connected to a 1.50 / 1.35 V supply, provide
DDQ
power to the processor DDR3 interface. This supply also powers the DDR3 memory
subsystem.
•7 each V
(5 ea. VSS) and 26 ea. V
TTA
(17 ea. VSS) lands must be supplied with
TTD
the voltage determined by the VTT_VID[4:2] signals. Coupled with a 20 mV offset,
this corresponds to a VTT_VID pattern of ‘010xxx10’. Table 2-4 specifies the
voltage levels associated with each VTT
represent V
static and transient limits.
TT
VID pattern. Table 2-11 and Figure 2-10
_
All VCC, V
CCPLL, VDDQ, VTTA
, and V
lands must be connected to their respective
TTD
processor power planes, while all VSS lands must be connected to the system ground
plane.
2.1.7.2Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low and full power states. This may
cause voltages on power planes to sag below their minimum values if bulk decoupling is
not adequate. Larger bulk storage (C
), such as electrolytic capacitors, supply
BULK
current during longer lasting changes in current demand, for example coming out of an
idle condition. Similarly, they act as a storage well for current when entering an idle
condition from a running condition. Care must be taken in the baseboard design to
ensure that the voltages provided to the processor remain within the specifications
listed in Table 2-8. Failure to do so can result in timing violations or reduced lifetime of
the processor.
2.1.7.3Processor VCC Voltage Identification (VID) Signals
The voltage set by the VID signals is the maximum reference voltage regulator (VR)
output to be delivered to the processor VCC lands. VID signals are CMOS push/pull
outputs. Please refer to Table 2-18 for the DC specifications for these signals.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core frequency may have different default VID settings.
The processor uses eight voltage identification signals, VID[7:0], to support automatic
selection of power supply voltages. Table 2-2 specifies the voltage level corresponding
to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers
to a low voltage level. If the processor socket is empty (SKTOCC# pulled high), or the
voltage regulation circuit cannot supply the voltage that is requested, the voltage
regulator must disable itself.
The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (V
). This is represented by a DC shift in the
CC
loadline. It should be noted that a low-to-high or high-to-low voltage state change may
result in as many VID transitions as necessary to reach the target core voltage.
T ransitions abov e the maximum specified VID are not permitted. Table 2-8 includes VID
step sizes and DC shift ranges. Minimum and maximum voltages must be maintained
as shown in Table 2-9.
20Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
The VRM or EVRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in
Table 2-18, while AC specifications are included in Table 2-28.
Power source characteristics must be guaranteed to be stable whenever the supply to
the voltage regulator is stable.
Table 2-2.Voltage Identification Definition (Sheet 1 of 5)
1.When the “11111111” VID pattern is observed, or when the SKTOCC# pin is pulled high, the voltage
regulator output should be disabled.
2.The VID range includes VID transitions that may be initiated by thermal events, Extended HALT state
transitions (see Section 8.2), higher C-States (see Section 8.2) or Enhanced Intel SpeedStep
transitions (see Section 8.5). The Extended HALT state must be enabled for the processor to
remain within its specifications
3.Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a
specific VID off code is received, the VRM/EVRD must turn off its output (the output should go to high
impedance) within 500 ms and latch off until power is cycled.
CC_MAX
®
Technology
2.1.7.3.1Power-On Configuration (POC) Logic
VID[7:0] signals also serve a second function. During power-up, Power-On
Configuration POC[7:0] logic levels are MUX’ed onto these signals via 1-5 kΩ pull-up or
pull down resistors located on the baseboard. These values provide voltage regulator
keying (VID[7]), inform the processor of the platforms power delivery capabilities
(MSID[2:0]), and program the gain applied to the ISENSE input (CSC[2:0]). Table 2-3
maps VID signals to the corresponding POC functionality.
Table 2-3. Power-On Configuration (POC[7:0]) Decode (Sheet 1 of 2)
FunctionBitsPOC SettingsDescription
VR_KeyVID[7]0b for VR11.1Electronic safety key
SpareVID[6]0b (default)Reserved for future use
Intel® Xeon® Processor 5600 Series Datasheet Volume 125
distinguishing VR11.1
Table 2-3. Power-On Configuration (POC[7:0]) Decode (Sheet 2 of 2)
FunctionBitsPOC SettingsDescription
CSC[2:0]VID[5:3]-000b
-001b
-010b
-011b
-100b
-101b
-111b
MSID[2:0]VID[2:0]-001b
-011b
-100b
-101b
-110b
Note:
1.This setting is defined for future use; no Intel Xeon processor 5600 series SKU is defined with ICC_MAX=40
A.
2.In general, set PWM IMON slope to 900 mV = IMAX, where IMAX = ICCMAX. For the 130 W SKU, set IMON
slope to 900 mV= 180 A. All other SKUs must match the values shown above. Please consult the PWM
datasheet for the IMON slope setting.
Feature Disabled
ICC_MAX = 40 A
40 W TDP / ICC_MAX = 50 A
60 W TDP / ICC_MAX = 80 A
80W TDP / ICC_MAX = 100 A
95W TDP / ICC_MAX = 120 A
130W TDP / ICC_MAX =
150A
40 W TDP / 50 A ICC_MAX
60 W TDP / 80 A ICC_MAX
80 W TDP / 100 A ICC_MAX
95 W TDP / 120 A ICC_MAX
130 W TDP / 150 A ICC_MAX
1
2
Current Sensor Configuration
(CSC) programs the gain
applied to the ISENSE A/D
output. ISENSE data is then
used to dynamically calculate
current and power.
MSID[2:0] signals are provided
to indicate the Market Segment
for the processor and may be
used for future processor
compatibility or keying. See
Section 8.1 for platform timing
requirements of the MSID[2:0]
signals.
Electrical Specifications
Some POC signals include specific timing requirements. Please refer to Section 8.1 for
further details.
2.1.7.4Processor VTT Voltage Identification (VTT_VID) Signals
The voltage set by the VTT_VID signals is the typical reference voltage regulator (VR)
output to be delivered to the processor V
regulator will supply all V
TTA
and V
TTD
outputs. Please refer to Table 2-18 for the DC specifications for these signals.
Individual processor VTT_VID values may be calibrated during manufacturing such that
two devices at the same core frequency may have different default VTT_VID settings.
The processor utilizes three voltage identification signals to support automatic selection
of power supply voltages. These correspond to VTT_VID[4:2]. The V
delivered to the processor lands must also encompass a 20 mV offset (See Table 2-4;
V
) above the voltage level corresponding to the state of the VTT_VID[7:0] signals
TT_TYP
(See Table 2-4; VR 11.0 Voltage). Table 2-11 and Figure 2-10 provide the resulting
static and transient tolerances. Please note that the maximum and minimum electrical
loadlines are defined by a 31.5 mV tolerance band above and below V
Power source characteristics must be guaranteed to be stable whenever the supply to
the voltage regulator is stable.
Table 2-4.VTT Voltage Identification Definition (Sheet 1 of 2)
VID7 VID6VID5VID4VID3 VID2 VID1 VID0
010
010
010
010
010
000101.200 V1.220 V
001101.175 V1.195 V
010101.150 V1.170 V
011101.125 V1.145 V
100101.100 V1.120 V
TTA
and V
lands. It is expected that one
TTD
lands. VTT_VID signals are CMOS push/pull
VR 11.0
Voltage
voltage level
TT
valu es.
TT_TYP
V
TT_TYP
(Voltage + Offset)
26Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
Table 2-4.VTT Voltage Identification Definition (Sheet 2 of 2)
VID7 VID6VID5VID4VID3 VID2 VID1 VID0
010101101.075 V1.095 V
010
010
110101.050 V1.070 V
111101.025 V1.045 V
2.1.8Reserved or Unused Signals
All Reserved (RSVD) signals must remain unconnected. Connection of these signals to
, V
, V
, V
V
CC
TTA
TTD
component malfunction or incompatibility with future processors. See Section 5 for the
land listing and the location of all Reserved signals.
For reliable operation, connect unused inputs or bidirectional signals to an appropriate
signal level. Unused Intel QuickPath Interconnect input and output pins can be left
floating. Unused active high inputs should be connected through a resistor to ground
). Unused outputs can be left unconnected; however, this may interfere with some
(V
SS
TAP functions, complicate debug probing, and prev ent boundary scan testing. A resistor
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, including a resistor will also allow for system testability.
Resistor values should be within ± 20% of the impedance of the baseboard trace,
unless otherwise noted in the appropriate platform design guidelines.
TAP signals do not include on-die termination, however they may include resistors on
package (refer to Section 2.1.6 for details). Inputs and utilized outputs must be
terminated on the baseboard. Unused outputs may be terminated on the baseboard or
left unconnected. Note that leaving unused outputs unterminated may interfere with
some TAP functions, complicate debug probing, and prevent boundary scan testing.
, VSS, or any other signal (including each other) can result in
DDQ
VR 11.0
Voltage
V
TT_TYP
(Voltage + Offset)
2.2Signal Group Summary
Signals are aligned in Table 2-5 by buffer type and characteristics. “Buffer Type”
denotes the applicable signaling technology and specifications.
Table 2-5.Signal Groups (Sheet 1 of 2)
Signal GroupBuffer TypeSignals
Intel® QuickPath Interconnect Signals
DifferentialIntel®
DifferentialIntel®
Single endedAnalog InputQPI[0/1]_COMP
DDR3 Reference Clocks
DifferentialOutputDDR{0/1/2}_CLK_[P/N][3:0]
DDR3 Command Signals
Single endedCMOS OutputDDR{0/1/2}_RAS#, DDR{0/1/2}_CAS#,
Single endedAsynchronous InputDDR{0/1/2}_PAR_ERR#[2:0],
Platform Environmental Control Interface (PECI)
Single endedAsynchronous Input/OutputPECI
Processor Sideband Signals
Single endedGTL Input/OutputBPM#[7:0], CAT_ERR#
Single endedAsynchronous InputPECI_ID#
Single endedAsynchronous GTL OutputPRDY#, THERMTRIP#
Single endedAsynchronous GTL InputPREQ#
Single endedAsynchronous GTL Input/OutputPROCHOT#
Single endedAsynchronous CMOS OutputPSI#, TAPPWRGOOD
Single endedCMOS OutputVID[7:6],
PWRGOOD Signal
Single endedAsynchronous InputVCCPWRGOOD, VDDPWRGOOD, VTTPWRGOOD
Reset Signal
Single endedReset InputRESET#
System Reference Clock
DifferentialInputBCLK_DP, BCLK_DN
Test Access Port (TAP) Signals
DifferentialCMOS OutputBCLK_ITP_DP, BCLK_ITP_DN
Single endedInputTCK, TDI, TMS, TRST#
Single endedGTL OutputTDO
Power/Other Signals
2
Power / GroundV
Analog InputCOMP0, ISENSE
Sense PointsVCCSENSE, VSSSENSE, VSS_SENSE_VTTD,
1.Unless otherwise specified, signals have ODT in the package with a 50 Ω pull-down to V
2.Unless otherwise specified, all DDR3 signals are terminated to V
3.DDR{0/1/2}_PAR_ERR#[2:0] are terminated to V
4.TCK does not include ODT, this signal is weakly pulled-down via a 1-5 kΩ resistor to VSS.
5.TDI, TMS, TRST# do not include ODT, these signals are weakly pulled-up via 1-5kΩ resistor to V
6.BPM[7:0]# and PREQ# signals have ODT in package with 35 Ω pull-ups to V
7.PECI_ID# has ODT in package with a 1-5 kΩ pull-up to VTT.
8.TAPPWRGOOD has ODT in package with a 1-2.5 kΩ pull-up to V
9.VCCPWRGOOD, VDDPWRGOOD, and VTTPWRGOOD have ODT in package with a 5-20 kΩ pull-down to V
DDQ.
DDQ
TT
/2.
TT.
.
.
SS
.
TT
2.3Mixing Processors
Intel supports dual-processor (DP) configurations consisting of processors:
• from the same power optimization segment.
• that support the same maximum Intel QuickPath Interconnect and DDR3 memory
speeds.
• that share symmetry across physical packages with respect to the number of
logical processor per package, number of cores per package, number of Intel
QuickPath Interconnect interfaces, and cache topology.
• that have identical Extended Family, Extended Model, Processor Type, Family Code
and Model Number as indicated by the Function 1 of the CPUID instruction.
Note:Processors must operate with the same Intel QuickPath Interconnect, DDR3 memory
and core frequency.
While Intel does nothing to prevent processors from operating together, some
combinations may not be supported due to limited validation, which may result in
uncharacterized errata. Coupling this fact with the large number of Intel Xeon
processor 5600 series processor attributes, the following population rules and stepping
matrix have been developed to clearly define supported configurations.
• Processors must be of the same power-optimization segment. This insures
processors include the same maximum Intel QuickPath Interconnect and DDR3
operating speeds and cache sizes.
• Processors must operate at the same core frequency. Note, processors within the
same power-optimization segment supporting different maximum core frequencies
can be operated within a system. However, both must operate at the highest
frequency rating commonly supported. Mixing components operating at different
internal clock frequencies is not supported and will not be validated by Intel.
.
SS
Intel® Xeon® Processor 5600 Series Datasheet Volume 129
Electrical Specifications
• Processors must share symmetry across physical packages with respect to the
number of logical processors per package, number of cores per package (but not
necessarily the same subset of cores within the packages), number of Intel
QuickPath Interconnect interfaces and cache topology.
• Mixing steppings is only supported with processors that have identical Extended
Family, Extended Model, Processor Type, Family Code and Model Number as
indicated by the Function 1 of the CPUID instruction. Mixing processors of different
steppings, but the same mode (as per CPUID instruction) is supported. Details
®
regarding the CPUID instruction are provide in the Intel
• After AND ’ing the fe ature flag and extended feature flags from the installed
processors, any processor whose set of feature flags exactly matches the AND’ed
feature flags can be selected by the BIOS as the BSP. If no processor exactly
matches the AND’ed feature flag values, then the processor with the numerically
lower CPUID should be selected as the BSP.
• Intel requires that the proper microcode update be loaded on each processor
operating within the system. Any processor that does not have the proper
microcode update loaded is considered by Intel to be operating out-of-specification.
• Customers are fully responsible for the v alidation of their system configurations
Note:Processors within a system must operate at the same frequency per bits [15:8] of the
FLEX_RATIO MSR (Address: 194h); however this does not apply to frequency
transitions initiated due to thermal events, Extended HALT, Enhanced Intel SpeedStep
Technology transitions signal (See Section 8).
2.4Flexible Motherboard Guidelines (FMB)
The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the
processor will have over certain time periods. The values are only estimates and actual
specifications for future processors may differ. Processors may or may not have
specifications equal to the FMB value in the foreseeable future. System designers
should meet the FMB values to ensure their systems will be compatible with future
processors.
2.5Absolute Maximum and Minimum Ratings
Table 2-7 specifies absolute maximum and minimum ratings only, which lie outside the
functional limits of the processor. Only within specified operation limits, can
functionality and long-term reliability be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function or its reliability will be
severely degraded.
30Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.
Table 2-7.Processor Absolute Minimum and Maximum Ratin gs
SymbolParameterMinMaxUnit Notes
V
V
CCPLL
V
V
V
T
CASE
T
STORAGE
V
ISENSE
Notes:
1.For functional operation, all processor electri cal, signal quality, mechanical and thermal specifications must
2.Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Section 3.
3.V
4.5% tolerance
5.Storage temperature is applicable to storage conditions only. In this scenario, the processor must not
6.This rating applies to the processor and does not include any tray or packaging.
7.Failure to adhere to this specification can affect the long-term reliability of the processor
Processor core voltage with respect to V
CC
Processor PLL voltage with respect to V
Processor I/O supply voltage for DDR3
DDQ
with respect to V
Processor uncore analog voltage with
TTA
respect to V
Processor uncore digital voltage with
TTD
respect to V
Processor case temperatureSee
Storage temperatureSee
Analog input voltage with respect to VSS
for sensing core current consumption
be satisfied.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
and V
TTA
receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect
the long-term reliability of the device. For functional operation, please refer to the processor case
temperature specification.
should be derived from the same voltage regulator (VR).
TTD
SS
SS
SS
-0.31.4V
SS
-0.32.0V4
SS
-0.31.8V4
-0.31.4V3
-0.31.4V3
Section 7
Section 7.4
-0.31.15V
Section 7
Section 7.4
See
See
1,2
°C
°C5,6,7
2.6Processor DC Specifications
DC specifications are defined at the processor pads, unless otherwise noted.
DC specifications are only valid while meeting specifications for case temperature
(T
specified in Section 7, “Thermal Specifications”), clock frequency, and input
CASE
voltages. Care should be taken to read all notes associated with each specification.
Table 2-8.Voltage and Current Specifications (Sheet 1 of 3)
SymbolParameter
VIDVCC VID Range-0.7501.350V2,3
V
CC
V
VID_STEP
V
CCPLL
V
DDQ
Intel® Xeon® Processor 5600 Series Datasheet Volume 131
Core Voltage
(Launch - FMB)
VID step size during a
transition
PLL Voltage
(DC + AC specification)
I/O Voltage for DDR3
(DC + AC specification)
Voltage
Plane
V
CC
-± 6.250mV9
V
CCPLL
V
DDQ
MinTypMaxUnitNotes
V
=VID-(ICC * 0.8 mΩ)
CCMAX
=(VID-VRTOL)-(ICC*0.8 mΩ)
V
CCMIN
See Table 2-9 and Figure 2-3
0.95*V
(Typ)
0.95*V
(Typ)
CCPLL
DDQ
1.8001.05*V
1.5001.05*V
(Typ)
(Typ)
CCPLL
DDQ
V3,4,6,7,11
V10
V10
1
Table 2-8.Voltage and Current Specifications (Sheet 2 of 3)
Electrical Specifications
SymbolParameter
V
DDQ
VTT_VIDV
V
I/O Voltage for DDR3L
(DC + AC specification)
VID Range-1.0451.220V2,3
TT
Uncore Voltage
TT
(Launch - FMB)
I
CC_MAX
I
CCPLL_MAX
I
DDQ_MAX
I
TT_MAX
Max. Processor Current:
Frequency Optimized
Server/Workstation
(TDP = 130 W)
DDR3 System Memory
Interface Supply
Current in Standby
State
Voltage
Plane
V
CC
V
CCPLL
V
DDQ
V
TTA
V
TTD
V
CC
V
CCPLL
V
DDQ
V
TTA
V
TTD
V
CC
V
CCPLL
V
DDQ
V
TTA
V
TTD
V
CC
V
CCPLL
V
DDQ
V
TTA
V
TTD
V
CC
V
CCPLL
V
DDQ
V
TTA
V
TTD
V
DDQ
MinTypMaxUnitNotes
110
1.1
9
6
22
101
1.1
9
6
22
70
1.1
9
6
22
60
1.1
9
6
20
40
1.1
9
6
20
A
11,12
A
A
A
A
A
11,12
A
A
A
A
A
11,12
A
A
A
A
A
11,12
A
A
A
A
A
11,12
A
A
A
A
1A13,14
1
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processors.
2. Individual processor VID and/or VTT_VID values may be calibrated during manufacturing such that two
devices at the same speed may have different settings.
3. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required.
4. The V
5. The V
6. Refer to Table 2-9 and corresponding Figure 2-3. The processor should not be subjected to any static V
7. Minimu m V
8. Refer to Table 2-11 and corresponding Figure 2-10. The processor should not be subjected to any static V
9. This specification represents the V
10.Baseboard b andwidth is limited to 20 MHz.
11.FMB is the flexible motherboard guidelines. See Section 2.4 for FMB details.
12.ICC_TDC (Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of
voltage specification requirements are measured across vias on the platform for the VCCSENSE and
CC
VSSSENSE pins close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe
capacitance, and 1 MΩ minimum impedance . The maximum length of ground wire on the probe should be
less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
voltage specification requirements are measured across vias on the platform for the VTTD_SENSE
TT
and VSS_SENSE_VTTD lands close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum
probe capacitance, and 1 MΩ minimum imped ance. The max imum length o f ground wire on the probe should
be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
level that exceeds the V
can shorten processor lifetime.
Table 7-1. I
drawing I
processor current draw over various time durations.
and maximum ICC are specified at the maximum processor case temperature (T
CC
is specified at the relative V
CC_MAX
for up to 10 ms. Refer to Figure 2-5 through Figure 2-8 for further details on the average
CC_MAX
level that exceeds the V
can shorten processor lifetime.
requirements for VID transitions are included in Figure 2-29.
drawing indefinitely and should be used for the voltage regulator temperature assessment. The voltage
regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the
processor of a thermal excursion.
associated with any particular current. Failure to adhere to this specification
CC_MAX
point on the VCC load line. The processor is capable of
CC_MAX
associated with any particular current. Failure to adhere to this specification
TT_MAX
reduction due to each VID transition. See Section 2.1.7.3. AC timing
CC
CASE
CC
) shown in
TT
Intel® Xeon® Processor 5600 Series Datasheet Volume 133
2.This table is intended to aid in reading discrete points on Figure 2-3.
3.The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. V oltag e
regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and
VSS_SENSE lands.
CC_MIN
and V
4.Processor core current (I
loadlines represent static and transient limits. Please see Section 2.6.1 for VCC
CC_MAX
) ranges are valid up to I
CC
CC_MAX
34Intel
of the processor SKU as defined in Table 2-8.
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
VID - 0.000
VID - 0.020
VID - 0.040
VID - 0.060
VID - 0.080
VID - 0.100
VID - 0.120
VID - 0.140
VID - 0.160
VID - 0.180
0102030405060708090100110120130140150
Icc [A]
Vcc [V]
Figure 2-3. VCC Static and Transient Tolerance Loadlines
Notes:
1.The V
overshoot specifications.
2.Refer to Table 2-9 for V
3.The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and
VSS_SENSE lands.
4.Processor core current (I
CC_MIN
and V
loadlines represent static and transient limits. Please see Section 2.6.1 for V
CC_MAX
Static and Transient Tolerance.
CC
) ranges are valid up to I
CC
CC_MAX
1,2,3,4
CC
of the processor SKU as defined in Table 2-8.
2.6.1VCC Overshoot Specifications
The processor can tolerate short transient overshoot events where VCC exceeds the VID
voltage when transitioning from a high-to-low current load condition. This overshoot
cannot exceed VID + V
OS_MAX
(V
OS_MAX
VID). These specifications apply to the processor die voltage as measured across the
VCC_SENSE and VSS_SENSE lands.
Table 2-10. VCC Overshoot Specifications
SymbolParameterMinMaxUnitsFigureNotes
V
OS_MAX
T
OS_MAX
Intel® Xeon® Processor 5600 Series Datasheet Volume 135
Magnitude of VCC overshoot above VID-50mV2-4
Time duration of VCC overshoot above VID-25µs2-4
is the maximum allowable overshoot above
Electrical Specifications
Example Overshoot Waveform
0510152025
Time [us]
Voltage [V]
VID - 0.000
VID + 0.050
V
OS
T
OS
TOS: Overshoot time above VID
OS
: Overshoot above VID
Figure 2-4. V
Overshoot Example Waveform
CC
Notes:
1.V
2.T
is the measured overshoot voltage.
OS
is the measured time duration above VID.
OS
V
2.6.2Die Voltage Validation
Core voltage (VCC) overshoot events at the processor must meet the specifications in
Table 2-10 when measured across the VCC_ SENSE and VSS_SENSE lands. Overshoot
events that are < 10 ns in duration may be ignored. These measurements of processor
die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope.
36Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
Notes:
Notes:
105
110
115
120
125
130
135
140
145
150
155
0.010.11101001000
Time Du ra tio n , (s )
Sustained Current (A)
95.0
100.0
105.0
110.0
115.0
120.0
125.0
0.010.11101001000
Time Duration, (s)
Sustained Current (A)
Figure 2-5. Load Current Versus Time (Frequency Optimized Server/Workstation)
1.Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than
2.Not 100% tested. Specified by design characterization.
I
CC_TDC
.
1,2
Figure 2-6. Load Current Versus Time (Advanced Server/Workstation)
Intel® Xeon® Processor 5600 Series Datasheet Volume 137
1.Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than
2.Not 100% tested. Specified by design characterization.
.
I
CC_TDC
1,2
Electrical Specifications
Notes:
Notes:
65
70
75
80
85
90
95
100
105
0.010.11101001000
Time Duration, (s)
Sustained Current (A)
45
50
55
60
65
70
75
80
85
0.010.11101001000
Time Duration , (s )
Sustained Current (A)
Figure 2-7. Load Current Versus Time (Standard Server/Workstation)
1.Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than
2.Not 100% tested. Specified by design characterization.
I
CC_TDC
.
1,2
Figure 2-8. Load Current Versus Time (Low Power & LV-60W)
1.Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than
2.Not 100% tested. Specified by design characterization.
I
CC_TDC
.
1,2
38Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
Notes:
35
40
45
50
55
0.010.11101001000
Time Duration, T
VR_AVE
(s)
Figure 2-9. Load Current Versus Time (Low Power & LV-40W)
Sust ai ned Cu r re nt ( A )
1.Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than
2.Not 100% tested. Specified by design characterization.
I
CC_TDC
.
1,2
Table 2-11. VTT Static and Transient Tolerance (Sheet 1 of 2)
2.This table is intended to aid in reading discrete points on Figure 2-10.
3.The V
offset from V
4.The loadlines specify voltage limits at the die measured at the VTTD_SENSE and VSS_SENSE_VTTD lands.
Voltage regulation feedback for regulator circuits must also be taken from VTTD_SENSE and
VSS_SENSE_VTTD lands.
TT_MIN
and V
TT_TYP
TT_MAX
.
(V)V
TT_Max
TTA
and I
(V)V
TT_Typ
.
TTD
loadlines represent static and transient limits. Each is char acterized by a ±31.5 mV
Electrical Specifications
(V)Notes
TT_Min
1,2,3,4
Figure 2-10. VTT Static and Transient Tolerance Loadlines
40Intel
Notes:
1.The V
2.Refer to Table 2-4 for processor VTT_VID information.
3.Refer to Table 2-11 for V
TT_MIN
offset from V
and V
TT_TYP
loadlines represent static and transient limits. Each is char acterized by a ±31.5 mV
TT_MAX
.
Static and Transient Tolerance.
TT
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
Table 2-12. DDR3 and DDR3L Signal Group DC Specifications
SymbolParameterMinTypMaxUnitsNotes
V
V
V
V
R
R
R
R
R
Data ODT
ParErr ODT
I
DDR_COMP0 COMP Resistance99100101Ω8
DDR_COMP1 COMP Resistance24.6524.925.15Ω8
DDR_COMP2 COMP Resistance128.7130131.3Ω8
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
is the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
2.V
IL
is the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
3.V
IH
and VOH may experience excursions above V
4.V
IH
signal quality specifications. Refer to Section 3.
5.This is the pull down driver resistance.
6.R
VTT_TERM
DIMM datasheet.
7.The minimum and maximum values for these signals are programmable by BIOS to one of the pairs.
8.COMP resistance must be provided on the system board with 1% resistors.
is the termination on the DIMM and not controlled by the processor. Please refer to the applicable
. However, input signal drivers must comply with the
DDQ
Table 2-13. PECI Signal DC Electrical Limits (Sheet 1 of 2)
SymbolDefinition and ConditionsMinMaxUnitsNotes
V
In
V
Hysteresis
V
N
V
P
R
Pullup
I
Leak+
I
Leak-
C
Bus
Input Voltage Range-0.150V
Hysteresis0.100 * V
Negative-edge threshold voltage0.275 * V
Positive-edge threshold voltage0.550 * V
Pullup Resistance
= 0.75 * V
(V
OH
High impedance state leakage to
V
(V
leak
= VOL)
TTD
TTD
)
High impedance leakage to GND
(V
= VOH)
leak
N/A50Ω
N/A50µA3
N/A25µA3
Bus capacitance per nodeN/A10pF4,5
TTD
TTD
TTD
+ 0.150V
TTD
0.500 * V
0.725 * V
TTD
TTD
1
V
V2,6
V2,6
Intel® Xeon® Processor 5600 Series Datasheet Volume 141
Table 2-13. PECI Signal DC Electrical Limits (Sheet 2 of 2)
SymbolDefinition and ConditionsMinMaxUnitsNotes
V
Noise
Signal noise immunity above
300 MHz
0.100 * V
TTD
Electrical Specifications
N/AV
p-p
1
Note:
1.V
2.It is expected that the PECI driver will take into account, the variance in the receiver input thresholds and
3.The leakage specification applies to powered devices on the PECI bus.
4.One node is counted for each client and one node for the s ystem host. Extended tr ace lengths might appear
5.Excessive capacitive loading on the PECI line may slow down the signal rise/f all times and consequently
6.Please refer to Figure 2-2 for further information.
supplies the PECI interface. PECI behavior does not affect V
TTD
consequently, be able to drive its output within safe limits (-0.150 V to 0.275*V
0.725*V
TTD
to V
+0.150 for the high level).
TTD
as additional nodes.
limit the maximum bit rate at which the interface can operate.
Table 2-14. System Reference Clock DC Specifications
SymbolParameterMinMax
V
BCLK_diff_ih
V
BCLK_diff_il
(abs)
V
cross
V
(rel)
cross
ΔV
cross
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.Crossing Voltage is d efined as the instantaneous voltage v alue when the rising edge of BCLK_DN is equal to
the falling edge of BCLK_DP.
3.V
Havg
4.The crossing point must meet the absolute and relative crossing point specifications simultaneously.
5.V
Havg
6.V
CROSS
Differential Input High
Voltage
Differential Input Low
Voltage
Absolute
Crossing Point
Relative
Crossing Point
Range of
Crossing Points
0.150N/AV
N/A-0.150V
0.2500.550V
0.250 +
0.5*(VH
- 0.700)
avg
N/A0.140V2-206
is the statistical average of the VH measured by the oscilloscope.
can be measured directly using “Vtop” on Agilent* and “High” on Tektronix* oscilloscopes.
is defined as the total variation of all crossing voltages as defined in Note 2.
0.5*(VH
min/max specifications.
TTD
TTD
UnitFigureNotes
0.550 +
- 0.700)
avg
V2-163,4,5
for the low level and
2-16
2-19
2, 4
1
Table 2-15. RESET# Signal DC Specifications
SymbolParameterMinTypMaxUnitsNotes
V
IL
V
IH
R
ON
I
LI
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.The V
3.For V
4.V
IH
specifications in Section 3.
42Intel
Input Low Voltage
Input High Voltage
Buffer On Resistance
0.7 * V
TTA
1018
Input Leakage Current± 200μA
referred to in these specifications refers to instantaneous V
TTA
between 0 V and V
IN
may experience excursions above VTT. However, input signal drivers must comply with the signal quality
. Measured when the driver is tri-stated.
TTA
0.6 * V
TTA
V2
V2,4
Ω
3
.
TTA
®
Xeon® Processor 5600 Series Datasheet Volume 1
1
Electrical Specifications
Table 2-16. TAP Signal Group DC Specifications
SymbolParameterMinTypMaxUnitsNotes
1
V
IL
V
IH
V
OL
V
OH
R
ON
I
LI
Input Low Voltage
Input High Voltage
0.60 * V
TTA
Input Low Voltage
Input High Voltage
Buffer On Resistance
V
TTA
1018Ω
Input Leakage Current± 200μA
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.The V
3.For V
4.V
referred to in these specifications refers to instantaneous V
TTA
between 0 V and V
IN
and VOH may experience excursions above VTT. However, input signal drivers must comply with the
IH
signal quality specifications in Section 3.
. Measured when the driver is tri-stated.
TTA
Table 2-17. xxxPWRGOOD Signal Group DC Specifications
SymbolParameterMinTypMaxUnitsNotes
V
IL
V
IL
V
IH
V
IH
R
ON
Input Low Voltage for
VCCPWRGOOD and
VTTPWRGOOD signals
Input Low Voltage for
VDDPWRGOOD signal
Input High Voltage for
VCCPWRGOOD and
VTTPWRGOOD signals
Input High Voltage for
VDDPWRGOOD signal
Buffer On Resistance
0.75 * V
TTA
0.87V4,6
1018Ω
0.40 * V
TTA
V
TTA * RON
0.25 * V
+ R
TTA
sys_term
.
TTA
/ (RON
)
V2,5
0.29V6
V2,4,5
V2
V2,4
V2
V2,4
3
1
I
LI
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.The V
3.For V
4.V
specifications in Section 3.
5.This specification applies to the VCCPWRGOOD and VTTPWRGOOD signals.
6.This specification applies to the VDDPWRGOOD signal.
Input Leakage Current± 200μA
referred to in these specifications refers to instantaneous V
TTA
between 0 V and V
IN
may experience excursions above VTT. However, input signal drivers must comply with the signal quality
IH
. Measured when the driver is tri-stated.
TTA
TTA
.
3
Table 2-18. Processor Sideband Signal Group DC Specifications (Sheet 1 of 2)
SymbolParameterMinTypMaxUnitsNotes
V
Input Low Voltage0.64
IL
V
Input Low Voltage for
IL
PROCHOT# Signal
Input Low Voltage for
V
IL
PECI ID Signal
Input High Voltage0.76
V
IH
V
Input High Voltage for
IH
PECI ID Signal
085
* VTTA
* VTTA
0.61
0.15
* VTTA
* VTTA
* VTTA
V2
V2
V
V2
V
Intel® Xeon® Processor 5600 Series Datasheet Volume 143
1
Electrical Specifications
Table 2-18. Processor Sideband Signal Group DC Specifications (Sheet 2 of 2)
SymbolParameterMinTypMaxUnitsNotes
V
V
ODTOn-Die Termination45554
R
R
COMP0COMP Resistance49.449.950.4Ω6
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.The V
3.R
4.Applies to all Processor Sideband signals, unless otherwise mentioned in Table 2-6 .
5.This specification only applies to DDR_THERM# and DDR_THERM2#signals.
6.COMP resistance must be provided on the syst em board with 1% resistors. COMP0 resistors are t ied to V
Output Low VoltageV
OL
Output High VoltageV
OH
Buffer On Resistance for
ON
Processor Sideband Signals
Buffer On Resistance for
ON
VID[7:0] Signals
Input Leakage Current for
I
LI
Processor Sideband Signals
Input Leakage Current for
I
LI
DDR_THERM# and
DDR_THERM2# Signals
referred to in these specifications refers to instantaneous V
TTA
is the termination on the system and is not controlled by the processor.
SYS_TERM
TTA
1018Ω
* RON /
TTA
(R
ON
+ R
SYS_TERM
)
100Ω
± 200μA
± 50μA5
.
TTA
1
V2,3
V2
.
SS
2.7Intel QuickPath Interconnect Specifications
Intel QuickPath Interconnect specifications are defined at the processor
pins. In most cases, termination resistors are not required as these are integrated into
the processor silicon (Refer to Table 2-6).
Table 2-19. Common Intel QuickPath Interconnect Specifications (Sheet 1 of 2)
SymbolParameterMinNomMaxUnitNotes
UIavgAvg UI size at “f” GT/s
(f = 4.8, 5.86, or 6.4)
T
slew-rise-fall-pin
Z
TX_LOW_CM_DC
ΔZ
TX_LOW_CM_DC
Defined as the slope of the rising or
falling waveform as measured between
+/- 100 mV of the differential transmitter
output, for any data or clock.
DC resistance of Tx terminations at half
the single ended swing (usually
0.25*V
Tx-diff-pp-pin
Defined as: ± (max(Z
min(Z
TX_LOW_CM_DC))
expressed in %, over full range of Tx
) bias point
single ended voltage
Z
RX_LOW_CM_DC
ΔZ
RX_LOW_CM_DC
N
MIN-UI-Validation
Z
TX_HIGH_CM_DC
DC resistance of Rx terminations at half
the single ended swing (usually
0.25*V
Tx-diff-pp-pin
Defined as: ± (max(Z
min(Z
RX_LOW_CM_DC))
expressed in %, over full range of Rx
single ended voltage
) bias point
# of UI over which the eye mask v ol tag e
and timing spec needs to be validated
Single ended DC impedance to GND for
either D+ or D- of any data bit at Tx
TX_LOW_CM_DC
/ Z
TX_LOW_CM_DC
RX_LOW_CM_DC
/ Z
RX_LOW_CM_DC
) -
) -
0.999 *
Nom
1000/f1.001 *
Nom
psec
1025V / nsec
3852Ω
-606% of
Z
TX_LOW_CM_DC
3852Ω
-606% of
Z
RX_LOW_CM_DC
1,000,000UI
10kΩ1
44Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
Table 2-19. Common Intel QuickPath Interconnect Specifications (Sheet 2 of 2)
SymbolParameterMinNomMaxUnitNotes
Z
RX_HIGH_CM_DC
Z
TX_LINK_DETECT
V
TX_LINK_DETECT
T
DATA_TERM_SKEW
T
INBAND_RESET_SENSE
T
CLK_DET
T
CLK_FREQ_DET
Single ended DC impedance to GND for
either D+ or D- of any data bit at Rx
Link Detection Resistor5002000Ω
Link Detection Resistor Pull-up Voltage1.6V
Skew between first to last data
termination meeting Z
Time taken by inband reset detector to
sense Inband Reset
RX_LOW_CM_DC
Time taken by clock detector to observe
clock stability
Time taken by clock frequency detector
to decide slow vs. operational clock after
stable clock
T
Refclk-Tx - Variability
T
Refclk-jitter-rms-onepll
Phase variability between Reference Clk
(at Tx input) and Tx output
Accumulated rms jitter over n UI of a
given PLL model output in response to
the jittery reference clock input. The PLL
output is generated by convolving t he
measured reference clock phase jitter
with a given PLL transfer function. Here
n=12.
BER
Lane
Bit Error Rate per lane valid for 4.8, 5.86
and 6.4 GT/s
QPI[1,0]_COMPCOMP Resistance21.0-1%21.021.0+1%Ω
10kΩ2
128UI
1.5µs
20kUI
32Reference
Clock Cycles
500psec
0.5psec
1.0E-14Events
Notes:
1.Used during initialization. It is the state of “OFF” condition for the t r ans mitter. That is, wh en the output driver is disconnected
and only the minimum termination is connected. The link detection resistor is assumed not connected when specifying this
parameter.
2.Used during initialization. It is the state of “OFF” condition for the receiver when only the minimum termination is connected.
Table 2-20. Parameter Values for Intel QuickPath Interconnect Channels at 4.8 GT/s
(Sheet 1 of 2)
SymbolParameterMinMaxUnitN otes
V
Tx-diff-pp-pin
V
Tx-cm-dc-pin
Transmitter differential swing 8001400mV
Transmitter output DC common mode, defined as average
and VD- Use setup of Figure 2-11.
of V
D+
0.230.27Fraction of
V
TX-diff-pp-pin
Intel® Xeon® Processor 5600 Series Datasheet Volume 145
Electrical Specifications
Table 2-20. Parameter Values for Intel QuickPath Interconnect Channels at 4.8 GT/s
(Sheet 2 of 2)
SymbolParameterMinM a xUnitNotes
V
Tx-cm-ac-pin
TX
duty-pin
TX
jitUI-UI-1E-7pin
TX
jitUI-UI-1E-9pin
TX
clk-acc-jit-N_UI-1E-7
TX
clk-acc-jit-N_UI-1E-9
T
Tx-data-clk-skew-pin
T
Rx-data-clk-skew-pin
V
Rx-cm-dc-pin
V
Rx-cm-ac-pin
T
Rx-margin
Transmitter output AC common mode, defined as ((VD+ +
)/2 - V
V
D-
Figure 2-13 for illustration of A C common mode distributio n
and spec limits.
Tx-cm-ac-pin
). Use setup of Figure 2-11 and
Average of UI-UI jitter, using setup of Figure 2-11. This
appears as bimodal peaks in UI-UI jitter distribution
Figure 2-14.
UI-UI jitter measured at Tx output pins with 1E-7
probability , using setup of Figure 2-11. Refer to Figure 2-14
for illustration of UI-UI jitter distribution and spec limits
UI-UI jitter measured at Tx output pins with 1E-9
probability , using setup of Figure 2-11. Refer to Figure 2-14
for illustration of UI-UI jitter distribution and spec limits
P-P accumulated jitter out of any Tx data or clock over 0 <=
n <= N UI where N=12, measured with 1E-7 probability.
Refer to Figure 2-14 for illustration
P-P accumulated jitter out of any Tx data or clock over 0 <=
n <= N UI where N=12, measured with 1E-9 probability.
Refer to Figure 2-14 for illustration
Delay of any data lane relative to the clock lane, as
measured at Tx output
Delay of any data lane relative to the clock lane, as
measured at Tx+ channel. This parameter is a collective
sum of effects of data clock mismatches in Tx and on the
medium connecting Tx and Rx.
DC common mode ranges at the Rx input for any data or
clock channel, defined as average of V
AC common mode ranges at the Rx input for any data or
clock channel, defined as((V
Refer to Figure 2-13 for illustration.
Measured timing margin during receiver margining with any
receiver equalizer off or for Tx EQ only based systems
+ VD-)/2 - V
D+
and VD-.
D+
RX-cm-dc-pin
).
-0.03750.0375Fraction of
V
TX-diff-pp-pin
-0.0780.078UI
-0.0850.085UI
-0.090.09UI
00.15UI
00.17UI
-0.40.4UI
02UI1
-112
145350mV
-5050mV
0.1UI
Notes:
1.Refers to routing lengths of 10 - 15 inches (25.4 - 38.1 cm).
2.Refers to routing lengths of 0 - 10 inches (0 - 25.4 cm).
46Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
Table 2-21. Parameter Values for Intel QuickPath Interconnect Channel at 5.86 or
6.4 GT/s
SymbolParameterMinMaxUnitNote
V
Tx-diff-pp-pin
V
Tx-cm-dc-pin
V
Tx-cm-ac-pin
TX
duty-pin
TX
jitUI-UI-1E-7pin
TX
jitUI-UI-1E-9pin
TX
clk-acc-jit-N_UI-1E-7
TX
clk-acc-jit-N_UI-1E-9
T
Tx-data-clk-skew-pin
T
Rx-data-clk-skew-pin
V
Rx-cm-dc-pin
V
Rx-cm-ac-pin
T
Rx-margin
V
Rx-margin
Transmitter differential swing8001400mV
Transmitter output DC common mode, defined as
average of V
Transmitter output AC common mode, defined as
+ VD–)/2 - V
((V
D+
Figure 2-11 and Figure 2-13 for illustration of AC
common mode distribution and spec limits.
and VD–. Use setup of Figure 2-11.
D+
TX-cm-dc-pin
). Use setup of
Average of UI-UI jitter, using setup of Figure 2-11.
This appears as bimodal peaks in UI-UI jitter
distribution Figure 2-14
UI-UI jitter measured at Tx output pins with 1E-7
probability, using setup of Figure 2-11. Refer to
Figure 2-14 for illustration of UI-UI jitter distribution
and spec limits
UI-UI jitter measured at Tx output pins with 1E-9
probability, using setup of Figure 2-11. Refer to
Figure 2-14 for illustration of UI-UI jitter distribution
0.230.27Fraction of
V
TX-diff-pp-pin
–0.03750.0375Fraction of
V
TX-diff-pp-pin
-0.0780.078UI
-0.0880.088UI
-0.0950.095UI
and spec limits.
P-P accumulated jitter out of any Tx data or clock
over 0 <= n <= N UI where N=12, measured with
00.15 UI
1E-7 probability. Refer to Figure 2-14 for illustration
P-P accumulated jitter out of any Tx data or clock
over 0 <= n <= N UI where N=12, measured with
00.17 UI
1E-9 probability. Refer to Figure 2-14 for illustration
Delay of any data lane relative to clock lane, as
measured at Tx output
Delay of any data lane relative to the clock lane, as
measured at the end of Tx+Channel. This parameter
is a collective sum of effects of data clock mismatches
-0.40.4UI
02 UI1
-112
in Tx and on the medium connecting Tx and Rx.
DC common mode ranges at the Rx input for any data
or clock channel, defined as average of V
AC common mode ranges at the Rx input for any data
or clock channel, defined as ((V
). Refer to Figure 2-13 for illustration.
dc-pin
Measured timing margin during receiver margining
with any receiver equalizer off or forTx EQ only based
+ VD-)/2 - V
D+
and VD-.
D+
RX-cm-
145350mV
–5050mV
0.1UI
systems
Measured voltage margin during receiver margining
with receiver equalizer off
40mV
Notes:
1.Refers to routing lengths of 10 - 15 inches (25.4 - 38.1 cm).
2.Refers to routing lengths of 0 - 10 inches (0 - 25.4 cm).
2.8AC Specifications
AC specifications are defined at the processor pads, unless otherwise noted.
Therefore, proper simulation is the only means to verify proper timing and signal
quality. Care should be taken to read all notes associated with each parameter.
Intel® Xeon® Processor 5600 Series Datasheet Volume 147
Electrical Specifications
Table 2-22. System Reference Clock AC Specifications
ParameterMinNomMaxUnitFigureNotes
BCLK Frequency (SSC-off)133.29133.33133.37MHz2-172
BCLK Frequency (SSC-on)132.62133.33133.37MHz2-172
ER
BCLK-diffRise
T
BCLK-Dutycycle
T
BCLK-diff-jit
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.SSC is Spread Spectrum Clocking. The processor core clock frequency is derived from BCLK. The system
reference clock to processor core clock ratio is determined during initialization as described in
Section 2.1.5.
3.Rise and fall time slopes (V/ns) are measured between +150 mV and -150 mV of the differential output of
reference clock.
4.Phase drift between reference clocks at two connected ports.
, ER
BCLK-diffFall
1.04.0V/ns2-183
405060%2-17
500ps4
Table 2-23. DDR3/DDR3L Electrical Characteristics and AC Specifications at 800 MT/s
(Sheet 1 of 2)
Channel 0
Channel 1
SymbolParameter
Channel 2
UnitFigureNote
1
Latency Timings
tCL – tRCD – tRPCAS Latency – RAS to CAS Delay –
Pre-charge Command Period
Electrical Characteristics
T
SLR_D
DQ[63:0], DQS_N[17:0],
DQS_P[17:0], ECC[7:0]
Input Slew Rate
Clock Timings
T
CK
T
CH
T
CL
T
SKEW
CLK Period32.50ns
CLK High Time1.501.25ns
CLK Low Time1.501.25ns
Skew Between Any System
DQ[63:0] Valid before and after
DQS[17:0] Rising or Falling Edge
DQ Input Setup plus Hold Time to
DQS Rising or Falling Edge
MaxMin
6 – 6 – 6 t
CK
4.01.0V/ns2
+155ps
+375-375ps2-223,4,6
+375-375ps2-223,6
0.67 * UIUI7
0.25 * UIns2-231,2,7
48Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
Table 2-23. DDR3/DDR3L Electrical Characteristics and AC Specifications at 800 MT/s
(Sheet 2 of 2)
Channel 0
Channel 1
SymbolParameter
T
DQS_CO
T
DQS_CO
T
WPRE
T
WPST
T
DQSS
DQS Edge Placement Accuracy to
CK Rising Edge BEFORE write
leveling
DQS Edge Placement Accuracy to
CK Rising Edge AFTER write
leveling
DQS/DQS# Write Preamble
Duration
DQS/DQS# Write Postamble
Duration
CK Rising Edge Output Access
Time, Where a Write Command Is
Referenced, to the First DQS Rising
Edge
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies. Timing
specifications only depend on the operatin g freq ue ncy of th e memory channel and not the maximum rated
frequency.
2.When the single ended slew rate of the input Data or Strobe signals, within a byte group, are below 1.0
V/ns, the tSU and tHD specifications must be increased by a derating factor. The input single ended slew
rate is measured DC to AC levels; V
edges. Use the worse case minimum slew rate measured between Data and Strobe, within a byte group, to
determine the required derating value. No derating is required for single ended slew rates equal to or
greater than 1.0 V/ns.
3.Edge Placement Accuracy (EPA): The silicon contains digital logic that automatically adjusts the timing
relationshipbetween the DDR reference clocks and DDR signals. The BIOS initiates a training procedure
that will place a givensignal appropriately within the clock period. The difference in delay between the
signal and clock is accurate towithin ±EPA. This EPA includes jitter, skew, within die variation and several
other effects.
4.Data to Strobe read setup and Data from Strobe read hold minimum requirements specified at the
processor pad are determined with the minimum Read DQS/DQS# delay.
5.C
6.The system memory clock outputs are differential (CLK and CLK#), the CLK rising edge is referenc ed at the
7.The system memory strobe outputs are differential (DQS and DQS#), the DQS rising edge is referenced at
8.This values specifies the parameter after write leveling, representing the residual error in the controller
(CAS Write Latency) is the delay, in clock cycles, between the rising edge of CK where a write
WL
command is referenced and the first rising strobe edge where the first byte of write data is present. The
value is determined by the value of the CL (CAS Latency) setting.
C
WL
crossing point where CLK is rising and CLK# is falling.
the crossing point where DQS is rising and DQS# is falling, and the DQS falling edge is referenced at the
crossing point where DQS is falling and DQS# is rising.
after training, and does not include any effects from the DRAM itself.
_DC to VIH_AC for rising edges, and VIH_DC to VIL_AC for falling
IL
Channel 2
UnitFig u reNote
MaxMin
+375-375ns3,6,7
+275-275ns3,6,7,8
2.379ns
1.3711.129ns
CWL x (TCK
+ 4)
ns5,6
Table 2-24. DDR3 Electrical Characteristics and AC Specifications at 1066 MT/s (Sheet 1
of 2)
Channel 0
Channel 1
SymbolParameter
Latency Timings
tCL – tRCD – tRPCAS Latency – RAS to CAS Delay –
Pre-charge Command Period
Electrical Characteristics
Intel® Xeon® Processor 5600 Series Datasheet Volume 149
Channel 2
MaxMin
7 – 7 – 7
8 - 8 - 8
UnitFigureNote
tCK
Electrical Specifications
Table 2-24. D DR3 Electrical Characteristics and AC Specifications at 1066 MT/s (Sheet 2
of 2)
Channel 0
Channel 1
SymbolParameter
T
SLR_D
DQ[63:0], DQS_P[17:0],
DQS_N[17:0], ECC[7:0]
Input Slew Rate
Clock Timings
T
CK
T
CH
T
CL
T
SKEW
CLK Period<2.501.875ns
CLK High Time1.250.94ns
CLK Low Time1.250.94ns
Skew Between Any System
DQ[63:0] Valid before and after
DQS[17:0] Rising or Falling Edge
DQ Input Setup plus Hold Time to
DQS Rising or Falling Edge
DQS Edge Placement Accuracy to
CK Rising Edge BEFORE write
leveling
T
DQS_CO
DQS Edge Placement Accuracy to
CK Rising Edge AFTER write
leveling
T
WPRE
T
WPST
T
DQSS
DQS/DQS# Write Preamble
Duration
DQS/DQS# Write Postamble
Duration
CK Rising Edge Output Access
Time, Where a Write Command Is
Referenced, to the First DQS Rising
Edge
Channel 2
UnitFigureNote
MaxM in
4.01.0V/ns2
+155ps
+300-300ps2-223,4,6
+300-300ps2-223,6
0.67 * UIUI7
0.25 * UIns2-231,2,7
+300-300ns3,6,7
+206-206ns3,6,7,8
1.781ns
1.0310.844ns
C
x (TCK
WL
+ 4)
ns5,6
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.When the single ended slew rate of the input Data or Strobe signals, within a byte group, are below 1.0
V/ns, the tSU and tHD specifications must be increased by a derating factor. The input single ended slew
rate is measured DC to AC levels; V
edges. Use the worse case minimum slew rate measured between Data and Strobe, within a byte group, to
determine the required derating value. No derating is required for single ended slew rates equal to or
greater than 1.0 V/ns.
3.Edge Placement Accuracy (EPA): The silicon contains digital logic that automatically adjusts the timing
relationshipbetween the DDR reference clocks and DDR signals. The BIOS initiates a training procedure
that will place a givensignal appropriately within the clock period. The difference in delay between the
signal and clock is accurate towithin ±EPA. This EPA includes jitter, skew, within die variation and several
other effects.
4.Data to Strobe read setup and Data from Strobe read hold minimum requirements specified at the
processor pad are determined with the minimum Read DQS/DQS# delay.
_DC to VIH_AC for rising edges, and VIH_DC to VIL_AC for falling
IL
50Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
5.CWL (CAS Write Latency) is the delay, in clock cycles, between the rising edge of CK where a write
command is referenced and the first rising strobe edge where the first byte of write data is present. The
CWL value is determined by the value of the CL (CAS Latency) setting.
6.The system memory clock outputs are differential (CLK and CLK#), the CLK rising edge is referenc ed at the
crossing point where CLK is rising and CLK# is falling.
7.The system memory strobe outputs are differential (DQS and DQS#), the DQS rising edge is referenced at
the crossing point where DQS is rising and DQS# is falling, and the DQS falling edge is referenced at the
crossing point where DQS is falling and DQS# is rising.
8.This values specifies the parameter after write leveling, representing the residual error in the controller
afrter training, and does not include any effects from the DRAM itself.
Table 2-25. DDR3/DDR3L Electrical Characteristics and AC Specifications at 1333 MT/s
DQ[63:0] Valid before and after
DQS[17:0] Rising or Falling Edge
DQ Input Setup plus Hold Time to
DQS Rising or Falling Edge
DQS Edge Placement Accuracy to
CK Rising Edge BEFORE write
leveling
DQS Edge Placement Accuracy to
CK Rising Edge AFTER write
leveling
Channel 2
UnitFigureNote
MaxMin
8 - 8 - 8
tCK
9 - 9 - 9
4.01.0V/ns2
+155ps
+250-250ps2-223,4,6
+250-250ps2-223,6
0.67 * UIUI7
0.25 * UIns1,2,7
+250-250ns2-243,6,7
+165-165ns2-243,6,7,8
Intel® Xeon® Processor 5600 Series Datasheet Volume 151
Electrical Specifications
Table 2-25. DDR3/DDR3L Electrical Characteristics and AC Specifications at 1333 MT/s
(Sheet 2 of 2)
Channel 0
Channel 1
SymbolParameter
T
WPRE
T
WPST
T
DQSS
DQS/DQS# Write Preamble
Duration
DQS/DQS# Write Postamble
Duration
CK Rising Edge Output Access
Time, Where a Write Command Is
Referenced, to the First DQS Rising
Edge
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.When the single ended slew rate of the input Data or Strobe signals, within a byte group, are below 1.0
V/ns, the tSU and tHD specifications must be increased by a derating factor. The input single ended slew
rate is measured DC to AC levels; V
edges. Use the worse case minimum slew rate measured between Data and Strobe, within a byte group, to
determine the required derating value. No derating is required for single ended slew rates equal to or
greater than 1.0 V/ns.
3.Edge Placement Accuracy (EPA): The silicon contains digital logic that automatically adjusts the timing
relationshipbetween the DDR reference clocks and DDR signals. The BIOS initiates a training procedure
that will place a givensignal appropriately within the clock period. The difference in delay between the
signal and clock is accurate towithin ±EPA. This EPA includes jitter, skew, within die variation and several
other effects.
4.Data to Strobe read setup and Data from Strobe read hold minimum requirements specified at the
processor pad are determined with the minimum Read DQS/DQS# delay.
5.CWL (CAS Write Latency) is the delay, in clock cycles, between the rising edge of CK where a write
command is referenced and the first rising strobe edge where the first byte of write data is present. The
CWL value is determined by the value of the CL (CAS Latency) setting.
6.The system memory clock outputs are differential (CLK and CLK#), the CLK rising edge is referenced at the
crossing point where CLK is rising and CLK# is falling.
7.The system memory strobe outputs are differential (DQS and DQS#), the DQS rising edge is refe renced at
the crossing point where DQS is rising and DQS# is falling, and the DQS falling edge is referenced at the
crossing point where DQS is falling and DQS# is rising.
8.This values specifies the parameter after write leveling, representing the residual error in the controller
afrter training, and does not include any effects from the DRAM itself.
_DC to VIH_AC for rising edges, and VIH_DC to VIL_AC for falling
IL
Channel 2
MaxM in
1.425ns
0.8250.674ns
CWL x (TCK
+ 4)
UnitFigureNote
ns5,6
Table 2-26. Processor Sideband Signal Group AC Specifications (Sheet 1 of 2)
T# ParameterMinMaxUnitFigure
Asynchronous GTL input pulse width8BCLKs
Tb: V
stable to VTTPWRGOOD assertion1500ms2-285,7,8,10
TT
Td: VTTPWRGOOD assertion to Dynamic V
Processor
Te: V
stable to VDDPWRGOOD assertion100ns2-285,6,7
DDQ
Tf: VTTPWRGOOD to valid VID010µs2-28
Th: V
stable to VCCPWRGOOD assertion0.05650ms2-28
CC
Ti: V
stable to VCCPWRGOOD assertion1ms2-28
CCPLL
Tj: BCLK stable to VCCPWRGOOD assertion10BCLKs2-28
Tk: VCCPWRGOOD assertion to RESET# de-assertion110ms2-28
Tm: VTTPWRGOOD assertion to VCCPWRGOOD
assertion
Tn: V
rise time1.5ms2-2814
CCPLL
Tq: PROCHOT# pulse width500µs2-26
Tr:THERMTRIP# assertion until V
/ VTT removed500ms2-27
CC
52Intel
VID from
TT
10µs2-289
1ms2-28
®
Xeon® Processor 5600 Series Datasheet Volume 1
Notes
1,2,3,4
Electrical Specifications
Table 2-26. Processor Sideband Signal Group AC Specifications (Sheet 2 of 2)
T# ParameterMinMaxUnitFigure
VTTPWRGOOD de-assertion to V
T
: Time from BCLK land until signal valid at output0.52.275ns11
CO
T
: Processor Sideband Input signals with respect to
SU
BCLK
: Processor Sideband Input signals with respect to
T
H
BCLK
: Power-On Configuration Hold Time (PROCHOT#)106BCLK8-113
T
H
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.All AC timings for the Asynchronous GTL signals are referenced to the BCLK_P rising edge at Crossing
Voltage (V
at 0.5 * V
3.These signals may be driven asynchronously.
4.Refer to Section 8 for additional timing requirements for entering and leaving low power states.
5.xxPWRGOOD signal has no edge rate requirement, but edge must be monotonic.
6.VDDPWRGOOD must be asserted no later then VCCPWRGOOD. There is no releationship between
VDDPWRGOOD and VCC ramp.
7.There is no dependency between V DDPWRGOOD and VTTPWRGOOD assertion.
8.VTTPWRGOOD must accurately reflect the state of VTT and must not glitch whenever VTT or VDD is
applied.
9.VTT must read VTTFINAL before VCCPWRGOOD assertion.
10. It may be required to add delay on the board to meet the 1 ms minimum processor requirement.
11. Based on a test load of 50 Ω to V
12. Specified for synchronous signals.
13. Applies to PROCHOT# signal only. Please see Section 2.1.7.3.1 and Section 8.1 for information regarding
Power-On Configuration options.
14. Rise time is measured from 10% to 90% of the final voltage.
). VCCPWRGOOD, VTTPWRGOOD and VDDPWRG OOD are referenced to BCLK_P rising edge
CROSS
.
TT
below specification100ns
TT
.
TT
Table 2-27. TAP Signal Group AC Specifications
Notes
1,2,3,4
600ps12
600ps
T# ParameterMinMaxUnitFigure
TCK Period31.25ns
T
: TDI, TMS Setup Time1ns2-25
s
T
: TDI, TMS Hold Time1ns2-25
h
T
: TDO Clock to Output Delay0.54ns2-25
x
T
: TRST# Assert Time2T
q
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.Not 100% tested. Specified by design characterization.
3.It is recommended that TMS be asserted while TRST# is being deasserted.
Table 2-28. VID Signal Group AC Specifications
T# ParameterMinMaxUnitFigureNotes
Ta: VID Step Time1.25µs2-29
Tb: VID Down Transition to Valid V
Tc: VID Up Transition to Valid V
Td: VID Down Transition to Valid V
Te: VID Up Transition to Valid V
Notes:
1.Platform support for VID transitions is required for the processor to operate within specifications.
(min)0µs2-29
CC
(min)15µs2-29
CC
(max)15µs2-29
CC
(max)0µs2-29
CC
TCK
Notes
1,2,3
2-26
1
Intel® Xeon® Processor 5600 Series Datasheet Volume 153
Electrical Specifications
Tx Package
Silicon TX
Ideal Loads
SI Tx pin terminations are set to optimum values
(targeted around 42.5 ohms si ngle-ended)
2.9Processor AC Timing Waveforms
The following figures are to be used in conjunction with the AC specifications included
in Table 2-19 through Table 2-28.
Note:For Figure 2-11 through Figure 2-29, the following apply:
1. All System Reference Clock signal AC specifications are referenced to the Crossing
Voltage (V
2. All TAP signal group AC specifications are referenced to the TCK at 0.5 * V
processor lands. All TAP signal group timings (TMS, TDI, and so forth) are
referenced at 0.5 * V
3. All CMOS signal AC specifications are referenced at 0.5 * VTT at the processor
lands.
The Intel QuickPath Interconnect electrical test setup are shown in Figure 2-11 and
Figure 2-12.
Figure 2-11. Intel QuickPath Interconnect Electrical Test Setup for Validating
Standalone TX Voltage and Timing Parameters
) of the BCLK_DP and BCLK_DN at rising edge of BCLK_DP.
CROSS
at the processor die (pads).
TT
at the
TT
54Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
S i lic o n
T x b it
(D ata )
W o rs t-C a s e Inte r c o n n e ct
Id e a l
Loads
Tx
Package
S i lic o n
T x b it
(C loc k)
Id e a l
Loads
Lossless Interconnect Phase
Matc h ed to D a ta B it In te rc o n n e c t
0.5* (VD+ - VD-) - X_cm_dc_pin
Figure 2-12. Intel QuickPath Interconnect Electrical Test Setup for Validating
TX + Worst-Case Interconnect Specifications
Figure 2-13. Distribution Profile of Common Mode Noise for Either Tx or Rx
Intel® Xeon® Processor 5600 Series Datasheet Volume 155
Figure 2-14. Distribution Profile of UI-UI Jitter and Accumulated Jitter
Figure 2-17. Differential Clock Measurement Points for Duty Cycle and Period
Figure 2-18. Differential Clock Measurement Points for Rise and Fall time
Intel® Xeon® Processor 5600 Series Datasheet Volume 157
Electrical Specifications
Figure 2-19. Single-Ended Clock Measurement Points for Absolute Cross Point and Swing
Figure 2-20. Single-Ended Clock Measurement Points for Delta Cross Point
Figure 2-21. Differential Clock Measurement Point for Ringback
58Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
CK# (IMC)
MA , B S,
RAS#,
CAS#, WE#
(IMC)
CK (IMC)
Control Signals
(IMC)
Tcm d_c o
Tcm d_co
BIOS
Programmabl e
Delay
Tcm d_c s
Tcm d_c s
Figure 2-22. DDR3 Command / Control and Clock Timing Waveform
Figure 2-23. DDR3 Clock to Output Timing Waveform
Intel® Xeon® Processor 5600 Series Datasheet Volume 159
Figure 2-24. DDR3 Clock to DQS Skew Timing Waveform
Figure 2-25. TAP Valid Delay Timing Waveform
Electrical Specifications
Note: Please refer to Table 2-18 for TAP Signal Group DC specifications and Table 2-27 for TAP Signal Group
AC specifications.
60Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
TRST# Assert Time, V = 0.5 * V
TTA
V
T
q
PROCHOT# Pulse Width, V = V
TTA
=
Tq
THERMTRIP#
V
CC
V
TT
Tr
Tr: THERMTRIP# assertion unti l VCC, VTT removal
Figure 2-26. Test Reset (TRST#), Asynch GTL Input, and PROCHOT# Timing Waveform
Figure 2-27. THERMTRIP# Power Down Sequence
Intel® Xeon® Processor 5600 Series Datasheet Volume 161
Figure 2-28. Voltage Sequence Timing Requirements
VTTPWRGOOD
V
TT
BCLK
VCCPWRGOOD
VCC VID[7:0]
V
CC
V
DDQ
VDDPWRGOOD
RESET#
V
CCPLL
LFM VID From C P U
V
CCBOOT
Tk
Tj
POC
MSID
V
LFM
Th
VTT VID FINAL
VTT_VID[2:0]
V
TTBOOT
V
TTSAFE
VT T VID from
VID Buffer
V
TTFINAL
Tb
Tm
Td
VDDPW R GO O D m ust assert before or at the same time as
VCCPWRGOOD assertion
VTT must be stable before VCCPWR GO O D
assertion
Varies based on BIOS execution
Dynamic VID From CPU
Tf
Refer to VRD11.1 specification for details on Vcc ramp timings
Ti
Te
Electrical Specifications
62Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications
Note: In order In order to ensure Timestamp Counter (TSC) synchronization across sockets in multi-socket
systems, the RESET# deassertion edge should arrive at the same BCLK rising edge at both sockets and
should meet the Tsu and Th requirement of 600ps relative to BCLK, as outlined in Table 2-26.
Figure 2-29. VID Step Times and Vcc Waveforms
Note: This waveform illustrates an example of an Intel Adaptive Thermal Monitor transition or an Intel
Enhanced SpeedStep Technology transition that is six VID step down from the current state and six
steps back up. Any arbitrary up or down transition can be generalized from this waveform.
§
Intel® Xeon® Processor 5600 Series Datasheet Volume 163
Electrical Specifications
64Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Signal Quality Specifications
3Signal Quality Specifications
Data transfer requires the clean reception of data and clock signals. Ringing below
receiver thresholds, non-monotonic signal edges, and excessive voltage swings will
adversely affect system timings. Ringback and signal non-monotonicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines.
Excessive signal swings (overshoot and undershoot) are detrimental to silicon gate
oxide integrity, and can cause device failure if absolute voltage limits are exceeded.
Overshoot and undershoot can also cause timing degradation due to the build up of
inter-symbol interference (ISI) effects.
For these reasons, it is crucial that the designer work towards a solution that provides
acceptable signal quality across all systematic variations encountered in volume
manufacturing.
This section documents signal quality metrics used to derive topology and routing
guidelines through simulation. All specifications are specified at the processor die (pad
measurements).
Specifications for signal quality are for measurements at the processor core only and
are only observable through simulation. Therefore, proper signal simulation is the only
means of properly verifying timing and signal quality requirements.
3.1Overshoot/Undershoot Tolerance
Overshoot (or undershoot) is the absolute value of the maximum voltage above or
below VSS. The overshoot/undershoot specifications limit transitions beyond V
due to the fast signal edge rates. The processor can be damaged by single and/or
V
SS
repeated overshoot or undershoot events on any input, output, or I/O buffer if the
charge is large enough (that is, if the over/undershoot is great enough). Baseboard
designs which meet signal integrity and timing requirements and which do not exceed
the maximum overshoot or undershoot limits will insure reliable IO performance for the
lifetime of the processor.
The pulse magnitude, duration, and activity factor must all be used to determine if the
overshoot/undershoot pulse is within specifications.
Note:Oscillations below the reference voltage cannot be subtracted from the total
Table 3-1. Overshoot/Undershoot Tolerance
overshoot/undershoot pulse duration.
Signal GroupMin UndershootMax OvershootDuration
Intel QuickPath Interconnect-0.1 * V
DDR3-0.1 * V
Processor Sideband Signals-0.1 * V
System Reference Clock-0.31.15NA
Notes:
1.These specifications are measured at the processor pin.
2.Refer to Figure 3-1 for description of Overshoot/Undershoot magnitude and duration.
TT
DDQ
TT
1.2 * V
1.2 * V
1.2 * V
TT
DDQ
TT
0.5 * T
CCIO
500 ps
50 ns
or
CH
Intel® Xeon® Processor 5600 Series Datasheet Volume 165
Figure 3-1. Maximum Acceptable Overshoot/Undershoot Waveform
Vss
Overshoot
Duration
Undershoot
Duration
Overshoot
Undershoot
Signal Quality Specifications
§
66Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Package Mechanical Specifications
IHS
Substrate
LGA1366 Socket
System Board
Capacitors
TIM
IHS
Substrate
LGA
System Board
Capacitors
Die
TIM
4Package Mechanical
Specifications
4.1Package Mechanical Specifications
The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA) package that
interfaces with the baseboard via an LGA1366 socket. The package consists of a
processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is
attached to the package substrate and core and serves as the mating surface for
processor component thermal solutions, such as a heatsink. Figure 4-1 shows a sketch
of the processor package components and how they are assembled together. Refer to
the Intel
complete details on the LGA1366 socket.
The package components shown in Figure 4-1 include the following:
1. Integrated Heat Spreader (IHS)
2. Thermal Interface Material (TIM)
3. Processor core (die)
4. Package substrate
5. Capacitors
®
Xeon® Processor 5500/5600 Series Thermal/Mechanical Design Guide for
Figure 4-1. Processor Package Assembly Sketch
Note:
1.Socket and baseboard are included for reference and are not part of processor package.
4.1.1Package Mechanical Drawing
The package mechanical drawings are shown in Figure 4-2 and Figure 4-2. The
drawings include dimensions necessary to design a thermal solution and reflect the
processor as received by Intel. These dimensions include:
1. Package reference with tolerances (total height, length, width, and so forth)
2. IHS parallelism and tilt
3. Land dimensions
4. Top-side and back-side component keep-out dimensions
5. Reference datums
Intel® Xeon® Processor 5600 Series Datasheet Volume 167
6. All drawing dimensions are in mm.
7. Guidelines on potential IHS flatness variation with socket load plate actuation and
installation of the cooling solution is available in the Intel® Xeon® Processor
5500/5600 Series Thermal/Mechanical Design Guide.
Figure 4-2. Processor Package Drawing (Sheet 1 of 2)
Package Mechanical Specifications
68Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Package Mechanical Specifications
Figure 4-3. Processor Package Drawing (Sheet 2 of 2)
Intel® Xeon® Processor 5600 Series Datasheet Volume 169
4.1.2Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component
keep-out zone requirements. A thermal and mechanical solution design must not
intrude into the required keep-out zones. Do not contact the Test Pad Area with
conductive material. Decoupling capacitors are typically mounted to either the topside
or land-side of the package substrate. See Figure 4-2 and Figure 4-2 for keep-out
zones. The location and quantity of package capacitors may change due to
manufacturing efficiencies but will remain within the component keep-in.
4.1.3Package Loading Specifications
Table 4-1 provides load specifications for the processor package. These maximum
limits should not be exceeded during heatsink assembly, shipping conditions, or
standard use condition. Exceeding these limits during test may result in component
failure. The processor substrate should not be used as a mechanical reference or load-
1.These specifications apply to uniform compressive loading in a direction normal to the processor IHS.
2.This is the maximum static force that can be applied by the heatsink and Independent Loading Mechanism
(ILM).
3.These specifications are based on limited testing for design characterization. Loading limits are for the
package constrained by the limits of the processor socket.
4.Dynamic loading is defined as an 11 ms duration average load superimposed on the static load
requirement.
5.See Intel® Xeon® Processor 5500/5600 Series Thermal/Mechanical Desi gn Guide for min imum so cket lo ad
to engage processor within socket.
4.1.4Package Handling Guidelines
Table 4-2 includes a list of guidelines on package handling in terms of recommended
maximum loading on the processor IHS relative to a fixed substrate. These package
handling loads may be experienced during heatsink removal.
Table 4-2.Package Handling Guidelines
ParameterMaximum RecommendedNotes
Shear70 lbs
Tensile25 lbs
Torque35 in.lbs
4.1.5Package Insertion Specifications
The processor can be inserted into and removed from an LGA1366 socket 15 times. The
socket should meet the LGA1366 requirements detailed in the Intel® Xeon® Processor
5500/5600 Series Thermal/Mechanical Design Guide.
70Intel
®
Xeon® Processor 5600 Series Datasheet Volume 1
Package Mechanical Specifications
4.1.6Processor Mass Specification
The typical mass of the processor is 35 grams. This mass [weight] includes all the
components that are included in the package.
4.1.7Processor Materials
Table 4-3 lists some of the package components and associated materials.