Intel 82540EP User Manual
82540EP Gigabit Ethernet Controller
Networking Silicon
Datasheet
Revision 1.2
April 2003
INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHA TSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel products referenced in this document may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-
4725 or by visiting Intel's website at http://www.intel.com.
*Other names and brands may be claimed as the property of others.
Copyright © Intel Corporation, 2002-2003
ii Datasheet
Revision History
Date Revision Notes
Apr 2002 0.25 Initial Release
Nov 2002 1.0 Changed document status to Intel Confidential.
Jan 2003 1.1 Section 1.0. Replaced Block Diagram
Section 2.6. Ad ded Table footnote
Section 4.1, 4.2, 4.3. Replaced tables
Section 5.1. Added Visual Pin Reference
Sectio n 4. 4 Remo v e d P o we r Sup pl y Characterist ic s; add ed no te to I/O Ch ar ac -
teristics
Section 5.0 Repl aced Pinout Diagram
Apr 2003 1.2 Removed confidential status.
Section 1. 0. Added prod uc t orderin g co de.
Networking Silicon — 82540EP
Datasheet iii
82540EP — Networking Silicon
Note: This page is int entionally left blank.
iv Datasheet
Networking Silicon — 82540EP
Contents
1.0 Introduction......................................................................................................................... 1
1.1 Document Scope.......... ................... ............................ ................... .......................3
1.2 Reference Documents...........................................................................................3
1.3 Product Code ........................................................................................................3
2.0 Features of the 82540EP Gigab it Ethernet Controller........................................................5
2.1 PCI Features.........................................................................................................5
2.2 MAC Specific Features.......................................................................................... 5
2.3 PHY Specific Fea tu re s.......... ................... ............................. ................... .............6
2.4 Host Offloading Features ................................................... ....... ................. ......... ..6
2.5 Manageability Features.........................................................................................7
2.6 Addition al Dev ice Fea tu r e s... ................... ............................. ............................ ....8
2.7 Technology Features.............................................................................................8
3.0 Signal Descriptions....................................................... ....... ............ ....... ....... ............ .........9
3.1 Signal Type Definitions..................................................................... .......... ....... ....9
3.2 PCI Bus Interface..................................................................................................9
3.2.1 PCI Address, Data and Cont r o l Si g nal s.............................. .....................9
3.2.2 Arbitrat ion Signals.............................. ................... ............................. ....11
3.2.3 Interrupt Signal.......................................................................................11
3.2.4 System Signal s..................... ................... ................... ............................11
3.2.5 Error Reporting Signals..........................................................................11
3.2.6 Power Man agem ent Signals ..................................................................12
3.2.7 Impe dance Comp ens ation Signals.........................................................12
3.2.8 SMB S ignals...........................................................................................12
3.3 EEPROM and Serial FLASH Interface Signals ...................................................12
3.4 Miscellan eou s Signals................................................. ................... .....................13
3.4.1 LED Signals............................................................................................ 13
3.4.2 Other Signals..........................................................................................13
3.5 PHY Signals... ................... ................... .................. ............................. ................14
3.5.1 Crystal Sign al s..... ............................ ............................ ................... .......14
3.5.2 Analog Signal s..... ................... .................. ................... ..........................14
3.6 Test Interface Signals..........................................................................................15
3.7 Power Supply Connections ................................................................................. 15
3.7.1 Digital Supplies.......................................................................................15
3.7.2 Analog Supplies .....................................................................................15
3.7.3 Ground and No Connect s........................ ............................ ...................16
3.7.4 Control Signals.......................................................................................16
4.0 Voltage, Temperat ure, and Timing Specifications............................................................17
4.1 Absolute Maximum Ratings.................................................................................17
4.2 Recomm ended Ope ra ting Conditions .................................................................17
4.3 DC Specifications................................................................................................18
4.4 AC Characteristics................. ............................. ................... ............................ ..21
4.5 Timing Specifications ........................... .................. ............................. ................22
4.5.1 PCI Bus Interface................................................................................... 22
4.5.2 Link Interface Timing..............................................................................26
Datasheet v
82540EP — Networking Silicon
4.5.3 EEPROM Interface................................................................................. 26
5.0 Package and Pin out Information................................... ............................ ................... ....27
5.1 Device Ident ification ............................................... ............................ ................27
5.2 Package Information.............. ................... ............................ ............................. .28
5.3 Thermal Specifications........................................................................................29
5.4 Pinout Information ..................................................... .......... ....... ....... ....... ....... ....30
5.5 Visual Pin Reference...........................................................................................39
vi Datasheet
1.0 Introduction
The Intel® 82540EP Gigabit Et hern et Contr oll er is a sing le, co mpact component wi th an integ rat ed
Gigabit Ethernet Media Access Control (MA C) and physical layer (PHY) functions. For desktop,
workstation and mobile PC Network designs with critical space constraints, the Intel
allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with
current generation 10/100 Mbps Fast Ethernet designs
®
The Intel
physical laye r circ uitry to provide a standard IEEE 802 .3 Ethernet interface for 1000BASE-T,
100BASE-TX, and 10B ASE -T applic at ions (80 2.3, 802. 3u, an d 802.3ab ). The cont roll er is capabl e
of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to
managing MA C and PHY layer functions, the control ler provides a 32-bit wide direct Peri pheral
Component Interconnect (PCI) 2.2 compliant interface capable of operating at 33 or 66 MHz.
The 82540EP also incorporates the CLKRUN protocol and ha rdware supported downshift
capabilit y to two or three-pair 100 Mb/s operation. These features optimize mobile applications.
82540EP integrates Intel’s fourth generation gigabit MAC design with fully integrated,
Networking Silicon — 82540EP
®
82540EP
The Intel
®
82540EP’ s on-board System Management Bus (SMB) port enables network
manageabilit y implementations requ ired by information tech nology personnel for remote control
and alerting via the LAN. Wit h SMB, managemen t packe ts can be rout ed to or from a management
processor . The SMB port en ables industry standards, such as In telligent P latform Man agement
Interface (IPMI) and Alert Standard Forum (ASF), to be implemented using the 82540EP. In
addition, on chi p ASF 1.0 circuitry provid es alerting and remote control capabilities wit h
standardized interfaces.
The 82540EP Gigabit Ethernet Controller architecture is designed to deliv er high performance and
PCI bus efficien cy. Wide inter n al da ta pat h s eli mi n at e p er f o r man ce bottlenecks by efficie n tl y
handling large address and data words. The 82540EP controller include s advanced interru pt
handling featu res to limit PCI bus traffic and a PCI interface that maximizes the use of bursts for
eff icient bus usage. The 82540EP caches up to 64 packet descriptors in a single burst for efficient
PCI bandwidth use. A large 64 KByte on-chip packet bu ffer maintains superior performance as
available PCI bandwidth changes. In addition, using hardwa re ac ce leration, the controll er offloads
tasks from the host controller , s uch as TCP/UDP/IP checksum calculations and TCP segmentation.
2
The 82540EP is packag ed in a 15 mm
196-ball grid array and is pin compatible with both the
82551QM 10/100 Mbps F as t Et hernet Multifuncti on PCI/CardBus Controller and the 82540EM
Gigabit Ethernet Controller (which does not have added power saving features like CLKRUN).
Datasheet 1
82540EP — Networking Silicon
PCI
i/f
PCI I/F
4-wire EEPROM Inte rfac e
SMBus Interface
blocks)
(Many
Clock / Reset
EEPROM
Configs
Default
ACPI
LED
HW
Packet Buffer
64K bytes
Manageability
FIFOs
Mgmt
ASF
CSR Register
Access
Statistics
Master
FIFO
read
Data Alignment
descriptor
FIFOs
engine
RX
Packet Buffer Interface
RX
In
CSR Register
Access
TX Data
RX Data
Filter
RX Data
RX
Master
FIFO
write
FIFOs
Flow
Ctrl
RX MAC
Core
PCI
Control
Target
descriptor
engine
TX
Target Logic
DMA
TX
Out
TX
Arb
Tx
TX MAC
GMII
MAC Core
Control, Status
& Interrupt
Registers
82540EP Architecture
Flash Interfac e
MDIOFlash
PHY
Link
TX
(Copper)
Interface
MDI
Figure 1. Gigabit Eth ernet Controller Bl ock Di agram
2 Datasheet
1.1 Document Scope
This document contains datasheet specifications for the 82540EP Gigabit Ethernet Cont roller,
including si gnal descriptions, DC and AC parameters, packaging data, and pinout information .
1.2 Reference Documents
This application assumes that the designer is acquainted with high-speed design and board la yout
techniques. The following documents provide additiona l information:
• 82544EI/82544GC Gigabit Ethernet Control ler Software Developer's Manual, Revision 0.25,
Intel Corporation.
• PCI Local Bus Specification, Revision 2.3, PCI Special Interest Group.
• PCI Bus Power Management Interface Specification, Rev. 1.1, PCI Special Interest Group.
• IEEE Standard 802.3, 1996 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3u, 1995 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3x, 1997 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3z, 1998 Edition, Institute of Elec trical and Electronics Engi nee r s (IEEE).
Networking Silicon — 82540EP
• IEEE Standard 802.3ab, 1999 Edition, Institute of Electrical and Electronics Engineers
(IEEE).
• 82559 Fast Ethernet Controllers Tim ing Device Selection Guide, AP-419, Intel Corporation.
• PCI Mobile Design Guide, Rev. 1.1, PCI Special Interest Group
1.3 Product Code
The product ordering code for the 82540EP is: RC82540EP.
Datasheet 3
82540EP — Networking Silicon
Note: Th is page is intentionally left blank.
4 Datasheet
Networking Silicon — 82540EP
2.0 Features of the 82540EP Gigabit Ethernet Controller
2.1 PCI Features
Features Benefits
• Application flexibility for LAN on Motherboard
PCI Revision 2. 3 support fo r 32-bit wid e interface at
33 MHz and 66 MHz
Algori thms that opt imally us e advance d PCI, MWI,
MRM, and MRL commands
CardBus Information Services (CIS) Pointer
CLKRUN# Signal • PCI clock suspension for lo w power mobile design
(LOM) or embedded solutions
• 64-bit addressing for system s with more th an 4
Gigabytes of physical memory
• Support for new PCI 2.3 interrupt status/control
• Efficient bus operations
• Enables CardBus operation (when us ed with
ext ernal FLASH device and series termination on
PCI bus)
2.2 MAC Specific Features
Features Benefits
Low- latency transmit and r eceive qu eues
IEEE 802.3x compliant flow control support with
softw are controllable pa use times and threshold
values
Caches up to 64 packet des cri ptors in a single bur st • Efficient use of PCI bandwid th
Programmable host memory receive buffers (256
Bytes to 16 KBytes) and cache line size (16 Bytes to
256 Bytes)
Wide, optimized internal data path architecture
64 KByte configu rable Transmit and Receive FIFO
buffers
Descriptor ring management hardware for transmit
and receive
Optimized descr iptor fetching and w rite-back
mechanisms
Mechanism available for reducing interrupts
generated by transmit and recei ve ope rations
Support for transm ission and receptio n of pack ets up
to 16 KBytes
• Netw ork pack ets handled withou t waiting or buffer
overflow.
• Control over t he transmi ssions of pause frames
through software or hardware triggering
• Frame loss reduced from receive overruns
• Efficient use of PCI bandw idth
• Low latency da ta handling
• Superior DMA t ransfer rate pe rfo rmance
• No external FIFO memory requirements
• FIFO size adjustable to application
• Simple software programming model
• Effi ci ent system mem ory and use of PCI
bandwidth
• Maxi m ize s sy s t em performa nc e and throug hput
• Enable s jum b o f ram es
Datasheet 5
82540EP — Networking Silicon
2.3 PH Y Spe cif ic Fe atu res
Features Benefits
Integrated PHY for 10/100/1000 Mbps full and half
duplex op eration
IEEE 802.3ab Auto-Negotiation support
IEEE 802.3ab PHY compliance and compatibility
State-of-the-art DSP architecture implements digital
adaptive equalization, echo cancellation, and crosstalk cancellation
PHY ability to autom atically detect polari ty and cable
lengths and MDI versus MDI-X cable at all speeds
2.4 Host Offloading Features
Features Benefits
T ransmit and receive IP, TCP and UDP checksum offloading capabil ities
Transmit TCP segmentation
Advanced packet filtering
IEEE 802.1q VLAN support with VLAN tag insertion,
strippin g an d pac k et filt e ring for up to 409 6 VL AN tags
Descriptor ring management hardware for transmit
and receive
16 KByte jumbo frame support
Interrupt coalescing (multiple packets per interrupt)
• Smaller footprint and lower power dissipation
compar ed to multi- chip MAC and PHY solutions
• Automatic link configuration including speed,
duplex, and flow control
• Robust operat ion over the installed base of
Category-5 (CAT-5) twisted pair cabling
• Robust performance in noisy environments
• Tolerance of com m on electrical signal
impairments
• Easier network installation and maintenance
• End-to -end wiring t olerance
• Lower CPU utilization
• Increased throug hput and lower CPU utilizat ion
• Large send offload feature (in Microsoft*
Window s* XP) compatible
• 16 exact matched packets (unicast or multicast)
• 409 6-b i t has h f ilt er for multicast fra me s
• Promiscu ous (unicast and multicast) transfer
mode support
• Optical filtering of inv alid frames
• Ability to create multiple virtual LAN segments
• Optimi zed f etc hing and writ e-bac k mech anis ms f or
efficient system memory and PCI bandwidth
usage
• High throughput for large data transfers on
networks supporting jumbo frames
• Increased throug hput by reducing interrupts
generated by tr ansmit an d receive operatio ns
6 Datasheet
2.5 Manageability Features
Features Benefits
Networking Silicon — 82540EP
Manageability features: SMB port, ASF 1.0, ACPI,
Wa ke on LAN, and PXE
On-board SMB port
Compliance with PCI Power Management 1.1 and
ACPI 2.0 register set compliant including:
• D0 and D 3 power states
• Network Device Class Power Management
Specification 1.1
• PCI Sp ecification 2.2
SNMP and R M O N statistic counters
SDG 3.0, WfM 2.0, and PC2001 com pliance
Wa ke on LAN sup port
Two or three-pair cable downshift • Assures link under adverse cable configurations
• Netw or k m anagemen t flexibi lity
• Enab les IPMI and ASF impl em entations
• Allow s pac k et s ro ut ing t o an d from ei th er L AN port
and a se rver management processor
• PCI po wer management capability requirements
for PC and embe dded applications
• Easy system monitorin g with indust ry standard
consoles
• Remote network management capabilities through
DMI 2.0 and SNMP software
• Packet recognitio n and wake-up for NIC and LOM
applic ations with out softw are configuration
Datasheet 7
82540EP — Networking Silicon
2.6 Additional Device Features
Features Benefits
Four activity and link indication outputs that di re ctly
drive LEDs
Progra mm a ble LE D f u nctiona li t y
Internal PLL for clock generation can use a 25 MHz
crystal
JTAG (IEEE 1149.1) Test Access Port built in silicon • Simplified testing using boundary scan
On-chip power control circuitry
Four software definable pins
Supports little endian byte ordering for both 32 and 64
bit sys t em s and bi g en dian byte ord ering for 64 bit
systems
Two or t hree-pair cable dow nshift • Supports modular har dware acc essories
Provi de s lo op back capabilitie s • Validates silicon int e gr i ty
Minimal ballout change from the 82540EM • Pin Compatibility
a. If applying the “low-power” EEPROM setting for the 82540EP chip, then only external voltage regulator circuits should be used
instead of the on-chip power control circuitry
a
2.7 Technology Features
• Link and activity indications (10, 100, and 1000
Mbps) on each port
• Software definable function (speed , link, and
activity) and bl inking allowing flexible LED
implementations
• Lower component count and system cost
• Redu c ed number of on -board power supply
regulators
• Simplified power supply design in less powercritical applications
• Additional flexibil ity for LE Ds or other low spe ed
I/O devices
• Portable across application architectures
Features Benefits
196-pin Ball Grid Array (TFBGA) package • 15 mm2 component making LOM designs easier
Pin compatible with 82551 QM and 82540EM
controllers
Implemented in 0. 15u CMOS process
Operating temperature: 0
operating temperature
Heat sink or forced airflow not required
65
° C to 140° C stor age temperature ran ge
PCI Signaling: 3.3 V (5 V tolerant) PCI signaling
Typic al tar ge t e d pow er dissipation:
• 1.38W @ D0 1000 Mb/s
• 386mW @ D3 100 Mb/s (wake-up enabled)
• <20mW @ D3 wake-up disabled
° C to 70° C (maximum)
• Enables 10/100 Mbps Fast Ethernet or 1000 Mbps
Gigabit Ethernet implementations on the same
board wi th only minor stuffing option changes
• Offe r s lowest ge ometry to mini m ize power and
size while maintainin g Intel quality reliability
standards
• Simple thermal design
• Lower power requirements for mobile applications
8 Datasheet
Loading...