INTEL 82503 User Manual

DUAL SERIAL TRANSCEIVER (DST)

82503 PRODUCT FEATURE SET OVERVIEW

Y

Single Component Ethernet* Interface
to Both 802.3 10BASE-T and AUI

Y

Automatic or Manual Port Selection

Y

Manchester Encoder/Decoder and
Clock Recovery

Y

No Glue Interface to Industry-Standard
LAN Controllers
Ð Intel 82586, 82590, 82593 and 82596
Ð AMD 7990 (LANCE*)
Ð National Semiconductor 8390 and

83932 (SONIC*)
Ð Western Digital 83C690
Ð Fujitsu 86950 (Etherstar*)

INTERFACE FEATURES

82503

Y

Y

Y

Y

Y

Y

Y

Y

Diagnostic Loopback

Reset, Low Power Modes

Network Status Indicators

Defeatable Jabber Timer

User Test Modes

10 MHz Transmit Clock Generator

One Micron CHMOS** IV (Px48)
Technology

Single 5-V Supply

TPE

Y

Complies with 10BASE-T, IEEE Std.

802.3i-1990 for Twisted Pair Ethernet

Y

Selectable Polarity Switching

Y

Direct Interface to TPE Analog Filters

Y

On-Chip TPE Squelch

Y

Defeatable Link Integrity (LI)

Y

Support of Cable Lengthsl100m

AUI

Y

Complies with IEEE 802.3 AUI Standard

Y

Direct Interface to AUI Transformers

Y

On-Chip AUI Squelch

A block diagram of a typical application is shown in Figure 1. The 82503 Dual Serial Transceiver is a high-inte­gration CMOS device designed to simplify interfacing industry standard Ethernet LAN Controllers to IEEE

802.3 local area network applications (10BASE5, 10BASE2, and 10BASE-T). The component supports both
an attachment unit interface (AUI) and a Twisted Pair Ethernet interface (TPE). It allows OEMs to design a
state-of-the-art media interface that is jumperless and fully automatic. The 82503 includes on-chip AUI and
TPE drivers and receivers; it offers designers a cost-effective, integrated solution for interfacing LAN control­lers to the wire medium.

**CHMOS is a patented process of Intel Corporation.

*Ethernet is a registered trademark of Xerox Corporation.

LANCE is a registered trademark of Advanced Micro Devices.
Etherstar is a registered trademark of Fujitsu Electronics.
Sonic is a registered trademark of National Semiconductor Corporation.

*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

October 1995COPYRIGHT©INTEL CORPORATION, 1996 Order Number: 290421-004

82503 Dual Serial Transceiver (DST)

CONTENTS PAGE

1.0 82503 PRODUCT FEATURES

2.0 PIN DEFINITION ААААААААААААААААААААААА 5

2.1 Power Pins АААААААААААААААААААААААААА 6

2.2 Clock Pins ААААААААААААААААААААААААААА 6

2.3 AUI Pins ААААААААААААААААААААААААААААА 6

2.4 TPE Pins АААААААААААААААААААААААААААА 7

2.5 Controller Interface Pins ААААААААААААА 7

2.6 Mode Pins ААААААААААААААААААААААААААА 8

2.7 LED Pins АААААААААААААААААААААААААААА 9

3.0 82503 ARCHITECTURE АААААААААААААА 10

3.1 Clock Generation ААААААААААААААААААА 10

3.2 Transmit Blocks АААААААААААААААААААА 10

3.3 Receive Blocks ААААААААААААААААААААА 11

3.4 Collision Detection ААААААААААААААААА 13

3.5 Link Integrity ААААААААААААААААААААААА 13

3.6 Jabber Function АААААААААААААААААААА 13

3.7 TPE Loopback ААААААААААААААААААААА 13

3.8 SQE Test Function ААААААААААААААААА 14

3.9 Port Selection АААААААААААААААААААААА 14

3.10 LED Description ААААААААААААААААААА 14

3.11 Polarity Switching ААААААААААААААААА 14

3.12 Controller Interface АААААААААААААААА 15

ААААААААА 3

CONTENTS PAGE

4.0 RESET, LOW POWER AND TEST
MODES

4.1 Reset АААААААААААААААААААААААААААААА 16

4.2 Low Power and High Impedance

4.3 Diagnostic Loopback ААААААААААААААА 16

4.4 Customer Test Modes (Continuous

5.0 APPLICATION EXAMPLE АААААААААААА 17

5.1 Introduction АААААААААААААААААААААААА 17

5.2 Design Guidelines АААААААААААААААААА 17

5.3 Layout Guidelines АААААААААААААААААА 17

6.0 PACKAGE THERMAL
SPECIFICATIONS АААААААААААААААААААААА 19

7.0 ELECTRICAL SPECIFICATIONS
AND TIMINGS АААААААААААААААААААААААААА 20

АААААААААААААААААААААААААААААААА 16

Modes

ААААААААААААААААААААААААААААААА 16

AUI/TPE Transmit) АААААААААААААААААА 16

2

Figure 1. Application Block Diagram

82503

290421– 1

1.0 82503 PRODUCT FEATURES

The 82503 incorporates all the active circuitry re­quired to interface Ethernet controllers to 10BASE-T
networks or the attachment unit interface (AUI). It
supports a direct no-glue interface to Intel’s family of
high-performance LAN controllers (82586, 82590,
82593, and 82596). The 82503 also provides a di­rect no-glue interface to the National Semiconductor
8390 and 83932 (SONIC), the Western Digital
83C690, the Advanced Micro Devices 7990
(LANCE) and 79C900 (ILACC), and the Fujitsu
86950 (Etherstar) controllers.

This component includes three advanced features:
jumperless two-port design capability, automatic port
selection, and polarity switching. The jumperless
TPE or AUI port selection capability allows design­ers maximum ease-of-use and network flexibility. Au­tomatic port selection ensures complete software
compatibility with existing 10BASE2 and 10BASE5
software drivers. The 82503’s polarity switching fea­ture will detect and correct polarity errors on the
twisted pairÐthe most common wiring fault in twist­ed pair networks.

The 82503 contains all the circuitry needed to meet
the 10BASE-T specification, including link integrity, a
jabber timer and internal predistortion. Deselecting
link integrity allows the component to be used in
some prestandard networks. The 82503’s jabber
timer prevents the station from continuously trans­mitting and is defeatable for simple design charac-

terization. The predistortion circuitry eliminates line
overcharge and reduces jitter on 10BASE-T links.

The 82503 can also support twisted pair cable
lengths of up to 200m when placed in TPE Extended
Squelch Mode (XSQ).

This component incorporates six LED drivers to dis­play transmit data, receive data, collision, link integri­ty, polarity faults and port selections, allowing for
complete network monitoring by the user. The trans­mit, receive and collision LEDs indicate the rate of
activity by the frequency of flashing. The 82503 also
has a low power mode. During low power, many of
the 82503’s pins are in a high-impedance state to
facilitate board-level testing.

The 82503’s diagnostic loopback control enables it
to route a transmission signal from the LAN control­ler through its Manchester encoder-decoder circuitry
and back to the LAN controller. This provides effec­tive network node fault detection and isolation capa­bilities. In addition, the 82503 supports diagnostic
test modes that generate continuous tranmission of
data through the twisted pair port, allowing design­ers to measure the analog performance of their de­sign.

The 82503 is available in 44-lead PLCC and 44-lead
QFP packages and is fabricated with Intel’s low­power, high-speed, CHMOS IV technology using a
single 5-V supply.

3

82503

290421– 2

Figure 2. 82503 Functional Block Diagram

4

2.0 PIN DEFINITION

82503

290421– 3

Figure 3. 44-Lead PLCC Pin Configuration

Figure 4. 44-Lead QFP Pin Configuration

290421– 44

5

82503

2.1 Power Pins

Symbol

(1)

V

SS

(1)

V

CC

(1)

V

CCA

(1)

V

SSA

NOTE:

and V

1. V

CC

Separate decoupling and noise conditioning (e.g., ferrite beads) should be used.

PLCC QFP

Pin Pin

Type Name and Function

7, 17, 39 1, 11, 33 Supply Digital Ground.

6, 18, 40 44, 12, 34 Supply Digital VCC. A 5-Vg5% Power Supply.

28 22 Supply Analog VCC. A 5-Vg5% Power Supply.

29 23 Supply Analog Ground.

must be connected to the same power supply. VSSand V

CCA

must be connected to the same ground.

SSA

2.2 Clock Pins

Symbol

X1 21 15 I CLOCK CRYSTAL. A 20 MHz crystal input. This pin can be driven

X2 20 14 O CLOCK CRYSTAL. A 20 MHz crystal output. X1 can be driven with

PLCC QFP

Pin Pin

Type Name and Function

with an external MOS level clock when X2 is left floating.

an external MOS level clock when this pin is left floating.

2.3 AUI Pins

Symbol

TRMT 27 21 O TRANSMIT PAIR. A differential output driver pair that drives the
TRMT

RCV 31 25 I RECEIVE PAIR. A differentially driven input pair which is tied to the
RCV

CLSN 25 19 I COLLISION PAIR. A differentially driven input pair tied to the
CLSN

PLCC QFP

Pin Pin

26 20 O

30 24 I

24 18 I

Type Name and Function

transmit pair of the transceiver cable. The output bit stream is
Manchester encoded. Following the last transition, which is positive
at TRMT, the differential voltage is reduced to zero volts.

receive pair of the Ethernet transceiver cable. The first transition on
RCV is negative-going to indicate the beginning of the frame. The
last transition is positive-going to indicate the end of the frame. The
received bit stream is assumed to be Manchester encoded.

collision presence pair of the Ethernet transceiver cable. The
collision presence signal is a 10 MHz square wave. The first
transition at CLSN is negative-going to indicate the beginning of the
signal; the last transition is positive-going to indicate the end of the
signal.

6

2.4 TPE Pins

Symbol

TDH 35 29 O TP TRANSMIT PAIR DRIVERS. These four outputs constitute the
TDH
TDL 34 28 O
TDL

RD 32 26 I TP RECEIVE PAIR. The differential twisted pair receiver. The
RD

PLCC QFP

Pin Pin

37 31 O

36 30 O

33 27 I

Type Name and Function

twisted-pair drivers, which have predistortion capabilities. The TDH/
TDH outputs generate the 10 Mb/s Manchester Encoded data. The
TDL/TDL
occurrences (100 ns pulses). During the second half of a fat bit
(either high or low), the TDL/TDL outputs are inverted with respect
to TDH/TDH
jitter by preventing overcharge on the twisted pair medium.

receiver pair is connected to the twisted pair medium and is driven
with 10 Mb/s Manchester encoded data.

outputs mirror the TDH/TDH outputs except for fat bit

outputs. This signal behavior reduces the amount of

2.5 Controller Interface Pins

Symbol

TxC 93OTRANSMIT CLOCK. A 10 MHz clock output tied directly to the

TxD 16 10 I TRANSMIT DATA. TTL input. NRZ serial data is clocked in on TxD

RTS 15 9 I REQUEST TO SEND. TTL input. An active low input signal

RxC 14 8 O RECEIVE CLOCK. A 10 MHz clock output tied directly to the

RxD 13 7 O RECEIVE DATA. Received NRZ data (synchronous to RxC) passed

CRS 10 4 O CARRIER SENSE. Output that alerts the Ethernet controller that

CDT 12 6 O COLLISION DETECT. Output that indicates presence of a collision.

PLCC QFP

Pin Pin

Type Name and Function

transmit clock pin of the Ethernet controller. Changes sense
depending on controller selected. Active low for Intel and Fujitsu
controller interfaces, active high for National and AMD interfaces.
Can drive one TTL load.

from the Ethernet controller. Connects directly to the transmit data
pin of the Ethernet controller.

synchronous to TxC
port. Changes sense depending on controller selected. Active low
for the Intel controller interface, active high for National, AMD, and
Fujitsu interfaces.

receive clock pin of the Ethernet controller. This clock is the
recovered clock from incoming data on the active port. Changes
sense depending on controller selected. Active low for Intel and
Fujitsu controller interfaces, active high for National and AMD
interfaces. Can drive one TTL load.

to the Ethernet controller. Connect directly to the receive data pin of
the controller. Can drive one TTL load.

data is present on the active port. Connects directly to the carrier
sense pin of the Ethernet controller. Changes sense depending on
controller mode selected. Active low for Intel controller interface,
active high for National, AMD, and Fujitsu interfaces. Can drive one
TTL load.

Connects directly to the collision detect pin of the Ethernet
controller. Changes sense depending on controller selected. Active
low for Intel and Fujitsu controller interfaces, active high for National
and AMD interfaces. Can drive one TTL load.

which enables data transmission on the active

82503

7

82503

2.6 Mode Pins

Symbol

TPE/AUI 2 40 I/O PORT SELECT. TTL input/LED output. If APORT is low,

APORT 3 41 I AUTOMATIC PORT SELECTION. TTL input. When high, 82503

APOL/XSQ 4 42 I AUTOMATIC POLARITY CORRECTION/EXTENDED

LID 38 32 I LINK INTEGRITY DISABLE. TTL input. If high, link integrity

CS0 5 43 I CONTROLLER SELECT. Selects the appropriate interface for
CS1 8 2 I

LPBK 11 5 I LOOPBACK. TTL input. An active low input signal that causes

JABD 23 17 I JABBER DISABLE. TTL input. When high, this pin disables the

TEST 19 13 I TEST MODE ENABLE. TTL input. When TEST is high and

RESET 22 16 I RESET. TTL input. When high, resets internal circuitry. On the

PLCC QFP

Pin Pin

Type Name and Function

TPE/AUI
high) or AUI port (TPE/AUI low). If APORT is high, the 82503 will
indicate the port selected by driving TPE/AUI
(AUI). TPE/AUI

will automatically select TPE or AUI port based on presence of
valid link beats or frames on the TPE receive input. Mode
selected will be indicated on TPE/AUI

SQUELCH ENABLE. TTL input. When high, the extended
squelch mode is disabled and automatic polarity correction is
enabled. Both junctions (APOL and XSQ) are enabled when this
pin is at a high impedance state. When low, both functions
become disabled. The presence of a polarity fault on the TPE
receive pair is indicated on POLED regardless of the state of
APOL.

function is disabled. If low, link integrity function is enabled.

the desired Ethernet controller. When CS0/1
Intel controllers. When CS0/1
controllers. When CS0/1
National controllers. When CS0/1
controllers. (See Table 2.)

the 82503 to enter diagnostic loopback mode. The twisted pair
or AUI medium will be removed from the circuit, thus isolating
the node from the network. When not connected, this pin
assumes the inactive (high) state. Diagnostic loopback does not
disable the operation of the link integrity processor, link beat
generator, or automatic port selection.

jabber function. When low, the jabber function is enabled and
the device performs AUI or TP jabber protection for the active
port. If this pin and TEST are asserted during a falling edge of
RESET, the 82503 enters its low power mode; when either this
pin or TEST deasserts, then the 82503 transitions to its normal
operating mode.

RESET is deasserted, a customer test mode is directly
accessed. When driven low, test mode is disabled. If this pin and
JABD are asserted during a falling edge of RESET, the 82503
enters its low power mode; when either this pin or JABD
deasserts, then the 82503 transitions to its normal operating
mode.

falling edge of RESET, either test mode or low power mode can
be entered depending on the state of JABD and TEST.

is an input and selects either the TPE port (TPE/AUI

can drive an LED pull-up.

.

e

0/1, supports Fujitsu

e

1/0, supports Western Digital and

e

1/1, supports AMD

high (TPE) or low

e

0/0, supports

8

2.7 LED Pins

Symbol

TxLED 42 36 I/O TRANSMIT LED. LED output. Indicates transmit status of the AUI or

RxLED 43 37 I/O RECEIVE LED. LED output. Indicates receive status of the AUI or

COLED 44 38 I/O COLLISION LED. LED output. Indicates collision status of the AUI

LILED 41 35 O LINK INTEGRITY LED. LED output. Normally on (low) output which

POLED 1 39 O POLARITY INDICATION. LED output. If the 82503 detects that the

PLCC QFP

Pin Pin

Type Name and Function

TPE port. Normally off (high) output. Turns on to indicate
transmission. Flashes at a rate dependent on the level of transmit
activity. Upon entering a customer test mode, this pin must be
driven high either through an LED, or a resistor.

TPE port. Normally off (high) output. Turns on to indicate reception.
Flashes at a rate dependent on the level of receive activity. Upon
entering a customer test mode, this pin must be driven high either
through an LED, or a resistor.

or TPE port. Normally off (high) output. Turns on to indicate
collision. Flashes at a rate dependent on the level of collision
activity. This pin is also used to determine which customer test
modes are entered.

indicates good link integrity on the TPE port during TPE mode.
Remains on when link integrity function has been disabled. Turns off
during AUI mode or when link integrity fails in TPE mode. Minimum
off time is 100 ms, minimum on time is set by the link integrity
function.

receive TPE wires are reversed, POLED will turn on (low) to indicate
the fault. POLED remains on even if APOL/XSQ is high and the
82503 has automatically corrected for the reversed wires.

82503

NOTE:

1. The LED outputs have a weak pull-up capable of sourcing 500 mA. They can sink 10 mA while still meeting TTL levels. All
LEDs can be used as indication pins if no LED is needed. Some of these outputs include pulse width conditioning, which
should be accounted for in software.

9

82503

3.0 82503 ARCHITECTURE

3.1 Clock Generation

A 20 MHz parallel resonant crystal is used to control
the clock generation oscillator, which provides the
basic 20 MHz clock source. An internal divide-by­two counter generates the 10 MHz
required by the IEEE 802.3 specification.

We recommend a crystal that meets the following
specifications be used.

Quartz Crystal

#

20 MHzg0.002% at 25§C

#

Accuracyg0.005% over full operating tempera-

#

ture, 0

Ctoa70§C

§

Parallel resonant with 20 pF Load Fundamental

#

Mode

Maximum Series Resistance: R

#

Several vendors have such crystals; either-off-the
shelf or custom made. Two possible vendors are:

1. M-Tron Industries, Inc.

Yankton, SD 57078

Specifications;
Part No. HC49 with 20 MHz, 50 PPM over 0

a

70§C, and 20 pF fundamental load.

2. Crystek Corporation

100 Crystal Drive
Ft. Myers, FL 33907

Part No. 013212

The accuracy of the Crystal Oscillator frequency de­pends on the PC board characteristics, therefore it is
advisable to keep the X1 and X2 traces as short as
possible. The optimum value of C1 and C2 should
be determined experimentally under nominal operat­ing conditions. The typical value of C1 and C2 is
between 22 pF and 35 pF.

An external 20 MHz MOS-level clock may be applied
to pin X1, if pin X2 is left floating.

g

0.01% clock

SERIES

e

30X

Cto

§

3.2 Transmit Blocks

3.2.1 MANCHESTER ENCODER

The 20 MHz clock is used to Manchester-encode
data on the TxD input. This clock is also divided by
two to produce the 10 MHz clock the LAN controller
needs for synchronizing its RTS

Data encoding and transmission begins with RTS
asserting. Since the first bit of a transmission is a 1,
the first transition is always negative on the transmit
outputs (TRMT or TD pins). Transmission ends
when RTS
positive at the transmit outputs (TRMT or TD pins)
and may occur at the center of the bit cell if the last
data bit to be transmitted is a 1, or at the boundary
of the bit cell if the last data bit to be sent is a 0.

Immediately after the end of a transmission, all sig­nals on the RCV pair (when AUI mode is selected)
are inhibited for 4 to 5 ms. This dead time is neces­sary for proper operation of the SQE (heartbeat)
test.

3.2.2 AUI CABLE DRIVER

The AUI cable driver (TRMT pair) is a differential
circuit, which interfaces to the AUI cable through a
pulse transformer.

High voltage protection is achieved by using a trans­former to isolate the transmit pins (TRMT pair) from
the transceiver cable. The total transmit circuit in­ductance, including the 802.3 transceiver transform­ers, should be a minimum of 27 mH for Ethernet ap­plications.

3.2.3 TWISTED PAIR CABLE DRIVER

The twisted pair line drivers (TD pairs) begin trans­mitting the serial Manchester bit stream 3 bit times
after RTS
tortion algorithm to improve jitter performance for up
to 100 meters of twisted pair cable. The line drivers
reduce their drive level during the second half of
‘‘fat’’ (100 ns) Manchester pulses and maintain a full
drive level during all ‘‘thin’’ (50 ns) pulses and during
the first half of the ‘‘fat’’ pulses. This reduces line
overcharging during ‘‘fat’’ pulses, a major source of
jitter.

deasserts. The last transition is always

is asserted. The line drivers use a predis-

and TxD signals.

10

Figure 5. TPE Predistortion

82503

290421– 4

3.3 Receive Blocks

3.3.1 MANCHESTER DECODER AND CLOCK

RECOVERY

The 82503 performs Manchester decoding and tim­ing recovery of the incoming data in AUI and TPE
modes.

The Manchester-encoded data stream is decoded to
separate the Receive Clock (RxC
Data (RxD) from the differential signal. The 82503
uses an advanced digital technique to perform the
decoding function. The use of digital circuitry instead
of analog circuitry (e.g., a phase-lock loop) to per­form the decoding ensures that the decoding func­tion is less sensitive to variations in operating condi­tions.

A high-resolution phase reference is used to digitize
the phase of the incoming data bit-center transition.
The digitizer has a phase resolution of 1/32 of a bit
time.

) and the Receive

The digitized phase is filtered by a digital low-pass
filter to remove rapid phase variations, i.e., phase
jitter. Slow phase variations, such as those caused
by small differences between the data frequency
and the clock frequency, are not filtered by the low­pass filter.

The RxC generator digitally sets the phases of the
two RxC
bit-center transition by (/4 bit time. RxC

transitions to respectively lead and lag the

is used to
recover RxD by sampling the incoming data with an
edge-triggered flip-flop.

Lock is achieved by reducing the time constant of
the digital filter to zero at the start of a new frame.
Any uncertainty in the bit-center phase of the first
transition that is caused by jitter is subsequently re­moved by gradually increasing the filter time con­stant during the following preamble. By that time, the
phase of the bit center is output by the filter, and
lock is achieved. Lock is achieved within the first 14
bit times as seen by the AUI inputs. The maximum
bit-cell timing distortion (jitter) tolerated by the Man­chester decoder circuitry is

g

18 ns (data) for AUI, andg13.5 ns for TPE (data

g

12 ns (preamble),

and preamble).

11

82503

290421– 5

Figure 6. Manchester Decoder and Clock Recovery

3.3.2 AUI RECEIVE AND COLLISION BUFFERS

The AUI receive and collision inputs are driven
through isolation transformers to provide high volt­age protection and DC common mode voltage rejec­tion. The incoming signals are converted to digital
levels and passed to the Manchester decoder and
collision detection circuitry.

3.3.3 AUI RECEIVE AND COLLISION SQUELCH CIRCUITS

Both the receive (RCV) and collision (CLSN) pairs
have the following squelch characteristics.

The squelch circuits are turned on at idle.

#

A pulse is rejected if the peak differential voltage

#

is more positive than
pulse width.

A pulse is considered valid if its peak differential

#

voltage is more negative than
width, measured at
25 ns.

The squelch circuits are disabled by the first valid

#

negative differential pulse on either the AUI re­ceive (RCV) or the AUI collision (CLSN) pair.

If a positive differential pulse occurs on either the

#

AUI receive or collision pairs for greater than
160 ns, End of Frame (EOF) is assumed and the
squelch circuitry is turned on.

3.3.4 TPE RECEIVE BUFFER

The TPE receive pins (RD and RD
the twisted pair medium through an analog front
end. The analog front end contains the line coupling

b

160 mV regardless of

b

b

285 mV, is greater than

300 mV and its

) are connected to

devices and EMI filters necessary to conform to the
10BASE-T standards and local RF regulations. The
input differential voltage range for the TPE receiver
is greater than 500 mV and less than 3.1V differen­tial.

3.3.5 TPE RECEIVE SQUELCH CIRCUITS

The TPE receive buffer distinguishes valid receive
differential data, link test pulses, and the idle condi­tion according to the requirements of the 10BASE-T
standard. Signals at the output of the EMI filter (thus
at the RD and RD

All differential pulses of peak magnitude less than

#

300 mV are rejected.

All continuous sinusoids with a differential ampli-

#

tude less than 6.2 V
2 MHz are rejected.

All sine waves of single cycle duration starting

#

with phase 0
than 6.2 V
16 MHz are rejected, if the single cycle is pre­ceeded and followed by 4 bit times of silence
(i.e., a signal less than 300 mV).

3.3.6 TPE Extended Squelch Mode

By placing the 82503 into TPE extended squelch
mode, the 82503 can support cable lengths greater
than the 100m specified in the 10Base-T IEEE stan­dard (802.3i-1990). The squelch thresholds for the
signals at the RD/RD

4.5 dB. This allows Grade 5 twisted-pair cable to be
used to overcome attenuation and multipair cross­talk for cable lengths up to 200 meters.

pair) are rejected as follows:

and a frequency less than

PP

or 180§that have an amplitude less

§

, and a frequency of 2 MHz to

PP

pair are typically reduced by

12

82503

TPE extended squelch mode is enabled by present­ing a high-impedance (
pin. This can be done by floating the APOL/XSQ pin,
tying APOL/XSQ low through a 100 KX resistor, or
driving APOL/XSQ with a three-state buffer. When
driven high or low using a TTL driver or a low imped­ance pull-up or pull-down (
squelch is disabled and the driven level at the
APOL/XSQ pin determines the state of the polarity­correction function (APOL/XSQ
ty correction, APOL/XSQ
rection). The TPE extended squelch feature is trans­parent to previous steppings of the 82503. Polarity
correction is always enabled when the TPE extend­ed-squelch feature is enabled (APOL/XSQ

The APOL/XSQ pin senses a high-impedance state
by an active-polling circuit implemented at the pin.
Two small polling devices attempt to pull the APOL/
XSQ pin up to V
high-impedance state, the devices will be successful
in pulling the APOL/XSQ pin high and low. If the pin
is driven high or low, the polling devices will not be
able to successfully pull the pin in the opposite di­rection. In this way, an internal state machine can
correctly determine one of three states of the
APOL/XSQ pin. The pin is polled every 25.6 ms.

l

100 KX) at the APOL/XSQ

k

2KX) extended

e

e

and down to VSS. If the pin is in a

CC

1 enables polari-

0 disables polarity cor-

e

Z).

3.4 Collision Detection

3.4.1 AUI COLLISION DETECTION

Collision detection in the AUI mode is performed by
the attached transceiver, and signalled to the 82503
on the CLSN pair. A 10 MHz
square wave with transition times between 35 ns
and 70 ns indicates the collision. The 82503 reports
this to the LAN controller on the CDT

a

25%, orb15%,

pin.

to the twisted pair medium as an indication to the
remote MAU that the link is good. These pulses will
be transmitted 8 ms to 24 ms after the end of the
last transmission or link test pulse.

The link integrity function continuously monitors ac­tivity on the receive circuit. If neither valid data nor
link test pulses are received, the link integrity proc­essor declares the link bad, and disables transmis­sion and reception on the media, loopback, and the
SQE test function. Transmission of link test pulses
and monitoring receive activity are not affected. The
idle time required for the link integrity processor to
determine the link is bad is 50 ms to 150 ms.

Once a frame or a sequence of 2 to 10 valid consec­utive link test pulses are detected, the Link Integrity
Processor declares the link is good, and reconnects
the transmitter and receiver.

The link integrity function can be disabled by driving
the LID pin high or by disabling automatic port selec­tion (APORT
option is intended primarily for use with pre­10BASE-T networks.

e

0) and selecting the AUI port. This

3.6 Jabber Function

The 82503 contains a jabber timer to implement the
jabber function. If a transmission continues beyond
the limits specified, the jabber function inhibits fur­ther transmission and asserts the collision indicator,
CDT. The limits for jabber transmission are 20 ms to
150 ms in TPE Mode, and 8 ms to 16 ms in AUI
mode. For both AUI and TPE mode, the transmis­sion inhibit period extends until the 82503 detects
sufficient idle time (between 250 ms and 750 ns) on
the RTS
by driving the JABD high.

signal. The jabber function can be disabled

3.4.2 TPE COLLISION DETECTION

Collision detection in the TPE mode is indicated by
simultaneous transmission and reception on the
twisted pair link segment. The CDT
ed for the duration of both RTS
received data; CRS
either RTS
a collision, the source of RxD will be the received
data. If the received data stream ends before the
transmit data stream, the RxD source will be
changed to transmit data stream until it ends.

or the presence of received data. During

is asserted for the duration of

signal is assert-

and the presence of

3.5 Link Integrity

The 82503 supports the link integrity function as de­fined by 10BASE-T. During long periods of idle on
the transmitter, link test pulses will be transmitted on

In TPE mode the link integrity function continues to
operate even if the jabber function is inhibiting trans­mission. Link test pulses continue to be sent and the
receive circuit continues to be monitored. Additional­ly, the link integrity function reconnects to a restored
link without waiting for the transmit input to go idle
when the jabber function is inhibiting transmission.

3.7 TPE Loopback

In TPE mode the 82503 implements the transmit to
receive loopback (DO to DI) mode specified in the
10BASE-T standard. This mode loops back transmit­ted data through the receive path.

This function is required to maintain full compatibility
with coax MAUs where the data loopback is a natu­ral result of the architecture.

13

82503

The transmit to receive loopback function is disabled
when the jabber function or link integrity function is
inhibiting transmission.

3.8 SQE Test Function

The 82503 supports the SQE test function when in
TPE mode or in Diagnostic Loopback mode. The
82503 will assert its CDT

pin within 0.6 msto1.6ms
after the end of a transmission, and it will remain
asserted for 5- to 15-bit times. If the 82503 is in the
TPE mode and is not in diagnostic loopback mode,
the link integrity function will disable the SQE test
function when it detects a bad link.

3.9 Port Selection

The 82503 features both manual and automatic port
selection. To enable automatic port selection, con­nect APORT to V
mode and monitors link integrity. If the link is good,
the 82503 stays in TPE mode and pulls TPE/AUI
high to indicate that the TPE port was selected. If
link integrity fails, the 82503 switches to AUI mode
and pulls TPE/AUI
is now active. TPE/AUI
port selection (on for AUI, off for TPE mode). Note
that LILED will be on if TPE mode is selected and off
if AUI mode is selected. If link integrity is disabled
while automatic port selection is enabled, the 82503
defaults to TPE mode. If the 82503 changes ports
while RTS

is active, transmission is terminated with
an End of Frame marker on the old port. Transmis­sion of the remaining packet fragment is not allowed
on the new port. Transmissions will begin with a
complete data packet.

The port can be manually selected by driving
APORT low. TPE/AUI
TPE/AUI

e

selected, the circuitry for the unused port is powered
down. Changing ports requires 100 ms to allow the
circuitry for the new port to resume normal opera­tion.

Configuration

LID APORT TPE/AUI

X 0 0 AUI (TPE Port Powered Down)
X 0 1 TPE (AUI Port Powered Down)
01 X*Automatic Port Selection
11 X*TPE

. The 82503 then starts in TPE

CC

low to indicate that the AUI port

can drive an LED to indicate

e

0 selects AUI mode, and

1 TPE mode. When the port is manually

Table 1. Port Selection

State

3.10 LED Description

The 82503 supports six LED pins to indicate the
status of important states; TPE/AUI
POLED, LILED, RxLED, COLED. Each pin is capable
of directly driving an LED.

3.10.1 TPE/AUI

When automatic port selection is enabled (APORT is
high), TPE/AUI

becomes an LED output and turns
off if TPE mode is selected and on if AUI mode is
selected.

3.10.2 TxLED

Transmit status. This LED is normally off and flashes
at 2.5 Hz, 5 Hz, and 10 Hz to indicate respectively a
low, medium, and high rate of transmit activity.

3.10.3 RxLED

Receive LED. This LED is normally off and flashes at

2.5 Hz, 5 Hz, and 10 Hz to indicate respectively a
low, medium, and high rate of receive activity.

3.10.4 COLED

Collision LED. This LED is normally off and flashes
at 2.5 Hz, 5 Hz, and 10 Hz to indicate respectively a
low, medium, and high rate of collision activity.

3.10.5 POLED

Polarity Fault. This LED is normally off and turns on
to indicate a polarity fault in the receive pair of the
10BASE-T link. Operation of this pin is not affected
by the state of the polarity correction function
(APOL/XSQ

e

X).

3.10.6 LILED

Link Integrity status. When Aport is enabled
(APORT

e

1), this LED is normally on (driven low)
to indicate the presence of a valid 10BASE-T link
when the TPE port is active. The LED will turn off
(driven high) when the link fails. When link integrity is
disabled (LID
(APORT
APORT is disabled (APORT
manually selected (TPE/AUI

e

e

1) while APORT is enabled

1) this LED is turned on (driven low). If

e

0) and the AUI port is

e

0) the LED output is

tristated.

, TxLED,

NOTE:

*TPE/AUI

14

is an output pin when APORTe1.

3.11 Polarity Switching

In TPE mode, the 82503 monitors receive link beats
and end-of-frame delimiters for a possible receiver