INTEL 82433LX, 82433NX User Manual

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82433LX/82433NX

LOCAL BUS ACCELERATOR (LBX)

Supports the Full 64-bit Pentium

Processor Data Bus at Frequencies up to 66 MHz (82433LX and 82433NX)

Drives 3.3V Signal Levels on the CPU Data and Address Buses (82433NX)

Provides a 64-Bit Interface to DRAM and a 32-Bit Interface to PCI

Five Integrated Write Posting and Read Prefetch Buffers Increase CPU and PCI Performance Ð CPU-to-Memory Posted Write Buffer

4 Qwords Deep

Ð PCI-to-Memory Posted Write Buffer

Two Buffers, 4 Dwords Each

Ð PCI-to-Memory Read Prefetch Buffer

4 Qwords Deep

Ð CPU-to-PCI Posted Write Buffer

4 Dwords Deep

Ð CPU-to-PCI Read Prefetch Buffer

4 Dwords Deep

CPU-to-Memory and CPU-to-PCI Write Posting Buffers Accelerate Write Performance

Two 82433LX or 82433NX Local Bus Accelerator (LBX) components provide a 64-bit data path between the host CPU/Cache and main memory, a 32-bit data path between the host CPU bus and PCI Local Bus, and a 32-bit data path between the PCI Local Bus and main memory. The dual-port architecture allows concurrent operations on the host and PCI Buses. The LBXs incorporate three write posting buffers and two read prefetch buffers to increase CPU and PCI performance. The LBX supports byte parity for the host and main memory buses. The 82433NX is intended to be used with the 82434NX PCI/Cache/Memory Controller (PCMC). The 82433LX is intended to be used with the 82434LX PCMC. During bus operations between the host, main memory and PCI, the PCMC commands the LBXs to perform functions such as latching address and data, merging data, and enabling output buffers. Together, these three components form a ‘‘Host Bridge’’ that provides a full function dual-port data path interface, linking the host CPU and PCI bus to main memory.

This document describes both the 82433LX and 82433NX. Shaded areas, like this one, describe the 82433NX operations that differ from the 82433LX.

Dual-Port Architecture Allows Concurrent Operations on the Host and PCI Buses

Operates Synchronously to the CPU and PCI Clocks

Supports Burst Read and Writes of Memory from the Host and PCI Buses

Sequential CPU Writes to PCI Converted to Zero Wait-State PCI Bursts with Optional TRDY

Connection

Byte Parity Support for the Host and Memory Buses Ð Optional Parity Generation for Host

to Memory Transfers

Ð Optional Parity Checking for the

Secondary Cache

Ð Parity Checking for Host and PCI

Memory Reads

Ð Parity Generation for PCI to Memory

Writes

160-Pin QFP Package

December 1995 Order Number: 290478-004

82433LX/82433NX

290478– 1

LBX Simplified Block Diagram

82433LX/82433NX

LOCAL BUS ACCELERATOR (LBX)

CONTENTS PAGE

1.0 ARCHITECTURAL OVERVIEW

1.1 Buffers in the LBX АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 5

1.2 Control Interface Groups ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 7

1.3 System Bus Interconnect ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 7

1.4 PCI TRDYÝInterface ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 8

1.5 Parity Support АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 8

2.0 SIGNAL DESCRIPTIONS ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 8

2.1 Host Interface Signals АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 9

2.2 Main Memory (DRAM) Interface Signals АААААААААААААААААААААААААААААААААААААААААААААААА 10

2.3 PCI Interface Signals АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 10

2.4 PCMC Interface Signals ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 10

2.5 Reset and Clock Signals ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 11

3.0 FUNCTIONAL DESCRIPTION ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 12

3.1 LBX Post and Prefetch Buffers ААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 12

3.1.1 CPU-TO-MEMORY POSTED WRITE BUFFER АААААААААААААААААААААААААААААААААААА 12

3.1.2 PCI-TO-MEMORY POSTED WRITE BUFFER ААААААААААААААААААААААААААААААААААААА 12

3.1.3 PCI-TO-MEMORY READ PREFETCH BUFFER ААААААААААААААААААААААААААААААААААА 12

3.1.4 CPU-TO-PCI POSTED WRITE BUFFER ААААААААААААААААААААААААААААААААААААААААААА 13

3.1.5 CPU-TO-PCI READ PREFETCH BUFFER ААААААААААААААААААААААААААААААААААААААААА 14

3.2 LBX Interface Command Descriptions ААААААААААААААААААААААААААААААААААААААААААААААААА 14

3.2.1 HOST INTERFACE GROUP: HIG[4:0

3.2.2 MEMORY INTERFACE GROUP: MIG[2:0

3.2.3 PCI INTERFACE GROUP: PIG[3:0

3.3 LBX Timing Diagrams АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 21

3.3.1 HIG[4:0]COMMAND TIMING ААААААААААААААААААААААААААААААААААААААААААААААААААААА 21

3.3.2 HIG[4:0]MEMORY READ TIMING АААААААААААААААААААААААААААААААААААААААААААААААА 22

3.3.3 MIG[2:0]COMMAND ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 23

3.3.4 PIG[3:0]COMMAND, DRVPCI, AND PPOUT TIMING ААААААААААААААААААААААААААААА 24

3.3.5 PIG[3:0]: READ PREFETCH BUFFER COMMAND TIMING АААААААААААААААААААААААА 25

3.3.6 PIG[3:0]: END-OF-LINE WARNING SIGNAL: EOL АААААААААААААААААААААААААААААААА 27

3.4 PLL Loop Filter Components АААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 29

3.5 PCI Clock Considerations АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 30

ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 5

]

АААААААААААААААААААААААААААААААААААААААААААА 14

]

АААААААААААААААААААААААААААААААААААААААА 18

]

ААААААААААААААААААААААААААААААААААААААААААААААА 19

CONTENTS PAGE

4.0 ELECTRICAL CHARACTERISTICS

АААААААААААААААААААААААААААААААААААААААААААААААААААААА 31

4.1 Absolute Maximum Ratings АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 31

4.2 Thermal Characteristics ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 31

4.3 DC Characteristics АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 32

4.3.1 82433LX LBX DC CHARACTERISTICS ААААААААААААААААААААААААААААААААААААААААААА 32

4.3.2 82433NX LBX DC CHARACTERISTICS ААААААААААААААААААААААААААААААААААААААААААА 33

4.4 82433LX AC Characteristics ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 35

4.4.1 HOST AND PCI CLOCK TIMING, 66 MHz (82433LX) АААААААААААААААААААААААААААААА 35

4.4.2 COMMAND TIMING, 66 MHz (82433LX) АААААААААААААААААААААААААААААААААААААААААА 36

4.4.3 ADDRESS, DATA, TRDYÝ, EOL, TEST, TSCON AND PARITY TIMING, 66 MHz (82433LX)

АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 37

4.4.4 HOST AND PCI CLOCK TIMING, 60 MHz (82433LX) АААААААААААААААААААААААААААААА 38

4.4.5 COMMAND TIMING, 60 MHz (82433LX) АААААААААААААААААААААААААААААААААААААААААА 38

4.4.6 ADDRESS, DATA, TRDYÝ, EOL, TEST, TSCON AND PARITY TIMING, 60 MHz (82433LX)

АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 39

4.4.7 TEST TIMING (82433LX) ААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 40

4.5 82433NX AC Characteristics ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 40

4.5.1 HOST AND PCI CLOCK TIMING (82433NX) ААААААААААААААААААААААААААААААААААААААА 40

4.5.2 COMMAND TIMING (82433NX) ААААААААААААААААААААААААААААААААААААААААААААААААААА 41

4.5.3 ADDRESS, DATA, TRDYÝ, EOL, TEST, TSCON AND PARITY TIMING (82433NX)

ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 41

4.5.4 TEST TIMING (82433NX) ААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 42

4.5.5 TIMING DIAGRAMS АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 43

5.0 PINOUT AND PACKAGE INFORMATION АААААААААААААААААААААААААААААААААААААААААААААААА 45

5.1 Pin Assignment АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 45

5.2 Package Information АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 50

6.0 TESTABILITY ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 51

6.1 NAND Tree ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 51

6.1.1 TEST VECTOR TABLE ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 51

6.1.2 NAND TREE TABLE АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 51

6.2 PLL Test Mode АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 53

82433LX/82433NX

1.0 ARCHITECTURAL OVERVIEW

The 82430 PCIset consists of the 82434LX PCMC and 82433LX LBX components plus either a PCI/ ISA bridge or a PCI/EISA bridge. The 82430NX PCIset consists of the 82434NX PCMC and 82433NX LBX components plus either a PCI/ISA bridge or a PCI/EISA bridge. The PCMC and LBX provide the core cache and main memory architecture and serves as the Host/PCI bridge. An overview of the PCMC follows the system overview section.

The Local Bus Accelerator (LBX) provides a high performance data and address path for the 82430LX/82430NX PCIset. The LBX incorporates five integrated buffers to increase the performance of the Pentium processor and PCI master devices. Two LBXs in the system support the following areas:

1. 64-bit data and 32-bit address bus of the Pentium processor.

2. 32-bit multiplexed address/data bus of PCI.

3. 64-bit data bus of the main memory.

In addition, the LBXs provide parity support for the three areas noted above (discussed further in Section 1.4).

1.1 Buffers in the LBX

The LBX components have five integrated buffers designed to increase the performance of the Host and PCI Interfaces of the 82430LX/82430NX PCIset.

With the exception of the PCI-to-Memory write buffer and the CPU-to-PCI write buffer, the buffers in the LBX store data only, addresses are stored in the PCMC component.

82433LX/82433NX

290478– 2

NOTES:

1. CPU-to-Memory Posted Write Buffer: This buffer is 4 Qwords deep, enabling the Pentium processor to write back a whole cache line in 4-1-1-1 timing, a total of 7 CPU clocks.

2. PCI-to-Memory Posted Write Buffer: A PCI master can post two consecutive sets of 4 Dwords (total of one cache line) or two single non-consecutive transactions.

3. PCI-to-Memory Read Prefetch Buffer: A PCI master to memory read transaction will cause this prefetch buffer to read up to 4 Qwords of data from memory, allowing up to 8 Dwords to be read onto PCI in a single burst transaction.

4. CPU-to-PCI Posted Write Buffer: The Pentium processor can post up to 4 Dwords into this buffer. The TRDY connect option allows zero-wait state burst writes to PCI, making this buffer especially useful for graphic write operations.

5. CPU-to-PCI Read Prefetch Buffer: This prefetch buffer is 4 Dwords deep, enabling faster sequential Pentium processor reads when targeting PCI.

Figure 1. Simplified Block Diagram of the LBX Data Buffers

82433LX/82433NX

1.2 Control Interface Groups

The LBX is controlled by the PCMC via the control interface group signals. There are three interface groups: Host, Memory, and PCI. These control groups are signal lines that carry binary codes which the LBX internally decodes in order to implement specific functions such as latching data and steering data from PCI to memory. The control interfaces are described below.

1. Host Interface Group: These control signals are named HIG[4:0]and define a total of 29 (30 for the 82433NX) discrete commands. The PCMC sends HIG commands to direct the LBX to perform functions related to buffering and storing host data and/or address.

2. Memory Interface Group: These control signals are named MIG[2:0]and define a total of 7 discrete commands. The PCMC sends MIG commands to direct the LBX to perform functions related to buffering, storing, and retiring data to memory.

3. PCI Interface Group: These control signals are named PIG[3:0]and define a total of 15 discrete commands. The PCMC sends PIG commands to direct the LBX to perform functions related to buffering and storing PCI data and/or address.

1.3 System Bus Interconnect

The architecture of the 82430/82430NX PCIset splits the 64-bit memory and host data buses into logical halves in order to manufacture LBX devices with manageable pin counts. The two LBXs interface to the 32-bit PCI AD[31:0]bus with 16 bits each. Each LBX connects to 16 bits of the AD[31:0]bus and 32-bits of both the MD[0:63]bus and the D[0:63]bus. The lower order LBX (LBXL) connects to the low word of the AD[31:0]bus, while the high order LBX (LBXH) connects to the high word of the AD[31:0]bus.

Since the PCI connection for each LBX falls on 16-bit boundaries, each LBX does not simply connect to either the low Dword or high Dword of the Qword memory and host buses. Instead, the low order LBX buffers the first and third words of each 64-bit bus while the high order LBX buffers the second and fourth words of the memory and host buses.

As shown in Figure 2, LBXL connects to the first and third words of the 64-bit main memory and host data buses. The same device also drives the first 16 bits of the host address bus, A[15:0]. The LBXH device connects to the second and fourth words of the 64-bit main memory and host data buses. Correspondingly, LBXH drives the remaining 16 bits of the host address bus, A[31:16].

Figure 2. Simplified Interconnect Diagram of LBXs to System Buses

290478– 3

82433LX/82433NX

1.4 PCI TRDYÝInterface

The PCI control signals do not interface to the LBXs, instead these signals connect to the 82434LX PCMC component. The main function of the LBXs PCI interface is to drive address and data onto PCI when the CPU targets PCI and to latch address and data when a PCI master targets main memory.

The TRDY

option provides the capability for zerowait state performance on PCI when the Pentium processor performs sequential writes to PCI. This option requires that PCI TRDY

be connected to each LBX, for a total of two additional connections in the system. These two TRDY addition to the single TRDY

connections are in

connection that the

PCMC requires.

1.5 Parity Support

The LBXs support byte parity on the host bus (CPU and second level cache) and main memory buses (local DRAM). The LBXs support parity during the address and data phases of PCI transactions to/ from the host bridge.

2.0 SIGNAL DESCRIPTIONS

This section provides a detailed description of each signal. The signals (Figure 3) are arranged in functional groups according to their associated interface.

The ‘

’ symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When ‘ ent after the signal name, the signal is asserted when at the high voltage level.

The terms assertion and negation are used extensively. This is done to avoid confusion when working with a mixture of ‘active-low’ and ‘active-high’ signals. The term assert,orassertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term ne- gate,ornegation indicates that a signal is inactive.

The following notations are used to describe the signal type.

in Input is a standard input-only signal.

out Totem Pole output is a standard active driver.

t/s Tri-State is a bi-directional, tri-state input/out-

put pin.

’ is not pres-

290478– 4

Figure 3. LBX Signals

82433LX/82433NX

2.1 Host Interface Signals

Signal Type Description

A[15:0]t/s ADDRESS BUS: The bi-directional A[15:0]lines are connected to the address lines of the

D[31:0]t/s HOST DATA: The bi-directional D[31:0]lines are connected to the data lines of the host

HP[3:0]t/s HOST DATA PARITY: HP[3:0]are the bi-directional byte parity signals for the host data

host bus. The high order LBX (determined at reset time using the EOL signal) is connected to A[31:16], and the low order LBX is connected to A[15:0]. The host address bus is common with the Pentium processor, second level cache, PCMC and the two LBXs. During CPU cycles A[31:3]are driven by the CPU and A[2:0]are driven by the PCMC, all are inputs to the LBXs. During inquire cycles the LBX drives the PCI master address onto the host address lines A[31:0]. This snoop address is driven to the CPU and the PCMC by the LBXs to snoop L1 and the integrated second level tags, respectively. During PCI configuration cycles bound for the PCMC, the LBXs will send or receive the configuration data to/from the PCMC by copying the host data bus to/from the host address bus. The LBX drives both halves of the Qword host data bus with data from the 32-bit address during PCMC configuration read cycles. The LBX drives the 32-bit address with either the low Dword or the high Dword during PCMC configuration write cycles.

In the 82433NX, these pins contain weak internal pull-down resistors.

The high order 82433NX LBX samples A11 at the falling edge of reset to configure the LBX for PLL test mode. When A11 is sampled low, the LBX is in normal operating mode. When A11 is sampled high, the LBX drives the internal HCLK from the PLL on the EOL pin. Note that A11 on the high order LBX is connected to the A27 line on the CPU address bus. This same address line is used to put the PCMC into PLL test mode.

data bus. The high order LBX (determined at reset time using the EOL signal) is connected to the host data bus D[63:48]and D[31:16]lines, and the low order LBX is connected to the host data bus D[47:32]and D[15:0]lines. In the 82433LX, these pins contain weak internal pull-up resistors.

In the 82433NX, these pins contain weak internal pull-down resistors.

bus. The low order parity bit HP[0]corresponds to D[7:0]while the high order parity bit HP[3]corresponds to D[31:24]. The HP[3:0 cycles and as parity outputs during read cycles. Even parity is supported and the HP[3:0 signals follow the same timings as D[31:0 internal pull-up resistors.

In the 82433NX, these pins contain weak internal pull-down resistors.

]

signals function as parity inputs during write

]

. In the 82433LX, these pins contain weak

]

82433LX/82433NX

2.2 Main Memory (Dram) Interface Signals

Signal Type Description

MD[31:0]t/s MEMORY DATA BUS: MD[31:0]are the bi-directional data lines for the memory data

MP[3:0]t/s MEMORY PARITY: MP[3:0]are the bi-directional byte enable parity signals for the

bus. The high order LBX (determined at reset time using the EOL signal) is connected to the memory data bus MD[63:48]and MD[31:16]lines, and the low order LBX is connected to the memory data bus MD[47:32]and MD[15:0]lines. The MD[31:0 signals drive data destined for either the host data bus or the PCI bus. The MD[31:0 signals input data that originated from either the host data bus or the PCI bus. These pins contain weak internal pull-up resistors.

memory data bus. The low order parity bit MP[0]corresponds to MD[7:0]while the high order parity bit MP[3]corresponds to MD[31:24]. The MP[3:0]signals are parity outputs during write cycles to memory and parity inputs during read cycles from memory. Even parity is supported and the MP[3:0]signals follow the same timings as MD[31:0]. These pins contain weak internal pull-up resistors.

2.3 PCI Interface Signals

Signal Type Description

AD[15:0]t/s ADDRESS AND DATA: AD[15:0]are bi-directional data lines for the PCI bus. The

TRDY

AD[15:0]signals sample or drive the address and data on the PCI bus. The high order LBX (determined at reset time using the EOL signal) is connected to the PCI bus AD[31:16]lines, and the low order LBX is connected to the PCI AD[15:0]lines.

in TARGET READY: TRDYÝindicates the selected (targeted) device’s ability to complete

the current data phase of the bus operation. For normal operation, TRDYÝis tied asserted low. When the TRDY burst writes), TRDY

should be connected to the PCI bus.

option is enabled in the PCMC (for zero wait-state PCI

]

2.4 PCMC Interface Signals

Signal Type Description

HIG[4:0]in HOST INTERFACE GROUP: These signals are driven from the PCMC and control the

MIG[2:0]in MEMORY INTERFACE GROUP: These signals are driven from the PCMC and control

PIG[3:0]in PCI INTERFACE GROUP: These signals are driven from the PCMC and control the PCI

MDLE in MEMORY DATA LATCH ENABLE: During CPU reads from DRAM, the LBX uses a

DRVPCI in DRIVE PCI BUS: This signals enables the LBX to drive either address or data

host interface of the LBX. The 82433LX decodes the binary pattern of these lines to perform 29 unique functions (30 for the 83433NX). These signals are synchronous to the rising edge of HCLK.

the memory interface of the LBX. The LBX decodes the binary pattern of these lines to perform 7 unique functions. These signals are synchronous to the rising edge of HCLK.

interface of the LBX. The LBX decodes the binary pattern of these lines to perform 15 unique functions. These signals are synchronous to the rising edge of HCLK.

clocked register to transfer data from the MD[31:0]and MP[3:0]lines to the D[31:0]and HP[3:0]lines. MDLE is the clock enable for this register. Data is clocked into this register when MDLE is asserted. The register retains its current value when MDLE is negated.

During CPU reads from main memory, the LBX tri-states the D[31:0]and HP[3:0]lines on the rising edge of MDLE when HIG[4:0

information onto the PCI AD[15:0]lines.

]

NOPC.

82433LX/82433NX

2.4 PCMC Interface Signals (Continued)

Signal Type Description

EOL t/s End Of Line: This signal is asserted when a PCI master read or write transaction is about

PPOUT t/s LBX PARITY: This signal reflects the parity of the 16 AD lines driven from or latched into

to overrun a cache line boundary. The low order LBX will have this pin connected to the PCMC (internally pulled up in the PCMC). The high order LBX connects this pin to a pulldown resistor. With one LBX EOL line being pulled down and the other LBX EOL pulled up, the LBX samples the value of this pin on the negation of the RESET signal to determine if it’s the high or low order LBX.

the LBX, depending on the command driven on PIG[3:0]. The PCMC uses PPOUT from both LBXs (called PPOUT[1:0]) to calculate the PCI parity signal (PAR) for CPU to PCI transactions during the address phase of the PCI cycle. The LBX uses PPOUT to check the PAR signal for PCI master transactions to memory during the address phase of the PCI cycle. When transmitting data to PCI the PCMC uses PPOUT to calculate the proper value for PAR. When receiving data from PCI the PCMC uses PPOUT to check the value received on PAR.

If the L2 cache does not implement parity, the LBX will calculate parity so the PCMC can drive the correct value on PAR during L2 reads initiated by a PCI master. The LBX samples the PPOUT signal at the negation of reset and compares that state with the state of EOL to determine whether the L2 cache implements parity. The PCMC internally pulls down PPOUT[0]and internally pulls up PPOUT[1]. The L2 supports parity if PPOUT[0]is connected to the high order LBX and PPOUT[1]is connected to the low order LBX. The L2 is defined to not support parity if these connections are reversed, and for this case, the LBX will calculate parity. For normal operations either connection allows proper parity to be driven to the PCMC.

2.5 Reset and Clock Signals

Signal Type Description

HCLK in HOST CLOCK: HCLK is input to the LBX to synchronize command and data from the host

PCLK in PCI CLOCK: All timing on the LBX PCI interface is referenced to the PCLK input. All

RESET in RESET: Assertion of this signal resets the LBX. After RESET has been negated the LBX

LP1 out LOOP 1: Phase Lock Loop Filter pin. The filter components required for the LBX are

LP2 in LOOP 2: Phase Lock Loop Filter pin. The filter components required for the LBX are

TEST in TEST: The TEST pin must be tied low for normal system operation.

TSCON in TRI-STATE CONTROL: This signal enables the output buffers on the LBX. This pin must

and memory interfaces. This input is derived from a buffered copy of the PCMC HCLKx output.

output signals on the PCI interface are driven from PCLK rising edges and all input signals on the PCI interface are sampled on PCLK rising edges. This input is derived from a buffered copy of the PCMC PCLK output.

configures itself by sampling the EOL and PPOUT pins. RESET is driven by the PCMC CPURST pin. The RESET signal is synchronous to HCLK and must be driven directly by the PCMC.

connected to these pins.

be held high for normal operation. If TSCON is negated, all LBX outputs will tri-state.

82433LX/82433NX

3.0 FUNCTIONAL DESCRIPTION

3.1 LBX Post and Prefetch Buffers

This section describes the five write posting and read prefetching buffers implemented in the LBX. The discussion in this section refers to the operation of both LBXs in the system.

3.1.1 CPU-TO-MEMORY POSTED WRITE BUFFER

The write buffer is a queue 4 Qwords deep, it loads Qwords from the CPU and stores Qwords to memory. It is 4 Qwords deep to accommodate write-backs from the first or second level cache. It is organized as a simple FIFO. Commands driven on the HIG[4:0 lines store Qwords into the buffer, while commands on the MIG[2:0]lines retire Qwords from the buffer. While retiring Qwords to memory, the DRAM controller unit of the PCMC will assert the appropriate MA,

]

CAS[7:0 track of full/empty states, status of the data and address.

Byte parity for data to be written to memory is either propagated from the host bus or generated by the LBX. The LBX generates parity for data from the second level cache when the second level cache does not implement parity.

3.1.2 PCI-TO-MEMORY POSTED WRITE BUFFER

The buffer is organized as 2 buffers (4 Dwords each). There is an address storage register for each buffer. When an address is stored one of the two buffers is allocated and subsequent Dwords of data are stored beginning at the first location in that buffer. Buffers are retired to memory strictly in order, Qword at a time.

Commands driven on the PIG[3:0]lines post addresses and data into the buffer. Commands driven on HIG[4:0]result in addresses being driven on the host address bus. Commands driven on MIG[2:0 result in data being retired to DRAM.

For cases where the address targeted by the first Dword is odd, i.e. A[2 an even location in the buffer, the LBX correctly aligns the Dword when retiring the data to DRAM. In other words the buffer is capable of retiring a Qword to memory where the data in the buffer is shifted by

, and WEÝsignals. The PCMC keeps

]

1, and the data is stored in

1 Dword (Dword is position 0 shifted to 1, 1 shifted to 2 etc.). The DRAM controller of the PCMC asserts the correct CAS[7:0 C/BE[3:0 Dword.

The End Of Line (EOL) signal is used to prevent PCI master writes from bursting past the cache line boundary. The device that provides ‘‘warning’’ to the PCMC is the low order LBX. This device contains the PCI master write low order address bits necessary to determine how many Dwords are left to the end of the line. Consequently, the LBX protocol uses the EOL signal from the low order LBX to provide this ‘‘end-of-line’’ warning to the PCMC, so that it may retry a PCI master write when it bursts past the cache line boundary. This protocol is described fully in Section 3.3.6.

]

The LBX calculates Dword parity on PCI write data, sending the proper value to the PCMC on PPOUT. The LBX generates byte parity on the MP signals for writing into DRAM.

3.1.3 PCI-TO-MEMORY READ PREFETCH

This buffer is organized as a line buffer (4 Qwords) for burst transfers to PCI. The data is transferred into the buffer a Qword at a time and read out a Dword at a time. The LBX then effectively decouples the memory read rate from the PCI rate to increase concurrence.

Each new transaction begins by storing the first Dword in the first location in the buffer. The starting Dword for reading data out of the buffer onto PCI must be specified within a Qword boundary; that is the first requested Dword on PCI could be an even or odd Dword. If the snoop for a PCI master read results in a write-back from first or second level caches, this write back is sent directly to PCI and main memory. The following two paragraphs describe this process for cache line write-backs.

Since the write-back data from L1 is in linear order,

]

writing into the buffer is straightforward. Only those Qwords to be transferred into PCI are latched into the PCI-to-memory read buffer. For example, if the address targeted by PCI is in the 3rd or 4th Qword in the line, the first 2 Qwords of write back data are discarded and not written into the read buffer. The primary cache write-back must always be written

]

BUFFER

]

signals stored in the PCMC for that

signals depending on the PCI

82433LX/82433NX

completely to the CPU-to-Memory posted Write Buffer.

If the PCI master read data is read from the secondary cache, it is not written back to memory. Writebacks from the second level cache, when using burst SRAMs, are in Pentium processor burst order (the order depending on which Qword of the line is targeted by the PCI read). The buffer is directly addressed when latching second level cache writeback data to accommodate this burst order. For example, if the requested Qword is Qword 1, then the burst order is 1-0-3-2. Qword 1 is latched in buffer location 0, Qword 0 is discarded, Qword 3 is latched into buffer location 2 and Qword 2 is latched into buffer location 1.

Commands driven on MIG[2:0]and HIG[4:0]enter data into the buffer from the DRAM interface and the host interface (i.e. the caches), respectively. Commands driven on the PIG[3:0]lines drive data from the buffer onto the PCI AD[31:0]lines.

Parity driven on the PPOUT signal is calculated from the byte parity received on the host bus or the memory bus, whichever is the source. If the second level cache is the source of the data and does not implement parity, the parity driven on PPOUT is generated by the LBX from the second level cache data. If main memory is the source of the read data, PCI parity is calculated from the DRAM byte parity. Main memory must implement byte parity to guarantee correct PCI parity generation.

3.1.4 CPU-TO-PCI POSTED WRITE BUFFER

The CPU-to-PCI Posted Write Buffer is 4 Dwords deep. The buffer is constructed as a simple FIFO,

with some performance enhancements. An address is stored in the LBX with each Dword of data. The structure of the buffer accommodates the packetization of writes to be burst on PCI. This is accomplished by effectively discarding addresses of data Dwords driven within a burst. Thus, while an address is stored for each Dword, an address is not necessarily driven on PCI for each Dword. The PCMC determines when a burst write may be performed based on consecutive addresses. The buffer also enables consecutive bytes to be merged within a single Dword, accommodating byte, word, and misaligned Dword string store and string move operations. Qword writes on the host bus are stored within the buffer as two individual Dword writes, with separate addresses.

The storing of an address with each Dword of data allows burst writes to be retried easily. In order to retry transactions, the FIFO is effectively ‘‘backed up’’ by one Dword. This is accomplished by making the FIFO physically one entry larger than it is logically. Thus, the buffer is physically 5 entries deep (an entry consists of an address and a Dword of data), while logically it is considered full when 4 entries have been posted. This design allows the FIFO to be backed up one entry when it is logically full.

Commands driven on HIG[4:0]post addresses and data into the buffer, and commands driven on PIG[3:0]retire addresses and data from the buffer and drive them onto the PCI AD[31:0]lines. As discussed previously, when bursting, not all addresses are driven onto PCI.

Data parity driven on the PPOUT signal is calculated from the byte parity received on the host bus. Address parity driven on PPOUT is calculated from the address received on the host bus.

82433LX/82433NX

3.1.5 CPU-TO-PCI READ PREFETCH BUFFER

This prefetch buffer is organized as a single buffer 4 Dwords deep. The buffer is organized as a simple FIFO. reads from the buffer are sequential; the buffer does not support random access of its contents. To support reads of less than a Dword the FIFO read pointer can function with or without a pre-increment. The pointer can also be reset to the first entry before a Dword is driven. When a Dword is read, it is driven onto both halves of the host data bus.

Commands driven on the HIG[4:0]lines enable read addresses to be sent onto PCI, the addresses are driven using PIG[3:0]commands. Read data is latched into the LBX by commands driven on the PIG[3:0]lines and the data is driven onto the host data bus using commands driven on the HIG[4:0 lines.

The LBX calculates Dword parity on PCI read data, sending the proper value to the PCMC on PPOUT. The LBX does not generate byte parity on the host data bus when the CPU reads PCI.

3.2 LBX Interface Command Descriptions

This section describes the functionality of the HIG, MIG and PIG commands driven by the PCMC to the LBXs.

3.2.1 HOST INTERFACE GROUP: HIG[4:0

The Host Interface commands are shown in Table 1. These commands are issued by the host interface of the PCMC to the LBXs in order to perform the following functions:

Reads from CPU-to-PCI read prefetch buffer

when the CPU reads from PCI.

Stores write-back data to PCI-to-memory read

]

prefetch buffer when PCI read address results in a hit to a modified line in first or second level caches.

Posts data to CPU-to-memory write buffer in the

case of a CPU to memory write.

Posts data to CPU-to-PCI write buffer in the case

of a CPU to PCI write.

Drives host address to Data lines and data to ad-

dress lines for programming the PCMC configuration registers.

]

82433LX/82433NX

Table 1. HIG Commands

Command Code Description

NOPC 00000b No Operation on CPU Bus

CMR 11100b CPU Memory Read

CPRF 00100b CPU Read First Dword from CPU-to-PCI Read Prefetch Buffer

CPRA 00101b CPU Read Next Dword from CPU-to-PCI Read Prefetch Buffer, Toggle A

CPRB 00110b CPU Read Next Dword from CPU-to-PCI Read Prefetch Buffer, Toggle B

CPRQ 00111b CPU Read Qword from CPU-to-PCI Read Prefetch Buffer

SWB0 01000b Store Write-Back Data Qword 0 to PCI-to-Memory Read Buffer

SWB1 01001b Store Write-Back Data Qword 1 to PCI-to-Memory Read Buffer

SWB2 01010b Store Write-Back Data Qword 2 to PCI-to-Memory Read Buffer

SWB3 01011b Store Write-Back Data Qword 3 to PCI-to-Memory Read Buffer

PCMWQ 01100b Post to CPU-to-Memory Write Buffer Qword

PCMWFQ 01101b Post to CPU-to-Memory Write and PCI-to-Memory Read Buffer First Qword

PCMWNQ 01110b Post to CPU-to-Memory Write and PCI-to-Memory Read Buffer Next Qword

PCPWL 10000b Post to CPU-to-PCI Write Low Dword

MCP3L 10011b Merge to CPU-to-PCI Write Low Dword 3 Bytes

MCP2L 10010b Merge to CPU-to-PCI Write Low Dword 2 Bytes

MCP1L 10001b Merge to CPU-to-PCI Write Low Dword 1 Byte

PCPWH 10100b Post to CPU-to-PCI Write High Dword

MCP3H 10111b Merge to CPU-to-PCI Write High Dword 3 Bytes

MCP2H 10110b Merge to CPU-to-PCI Write High Dword 2 Bytes

MCP1H 10101b Merge to CPU-to-PCI Write High Dword 1 Byte

LCPRAD 00001b Latch CPU-to-PCI Read Address

DPRA 11000b Drive Address from PCI A/D Latch to CPU Address Bus

DPWA 11001b Drive Address from PCI-to-Memory Write Buffer to CPU Address Bus

ADCPY 11101b Address to Data Copy in the LBX

DACPYH 11011b Data to Address Copy in the LBX High Dword

DACPYL 11010b Data to Address Copy in the LBX Low Dword

PSCD 01111b Post Special Cycle Data

DRVFF 11110b Drive FF..FF (All 1’s) onto the Host Data Bus

PCPWHC 00011b Post to CPU-to-PCI Write High Dword Configuration

NOTE:

All other patterns are reserved.

82433LX/82433NX

NOPC No Operation is performed on the host

bus by the LBX hence it tri-states its host bus drivers.

CMR This command effectively drives

DRAM data onto the host data bus. The LBX acts as a transparent latch in this mode, depending on MDLE for latch control. With the MDLE signal high the CMR command will cause the LBXs to buffer memory data onto the host bus. When MDLE is low. The LBX will drive onto the host bus whatever memory data that was latched when MDLE was negated.

CPRF This command reads the first Dword of

the CPU-to-PCI read prefetch buffer. The read pointer of the FIFO is set to point to the first Dword. The Dword is driven onto the high and low halves of the host data bus.

CPRA This command increments the read

pointer of the CPU-to-PCI read prefetch buffer FIFO and drives that Dword onto the host bus when it is driven after a CPRF or CPRB command. If driven after another CPRA command, the LBX drives the current Dword while the read pointer of the FIFO is not incremented. The Dword is driven onto the upper and lower halves of the host data bus.

CPRB This command increments the read

pointer of the CPU-to-PCI read prefetch buffer FIFO and drives that Dword onto the host bus when it is driven after a CPRA command. If driven after another CPRB command, the LBX drives the current Dword while the read pointer of the FIFO is not incremented. The Dword is driven onto the upper and lower halves of the host data bus.

CPRQ This command drives the first Dword

stored in the CPU-to-PCI read prefetch buffer onto the lower half of the host data bus, and drives the second Dword onto the upper half of the host data bus, regardless of the state of the read pointer. The read pointer is not affected by this command.

SWB0 This command stores a Qword from

the host data lines into location 0 of the PCI-to-Memory Read Buffer. Parity is either generated for the data or propagated from the host bus based on the state of the PPOUT signals sampled at the negation of RESET when the LBXs were initialized.

SWB1 This command, (similar to SWB0),

stores a Qword from the host data lines into location 1 of the PCI-to-Memory Read Buffer. Parity is either generated from the data or propagated from the host bus based on the state of the PPOUT signal sampled at the falling edge of RESET.

SWB2 This command, (similar to SWB0),

stores a Qword written back from the first or second level cache into location 2 of the PCI-to-memory read buffer. Parity is either generated from the data or propagated from the host bus based on the state of the PPOUT signal sampled at the falling edge of RESET.

SWB3 This command stores a Qword from

the host data lines into location 3 of the PCI-to-Memory Read Buffer. Parity is either generated for the data or propagated from the host bus based on the state of the PPOUT signal sampled at the falling edge of RESET.

PCMWQ This command posts one Qword of

data from the host data lines to CPUto-Memory Write Buffer in case of a CPU memory write or a write-back from the second level cache.

PCMWFQ If the PCI Memory read address leads

to a hit on a modified line in the first level cache, then a write-back is scheduled and this data has to be written into the CPU-to-Memory Write Buffer and PCI-to-Memory Read Buffer at the same time. The write-back of the first Qword is done by this command to both the buffers.

PCMWNQ This command follows the previous

command to store or post subsequent write-back Qwords.

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