Intel 317698-001 User Manual

Intel

Design Guide V1.00

June 2007

317698-001

82575 Gigabit Ethernet Controller

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82575 Ethernet Controller Design Guide

Contents

1.0 Introduction ..............................................................................................................1

1.1 Scope ................................................................................................................1

1.2 Reference Documents ..........................................................................................2

2.0 PCI Express Port Connection to the Device ................................................................3

2.1 PCI Express Reference Clock.................................................................................3

2.2 Other PCI Express Signals ....................................................................................3

2.3 Physical Layer Features........................................................................................3

2.3.1 Link Width Configuration ...........................................................................3

2.3.2 Polarity Inversion .....................................................................................4

2.3.3 Lane Reversal ..........................................................................................4

2.4 PCI Express Routing ............................................................................................5

3.0 Ethernet Component Design Guidelines .....................................................................7

3.1 General Design Considerations for Ethernet Controllers ............................................7

3.1.1 Clock Source ...........................................................................................7

3.1.2 Magnetics for 1000 BASE-T........................................................................7

3.2 Designing with the 82575/EB/ES Gigabit Ethernet Controller .....................................8

3.2.1 LAN Disable for 82575 Ethernet Controller Gigabit Ethernet Controller ............. 9

3.2.2 Serial EEPROM ....................................................................................... 10

3.2.3 EEPROM Map Information ........................................................................ 11

3.2.4 FLASH .................................................................................................. 12

3.3 SMBus and NC-SI.............................................................................................. 14

3.4 Power Supplies for the 82575 Ethernet Controller Controllers .................................. 15

3.4.1 82575 Ethernet Controller Power Sequencing............................................. 17

3.4.2 82575 Ethernet Controller Device Power Supply Filtering ............................. 19

3.4.3 82575 Ethernet Controller Controller Power Management and Wake Up ......... 19

3.4.4 Power Management ................................................................................ 20

3.5 82575 Ethernet Controller Device Test Capability................................................... 22

3.6 PHY Functionality .............................................................................................. 22

3.6.1 Auto Cross-over for MDI and MDI-X resolution ........................................... 22

3.6.2 Smartspeed........................................................................................... 23

3.6.3 Flow Control .......................................................................................... 23

3.6.4 Low-Power Link Up ................................................................................. 23

3.6.5 Link Energy Detect ................................................................................. 24

3.6.6 Polarity Correction.................................................................................. 24

3.6.7 Auto-Negotiation differences between PHY, SerDes and SGMII ..................... 25

3.6.8 Copper PHY Link Configuration ................................................................. 25

3.7 Copper/Fiber Switch .......................................................................................... 26

3.8 Device Disable .................................................................................................. 27

3.8.1 BIOS handling of Device Disable............................................................... 28

3.9 Software-Definable Pins (SDPs)........................................................................... 28

4.0 Frequency Control Device Design Considerations..................................................... 30

4.1 Frequency Control Component Types ................................................................... 30

4.1.1 Quartz Crystal ....................................................................................... 30

4.1.2 Fixed Crystal Oscillator............................................................................ 30

4.1.3 Programmable Crystal Oscillators ............................................................. 31

4.1.4 Ceramic Resonator ................................................................................. 31

5.0 Crystal Selection Parameters................................................................................... 32

5.1 Vibrational Mode ............................................................................................... 32

5.2 Nominal Frequency............................................................................................ 32

iii

82575 Ethernet Controller Design Guide

5.3 Frequency Tolerance ..........................................................................................32

5.4 Temperature Stability and Environmental Requirements..........................................32

5.5 Calibration Mode................................................................................................33

5.6 Load Capacitance...............................................................................................33

5.7 Shunt Capacitance .............................................................................................34

5.8 Equivalent Series Resistance ...............................................................................34

5.9 Drive Level .......................................................................................................34

5.10 Aging ...............................................................................................................34

5.11 Reference Crystal ..............................................................................................34

5.11.1 Reference Crystal Selection......................................................................35

5.11.2 Circuit Board..........................................................................................35

5.11.3 Temperature Changes .............................................................................35

6.0 Oscillator Support ....................................................................................................37

6.1 Oscillator Solution..............................................................................................37

7.0 Ethernet Component Layout Guidelines....................................................................39

7.1 Layout Considerations for 82575 Ethernet Controllers .............................................39

7.1.1 Guidelines for Component Placement.........................................................39

7.1.2 Crystals and Oscillators ...........................................................................42

7.1.3 Board Stack Up Recommendations ............................................................43

7.1.4 Differential Pair Trace Routing for 10/100/1000 Designs ..............................44

7.1.5 Signal Trace Geometry for 1000 BASE-T Designs ........................................45

7.1.6 Trace Length and Symmetry for 1000 BASE-T Designs.................................45

7.1.7 Routing 1.8 V to the Magnetics Center Tap.................................................46

7.1.8 Impedance Discontinuities .......................................................................46

7.1.9 Reducing Circuit Inductance .....................................................................46

7.1.10 Signal Isolation ......................................................................................46

7.1.11 Power and Ground Planes ........................................................................47

7.1.12 Traces for Decoupling Capacitors ..............................................................47

7.1.13 Light Emitting Diodes for Designs Based on the 82575 Controller ..................47

7.1.14 Thermal Design Considerations.................................................................48

7.2 Physical Layer Conformance Testing .....................................................................48

7.2.1 Conformance Tests for 10/100/1000 Mbps Designs .....................................48

7.3 Troubleshooting Common Physical Layout Issues ...................................................48

8.0 Thermal Management ..............................................................................................50

9.0 Reference Design Bill of Materials ............................................................................50

10.0 Design and Layout Checklists...................................................................................50

11.0 Reference Schematics ..............................................................................................50

12.0 Symbol.....................................................................................................................50

82575 Ethernet Controller Design Guide

Revision History

Date Revision Description

0.25 Jan 2006 Initial publication of preliminary design guide information.

0.50 July 2006 Added features listings, NC-SI, LED, strapping, pull-up/pull-down information.

0.75 March 2007

1.00 June 2007

Changed classification to “Confidential”; updated crystal layout guidance; removed thermal sensor references; removed password requirements for schematic, checklist, and symbol files; updated EEPROM selection information.

Changed classification to unclassified; removed information regarding Smart Power Down feature; changed signal name from LAN_PWR_GOOD to Internal_Power_On_Reset.

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82575 Ethernet Controller Design Guide

1.0 Introduction

The Intel® 82575 Ethernet Controller is a single, compact component that offers two fully-integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. This device uses the PCI Express* (PCIe) architecture (Rev. 1.1RD). The 82575 enables two-port implementation in a relatively small area and can be used for server and workstation network designs with critical space constraints.

The 82575 provides:

• a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab).

• a Serializer-Deserializer (SERDES) to support 1000Base-SX/LX (optical fiber) and Gigabit backplane applications. Information concerning SERDES can be found in the 82575 Ethernet Controller SERDES Application Note.

• SGMII for SFP/external PHY

• management of MAC and PHY Ethernet layer functions

• management of PCI Express packet traffic across its transaction, link, and physical/ logical layers.

• I/O Acceleration Technologies (I/OAT2). to accelerate the data transactions by hardware means optimizing the TCP flow and reducing the load on the CPU.

In addition, the 82575’s on-board System Management Bus (SMB) ports enable network manageability implementations required by information technology personnel for remote control and alerting via the LAN. With SMB, management packets can be routed to or from a management processor. The SMB ports enable industry standards, such as Intelligent Platform Management Interface (IPMI) and Alert Standard Forum (ASF) 2.0, to be implemented using the 82575. In addition, on-chip ASF 2.0 circuitry provides alerting and remote control capabilities with standardized interfaces. The 82575 Ethernet Controller contains a dedicated microcontroller for manageability with with NC-SI and DMTF support.

The 82575 with PCIe architecture is designed for high-performance and low-hostmemory access latency. The device connects directly to a system Memory Control Hub (MCH) or I/O Controller Hub (ICH) using one, two, or four PCI Express lanes.

Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. Combining a parallel and pipelined logic architecture optimized for ethernet and independent transmit and receive queues, the 82575 efficiently handles packets with minimum latency. The 82575 includes advanced interrupt handling features. It uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors cached on chip. A large 48 KByte on-chip packet buffer maintains superior performance. In addition, using hardware acceleration, the controller offloads tasks from the host, such as TCP/UDP/IP checksum calculations and TCP segmentation.

The 82575 is packaged in 25mm x 25mm, 576-ball grid array.

1.1 Scope

This application note contains Ethernet design guidelines applicable to LOM designs based on PCI Express-supported chipsets.

82575 Ethernet Controller Design Guide

1.2 Reference Documents

This application assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information:

• 82575 Ethernet Controller Product Datasheet. Intel Corporation.

• PCI Express Base Specification, Revision 1.1. PCI Special Interest Group.

• PCI Express Card Electromechanical Specification, Revision 1.0a. PCI Special Interest Group.

• PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special Interest Group.

• IEEE Standard 802.3, 2002 & 2005 Edition. Institute of Electrical and Electronics Engineers (IEEE).

• Incorporates various IEEE standards previously published separately.

• Intel Ethernet Controllers Timing Device Selection Guide, AP-419. Intel Corporation.

• Intel 82575 Ethernet Controller Thermal Design Considerations. Intel Corporation

Note: Intel documentation is subject to frequent revision. Verify with your local Intel sales

office that you have the latest information before finalizing a design.

82575 Ethernet Controller Design Guide

2.0 PCI Express Port Connection to the Device

PCI Express (PCIe*) is a dual simplex point-to-point serial differential low-voltage interconnect. The signaling bit rate is 2.5 Gbps per lane per direction. Each port consists of a group of transmitters and receivers located on the same chip. Each lane consists of a transmitter and a receiver pair. A link between the ports of two devices is a collection of lanes. The device supports up to four lanes on the PCIe interface.

Each signal is 8b/10b encoded with an embedded clock.

The PCI Express topology consists of a transmitter (Tx) located on one device connected through a differential pair connected to the receiver (Rx) on a second device. The controller may be located on the motherboard or on an add-in card using a connector specified by PCI Express.

The lane is AC-coupled between its corresponding transmitter and receiver. The ACcoupling capacitor is located on the board close to transmitter side. Each end of the link is terminated on the die into nominal 100 Ω differential DC impedance. Board termination is not required.

For more information on PCI Express, refer to the PCI Express* Base Specification, Revision 1.1 and PCI Express* Card Electromechanical Specification, Revision 1.1RD.

For information about PCIe power management with the 82575, refer to section 3.4 in this document.

2.1 PCI Express Reference Clock

The device uses a 100 MHz differential reference clock, denoted PE_CLK_P and PE_CLK_N. This signal is typically generated on the system board and routed to the PCI Express port. For add-in cards, the clock will be furnished at the PCI Express connector.

The frequency tolerance for the PCI Express reference clock is +/- 300 ppm.

2.2 Other PCI Express Signals

The device also implements other signals required by the PCI Express specification. The Ethernet controller signals power management events to the system using the PE_WAKE# signal, which operates very similarly to the familiar PCI PME# signal. Finally, there is a PE_RST# signal which serves as the familiar reset function for the controller.

2.3 Physical Layer Features

2.3.1 Link Width Configuration

The device supports a maximum link width of x4, x2, or x1 as determined by the EEPROM Lane_Width field in PCIe init configuration.

The max link width is loaded into the Maximum Link Width field of the PCIe capability Register (LCAP[11:6]). The 82575 Ethernet Controller default is x4 link.

During link configuration, the platform and the 82575 Ethernet Controller negotiate on a common link width. The link width must be one of the supported PCIe link widths (1x, 2x, 4x), such that:

• If Maximum Link Width = x4, then the 82575 Ethernet Controller negotiates to either x4, x2 or x1

• If Maximum Link Width = x2, then the 82575 Ethernet Controller negotiates to either x2 or x1

• If Maximum Link Width = x1, then the 82575 Ethernet Controller only negotiates to x1

2.3.2 Polarity Inversion

If polarity inversion is detected the Receiver must invert the received data.

During the training sequence, the Receiver looks at Symbols 6-15 of TS1 and TS2 as the indicator of lane polarity inversion (D+ and D- are swapped). If lane polarity inversion occurs, the TS1 Symbols 6-15 received will be D21.5 as opposed to the expected D10.2. Similarly, if lane polarity inversion occurs, Symbols 6-15 of the TS2 ordered set will be D26.5 as opposed to the expected D5.2. This provides the clear indication of lane polarity inversion.

2.3.3 Lane Reversal

The following lane reversal modes are supported (see Figure below):

• Lane configuration of x4, x2, and x1

• Lane reversal in x4 and in x2

• Degraded mode (downshift) from x4 to x2 to x1 and from x2 to x1, with one restriction - if lane reversal is executed in x4, then downshift is only to x1 and not to x2.

82575 Ethernet Controller Design Guide

These restrictions require that a x2 interface to the 82575 Ethernet Controller must connect to lanes 0 &1 on the 82575 Ethernet Controller. The PCI Express Card Electromechanical specification does not allow routing a x2 link to a wider connector. Therefore, the system designer is not allowed to connect a x2 link to lanes 2 and 3 of a PCI Express connector. It is also recommended that, when using x2 mode on a network interface card, the 82575 Ethernet Controller be connected to lanes 0 & 1 of the card.

82575 Ethernet Controller Design Guide

3 2 1 0

0 1 2 3

3 2 0

Lane Reversal in x4 mode

Lane Reversal in x2 mode

x x 1 0x2

3 2 1 0

0 1x x

0x x

Reversal

x2 ٛ

3 2 1 0

0 1 2 3

x4 ٛ

Figure 1. Lane Reversal supported modes

Configuration bits: EEPROM "Lane reversal disable" bit - disables lane reversal altogether

2.4 PCI Express Routing

For information regarding the PCIe signal routing, please refer to the Intel PCIe Design Guide. Contact your Intel representative for information.

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82575 Ethernet Controller Design Guide

3.0 Ethernet Component Design Guidelines

These sections provide recommendations for selecting components and connecting special pins.

For 1000 BASE-T designs, the main design elements are the 82575 Gigabit Ethernet Controller, an integrated discrete or magnetics module with RJ-45 connector, an EEPROM, and a clock source.

3.1 General Design Considerations for Ethernet Controllers

Follow good engineering practices with respect to unused inputs by terminating them with pull-up or pull-down resistors, unless the datasheet, design guide or reference schematic indicates otherwise. Do not attach pull-up or pull-down resistors to any balls identified as No Connect. These devices may have special test modes that could be entered unintentionally.

3.1.1 Clock Source

All designs require a 25 MHz clock source. The 82575 Gigabit Ethernet Controller uses the 25 MHz source to generate clocks up to 125 MHz and 1.25 GHz for the PHY circuits, and 1.25 GHz for the SERDES. For optimum results with lowest cost, connect a 25 MHz parallel resonant crystal and appropriate load capacitors at the XTAL1 and XTAL2 leads. The frequency tolerance of the timing device should be 30 ppm or better. Refer to the application note, Intel Fast Ethernet Controllers Timing Device Selection Guide, AP-419, for more information on choosing crystals.

For further information regarding the clock for the 82575, see the sections about frequency control, crystals, and oscillators later in this document.

3.1.2 Magnetics for 1000 BASE-T

Magnetics for the 82575 can be either integrated or discrete.

The magnetics module has a critical effect on overall IEEE and emissions conformance. The device should meet the performance required for a design with reasonable margin to allow for manufacturing variation. Occasionally, components that meet basic specifications may cause the system to fail IEEE testing because of interactions with other components or the printed circuit board itself. Carefully qualifying new magnetics modules prevents this problem.

When using discrete magnetics it is necessary to use Bob Smith termination: Use four 75 Ω resistors for cable-side center taps and unused pins. This method terminates pairto-pair common mode impedance of the CAT5 cable.

Use an EFT capacitor attached to the termination plane. Suggested values are 1500 pF/ 2KV or 1000 pF/3KV. A minimum of 50-mil spacing from capacitor to traces and components should be maintained.

3.1.2.1 Magnetics Module Qualification Steps

The steps involved in magnetics module qualification are similar to those for crystal qualification:

1. Verify that the vendor’s published specifications in the component datasheet meet or exceed the required IEEE specifications.

2. Independently measure the component’s electrical parameters on the test bench, checking samples from multiple lots. Check that the measured behavior is

consistent from sample to sample and that measurements meet the published specifications.

3. Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems. Vary temperature and voltage while performing system level tests.

3.1.2.2 Modules for 1000 BASE-T Ethernet

Magnetics modules for 1000 BASE-T Ethernet are similar to those designed solely for 10/100 Mbps, except that there are four differential signal pairs instead of two. Use the following guidelines to verify specific electrical parameters:

1. Verify that the rated return loss is 19 dB or greater from 2 MHz through 40 MHz for 100/1000 BASE-TX.

2. Verify that the rated return loss is 12 dB or greater at 80 MHz for 100 BASE-TX (the specification requires greater than or equal to 10 dB).

3. Verify that the rated return loss is 10 dB or greater at 100 MHz for 1000 BASE-TX (the specification requires greater than or equal to 8 dB).

4. Verify that the insertion loss is less than 1.0 dB at 100 kHz through 80 MHz for 100 BASE-TX.

5. Verify that the insertion loss is less than 1.4 dB at 100 kHz through 100 MHz for 1000 BASE-T.

6. Verify at least 30 dB of crosstalk isolation between adjacent channels (through 150 MHz).

7. Verify high voltage isolation to 15000 Vrms. (Does not apply to discrete magnetics.)

8. Transmitter OCL should be greater than or equal to 350 μH with 8 mA DC bias.

82575 Ethernet Controller Design Guide

3.1.2.3 Third-Party Magnetics Manufacturers

The following magnetics modules have been used successfully in previous designs..

Manufacturer Part Number

Pulse H5007

Bel (discrete) Bel 0344FLA

3.1.2.4 Layout Guidelines for Use with Integrated and Discrete Magnetics

Layout requirements are slightly different when using discrete magnetics.

These include:

• Ground cut for HV installation (not required for integrated magnetics)

• A maximum of two (2) vias

•Turns less than 45

• Discrete terminators

3.2 Designing with the 82575/EB/ES Gigabit Ethernet Controller

This section provides design guidelines specific to the 82575/EB/ES controller.

82575 Ethernet Controller Design Guide

3.2.1 LAN Disable for 82575 Ethernet Controller Gigabit Ethernet Controller

The 82575 Ethernet Controller device has three signals that can be used for disabling Ethernet functions from system BIOS. LAN0_DIS_N and LAN1_DIS_N are the separated port disable signals and DEV_OFF_N is the device disable signal. Each signal can be driven from a system output port. Choose outputs from devices that retain their values during reset. For example, ICH7 resumes GPIO outputs (GP24, 25, 27, 28) transition high during reset. It is important not to use these signals to drive LAN0_DIS_N or LAN1_DIS_N because these inputs are latched upon the rising edge of PE_RST_N or an inband reset end. The DEV_OFF_N input is completely asynchronous and does not have this restriction.

Each PHY may be disabled if its LAN function's LAN Disable input indicates that the relevant function should be disabled. Since the PHY is shared between the LAN function and manageability, it may not be desired to power down the PHY in LAN Disable. The PHY_in_LAN_Disable EEPROM bit determines whether the PHY (and MAC) are powered down when the LAN Disable pin is asserted. Default is not to power down.

A LAN port may also be disabled through EEPROM settings. If the LAN_DIS EEPROM bit is set, the PHY enters power down. Note, however, that setting the EEPROM LAN_PCI_DIS bit does not bring the PHY into power down.

Table 1. PCI/LAN Function Index

PCI Function #

Both LAN functions are

enabled

LAN 0 is disabled 0 Dummy LAN1

LAN 1 is disabled 0 LAN 0 -

LAN 0 is disabled 1 LAN 1 -

Both LAN functions are

enabled

LAN 1 is disabled 1 Dummy LAN 0

Both LAN functions are

disabled

LAN

Function

Select

0 LAN 0 LAN 1

1 LAN 1 LAN 0

Don’t Care

Function 0 Function 1

All PCI functions are

disabled

Whole Device is at deep

Table 2. Strapping Options for LAN Disable

Symbol Ball # Name and function

This pin is a strapping option pin always active. This pin has an internal weak pull-up

LAN1_DIS_N A15

LAN0_DIS_N B13

resistor. In case this pin is not connected or driven hi during init time, LAN 1 is enabled. In case this pin is driven low during init time, LAN 1 function is disabled. This pin is also used for testing and scan.

This pin is a strapping option pin always active. This pin has an internal weak pull-up resistor. In case this pin is not connected or driven hi during init time, LAN 0 is enabled. In case this pin is driven low during init time, LAN 0 is disabled. This pin is also used for testing and scan.

Table 3. Control Options for LAN Disable

Function Default Control options

82575 Ethernet Controller Design Guide

LAN 0 1

LAN 1 1

3.2.2 Serial EEPROM

The 82575 Ethernet Controller Gigabit Ethernet Controller uses an Serial Peripheral Interface (SPI)* EEPROM. Several words of the EEPROM are accessed automatically by the device after reset to provide pre-boot configuration data before it is accessed by host software. The remainder of the EEPROM space is available to software for storing the MAC address, serial numbers, and additional information. This information is available to the 82575 Ethernet Controller also and is part of the pre-boot configuration data.

The 82575 has a thermal sensor that can send alerts. Trip points for the sensor are set in the EEPROM. For information regarding the use of the sensor and the programming its function in the EEPROM, please refer to the EEPROM Programming Information and Map Application Note.

3.2.2.1 General Regions

The EEPROM is divided into four regions based on the type of access:

• Hardware accessed--this region is accessed by other hardware

• Alert (ASF) accessed--this region is accessed by alert routines

• PT accessed--this region is accessed by the pass-through routines

• Software accessed--this region is accessed by applications

Strapping Option + EEPROM word 20h bit 13 (full/PCI only disable in case of strap)

Strapping Option + EEPROM word 10h bit 13 (full/PCI only disable in case of strap)/ EEPROM Word 10h bit 11 (full disable) / EEPROM word 10h bit 10 (PCI only disable)

3.2.2.2 EEPROM-less Operation

The 82575 can be operated without an EEPROM, however the following conditions apply:

• Non-manageability mode only

82575 Ethernet Controller Design Guide

• Legacy Wake On LAN (magic packets) is not supported

• All the initializations normally loaded from the EEPROM will be loaded by the host driver.

For more information, see the 82575 Gigabit Ethernet Controller Software Developer's Manual and the 82575 EEPROM Information Guide Application Note AP-499.

3.2.2.3 SPI EEPROMs for 82575 Ethernet Controller Controller

SPI EEPROMs that have been found to work satisfactorily with the 82575 device are listed in Ta b le 4 . SPI EEPROMs must be rated for a clock rate of at least 2 MHz.

Table 4. SPI EEPROMs for 82575 Ethernet Controller Controller

Manufacturer Size

Catalyst 32Kb 25C32S 0113A

Catalyst 8Kb 25C08S

Catalyst 64Kb 25C64S 0139B

STM 256Kb 95256W6 K350V

STM 64Kb 95640W6

STM 32Kb 95320W6

STM 16Kb 95160W6

STM 8Kb 95080W6

Motorola 64Kb 25AA640

Motorola 32kb 25AA320

Motorola 16Kb 25AA160A

Manufacturer's Part

Number

Note: Use a 128 kbit EEPROM for all applications until an appropriate size for each application

is determined. Recommended manufacturer and part numbers are Atmel’s AT25128N or Microchip’s 25LC128.

For more information on the various management options refer to Intel’s Application Note 459, 82573/82572/82571/ESB2/82575 LAN Total Cost of Ownership (TCO) System Management Bus Interface.

3.2.3 EEPROM Map Information

The table below summarizes the EEPROM map for the 82575 Ethernet Controller Gigabit Ethernet Controller. For more about the using an EEPROM, see the 82575 Ethernet Controller EEPROM Map and Programming Information Guide, Application Note (AP-nnn).

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