• Spurious and image rejection ratio: More than 70 dB
• Squelch sensitivity (pre-amp OFF):
SSB, CW, RTTY, PSK31Less than 5.6 µ V
FMLess than 1 µV
• RIT variable range: ±9.999 kHz
• Audio output power: More than 2.6 W at 10% distortion with an 8 1 load
• PHONES connector: 3-conductor 6.35 (d) mm (1⁄4w)
• EXT-SP connectors: 2-conductor 3.5 (d) mm (1⁄8w)/8 1
(pre-amp 1 ON)
(pre-amp 1 ON)
(pre-amp 1 ON)
(pre-amp 2 ON)
Antenna tuner
• Matching impedance range: 16.7 to 150 1 unbalanced
(HF bands; VSWR better than 3:1)
20 to 125 1 unbalanced
(50 MHz band; VSWR better than 2.5:1)
• Minimum operating input: 8W (HF bands)
15 W (50 MHz band)
• Tuning accuracy: VSWR 1.5:1 or less
• Insertion loss (after tuning) : Less than 1.0 dB
All stated specifications are typical and subject to change without notice or obligation.
1 - 2
SECTION 2 INSIDE VIEW
(viewing from the bottom)
RF UNIT
MAIN UNIT
PLL UNIT
DIGISEL UNIT
(under the cover)
SCOPE UNIT
OSC UNIT
2 - 1
SECTION 3 CIRCUIT DESCRIPTION
3-1 RECEIVER CIRCUITS
ANT-SW UNIT
Antenna switching relays (RL51, 61, 71, 81) select the RX
signals which are from [ANT1]–[ANT4], and the relays are
controlled by relay controller (IC11). RX signals from [ANT1]
–[ANT3] are applied to the CTRL BOARD, RX signals from
[ANT4] are applied to the RF UNIT directly.
CTRL BOARD
The CTRL BOARD has TX/RX switch which toggles the RF
path between in TX and RX.
RX signals from the ANT-SW UNIT are passed through the
TX/RX switches (RL252–254), and applied to the RF UNIT.
RF UNIT
RF UNIT contains receive circuits; from RX BPF to 2nd
RX IF AMP. The RX signals are filtered by BPFs to remove
unwanted signals and amplified, then down-converted twice
into 2nd IF signal.
The received signals from the ANT-SW UNIT and CTRL
BOARD are passed through some relays and attenuators,
then filtered by BPFs which is assigned to filter the RX
signals that desired to receive. The filtered RX signals are
amplified by RF AMPs before being applied to the 1st mixer.
• 0.03–30 MHz SIGNALS
The RX signals from the band SW (RL351) are passed
though one of the BPF or LPF. The filtered signals are
entered to the DIGISEL UNIT, and gone through or
by-passed the DIGISEL (Digital RF Selector Switch) filter.
When the DIGISEL function is activated, the RX signals
are passed through the DIGISEL SW (RL21) and narrow
bandwidth filter (D_SEL) which filters out unwanted signals
with its sharpen frequency response. The filtered signals are
amplified by the RF AMP (Q201) which recovers the insert
loss of the D_SEL filter, then backed to the RF UNIT via
DIGISEL SW (RL2).
• 30–60 MHz SIGNALS
RX signals from the band SW (RL351) are passed though
one of the BPFs (Fc=50–54 MHz or Fc=54–60 MHz) to
remove unwanted signals.
The filtered signals are amplified by one of (or both of)
the Pre-AMPs (or by-passed; according to the setting).
The amplified RX signals are then applied to the 1st mixer
(Q1211, 1212) via the LPF.
The RX signals are mixed with the 1st LO signals from PLL
UNIT (the 1st LO signals are gone through LO AMP (Q1301),
HPF and LPF before being applied.) to be converted into
the 1st RX IF signal.
A portion of 1st IF signal is applied to the SCOPE UNIT via
buffer (Q1352).
The converted 1st RX IF signal is then filtered by one of 1st
IF filters on the MCF BOARDs (FI1401). Selecting of the
filter to pass is carried out by IF SW (IC1402, 1403). The
filtered 1st RX IF signal is amplified by two 1st IF AMPs
(Q1401–1403), then splitted into two before being applied
to the 2nd mixers; as a image rejection mixer (IC501,
1502). Each divided 1st RX IF signal is mixed with 2nd LO
signals from the PLL UNIT (gone through ATT, LO AMP
(Q1651), buffer (IC1651) and another buffer (IC1651)), to be
converted into the 36 kHz 2nd RX IF signal.
One of the LO signal is 90 degrees phase-shifted before
being applied to the 2nd mixer (IC1502), and the converted
2nd RX IF is 90 degrees phase-shifted too.
These converted 2nd RX IF signals are buffer-amplified
by buffer (IC1502/IC1501) and amplified by 2nd IF AMP
(IC1504/IC1503). Then the 2nd RX IF signals whose phase
is different each other are phase-shifted by the phase shifter
(IC1505), then composed by the composer (IC1505).
The composed 2nd RX IF signal is amplified by another 2nd
IF AMP (IC1506), then entered to the MAIN UNIT.
The RX signals from the DIGISEL UNIT are applied to or
by-passed the Pre-AMP.
When the Pre-AMP1/2 is activated, the RX signals are
applied to the Pre-AMP1 (for all HF bands) or Pre-AMP2
(for 24 MHz and above) via P.AMP SW (RL1004), and the
amplified RX signals are applied to the 1st mixer (IC1051)
via the P.AMP SWs (RL1005, 1006) and LPF.
The RX signals are mixed with the 1st LO signals from
the PLL UNIT (1st LO signals are gone through LO AMPs
(Q1105, 1104, 1101) before being applied.) to be converted
into the 1st RX IF signal.
• FREQUENCY CONFIGURATION
SignalFrequencySignalFrequency
1st RX IF64.455 MHz 1st RX LO64.485–124.455 MHz
2nd RX IF36 kHz2nd RX LO64.491 MHz
1st TX IF36 kHz1st TX LO64.485–124.455 MHz
2nd TX IF455 kHz2nd TX LO64 MHz
3rd TX IF(*)
*; Refer to "SPECIFICATIONS."
3 - 1
MAIN UNIT
MIAN UNIT contains receive circuits; from demodulator
to AF circuits. The 2nd IF signal is demodulated by digital
audio processing circuits.
• DEMODULATOR CIRCUIT
The 36 kHz 2nd RX IF signal from the MAIN UNIT is
applied to the Analog to Digital Converter (ADC; IC1251) via
the IF mute SW (IC1201) and unbalance-balance convert
circuit (IC1211, 1231), to be converted into the 24-bit serial
data. The serial data is applied to the DSP (IC1001) and
processed as digital audio signals. The processed digital
audio signals are then applied to the Digital Audio Converter
(DAC; IC1501) to be converted into the analog audio
signals; as recovered AF signals.
The recovered AF signals are applied to the RX AF circuits
via buffer (IC1751).
• RX AF CIRCUITS
The recovered AF signals are amplified and level-adjusted,
then output from the audio interfaces. (The destination of AF
output signals is depends on the setting)
<OUTPUT FROM Int./Ext. SPEAKER>
The recovered AF signals from the buffer (IC1751) are
passed through the SQL SW (Q351), and applied to the
AF AMP (IC331). The amplified AF signals are splitted into
two AF lines; one is bound for the headphones jack (J2) on
the FRONT UNIT, another is bound for the internal speaker
(SP1)/external speaker via the external SP jack (J751) on
the MAIN UNIT. Both of AF signals on each AF lines are
applied to the 2-channel Voltage Controlled Amplifier (VCA;
IC311) whose gain is determined by applied control voltage
to be adjusted its signal level.
SCOPE UNIT
The 1st RX/TX IF signal from the buffer (Q1352) on the RF
UNIT are passed through the scope IF SW (IC31), scope
ATT, LPF and BPF (dual tuned), and amplified by scope
AMP (Q2) then applied to the 2nd scope mixer (D101).
The 1st IF signal is converted into the 45 MHz 2nd scope IF
signal (S2IF), and filtered to remove unwanted signals, then
amplified by the 2nd scope IF AMPs (Q201 and Q202). The
amplified 2nd scope IF signal is applied to the 3rd scope
mixer (D4) to be converted into the 200 kHz 3rd scope IF
signal. The converted signal is amplified by the 3rd scope IF
AMP (IC401), filtered by the active LPF (IC403), level-limited
by the saturation AMP (IC404). The level-limited signal is
applied to the ADC (IC501) which samples the 200 kHz 3rd
scope IF signal (0–2.5 V) into digital signal, then applied to
the DSP (IC601) as the serial data.
The DSP processes input data, then output to the CPU to
display the frequency and relative signal strength of RX
signals on the spectrum screen.
The level-adjusted AF signals are applied to the AF power
AMP (IC281) which power-amplifies to obtain audio output
power, via LPF (Q291/301).
The power-amplified AF signals are passed through the AF
mute SW (RL261), then applied to the internal speaker (SP1)
via the external SP jack (J751), or an external speaker on
the MAIN UNIT.
When the headphones are connected to the headphones
jack (J2) on the FRONT UNIT, the power-amplified AF
signals from the AF power AMP (IC281) are applied to the
connected headphones.
<TO THE AUDIO STORAGE>
When recording received audio, recovered AF signals from
the buffer (IC1571) are also send to the audio storage
(IC203) on the LOGIC UNIT to be recorded.
<OUTPUT FROM ACC PORT>
The recovered AF signals from the buffer (IC1571) are
amplified by AF AMPs (IC241), the amplified AF signals
are applied to the VCA (IC231) to be adjusted its signal
level. The level-adjusted AF signals are output from [ACC1]
socket.
3 - 2
3-2 TRANSMITTER CIRCUITS
MAIN UNIT
The MAIN UNIT contains transmit circuits; from MIC AMP to
modulator cicuit.
CTRL BOARD
The CTRL BOARD mainly contains circuits for parameter
detection of TX signal; Forward Wave, Reflected wave,
Reactance, Resistance, antenna current and voltage.
• TX AF CIRCUITS
The audio signals from the microphone (MIC signals)
are amplified by MIC AMP (IC171) and level-adjusted by
VCA (IC171). The level-adjusted MIC signals are passed
through the MIC mute SW (IC201) and MIC line selector
(IC211) which selects the MIC line; MIC signals from the
microphone jack on the FRONT UNIT, or from [ACC1]
socket on the MAIN UNIT.
The MIC signals are then applied to the limiter AMP (IC221)
which limits the amplitude of MIC signals. The amplitudelimited MIC signals are applied to the ADC (IC1251) via the
unbalance-balance convert circuit (IC1311, 1321, 1331),
to be converted into the 24-bit serial data. The serial data
is applied to the DSP (IC1001) and processed as digital
audio signals. The processed digital audio signals are then
applied to the Digital to Analog Converter (DAC; IC1501) to
be converted into the analog audio signals; as the 36 kHz
1st TX IF signal. The 1st TX IF signal is entered to the RF
UNIT.
RF UNIT
RF UNIT contains transmit circuits; TX mixers and AMPs.
The 36 kHz 1st TX IF signal from the MAIN UNIT is applied
to the 1st TX mixer (IC503) to be mixed with the 491 kHz
3rd LO signal from the PLL UNIT, to be converted into
the 455 kHz 2nd TX IF signal. The converted 2nd TX IF is
amplified by the 2nd IF AMP (Q501), filtered by 2nd TX IF
filter (FI1501 for BW=20 kHz or FI1502 for BW=4 kHz). The
filtered 2nd TX signal is amplified by 2nd IF AMP (Q504),
and applied to the 2nd TX mixer (D505) to be mixed with the
64 MHz 2nd LO signal from the PLL UNIT, to be converted
into the 64.455 MHz 3rd TX IF signal. The converted 3rd
TX IF signal is passed through the BPF (FI503), amplified
by 3rd IF AMP (Q506), and filtered by the LPF. The filtered
3rd TX IF signal is applied to the 3rd TX mixer (D506) to
be mixed with the 3rd LO signal from the PLL UNIT, to
be converted into the 4th TX IF signal (=TX signal). The
converted TX signal is filtered by the LPF, amplified by RF
AMP (Q508), passed through one of BPFs, then applied to
the YGR AMP (Q801).
TX signal from the FILTER UNIT is passed through several
detection circuits in sequence, then applied to the antenna
[ANT1]–[ANT4].
• FOR (Forward Wave) voltage detection circuit
A portion of TX signal is rectified by current trans (L101) and
diode (D102), and the produced DC voltage is composed
by C103, C106 and C116 to detect FOR voltage (Forward
wave components). The detected voltage is amplified by
IC101 and applied to the A/D port of CPU (IC1).
• REF (Reflected Wave) voltage detection circuit
A portion of TX signal is rectified by current trans (L101) and
diode (D101), and the produced DC voltage is composed by
C102, C105, C115, C120 and C121 to detect REF voltage
(Reflected wave components). The detected voltage is
amplified by IC101 and applied to the A/D port of CPU (IC1).
• Reactance components detection circuit
A portion of TX signal which is detected by current trans
(L151) and TX signal which is divided by C153 and C158
are amplified by C-MOS IC. This AMP, as the first stage,
employs a C-MOS type AMP to detect the low TX signal.
The inverter AMP requires input level lower than others
need, and provides high speed operation for stable high
frequency operation with low TX signal.
The amplified signal is adjusted its wavefor m, then applied
to the IC155 and IC156 for phase comparison. The output
signal is rectified by D153 and D154, composed and
amplified by IC201, then applied to the A/D port of the CPU
(IC1).
• Resistance components detection
A portion of TX signal which is detected by current trans
(L201) and TX signal which is divided by C202, C205 and
C206 are adjusted so that two of these are the same on the
voltage. And two of these are rectified composed each other
to detect the resistance components. When the detected
voltage is increased, Q201 is activated to amplify the signal
for high detection sensitivity.
The amplified TX signal is entered to the PA200W BOARD.
PA200W BOARD
• TX AMPLIFIERS
The TX signal from the RF UNIT is amplified by the RF AMP
(Q101), Pre-drive (Q201), drive (Q301) and power (Q401A,
B) amplifiers in sequence, to obtain TX output power. The
power-amplified TX signal is entered to the FILTER UNIT.
FILTER UNIT
• TX FILTERS
The power-amplified TX signal from the PA200W BOARD
is passed through one of BPFs (according to the TX
frequency) to remove unwanted signals including harmonic
components. The filtered TX signal is then entered to the
CTRL BOARD.
3 - 3
3-3 FREQUENCY SYNTHESIZER CIRCUITS
PLL UNIT
PLL UNIT provides LO signals; 1st LO for TX/RX IF circuits,
2nd RX LO (64.491 MHz), 2nd TX LO (64 MHz), 3rd TX LO
(491 kHz), marker frequency (100 kHz), reference frequency
for the SCOPE UNIT (40 MHz) and clock signal for the DSP
UNIT (12.888 MHz). These LO signals are generated by the
reference signal from the OSC UNIT as reference.
This transeiver employs the Direct Digital Synthesizer (DDS)
which digitally creates arbitrary waveforms and frequencies
from a fixed source frequency, to provide extremely high
resolution and stability frequency and pure wavefor m.
• Reference frequency signal
The 10 MHz reference frequency signal generated on
the OSC UNIT is applied to the 4th harmonic extractor
(Q702, L702, 703) via buffer (Q30) to produce the 40 MHz
reference signal.
• 1st LO signals
The 40 MHz reference signal from the harmonic extractor
is amplified by Q101, and applied to the DDS (IC101)
as the clock signal. The DDS generates the 10.4122038
–10.4963312 MHz sine waves, and these are passed
through the ceramic filter (FI101; Fc=10.7 MHz) to adjust
the wavefor m, then applied to the PLL IC (IC201) via buffer
(Q151).
<2nd TX LO signal>
The VCO output signal from the hybrid divider is passed
through the ATT, and applied to the 2nd LO AMP (Q591).
The amplified VCO output signal is passed through the BPF,
then entered to the RF UNIT as the 2nd TX LO signal.
<2nd RX LO signal>
The VCO output signal from the hybrid divider is passed
through the ATT, and applied to the 2nd LO AMP (Q801).
The amplified VCO output signal is passed through the ATT
and, applied to the 2nd LO mixer (D821) and mixed with
the 491 kHz 3rd TX LO signal from the 3rd TX LO oscillator
(IC651), to convert into the 64.491 MHz 2nd RX LO signal.
The converted 2nd RX LO signal is passed through the
ATT and BPF, and applied to the 2nd LO AMP (Q831). The
amplified signal is entered to the RF UNIT as the 2nd RX
LO signal.
• 3rd TX LO signal
The 40 MHz reference signal from the harmonic extractor
is amplified by IC652, and applied to the DDS (IC565) as
the clock signal. Using the clock signal, the DDS directly
generates the 491 kHz 3rd TX LO signal.
The output signal of DDS is passed through the LPF and
HPF, and applied to the buffer AMP (Q680). The bufferamplified 2rd TX LO signal is entered to the RF UNIT via
ATT.
The PLL IC (IC201) controls the oscillating frequency
of 6 VCOs (VCO1 to VCO6) using the reference signal
generated by the DDS as reference frequency.
The output signals of each VCOs (1st LO signals) are
buffer-amplified by Q301, passed through the HPF and
LPF, then amplified by the 1st LO AMPs (Q302 and Q351).
The amplified 1st LO signals are buffer-amplified by Q352,
passed through the LPF, HPF and ATT, then output to the
RF UNIT as 1st LO signals (64.485–124.455 MHz).
• 2nd LO signals
The 40 MHz reference signal from the harmonic extractor is
amplified by IC503, and applied to the DDS (IC501) as the
clock signal. The DDS generates the reference frequency
which controls the oscillating frequency of 64 MHz VCO
(Q541).
The output signal of 64 MHz VCO (Q541) is buffer-amplified
by Q561, and applied to the hybrid divider.
The hybrid divider divides the VCO output into two; 2nd TX
LO and 2nd RX LO.
• DSP system clock
The 40 MHz reference signal from the harmonic extractor
is amplified by IC1651, and applied to the DDS (IC1652)
as the clock signal. Using the clock signal, the DDS directly
generates 12.288 MHz system clock signal. The system
clock signal is passed through the LPF and HPF, and
applied to the buffer (Q1680). The buffer-amplified system
clock signal is entered to the MAIN UNIT via ATT.
• Scope clock
The 40 MHz reference signal from the harmonic extractor is
amplified by Q1601, and entered to the SCOPE UNIT.
3 - 4
3-4 MAIN CPU (IC604) PORT ALLOCATIONS
Pin
No.
Clock signal to 4094/LMX2306 (PLL UNIT).
42
(DDS for 1st LO PLL-IC/DDS, 2nd TX LO DDS, 3rd TX LO)
"Serial data to 4094/LMX2306 (PLL UNIT).
43
(DDS for 1st LO PLL-IC/DDS, 2nd TX LO DDS, 3rd TX LO)
44 N/C O
45 Mode status (1Lo or T2Lo) output. O
46 Chip select siganl to PLL.I/O
47 Strobe to the PLL. O
51 Clock signal to units other than PLL and SCOPE. O
52 Serial data (other than PLL, SCOPE and DSP). O
53 N/C O
54 CI-V format data (UART). O
55 CI-V format data (UART).I
56 Clock to the DSP IC. O
57 Seral data (TXD/RXD) to the DSP. O
58 START signal to the TUNER UNIT (UART, 9600). O
142 Serial data to the DAC (BU9480) for ext. S-meter. O
140 Clock (A-clock) to the DAC (BU9480) for ext. S-meter. O
138 Clock (B-clock) to the DAC (BU9480) for ext. S-meter. O
137 Power line for liner circuit control signal. O"H"=Power ON
113 Forword wave detected voltage (A/D).I
114 Refl ected wave detected voltage (A/D).I
115 ALC fedback voltage (A/D).I
116 Drain current (fi nal amp.).I
117 Drain voltage (fi nal amp.).I
118 PA UNIT temparature.I
119 Cooling fan motor current.I
120 Voltage from key pad (rear panel). I
133 Serial data to the FRONT CPU (UART, 38400). O
134 Serial data from the FRONT CPU (UART, 38400).I
135 CW/RTTY keying signal to the DSP. O"L"=Key pushed
81 Mute control signal.I"H"=Mute
82 TX power line control signal. O"L"=TX
83 Noise pulse.I
105 RX power line control signal. O"L"=RX
3 Serial communication with the scope DDS (AD9857) detect signal. O"H"=detected
33 Serial data to the SCOPE UNIT DDS/PLL/DSP. O
34 Strobe to the scope PLL (LMX2306). O
59 Chip selet signal to the scope DDS (AD9857). O"L"=AD9875 is slected
60 Profi le (0/1) select signal to the scope DDS (AD9857). O"H"=Profi le 1 is selected.
61 Clock signal to the DDS/PLL/DSP. O
121 DSP data (TXD/RXD).I
122 Hand shake signal from SCOPE DSP.I
123 Extra port for SCOPE DSP.I
124 Serial data from SCOPE DSP.I
125 N/CI
126 Through signal from the TUNER UNIT.I"H"=Through
127 Key input from the tUNER UNIT.I"H"=Tuner ON
128 Straight key input (A/D).I"L"=Key pushed
Description
IN/
OUT
O
O
Condtion
3 - 5
3-4 MAIN CPU (IC604) PORT ALLOCATIONS (continued)
Pin
No.
23 Clock to the EEPRROM (HN58X2464TI). O
24 Serial data from the EEPRROM (HN58X2464TI).I/O
26 Clock signal to the EEPROM (DIGISEL UNIT; CAT24WC256). O
27 Serial data from/to the EEPROM (DIGISEL UNIT; CAT24WC256).I/O
30 RTTY keying.I"H"="space" is marked
31 Transverter control signal from the [ACC] connector.I
21 PLL unlock signal.I"L"=Unlocked
5–
Address bus lines. O
20
73–
Data bus lines.I/O
71
84 WAIT signal (bus line control).I"L"=Wait.
85 SEND signal. O"L"=TX
86 Dual Port SRAM intrude signal.I
87 "L" indicator control signal (bus control). O"L"= lights.
88 "H" indicator control signal (bus control). O"H"= lights.
89 READ data (bus contol). O
90 Address data (bus contol). O
94 PTT/ACC SEND input.I"H"=TX
107 Squelch signal to the [ACC] connector. O
109 Squelch signal. O
35 External SEND (lead relay) signal output. O"H"=Relay ON
36 External SEND (IC relay) signal output. O"H"=Relay ON
37 Chip select signal to the Dual Port SRAM. O"L"=SRAM is selected.
38 Chip select signal to the expander. O
Description
IN/
OUT
"L"= Transverter is
"H"= Squelch open (RX
"L"= Squelch open (Mute
"L"= Expander is
Condtion
activated.
LED lights)
OFF)
selected.
3 - 6
SECTION 4 ADJUSTMENT PROCEDURE
4-1 PREPARATION
¤ REQUIRED EQUIPMENTS
EQUIPMENTSPECIFICATIONEQUIPMENTSPECIFICATION
Spectrum analyzer
RF power
(terminated type)
Frequency Counter
Modulation
Analyzer
Audio Generator
Frequency range : At least 90 MHz
Bandwidth : 100 kHz or more
Measuring range : 10–300 W
Frequency range : 1.8–100 MHz
Impedance : 50
SWR : Less than 1.2 : 1
Frequency range : 0.1–100 MHz
Frequency accuracy :
Input level : Less than 1 mW
Frequency range : 30–300 MHz
Measuring range : 0 to ±10 kHz
Frequency range : 300–3000 Hz
Output level : 1–500 mV
Ω
±0.5 ppm or better
Digital multimeter
Standard Signal
Generator (SSG)
AC MillivoltmeterMeasuring range : 10 mV to 10 V
External Speaker
Attenuator
CAUTION!: BACK UP originally programmed contents (Memory channels, Common settings, etc.) in the transceiver before
starting adjustment. When all adjustments are completed, these contents in the transceiver will be cleared.
Input impedance : 50 kΩ/DC or more
Measuring range : Voltage: 0.1–10V
Current: 5A/30A
Frequency range : 0.1–100 MHz
Output level : 0.1 µV to 32 mV
(–127 to –17 dBm)
Input impedance : 8
Capacity : More than 5 W
Power attenuation : 50 or 60 dB
Capacity : More than 200 W
Ω
¤ EXPOSING UNITS
CAUTION: The transceiver weighs approx. 22.5 kg (50 lb). Always have two people available to carry, lift or turn over the transceiver.
1) Remove 8 screws from the both sides.
2) Remove 7 screws from the bottom, then remove the
bottom cover.
Bottom cover
OSC UNIT cover
RF UNIT cover
PLL/SCOPE UNITs cover
3) Turn over the transceiver.
4) Remove 8 screws from the RF UNIT cover, 10 screws
from the PLL/SCOPE UNITs cover and 10 screws
from the OSC UNIT cover, then remove those covers.
4 - 1
¤ UNITS LOCATION
<Bottom view>
SCOPE UNIT
PLL UNIT
MAIN UNIT
¤ CONNECTIONS
SSG
RF power meter
OSC UNIT
RF UNIT
CAUTION !
DO NOT select an TX adjustment item while an SSG
is connected to the antenna connector.
AC millvolt
meter
RX ANT
Audio
generator
<Rear view>
CW KEY
-
RS
232C
I
REF I/O
10MHz
-
10dBm
SSG
AC
S/P DIF
REMOTE
INOUT
EXT-DISPLAY
15A
ANT 1AN T 2ANT 3ANT 4
DC OUT
INOUT
X-VERTER
15V
MAX1A
METER
EXT
KEYPAD
EXT-SP
ACC
12
GND
ALC
ALCRELAY
ADJ
SINAD METER
(for adjustments on the OSC UNIT)
<Front view>
[MIC]
PTT
4 - 2
4-2 ADJUSTMENTS ON THE OSC UNIT AND PLL UNIT
ADJUSTMENTADJUSTMENT CONDITIONOPERATION
REFERENCE
SIGNAL LEVEL
REFERENCE
SIGNAL LEVEL
(40MHz)
HPL
LOCK VOL T A GE
(VCO1)
(VCO2)2 • Frequency : 14.999 MHz
(VCO3)3 • Frequency : 21.999 MHz
(VCO4)4 • Frequency : 29.999 MHz
(VCO5)5
(VCO6)6 • Frequency : 60.000 MHz
1st LO
OUTPUT LEVEL
2nd LO
LOCK VOL T A GE
RX 2nd LO
LEVEL
TX 2nd LO
LEVEL
1 • Reference signal source :
External
• Receiving
1 • Receiving1) Connect a Spectrum Analyzer to
1 • Frequency : 7.999 MHz
• Mode : USB
• Receiving
• Mode : USB
• Receiving
• Mode : USB
• Receiving
• Mode : USB
• Receiving
• Frequency : 44.999 MHz
• Mode : USB
• Receiving
• Mode : USB
• Receiving
1 • Frequency : 14.999 MHz
• Mode : USB
• Receiving
1 • Frequency : 14.100 MHz
• Mode : USB
• Receiving
1 • Frequency : 14.100 MHz
• Mode : USB
• Receiving
1 • Frequency : 14.100 MHz
• Mode : USB
• T r ansmitting
1) Connect an Standard Signal
Generator to J1071 ([EXT-REF I/O]
terminal on the rear panel) and set
as;