HP HSDL-7001, HSDL-7001-2500 Datasheet

16XCLK

TXD

RCV

OSCIN

OSCOUT

POWERDN

CLK_SEL

GND

PULSEMOD

IR_TXD

IR_RCV

NRST

SIR

ENCODE

SIR

DECODE

TXD IR_TXD

RCD IR_RCV

/NRST

A0 A1 A2

16XCLK

PULSEMOD

CLK_SEL

INT_CLOCK

CLOCK

DIVIDE

IR 3/16 Encode/Decode IC

Technical Data

HSDL-7001-2500 pc, tape

and reel

HSDL-7001#100-100pc,

50/tube

Features

• Compliant with IrDA 1.0 Physical Layer Specs

• Interfaces with IrDA 1.0 Compliant IR Transceivers

• Used in Conjunction with Standard 16550 UART

• Transmits/Receives either

1.63 µs or 3/16 Pulse Mode

• Internal or External Clock Modes

• Programmable Baud Rate

• 2.7-5.5 V Operation

• 16 Pin SOIC Package

Applications

• Interfaces with IR Transceivers in:

- Computer Applications:

Notebook Computers Sub-notebooks Desktop PCs PDAs Printers Dongle or other RS-232

adapter

- Telecom Applications:

Modems Fax Machines Pagers Phones

- Handheld Data Collection:

Industrial Medical Transportation

Description

The HSDL-7001 modulates and demodulates electrical pulses from Hewlett-Packard’s HSDL-1001 Infrared transceiver module and other IrDA-compliant transceivers. The HSDL-7001 can be used with a microcontroller/ microprocessor that has a serial communication interface (UART). Prior to communication, the processor selects the transmission baud rate. Serial data is then transmitted or received at the prescribed data rate.

The HSDL-7001 consists of two state machines – the SIR (Serial InfraRed) Encode and SIR Decode blocks. It also contains a sequential block Clock Divide which synthesizes the required internal signal.

The HSDL-7001 can be placed into the Internal Clock Mode or External Clock Mode. An external crystal is needed for the Internal Clock Mode. In applications where the external 16XCLK signal is provided, a crystal is not needed.

There are two data transmission modes. Data can be transmitted and received in either a standard 3/16 modulation mode or a

1.63 µs pulse mode.

Schematic

Pin Out

I/O Pinout List

Pin Name Type Function

1 16XCLK DIGIN Positive edge triggered input clock that is set to 16 times the data

(SIXTNCK) transmission baud rate. The encode and decode schemes require this

signal. The signal is usually tied to a UART’s BAUDOUT signal. The 16XCLK may be provided by application circuitry if BAUDOUT is not available. This signal is required when the internal clock is not used.

2 /TXD DIGIN Negative edge triggered input signal that is normally tied to the SOUT

signal of the UART (serial data to be transmitted). Data is modulated and output as IR_TXD.

3 RCV DIGOUT Output signal normally tied to SIN signal of a UART (received serial

data). RCV is the demodulated output of IR_RVC. 4 A0 DIGIN Clock Multiplex Signal 5 A1 DIGIN Clock Multiplex Signal 6 A2 DIGIN Clock Multiplex Signal 7 CLK_SEL DIGIN Used to activate either the Internal or External Clock. A high on this

line activates the External clock (16XCLK) and a low activates the

Internal clock. When the External clock is activated, the internal

oscillator is put in POWERDOWN MODE. 8 GND Chip Ground 9 /NRST DIGIN Active low signal used to reset the IrDA-SIR DECODE state machine.

This signal can be tied to POR (Power On Reset) or VCC. This signal can

also be used to disable any data reception.

10 /IR_RCV DIGIN Input from SIR optoelectronics. Input signal is a 3/16th or 1.6 µs pulse

which is demodulated to generate RCV output signal.

11 IR_TXD DIGOUT This is the modulated TXD signal. 12 PULSEMOD DIGIN A high level on this input puts the chip into the monoshot transmit

(with mode. In this mode, when there is a negative transition on the TXD

pulldown) input, a rising edge on the internal transmit modulation state machine

will activate a high pulse on IR_TXD for 6 crystal clock cycles. With a

3.6864 MHz crystal, this corresponds to 1.63 µs. This mode cannot be

used in conjunction with the 16XCLK clock. It is meant to be used with

the external crystal clock. By default, this input pin is pulled to GND.

13 POWERDN DIGIN A high on this input puts only the internal oscillator cell (OSCII) in

(with POWERDOWN MODE. The cell is normally not powered down.

pulldown) 14 OSCOUT ANAOUT Oscillator Output 15 OSCIN ANAIN Oscillator Input 16 V

Power

Note: There are two methods of putting the internal oscillator cell in POWERDOWN MODE. Whenever the CLKSEL Pin is asserted high (External clock selected) the oscillator cell is automatically put in powerdown mode, or whenever the POWERDN Pin is asserted high.

–A–

NOTES:

1. DIMENSIONS A AND B ARE DATUMS AND T IS A DATUM SURFACE.

2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

3. CONTROLLING DIMENSION: MILLIMETER.

4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

–B–

0.25 (0.010)φMTBSAS

–T–

16 PL.

SEATING PLANE

16 9

0.25 (0.010)φMBM

R X 45°

MILLIMETERS INCHES

MIN.

9.80

3.80

1.35

0.35

0.40

1.27 BSC

0.19

0.10 0°

5.80

0.25

MAX.

10.00

4.00

1.75

0.49

1.25

0.25

0.25 7°

6.20

0.50

DIM.

A B C D F G J K M P R

MIN.

0.386

0.150

0.054

0.014

0.016

0.060 BSC

0.008

0.004 0°

0.229

0.010

MAX.

0.393

0.157

0.068

0.019

0.049

0.009

0.009 7°

0.244

0.019

8 PL.

Table 1. Selection of Internal Clock Rate from Crystal Oscillator

Selected Clock Rate (bps) A2 A1 A0 Crystal Freq. Division

115200 0 0 0 Divided by 2

57600 0 0 1 Divided by 4 19200 0 1 0 Divided by 12

9600 0 1 1 Divided by 24

38400 1 0 0 Divided by 6

4800 1 0 1 Divided by 48 2400 1 1 0 Divided by 96

TEST PURPOSE 1 1 1 No division

Package Dimensions

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