HP ELITEBOOK 1040 Schematics

5

www.schematic-x.blogspot.com

4

3

2

1

PCB 10L STACK UP(1.0mm)

2015 Bellagio 1.0, Y0F ,14"UMA Schematics

LAYER 1 : TOP

01

LAYER 2 : SGND
LAYER 3 : IN1(High)

D D

DDR4x16

DDR4x16 DDR4x16 DDR4x16

1866MT/S1866MT/S1866MT/S

1866MT/S

SkyLake U

Memory Down 8GB2GB * 16 * 4Pcs PAGE 16

CHA/B: DDR4 1866 /2133MT/s

DDR4x16 DDR4x16 DDR4x16 DDR4x16

1866MT/S1866MT/S1866MT/S

1866MT/S

Processor

GT2

Processor : Daul Core
Power : 15 (Watt)

eDP X 4

DDI1

DDI2

QHD and FHD

DP
DemultiPlexter

Parade

PS8339A
PAGE 21

DP1

DP2 (HDMI)

HDMI
REPEATER
PS8407A

eDP

DOCKING

PortB

PAGE 22

DOCKING

PortA

PAGE 20

PAGE 45

HDMI Connector

PAGE 23

PAGE 43

LAYER 4 : IN2(High)
LAYER 5 : SGND
LAYER 6 : SVCC
LAYER 7 : IN3(High/Low)
LAYER 8 : IN4(HIGH)
LAYER 9 : SGND
LAYER 10 : BOT

(M Key)

PAGE 40

PAGE 37

PAGE 27

Nuvoton

PAGE 45,46

PAGE 17

SMBUS(SMB_ME0)

I2C1

Thermal IC
EMC1412

24MHz

32.768KHz

SATA0 6GB/s

PCIE:Port 9~12

SOC_I2C3/PS2(EC)

SOC_I2C0

SPI Interface

Share ROM
SPI ROM 16MB

PAGE 47

TPM

Infineon

SLB9670VQ1.2

PAGE 29

PAGE 39

4

SKL PCH-LP

Package : BGA1356
Size : 40 X 24 (mm)

Ball pitch:0.65mm

DOCKING(Quest)

USB2.0 *1 Port
USB3.0 *1 Port
Lan
DP Port*2

USB3.0/2.0:Port6

DOCK LINE IN/OUT

PAGE 2~14

USB3.0/2.0 Interface

USB 3.0 Port 1(USB 2.0 Port 1)

USB3.0/2.0 Interface

USB 3.0 Port 2(USB 2.0 Port 2)

USB3.0/2.0 Interface

USB 3.0 Port 3/5(USB 2.0 Port 5)

USB2.0 Interface

PCIE Gen 1 x 1 Lane

SMB_ME0

HD Audio

Port A/B HP

PAGE 43

SIM Card

WWAN Combo (B Key)

NGFF

WLAN Combo (E Key)

PCIE:Port4

PCIE:Port3

3

USB Charger

Ti TPS2546

PAGE 33

PAGE 33NGFF

Port3

Port7

PAGE 32

Intel LanNPCE576HA0YX

Jacksonville(i219LM)
Vpro/AMT

PAGE 26

Audio Codec

Conexant

CX7501

PAGE 24

TPS2546Ti

PAGE 30

PAGE 30

Port E HP

XDP

USB3.0/2.0 Port

USB3.0/2.0 Port

USB TYPE-C

Smart Card

PAGE 34

Alcor

AU9560

PAGE 34

Port10

Port 8 Port9

Fingerprint

VFS495

PAGE 19

DOCKING

Digital MIC

Combo Jack. AMP.

HPA022642RTJR

Speaker

Camera

PAGE 20

PAGE 45

PAGE 20

PAGE 25

PAGE 24

2

PAGE 15

PAGE 30

PAGE 30

PAGE 42

Cypress CCG1

PAGE 41

EC/I2C1

Audio/B conn.

Apple Type Combo Jack

PAGE 25

NB5

NB5

NB5

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Block Diagram

Block Diagram

Block Diagram

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1 67Tuesday, December 29, 2015

1 67Tuesday, December 29, 2015

1 67Tuesday, December 29, 2015

1A

1A

1A

Memory Down 8GB2GB * 16 * 4Pcs

C C

NGFF SSD
Package : 22*80 (mm)

Power :

Click Pad

NFC NPC100

Touch Screen

B B

Commercial
Debug card

Keyboard

EC BIOS
SPI ROM 8MB

1

PAGE 44

PAGE 35

SPI

PAGE 47

PAGE 20

eSPI interface

LPC/

KBC

Embedded Controller

132QFN

Battery

PAGE 49

A A

Function Conn.

PAGE 28

FAN1/2

PAGE 38

EC Commercial
Debug card

2

PAGE 44

5

5

4

3

2

1

H_TCK 15
H_TDI 15

H_TDO 15
H_TMS 15
H_TRST# 2,15

PCH_TCK 15

PCH_TDI 15

PCH_TDO 15

PCH_TMS 15

H_TRST# 2,15

02

+VCCSFR

D D

C C

B B

SI1B, 0603 change to Install

R648 49.9/F_4
R313 1K/F_4

+3V

R534 10K/F_4
R519 200K_4
R541 10K/F_4
R640 10K/F_4

CATERR#
PM_THRMTRIP#

THERM_SCI#

KBL_DET#
GPS_XMIT_OFF#
OCP_OC#

CPU_PROCHOT#38,56,59,63

PROCHOT_KBC38,45

+VCCSTG

PROCHOT_KBC

R651

*100K_4

R310 1K/F_4

2

H_PROCHOT#

3

Q44
PJE138K

1

R312 499/F_4

C288
47P/50V_4

SI1B, 0528 change to GPP_E7

CPU_PROCHOT#_R

SKL_ULT

CPU MISC

?

4 OF 20

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

JTAGX

B61

H_TCK

D60

H_TDI

A61

H_TDO

C60

H_TMS

B59

H_TRST#

B56

PCH_TCK

D59

PCH_TDI

A56

PCH_TDO

C59

PCH_TMS

C61

H_TRST#

A59

JTAGX_PCH

R774 *0_4/S

H_TCK

SI1, 2/4 add

PV, 0917, change to short pad

?

TP59

EC_PECI45

XDP_BPM015
XDP_BPM115

THERM_SCI#39

OCP_OC#46

KBL_DET#35

GPS_XMIT_OFF#33

EC_PECI

THERM_SCI#
OCP_OC#
KBL_DET#
GPS_XMIT_OFF#

R94 49.9/F_4
R95 49.9/F_4
R183 *49.9/F_4
R184 *49.9/F_4

SI1B, 0525 change to DNI

CATERR#

CPU_PROCHOT#_R

PM_THRMTRIP#

PROC_POPIRCOMP
PCH_OPI_RCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

*SKL_ULT

REV = 1

U29D

D63

Processor pull-up (CPU)

H_TMS
H_TDI
H_TDO

DB1 change, follow Caesar

H_TCK
PCH_TCK

R308 *51_4
R283 *51_4
R307 51_4

R281 51_4

R635 *51_4

+VCCSTG

PCH_TDO
PCH_TMS
PCH_TDI

R637 51_4
R638 51_4
R284 51_4

+VCCSTG

A A

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

+VCCSTG 11,13,62
+VCCSFR 3,11,13,45,56,59,62
+3V 3,4,5,7,8,9,10,15,19,20,21,22,24,27,28,29,37,38,39,40,44,45,48,49,56,62,64

5

NB5

NB5

4

3

2

NB5

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

SKYPAKE (MISC/JTAG)

SKYPAKE (MISC/JTAG)

SKYPAKE (MISC/JTAG)

Date: Sheet of

Date: Sheet of

Date: Sheet

1

2 67Tuesday, December 22, 2015

2 67Tuesday, December 22, 2015

2 67Tuesday, December 22, 2015

of

1A

1A

1A

5

SI2, 7/7

PCH_SPI1_CLK29,45,47
PCH_SPI1_SO29,45,47

PCH_SPI1_SI15,29,45,47
PCH_SPI_IO2_L47
PCH_SPI_IO3_L47

PCH_SPI_CS0#45,47

TP3

SPI_TPM_CS#29

D D

ISO_PREP#43
WWAN_CONFIG_133
WWAN_CONFIG_233
LANLINK_STATUS26

PV, 0826

CL_DATA32

+VCC_ESPI_LPC

PCI_3S_SERIRQ44

CL_CLK32
CL_RST32

PCH_SPI_IO3_L

SI1, 4.22 change to installed for follow Caesar

C C

B B

VCCIO_PG54,60,61,64

PVCORE_PG56,59

SI1, 0407 change R639 to 1K

EC_PWROK46

R529 100K/F_4

R538 10/F_4
R517 0_4

R131 0_4
R117 0_4

ISO_PREP#
WWAN_CONFIG_1
WWAN_CONFIG_2
LANLINK_STATUS

CL_CLK
CL_DATA
CL_RST

R683 10K/F_4

PCI_3S_SERIRQ

R537 *1K/F_4

PV, 0924, uninstall

+3V

2
1

U24

3 5

TC7SH08FU

PLTRST#4,8,29

XDP_DBRESET#15

RSMRST#15,46

H_VCCST_PWRGD

EC_PWROK

DPWROK46,64

SUSWARN#44

SI1, 0311 add

PCH_WAKE#32,33,44

INTLWAKE#26

LAN_DIS#26

DPWROK_R

SI1, 0311 change to 4.7K

R647 4.7K/F_4

+3V_DEEP_SUS

A A

5

PCH_SPI1_CLK_L
PCH_SPI1_SO
PCH_SPI1_SI_L
PCH_SPI_IO2_L
PCH_SPI_IO3_L
PCH_SPI_CS0#_L

SPI_TPM_CS#_L

GPP_D1
GPP_D2

R623 10K/F_4

GPP_A0

4

PCH_PWROK

R502
20K/F_4

PVR, 1008, change back to stuff

PLTRST#
XDP_DBRESET#

R293 *10K/F_4

R285 60.4/F_4

R6391K/F_4

PCH_PWROK

DPWROK DPWROK_R

DB1 CHANGE

R789 *0_4

INTLWAKE#
LAN_DIS#

+VCCSFR

R311
1K/F_4

Q42B
PJX138K

61

H_VCCST_PWRGD

2

PWR_GOOD_3

5

3 4

PJX138K
Q42A

U29E

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

AW13

GPP_A0/RCIN#

AY11

GPP_A6/SERIRQ

*SKL_ULT

REV = 1

C545

*33P/50V_4

R115 0_4

RSMRST#

H_PWRGD
H_VCCST_PWRGD_R

SYS_PWROK60,61

R550 0_4

R528 0_4

SUSWARN#

R110*0_4

SUSACK#

PCH_WAKE#_R

PWR_GOOD_3 15,18,46,64,65

4

?

SPI - FLASH

SPI - TOUCH

C LINK

SKL_ULT

SMBUS, SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

LPC

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

5 OF 20

DB1 EMI suggestion

PCH_SPI1_CLK CL_CLK LPC_ESPI_CLK

C546

*33P/50V_4

DOCK/XDP

U29K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

*SKL_ULT

REV = 1

C547

*33P/50V_4

+3V

PCH_SMBCLK15,43

+3V

PCH_SMBDATA15,43

SKL_ULT

SYSTEM POWER MANAGEMENT

R212 2.2K_4

R239 2.2K_4

?

11 OF 20

DB1 CHANGE

PLTRST#(CLG)

PLTRST#

4

+3V

C853 0.1U/16V_4

2
1

U27

3 5

TC7SH08FU

R718 *0_4

+3V_DEEP_SUS 4,5,6,8,10,15,18,27,32,37,44,45,47,52,54,55,62,64,65
+3VPCU 10,15,18,27,28,30,32,33,35,36,39,41,43,44,45,46,47,48,49,50,51,52,53,54,55,60,61,62,63,64,65,66
+3V_ALW 9,18,36,49,50,53,62,63,64,65
+3V 2,4,5,7,8,9,10,15,19,20,21,22,24,27,28,29,37,38,39,40,44,45,48,49,56,62,64
+VCCSFR 2,11,13,45,56,59,62
+1.2VSUS 6,13,16,17,51,62
+3V_RTC 9,10,33,45

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

4

PCI_PLTRST#

R554

20K/F_4

PCI_PLTRST#

3

R7

PCH_SMB_CLK

R8

PCH_SMB_DATA

R10

TLS_ENCRYPTION

R9

SMB_ME0_CLK

W2

SMB_ME0_DAT

W1

ESPI_LPC#

W3

SMB_PCH_CLK

V3

SMB_PCH_DAT

AM7

R135 *0_4/S

SI2, 6/22

AY13

LAD0_L

BA13

LAD1_L

BB13

LAD2_L

AY12

LAD3_L

BA12
BA11

ESPI_RESET#

AW9

CLK_PCI_EC_R

AY9

CLK_PCI_LPC_R

AW11

CLKRUN#

?

Q7

4 3

1

PJX138K

AT11
AP15
BA16
AY16

AN15

SLP_SUS#

AW15

SLP_LAN#

BB17
AN16

BA15
AY15
AU13

AU11
AP16

AM10
AM11

?

SLP_S4#_3R SLP_S4#_KBC

LAD0_L 44
LAD1_L 44
LAD2_L 44
LAD3_L 44
LFRAME# 44,45
ESPI_RESET# 44

+3V

5

2
6

PVR, 1008, change back to stuff

VRPPM_SLP_S0_N

SLP_S3#_R

R90 0_4

SLP_S4#_R

R526 0_4

SLP_SUS#

R70 0_4

R98 0_4

SLP_WLAN_PCH#
SLP_A#

R527 0_4

PWR_BTN_OUT#
ADP_PRES_OUT
BATLOW#

GPP_A11
SM_INTRUDER#

EXT_PWR_GATE#

GPP_B2

R548 *0_4/S

PV, 0917, change to short pad

PCI_PLTRST# 15,26,29,32,33,40,44,46

3

SMB_ME0_CLK 26,27
SMB_ME0_DAT 26,27

ESPI_LPC# 44

SMB_PCH_CLK 45
SMB_PCH_DAT 45

TPM_PIRQ# 29

R77 22/F_4

PCH_SMB_CLK

PCH_SMB_DATA

PCH_SLP_SUS#
SLP_LAN#SLP_LAN#_R

EXT_PWR_GATE# 18,65

LAN

E

C

VRPPM_SLP_S0_N 15,45,62,65

SLP_S3#_3R 15,18,23,30,43,46,62,64
SLP_S4#_3R 15,18,30,53,62

SLP_S5#_3R 15,41

SLP_LAN# 45,62

TP2

PM_SLP_A# 15,45,64

PWR_BTN_OUT# 46

ADP_PRES_OUT 20,45

BATLOW# 45,46
SM_INTRUDER# 33

R1041M/F_4

+3V_RTC

SLP_S4#_KBC 43,45

2

LPC_ESPI_CLK 44,45
CLK_PCI_LPC_R 44
CLKRUN# 44

PCH_SLP_SUS# 46

2

SMB_PCH_CLK
SMB_PCH_DAT

SMB_ME0_CLK
SMB_ME0_DAT

PCH_SMB_CLK
PCH_SMB_DATA

LANLINK_STATUS

ISO_PREP#

TLS_ENCRYPTION
WWAN_CONFIG_1
WWAN_CONFIG_2

GPP_D1
GPP_D2

SI1, 0412 reserve

ESPI_RESET#

+3V_DEEP_SUS

R6022.2K_4
R6072.2K_4

R598499/F_4
R599499/F_4

Follow 544506

R1862.2K_4

I219 Schematic

R1912.2K_4

R619 10K/F_4

R622 10K/F_4

R177 1K/F_4

R162 10K/F_4

R164 10K/F_4
R798 *100K/F_4
R799 *100K/F_4

R540 100K/F_4

and Layout
Checklists v0.7
suggestion to
change to
499ohm

PCH Pull-high/low(CLG)

BATLOW#
ADP_PRES_OUT
INTLWAKE#
PCH_WAKE#_R
LAN_DIS#

GPP_A11
GPP_A0
SUSACK#

GPP_B2

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

SKYPAKE (SPI/LPC/SMBUS)

SKYPAKE (SPI/LPC/SMBUS)

NB5

NB5

NB5

SKYPAKE (SPI/LPC/SMBUS)

Date: Sheet of

Date: Sheet of

Date: Sheet

1

03

R107 10K/F_4
R547 100K/F_4
R108 10K/F_4
R546 100K/F_4
R67 *10K/F_4

+VCC_ESPI_LPC

R81 *100K/F_4
R525 100K/F_4
R109 *10K/F_4

+3V_DEEP_SUS

R127 100K/F_4

1

+3VPCU

1A

1A

1A

3 67Tuesday, December 22, 2015

3 67Tuesday, December 22, 2015

3 67Tuesday, December 22, 2015

of

5

4

3

2

1

Skylake (GPIO)

?

U29F

LPSS ISH

NFC_DWL_REQ27

D D

SI1, 0422 rename

FPR_OFF19

SI1, 0422 rename

I2C_CLICKPAD_DATA37

DMUX_PD21 CLICKPAD_INT# 37

CAMERA_ON20
NMI_SMI_DBG#44,46
NFC_HOST_INT27

UART0_RXD44
UART0_TXD44
FPR_LOCK#19

TOUCH_INT#20

FPR_OFF

RUNSCI_EC#44

I2C_TS_SDA20

I2C_TS_SCL20

I2C_CLICKPAD_CLK37

SI1, 0318 change for HP command

DB1 change

C C

TP9

NFC_DWL_REQ
DMUX_PD

GPP_B17

CAMERA_ON
NMI_SMI_DBG#
NFC_HOST_INT
BOOT_SPI#

UART0_RXD
UART0_TXD

FPR_LOCK#
TOUCH_INT#

HDD_HALTLED
GPP_C22
RUNSCI_EC#

I2C_TS_SDA
I2C_TS_SCL

I2C_CLICKPAD_DATA
I2C_CLICKPAD_CLK

I2C_CAMERA_DATA
I2C_CAMERA_CLK

GPP_F8
GPP_F9

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

*SKL_ULT

REV = 1

SKL_ULT

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

6 OF 20

GPP_D15/ISH_UART0_RTS#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

PLTRST#3,8,29

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

PLTRST#

RUNSCI_EC#_R45

GPP_D9
GPP_D10
GPP_D11
GPP_D12

?

R591 *0_4

P2

WWAN_TRANSMIT_OFF#

P3

CLICKPAD_INT#

P4

CR_PWREN

P1

BT_OFFNFC_FW_RESET

M4
N3

N1
N2

AD11

GPP_F10

AD12

GPP_F11

U1

GPP_D13

U2

GPP_D14

U3

MPHY_PWREN

U4

WWANSSD_M2

AC1

PCH_LAN_RST#

AC2

PCH_WLAN_RST#

AC3

PCH_SLP_S0IX#

AB4

TOUCH_RST#

AY8

GPP_A18

BA8

GPP_A19

BB7

SWD_CLK_PCH

BA7

SWD_IO_PCH

AY7

SWD_XRES_PCH

AW7
AP13

GPP_A12

R73 *0_4/S

PV, 0917, change to short pad

R592 *0_4

TP10

RUNSCI_EC#

WWAN_TRANSMIT_OFF# 28,33

BT_OFF 32NFC_FW_RESET27

TP40

WWANSSD_M2 33

PCH_SLP_S0IX# 45
TOUCH_RST# 20

SI1B, 0528

SWD_CLK_PCH 41
SWD_IO_PCH 41
SWD_XRES_PCH 41

SX_EXIT_HOLDOFF# 45

GPIO Pull-up/Pull-down(CLG)

GPP_A18
GPP_A19
GPP_A12

WWANSSD_M2
NFC_DWL_REQ
PCH_LAN_RST#
PCH_WLAN_RST#

WWAN_TRANSMIT_OFF#

CR_PWREN
GPP_D13
GPP_D14
BT_OFF

SI1, 0422 DNI

GPP_B17
FPR_OFF
PCH_SLP_S0IX#
NFC_FW_RESET
CAMERA_ON
NMI_SMI_DBG#
MPHY_PWREN
HDD_HALTLED
GPP_C22

SI1, 0422 DNI

I2C_CLICKPAD_DATA
I2C_CLICKPAD_CLK

R74 *100K/F_4
R542 *100K/F_4
R80 *100K/F_4

R165 10K/F_4
R114 *10K/F_4
R596 100K/F_4
R595 100K/F_4
R615 100K/F_4
R613 *10K/F_4
R609 100K/F_4
R610 100K/F_4
R614 *10K/F_4

R120 *10K/F_4
R588 10K/F_4
R594 100K/F_4
R126 10K/F_4
R128 10K/F_4
R121 10K/F_4
R608 10K/F_4
R167 10K/F_4
R168 *8.2K/F_4
R750 2.2K_4
R751 2.2K_4

04

+VCC_ESPI_LPC

+3V_DEEP_SUS

+3V

SI1, 0318 change for HP command

+1.8V

B B

GPP_F8
GPP_F10
I2C_CAMERA_DATA
I2C_CAMERA_CLK

R144 *100K_4
R148 *100K_4
R139 1K/F_4
R744 1K/F_4

CR_PWREN
NFC_FW_RESET
BOOT_SPI#
NFC_DWL_REQ
NFC_HOST_INT
MPHY_PWREN

+1.8V 5,8,24,64,65
+3VPCU 3,10,15,18,27,28,30,32,33,35,36,39,41,43,44,45,46,47,48,49,50,51,52,53,54,55,60,61,62,63,64,65,66
+3V_DEEP_SUS 3,5,6,8,10,15,18,27,32,37,44,45,47,52,54,55,62,64,65
+3V 2,3,5,7,8,9,10,15,19,20,21,22,24,27,28,29,37,38,39,40,44,45,48,49,56,62,64

A A

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

SKYPAKE (GPIO)

SKYPAKE (GPIO)

NB5

NB5

5

4

3

2

NB5

SKYPAKE (GPIO)

Date: Sheet of

Date: Sheet of

Date: Sheet

R612 10K/F_4
R129 *10K/F_4
R130 10K/F_4
R116 100K/F_4
R125 10K/F_4
R611 *10K/F_4

1

1A

1A

1A

4 67Tuesday, December 22, 2015

4 67Tuesday, December 22, 2015

4 67Tuesday, December 22, 2015

of

5

4

3

2

1

BRD_ID TABLE

SKL_ULT

MD_ID48

+VCC_IO

?

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

9 OF 20

DDI1_TX0_N21
DDI1_TX0_P21
DDI1_TX1_N21
DDI1_TX1_P21
DDI1_TX2_N21
DDI1_TX2_P21
DDI1_TX3_N21
DDI1_TX3_P21

DDI2_TX0_N43
DDI2_TX0_P43
DDI2_TX1_N43
DDI2_TX1_P43
DDI2_TX2_N43
DDI2_TX2_P43
DDI2_TX3_N43
DDI2_TX3_P43

DPB_DDCCLK21

DPB_DDCDATA21

DPC_DDCCLK43

DPC_DDCDATA43

WLAN_LED_EN28

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3
CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

?

MD_ID4

GPP_E22

R156 24.9/F_4

WLAN_LED_EN

C37
D37
C32
D32
C29
D29
B26
A26

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

DDI1_TX0_N
DDI1_TX0_P
DDI1_TX1_N
DDI1_TX1_P
DDI1_TX2_N
DDI1_TX2_P
DDI1_TX3_N
DDI1_TX3_P

DDI2_TX0_N
DDI2_TX0_P
DDI2_TX1_N
DDI2_TX1_P
DDI2_TX2_N
DDI2_TX2_P
DDI2_TX3_N
DDI2_TX3_P

DPB_DDCCLK
DPB_DDCDATA

DPC_DDCCLK
DPC_DDCDATA

eDP_RCOMP

SI1, 0422 rename

GPP_D4

BRD_ID2
BRD_ID3
BRD_ID4
PLT_ID1
PLT_ID2
PLT_ID3
SG_IN
MD_ID1

MD_ID2
MD_ID3
BRD_ID1

U29A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

*SKL_ULT

REV = 1

+1.8V

+1.8V

+1.8V

+1.8V

SKL_ULT

DDI

DISPLAY SIDEBANDS

SI1, 0422 DNI

GPP_D4

R563 100K/F_4
R565 100K/F_4
R567 *100K/F_4
R569 *100K/F_4

R584 *10K/F_4
R585 *10K/F_4
R587 10K/F_4
R143 10K/F_4

R572 *100K_4
R577 100K/F_4
R576 *100K/F_4

R579 *10K/F_4

R579 SWITCHABLE GRAPHICS ENABLE
R581 SWITCHABLE GRAPHICS DISABLE

?

1 OF 20

EDP

R645 *10K/F_4

BRD_ID1
BRD_ID2
BRD_ID3
BRD_ID4

MD_ID1
MD_ID2
MD_ID3
MD_ID4

PLT_ID1
PLT_ID2
PLT_ID3

SG_IN

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

R564 *100K/F_4
R562 *100K/F_4
R568 100K/F_4
R570 100K/F_4

R583 10K/F_4
R586 10K/F_4
R589 *10K/F_4
R137 *10K/F_4

R571 100K/F_4
R578 *100K_4
R580 100K_4

R581 10K/F_4

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52
G50

F50
E48
F48
G46
F46

L9

HDMI_HPD_CON

L7

DDI2_HPD_CON

L6

RTD3_WAKE#

N9

EXT_SMI#

L10
R12

R11
U13

?

+3V

INT_eDP_TXN0
INT_eDP_TXP0
INT_eDP_TXN1
INT_eDP_TXP1
INT_eDP_TXN2
INT_eDP_TXP2
INT_eDP_TXN3
INT_eDP_TXP3

INT_eDP_AUXN
INT_eDP_AUXP

EDP_DISP_UTIL
INT_DDI1_AUXN

INT_DDI1_AUXP
INT_DDI2_AUXN
INT_DDI2_AUXP

INT_eDP_HPD_Q

PCH_LVDS_BLON
PCH_DPST_PWM
PCH_DISP_ON

DB1

DB2

SI1

SI2

PV

PVR

MV

INT_eDP_TXN0 20
INT_eDP_TXP0 20
INT_eDP_TXN1 20
INT_eDP_TXP1 20
INT_eDP_TXN2 20
INT_eDP_TXP2 20
INT_eDP_TXN3 20
INT_eDP_TXP3 20

INT_eDP_AUXN 20
INT_eDP_AUXP 20

TP51

INT_DDI1_AUXN 21
INT_DDI1_AUXP 21
INT_DDI2_AUXN 43
INT_DDI2_AUXP 43

HDMI_HPD_CON 21
DDI2_HPD_CON 43

EXT_SMI# 45

INT_eDP_HPD_Q 20

PCH_LVDS_BLON 20

PCH_DPST_PWM 20

PCH_DISP_ON 20

DB0

BRD_ID1

DB1
DB2

SI1
SI1B
SI2

BRD_ID2 BRD_ID3 BRD_ID4
0 0 0 0
0 0 0
0 0
0

0
1
1 1

1
1 1
0 00
00
11

110
PV1 0 0 0
PVR

MV

1
1
1
1
1
1
1

0 0
0
0
1
1
1

1 0

0

0

1

1

Follow Promate's suggestion to change to 10K

DPB_DDCCLK
DPB_DDCDATA
DPC_DDCCLK
DPC_DDCDATA

1
0

00
1

Bellagio 14
Skylake U & Y

VPRO

Bellagio 14
S

kylake U & Y

NON-VPRO

1

11
0
1
0
111

DB1

DB2

MICRON 4G
SAMSUNG 4G
MICRON 8G
SAMSUNG 8G
MICRON 16G
SAMSUNG 16G

R19310K/F_4
R20810K/F_4
R2202.2K_4
R2072.2K_4

PLT_ID TABLE

PLT_ID1

PLT_ID2 PLT_ID3

0 1 0

1 1 0

SI1, 0422 ADD

MEMORY_ID TABLE

MD_ID1 MD_ID2 MD_ID3 MD_ID4

0
0
0
0
0
0

0 0
0
0
0
1

1 0
0
0

RTD3_WAKE#
EXT_SMI#

+3V

GPP_E22

HDMI_HPD_CON
DDI2_HPD_CON
WLAN_LED_EN

R259 100K/F_4
R252 100K/F_4
R187 100K/F_4

SI, 3/23 add for HP command

0
1
1
0

1
0
1
0
1
01 1
11 1

+3V_DEEP_SUS

R176100K/F_4
R178100K/F_4
R172100K/F_4

0

05

U29I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

D D

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

*SKL_ULT

REV = 1

C C

For DOCK & HDMI

For DOCK & HDMI

For DOCK & HDMIFor DOCK & HDMI

For DOCK

For DOCK

For DOCK

For DOCK

B B

SI, 3/23 add for HP command

eDP_COMPIO and ICOMPO signals should be shorted
near balls and routed with typical impedance <25 mohms

A A

PROJECT : Y0F

PROJECT : Y0F

+VCC_IO 13,15,38,54
+3V_DEEP_SUS 3,4,6,8,10,15,18,27,32,37,44,45,47,52,54,55,62,64,65
+3V 2,3,4,7,8,9,10,15,19,20,21,22,24,27,28,29,37,38,39,40,44,45,48,49,56,62,64

5

NB5

NB5

4

3

2

NB5

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

SKYPAKE (eDP/DDI/eMMC)

SKYPAKE (eDP/DDI/eMMC)

SKYPAKE (eDP/DDI/eMMC)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

5 67Tuesday, December 22, 2015

5 67Tuesday, December 22, 2015

5 67Tuesday, December 22, 2015

1A

1A

1A

5

M_A_DQ[63:0]16

M_B_DQ[63:0]17

M_A_DQSN[7:0]16

M_A_DQSP[7:0]16

M_B_DQSN[7:0]17

M_B_DQSP[7:0]17

D D

C C

B B

SkyLake ULT Processor (DDR4-A)

SKL_ULT

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

U29B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

*SKL_ULT

REV = 1

4

?

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]

DDR0_ODT[0]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

NIL-DDR CH ­A

2 OF 20

DDR0_ODT[1]

DDR0_MA[3]
DDR0_MA[4]

DDR0_DQSN[0]

DDR0_DQSP[0]

DDR0_DQSN[1]

DDR0_DQSP[1]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]

DDR0_ALERT#

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

DDR0_PAR

AU53
AT53
AU55
AT55

BA56
BB56
AW56
AY56

AU45
AU43
AT45
AT43

BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54

AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52

AM70
AM69
AT69
AT70
AH66
AH65
AG69
AG70
BA64
AY64
AY60
BA60
AR66
AR65
AR61
AR60

AW50
AT52

AY67
AY68
BA67

AW67

?

M_A_CLKN0 16
M_A_CLKP0 16

M_A_CKE0 16

M_A_CS#0 16
M_A_ODT0 16

M_A_A5
M_A_A9
M_A_A6
M_A_A8
M_A_A7

M_A_A12
M_A_A11
DDRA_ACT#
M_A_BG#1

M_A_A13
M_A_A15
M_A_A14
M_A_A16

M_A_A2
M_A_A10

M_A_A1
M_A_A0
M_A_A3
M_A_A4

M_A_DQSN0
M_A_DQSP0
M_A_DQSN1
M_A_DQSP1
M_A_DQSN2
M_A_DQSP2
M_A_DQSN3
M_A_DQSP3
M_A_DQSN4
M_A_DQSP4
M_A_DQSN5
M_A_DQSP5
M_A_DQSN6
M_A_DQSP6
M_A_DQSN7
M_A_DQSP7

DDR0_ALERT#
DDR0_PAR

SM_VREF

SMDDR_VREF_DQ1_M3

20mils width

DDR_PG_CNTL

SM_VREF

M_A_A5 16
M_A_A9 16
M_A_A6 16
M_A_A8 16
M_A_A7 16
M_A_BG#0 16
M_A_A12 16
M_A_A11 16
DDRA_ACT# 16
M_A_BG#1 16

M_A_A13 16
M_A_A15 16
M_A_A14 16
M_A_A16 16
M_A_BS#0 16
M_A_A2 16
M_A_BS#1 16
M_A_A10 16
M_A_A1 16
M_A_A0 16
M_A_A3 16
M_A_A4 16

DDR0_ALERT# 16

DDR0_PAR 16
SM_VREF 16
SMDDR_VREF_DQ1_M3 17

3

2

1

06

SkyLake ULT Processor (DDR4-B)

?

SKL_ULT

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]

DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

NIL-DDR CH ­B

3 OF 20

DDR1_ODT[1]

DDR1_DQSP[5]/DDR1_DQSP[3]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR1_ALERT#

DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]

DDR1_MA[3]
DDR1_MA[4]

DDR1_PAR

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47

BA38
AY38
AY34
BA34
AT38
AR38
AT32
AR32
BA30
AY30
AY26
BA26
AR25
AR27
AR22
AR21

AN43
AP43
AT13
AR18
AT18
AU18

?

M_B_A5
M_B_A9
M_B_A6
M_B_A8
M_B_A7

M_B_A12
M_B_A11
DDRB_ACT#
M_B_BG#1

M_B_A13
M_B_A15
M_B_A14
M_B_A16

M_B_A2
M_B_A10

M_B_A1
M_B_A0
M_B_A3
M_B_A4

M_B_DQSN0
M_B_DQSP0
M_B_DQSN1
M_B_DQSP1
M_B_DQSN2
M_B_DQSP2
M_B_DQSN3
M_B_DQSP3
M_B_DQSN4
M_B_DQSP4
M_B_DQSN5
M_B_DQSP5
M_B_DQSN6
M_B_DQSP6
M_B_DQSN7M_B_DQ53
M_B_DQSP7

DDR1_ALERT#

DDR1_PAR
SM_DRAMRST#_CPU
SM_RCOMP_0

R91 200/F_4

SM_RCOMP_1

R92 80.6/F_4

SM_RCOMP_2

R93 100/F_4

M_B_CLKN0 17
M_B_CLKP0 17

M_B_CKE0 17

M_B_CS#0 17
M_B_ODT0 17

M_B_A5 17
M_B_A9 17
M_B_A6 17
M_B_A8 17
M_B_A7 17
M_B_BG#0 17
M_B_A12 17
M_B_A11 17
DDRB_ACT# 17
M_B_BG#1 17

M_B_A13 17
M_B_A15 17
M_B_A14 17
M_B_A16 17
M_B_BS#0 17
M_B_A2 17
M_B_BS#1 17
M_B_A10 17
M_B_A1 17
M_B_A0 17
M_B_A3 17
M_B_A4 17

R64 *0_4/S

DDR1_ALERT# 17

DDR1_PAR 17

SI2, 6/22

DDR_DRAMRST# 16,17

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52

M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

U29C

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

*SKL_ULT

REV = 1

DDR4 SODIMM ODT GENERATION

+3V_DEEP_SUS

R560
10K/F_4

A A

DDR_PG_CNTL

5

DB1 change to 10k

R566 10K/F_4

Q34

2

PMST3904

1 3

DB1 change to 2N3904 type

R575
100K/F_4

+3V_DEEP_SUS

2

4

R558
10K/F_4

3

Q30
PJE138K

1

DDR_VTT_PG_CTRL 18,51

R553
*100K/F_4

C1010
47P/50V_4

SI1B, 0603, close U29.AY67

SM_DRAMRST#_CPU

+1.2VSUS

3

R84
470/F_4

C59
*0.1U/16V_4

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

SKYPAKE (DDR4-A/B I/F)

SKYPAKE (DDR4-A/B I/F)

NB5

NB5

2

NB5

SKYPAKE (DDR4-A/B I/F)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

6 67Tuesday, December 22, 2015

6 67Tuesday, December 22, 2015

6 67Tuesday, December 22, 2015

5

3,4,5,6,8,10,15,18,27,32,37,44,45,47,52,54,55,62,64,65

2,3,4,5,8,9,10,15,19,20,21,22,24,27,28,29,37,38,39,40,44,45,48,49,56,62,64

4

3

2

1

07

?

U29H

D D

USB30_RX5-42
USB30_RX5+42

TYPE C-1

PCIE_RXN3_LAN26
PCIE_RXP3_LAN26

LAN

PCIE_TXN3_LAN26
PCIE_TXP3_LAN26

PCIE_RXN4_WLAN32

PCIE_RXP4_WLAN32

W

LAN

PCIE_TXN4_WLAN32

PCIE_TXP4_WLAN32

USB30_TX5-42
USB30_TX5+42

C494 0.1U/16V_4
C493 0.1U/16V_4

C477 0.1U/16V_4
C478 0.1U/16V_4

PCIE_TXN3_LAN_C
PCIE_TXP3_LAN_C

PCIE_TXN4_WLAN_C
PCIE_TXP4_WLAN_C

SI1, 2/9 change port

C C

PCIE_RXN9_SSD40
PCIE_RXP9_SSD40

SSD

PCIE_TXN9_SSD40

PCIE_TXP9_SSD40

PCIE_RXN10_SSD40
PCIE_RXP10_SSD40

SSD

PCIE_TXN10_SSD40
PCIE_TXP10_SSD40

B B

SSD

SSD

PCIE_RXN11_SSD40
PCIE_RXP11_SSD40

PCIE_TXN11_SSD40

PCIE_TXP11_SSD40
PCIE_RXN12_SSD40
PCIE_RXP12_SSD40

PCIE_TXN12_SSD40

PCIE_TXP12_SSD40

H_PRDY#15

H_PREQ#15

C480 0.22U/10V_4
C479 0.22U/10V_4

C496 0.22U/10V_4
C497 0.22U/10V_4

R240 100/F_4

C498 0.22U/10V_4
C499 0.22U/10V_4

C481 0.22U/10V_4
C482 0.22U/10V_4

PCIE_TXN9_SSD_C
PCIE_TXP9_SSD_C

PCIE_TXN10_SSD_C
PCIE_TXP10_SSD_C

PCIE_RCOM_R
PCIE_RCOM_L

GPP_A7

PCIE_TXN11_SSD_C
PCIE_TXP11_SSD_C

PCIE_TXN12_SSD_C
PCIE_TXP12_SSD_C

DB1 change to 0.22u for support GEN 3

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

*SKL_ULT

REV = 1

SKL_ULT

SSIC / USB3

USB2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

8 OF 20

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN

USB3_1_TXP

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN

USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP

USB3_4_RXN
USB3_4_RXP
USB3_4_TXN

USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E8/SATALED#

?

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6

USB_BIAS

AG3

USB2_ID

AG4

USB2_VBUSSENSE

A9

DGPU_HOLD_RST#

C9

DGPU_PRSNT#

D9

DGPU_PWR_EN

B9

DGPU_PWROK

J1
J2

SC_PWRSV#

J3
H2

DOCK_ID1

H3
G4

mSATA_DET#

H1

SATA_LED#

USB30_RX1­USB30_RX1+
USB30_TX1­USB30_TX1+

USB30_RX2­USB30_RX2+
USB30_TX2­USB30_TX2+

USBP1­USBP1+

USBP2­USBP2+

USBP3­USBP3+

USBP4­USBP4+

USBP5­USBP5+

USBP7­USBP7+

USBP8­USBP8+

USBP9­USBP9+

USBP10­USBP10+

R169 113/F_4

DEVSLP0
DEVSLP2

SATA_LED# 40

USB30_RX1- 30

USB30_RX1+ 30

USB30_TX1- 30

USB30_TX1+ 30
USB30_RX2- 30

USB30_RX2+ 30

USB30_TX2- 30

USB30_TX2+ 30
USB30_RX3- 42

USB30_RX3+ 42

USB30_TX3- 42

USB30_TX3+ 42
USB30_RX4- 43

USB30_RX4+ 43

USB30_TX4- 43

USB30_TX4+ 43

USBP1- 30
USBP1+ 30

USBP2- 30
USBP2+ 30

USBP3- 33
USBP3+ 33

USBP4- 43
USBP4+ 43

USBP5- 42
USBP5+ 42

USBP7- 32
USBP7+ 32

USBP8- 19
USBP8+ 19

USBP9- 20
USBP9+ 20

USBP10- 34
USBP10+ 34

TIE TRACES TOGETHER
CLOSE TO PINS WITH LENGTH
TO RESISTOR

TP42

SC_PWRSV# 34
DEVSLP2 40

DOCK_ID1 21,43

mSATA_DET# 40

USB3.0 (M/B Right side)

USB3.0 (M/B Left side)

TYPE C-2

USB3.0 (DOCK)

USB2.0(M/B Right side)
USB2.0(M/B Left side)

WWAN

Dock

USB type-c

BT

FPR

Camera

Smart Card

(USBP3)
(

USBP4)

(USBP5)

(USBP7)
(USBP8)

SBP9)

(U
(USBP10)

DG require 113 Ohm +/- 1%

LED3

*WHITE

(USBP1)
(USBP2)

SI1, 1/8, follow Intel DG non-support OTG

R790 *360_6

21

SATA_LED#_R_1SATA_LED#

MV, 1130 change to un-stuff

DOCK_ID1
SC_PWRSV#
mSATA_DET#
DEVSLP0
DEVSLP2

SATA_LED#
DGPU_HOLD_RST#

DGPU_PWROK

SI1, 0429 change to DNI

GPP_A7

DGPU_PRSNT#
DGPU_PWR_EN
USB2_ID
USB2_VBUSSENSE

1 2

+3V

+3V

R62610K/F_4
R61610K/F_4

R625100K/F_4
R617*10K/F_4
R621*10K/F_4

R62410K/F_4

R198*10K/F_4

R641*10K/F_4

+VCC_ESPI_LPC

R545100K/F_4

+3V

R64210K/F_4

SI1, 0429 change to DNI

R643*10K/F_4

R644*10K/F_4
R7651K/F_4
R7661K/F_4

A A

+3V_DEEP_SUS
+3V

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

5

Custom

SKYPAKE (PCIE/USB)

SKYPAKE (PCIE/USB)

NB5

NB5

4

3

2

NB5

SKYPAKE (PCIE/USB)

Date: Sheet of

Date: Sheet of

Date: Sheet

1

1A

1A

1A

7 67Tuesday, December 22, 2015

7 67Tuesday, December 22, 2015

7 67Tuesday, December 22, 2015

of

5

2,3,4,5,7,9,10,15,19,20,21,22,24,27,28,29,37,38,39,40,44,45,48,49,56,62,64

ACZ_SYNC_AUDIO24

BIT_CLK_AUDIO24

D D

SI2, 0622

C C

ACZ_SDIN024

ACZ_RST#_AUDIO24

R552 33_4
R530 33_4

R531 *0_4/S

R551 33_4

TOUCH_PWR_EN20

WLAN_TRANSMIT_OFF#32

A_3S_ICHSPKR24

ACZ_SDO

Q33

PJE138K

TP5

3

2

4

ACZ_SYNC
ACZ_BCLK
ACZ_SDO

ACZ_RST#
TOUCH_PWR_EN

GPP_F1
AMD_VBIOS_SEL#
GPP_F2
GPP_F3

GPP_D19
GPP_D20

WLAN_TRANSMIT_OFF#

A_3S_ICHSPKR

+5V

R574

10K/F_4

ACZ_SDOUT_G

U29G

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

*SKL_ULT

AUDIO

REV = 1

SKL_ULT

3

?

SDIO/SDXC

GPP_A17/SD_PW R_EN#/ISH_GP7

7 OF 20

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_G7/SD_W P

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

?

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

AB7

AF13

GPP_G0

GPP_G3

GPP_A17
GPP_A16

ESDIO_RCOMP

MD_ID4

TP33

R160 200/F_4

MD_ID4 5

2

1

08

+VCC_ESPI_LPC

GPP_A17

GPP_D19
GPP_D20
GPP_G0
GPP_G3

GPP_F1
GPP_F2

AMD_VBIOS_SEL#

R543 *100K/F_4

+3V_DEEP_SUS

R189 100K/F_4
R185 100K/F_4
R151 100K/F_4
R150 100K/F_4

R134 *100K/F_4
R582 *100K/F_4

R136 *10K/F_4
R140 10K/F_4

+1.8V

+1.8V

+3V

1

ACZ_SDOUT_AUDIO24

B B

R573 33_4

ACZ_SDOUT

SI1, 0424 remove

TOUCH_PWR_EN

ME_UNLOCK#46

SI1, 0421 change to 0ohm

PV, 0917, change to short pad

PLTRST#3,4,29

A A

NB5

NB5

5

4

3

2

NB5

R190 100K/F_4

+3V_DEEP_SUS

R507
1K/F_4

1

R508 *0_4/S

+3V_DEEP_SUS 3,4,5,6,10,15,18,27,32,37,44,45,47,52,54,55,62,64,65
+1.8V 4,5,24,64,65
+3V
+5V 20,24,25,27,34,35,38,62,64,65

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

SKYPAKE (HDA)

SKYPAKE (HDA)

SKYPAKE (HDA)

Date: Sheet of

Date: Sheet of

Date: Sheet

2

Q26

BSS84

3
1

2

Q25

BSS84

3

ACZ_SDO

8 67Tuesday, December 22, 2015

8 67Tuesday, December 22, 2015

8 67Tuesday, December 22, 2015

1

of

1A

1A

1A

5

4

3

2

1

?

RTC Clock 32.768KHz

U29J

CLK_PCIE_SSDN
CLK_PCIE_SSDP
PCIE_CLKREQ_SSD#

CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_CLKREQ_LAN#

CLK_PCIE_WLANN
CLK_PCIE_WLANP
PCIE_CLKREQ_WLAN#

CFG015
CFG115
CFG215
CFG315
CFG415
CFG515
CFG615
CFG715
CFG815
CFG915
CFG1015
CFG1115
CFG1215
CFG1315
CFG1415
CFG1515

CFG1615
CFG1715

CFG1815
CFG1915

R289 49.9/F_4

ITP_PMODE15

PCIE_CLKREQ_CR#

PCIE_CLKREQ4#

PCIE_CLKREQ5#

RTC_RST#

C1023

0.1U/16V_4

PCIE_CLKREQ_SSD#40

PCIE_CLKREQ_LAN#26

PCIE_CLKREQ_WLAN#32

CLK_PCIE_SSDN40
CLK_PCIE_SSDP40

CLK_PCIE_LANN26
CLK_PCIE_LANP26

CLK_PCIE_WLANN32

CLK_PCIE_WLANP32

RTC_RST# 15

SI2, 0702

CFG0-19 need Reserve TP

+1.0V_DEEP_SUS

C462 10P/50V_4

12

D D

C463 10P/50V_4

XTAL24_IN
XTAL24_OUT

C C

RTC Circuitry(RTC)

SI1, 0326 add R795, R794 to prevent RTC power over +3.2V

+3V_RTC_0

CN4
RTC_CONN

DFHD02MS119

B B

A A

Y2

32.768KHz

SI1, 0326 change Y2 to CL 9pF type and change
C462 to 10p,C463 to 10p as vender recommend

R633
1M/F_4

+3V_ALW

R794 47K/F_4

+3V_RTC_0 +3V_RTC_1+3V_RTC_0

R424
1K/F_4

1

23

4

CFG4
CFG9

5

RTC_X1

R536
10M_4

RTC_X2

TP48

C485 27pF_4

1

2

24MHZ +-30PPM
Y3

4

3

C484 27pF_4

TP47

R795

1.5K/_4

+3V_RTC_2

D7

BAT54C

SI1, 0320 change to 27p for vernder's suggestion

SI1, 0428 change to 24M to CL 20p, follow for Intel DG

30mils

+3V_RTC

R422

+3V_RTC

C376

1U/6.3V_4

20K/F_4

R423
20K/F_4

RTC Power trace width 20mils.

R182 1K/F_4
R181 *1K/F_4

+VCCSFR 2,3,11,13,45,56,59,62
+1.0V_DEEP_SUS 10,15,52,55,62,65

+3V 2,3,4,5,7,8,10,15,19,20,21,22,24,27,28,29,37,38,39,40,44,45,48,49,56,62,64

4

SSD

WLAN

C375
1U/6.3V_4

C377
1U/6.3V_4

N

LA

SRTC_RST#

D42
C42

AR10

B42
A42
AT7

D41
C41
AT8

D40
C40

AT10

B40
A40

AU8

E40
E38

AU7

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG17

CFG18
CFG19

CFG_RCOMP

R1591.5K_4

3

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
GPP_B6/SRCCLKREQ1#

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
GPP_B7/SRCCLKREQ2#

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
GPP_B8/SRCCLKREQ3#

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
GPP_B9/SRCCLKREQ4#

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#

*SKL_ULT

REV = 1

U29S

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

E70

CFG[4]

C68

CFG[5]

D68

CFG[6]

C67

CFG[7]

F71

CFG[8]

G69

CFG[9]

F70

CFG[10]

G68

CFG[11]

H70

CFG[12]

G71

CFG[13]

H69

CFG[14]

G70

CFG[15]

E63

CFG[16]

F63

CFG[17]

E66

CFG[18]

F66

CFG[19]

E60

CFG_RCOMP

E8

ITP_PMODE

AY2

RSVD_AY2

AY1

RSVD_AY1

D1

RSVD_D1

D3

RSVD_D3

K46

RSVD_K46

K45

RSVD_K45

AL25

RSVD_AL25

AL27

RSVD_AL27

C71

RSVD_C71

B70

RSVD_B70

F60

RSVD_F60

A52

RSVD_A52

BA70

RSVD_TP_BA70

BA68

RSVD_TP_BA68

J71

RSVD_J71

J68

RSVD_J68

F65

VSS_F65

G65

VSS_G65

F61

RSVD_F61

E61

RSVD_E61

*SKL_ULT

REV = 1

SKL_ULT

CLOCK SIGNALS

SKL_ULT

RESERVED SIGNALS-1

10 OF 20

?

19 OF 20

T

BT

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

SRTCRST#

RTCRST#

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

TP5
TP6

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

TP4

RSVD_A69
RSVD_B69

RSVD_AY3
RSVD_D71

RSVD_C70
RSVD_C54

RSVD_D54

TP1
TP2

VSS_AY71

ZVM#

RSVD_TP_AW71
RSVD_TP_AW70

MSM#

PROC_SELECT#

?

RTCX1
RTCX2

2

?

BB68
BB69

AK13
AK12

BB2
BA3

AU5
AT5

D5
D4
B2
C2

B3
A3

AW1
E1

E2
BA4

BB4
A4

C4
BB5
A69

B69
AY3
D71

C70
C54

D54
AY4

BB3
AY71

AR56
AW71

AW70
AP56

C64

F43

CK_XDP_N_R

E43

CK_XDP_P_R

BA17
E37

XTAL24_IN

E35

XTAL24_OUT

E42

XCLK_BIASREF

AM18
AM20

AN18

SRTC_RST#

AM16

RTC_RST#

RP1 install for XDP

0_4P2R_4
RP2

4

3

2

1

RTC_X1
RTC_X2

R769 *0_4

R636 2.7K/F_4

RTC_RST# 15

SUSCLK32_KBC_WLAN 32

SI1, 1/9 HP review

+1.0V_DEEP_SUS

SI1, 3/18 Del for don't need reserve for
Cannon Lake, support Kaby lake

CLK_REQ/Strap Pin(CLG)

PCIE_CLKREQ4#
PCIE_CLKREQ5#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ_CR#
PCIE_CLKREQ_SSD#

AW69
AW68

AU56

AW48

C7
U12
U11
H11

REV = 1

SI1, 3/18 Del for don't need reserve for
Cannon Lake, support Kaby lake

SI1, 3/18 Del for don't need reserve for
Cannon Lake, support Kaby lake

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

NB5

NB5

NB5

Date: Sheet of

Date: Sheet of

Date: Sheet

CK_XDP_N 15
CK_XDP_P 15

SUSCLK32_KBC 46

R122 10K/F_4
R111 *10K/F_4
R112 10K/F_4
R106 10K/F_4
R113 10K/F_4
R79 10K/F_4

?

SKL_ULT

U29T

SPARE

RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11

*SKL_ULT

SKYLAKE (CLK,RSV,RTC)

SKYLAKE (CLK,RSV,RTC)

SKYLAKE (CLK,RSV,RTC)

20 OF 20

1

09

TO KBC & WLAN

+3V

F6

RSVD_F6

E3

RSVD_E3

C11

RSVD_C11

B11

RSVD_B11

A11

RSVD_A11

D12

RSVD_D12

C12

RSVD_C12

F52

RSVD_F52

?

9 67Tuesday, December 22, 2015

9 67Tuesday, December 22, 2015

9 67Tuesday, December 22, 2015

1A

1A

1A

of

5

4

3

2

1

10

D D

?

SKL_ULT

U29O

CPU POWER 4 OF 4

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE

DCPDSW_1P0
VCCMPHYAON_1P0

VCCMPHYAON_1P0
VCCMPHYGT_1P0_N15

VCCMPHYGT_1P0_N16
VCCMPHYGT_1P0_N17
VCCMPHYGT_1P0_P15
VCCMPHYGT_1P0_P16

VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0

VCCAPLL_1P0
VCCPRIM_1P0_AB17

VCCPRIM_1P0_Y18
VCCDSW_3P3_AD17

VCCDSW_3P3_AD18
VCCDSW_3P3_AJ17

VCCHDA
VCCSPI
VCCSRAM_1P0

VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0

VCCPRIM_3P3_AJ21
VCCPRIM_1P0_AK20
VCCAPLLEBB

*SKL_ULT

0.696A

2.574A

22mA

3.5A

88mA
26mA

118mA

68mA
11mA

642mA

33mA

75mA

6mA
1mA

1mA

35
29mA
24mA
33mA
4mA
10mA

15 OF 20

20mA
4mA
6mA
8mA
6mA
161mA
41mA

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

mA

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG

VCCATS_1P8

DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6

?

+VCCSPI

AB19
AB20

AF18
AF19

AB17

AD17
AD18

AJ17
AJ19
AJ16
AF20

AF21

AJ21

AK20

P18

V20
V21

AL1
K17

L1

N15
N16
N17
P15
P16

K15

L15

V15

Y18

T19
T20

N18

REV = 1

+1.0V_DEEP_SUS

+VCC_PRIM

PCH Internal VRM

+1.0V_MODPHY

C C

+VCCDSW_1.0V

+1.0V_DEEP_SUS

C183 1U/6.3V_4
C98 1U/6.3V_4
C94 0.1U/16V_4
C95 0.1U/16V_4

+1.0V_DEEP_SUS

+1.0V_MODPHY

SI1B, 0508 close U20.V15

+3VPCU

SI1B, 0508 close U20.AJ19

B B

+1.5V

+3V_DEEP_SUS

+1.8V_DEEP_SUS

+1.0V_MODPHY

+3V_DEEP_SUS

+1.0V_DEEP_SUS

+1.0V_MODPHY

C164 22U/6.3V_6

C135 1U/6.3V_4
C171 0.1U/16V_4

C471 1U/6.3V_4

C157 1U/6.3V_4

R812 BLM15PX181SN1D

SI2, 6/22

R813 BLM15PX181SN1D

+3V

R835 *BLM15PX181SN1D

PVR, 1027

C158 1U/6.3V_4

C458 22U/6.3V_6
C243 22U/6.3V_6

C200 1U/6.3V_4
C90 1U/6.3V_4
C96 0.1U/16V_4
C97 0.1U/16V_4

PV, 0907

L21 2.2UH_6

R68 *0_4/S

R145 *0_4/S
R153 *0_4

R601 *0_6/S

+VCCDSW_1.0V

+1.0V_VCCAMPHYPLL

C1029 22U/6.3V_6

+1.0V_VCCAPLL

C234 22U/6.3V_6
C600 0.1U/16V_4

+VCCDSW

C121 1U/6.3V_4

+V3.3DX_1.5DX_ADO

C60 1U/6.3V_4
C601 0.1U/16V_4

C104 0.1U/16V_4

+VCCAPLLEBB

SI2, 6/22

+3V_DEEP_SUS

AK15
AG15
Y16
Y15
T16
AF16
AD15

V19
T1
AA1
AK17
AK19

BB14
BB10
A14
K19
L21
N20
L19
A10
AN11

AN13

+1.8V_DEEP_SUS
+3V_DEEP_SUS

DCPRTC
+VCCCLK1
+VCCCLK2
+VCCCLK3
+VCCCLK4
+VCCCLK5
+VCCCLK6

CORE_VID0
CORE_VID1

+VCC_ESPI_LPC

PV, 0917, change to short pad

+VCC_ESPI_LPC

+1.8V_DEEP_SUS

C460 0.1U/16V_4

R86*0_4/S
R69*0_4/S

SI1, 0424 stuff

+1.0V_DEEP_SUS

C221 22U/6.3V_6

+3V_RTC

C100 0.1U/16V_4
C82 1U/6.3V_4

VID0_VCC_PRIM 55
VID1_VCC_PRIM 55

+1.0V_DEEP_SUS

C461

1U/6.3V_4

+1.8V_DEEP_SUS

*1U/6.3V_4

C964

+3V_DEEP_SUS+1.8V_DEEP_SUS

C119

1U/6.3V_4

C107

0.1U/16V_4

+3V_DEEP_SUS 3,4,5,6,8,15,18,27,32,37,44,45,47,52,54,55,62,64,65
+1.5V 21,22,24,52
+3VPCU 3,15,18,27,28,30,32,33,35,36,39,41,43,44,45,46,47,48,49,50,51,52,53,54,55,60,61,62,63,64,65,66
+1.0V_DEEP_SUS 9,15,52,55,62,65

A A

+VCC_PRIM 55
+3V 2,3,4,5,7,8,9,15,19,20,21,22,24,27,28,29,37,38,39,40,44,45,48,49,56,62,64
+1.8V_DEEP_SUS 11,44,47,64,65

5

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

SKYPAKE ( PCH POWER)

SKYPAKE ( PCH POWER)

NB5

NB5

4

3

2

NB5

SKYPAKE ( PCH POWER)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

10 67Tuesday, December 22, 2015

10 67Tuesday, December 22, 2015

10 67Tuesday, December 22, 2015

1A

1A

1A

5

4

3

2

1

?

29A

Under U29 Under U29

C178
10U/6.3V_6

C149
10U/6.3V_4

C199
22U/6.3V_6

+VCC_EDRAM

+VCC_EOPIO

Under U9052

+VCC_EDRAM

22U/6.3V_6

C176
*1U/6.3V_4

D D

SI1, 0407 change C512 contact
to +1.8V_DEEP_SUS

C C

C214

C240

C117
10U/6.3V_4

C169
22U/6.3V_6

22U/6.3V_6

C278
10U/6.3V_4

C182
22U/6.3V_6

C154
*10U/6.3V_4

22U/6.3V_6

10U/6.3V_4

C172
22U/6.3V_6

+1.8V_DEEP_SUS

C134
10U/6.3V_4

22U/6.3V_6

C512
*0.1U/16V_4

C113
*10U/6.3V_4

C161
10U/6.3V_4

C173
22U/6.3V_6

R652 *0_4

VID0_VCC_EDRAM60
VID1_VCC_EDRAM60

VID0_VCC_EOPIO61
VID1_VCC_EOPIO61

C167

22U/6.3V_6

C146
10U/6.3V_4

C174
22U/6.3V_6

C168

22U/6.3V_6

10U/6.3V_4

TP13
TP8

+V1.8S_EDRAM

VID0_VCC_EDRAM
VID1_VCC_EDRAM

VID0_VCC_EOPIO
VID1_VCC_EOPIO

DB1 change to DNI, for 2+3E only

C212
*1U/6.3V_4

C188
*1U/6.3V_4

C155
*1U/6.3V_4

C153
*1U/6.3V_4

C213
1U/6.3V_4

+VCC_CORE +VCC_CORE

A30
A34
A39
A44

+VCCG0
+VCCG1

3A
50mA

3A

AK33
AK35
AK37
AK38
AK40

AL33
AL37

AL40
AM32
AM33
AM35
AM37
AM38

G30

K32
AK32
AB62

P62

V62

H63

G61

AC63
AE63

AE62
AG62

AL63
AJ62

+VCC_EDRAM +VCC_EOPIO

C181

22U/6.3V_6

SI1, 0429 C134/C213 stuff for 2+2 only

SKL_ULT

U29L

CPU POWER 1 OF 4

VCC_A30
VCC_A34
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30

RSVD_K32
RSVD_AK32
VCCOPC_AB62

VCCOPC_P62
VCCOPC_V62

VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE

VSSOPC_SENSE
VCCEOPIO

VCCEOPIO
VCCEOPIO_SENSE

VSSEOPIO_SENSE

*SKL_ULT

REV = 1

R499 *0_8

12 OF 20

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63
A63
D64

G20

?

C208
1U/6.3V_4

C206
1U/6.3V_4

H_CPU_SVIDALRT#
VR_SVID_CLK_L
H_CPU_SVIDDAT

C207
1U/6.3V_4

C205
1U/6.3V_4

R196 100/F_4

R197 100/F_4

+VCCSTG

C239
1U/6.3V_4

C128
1U/6.3V_4

VCCSENSE 56
VSSSENSE 56

C238

C237

1U/6.3V_4C180

1U/6.3V_4

C282

C275

1U/6.3V_4

1U/6.3V_4

+VCC_CORE

100- ±1% pull-up to VCC
near processor.
Trace Length Match <25mil

+VCC_CORE

C509
47U/6.3V_8

+VCC_CORE

C291
10U/6.3V_4

C148
1U/6.3V_4C228

C273
1U/6.3V_4C160

lose U29

C

C501
47U/6.3V_8

C290
10U/6.3V_4

C488
1U/6.3V_4

C272
1U/6.3V_4C156

47U/6.3V_8

C490

C296
10U/6.3V_4

C204
1U/6.3V_4

47U/6.3V_8

C515

C297
10U/6.3V_4

+VCC_CORE

C517

47U/6.3V_8

C277
10U/6.3V_4

C857

3.3P/50V_4

C510

47U/6.3V_8

C283
10U/6.3V_4

C858
68P/50V_4

DB1 RF

C502

47U/6.3V_8

C103
10U/6.3V_4

C491

47U/6.3V_8

C203
10U/6.3V_4

11

B B

Layout note: need routing together and ALERT need between CLK and DATA.

CLOSE TO CPU
PL

ACE THE PU RESISTORS

H_CPU_SVIDALRT#

PLACE THE PU RESISTORS
CLOSE TO VR
PULL UP IS IN THE VR MODULE

VR_SVID_CLK_L

+VCCSFR

R288 220/F_4

R286 *0_4/S

R649

56.2/F_4

C503 *0.1U/16V_4

SVID ALERT

VR_SVID_ALERT# 56,59

VID CLK

S

VR_SVID_CLK 56,59

SI2, 6/22

+VCCSFR

Place PU resistor
close to VR

R314

CLOSE TO CPU

A A

5

4

PLACE THE PU RESISTORS

H_CPU_SVIDDAT

3

R287 *0_4/S

100/F_4

SI2, 6/22

SVID DATA

VR_SVID_DATA 56,59

2

+1.8V 4,5,8,24,64,65
+VCC_CORE 56,57,66
+VCCSFR 2,3,13,45,56,59,62
+VCC_EOPIO 61
+VCC_EDRAM 60
+VCCSTG 2,13,62

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

SKYPAKE (POWER-1)

SKYPAKE (POWER-1)

NB5

NB5

NB5

SKYPAKE (POWER-1)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

11 67Tuesday, December 22, 2015

11 67Tuesday, December 22, 2015

11 67Tuesday, December 22, 2015

5

4

3

2

1

12

?

SKL_ULT

AA63
AA64
AA66
AA67
AA69
AA70

AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

M62
N63
N64
N66
N67
N69

A48
A53
A58
A62
A66

J43
J45
J46
J48
J50
J52
J53
J55
J56
J58

J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71

J70

J69

U29M

CPU POWER 2 OF 4

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT_SENSE
VSSGT_SENSE

*SKL_ULT

REV = 1

VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70

VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56

VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66

VCCGTX_SENSE
VSSGTX_SENSE

13 OF 20

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

?

D D

+VCC_GT

Under U29

C215
10U/6.3V_4

C216
10U/6.3V_4

C235
1U/6.3V_4

C C

C145
1U/6.3V_4

B B

Trace Length Match <25mil

C218
10U/6.3V_4

C217
10U/6.3V_4

C143
1U/6.3V_4

C147
1U/6.3V_4

C142
1U/6.3V_4

C185
1U/6.3V_4

C219
10U/6.3V_4

C232
10U/6.3V_4

C144
1U/6.3V_4

C166
1U/6.3V_4

VGT_VCCSENSE56

VGT_VSSSENSE56

C209
10U/6.3V_4

C233
10U/6.3V_4

C165
1U/6.3V_4

C236
1U/6.3V_4

C184
10U/6.3V_4

C231
10U/6.3V_4

C187
1U/6.3V_4

C186
1U/6.3V_4

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

+VCC_GT

22U/6.3V_6

22U/6.3V_6

+VCC_GTX

*22U/6.3V_6

10U/6.3V_4

C190

C191

C152

57A

Close U29

C511

C116

C507
47U/6.3V_8

C227

22U/6.3V_6

C193

*22U/6.3V_6

C500
47U/6.3V_8

C222

22U/6.3V_6

C226

22U/6.3V_6

7A

C133

*22U/6.3V_6

C506
47U/6.3V_8

C223

22U/6.3V_6

C225

22U/6.3V_6

C151

*22U/6.3V_6

C504
47U/6.3V_8

C189

22U/6.3V_6

C224

22U/6.3V_6

C192

*22U/6.3V_6

C505
47U/6.3V_8

22U/6.3V_6

Close U9052

*22U/6.3V_6

SI1, 0429 C138/C74 stuff for 2+2 only

C138

C112

*10U/6.3V_4

C111

*10U/6.3V_4

Under U9052

C124

*10U/6.3V_4

C137

*10U/6.3V_4

DB1 change to DNI, for 2+3E only

VCCGTUS_SENSE 59
VSSGTUS_SENSE 59

Trace Length Match <25mil

22U/6.3V_6

*22U/6.3V_6

C123

*10U/6.3V_4

C508
47U/6.3V_8

C179

C195

22U/6.3V_6

*22U/6.3V_6

C75

*10U/6.3V_4

C175

C194

C74

10U/6.3V_4

+VCC_GT

C859

3.3P/50V_4

C860
68P/50V_4

DB1 RF

A A

NB5

NB5

5

4

3

2

NB5

+VCC_GT 56,58
+VCC_GTX 59

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

SKYPAKE (POWER-1)

SKYPAKE (POWER-1)

SKYPAKE (POWER-1)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

12 67Tuesday, December 22, 2015

12 67Tuesday, December 22, 2015

12 67Tuesday, December 22, 2015

1A

1A

1A

5

4

3

2

1

13

+1.2VSUS +VDDQC

DB1 Intel

D D

+1.2VSUS

C53

C864

3.3P/50V_4

C863
68P/50V_4

DB1 RF

C C

10U/6.3V_4

Close U29 Under U29

C67

10U/6.3V_4

Under U29 Under U29 Close U29

C51

C81

C72

10U/6.3V_4

+VCCSFR+VCCST

1U/6.3V_4

10U/6.3V_4

+1.2V_VCCPLL_OC

+1.2VSUS

10U/6.3V_4

SI1, 0416

+1.2VSUS +VCC_IO

C50

1U/6.3V_4

C66

DB1 Intel

C77

1U/6.3V_4

C76

10U/6.3V_4

R96 *0_4/S

C892 1U/6.3V_4

R814 *0_4

C64

1U/6.3V_4

+VDDQC

+VCCSFR

+VCCSTG

+VCCPLL_OC

+VCCSFR

PVR, 1027

+VCCPLL_OC

C476

1U/6.3V_4

SI1B, 0521

+VDDQC +VCCSTG

C105

1U/6.3V_4

C73

10U/6.3V_6

C495

1U/6.3V_4

+1.2VSUS

AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51

AM40

AL23

A18
A22

K20
K21

U29N

VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51

VDDQC
VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20

VCCPLL_K21

*SKL_ULT

SKL_ULT

CPU POWER 3 OF 4

2A 3.1A

12A

0.

0.04A

0.12A

REV = 1

?

14 OF 20

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCSA

5.1A

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

?

AK28
AK30
AL30
AL42
AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23
AM22

H21
H20

C118
1U/6.3V_4

+VCC_SA

C177
1U/6.3V_4

VCCIO_VCCSENSE
VCCIO_VSSSENSE

C101

C129

1U/6.3V_4

1U/6.3V_4

C170

C162

1U/6.3V_4

1U/6.3V_4

C201

C202

10U/6.3V_4

10U/6.3V_4

VCCIO_VCCSENSE 54

VCCSA_VSSSENSE 56
VCCSA_VCCSENSE 56

VCCIO_VSSSENSE 54

C109

C115

10U/6.3V_4

1U/6.3V_4

C150

C198

1U/6.3V_4

1U/6.3V_4

C196

C197

10U/6.3V_4

10U/6.3V_4

Trace Length Match <25mil

Trace Length Match <25mil

C139
10U/6.3V_4

C211
1U/6.3V_4

C140
10U/6.3V_4

C65
1U/6.3V_4

C159
1U/6.3V_4

C242
10U/6.3V_4

C130
1U/6.3V_4

C126
10U/6.3V_4

Close U29

C106
1U/6.3V_4

C229
10U/6.3V_4

C108
10U/6.3V_4

C102
1U/6.3V_4

C132
10U/6.3V_4

+VCC_IO

C125
10U/6.3V_4

C862

3.3P/50V_4

C244
10U/6.3V_4

C861
68P/50V_4

DB1 RF

C141
10U/6.3V_4

Under U9052

B B

+VCCSFR 2,3,11,45,56,59,62
+1.2VSUS 6,16,17,51,62
+VCCSTG 2,11,62
+VCC_IO 5,15,38,54
+VCC_SA 56,57,66

A A

5

C391

10U/6.3V_6

C390

10U/6.3V_6

C386

10U/6.3V_6

4

C389

10U/6.3V_6

C388

10U/6.3V_6

10U/6.3V_6

Close to CPU

C387

C80

1U/6.3V_4

C83

1U/6.3V_4

C79

1U/6.3V_4

3

C52

1U/6.3V_4

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

SKYPAKE (POWER-2)

SKYPAKE (POWER-2)

NB5

NB5

2

NB5

SKYPAKE (POWER-2)

Date: Sheet of

Date: Sheet of

Date: Sheet

1

1A

1A

1A

13 67Tuesday, December 22, 2015

13 67Tuesday, December 22, 2015

13 67Tuesday, December 22, 2015

of

5

4

3

2

1

?

?

SKL_ULT

U29P

A5

VSS

A67

VSS

AA65
AA68
AB15
AB16
AB18
AB21

AD13
AD16
AD19
AD20
AD21
AD62

AE64
AE65
AE66
AE67
AE68
AE69

AF10
AF15
AF17

AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13

AH63
AH64
AH67

AJ15

AJ18

AJ20
AK11

AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AL28

AL32

AL35

AL38

AL45

AL48

AL52

AL55

AL58

AL64

A70
AA2
AA4

AB8

AD8

AF1

AF2
AF4

AH6

AJ4

AK8
AL2

AL4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

*SKL_ULT

REV = 1

D D

C C

B B

A A

Need apply PN Need apply PN Need apply PN

GND 1 OF 3

16 OF 20

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

?

AT63
AT68

AT71
AU10
AU15
AU20
AU32
AU38

AV68
AV69
AV70
AV71

AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6

AW60
AW62
AW64
AW66

AW8
AY66

BA10
BA14
BA18

BA23
BA28
BA32
BA36

BA45

SKL_ULT

?

U29Q

GND 2 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AV1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B10

VSS

B14

VSS

B18

VSS

B22

VSS

B30

VSS

B34

VSS

B39

VSS

B44

VSS

B48

VSS

B53

VSS

B58

VSS

B62

VSS

B66

VSS

B71

VSS

BA1

VSS
VSS
VSS
VSS

BA2

VSS
VSS
VSS
VSS
VSS

F68

VSS
VSS

17 OF 20

*SKL_ULT

REV = 1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

?

SKL_ULT

U29R

GND 3 OF 3

F8

VSS

G10

VSS

G22

VSS

G43

VSS

G45

VSS

G48

VSS

G5

VSS

G52

VSS

G55

VSS

G58

VSS

G6

VSS

G60

VSS

G63

VSS

G66

VSS

H15

VSS

H18

VSS

H71

VSS

J11

VSS

J13

VSS

J25

VSS

J28

VSS

J32

VSS

J35

VSS

J38

VSS

J42

VSS

J8

VSS

K16

VSS

K18

VSS

K22

VSS

K61

VSS

K63

VSS

K64

VSS

K65

VSS

K66

VSS

K67

VSS

K68

VSS

K70

VSS

K71

VSS

L11

VSS

L16

VSS

L17

VSS

18 OF 20

*SKL_ULT

REV = 1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

?

14

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

SKYPAKE (GND)

SKYPAKE (GND)

NB5

NB5

5

4

3

2

NB5

SKYPAKE (GND)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

14 67Tuesday, December 22, 2015

14 67Tuesday, December 22, 2015

14 67Tuesday, December 22, 2015

5

SI1, 2/4 change to DNI

H_PREQ#7

H_PRDY#7

CFG09
CFG19
CFG29
CFG39
CFG49

CFG59

CFG69
CFG79

CK_XDP_P9
CK_XDP_N9

H_TCK
PCH_SPI_IO2

HOOK2

R43 *51_4

+3V

+1.0V_DEEP_SUS

D D

SI1B, 0521

ON_OFF#1_Q15,36,43,46

PCH_SMBDATA3,43

PCH_SMBCLK3,43

H_TCK2

PCH_SPI_IO247

+VCC_IO

C C

R65 150_4

SI1, 0422 corrected APS conn. power pin define

APS

+3VPCU+3V_DEEP_SUS

4

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7

R815 *0_4

CFG0 HOOK2

R40 1K/F_4

XDP_DBRESET#

R3231K/F_4

PCH_TDO
XDP_TRST#
PCH_TDI
PCH_TMS

R72 1K/F_4

MSR_ENABLE_N

3

SI1, 3/26 Correct XDP pin define

CN1

3

OBSFN_A0

5

OBSFN_A1

9

OBSDATA_A0

11

OBSDATA_A1

15

OBSDATA_A2

17

OBSDATA_A3

27

OBSDATA_B0

29

OBSDATA_B1

33

OBSDATA_B2

35

OBSDATA_B3

41

HOOK1

45

HOOK2

40

ITPCLK/HOOK4

42

ITPCLK#/HOOK5

48

DBR#/HOOK7

51

SDA

53

SCL

52

TDO

54

TRSTN

56

TDI

58

TMS

57

TCK0

60

GND17

59

GND16

50

CPU XDP

GND15

49

GND14

38

GND13

37

GND12

32

GND11

31

GND10

*Samtec BSH-030-01

VCC_OBS_CD
VCC_OBS_AB

OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3

OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3

PWRGOOD/HOOK0

RESET#/HOOK6

OBSFN_B0
OBSFN_B1
OBSFN_C0
OBSFN_C1

OBSFN_D0
OBSFN_D1

HOOK3

TCK1

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

+1.0V_DEEP_SUS

44
43
21
23
4
6
10
12
16
18
22
24
28
30
34
36
47
55

PCH_TCK

39
46
1

GND0

2
7
8
13
14
19
20
25
26

+1.0V_DEEP_SUS

TP1

CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
HOOK3

R41 *0_4

XDP_BPM0 2
XDP_BPM1 2
CFG17 9
CFG16 9
CFG8 9
CFG9 9
CFG10 9
CFG11 9
CFG19 9

CFG18 9
CFG12 9
CFG13 9
CFG14 9
CFG15 9

PCH_TCK 2

C63

0.1U/16V_4

2

R71 1K/F_2
R66 *0_2
R777 *0_2/S

RSMRST# 3,46

PCI_PLTRST# 3,26,29,32,33,40,44,46
ITP_PMODE 9

SI1, 4/13 change to 0201 type for ME concern

PV, 0917, change to short pad

CFG3GND0

R421K/F_4

PCH_SPI1_SIHOOK3

R851K/F_4
R82*1.5K_4

PCH_SPI1_SI 3,29,45,47

+SPI_VCC

1

15

CN23

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

19

19

20

20

*APS CONN.

11

12

12

13

XDP_DBRESET#

13

14

14

15

15

16

16

17

17

18

18

B B

SLP_S3#_3R 3,18,23,30,43,46,62,64
SLP_S5#_3R 3,41

SLP_S4#_3R 3,18,30,53,62
PM_SLP_A# 3,45,64

RTC_RST# 9
ON_OFF#1_Q 15,36,43,46
XDP_DBRESET# 3
VRPPM_SLP_S0_N 3,45,62,65

2

PWR_GOOD_33,18,46,64,65

Q40B
PJX138K

6 1

34

PJX138K

5

Q40A

2

Q41B
PJX138K

6 1

XDP_TRST#

34

PJX138K

5

Q41A

H_TDI 2

PCH_TDI 2
PCH_TMS 2

H_TMS 2
H_TDO 2

PCH_TDO 2

H_TRST# 2

SI1B, 0521 change to DNI

R305
*51_4

+3V_DEEP_SUS 3,4,5,6,8,10,18,27,32,37,44,45,47,52,54,55,62,64,65
+1.0V_DEEP_SUS 9,10,52,55,62,65
+VCC_IO 5,13,38,54
+3VPCU 3,10,18,27,28,30,32,33,35,36,39,41,43,44,45,46,47,48,49,50,51,52,53,54,55,60,61,62,63,64,65,66

A A

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

SKYLAKE XDP & APS

SKYLAKE XDP & APS

NB5

NB5

5

4

3

2

NB5

SKYLAKE XDP & APS

Date: Sheet of

Date: Sheet of

Date: Sheet of

15 67Tuesday, December 22, 2015

15 67Tuesday, December 22, 2015

15 67Tuesday, December 22, 2015

1

1A

1A

1A

5

M_A_DQ[63:0]6

M_A_A[16:0]6

D D

C C

DDR_DRAMRST#6,17

+2.5VSUS

SI1, 0427 RF

DDR0_ALERT#6

DDRA_ACT#6

DDR0_PAR6

68P/50V_4

+SMDDR_VREF_DQ0_M1

C991

R4 240/F_4

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16

M_A_BS#06
M_A_BS#16
M_A_BG#06

M_A_CLKP06
M_A_CLKN06
M_A_CKE06

M_A_ODT06

M_A_CS#06

M_A_DQSP76
M_A_DQSP66 M_A_DQSP46

M_A_DQSN76
M_A_DQSN66

+1.2VSUS

M_A1_ZQ0

DDR0_ALERT# DDR0_ALERT# DDR0_ALERT# DDR0_ALERT#
DDRA_ACT#
DDR0_PAR DDR0_PAR DDR0_PAR DDR0_PAR

U16

M1

B1

R9

P3

P7
R3
N7
N3

P8

P2
R8
R2
R7
M3

T2
M7

T8

L2
M8

L8

N2
N8
M2

K7

K8

K2

K3

L7

G3

B7

F3

A7

E7

E2

P1

F9
N9

P9

L3

T3

T7

K4

VREFCA
VPP
VPP

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
WE_n/A14
CAS_n/A15
RAS_n/A16

BA0
BA1
BG0

CK_t
CK_c
CKE

ODT
CS

DQSL_t
DQSU_t

DQSL_c
DQSU_c

DML_n/DBIL_n
DMU_n/DBIU_n

RESET_n
ZQ
TEN

ALERT_n
ACT_n
PAR

NC

96-BALL
DDR4

A8G165WB-BCPB

BYTE6_48-55
BYTE7_56-63

G2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B3
VDD#B9
VDD#D1
VDD#G7

VDD#J1
VDD#J9
VDD#L1
VDD#L9

VDD#R1

VDD#T9

VDDQ#A1

VDDQ#A9
VDDQ#C1
VDDQ#D9

VDDQ#F2

VDDQ#F8
VDDQ#G1
VDDQ#G9

VDDQ#J2

VDDQ#J8

VSS#B2
VSS#E1

VSS#E9
VSS#G8
VSS#K1
VSS#K9

VSS#M9

VSS#N1
VSS#T1

VSSQ#A2
VSSQ#A8
VSSQ#C9
VSSQ#D2
VSSQ#D8
VSSQ#E3
VSSQ#E8
VSSQ#F1
VSSQ#H1
VSSQ#H9

M_A_DQ61

F7

M_A_DQ63

H3

M_A_DQ56

H7

M_A_DQ62

H2

M_A_DQ60

H8

M_A_DQ59

J3

M_A_DQ57

J7

M_A_DQ58

A3

M_A_DQ49

B8

M_A_DQ53

C3

M_A_DQ54

C7

M_A_DQ48

C2

M_A_DQ50

C8

M_A_DQ52

D3

M_A_DQ51

D7

M_A_DQ55

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

B2
E1
E9
G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

+1.2VSUS

DB1 Option for 16Gbx16 die DB1 Option for 16Gbx16 die DB1 Option for 16Gbx16 die DB1 Option for 16Gbx16 die

R694 0_4

M_A_BG#1_1 M_A_BG#1_2 M_A_BG#1 M_A_BG#1_3 M_A_BG#1 M_A_BG#1_4 M_A_BG#1

R705 *0_2

4

U17

68P/50V_4

+SMDDR_VREF_DQ0_M1

C992

+2.5VSUS

SI1, 0427 RF SI1, 0427 RF SI1, 0427 RF

M_A_BS#0
M_A_BS#1
M_A_BG#0 M_A_BG#0 M_A_BG#0

M_A_CLKP0
M_A_CLKN0
M_A_CKE0

M_A_ODT0
M_A_CS#0

M_A_DQSP16 M_A_DQSP26
M_A_DQSP06

M_A_DQSN16
M_A_DQSN06

M_A_BG#1 6

+1.2VSUS

SI1C, 0615

DDR_DRAMRST#

R6 240/F_4

DDRA_ACT# DDRA_ACT# DDRA_ACT#

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16

M_A_DQSP1
M_A_DQSP0

M_A_DQSN1
M_A_DQSN0

M_A2_ZQ0

M1
B1
R9

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3
T2
M7
T8

L2

M8

L8

N2
N8
M2

K7
K8
K2

K3

L7

G3
B7

F3
A7

E7
E2

P1
F9
N9

P9

L3

T3

T7

K4

VREFCA
VPP
VPP

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
WE_n/A14
CAS_n/A15
RAS_n/A16

BA0
BA1
BG0

CK_t
CK_c
CKE

ODT
CS

DQSL_t
DQSU_t

DQSL_c
DQSU_c

DML_n/DBIL_n
DMU_n/DBIU_n

RESET_n
ZQ
TEN

ALERT_n
ACT_n
PAR

NC

96-BALL
DDR4

A8G165WB-BCPB

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B3
VDD#B9
VDD#D1

VDD#G7

VDD#J1
VDD#J9
VDD#L1
VDD#L9
VDD#R1
VDD#T9

VDDQ#A1
VDDQ#A9
VDDQ#C1
VDDQ#D9
VDDQ#F2
VDDQ#F8
VDDQ#G1
VDDQ#G9

VDDQ#J2
VDDQ#J8

VSS#B2
VSS#E1

VSS#E9
VSS#G8
VSS#K1
VSS#K9
VSS#M9
VSS#N1

VSS#T1

VSSQ#A2

VSSQ#A8
VSSQ#C9
VSSQ#D2
VSSQ#D8

VSSQ#E3

VSSQ#E8

VSSQ#F1
VSSQ#H1
VSSQ#H9

BYTE0_0-7
BYTE1_8-15

G2

M_A_DQ9

F7

M_A_DQ11

H3

M_A_DQ8

H7

M_A_DQ14

H2

M_A_DQ13

H8

M_A_DQ15

J3

M_A_DQ12

J7

M_A_DQ10

A3

M_A_DQ0

B8

M_A_DQ6

C3

M_A_DQ4

C7

M_A_DQ2

C2

M_A_DQ1

C8

M_A_DQ3

D3

M_A_DQ5

D7

M_A_DQ7

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

B2
E1
E9

R695 0_4

G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

3

U21

68P/50V_4

M_A_DQSP56

M_A_DQSN56
M_A_DQSN46

C993

+SMDDR_VREF_DQ0_M1

M_A_BS#0
M_A_BS#1

M_A_CLKP0
M_A_CLKN0
M_A_CKE0

M_A_ODT0
M_A_CS#0

+2.5VSUS

+1.2VSUS

R704 *0_2

SI1C, 0615 SI1C, 0615 SI1C, 0615

DDR_DRAMRST#

R47 240/F_4

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16

M_A_DQSP5
M_A_DQSP4

M_A_DQSN5
M_A_DQSN4

M_A3_ZQ0

M1

B1
R9

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7

M3

T2

M7

T8
L2

M8

L8

N2
N8

M2

K7
K8
K2

K3
L7

G3

B7
F3

A7

E7
E2

P1
F9
N9

P9
L3
T3

T7

VREFCA
VPP
VPP

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
WE_n/A14
CAS_n/A15
RAS_n/A16

BA0
BA1
BG0

CK_t
CK_c
CKE

ODT
CS

DQSL_t
DQSU_t

DQSL_c
DQSU_c

DML_n/DBIL_n
DMU_n/DBIU_n

RESET_n
ZQ
TEN

ALERT_n
ACT_n
PAR

NC

96-BALL
DDR4

K4

A8G165WB-BCPB

BYTE4_32-39
BYTE5_40-47

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B3
VDD#B9
VDD#D1
VDD#G7
VDD#J1
VDD#J9
VDD#L1
VDD#L9
VDD#R1
VDD#T9

VDDQ#A1
VDDQ#A9
VDDQ#C1
VDDQ#D9
VDDQ#F2
VDDQ#F8
VDDQ#G1
VDDQ#G9

VDDQ#J2
VDDQ#J8

VSS#B2
VSS#E1
VSS#E9
VSS#G8
VSS#K1
VSS#K9
VSS#M9
VSS#N1

VSS#T1

VSSQ#A2

VSSQ#A8
VSSQ#C9
VSSQ#D2
VSSQ#D8

VSSQ#E3

VSSQ#E8

VSSQ#F1

VSSQ#H1

VSSQ#H9

G2
F7
H3
H7
H2
H8
J3
J7

A3
B8
C3
C7
C2
C8
D3
D7

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

B2
E1
E9

R696 0_4

G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

M_A_DQ47
M_A_DQ45
M_A_DQ46
M_A_DQ44
M_A_DQ43
M_A_DQ40
M_A_DQ42
M_A_DQ41

M_A_DQ34
M_A_DQ33
M_A_DQ39
M_A_DQ37
M_A_DQ38
M_A_DQ32
M_A_DQ35
M_A_DQ36

R703 *0_2

+1.2VSUS

2

+2.5VSUS

68P/50V_4

M_A_DQSP36
M_A_DQSN26

M_A_DQSN36

R45 240/F_4

+SMDDR_VREF_DQ0_M1

C994

+1.2VSUS+1.2VSUS

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16

M_A_BS#0
M_A_BS#1

M_A_CLKP0
M_A_CLKN0
M_A_CKE0

M_A_ODT0
M_A_CS#0

M_A_DQSP2
M_A_DQSP3

M_A_DQSN2
M_A_DQSN3

DDR_DRAMRST#

M_A4_ZQ0

U22

M1
B1
R9

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7

M3

T2

M7

T8
L2

M8

L8

N2
N8
M2

K7
K8
K2

K3

L7

G3
B7

F3
A7

E7
E2

P1
F9

N9

P9
L3
T3

T7

K4

VREFCA
VPP
VPP

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
WE_n/A14
CAS_n/A15
RAS_n/A16

BA0
BA1
BG0

CK_t
CK_c
CKE

ODT
CS

DQSL_t
DQSU_t

DQSL_c
DQSU_c

DML_n/DBIL_n
DMU_n/DBIU_n

RESET_n
ZQ
TEN

ALERT_n
ACT_n
PAR

NC

96-BALL
DDR4

A8G165WB-BCPB

BYTE2_16-23
BYTE3_24-31

G2

DQL0

F7

DQL1

H3

DQL2

H7

DQL3

H2

DQL4

H8

DQL5

J3

DQL6

J7

DQL7

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

B3

VDD#B3

B9

VDD#B9

D1

VDD#D1

G7

VDD#G7

J1

VDD#J1

J9

VDD#J9

L1

VDD#L1

L9

VDD#L9

R1

VDD#R1

T9

VDD#T9

A1

VDDQ#A1

A9

VDDQ#A9

C1

VDDQ#C1

D9

VDDQ#D9

F2

VDDQ#F2

F8

VDDQ#F8

G1

VDDQ#G1

G9

VDDQ#G9

J2

VDDQ#J2

J8

VDDQ#J8

B2

VSS#B2

E1

VSS#E1

E9

VSS#E9

G8

VSS#G8

K1

VSS#K1

K9

VSS#K9

M9

VSS#M9

N1

VSS#N1

T1

VSS#T1

A2

VSSQ#A2

A8

VSSQ#A8

C9

VSSQ#C9

D2

VSSQ#D2

D8

VSSQ#D8

E3

VSSQ#E3

E8

VSSQ#E8

F1

VSSQ#F1

H1

VSSQ#H1

H9

VSSQ#H9

1

M_A_DQ23
M_A_DQ20
M_A_DQ18
M_A_DQ21
M_A_DQ22
M_A_DQ16
M_A_DQ19
M_A_DQ17

M_A_DQ29
M_A_DQ26
M_A_DQ28
M_A_DQ27
M_A_DQ24
M_A_DQ31
M_A_DQ25
M_A_DQ30

+1.2VSUS

R697 0_4

R702 *0_2

16

M_A_BG#1_1

R706 0_2

M_A_BG#1_2

R707 0_2

M_A_BG#1_3

R708 0_2

M_A_BG#1_4

R709 0_2

DB1 Option for 16Gbx16 die
Close DDR ball

MIC 16G

Elpida

P/NVendor

AKD5EG0TL00

Ve

ndor P/N

MT40A1G16HBA-083E:A

SAMSUNG

B B

DB1 Follow Intel suggestion

+0.6V_DDR_VTT

SI1, 1/12 follow Intel DG

M_A_BS#0

R476 34.8/F_4

M_A_BS#1

R486 34.8/F_4

M_A_BG#0

R444 34.8/F_4

M_A_CKE0

R20 34.8/F_4

M_A_CS#0

R481 34.8/F_4

M_A_A0

R9 34.8/F_4

M_A_A1

R471 34.8/F_4

M_A_A2

R463 34.8/F_4

M_A_A3

R465 34.8/F_4

M_A_A4

R27 34.8/F_4

M_A_A5

R25 34.8/F_4

M_A_A6

R431 34.8/F_4

M_A_A7

R439 34.8/F_4

M_A_A8

R450 34.8/F_4

M_A_A9

R447 34.8/F_4

M_A_A10

R14 34.8/F_4

M_A_A11

R461 34.8/F_4 C897 0.01U/16V_2

M_A_A12

R472 34.8/F_4

M_A_A13

R451 34.8/F_4

M_A_A14

R37 34.8/F_4

M_A_A15

R468 34.8/F_4

M_A_A16

R487 34.8/F_4

M_A_ODT0

R24 34.8/F_4

DDR0_PAR

A A

DDRA_ACT#
M_A_BG#1

R19 34.8/F_4
R36 34.8/F_4
R763 34.8/F_4

+0.6V_DDR_VTT 17,51,62
+1.2VSUS 6,13,17,51,62
+2.5VSUS 17,53

M_A_CLKP0

R10 36/F_4

M_A_CLKN0

R11 36/F_4

SI1B, 0603 close R10, R11

DDR0_ALERT#

R492 51_4

C893 0.01U/16V_2

+1.2VSUS

C894 0.01U/16V_2
C895 0.01U/16V_2
C896 0.01U/16V_2

DB1 12/11, close memory

C903 1U/6.3V_4

+2.5VSUS

C904 1U/6.3V_4
C905 1U/6.3V_4
C906 1U/6.3V_4
C907 1U/6.3V_4
C908 1U/6.3V_4
C909 1U/6.3V_4

C949 10U/6.3V_4
C950 10U/6.3V_4
C951 10U/6.3V_4
C976 68P/50V_4

SI1B, 0603

+0.6V_DDR_VTT

C1011

0.1U/16V_4

+1.2VSUS

Memory 8G & Memory 16G TABLE

R694
R695
R696
R697
R702
R703
R704
R705
R706
R707
R708
R709

Memory 8G Memory 16G
0Ω CS00002JB38
0Ω CS00002JB38
0Ω CS00002JB38
0Ω CS00002JB38

UNINSTAL
UNINSTAL
UNINSTAL
UNINSTAL
INSTAL
INSTAL
INSTAL
INSTAL

240Ω CS12402FB03
240Ω CS12402FB03
240Ω CS12402FB03
240Ω CS12402FB03
INSTAL
INSTAL
INSTAL
INSTAL
UNINSTAL
UNINSTAL
UNINSTAL
UNINSTAL

+1.2VSUS +SMDDR_VREF_DQ0_M1+0.6V_DDR_VTT +1.2VSUS

SI1, 0417 RF

DB1 12/11, close memory

5

4

3

Place these Caps near Channel A

1uF/10uF 4pcs on each side of connector

+1.2VSUS

C56 1U/6.3V_4
C45 1U/6.3V_4
C383 1U/6.3V_4
C385 1U/6.3V_4
C2 1U/6.3V_4
C42 1U/6.3V_4
C382 1U/6.3V_4
C43 1U/6.3V_4
C447 1U/6.3V_4

C451 1U/6.3V_4
C448 1U/6.3V_4

C450 10U/6.3V_4
C445 10U/6.3V_4

C7 10U/6.3V_4
C449 10U/6.3V_4

C10 10U/6.3V_4
C985 1U/6.3V_4

C986 1U/6.3V_4
C987 1U/6.3V_4
C988 1U/6.3V_4
C989 1U/6.3V_4

SI1, 0421 add

+0.6V_DDR_VTT

C30 1U/6.3V_4
C5 1U/6.3V_4
C393 1U/6.3V_4
C440 1U/6.3V_4
C960 1U/6.3V_4
C961 1U/6.3V_4
C962 1U/6.3V_4
C963 1U/6.3V_4

C959 10U/6.3V_4
C4 10U/6.3V_4

DB1 Intel

+SMDDR_VREF_DQ0_M1

C415 0.1U/16V_4
C405 2.2U/6.3V_4
C941 0.047U/25V_4
C942 0.047U/25V_4
C943 0.047U/25V_4
C944 0.047U/25V_4

DB1 Intel

SI1B, 0603

+0.6V_DDR_VTT

C1003 1U/10V_2
C1002 1U/10V_2
C1004 1U/10V_2
C1008 1U/10V_2
C1000 1U/10V_2
C1001 1U/10V_2
C1005 1U/10V_2
C1007 1U/10V_2

C999 10U/6.3V_4
C1006 10U/6.3V_4

SI1B, 0601 Intel

C1

0.022U/25V_4

2 1

R2 2.7/F_6

R1

24.9/F_4

SM_VREF6

SI1, 0417 RF

C886

C887

68P/50V_4

2200P/50V_4

DB1 RF DB1 RFDB1 RF DB1 RF

C888

0.1U/16V_4

SI1B, 0601

C869
1U/6.3V_4

C870
68P/50V_4

C973
2200P/50V_4

SI1, 0417 RF

2

C867

3.3P/50V_4

C974

C868

2200P/50V_4

68P/50V_4C910 1U/6.3V_4

NB5

NB5

NB5

REF DQ0 M1 Solution

V

+1.2VSUS

R3

1.8K/F_4

+SMDDR_VREF_DQ0_M1

R430

1.8K/F_4

SI1, 0422 Del

SI1, 0417 RF

C865
68P/50V_4

1

C975
2200P/50V_4

16 67Tuesday, December 22, 2015

16 67Tuesday, December 22, 2015

16 67Tuesday, December 22, 2015

C866

3.3P/50V_4

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

DDR4 Memory Down (CH. A)

DDR4 Memory Down (CH. A)

DDR4 Memory Down (CH. A)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1A

1A

1A

5

BYTE6_48-55

DB1 change DB1 change DB1 change DB1 change

+SMDDR_VREF_DQ1_M1

C995

68P/50V_4

SI1, 0427 RF

D D

C C

DDR_DRAMRST#6,16

M_B_A[16:0]6

M_B_DQSN66
M_B_DQSN76

DDR1_ALERT#6

DDRB_ACT#6
DDR1_PAR6

M_B_BS#06
M_B_BS#16
M_B_BG#06

M_B_CLKP06
M_B_CLKN06
M_B_CKE06

M_B_ODT06
M_B_CS#06

M_B_DQSP66
M_B_DQSP76

R428 240/F_4

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16

M_B_DQSP6
M_B_DQSP7

M_B_DQSN6
M_B_DQSN7

M_B1_ZQ0

DDR1_ALERT# DDR1_ALERT# DDR1_ALERT# DDR1_ALERT#

U14

M1

B1
R9

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7

M3

T2

M7

T8
L2

M8

L8

N2
N8

M2

K7
K8
K2

K3
L7

G3

B7
F3

A7

E7
E2

P1
F9
N9

P9
L3
T3

T7

K4

VREFCA
VPP
VPP

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
WE_n/A14
CAS_n/A15
RAS_n/A16

BA0
BA1
BG0

CK_t
CK_c
CKE

ODT
CS

DQSL_t
DQSU_t

DQSL_c
DQSU_c

DML_n/DBIL_n
DMU_n/DBIU_n

RESET_n
ZQ
TEN

ALERT_n
ACT_n
PAR

NC

96-BALL
DDR4

A8G165WB-BCPB

BYTE7_56-63

G2

M_B_DQ52

DQL0

F7

M_B_DQ55

DQL1

H3

M_B_DQ49

DQL2

H7

M_B_DQ54

DQL3

H2

M_B_DQ53

DQL4

H8

M_B_DQ50

DQL5

J3

M_B_DQ48

DQL6

J7

M_B_DQ51

DQL7

A3

M_B_DQ63

DQU0

B8

M_B_DQ57

DQU1

C3

M_B_DQ62

DQU2

C7

M_B_DQ60

DQU3

C2

M_B_DQ59

DQU4

C8

M_B_DQ56

DQU5

D3

M_B_DQ58

DQU6

D7

M_B_DQ61

DQU7

B3

VDD#B3

B9

VDD#B9

D1

VDD#D1

G7

VDD#G7

J1

VDD#J1

J9

VDD#J9

L1

VDD#L1

L9

VDD#L9

R1

VDD#R1

T9

VDD#T9

A1

VDDQ#A1

A9

VDDQ#A9

C1

VDDQ#C1

D9

VDDQ#D9

F2

VDDQ#F2

F8

VDDQ#F8

G1

VDDQ#G1

G9

VDDQ#G9

J2

VDDQ#J2

J8

VDDQ#J8

B2

VSS#B2

E1

VSS#E1

E9

R698 0_4

VSS#E9

G8

VSS#G8

K1

VSS#K1

K9

VSS#K9

M9

M_B_BG#1_1 M_B_BG#1_2 M_B_BG#1 M_B_BG#1_3 M_B_BG#1 M_B_BG#1_4 M_B_BG#1

VSS#M9

N1

VSS#N1

T1

VSS#T1

A2

VSSQ#A2

A8

VSSQ#A8

C9

VSSQ#C9

D2

VSSQ#D2

D8

VSSQ#D8

E3

VSSQ#E3

E8

VSSQ#E8

F1

VSSQ#F1

H1

VSSQ#H1

H9

VSSQ#H9

4

BYTE4_32-39

U15

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16

M_B2_ZQ0

M1

B1
R9

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7

M3

T2

M7

T8
L2

M8

L8

N2
N8

M2

K7
K8
K2

K3
L7

G3

B7
F3

A7

E7
E2

P1
F9
N9

P9
L3
T3

T7

K4

VREFCA
VPP
VPP

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
WE_n/A14
CAS_n/A15
RAS_n/A16

BA0
BA1
BG0

CK_t
CK_c
CKE

ODT
CS

DQSL_t
DQSU_t

DQSL_c
DQSU_c

DML_n/DBIL_n
DMU_n/DBIU_n

RESET_n
ZQ
TEN

ALERT_n
ACT_n
PAR

NC

96-BALL
DDR4

A8G165WB-BCPB

M_B_DQSP46
M_B_DQSP56

M_B_DQSN46
M_B_DQSN56

68P/50V_4

M_B_BG#1 6

C996

+SMDDR_VREF_DQ1_M1

M_B_BS#0
M_B_BS#1
M_B_BG#0

M_B_CLKP0
M_B_CLKN0
M_B_CKE0

M_B_CS#0
M_B_DQSP4

M_B_DQSP5
M_B_DQSN4

M_B_DQSN5

M_B_DQ52 6
M_B_DQ55 6
M_B_DQ49 6
M_B_DQ54 6
M_B_DQ53 6
M_B_DQ50 6
M_B_DQ48 6
M_B_DQ51 6

SI1, 0427 RF

M_B_DQ63 6
M_B_DQ57 6
M_B_DQ62 6
M_B_DQ60 6
M_B_DQ59 6
M_B_DQ56 6
M_B_DQ58 6
M_B_DQ61 6

+1.2VSUS +1.2VSUS +1.2VSUS +1.2VSUS

R714 *0_2

SI1C, 0615 SI1C, 0615 SI1C, 0615 SI1C, 0615

R425 240/F_4

DDR_DRAMRST# DDR_DRAMRST#

DDRB_ACT#DDRB_ACT# DDRB_ACT# DDRB_ACT#

BYTE5_40-47

G2

DQL0

F7

DQL1

H3

DQL2

H7

DQL3

H2

DQL4

H8

DQL5

J3

DQL6

J7

DQL7

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

B3

VDD#B3

B9

VDD#B9

D1

VDD#D1

G7

VDD#G7

J1

VDD#J1

J9

VDD#J9

L1

VDD#L1

L9

VDD#L9

R1

VDD#R1

T9

VDD#T9

A1

VDDQ#A1

A9

VDDQ#A9

C1

VDDQ#C1

D9

VDDQ#D9

F2

VDDQ#F2

F8

VDDQ#F8

G1

VDDQ#G1

G9

VDDQ#G9

J2

VDDQ#J2

J8

VDDQ#J8

B2

VSS#B2

E1

VSS#E1

E9

VSS#E9

G8

VSS#G8

K1

VSS#K1

K9

VSS#K9

M9

VSS#M9

N1

VSS#N1

T1

VSS#T1

A2

VSSQ#A2

A8

VSSQ#A8

C9

VSSQ#C9

D2

VSSQ#D2

D8

VSSQ#D8

E3

VSSQ#E3

E8

VSSQ#E8

F1

VSSQ#F1

H1

VSSQ#H1

H9

VSSQ#H9

M_B_DQ32
M_B_DQ35
M_B_DQ37
M_B_DQ39
M_B_DQ33
M_B_DQ34
M_B_DQ36
M_B_DQ38

M_B_DQ42
M_B_DQ40
M_B_DQ46
M_B_DQ41
M_B_DQ47
M_B_DQ44
M_B_DQ43
M_B_DQ45

R699 0_4

3

M_B_DQ32 6
M_B_DQ35 6
M_B_DQ37 6
M_B_DQ39 6
M_B_DQ33 6
M_B_DQ34 6
M_B_DQ36 6
M_B_DQ38 6

M_B_DQ42 6
M_B_DQ40 6
M_B_DQ46 6
M_B_DQ41 6
M_B_DQ47 6
M_B_DQ44 6
M_B_DQ43 6
M_B_DQ45 6

R715 *0_2

C997

68P/50V_4

SI1, 0427 RF

M_B_DQSP36
M_B_DQSP26

M_B_DQSN36
M_B_DQSN26

R46 240/F_4

2

BYTE2_16-23

U19

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16

M_B_DQSP3
M_B_DQSP2

M_B_DQSN3
M_B_DQSN2

M_B3_ZQ0

M1
B1
R9

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3

T2

M7

T8
L2

M8

L8

N2
N8
M2

K7
K8
K2

K3

L7

G3
B7

F3
A7

E7
E2

P1
F9
N9

P9

L3
T3

T7

VREFCA
VPP
VPP

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
WE_n/A14
CAS_n/A15
RAS_n/A16

BA0
BA1
BG0

CK_t
CK_c
CKE

ODT
CS

DQSL_t
DQSU_t

DQSL_c
DQSU_c

DML_n/DBIL_n
DMU_n/DBIU_n

RESET_n
ZQ
TEN

ALERT_n
ACT_n
PAR

NC

K4

96-BALL
DDR4

A8G165WB-BCPB

+SMDDR_VREF_DQ1_M1 +SMDDR_VREF_DQ1_M1

M_B_BS#0
M_B_BS#1
M_B_BG#0

M_B_CLKP0
M_B_CLKN0
M_B_CKE0 M_B_CKE0

M_B_ODT0 M_B_ODT0M_B_ODT0
M_B_CS#0

DDR_DRAMRST#

DDR1_PARDDR1_PAR DDR1_PARDDR1_PAR

BYTE3_24-31 BYTE1_8-15

G2

M_B_DQ27
M_B_DQ28
M_B_DQ30
M_B_DQ24
M_B_DQ26
M_B_DQ29
M_B_DQ31
M_B_DQ25

M_B_DQ22
M_B_DQ16
M_B_DQ18
M_B_DQ21
M_B_DQ23
M_B_DQ17
M_B_DQ19
M_B_DQ20

M_B_DQ27 6
M_B_DQ28 6
M_B_DQ30 6
M_B_DQ24 6
M_B_DQ26 6
M_B_DQ29 6
M_B_DQ31 6
M_B_DQ25 6

M_B_DQ22 6
M_B_DQ16 6
M_B_DQ18 6
M_B_DQ21 6
M_B_DQ23 6
M_B_DQ17 6
M_B_DQ19 6
M_B_DQ20 6

R716 *0_2

+2.5VSUS+2.5VSUS+2.5VSUS+2.5VSUS

68P/50V_4

SI1, 0427 RF

M_B_DQSP16
M_B_DQSP06

M_B_DQSN16
M_B_DQSN06

C998

M_B_CLKP0
M_B_CLKN0

+1.2VSUS+1.2VSUS+1.2VSUS+1.2VSUS

R48 240/F_4

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16

M_B_BS#0
M_B_BS#1
M_B_BG#0

M_B_CS#0
M_B_DQSP1

M_B_DQSP0
M_B_DQSN1

M_B_DQSN0

M_B4_ZQ0

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B3
VDD#B9
VDD#D1
VDD#G7
VDD#J1
VDD#J9
VDD#L1
VDD#L9
VDD#R1
VDD#T9

VDDQ#A1
VDDQ#A9
VDDQ#C1
VDDQ#D9
VDDQ#F2
VDDQ#F8
VDDQ#G1
VDDQ#G9
VDDQ#J2
VDDQ#J8

VSS#B2
VSS#E1
VSS#E9
VSS#G8
VSS#K1
VSS#K9
VSS#M9
VSS#N1
VSS#T1

VSSQ#A2
VSSQ#A8
VSSQ#C9
VSSQ#D2
VSSQ#D8
VSSQ#E3
VSSQ#E8
VSSQ#F1
VSSQ#H1
VSSQ#H9

F7
H3
H7
H2
H8
J3
J7

A3
B8
C3
C7
C2
C8
D3
D7

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

B2
E1
E9

R701 0_4

G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

U20

M1

B1

R9

P3

P7
R3
N7
N3

P8

P2
R8
R2
R7
M3

T2
M7

T8

L2
M8

L8

N2
N8
M2

K7

K8

K2

K3

L7
G3

B7

F3

A7

E7

E2

P1

F9
N9

P9

L3

T3

T7

K4

VREFCA
VPP
VPP

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
WE_n/A14
CAS_n/A15
RAS_n/A16

BA0
BA1
BG0

CK_t
CK_c
CKE

ODT
CS

DQSL_t
DQSU_t

DQSL_c
DQSU_c

DML_n/DBIL_n
DMU_n/DBIU_n

RESET_n
ZQ
TEN

ALERT_n
ACT_n
PAR

NC

96-BALL
DDR4

A8G165WB-BCPB

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B3
VDD#B9
VDD#D1
VDD#G7

VDD#J1

VDD#J9
VDD#L1
VDD#L9
VDD#R1
VDD#T9

VDDQ#A1
VDDQ#A9
VDDQ#C1
VDDQ#D9
VDDQ#F2
VDDQ#F8
VDDQ#G1
VDDQ#G9
VDDQ#J2
VDDQ#J8

VSS#B2
VSS#E1
VSS#E9
VSS#G8
VSS#K1
VSS#K9
VSS#M9
VSS#N1

VSS#T1

VSSQ#A2
VSSQ#A8
VSSQ#C9
VSSQ#D2
VSSQ#D8
VSSQ#E3
VSSQ#E8
VSSQ#F1
VSSQ#H1
VSSQ#H9

1

BYTE0_0-7

G2

M_B_DQ14

F7

M_B_DQ8

H3

M_B_DQ11

H7

M_B_DQ12

H2

M_B_DQ10

H8

M_B_DQ13

J3

M_B_DQ15

J7

M_B_DQ9

A3

M_B_DQ2

B8

M_B_DQ1

C3

M_B_DQ6

C7

M_B_DQ5

C2

M_B_DQ7

C8

M_B_DQ0

D3

M_B_DQ3

D7

M_B_DQ4

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

DB1 Option for 16Gbx16 dieDB1 Option for 16Gbx16 dieDB1 Option for 16Gbx16 dieDB1 Option for 16Gbx16 die

B2
E1
E9

R700 0_4

G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

R717 *0_2

M_B_DQ14 6
M_B_DQ8 6
M_B_DQ11 6
M_B_DQ12 6
M_B_DQ10 6
M_B_DQ13 6
M_B_DQ15 6
M_B_DQ9 6

M_B_DQ2 6
M_B_DQ1 6
M_B_DQ6 6
M_B_DQ5 6
M_B_DQ7 6
M_B_DQ0 6
M_B_DQ3 6
M_B_DQ4 6

17

Hynix AKD5JGETW00--H5TC4G63AFR-PBA

M_B_BG#1_1

Ve

P/NVendor

KD5EG0TL00

A

MIC 16G

Elpida

B B

SAMSUNG

SI1, 1/12 follow Intel DG

M_B_BS#0
M_B_BS#1
M_B_BG#0
M_B_CKE0
M_B_CS#0
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16
M_B_ODT0
DDRB_ACT#
DDR1_PAR
M_B_BG#1

A A

R480 34.8/F_4
R490 34.8/F_4
R441 34.8/F_4
R17 34.8/F_4
R485 34.8/F_4
R437 34.8/F_4
R469 34.8/F_4
R458 34.8/F_4
R493 34.8/F_4
R35 34.8/F_4
R473 34.8/F_4
R18 34.8/F_4
R446 34.8/F_4
R454 34.8/F_4
R445 34.8/F_4
R449 34.8/F_4
R453 34.8/F_4
R15 34.8/F_4
R438 34.8/F_4
R479 34.8/F_4

R491 34.8/F_4
R466 34.8/F_4
R489 34.8/F_4
R459 34.8/F_4
R764 34.8/F_4

ndor P/N

MT40A1G16HBA-083E:A

+0.6V_DDR_VTT

+0.6V_DDR_VTT 16,51,62
+1.2VSUS 6,13,16,51,62
+2.5VSUS 16,53

5

DB1 Follow Intel suggestion

M_B_CLKP0
M_B_CLKN0

DDR1_ALERT#

+1.2VSUS

R29 36/F_4
R30 36/F_4

R39 51_4

C900 0.01U/16V_2
C899 0.01U/16V_2
C901 0.01U/16V_2
C902 0.01U/16V_2R26 34.8/F_4
C898 0.01U/16V_2

DB1 12/11, close memory

C911 1U/6.3V_4

+2.5VSUS

C912 1U/6.3V_4
C913 1U/6.3V_4
C914 1U/6.3V_4
C915 1U/6.3V_4
C916 1U/6.3V_4
C918 1U/6.3V_4
C917 1U/6.3V_4
C952 10U/6.3V_4
C953 10U/6.3V_4
C977 68P/50V_4

DB1 12/11, close memory

SI1, 0417 RF

SI1B, 0603

+0.6V_DDR_VTT

SI1B, 0603

+1.2VSUS

C1012

0.1U/16V_4

R698
R699
R700
R701
R714
R715
R716
R717
R710
R711
R712
R713

4

R710 0_2

M_B_BG#1_2

R711 0_2

M_B_BG#1_3

R712 0_2

M_B_BG#1_4

R713 0_2

DB1 Option for 16Gbx16 die
Close DDR ball

Memory 8G & Memory 16G TABLE

Memory 8G Memory 16G
0Ω CS00002JB38
0Ω CS00002JB38
0Ω CS00002JB38
0Ω CS00002JB38

UNINSTAL

UNINSTAL

UNINSTAL

UNINSTAL

INSTAL

INSTAL

INSTAL

INSTAL

240Ω CS12402FB03
240Ω CS12402FB03
240Ω CS12402FB03
240Ω CS12402FB03
INSTAL
INSTAL
INSTAL
INSTAL
UNINSTAL
UNINSTAL
UNINSTAL
UNINSTAL

Place these Caps near Channel B

1uF/10uF 4pcs on each side of connector

+1.2VSUS

C396 1U/6.3V_4
C41 1U/6.3V_4
C48 1U/6.3V_4
C3 1U/6.3V_4
C400 1U/6.3V_4
C44 1U/6.3V_4
C384 1U/6.3V_4
C46 1U/6.3V_4
C11 1U/6.3V_4

C381 1U/6.3V_4
C394 1U/6.3V_4

C404 10U/6.3V_4
C380 10U/6.3V_4

C392 10U/6.3V_4
C9 10U/6.3V_4

C399 10U/6.3V_4
C980 1U/10V_2

C981 1U/10V_2
C982 1U/10V_2
C983 1U/10V_2
C984 1U/10V_2

SI1, 0421 add

+0.6V_DDR_VTT

+SMDDR_VREF_DQ1_M1

+SMDDR_VREF_DQ1_M1

C871

3.3P/50V_4

C395 1U/6.3V_4
C428 1U/6.3V_4
C398 1U/6.3V_4
C439 1U/6.3V_4
C955 1U/6.3V_4
C956 1U/6.3V_4
C957 1U/6.3V_4
C958 1U/6.3V_4

C403 10U/6.3V_4
C954 10U/6.3V_4

DB1 Intel

C6 0.1U/16V_4
C402 2.2U/6.3V_4
C945 0.047U/25V_4
C946 0.047U/25V_4
C947 0.047U/25V_4
C948 0.047U/25V_4

SI1B, 0603

DB1 Intel

SI1, 0417 RF SI1, 0417 RF

C978

C872

2200P/50V_4

68P/50V_4

DB1 RF

3

SMDDR_VREF_DQ1_M36

+1.2VSUS

C878
68P/50V_4

2

R12 2.7/F_6

C12

0.022U/25V_4

2 1

C979

3.3P/50V_4

+1.2VSUS

R7

1.8K/F_4

R5

1.8K/F_4

REF DQ1 M1 Solution

V

SMDDR_VREF_DQ1_M3 +SMDDR_VREF_DQ1_M1

R13 24.9/F_4

C877
2200P/50V_4

C879

0.1U/16V_4

DB1 RF

SI1, 0422 Del

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

DDR4 Memory Down (CH. B)

DDR4 Memory Down (CH. B)

NB5

NB5

NB5

DDR4 Memory Down (CH. B)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

17 67Tuesday, December 22, 2015

17 67Tuesday, December 22, 2015

17 67Tuesday, December 22, 2015

5

4

3

2

1

PV, 0917, change to short pad

EN_5V_3V

D D

+3VPCU

SI1, 0311 chane to +3VPCU

R49
10K/F_4

2V5_PG53

SLP_S4#_3R3,15,18,30,53,62

C C

SLP_S4#_3R3,15,18,30,53,62

D18

MEK500V-40

D19

2 1

MEK500V-40

PV, 0917, change to short pad

DDR_VTT_PG_CTRL6,51

+3V_DEEP_SUS

21

R846 100/F_4

R605*0_4/S

R604*0_4/S

R606*0_4/S

R44*0_4/S

EN_5V 50

EN_3V 50

EN_1V8 53

EN_VRPVDDQ 51

PV, 0827

R158100K/F_4

R31*0_4/S

SI1B, 0505 R89 change to NI

R89*10K/F_4

EN_2V5 53

EN_VRPVTT 51

EN_PVCC_PRIM 55

+3V_ALW

R380 100K/F_4

SI, 0429 CHANGE TO 100K

SI, 0429 CHANGE to 10kohm

R379 10K/F_4

C327

0.1U/16V_4

EN_5V_3V

EN_5V_3V 36,39

18

B B

PWR_GOOD_33,15,46,64,65

R348*0_4/S

R332*0_4/S

EN_PVCCIO 54

VRAVR_ON 56,59

PV, 0917, change to short pad

SLP_S3#_3R3,15,23,30,43,46,62,64

KBC_PWR_ON45,62,65

EXT_PWR_GATE#3,65

A A

5

KBC_PWR_ON

SI2, 0528

R276*0_4/S

R25610K/F_4

R238*0_4

C258

*0.022U/25V_4

2 1

4

C271
*0.022U/25V_4

2 1

EN_P1V5S 52

EN_1V0A 52,55

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Power enable

Power enable

NB5

NB5

3

2

NB5

Power enable

Date: Sheet of

Date: Sheet of

Date: Sheet

1

1A

1A

1A

18 67Tuesday, December 22, 2015

18 67Tuesday, December 22, 2015

18 67Tuesday, December 22, 2015

of

5

4

3

2

1

Fingerprint Conn

D D

ESD3

USBP8+_C FPR_OFF
USBP8-_C FPR_LOCK#

C C

1

1

2

2

3

3

AZC099-04S

SI1B, 0609

USBP8-7
USBP8+7

FPR_LOCK#4
FPR_OFF4

B B

R672 *0_4/S
R671 *0_4/S

FPR_LOCK#
FPR_OFF

+3V

6

6

5

5

4

4

C379

0.1U/16V_4

R673

10K/F_4

USBP8-_C
USBP8+_C

C372

4.7U/6.3V_4

+3V

CN27

1
2
3
4
5

7

6 8

FPR conn.

DFFC06FR116

50503-0060n-001-6p-l

19

A A

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

NB5

NB5

NB5

5

4

3

2

Date: Sheet of

Date: Sheet of

Date: Sheet of

FPR

FPR

FPR

19 67Tuesday, December 22, 2015

19 67Tuesday, December 22, 2015

19 67Tuesday, December 22, 2015

1

1A

1A

1A

1

2

3

4

5

6

7

8

LID Switch

INT_eDP_TXN35

INT_eDP_TXP35

A A

+VIN

L6 *0_6/S

L5 *0_6/S

C27

4.7U/25V_6

+VIN_BLIGHT

60 mil

C24

0.1U/25V_4

C29

0.1U/25V_4

C32

0.1U/25V_4

C33

0.1U/25V_4

MV, 1211

+3V

C14

0.1U/16V_4

2 1

+3VLCD_CON

C19
10U/6.3V_4

C921

3.3P/50V_4

C922
68P/50V_4

DB1 RF

PCH_DPST_PWM PCH_DPST_PWM_R

R436 1K/F_4

C414 22P/50V_4

OUT
GND

SI2, 0622

1
2

L1

*0_6/S

C20

0.01U/50V_4

2 1

PCH_DPST_PWM5

C21
1U/6.3V_4

B B

PCH_DISP_ON5,20

PCH_DISP_ON

R32
100K/F_4

U1

5

IN

4

IN

3

ON/OFF

NCT3522U

for eDP,stuff U2 & L8

for LVDS,stuff C29 & R23

LID_SW#_328,36,37,46

PCH_LVDS_BLON5

PCH_LVDS_BLON

R443 2K/F_4

R442
100K/F_4

0.1U/16V_4

+3V

D8MEK500V-40

+3V

C15

2 1

L3 600,1A_6

C426

4.7U/6.3V_4

SI2, 0630

INT_eDP_TXN25

INT_eDP_TXP25

INT_eDP_AUXP5
INT_eDP_AUXN5

BLON_CON

INT_eDP_TXN15
INT_eDP_TXP15

INT_eDP_TXN05
INT_eDP_TXP05

+3VLCD_CON

INT_eDP_HPD_Q5

2 1

C23 0.1U/16V_4

VCC_CAMERA

C28 4.7U/6.3V_4

C22 1U/6.3V_4

C421 0.1U/16V_4
C420 0.1U/16V_4

C423 0.1U/16V_4
C422 0.1U/16V_4

C418 0.1U/16V_4
C419 0.1U/16V_4

C425 0.1U/16V_4
C424 0.1U/16V_4

C16 0.1U/16V_4
C17 0.1U/16V_4

R22 100K/F_4

SI1, 0422 change

CAMERA_ON4

USBP9+7
USBP9-7

+VIN_BLIGHT

USBP9+
USBP9-

1
4 3

L19 MCM2012B900GBE

INT_eDP_TXN3_R
INT_eDP_TXP3_R

INT_eDP_TXN2_R
INT_eDP_TXP2_R

INT_eDP_TXN1_R
INT_eDP_TXP1_R

INT_eDP_TXN0_R
INT_eDP_TXP0_R

INT_eDP_AUXP_R
INT_eDP_AUXN_R

INT_eDP_HPD_Q

PCH_DPST_PWM_R

DIGITAL_CLK_L
DIGITAL_D1_R

R455 *0_4
R460 *0_4

USBP9+_C
USBP9-_C

LVDS Conn.

2

USBP9+_CVCC_CAMERA
USBP9-_C

eDP conn.

CN7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Y08 type

20

G_0

G_1

G_2

G_4

G_5

10P/50V_4

I2C_TS_SCL
I2C_TS_SDA
TOUCH_RST#
TOUCH_INT#
PCH_DISP_ON_R

NB5

NB5

NB5

7

PVR, 1027

R675 *0_4/S

C417

TOUCH_RST#

2 1

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

eDP/CAM/D-MIC/TS

eDP/CAM/D-MIC/TS

eDP/CAM/D-MIC/TS

Date: Sheet of

Date: Sheet of

Date: Sheet of

1
2
3

11
4
5
6
7

12
8
9
10

CN11

TS_CONN

C37
*10P/50V_4

DIGITAL_D1_R
DIGITAL_CLK_L

20 67Tuesday, December 22, 2015

20 67Tuesday, December 22, 2015

20 67Tuesday, December 22, 2015

8

1A

1A

1A

SI1, 3/19 add for HP command

+3V_TS +3V_TS

C C

PCH_DISP_ON5,20

D D

TOUCH_PWR_EN8

+3V2,3,4,5,7,8,9,10,15,19,21,22,24,27,28,29,37,38,39,40,44,45,48,49,56,62,64

+3VPCU

+5V8,24,25,27,34,35,38,62,64,65

+VIN44,48,49,50,51,52,53,54,55,57,58,59,60,61,66

1

2

R791
100K/F_4

2

5

3

Q55B

PJX138K

6 1
34

PJX138K

Q55A

R793 *0_4

+5V +3V

R52
*100K/F_4

3

2

1

Q3
*PJE138K

R792
100K/F_4

R50 *0_4/S

SI2, 0622

4

2

PCH_DISP_ON_R

1

Q27
*AO3409

3

+3V

MV, 12/11

R51
*0_6/S

ADP_PRES_OUT3,45

+3V_TS

5

DIGITAL_D124

DIGITAL_CLK24

+3V_TS

R503
1M/F_4

D9 MEK500V-40

TOUCH_INT#

I2C_TS_SCL
I2C_TS_SDA

I2C_TS_SCL
I2C_TS_SDA

6

CHRG_IN

SI1, 2/5 follow Caesar

SI2, 0701, close CN11

C1021 12P/50V_4
C1022 12P/50V_4

C427 10P/50V_4

L18

SBY100505T-601Y-N

DB1 change value for RF

+3V_TS

PV, 0826, RF request

+3V_TS

R77510K/F_4
R5410K/F_4

R5310K/F_4

TOUCH_RST#4

TOUCH_INT#4

12

I2C_TS_SCL4
I2C_TS_SDA4

C1028
12P/50V_4

5

3 Levels Input:
L: Low
H: High
M: VDD33/2, connect both pull-up and pull-down resistors

INT_DDI1_AUXN5

INT_DDI1_AUXP5

D D

C C

HDMI_HPD_CON5

TP6

B B

A A

DOCK_ID1==> HIGH, DP PRIORITY 1
DOCK_ID1==> LOW, HDMI PRIORITY 1

MODE = L: Control Switching Mode, HDMI ID disable
= H: Automatic Switching Mode, HDMI ID disable
= M: Automatic Switching Mode, HDMI ID enable

TMDS_DDCBUF = L: DDC pass through
= H: DDC active buffer
= M: DDC pass through with 40 kohm pull up resistor

DDI1_TX0_P5

DDI1_TX0_N5

DDI1_TX1_P5

DDI1_TX1_N5

DDI1_TX2_P5

DDI1_TX2_N5

DDI1_TX3_P5

DDI1_TX3_N5

PEQ = L: default, LEQ, compensate channel loss up to 12dB @ HBR2
= H: HEQ, compensate channel loss up to 15dB @ HBR2
= M: LLEQ, compensate channel loss up to 5dB @ HBR2

DOCK_ID17,43

5

C85 0.1U/16V_4

C86 0.1U/16V_4

C93 0.1U/16V_4

C110 0.1U/16V_4

C88 0.1U/16V_4

C89 0.1U/16V_4

C99 0.1U/16V_4

C122 0.1U/16V_4

+1.5V

C120

0.1U/16V_4

TMDS_PRE = L: no pre-emphasis
= H: 1.5dB pre-emphasis

R810

4.7K/F_4

Q59
PJE138K

DP_DEMUX_SW

= M: 3.0dB pre-emphasis

+3V

3

2

1

SI1, 0424 Add

4

C71 0.1U/16V_4
C70 0.1U/16V_4

+3V

R555

4.7K/F_4

R557

4.7K/F_4

+3V

R119
*4.7K_4

R118
*4.7K_4

+3V

4

+1.5V

C68

0.01U/50V_4

TMDS_DDCBUF DP_CA_DET

DPB0_C_DP
DPB0_C_DN

DPB1_C_DP
DPB1_C_DN
DEMUX_PEQ
DPB2_C_DP
DPB2_C_DN

DPB3_C_DP
DPB3_C_DN

R133

4.7K/F_4

R132

4.7K/F_4

DPB_AUX_C_DN
DPB_AUX_C_DP

DEMUX_MODE

DP_DATA_AUX_DN43

DP_CLK_AUX_DP43

+3V

C69

0.1U/16V_4

56

57

U3

58

EPAD

59

EPAD

EPAD

60

EPAD

1

VDD15

2

TMDS_DDCBUF

3

IN_D0p

4

IN_D0n

5

IN_HPD

6

IN_D1p

7

IN_D1n

8

PEQ

9

IN_D2p

10

IN_D2n

11

IN_CA_DET

12

IN_D3p

13

IN_D3n

14

VDD15

PS8339A

+3V

R146

*4.7K_4

TMDS_PRE

R147
*4.7K_4

C_IN_CLK#22

C_IN_CLK22

HDMI_HPD22

C_TX0_HDMI-22

C_TX0_HDMI+22

VDD33

TMDS_CLKn15TMDS_CLKp16TMDS_HPD17TMDS_CH0n18TMDS_CH0p19TMDS_PRE20TMDS_CH1n21TMDS_CH1p22TMDS_RT23TMDS_CH2n24TMDS_CH2p25GND26REXT27VDD15

EPAD61EPAD62EPAD

63

55

52

54

53

MODE

DP_AUXp_SCL

DP_AUXn_SDA

PS8339A

3

DPB_DDCCLK 5
DPB_DDCDATA 5

HDMI_SCL_R 22
HDMI_SDA_R 22

4

DMUX_PD

SI1, 0412 add

DP_DEMUX_SW

DP_CFG0

R806 *0_4

45

50

44

49

48

47

46

IN_AUXn51IN_AUXp

TMDS_SCL

TMDS_SDA

IN_DDC_SCL

IN_DDC_SDA

3

43

PD

GND

SW/SDA_CTL

DP_CA_DET

DP_CFG0/SCL_CTL

I2C_CTL_EN

DP_HPD

DP_CFG1

28

Need apply PN

R138

4.99K_4

EPAD69EPAD68EPAD

VDD15
DP_D0p
DP_D0n

DP_D1p
DP_D1n

GND
DP_D2p
DP_D2n

DP_D3p
DP_D3n

EPAD
EPAD
EPAD

+1.5V

67

C91

42
41
40
39
38
37
36
35
34
33
32
31
30
29

64
65
66

0.01U/50V_4

C_TX2_HDMI+ 22
C_TX2_HDMI- 22
C_TX1_HDMI+ 22
C_TX1_HDMI- 22

+1.5V

DP_CA_DET

TMDS_RT

C78

0.1U/16V_4

+3V

+3V

R87
*4.7K_4

R88
*4.7K_4

DP_CFG1

R142

4.7K/F_4

R149
*4.7K_4

TMDS_RT = L: Standard open drain driver
= H: Open drain driver with termination resistors

2

DP_CFG0 = L: default, automatic EQ enable & AUX interception enable
= H: automatic EQ disable & AUX interception enable
= M: automatic EQ disable & AUX interception disable, no pre-emphasis, 800mVpp swing

DP_DATA_AUX_DN
DP_CLK_AUX_DP

1

R100 100K/F_4
R99 100K/F_4

PVR,10/19

DP_CA_DET 43

DPB_DOCK_D0P 43
DPB_DOCK_D0N 43

DPB_DOCK_D1P 43
DPB_DOCK_D1N 43

DP_HPD 43

+3V

R124
*4.7K_4

DP_CFG1 = L: default, auto test disable & input offset cancellation enable
= H: auto test enable & input offset cancellation enable
= M: auto test disable & input offset cancellation disable

R123
*4.7K_4

PROJECT : Y0F

PROJECT : Y0F

PROJECT : Y0F

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

NB5

NB5

NB5

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

DEMUX 8339A

DEMUX 8339A

DEMUX 8339A

1

R103
1M_4

21

+3V

21 67Tuesday, December 22, 2015

21 67Tuesday, December 22, 2015

21 67Tuesday, December 22, 2015

1A

1A

1A