FUJITSU MB90335 DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

MB90335 Series

MB90337/F337/V330A

DESCRIPTION

■

The MB90335 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but also MiniHost operation. It is equipped with functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of mobile devices that support USB communications. While inheriting the AT architecture of the F addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, long word processing is now available by introducing a 32-bit accumulator.

* : F

MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.

MC* family, the instruction set supports the C language and extended

FEATURES

■

••••

Clock

• Built-in oscillation circuit and PLL clock frequency multiplication circuit

• Oscillation clock The machine clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz) Clock for USB is 48 MHz Machine clock frequency of 6 MHz, 12 MHz or 24 MHz selectable

• Minimum execution time of instruction : 41.6 ns (6 MHz oscillation clock, 4-time multiplied : machine clock 24 MHz and at operating V

••••

The maximum memory space:16 MB

••••

24-bit addressing

••••

Bank addressing

PACKAGE

■

CC = 3.3 V)

(Continued)

64-pin plastic LQFP

(FPT-64P-M09)

MB90335 Series

(Continued)

••••

Instruction system

Data types: Bit, Byte, Word, Long word Addressing mode (23 types) Enhanced high-precision computing with 32-bit accumulator Enhance Multiply/Divide instructions with sign and the RETI instruction

••••

Instruction system compatible with high-level language (C language) and multitask

• Employing system stack pointer

• Instruction set symmetry and barrel shift instructions

••••

Program Patch Function (2 address pointer)

••••

4-byte instruction queue

••••

Interrupt function

• Priority levels are programmable

• 20 interrupts

••••

Data transfer function

• Expanded intelligent I/O service function (EI

• µDMAC : Maximum 16 channels

OS) : Maximum of 16 channels

••••

Low Power Consumption Mode

• Sleep mode (with the CPU operating clock stopped)

• Time - base timer mode (with the oscillator clock and time - base timer operating)

• Stop mode (with the oscillator clock stopped)

• CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles)

••••

Package

• LQFP-64P (FPT-64P-M09 : 0.65 mm pin pitch)

••••

Process : CMOS technology

••••

Operation guaranteed temperature:

−−−−

°°°°

C to

++++

°°°°

C (0

°°°°

C to

++++

°°°°

C when USB is in use)

MB90335 Series

INTERNAL PERIPHERAL FUNCTION (RESOURCE)

■■■■

••••

I/O port: Max 45 ports

••••

Time-base timer : 1channel

••••

Watchdog timer : 1 channel

••••

16-bit reload timer : 1 channel

••••

Multi-functional timer

• 8/16-bit PPG timer (8-bit × 4 channels or 16-bit × 2 channels) the period and duty of the output pulse can be set by the program.

• 16-bit PWC timer : 1 channel Timer function and pulse width measurement function

••••

UART : 2 channels

• Equipped with Full duplex double buffer with 8-bit lenghth

• Asynchronous transfer or clock-synchronous serial (I/O extended serial) transfer can be set.

••••

Extended I/O serial interface: 1 channel

••••

DTP/External interrupt circuit (8 channels)

• Activate the extended intelligent I/O service by external interrupt input

• Interrupt output by external interrupt input

••••

Delayed interrupt output module

• Output an interrupt request for task switching

••••

USB : 1 channel

• USB function (conform to USB 2.0 Full Speed)

• Supports for Full Speed/Endpoint are specifiable up to six.

• Dual port RAM (The FIFO mode is supported).

• Transfer type: Control, Interrupt, Bulk or Isochronous transfer possible

• USB Mini Host function

••••

C Interface : 1 channel

• Supports Intel SM bus standards and Phillips I

C bus standards

• Two-wire data transfer protocol specification

• Master and slave transmission/reception

Note : I

C licenae :

Purchase of Fujitsu I

C components conveys a license under the Philips I2C Patent Rights to use,

these components in an I

C system provided that the system conforms to the I2C Standard Specification as

defined by Phillips.

MB90335 Series

PRODUCT LINEUP

■■■■

1. MB90335 Series

Part number MB90V330A MB90F337 MB90337

Type For evaluation Built-in FLASH MEMORY Built-in Mask ROM ROM capacity No 64 Kbyte RAM capacity 28 Kbyte 4 Kbyte Emulator-specific

power supply *

Number of basic instructions Minimum instruction execu-

CPU functions

Ports I/O Ports(CMOS) 45 ports

UART

16-bit reload timer

Multi-functional timer

DTP/External interrupt

C 1 channel

Extended I/O serial interface 1 channel

USB

Withstand voltage of 5 V 6 ports (Excluding VBUS and I/O for I Low Power Consumption

Mode Process CMOS Operating voltage VCC 3.3 V ± 0.3 V (at maximum machine clock 24 MHz)

tion time Addressing type Program Patch Function maximum memory space

Equipped with full-duplex double buffer Clock synchronous or asynchronous operation selectable. It can also be used for I/O serial. Built-in special baud-rate generator Built-in 2 channels

16-bit reload timer operation Built-in 1 channel

8/16-bit PPG timer (8-bit mode × 4 channels, 16-bit mode × 2 channels) 16-bit PWC timer × 1 channel

8 channels Interrupt factor : “L”→“H” edge /“H”→“L” edge /“L” level /“H” level selectable

1 channel USB function (conform to USB 2.0 Full Speed) USB Mini-HOST function

Sleep mode/Timebase timer mode/Stop mode/CPU intermittent mode

Used bit 

: 351 instructions : 41.6 ns / at oscillation of 6 MHz

(When 4 times is used : Machine clock of 24 MHz) : 23 types : For two address pointers : 16 Mbyte

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB2147-

01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details.

PACKAGES AND PRODUCT MODELS

■

Package MB90337 MB90F337 MB90V330A

FPT-64P-M09 (LQFP-0.65 mm) × PGA-299C-A01 (PGA) × ×

: Yes × : No

Note : For detailed information on each package, see “■ PACKAGE DIMENSIONS”.

PIN ASSIGNMENT



■■■■

(TOP VIEW)

P51

P41/TOT0

P40/TIN0

P67/INT7/SDA0

P66/INT6/SCL0

P65/INT5/PWC

P64/INT4/SCK

P63/INT3/SOT

P62/INT2/SIN

P61/INT1

P60/INT0

P27/PPG3

P26/PPG2

P25/PPG1

P50

646362616059585756555453525150

MB90335 Series

Vcc 49

VBUS

Vss

DVM

DVP

Vcc Vss

HVM

HVP

Vcc

HCONX

P42/SIN0 P43/SOT0 P44/SCK0

P45/SIN1 P46/SOT1 P47/SCK1

10 11 12 13 14 15 16

1 2 3 4 5 6 7 8 9

171819202122232425262728293031

Vss

P52

P53

MD2

MD1

MD0

RST

P54

P00

P01

P02

P03

P04

P05

P06

32 P07

Vss

P24/PPG0

P23

P22

P21

P20

P17

P16

P15

P14

P13

P12

P11

P10

(FPT-64P-M09)

MB90335 Series

PIN DESCRIPTION

■■■■

Pin no.

QFPM09

46 , 47 X0, X1 A

23 RST

25 to 32 P00 to P07 I

33 to 40 P10 to P17 I

41 to 44 P20 to P23 D General purpose input/output port.

51 to 53

16 50 P50 K General purpose input/output port.

64 P51 K General purpose input/output port.

17, 18 P52, P53 K General purpose input/output port.

24 P54 K General purpose input/output port.

Pin name

P24

PPG0 Functions as output pins of PPG timers ch0.

P25 to P27

PPG1 to

PPG3

P40

TIN0 Function as event input pin of 16-bit reload timer.

P41

TOT0 Function as output pin of 16-bit reload timer.

P42

SIN0 Functions as a data input pin for UART ch0.

P43

SOT0 Functions as a data output pin for UART ch0.

P44

SCK0 Functions as a clock I/O pin for UART ch0.

P45

SIN1 Functions as a data input pin for UART ch1.

P46

SOT1 Functions as a data output pin for UART ch1.

P47

SCK1 Functions as a clock I/O pin for UART ch1.

Circuit

type*

Status at

reset/

function

Oscillation

status

F Reset input External reset input pin.

Port input

(High-Z)

It is a terminal which connects the oscillator. When connecting an external clock, leave the X1 pin side unconnected.

General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD00 to RD07 = 1) by the pull-up resistor setting register (RDR0). (When the power output is set, it is invalid.)

General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD10 to RD17 = 1) by the pull-up resistor setting register (RDR1). (When the power output is set, it is invalid.)

General purpose input/output port.

General purpose input/output port. Functions as output pins of PPG timers ch1 to ch3. General purpose input/output port.

General purpose input/output port.

Function

* : For circuit information, see “■ I/O CIRCUIT TYPE”.

(Continued)

MB90335 Series

(Continued)

Pin no.

QFPM09

54, 55

Pin name

P60, P61

INT0, INT1 Functions as the input pin for external interrupt ch0 and ch1.

Circuit

type*

P62

INT2 Functions as the input pin for external interrupt ch2.

SIN Data input pin for simple serial IO.

P63

INT3 Functions as the input pin for external interrupt ch3.

SOT Data output pin for simple serial IO

P64

INT4 Functions as the input pin for external interrupt ch4.

SCK Clock I/O pin for simple serial IO.

P65

INT5 Functions as the input pin for external interrupt ch5.

PWC Functions as the PWC input pin.

P66

INT6 Functions as the input pin for external interrupt ch6.

SCL0

P67

INT7 Functions as the input pin for external interrupt ch7.

SDA0

1 VBUS C VBUS input Status detection pin of USB cable. 3DVMJ 4 DVP J USB function D + pin. 7 HVM J USB Mini Host D − pin. 8 HVP J USB Mini Host D + pin.

10 HCONX E High output External pull-up resistor connection pin.

21, 22 MD1, MD0 B

20 MD2 G

5Vcc 9Vcc Power supply pin.

49 Vcc  Power supply pin.

2Vss Power supply pin (GND).

6Vss Power supply pin (GND). 19 Vss  Power supply pin (GND). 48 Vss  Power supply pin (GND).

Status at

reset/

function

Port input

(High-Z)

USB input

(SUSPEND)

Mode input

Power supply

Function

General purpose input/output port. (withstand voltage of 5 V)

General purpose input/output port.

Functions as the input/output pin for I output must be placed in High-Z state during I operation.

General purpose input/output port.

Functions as the I

C interface data input/output pin. The port out-

put must be placed in High-Z state during I

USB function D − pin.

Input pin for selecting operation mode. Power supply pin.

C interface clock. The port

C interface

C interface operation.

* : For circuit information, see “■ I/O CIRCUIT TYPE”.

MB90335 Series

I/O CIRCUIT TYPE

■■■■

Type Circuit Remarks

Clock input

Standby control signal

Hysteresis input

NoutNch

Hysteresis input

• Oscillation feedback resistance : approx. 1 MΩ

• With standby control

• CMOS hysteresis input

• Hysteresis input

• Nch open drain output

Standby control signal

• CMOS output

• CMOS hysteresis input

Pch

Pout

(With input interception function at standby)

Nch

Nout

Note : • The I/O ports and internal

resources share one output buffer for their outputs.

Hysteresis input

Standby control signal

• The I/O port and internal resources share one input buffer for their input.

• CMOS output

Pch

Pout

Nch

Nout

• CMOS hysteresis input with pull-up

• Resistor approx. 50 kΩ

Hysteresis input

• CMOS hysteresis input with pull-down

• Resistor approx. 50 kΩ

Hysteresis input

• FLASH product is not provided with pull-down resistor.

(Continued)

MB90335 Series

(Continued)

Type Circuit Remarks

• CMOS output

Open drain control

Pch

Nch

Pout

Nout

signal

Hysteresis input Standby control signal

CTL

Pch

Nch

Pout

Nout

• CMOS hysteresis input (With input interception function at standby) With open drain control signal

• CMOS output

•CMOS input (With input interception function at standby) Programmable pull-up Resistor approx. 50 kΩ

CMOS input

Standby control signal

• USB I/O pin

D + input

D-input Differential input

−

Full D + output

Full D-output

Low D + output

Low D-output

Direction Speed

• CMOS output

Pch

Pout

•CMOS input (With input interception function at

Nch

Nout

standby)

CMOS input

Standby control signal

MB90335 Series

HANDLING DEVICES

■■■■

1. Preventing latchup and turning on power supply

Latchup may occur on CMOS IC under the following conditions:

1. If a voltage higher than VCC or lower than VSS is applied to input and output pins.

2. A voltage higher than the rated voltage is applied between V When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using CMOSICs, take great care to prevent the occurrence of latchup.

CC and VSS.

2. Treatment of unused pins

Leaving unused input pins open ma y cause a malfunction. These pins must theref ore be set to a pull-up or pulldown state.

3. About the attention when the external clock is used

• Using external clock

X1OPEN

4. Treatment of power supply pins (VCC/VSS)

When the device is provided with multiple VCC and VSS pins, be sure to connect all of the po wer pins to the power supply and ground outside the device to reduce latch-up and unwanted r adiation, pre vent the strobe signal from malfunctioning due to a rise of grand level, and to follow the standards of total output current for device design reasons. The power supply source should be connected to the V impedance. It is also advisable to connect a bypass capacitor of appro ximately 0.1 µF between V this device.

CC and VSS of this device at the lowest possib le

CC and VSS near

5. About crystal oscillator circuit

Noise near the X0/X1 pin may cause the device to malfunction. When designing the ar twork for a PC board using the microcontroller, it is strongly advisable to place the X0/X1 and cr ystal (ceramic) oscillator, and the bypass capacitor leading to the ground as close to one another as possible and prevent their writing patterns from crossing other patterns as possible be cause stable operation can be expected with such a layout.

6. Caution on Operations during PLL Clock Mode

Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the microcontroller may continue to operate at the free-running frequency of the PLL internal automatic oscillator circuit.Performance of this operation, however, cannot be guaranteed.

MB90335 Series

7. Stabilization of supply voltage

A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage operating range. F or stabilization ref erence, the supply v oltage should be controlled so that V (peak-to-peak values) at commercial frequencies (50 MHz to 60 MHz) fall belo w 10% of the standard V voltage and the transient regulation does not exceed

0.1 V/ms at temporary changes such as power supply switching.

8. Writing to flash memory

For serial writing to flash memory , alwa ys mak e sure that the operating v oltage VCC is between 3.13 V and 3.6 V.

CC ripple variations

CC supply

For normal writing to flash memory , alwa ys make sure that the operating v oltage V

CC is between 3.0 V and 3.6 V.

MB90335 Series

BLOCK DIAGRAM

■■■■

X0, X1

RST

MD0 to MD2

SIN0, SIN1 SOT0, SOT1 SCK0, SCK1

SCL0

SDA0

TOT0

TIN0

DVP

DVM

HVP

HVM

HCONX

VBUS

INT0 to INT7

Clock control

circuit

Interrupt

controller

RAM

ROM

UART/SIO

ch0, ch1

I2C

16-bit reload

timer

USB

(Function)

(Mini-HOST)

External interrupt

F2MC-16LX

CPU

Internal data bus

8/16-bit PPG

timer

ch0 to ch3*

16-bit PWC

SIO

µDMAC

PPG0 to PPG3

PWC

SIN SOT SCK

I/O port (port 0, 1, 2, 4, 5, 6)

P00 P07

P10 P17

P20 P27

P40 P47

P50 P54

P60 P67

* : Channel for use in 8-bit mode. Two channels (ch1, ch3) are used in 16-bit mode. Note : I/O ports share pins with peripheral resources.

For details, see “■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”. Note also that pins used for peripheral resources cannot serve as I/O ports.

MEMORY MAP

■■■■

Single chip mode (ROM mirror function)

MB90V330A MB90F337 MB90337

FFFFFFH

FF0000H

ROM (FF bank)

FFFFFFH

FF0000H

ROM (FF bank)

MB90335 Series

FFFFFFH

FF0000H

ROM (FF bank)

00FFFFH

008000H

007FFFH

007900H

007100H

000100H

0000FBH

000000H

ROM area

(image of FF bank)

Peripheral area

RAM area

(28 Kbytes)

Peripheral area

00FFFFH

008000H

007FFFH

007900H

001100H

000100H

0000FBH

000000H

ROM area

(image of FF bank)

Peripheral area

RAM area

(4 Kbytes)

Peripheral area

00FFFFH

008000H

007FFFH

007900H

001100H

000100H

0000FBH

000000H

ROM area

(image of FF bank)

Peripheral area

RAM area

(4 Kbytes)

Peripheral area

Memory Map of MB90335 Series

Notes : • When the ROM mirror function register has been set, the mirror image data at higher addresses (“FF8000

to FFFFFF

H” ) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of bank 00.

• For setting the ROM mirror function, see “16. ROM mirror function select module” in “■ PERIPHERAL

RESOURCES”.

Reference : • The ROM mirror function is for using the C compiler small model.

• The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be reproduced in bank 00.

• When the C compiler small model is used, the data tab le mirror image can be shown at “008000 00FFFF

H” by storing the data table at “FF8000H to FFFFFFH”.

H to

Therefore, data tab les in the ROM area can be ref erenced without declaring the f ar addressing with the pointer.

MB90335 Series

MC-16L CPU PROGRAMMING MODEL

■■■■

• Dedicated register

AH AL

• General purpose registers

32 bit

USP SSP

16 bit

DPR

PCB DTB USB SSB

ADB

8 bit

Accumulator User stack pointer

System stack pointer Processor status Program counter

Direct page register

Program bank register Data bank register

User stack bank register System stack bank register Additional data bank register

• Processor status

PS RP CCR

000180

H + RP × 10H

15 13

ILM

MSB LSB

12 8 70

16 bit

RW0 RW1 RW2

RW3 R1 R0 R3 R2

R7 R6

RL0

RL1

RW4

RL2

RW5 RW6

RL3

RW7

I/O MAP

■■■■

MB90335 Series

Address

000000

abbreviation

H PDR0 Port 0 Data Register R/W Port 0 XXXXXXXXB

Read/

Write

Resource name Initial Value

000001H PDR1 Port 1 Data Register R/W Port 1 XXXXXXXXB 000002H PDR2 Port 2 Data Register R/W Port 2 XXXXXXXXB 000003H Prohibited 000004H PDR4 Port 4 Data Register R/W Port 4 XXXXXXXXB 000005H PDR5 Port 5 Data Register R/W Port 5 - - - XXXXXB 000006H PDR6 Port 6 Data Register R/W Port 6 XXXXXXXXB 000007H

00000F

000010

H DDR0 Port 0 Direction Register R/W Port 0 0 0 0 0 0 0 0 0B

Prohibited

000011H DDR1 Port 1 Direction Register R/W Port 1 0 0 0 0 0 0 0 0B 000012H DDR2 Port 2 Direction Register R/W Port 2 0 0 0 0 0 0 0 0B 000013H Prohibited 000014H DDR4 Port 4 Direction Register R/W Port 4 0 0 0 0 0 0 0 0B 000015H DDR5 Port 5 Direction Register R/W Port 5 - - - 0 0 0 0 0B 000016H DDR6 Port 6 Direction Register R/W Port 6 0 0 0 0 0 0 0 0B 000017H

00001A 00001B

H ODR4 Port 4 Output Pin Register R/W

Prohibited

Port 4

(OD control)

0 0 0 0 0 0 0 0B

00001CH RDR0 Port 0 Pull-up Resistance Register R/W Port 0 (PULL-UP) 0 0 0 0 0 0 0 0B 00001DH RDR1 Port 0 Pull-up Resistance Register R/W Port 1 (PULL-UP) 0 0 0 0 0 0 0 0B 00001EH

Prohibited

00001F

000020H SMR0 Serial Mode Register ch0 R/W

0 0 1 0 0 0 0 0B

000021H SCR0 Serial Control Register ch0 R/W 0 0 0 0 0 1 0 0B 000022H 000023

SODR0 Serial Output Data Register ch0 W

H SSR0 Serial Status Register ch0 R/W 0 0 0 0 1 0 0 0B

000024H UTRLR0 UART Prescaler Reload Register ch0 R/W 000025H UTCR0 UART Prescaler Control Register ch0 R/W 0 0 0 0 - 0 0 0B 000026H SMR1 Serial Mode Register ch1 R/W

SIDR0 Serial Input Data Register ch0 R

UART0

Communication

Prescaler (UART0)

XXXXXXXX

0 0 0 0 0 0 0 0B

0 0 1 0 0 0 0 0B

000027H SCR1 Serial Control Register ch1 R/W 0 0 0 0 0 1 0 0B 000028H

SIDR1 Serial Input Data Register ch1 R

UART1

XXXXXXXX

SODR1 Serial Output Data Register ch1 W

000029H SSR1 Serial Status Register ch1 R/W 0 0 0 0 1 0 0 0B

(Continued)

MB90335 Series

Address

00002A

abbreviation

H UTRLR1 UART Prescaler Reload Register ch1 R/W

00002BH UTCR1 UART Prescaler Control Register ch1 R/W 0 0 0 0 - 0 0 0B

Read/

Write

Resource name Initial Value

Communication

0 0 0 0 0 0 0 0B

Prescaler (UART1)

00002CH

00003B

00003C

H ENIR Interrupt/DTP Enable Register R/W

00003DH EIRR Interrupt/DTP source Register R/W 0 0 0 0 0 0 0 0B

00003EH 00003FH Request Level Setting Register Higher R/W 0 0 0 0 0 0 0 0B

ELVR

Request Level Setting Register Lower R/W 0 0 0 0 0 0 0 0

Prohibited

0 0 0 0 0 0 0 0B

DTP/External

interrupt

000040H

000045 000046

H PPGC0 PPG0 Operation Mode Control Register R/W PPG ch0 0X0 0 0XX1B

Prohibited

000047H PPGC1 PPG1 Operation Mode Control Register R/W PPG ch1 0X0 0 0 0 0 1B 000048H PPGC2 PPG2 Operation Mode Control Register R/W PPG ch2 0X0 0 0XX1B 000049H PPGC3 PPG3 Operation Mode Control Register R/W PPG ch3 0X0 0 0 0 0 1B 00004AH 00004B

Prohibited

00004CH PPG01 PPG0 and PPG1 Output Control Register R/W PPG ch0/1 0 0 0 0 0 0XXB 00004DH Prohibited

00004E

H PPG23 PPG2 and PPG3 Output Control Register R/W PPG ch2/3 0 0 0 0 0 0 XXB

00004FH

000057 000058 000059H 0 0 0 0 0 0 1 0B

SMCS Serial Mode Control Status Register R/W

Prohibited

XXXX0 0 0 0

Extended Serial

I/O

00005AH SDR Serial Data Register R/W XXXXXXXXB 00005BH SDCR

00005CH 00005DH 0 0 0 0 0 0 0 XB

00005EH 00005FH 0 0 0 0 0 0 0 0B

PWCSR PWC Control Status Register R/W

PWCR PWC Data Buffer Register R/W

Communication Prescaler Control Register

R/W

Communication

Prescaler

16-bit

PWC Timer

0XXX0 0 0 0B

0 0 0 0 0 0 0 0

000060H DIVR PWC Dividing Ratio Register R/W - - - - - - 0 0B 000061H Prohibited 000062 000063H XXXX 0 0 0 0B

000064H

000065H

TMCSR0 Timer control status Register R/W

TMR0 16-bit Timer Register Lower R XXXXXXXXB

TMRLR0 16-bit Reload Register Lower W XXXXXXXXB

16-bit Reload

Timer

TMR0 16-bit Timer Register Higher R XXXXXXXXB

TMRLR0 16-bit Reload Register Higher W XXXXXXXXB

0 0 0 0 0 0 0 0

(Continued)

MB90335 Series

Address

000066

00006E

00006F

abbreviation

H ROMM

ROM Mirroring Function Selection Register

Prohibited

000070H IBSR0 I2C Bus Status Register R

Read/ Write

Resource name Initial Value

ROM Mirror

Function

- - - - - - 1 1B

Selection Module

0 0 0 0 0 0 0 0

000071H IBCR0 I2C Bus Control Register R/W 0 0 0 0 0 0 0 0B

000072H ICCR0 I2C Bus Clock Selection Register R/W XX 0 XXXXXB

C Bus Interface 000073H IADR0 I2C Bus Address Register R/W XXXXXXXXB 000074H IDAR0 I2C Bus Data Register R/W XXXXXXXXB 000075H

00009A 00009B

H DCSR

DMA Descriptor Channel Specification Register

00009CH DSRL DMA Status Register Lower R/W 0 0 0 0 0 0 0 0B

Prohibited

R/W

0 0 0 0 0 0 0 0B

µDMAC 00009DH DSRH DMA Status Register Higher R/W 0 0 0 0 0 0 0 0B 00009EH PACSR

00009FH DIRR

Program Address Detection Control Status Register

Delayed Interrupt Source generate/ release Register

R/W

R/W Delayed Interrupt - - - - - - - 0B

Address Match

Detection

0 0 0 0 0 0 0 0B

Low Power

0000A0H LPMCR Low Power Consumption Mode Register R/W

Consumption

0 0 0 1 1 0 0 0B

control circuit 0000A1H CKSCR Clock Selection Register R/W Clock 1 1 1 1 1 1 0 0B 0000A2H 0000A3

Prohibited

0000A4H DSSR DMA Stop Status Register R/W µDMAC 0 0 0 0 0 0 0 0B 0000A5H

0000A7 0000A8

H WDTC Watchdog Control Register R/W Watchdog Timer X - XXX 1 1 1B

Prohibited

0000A9H TBTC Time-base Timer Control Register R/W Time-base Timer 1 - - 0 0 1 0 0B 0000AAH 0000AB

0000ACH DERL DMA Enable Register Lower R/W 0000ADH DERH DMA Enable Register Higher R/W 0 0 0 0 0 0 0 0B

0000AEH FMCR Flash Memory Control Status Register R/W

Prohibited

µDMAC

FLASH

MEMORY I/F

0 0 0 0 0 0 0 0B

0 0 0 X 0 0 0 0B

0000AFH Prohibited

(Continued)

MB90335 Series

Address

0000B0

abbreviation

H ICR00 Interrupt Control Register 00 R/W

Read/

Write

Resource name Initial Value

0 0 0 0 0 1 1 1B 0000B1H ICR01 Interrupt Control Register 01 R/W 0 0 0 0 0 1 1 1B 0000B2H ICR02 Interrupt Control Register 02 R/W 0 0 0 0 0 1 1 1B 0000B3H ICR03 Interrupt Control Register 03 R/W 0 0 0 0 0 1 1 1B 0000B4H ICR04 Interrupt Control Register 04 R/W 0 0 0 0 0 1 1 1B 0000B5H ICR05 Interrupt Control Register 05 R/W 0 0 0 0 0 1 1 1B 0000B6H ICR06 Interrupt Control Register 06 R/W 0 0 0 0 0 1 1 1B 0000B7H ICR07 Interrupt Control Register 07 R/W 0 0 0 0 0 1 1 1B 0000B8H ICR08 Interrupt Control Register 08 R/W 0 0 0 0 0 1 1 1B

Interrupt

Controller

0000B9H ICR09 Interrupt Control Register 09 R/W 0 0 0 0 0 1 1 1B

0000BAH ICR10 Interrupt Control Register 10 R/W 0 0 0 0 0 1 1 1B 0000BBH ICR11 Interrupt Control Register 11 R/W 0 0 0 0 0 1 1 1B 0000BCH ICR12 I nterrupt Control Register 12 R/W 0 0 0 0 0 1 1 1B 0000BDH ICR13 I nterrupt Control Register 13 R/W 0 0 0 0 0 1 1 1B 0000BEH ICR14 Interrupt Control Register 14 R/W 0 0 0 0 0 1 1 1B

0000BFH ICR15 Interrupt Control Register 15 R/W 0 0 0 0 0 1 1 1B 0000C0H HCNT0 USB Host Control Register 0 R/W

0 0 0 0 0 0 0 0B 0000C1H HCNT1 USB Host Control Register 1 R/W 0 0 0 0 0 0 0 1B 0000C2H HIRQ USB Host Interruption Register R/W 0 0 0 0 0 0 0 0B 0000C3H HERR USB Host Error Status Register R/W 0 0 0 0 0 0 1 1B 0000C4H HSTATE USB Host State Status Register R/W XX 0 1 0 0 1 0B

0000C5H HFCOMP 0000C6H

0000C7H USB Retry Timer Setting Register 1 R/W 0 0 0 0 0 0 0 0B

HRTIMER

USB SOF Interrupt FRAME compare Register

R/W 0 0 0 0 0 0 0 0B

USB Retry Timer Setting Register 0 R/W 0 0 0 0 0 0 0 0

USB Mini HOST

0000C8H USB Retry Timer Setting Register 2 R/W XXXXXX 0 0B 0000C9H HADR USB Host Address Register R/W X 0 0 0 0 0 0 0B

0000CAH

HEOF

USB EOF Setting Register 0 R/W 0 0 0 0 0 0 0 0 0000CBH USB EOF Setting Register 1 R/W XX 0 0 0 0 0 0B 0000CCH

USB FRAME Setting Register 0 R/W 0 0 0 0 0 0 0 0

HFRAME

0000CDH USB FRAME Setting Register 1 R/W XXXXX 0 0 0B 0000CEH HTOKEN USB Host Token End Point Register R/W 0 0 0 0 0 0 0 0B 0000CFH Prohibited

0000D0

H UDCC UDC Control Register R/W USB function 1 0 1 0 0 0 0 0B

0000D1H Prohibited

(Continued)

MB90335 Series

Address

0000D2 0000D3H R/W XXXX 0 0 0 XB 0000D4H 0000D5H R/W 0 1 1 0 0 0 0 1B 0000D6H 0000D7H R/W 0 1 1 0 0 0 0 0B 0000D8H

0000D9H R/W 0 1 1 0 0 0 0 0B 0000DAH 0000DBH R/W 0 1 1 0 0 0 0 0B 0000DCH 0000DDH R/W 0 1 1 0 0 0 0 0B 0000DEH 0000DFH R/W 0 0 0 0 0 0 0 0B

abbreviation

EP0C EP0 Control Register

EP1C EP1 Control Register

EP2C EP2 Control Register

EP3C EP3 Control Register

EP4C EP4 Control Register

EP5C EP5 Control Register

TMSP Time Stamp Register

Read/

Write

R/W

Resource name Initial Value

X 1 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 1 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0

0000E0H UDCS UDC Status Register R/W 0 0 0 0 0 0 0 0B

0000E1H UDCIE Interrupt Enable Register R/W 0 0 0 0 0 0 0 0B

0000E2H

0000E3H R/W 1 0 XXX 1 XXB

0000E4H

0000E5H R/W 1 0 0 XX 0 0 XB

0000E6H

0000E7H R/W 1 0 0 0 0 0 0 XB

0000E8H

0000E9H R/W 1 0 0 0 0 0 0 XB 0000EAH 0000EBH R/W 1 0 0 0 0 0 0 XB 0000ECH 0000EDH R/W 1 0 0 0 0 0 0 XB 0000EEH

0000EFH R/W 1 0 0 0 0 0 0 XB

0000F0H

0000F1H R/W XXXXXXXXB

0000F2H

0000F3H R/W XXXXXXXXB

0000F4H

0000F5H R/W XXXXXXXXB

0000F6H

0000F7H R/W XXXXXXXXB

0000F8H

0000F9H R/W XXXXXXXXB

EP0IS EP0I Status Register

EP0OS EP0O Status Register

EP1S EP1 Status Register

EP2S EP2 Status Register

EP3S EP3 Status Register

EP4S EP4 Status Register

EP5S EP5 Status Register

EP0DT EP0 Data Register

EP1DT EP1 Data Register

EP2DT EP2 Data Register

EP3DT EP3 Data Register

EP4DT EP4 Data Register

R/W XXXXXXXX

R XXXXXXXX

USB Function

R XXXXXXXX

R/W XXXXXXXX

(Continued)

MB90335 Series

Address

0000FA

abbreviation

EP5DT EP5 Data Register

Read/

Write

R/W

Resource name Initial Value

XXXXXXXX

USB Function

0000FBH R/W XXXXXXXXB 0000FCH

0000FF

000100

001100

001FF0

001FF1H

001FF2H

001FF3H

001FF4H

001FF5H

PADR0

Program Address Detection Register ch0 Lower

Program Address Detection Register ch0 Middle

Program Address Detection Register ch0 Higher

Program Address Detection Register ch1 Lower

PADR1

Program Address Detection Register ch1 Middle

Program Address Detection Register ch1 Higher

007900H PRLL0 PPG Reload Register Lower ch0 R/W

Prohibited

RAM Area

R/W

XXXXXXXX

R/W XXXXXXXXB

Address Match

Detection

R/W XXXXXXXX

R/W XXXXXXXXB

XXXXXXXXB

PPG ch0

007901H PRLH0 PPG Reload Register Higher ch0 R/W XXXXXXXXB 007902H PRLL1 PPG Reload Register Lower ch1 R/W 007903H PRLH1 PPG Reload Register Higher ch1 R/W XXXXXXXXB 007904H PRLL2 PPG Reload Register Lower ch2 R/W

PPG ch1

PPG ch2

XXXXXXXXB

XXXXXXXXB 007905H PRLH2 PPG Reload Register Higher ch2 R/W XXXXXXXXB 007906H PRLL3 PPG Reload Register Lower ch3 R/W

XXXXXXXXB

PPG ch3

007907H PRLH3 PPG Reload Register Higher ch3 R/W XXXXXXXXB 007908H

00790B 00790C

H FWR0 Flash Program Control Register 0 R/W Flash 0 0 0 0 0 0 0 0B

Prohibited

00790DH FWR1 Flash Program Control Register 1 R/W Flash 0 0 0 0 0 0 0 0B 00790EH SSR0 Sector Conversion Setting Register R/W Flash 0 0 XXXXX0B 00790FH

00791F

Prohibited

(Continued)

MB90335 Series

(Continued)

Address

007920

abbreviation

H DBAPL DMA Buffer Address Pointer Lower 8-bit R/W

007921H DBAPM DMA Buffer Address Pointer Middle 8-bit R/W XXXXXXXXB 007922H DBAPH DMA Buffer Address Pointer Higher 8-bit R/W XXXXXXXXB 007923H DMACS DMA Control Register R/W XXXXXXXXB

007924H DIOAL

007925H DIOAH

DMA I/O Register Address Pointer Lower 8-bit

DMA I/O Register Address Pointer

Higher 8-bit 007926H DDCTL DMA Data Counter Lower 8-bit R/W XXXXXXXXB 007927H DDCTH DMA Data Counter Higher 8-bit R/W XXXXXXXXB 007928H

007FFF

Prohibited

Read/

Write

Resource name Initial Value

XXXXXXXXB

R/W XXXXXXXXB

µDMAC

R/W XXXXXXXXB

• Explanation on read/write R/W Read and write enabled

R Read only

W Write only

• Explanation of initial values

0 : Initial Value is “0”. 1 : Initial Value is “1”. X : Initial Value is undefined.

- : Initial Value is undefined (None).

Note : No IO instruction can be used for registers located between 007900

H to 007FFFH.

MB90335 Series

■

INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

Interrupt source

support

µµµµ

DMAC

Interrupt vector

Number*

Reset × × #08 08 INT 9 instruction × × #09 09 Exceptional treatment × × #10 0A USB Function1 × 0, 1 #11 0B

Address ICR Address

H FFFFDCH High H FFFFD8H 

H FFFFD4H  H FFFFD0H

Interrupt control

Priori-

ICR00 0000B0H

USB Function2 × 2 to 6 #12 0CH FFFFCCH USB Function3 × × #13 0DH FFFFC8H

ICR01 0000B1H

USB Function4 × × #14 0EH FFFFC4H USB Mini-HOST1 × × #15 0FH FFFFC0H

ICR02 0000B2H

USB Mini-HOST2 × × #16 10H FFFFBCH I2C ch0 × × #17 11H FFFFB8H

ICR03 0000B3H

DTP/External interrupt ch0/1 × #18 12H FFFFB4H No #19 13H FFFFB0H

ICR04 0000B4H

DTP/External interrupt ch2/3 × #20 14H FFFFACH No #21 15H FFFFA8H

ICR05 0000B5H

DTP/External interrupt ch4/5 × #22 16H FFFFA4H PWC/Reload timer ch0 14 #23 17H FFFFA0H

ICR06 0000B6H

DTP/External interrupt ch6/7 × #24 18H FFFF9CH No #25 19H FFFF98H

ICR07 0000B7H

No #26 1AH FFFF94H No #27 1BH FFFF90H

ICR08 0000B8H

No #28 1CH FFFF8CH No #29 1DH FFFF88H

ICR09 0000B9H

PPG ch0/1 × × #30 1EH FFFF84H No #31 1FH FFFF80H

ICR10 0000BAH

PPG ch2/3 × × #32 20H FFFF7CH No #33 21H FFFF78H

ICR11 0000BBH

No #34 22H FFFF74H No #35 23H FFFF70H

ICR12 0000BCH

No #36 24H FFFF6CH UART (Send completed) ch0/ch1 13 #37 25H FFFF68H

ICR13 0000BDH

Extended serial I/O × 9 #38 26H FFFF64H UART(Reception completed) ch0/ch1 12 #39 27H FFFF60H

ICR14 0000BEH

Time-base timer × × #40 28H FFFF5CH Flash memory status × × #41 29H FFFF58H

ICR15 0000BFH

Delayed interrupt output module × × #42 2AH FFFF54H Low

MB90335 Series

: Available. EI

There is a stop demand.) : Available (The interrupt request flag is cleared by the interrupt clear signal). : Available when any interrupt source sharing ICR is not used.

× : Unavailable

• If the same interrupt control register (ICR) has two interrupt factors and the use of the EI

OS is activated when either of the factors is detected. As any interr upt other than the activation factor is masked while the EI when using the EI

• The interrupt flag is cleared by the EI in the same interrupt control register (ICR).

Note : If a resource has two interrupt sources for the same interrupt number , both of the interrupt request flags are

cleared by the µDMAC interrupt clear signal. Theref ore, when y ou use either of two interrupt f actors f or the DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to " 0 " in the appropriate resource, and take measures by software polling.

USB INTERRUPT FACTOR CONTENTS

■■■■

OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal.

OS is permitted, the

OS is running, it is recommended that you should mask either of the interrupt requests

OS.

OS interrupt clear signal for the resource that has two interrupt factors

USB interrupt factor Details

USB function 1 End Point0-IN, EndPoint 0-OUT USB function 2 End Point 1-5 USB function 3 VOFF, VON, SUSP, SOF, BRST, WKOP, COHF

USB function 4 SPIT USB Mini-HOST1 DIRQ, CHHIRQ, URIRQ, RWKIRQ USB Mini-HOST2 SOFIRQ, CMPIRQ

MB90335 Series

PERIPHERAL RESOURCES

■■■■

1. I/O port

• The I/O ports are used as general-purpose input/output por ts (parallel I/O por ts). MB90335 series model is provided with 6 ports (45 inputs) . The ports function as input/output pins for peripheral functions also.

• An I/O port, using port data register (PDR) , outputs the output data to I/O pin and input a signal input to I/O port. The port direction register (DDR) specifies direction of input/output of I/O pins on a bit-by-bit basis.

• The following table lists the I/O ports and the peripheral functions with which they share pins.

Port pin name Pin Name (Peripheral) Peripheral Function that Shares Pin

Port 0 P00 to P07  Port 1 P10 to P17 

Port 2

Port 4

Port 5 P50 to P54 

Port 6

P20 to P23  P24 to P27 PPG0 to PPG3 8/16 bit PPG timer 0, 1

P40, P41 TIN0, TOT0 16-bit reload timer

P42 to P47

P60, P61 INT0, INT1 External interrupt

P62 to P64

P65 INT5, PWC External interrupt, PWC

P66, P67 INT6, INT7, SCL0, SDA0 External interrupt, I

SIN0, SOT0, SCK0,

SIN1, SOT1, SCK1

INT2 to INT4,

SIN, SOT, SCK

UART0, 1

External interrupt, serial IO

• Register list (port data register)

MB90335 Series

PDR0 Initial Value Access

Address : 000000

PDR1

Address : 000001

PDR2

Address : 000002

PDR4

Address : 000004

PDR5

Address : 000005

PDR6

Address : 000006

76543210

H XXXXXXXXB R/W*

15 14 13 12 11 10 9 8

H XXXXXXXXB R/W*

76543210

H XXXXXXXXB R/W*

76543210

H XXXXXXXXB R/W*

15 14 13 12 11 10 9 8

H - - - XXXXXB R/W*

76543210

H XXXXXXXXB R/W*

P67

P06P07 P05 P04 P03 P02 P01 P00

P16P17 P15 P14 P13 P12 P11 P10

P26P27 P25 P24 P23 P22 P21 P20

P46P47 P45 P44 P43 P42 P41 P40

P54 P53 P52 P51 P50

P66 P65 P64 P63 P62 P61 P60

* : R/W access to I/O ports is a bit different in behavior from R/W access to memory as follows:

• Input mode Read : The level at the relevant pin is read.

Write : Data is written to the output latch.

• Output mode

Read : The data register latch value is read. Write : Data is output to the relevant pin.

MB90335 Series

• Register list (port direction register) DDR0 Initial Value Access

Address : 000010

DDR1

Address : 000011

DDR2

Address : 000012

DDR4

Address : 000014

DDR5

Address : 000015

DDR6

Address : 000016

76543210

H 00000000B R/W

15 14 13 12 11 10 9 8

H 00000000B R/W

15 14 13 12 11 10 9 8

H - - - 00000B R/W

76543210

H 00000000B R/W

D06D07 D05 D04 D03 D02 D01 D 00

D16D17 D15 D14 D13 D12 D11 D10

76543210

D26D27 D25 D24 D23 D22 D21 D20

76543210

D46D47 D45 D44 D43 D42 D41 D40

D54 D53 D52 D51 D50

D66D67 D65 D64 D63 D62 D61 D60

• When each pin is serving as a port, the corresponding pin is controlled as follows: 0 : Input mode 1 : Output mode

This bit becomes 0 after a reset.

Note : If these registers are accessed by a read modify write instruction (such as a bit set instruction) , the bits

manipulated by the instruction are set to prescribed values but those other bits in output registers which have been set f or input are re written to the current input values of the pins . When s witching a pin from input port to output port, therefore, write a desired value in the PDR first, then set the DDR to switch the pin for output.

• Register list (Port pull-up register) RDR0 Initial Value Access

Address : 00001C

RDR1

Address : 00001D

76543210

H 00000000B R/W

RD06RD07 RD05 RD04 RD03 RD02 RD01 RD00

15 14 13 12 11 10 9 8

RD16RD17 RD15 RD14 RD13 RD12 RD11 RD10

Controls the pull-up resistor in input mode.

0 : Without pull-up resistor in input mode. 1 : With Pull-up resistor in input mode.

Meaningless in output mode (without pull-up resistor) ./ The input/output register is decided by the setting of the direction register (DDR) .

No pull-up resistor is used in stop mode (SPL = 1).

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