FUJITSU MB90335 DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

MB90335 Series

MB90337/F337/V330A

DESCRIPTION

■

The MB90335 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but also MiniHost operation. It is equipped with functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of mobile devices that support USB communications. While inheriting the AT architecture of the F addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, long word processing is now available by introducing a 32-bit accumulator.

* : F

MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.

MC* family, the instruction set supports the C language and extended

FEATURES

■

••••

Clock

• Built-in oscillation circuit and PLL clock frequency multiplication circuit

• Oscillation clock The machine clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz) Clock for USB is 48 MHz Machine clock frequency of 6 MHz, 12 MHz or 24 MHz selectable

• Minimum execution time of instruction : 41.6 ns (6 MHz oscillation clock, 4-time multiplied : machine clock 24 MHz and at operating V

••••

The maximum memory space:16 MB

••••

24-bit addressing

••••

Bank addressing

PACKAGE

■

CC = 3.3 V)

(Continued)

64-pin plastic LQFP

(FPT-64P-M09)

MB90335 Series

(Continued)

••••

Instruction system

Data types: Bit, Byte, Word, Long word Addressing mode (23 types) Enhanced high-precision computing with 32-bit accumulator Enhance Multiply/Divide instructions with sign and the RETI instruction

••••

Instruction system compatible with high-level language (C language) and multitask

• Employing system stack pointer

• Instruction set symmetry and barrel shift instructions

••••

Program Patch Function (2 address pointer)

••••

4-byte instruction queue

••••

Interrupt function

• Priority levels are programmable

• 20 interrupts

••••

Data transfer function

• Expanded intelligent I/O service function (EI

• µDMAC : Maximum 16 channels

OS) : Maximum of 16 channels

••••

Low Power Consumption Mode

• Sleep mode (with the CPU operating clock stopped)

• Time - base timer mode (with the oscillator clock and time - base timer operating)

• Stop mode (with the oscillator clock stopped)

• CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles)

••••

Package

• LQFP-64P (FPT-64P-M09 : 0.65 mm pin pitch)

••••

Process : CMOS technology

••••

Operation guaranteed temperature:

−−−−

°°°°

C to

++++

°°°°

C (0

°°°°

C to

++++

°°°°

C when USB is in use)

MB90335 Series

INTERNAL PERIPHERAL FUNCTION (RESOURCE)

■■■■

••••

I/O port: Max 45 ports

••••

Time-base timer : 1channel

••••

Watchdog timer : 1 channel

••••

16-bit reload timer : 1 channel

••••

Multi-functional timer

• 8/16-bit PPG timer (8-bit × 4 channels or 16-bit × 2 channels) the period and duty of the output pulse can be set by the program.

• 16-bit PWC timer : 1 channel Timer function and pulse width measurement function

••••

UART : 2 channels

• Equipped with Full duplex double buffer with 8-bit lenghth

• Asynchronous transfer or clock-synchronous serial (I/O extended serial) transfer can be set.

••••

Extended I/O serial interface: 1 channel

••••

DTP/External interrupt circuit (8 channels)

• Activate the extended intelligent I/O service by external interrupt input

• Interrupt output by external interrupt input

••••

Delayed interrupt output module

• Output an interrupt request for task switching

••••

USB : 1 channel

• USB function (conform to USB 2.0 Full Speed)

• Supports for Full Speed/Endpoint are specifiable up to six.

• Dual port RAM (The FIFO mode is supported).

• Transfer type: Control, Interrupt, Bulk or Isochronous transfer possible

• USB Mini Host function

••••

C Interface : 1 channel

• Supports Intel SM bus standards and Phillips I

C bus standards

• Two-wire data transfer protocol specification

• Master and slave transmission/reception

Note : I

C licenae :

Purchase of Fujitsu I

C components conveys a license under the Philips I2C Patent Rights to use,

these components in an I

C system provided that the system conforms to the I2C Standard Specification as

defined by Phillips.

MB90335 Series

PRODUCT LINEUP

■■■■

1. MB90335 Series

Part number MB90V330A MB90F337 MB90337

Type For evaluation Built-in FLASH MEMORY Built-in Mask ROM ROM capacity No 64 Kbyte RAM capacity 28 Kbyte 4 Kbyte Emulator-specific

power supply *

Number of basic instructions Minimum instruction execu-

CPU functions

Ports I/O Ports(CMOS) 45 ports

UART

16-bit reload timer

Multi-functional timer

DTP/External interrupt

C 1 channel

Extended I/O serial interface 1 channel

USB

Withstand voltage of 5 V 6 ports (Excluding VBUS and I/O for I Low Power Consumption

Mode Process CMOS Operating voltage VCC 3.3 V ± 0.3 V (at maximum machine clock 24 MHz)

tion time Addressing type Program Patch Function maximum memory space

Equipped with full-duplex double buffer Clock synchronous or asynchronous operation selectable. It can also be used for I/O serial. Built-in special baud-rate generator Built-in 2 channels

16-bit reload timer operation Built-in 1 channel

8/16-bit PPG timer (8-bit mode × 4 channels, 16-bit mode × 2 channels) 16-bit PWC timer × 1 channel

8 channels Interrupt factor : “L”→“H” edge /“H”→“L” edge /“L” level /“H” level selectable

1 channel USB function (conform to USB 2.0 Full Speed) USB Mini-HOST function

Sleep mode/Timebase timer mode/Stop mode/CPU intermittent mode

Used bit 

: 351 instructions : 41.6 ns / at oscillation of 6 MHz

(When 4 times is used : Machine clock of 24 MHz) : 23 types : For two address pointers : 16 Mbyte

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB2147-

01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details.

PACKAGES AND PRODUCT MODELS

■

Package MB90337 MB90F337 MB90V330A

FPT-64P-M09 (LQFP-0.65 mm) × PGA-299C-A01 (PGA) × ×

: Yes × : No

Note : For detailed information on each package, see “■ PACKAGE DIMENSIONS”.

PIN ASSIGNMENT



■■■■

(TOP VIEW)

P51

P41/TOT0

P40/TIN0

P67/INT7/SDA0

P66/INT6/SCL0

P65/INT5/PWC

P64/INT4/SCK

P63/INT3/SOT

P62/INT2/SIN

P61/INT1

P60/INT0

P27/PPG3

P26/PPG2

P25/PPG1

P50

646362616059585756555453525150

MB90335 Series

Vcc 49

VBUS

Vss

DVM

DVP

Vcc Vss

HVM

HVP

Vcc

HCONX

P42/SIN0 P43/SOT0 P44/SCK0

P45/SIN1 P46/SOT1 P47/SCK1

10 11 12 13 14 15 16

1 2 3 4 5 6 7 8 9

171819202122232425262728293031

Vss

P52

P53

MD2

MD1

MD0

RST

P54

P00

P01

P02

P03

P04

P05

P06

32 P07

Vss

P24/PPG0

P23

P22

P21

P20

P17

P16

P15

P14

P13

P12

P11

P10

(FPT-64P-M09)

MB90335 Series

PIN DESCRIPTION

■■■■

Pin no.

QFPM09

46 , 47 X0, X1 A

23 RST

25 to 32 P00 to P07 I

33 to 40 P10 to P17 I

41 to 44 P20 to P23 D General purpose input/output port.

51 to 53

16 50 P50 K General purpose input/output port.

64 P51 K General purpose input/output port.

17, 18 P52, P53 K General purpose input/output port.

24 P54 K General purpose input/output port.

Pin name

P24

PPG0 Functions as output pins of PPG timers ch0.

P25 to P27

PPG1 to

PPG3

P40

TIN0 Function as event input pin of 16-bit reload timer.

P41

TOT0 Function as output pin of 16-bit reload timer.

P42

SIN0 Functions as a data input pin for UART ch0.

P43

SOT0 Functions as a data output pin for UART ch0.

P44

SCK0 Functions as a clock I/O pin for UART ch0.

P45

SIN1 Functions as a data input pin for UART ch1.

P46

SOT1 Functions as a data output pin for UART ch1.

P47

SCK1 Functions as a clock I/O pin for UART ch1.

Circuit

type*

Status at

reset/

function

Oscillation

status

F Reset input External reset input pin.

Port input

(High-Z)

It is a terminal which connects the oscillator. When connecting an external clock, leave the X1 pin side unconnected.

General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD00 to RD07 = 1) by the pull-up resistor setting register (RDR0). (When the power output is set, it is invalid.)

General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD10 to RD17 = 1) by the pull-up resistor setting register (RDR1). (When the power output is set, it is invalid.)

General purpose input/output port.

General purpose input/output port. Functions as output pins of PPG timers ch1 to ch3. General purpose input/output port.

General purpose input/output port.

Function

* : For circuit information, see “■ I/O CIRCUIT TYPE”.

(Continued)

MB90335 Series

(Continued)

Pin no.

QFPM09

54, 55

Pin name

P60, P61

INT0, INT1 Functions as the input pin for external interrupt ch0 and ch1.

Circuit

type*

P62

INT2 Functions as the input pin for external interrupt ch2.

SIN Data input pin for simple serial IO.

P63

INT3 Functions as the input pin for external interrupt ch3.

SOT Data output pin for simple serial IO

P64

INT4 Functions as the input pin for external interrupt ch4.

SCK Clock I/O pin for simple serial IO.

P65

INT5 Functions as the input pin for external interrupt ch5.

PWC Functions as the PWC input pin.

P66

INT6 Functions as the input pin for external interrupt ch6.

SCL0

P67

INT7 Functions as the input pin for external interrupt ch7.

SDA0

1 VBUS C VBUS input Status detection pin of USB cable. 3DVMJ 4 DVP J USB function D + pin. 7 HVM J USB Mini Host D − pin. 8 HVP J USB Mini Host D + pin.

10 HCONX E High output External pull-up resistor connection pin.

21, 22 MD1, MD0 B

20 MD2 G

5Vcc 9Vcc Power supply pin.

49 Vcc  Power supply pin.

2Vss Power supply pin (GND).

6Vss Power supply pin (GND). 19 Vss  Power supply pin (GND). 48 Vss  Power supply pin (GND).

Status at

reset/

function

Port input

(High-Z)

USB input

(SUSPEND)

Mode input

Power supply

Function

General purpose input/output port. (withstand voltage of 5 V)

General purpose input/output port.

Functions as the input/output pin for I output must be placed in High-Z state during I operation.

General purpose input/output port.

Functions as the I

C interface data input/output pin. The port out-

put must be placed in High-Z state during I

USB function D − pin.

Input pin for selecting operation mode. Power supply pin.

C interface clock. The port

C interface

C interface operation.

* : For circuit information, see “■ I/O CIRCUIT TYPE”.

MB90335 Series

I/O CIRCUIT TYPE

■■■■

Type Circuit Remarks

Clock input

Standby control signal

Hysteresis input

NoutNch

Hysteresis input

• Oscillation feedback resistance : approx. 1 MΩ

• With standby control

• CMOS hysteresis input

• Hysteresis input

• Nch open drain output

Standby control signal

• CMOS output

• CMOS hysteresis input

Pch

Pout

(With input interception function at standby)

Nch

Nout

Note : • The I/O ports and internal

resources share one output buffer for their outputs.

Hysteresis input

Standby control signal

• The I/O port and internal resources share one input buffer for their input.

• CMOS output

Pch

Pout

Nch

Nout

• CMOS hysteresis input with pull-up

• Resistor approx. 50 kΩ

Hysteresis input

• CMOS hysteresis input with pull-down

• Resistor approx. 50 kΩ

Hysteresis input

• FLASH product is not provided with pull-down resistor.

(Continued)

MB90335 Series

(Continued)

Type Circuit Remarks

• CMOS output

Open drain control

Pch

Nch

Pout

Nout

signal

Hysteresis input Standby control signal

CTL

Pch

Nch

Pout

Nout

• CMOS hysteresis input (With input interception function at standby) With open drain control signal

• CMOS output

•CMOS input (With input interception function at standby) Programmable pull-up Resistor approx. 50 kΩ

CMOS input

Standby control signal

• USB I/O pin

D + input

D-input Differential input

−

Full D + output

Full D-output

Low D + output

Low D-output

Direction Speed

• CMOS output

Pch

Pout

•CMOS input (With input interception function at

Nch

Nout

standby)

CMOS input

Standby control signal

MB90335 Series

HANDLING DEVICES

■■■■

1. Preventing latchup and turning on power supply

Latchup may occur on CMOS IC under the following conditions:

1. If a voltage higher than VCC or lower than VSS is applied to input and output pins.

2. A voltage higher than the rated voltage is applied between V When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using CMOSICs, take great care to prevent the occurrence of latchup.

CC and VSS.

2. Treatment of unused pins

Leaving unused input pins open ma y cause a malfunction. These pins must theref ore be set to a pull-up or pulldown state.

3. About the attention when the external clock is used

• Using external clock

X1OPEN

4. Treatment of power supply pins (VCC/VSS)

When the device is provided with multiple VCC and VSS pins, be sure to connect all of the po wer pins to the power supply and ground outside the device to reduce latch-up and unwanted r adiation, pre vent the strobe signal from malfunctioning due to a rise of grand level, and to follow the standards of total output current for device design reasons. The power supply source should be connected to the V impedance. It is also advisable to connect a bypass capacitor of appro ximately 0.1 µF between V this device.

CC and VSS of this device at the lowest possib le

CC and VSS near

5. About crystal oscillator circuit

Noise near the X0/X1 pin may cause the device to malfunction. When designing the ar twork for a PC board using the microcontroller, it is strongly advisable to place the X0/X1 and cr ystal (ceramic) oscillator, and the bypass capacitor leading to the ground as close to one another as possible and prevent their writing patterns from crossing other patterns as possible be cause stable operation can be expected with such a layout.

6. Caution on Operations during PLL Clock Mode

Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the microcontroller may continue to operate at the free-running frequency of the PLL internal automatic oscillator circuit.Performance of this operation, however, cannot be guaranteed.

MB90335 Series

7. Stabilization of supply voltage

A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage operating range. F or stabilization ref erence, the supply v oltage should be controlled so that V (peak-to-peak values) at commercial frequencies (50 MHz to 60 MHz) fall belo w 10% of the standard V voltage and the transient regulation does not exceed

0.1 V/ms at temporary changes such as power supply switching.

8. Writing to flash memory

For serial writing to flash memory , alwa ys mak e sure that the operating v oltage VCC is between 3.13 V and 3.6 V.

CC ripple variations

CC supply

For normal writing to flash memory , alwa ys make sure that the operating v oltage V

CC is between 3.0 V and 3.6 V.

MB90335 Series

BLOCK DIAGRAM

■■■■

X0, X1

RST

MD0 to MD2

SIN0, SIN1 SOT0, SOT1 SCK0, SCK1

SCL0

SDA0

TOT0

TIN0

DVP

DVM

HVP

HVM

HCONX

VBUS

INT0 to INT7

Clock control

circuit

Interrupt

controller

RAM

ROM

UART/SIO

ch0, ch1

I2C

16-bit reload

timer

USB

(Function)

(Mini-HOST)

External interrupt

F2MC-16LX

CPU

Internal data bus

8/16-bit PPG

timer

ch0 to ch3*

16-bit PWC

SIO

µDMAC

PPG0 to PPG3

PWC

SIN SOT SCK

I/O port (port 0, 1, 2, 4, 5, 6)

P00 P07

P10 P17

P20 P27

P40 P47

P50 P54

P60 P67

* : Channel for use in 8-bit mode. Two channels (ch1, ch3) are used in 16-bit mode. Note : I/O ports share pins with peripheral resources.

For details, see “■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”. Note also that pins used for peripheral resources cannot serve as I/O ports.

MEMORY MAP

■■■■

Single chip mode (ROM mirror function)

MB90V330A MB90F337 MB90337

FFFFFFH

FF0000H

ROM (FF bank)

FFFFFFH

FF0000H

ROM (FF bank)

MB90335 Series

FFFFFFH

FF0000H

ROM (FF bank)

00FFFFH

008000H

007FFFH

007900H

007100H

000100H

0000FBH

000000H

ROM area

(image of FF bank)

Peripheral area

RAM area

(28 Kbytes)

Peripheral area

00FFFFH

008000H

007FFFH

007900H

001100H

000100H

0000FBH

000000H

ROM area

(image of FF bank)

Peripheral area

RAM area

(4 Kbytes)

Peripheral area

00FFFFH

008000H

007FFFH

007900H

001100H

000100H

0000FBH

000000H

ROM area

(image of FF bank)

Peripheral area

RAM area

(4 Kbytes)

Peripheral area

Memory Map of MB90335 Series

Notes : • When the ROM mirror function register has been set, the mirror image data at higher addresses (“FF8000

to FFFFFF

H” ) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of bank 00.

• For setting the ROM mirror function, see “16. ROM mirror function select module” in “■ PERIPHERAL

RESOURCES”.

Reference : • The ROM mirror function is for using the C compiler small model.

• The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be reproduced in bank 00.

• When the C compiler small model is used, the data tab le mirror image can be shown at “008000 00FFFF

H” by storing the data table at “FF8000H to FFFFFFH”.

H to

Therefore, data tab les in the ROM area can be ref erenced without declaring the f ar addressing with the pointer.

MB90335 Series

MC-16L CPU PROGRAMMING MODEL

■■■■

• Dedicated register

AH AL

• General purpose registers

32 bit

USP SSP

16 bit

DPR

PCB DTB USB SSB

ADB

8 bit

Accumulator User stack pointer

System stack pointer Processor status Program counter

Direct page register

Program bank register Data bank register

User stack bank register System stack bank register Additional data bank register

• Processor status

PS RP CCR

000180

H + RP × 10H

15 13

ILM

MSB LSB

12 8 70

16 bit

RW0 RW1 RW2

RW3 R1 R0 R3 R2

R7 R6

RL0

RL1

RW4

RL2

RW5 RW6

RL3

RW7

I/O MAP

■■■■

MB90335 Series

Address

000000

abbreviation

H PDR0 Port 0 Data Register R/W Port 0 XXXXXXXXB

Read/

Write

Resource name Initial Value

000001H PDR1 Port 1 Data Register R/W Port 1 XXXXXXXXB 000002H PDR2 Port 2 Data Register R/W Port 2 XXXXXXXXB 000003H Prohibited 000004H PDR4 Port 4 Data Register R/W Port 4 XXXXXXXXB 000005H PDR5 Port 5 Data Register R/W Port 5 - - - XXXXXB 000006H PDR6 Port 6 Data Register R/W Port 6 XXXXXXXXB 000007H

00000F

000010

H DDR0 Port 0 Direction Register R/W Port 0 0 0 0 0 0 0 0 0B

Prohibited

000011H DDR1 Port 1 Direction Register R/W Port 1 0 0 0 0 0 0 0 0B 000012H DDR2 Port 2 Direction Register R/W Port 2 0 0 0 0 0 0 0 0B 000013H Prohibited 000014H DDR4 Port 4 Direction Register R/W Port 4 0 0 0 0 0 0 0 0B 000015H DDR5 Port 5 Direction Register R/W Port 5 - - - 0 0 0 0 0B 000016H DDR6 Port 6 Direction Register R/W Port 6 0 0 0 0 0 0 0 0B 000017H

00001A 00001B

H ODR4 Port 4 Output Pin Register R/W

Prohibited

Port 4

(OD control)

0 0 0 0 0 0 0 0B

00001CH RDR0 Port 0 Pull-up Resistance Register R/W Port 0 (PULL-UP) 0 0 0 0 0 0 0 0B 00001DH RDR1 Port 0 Pull-up Resistance Register R/W Port 1 (PULL-UP) 0 0 0 0 0 0 0 0B 00001EH

Prohibited

00001F

000020H SMR0 Serial Mode Register ch0 R/W

0 0 1 0 0 0 0 0B

000021H SCR0 Serial Control Register ch0 R/W 0 0 0 0 0 1 0 0B 000022H 000023

SODR0 Serial Output Data Register ch0 W

H SSR0 Serial Status Register ch0 R/W 0 0 0 0 1 0 0 0B

000024H UTRLR0 UART Prescaler Reload Register ch0 R/W 000025H UTCR0 UART Prescaler Control Register ch0 R/W 0 0 0 0 - 0 0 0B 000026H SMR1 Serial Mode Register ch1 R/W

SIDR0 Serial Input Data Register ch0 R

UART0

Communication

Prescaler (UART0)

XXXXXXXX

0 0 0 0 0 0 0 0B

0 0 1 0 0 0 0 0B

000027H SCR1 Serial Control Register ch1 R/W 0 0 0 0 0 1 0 0B 000028H

SIDR1 Serial Input Data Register ch1 R

UART1

XXXXXXXX

SODR1 Serial Output Data Register ch1 W

000029H SSR1 Serial Status Register ch1 R/W 0 0 0 0 1 0 0 0B

(Continued)

MB90335 Series

Address

00002A

abbreviation

H UTRLR1 UART Prescaler Reload Register ch1 R/W

00002BH UTCR1 UART Prescaler Control Register ch1 R/W 0 0 0 0 - 0 0 0B

Read/

Write

Resource name Initial Value

Communication

0 0 0 0 0 0 0 0B

Prescaler (UART1)

00002CH

00003B

00003C

H ENIR Interrupt/DTP Enable Register R/W

00003DH EIRR Interrupt/DTP source Register R/W 0 0 0 0 0 0 0 0B

00003EH 00003FH Request Level Setting Register Higher R/W 0 0 0 0 0 0 0 0B

ELVR

Request Level Setting Register Lower R/W 0 0 0 0 0 0 0 0

Prohibited

0 0 0 0 0 0 0 0B

DTP/External

interrupt

000040H

000045 000046

H PPGC0 PPG0 Operation Mode Control Register R/W PPG ch0 0X0 0 0XX1B

Prohibited

000047H PPGC1 PPG1 Operation Mode Control Register R/W PPG ch1 0X0 0 0 0 0 1B 000048H PPGC2 PPG2 Operation Mode Control Register R/W PPG ch2 0X0 0 0XX1B 000049H PPGC3 PPG3 Operation Mode Control Register R/W PPG ch3 0X0 0 0 0 0 1B 00004AH 00004B

Prohibited

00004CH PPG01 PPG0 and PPG1 Output Control Register R/W PPG ch0/1 0 0 0 0 0 0XXB 00004DH Prohibited

00004E

H PPG23 PPG2 and PPG3 Output Control Register R/W PPG ch2/3 0 0 0 0 0 0 XXB

00004FH

000057 000058 000059H 0 0 0 0 0 0 1 0B

SMCS Serial Mode Control Status Register R/W

Prohibited

XXXX0 0 0 0

Extended Serial

I/O

00005AH SDR Serial Data Register R/W XXXXXXXXB 00005BH SDCR

00005CH 00005DH 0 0 0 0 0 0 0 XB

00005EH 00005FH 0 0 0 0 0 0 0 0B

PWCSR PWC Control Status Register R/W

PWCR PWC Data Buffer Register R/W

Communication Prescaler Control Register

R/W

Communication

Prescaler

16-bit

PWC Timer

0XXX0 0 0 0B

0 0 0 0 0 0 0 0

000060H DIVR PWC Dividing Ratio Register R/W - - - - - - 0 0B 000061H Prohibited 000062 000063H XXXX 0 0 0 0B

000064H

000065H

TMCSR0 Timer control status Register R/W

TMR0 16-bit Timer Register Lower R XXXXXXXXB

TMRLR0 16-bit Reload Register Lower W XXXXXXXXB

16-bit Reload

Timer

TMR0 16-bit Timer Register Higher R XXXXXXXXB

TMRLR0 16-bit Reload Register Higher W XXXXXXXXB

0 0 0 0 0 0 0 0

(Continued)

MB90335 Series

Address

000066

00006E

00006F

abbreviation

H ROMM

ROM Mirroring Function Selection Register

Prohibited

000070H IBSR0 I2C Bus Status Register R

Read/ Write

Resource name Initial Value

ROM Mirror

Function

- - - - - - 1 1B

Selection Module

0 0 0 0 0 0 0 0

000071H IBCR0 I2C Bus Control Register R/W 0 0 0 0 0 0 0 0B

000072H ICCR0 I2C Bus Clock Selection Register R/W XX 0 XXXXXB

C Bus Interface 000073H IADR0 I2C Bus Address Register R/W XXXXXXXXB 000074H IDAR0 I2C Bus Data Register R/W XXXXXXXXB 000075H

00009A 00009B

H DCSR

DMA Descriptor Channel Specification Register

00009CH DSRL DMA Status Register Lower R/W 0 0 0 0 0 0 0 0B

Prohibited

R/W

0 0 0 0 0 0 0 0B

µDMAC 00009DH DSRH DMA Status Register Higher R/W 0 0 0 0 0 0 0 0B 00009EH PACSR

00009FH DIRR

Program Address Detection Control Status Register

Delayed Interrupt Source generate/ release Register

R/W

R/W Delayed Interrupt - - - - - - - 0B

Address Match

Detection

0 0 0 0 0 0 0 0B

Low Power

0000A0H LPMCR Low Power Consumption Mode Register R/W

Consumption

0 0 0 1 1 0 0 0B

control circuit 0000A1H CKSCR Clock Selection Register R/W Clock 1 1 1 1 1 1 0 0B 0000A2H 0000A3

Prohibited

0000A4H DSSR DMA Stop Status Register R/W µDMAC 0 0 0 0 0 0 0 0B 0000A5H

0000A7 0000A8

H WDTC Watchdog Control Register R/W Watchdog Timer X - XXX 1 1 1B

Prohibited

0000A9H TBTC Time-base Timer Control Register R/W Time-base Timer 1 - - 0 0 1 0 0B 0000AAH 0000AB

0000ACH DERL DMA Enable Register Lower R/W 0000ADH DERH DMA Enable Register Higher R/W 0 0 0 0 0 0 0 0B

0000AEH FMCR Flash Memory Control Status Register R/W

Prohibited

µDMAC

FLASH

MEMORY I/F

0 0 0 0 0 0 0 0B

0 0 0 X 0 0 0 0B

0000AFH Prohibited

(Continued)

MB90335 Series

Address

0000B0

abbreviation

H ICR00 Interrupt Control Register 00 R/W

Read/

Write

Resource name Initial Value

0 0 0 0 0 1 1 1B 0000B1H ICR01 Interrupt Control Register 01 R/W 0 0 0 0 0 1 1 1B 0000B2H ICR02 Interrupt Control Register 02 R/W 0 0 0 0 0 1 1 1B 0000B3H ICR03 Interrupt Control Register 03 R/W 0 0 0 0 0 1 1 1B 0000B4H ICR04 Interrupt Control Register 04 R/W 0 0 0 0 0 1 1 1B 0000B5H ICR05 Interrupt Control Register 05 R/W 0 0 0 0 0 1 1 1B 0000B6H ICR06 Interrupt Control Register 06 R/W 0 0 0 0 0 1 1 1B 0000B7H ICR07 Interrupt Control Register 07 R/W 0 0 0 0 0 1 1 1B 0000B8H ICR08 Interrupt Control Register 08 R/W 0 0 0 0 0 1 1 1B

Interrupt

Controller

0000B9H ICR09 Interrupt Control Register 09 R/W 0 0 0 0 0 1 1 1B

0000BAH ICR10 Interrupt Control Register 10 R/W 0 0 0 0 0 1 1 1B 0000BBH ICR11 Interrupt Control Register 11 R/W 0 0 0 0 0 1 1 1B 0000BCH ICR12 I nterrupt Control Register 12 R/W 0 0 0 0 0 1 1 1B 0000BDH ICR13 I nterrupt Control Register 13 R/W 0 0 0 0 0 1 1 1B 0000BEH ICR14 Interrupt Control Register 14 R/W 0 0 0 0 0 1 1 1B

0000BFH ICR15 Interrupt Control Register 15 R/W 0 0 0 0 0 1 1 1B 0000C0H HCNT0 USB Host Control Register 0 R/W

0 0 0 0 0 0 0 0B 0000C1H HCNT1 USB Host Control Register 1 R/W 0 0 0 0 0 0 0 1B 0000C2H HIRQ USB Host Interruption Register R/W 0 0 0 0 0 0 0 0B 0000C3H HERR USB Host Error Status Register R/W 0 0 0 0 0 0 1 1B 0000C4H HSTATE USB Host State Status Register R/W XX 0 1 0 0 1 0B

0000C5H HFCOMP 0000C6H

0000C7H USB Retry Timer Setting Register 1 R/W 0 0 0 0 0 0 0 0B

HRTIMER

USB SOF Interrupt FRAME compare Register

R/W 0 0 0 0 0 0 0 0B

USB Retry Timer Setting Register 0 R/W 0 0 0 0 0 0 0 0

USB Mini HOST

0000C8H USB Retry Timer Setting Register 2 R/W XXXXXX 0 0B 0000C9H HADR USB Host Address Register R/W X 0 0 0 0 0 0 0B

0000CAH

HEOF

USB EOF Setting Register 0 R/W 0 0 0 0 0 0 0 0 0000CBH USB EOF Setting Register 1 R/W XX 0 0 0 0 0 0B 0000CCH

USB FRAME Setting Register 0 R/W 0 0 0 0 0 0 0 0

HFRAME

0000CDH USB FRAME Setting Register 1 R/W XXXXX 0 0 0B 0000CEH HTOKEN USB Host Token End Point Register R/W 0 0 0 0 0 0 0 0B 0000CFH Prohibited

0000D0

H UDCC UDC Control Register R/W USB function 1 0 1 0 0 0 0 0B

0000D1H Prohibited

(Continued)

MB90335 Series

Address

0000D2 0000D3H R/W XXXX 0 0 0 XB 0000D4H 0000D5H R/W 0 1 1 0 0 0 0 1B 0000D6H 0000D7H R/W 0 1 1 0 0 0 0 0B 0000D8H

0000D9H R/W 0 1 1 0 0 0 0 0B 0000DAH 0000DBH R/W 0 1 1 0 0 0 0 0B 0000DCH 0000DDH R/W 0 1 1 0 0 0 0 0B 0000DEH 0000DFH R/W 0 0 0 0 0 0 0 0B

abbreviation

EP0C EP0 Control Register

EP1C EP1 Control Register

EP2C EP2 Control Register

EP3C EP3 Control Register

EP4C EP4 Control Register

EP5C EP5 Control Register

TMSP Time Stamp Register

Read/

Write

R/W

Resource name Initial Value

X 1 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 1 0 0 0 0 0 0

R 0 0 0 0 0 0 0 0

0000E0H UDCS UDC Status Register R/W 0 0 0 0 0 0 0 0B

0000E1H UDCIE Interrupt Enable Register R/W 0 0 0 0 0 0 0 0B

0000E2H

0000E3H R/W 1 0 XXX 1 XXB

0000E4H

0000E5H R/W 1 0 0 XX 0 0 XB

0000E6H

0000E7H R/W 1 0 0 0 0 0 0 XB

0000E8H

0000E9H R/W 1 0 0 0 0 0 0 XB 0000EAH 0000EBH R/W 1 0 0 0 0 0 0 XB 0000ECH 0000EDH R/W 1 0 0 0 0 0 0 XB 0000EEH

0000EFH R/W 1 0 0 0 0 0 0 XB

0000F0H

0000F1H R/W XXXXXXXXB

0000F2H

0000F3H R/W XXXXXXXXB

0000F4H

0000F5H R/W XXXXXXXXB

0000F6H

0000F7H R/W XXXXXXXXB

0000F8H

0000F9H R/W XXXXXXXXB

EP0IS EP0I Status Register

EP0OS EP0O Status Register

EP1S EP1 Status Register

EP2S EP2 Status Register

EP3S EP3 Status Register

EP4S EP4 Status Register

EP5S EP5 Status Register

EP0DT EP0 Data Register

EP1DT EP1 Data Register

EP2DT EP2 Data Register

EP3DT EP3 Data Register

EP4DT EP4 Data Register

R/W XXXXXXXX

R XXXXXXXX

USB Function

R XXXXXXXX

R/W XXXXXXXX

(Continued)

MB90335 Series

Address

0000FA

abbreviation

EP5DT EP5 Data Register

Read/

Write

R/W

Resource name Initial Value

XXXXXXXX

USB Function

0000FBH R/W XXXXXXXXB 0000FCH

0000FF

000100

001100

001FF0

001FF1H

001FF2H

001FF3H

001FF4H

001FF5H

PADR0

Program Address Detection Register ch0 Lower

Program Address Detection Register ch0 Middle

Program Address Detection Register ch0 Higher

Program Address Detection Register ch1 Lower

PADR1

Program Address Detection Register ch1 Middle

Program Address Detection Register ch1 Higher

007900H PRLL0 PPG Reload Register Lower ch0 R/W

Prohibited

RAM Area

R/W

XXXXXXXX

R/W XXXXXXXXB

Address Match

Detection

R/W XXXXXXXX

R/W XXXXXXXXB

XXXXXXXXB

PPG ch0

007901H PRLH0 PPG Reload Register Higher ch0 R/W XXXXXXXXB 007902H PRLL1 PPG Reload Register Lower ch1 R/W 007903H PRLH1 PPG Reload Register Higher ch1 R/W XXXXXXXXB 007904H PRLL2 PPG Reload Register Lower ch2 R/W

PPG ch1

PPG ch2

XXXXXXXXB

XXXXXXXXB 007905H PRLH2 PPG Reload Register Higher ch2 R/W XXXXXXXXB 007906H PRLL3 PPG Reload Register Lower ch3 R/W

XXXXXXXXB

PPG ch3

007907H PRLH3 PPG Reload Register Higher ch3 R/W XXXXXXXXB 007908H

00790B 00790C

H FWR0 Flash Program Control Register 0 R/W Flash 0 0 0 0 0 0 0 0B

Prohibited

00790DH FWR1 Flash Program Control Register 1 R/W Flash 0 0 0 0 0 0 0 0B 00790EH SSR0 Sector Conversion Setting Register R/W Flash 0 0 XXXXX0B 00790FH

00791F

Prohibited

(Continued)

MB90335 Series

(Continued)

Address

007920

abbreviation

H DBAPL DMA Buffer Address Pointer Lower 8-bit R/W

007921H DBAPM DMA Buffer Address Pointer Middle 8-bit R/W XXXXXXXXB 007922H DBAPH DMA Buffer Address Pointer Higher 8-bit R/W XXXXXXXXB 007923H DMACS DMA Control Register R/W XXXXXXXXB

007924H DIOAL

007925H DIOAH

DMA I/O Register Address Pointer Lower 8-bit

DMA I/O Register Address Pointer

Higher 8-bit 007926H DDCTL DMA Data Counter Lower 8-bit R/W XXXXXXXXB 007927H DDCTH DMA Data Counter Higher 8-bit R/W XXXXXXXXB 007928H

007FFF

Prohibited

Read/

Write

Resource name Initial Value

XXXXXXXXB

R/W XXXXXXXXB

µDMAC

R/W XXXXXXXXB

• Explanation on read/write R/W Read and write enabled

R Read only

W Write only

• Explanation of initial values

0 : Initial Value is “0”. 1 : Initial Value is “1”. X : Initial Value is undefined.

- : Initial Value is undefined (None).

Note : No IO instruction can be used for registers located between 007900

H to 007FFFH.

MB90335 Series

■

INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

Interrupt source

support

µµµµ

DMAC

Interrupt vector

Number*

Reset × × #08 08 INT 9 instruction × × #09 09 Exceptional treatment × × #10 0A USB Function1 × 0, 1 #11 0B

Address ICR Address

H FFFFDCH High H FFFFD8H 

H FFFFD4H  H FFFFD0H

Interrupt control

Priori-

ICR00 0000B0H

USB Function2 × 2 to 6 #12 0CH FFFFCCH USB Function3 × × #13 0DH FFFFC8H

ICR01 0000B1H

USB Function4 × × #14 0EH FFFFC4H USB Mini-HOST1 × × #15 0FH FFFFC0H

ICR02 0000B2H

USB Mini-HOST2 × × #16 10H FFFFBCH I2C ch0 × × #17 11H FFFFB8H

ICR03 0000B3H

DTP/External interrupt ch0/1 × #18 12H FFFFB4H No #19 13H FFFFB0H

ICR04 0000B4H

DTP/External interrupt ch2/3 × #20 14H FFFFACH No #21 15H FFFFA8H

ICR05 0000B5H

DTP/External interrupt ch4/5 × #22 16H FFFFA4H PWC/Reload timer ch0 14 #23 17H FFFFA0H

ICR06 0000B6H

DTP/External interrupt ch6/7 × #24 18H FFFF9CH No #25 19H FFFF98H

ICR07 0000B7H

No #26 1AH FFFF94H No #27 1BH FFFF90H

ICR08 0000B8H

No #28 1CH FFFF8CH No #29 1DH FFFF88H

ICR09 0000B9H

PPG ch0/1 × × #30 1EH FFFF84H No #31 1FH FFFF80H

ICR10 0000BAH

PPG ch2/3 × × #32 20H FFFF7CH No #33 21H FFFF78H

ICR11 0000BBH

No #34 22H FFFF74H No #35 23H FFFF70H

ICR12 0000BCH

No #36 24H FFFF6CH UART (Send completed) ch0/ch1 13 #37 25H FFFF68H

ICR13 0000BDH

Extended serial I/O × 9 #38 26H FFFF64H UART(Reception completed) ch0/ch1 12 #39 27H FFFF60H

ICR14 0000BEH

Time-base timer × × #40 28H FFFF5CH Flash memory status × × #41 29H FFFF58H

ICR15 0000BFH

Delayed interrupt output module × × #42 2AH FFFF54H Low

MB90335 Series

: Available. EI

There is a stop demand.) : Available (The interrupt request flag is cleared by the interrupt clear signal). : Available when any interrupt source sharing ICR is not used.

× : Unavailable

• If the same interrupt control register (ICR) has two interrupt factors and the use of the EI

OS is activated when either of the factors is detected. As any interr upt other than the activation factor is masked while the EI when using the EI

• The interrupt flag is cleared by the EI in the same interrupt control register (ICR).

Note : If a resource has two interrupt sources for the same interrupt number , both of the interrupt request flags are

cleared by the µDMAC interrupt clear signal. Theref ore, when y ou use either of two interrupt f actors f or the DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to " 0 " in the appropriate resource, and take measures by software polling.

USB INTERRUPT FACTOR CONTENTS

■■■■

OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal.

OS is permitted, the

OS is running, it is recommended that you should mask either of the interrupt requests

OS.

OS interrupt clear signal for the resource that has two interrupt factors

USB interrupt factor Details

USB function 1 End Point0-IN, EndPoint 0-OUT USB function 2 End Point 1-5 USB function 3 VOFF, VON, SUSP, SOF, BRST, WKOP, COHF

USB function 4 SPIT USB Mini-HOST1 DIRQ, CHHIRQ, URIRQ, RWKIRQ USB Mini-HOST2 SOFIRQ, CMPIRQ

MB90335 Series

PERIPHERAL RESOURCES

■■■■

1. I/O port

• The I/O ports are used as general-purpose input/output por ts (parallel I/O por ts). MB90335 series model is provided with 6 ports (45 inputs) . The ports function as input/output pins for peripheral functions also.

• An I/O port, using port data register (PDR) , outputs the output data to I/O pin and input a signal input to I/O port. The port direction register (DDR) specifies direction of input/output of I/O pins on a bit-by-bit basis.

• The following table lists the I/O ports and the peripheral functions with which they share pins.

Port pin name Pin Name (Peripheral) Peripheral Function that Shares Pin

Port 0 P00 to P07  Port 1 P10 to P17 

Port 2

Port 4

Port 5 P50 to P54 

Port 6

P20 to P23  P24 to P27 PPG0 to PPG3 8/16 bit PPG timer 0, 1

P40, P41 TIN0, TOT0 16-bit reload timer

P42 to P47

P60, P61 INT0, INT1 External interrupt

P62 to P64

P65 INT5, PWC External interrupt, PWC

P66, P67 INT6, INT7, SCL0, SDA0 External interrupt, I

SIN0, SOT0, SCK0,

SIN1, SOT1, SCK1

INT2 to INT4,

SIN, SOT, SCK

UART0, 1

External interrupt, serial IO

• Register list (port data register)

MB90335 Series

PDR0 Initial Value Access

Address : 000000

PDR1

Address : 000001

PDR2

Address : 000002

PDR4

Address : 000004

PDR5

Address : 000005

PDR6

Address : 000006

76543210

H XXXXXXXXB R/W*

15 14 13 12 11 10 9 8

H XXXXXXXXB R/W*

76543210

H XXXXXXXXB R/W*

76543210

H XXXXXXXXB R/W*

15 14 13 12 11 10 9 8

H - - - XXXXXB R/W*

76543210

H XXXXXXXXB R/W*

P67

P06P07 P05 P04 P03 P02 P01 P00

P16P17 P15 P14 P13 P12 P11 P10

P26P27 P25 P24 P23 P22 P21 P20

P46P47 P45 P44 P43 P42 P41 P40

P54 P53 P52 P51 P50

P66 P65 P64 P63 P62 P61 P60

* : R/W access to I/O ports is a bit different in behavior from R/W access to memory as follows:

• Input mode Read : The level at the relevant pin is read.

Write : Data is written to the output latch.

• Output mode

Read : The data register latch value is read. Write : Data is output to the relevant pin.

MB90335 Series

• Register list (port direction register) DDR0 Initial Value Access

Address : 000010

DDR1

Address : 000011

DDR2

Address : 000012

DDR4

Address : 000014

DDR5

Address : 000015

DDR6

Address : 000016

76543210

H 00000000B R/W

15 14 13 12 11 10 9 8

H 00000000B R/W

15 14 13 12 11 10 9 8

H - - - 00000B R/W

76543210

H 00000000B R/W

D06D07 D05 D04 D03 D02 D01 D 00

D16D17 D15 D14 D13 D12 D11 D10

76543210

D26D27 D25 D24 D23 D22 D21 D20

76543210

D46D47 D45 D44 D43 D42 D41 D40

D54 D53 D52 D51 D50

D66D67 D65 D64 D63 D62 D61 D60

• When each pin is serving as a port, the corresponding pin is controlled as follows: 0 : Input mode 1 : Output mode

This bit becomes 0 after a reset.

Note : If these registers are accessed by a read modify write instruction (such as a bit set instruction) , the bits

manipulated by the instruction are set to prescribed values but those other bits in output registers which have been set f or input are re written to the current input values of the pins . When s witching a pin from input port to output port, therefore, write a desired value in the PDR first, then set the DDR to switch the pin for output.

• Register list (Port pull-up register) RDR0 Initial Value Access

Address : 00001C

RDR1

Address : 00001D

76543210

H 00000000B R/W

RD06RD07 RD05 RD04 RD03 RD02 RD01 RD00

15 14 13 12 11 10 9 8

RD16RD17 RD15 RD14 RD13 RD12 RD11 RD10

Controls the pull-up resistor in input mode.

0 : Without pull-up resistor in input mode. 1 : With Pull-up resistor in input mode.

Meaningless in output mode (without pull-up resistor) ./ The input/output register is decided by the setting of the direction register (DDR) .

No pull-up resistor is used in stop mode (SPL = 1).

• Register list (output pin register)

MB90335 Series

ODR4 Initial Value Access

Address : 00001B

76543210

H 00000000B R/W

OD46OD47 OD45 OD44 OD43 OD42 OD41 OD40

Controls open-drain output in output mode.

0 : Serves as a standard output port in output mode. 1 : Serves as an open-drain output port in output mode.

Meaningless in input mode. (output High-Z) / The input/output register is decided by the setting of the direction register (DDR) .

• Block diagram of port 0 pin and port1 pin

Pull-up resistor setting register

(RDRx)

Built-in pull-up

resistor

PDRx read

Input

buffer

Output

buffer

Port

Standby control (LPMCR : SPL = “1”)

Internal data bus

PDRx Write

Port data

Port direction

I/O

decision circuit

• Block diagram of port 2 pin, port 4 pin, port 5 pin and port 6 pin

Resource input

PDRx read

PDRx

Internal data bus

write

Port data

Port direction

I/O

decision circuit

Resource output control signal

Release output

input

buffer

Output

buffer

Port

Standby control (LPMCR : SPL = “1”)

MB90335 Series

2. Time-base timer

• The time-base timer is an 18-bit free-running counter (time-base timer counter) that counts in synchronization with the main clock (2 cycles of the oscillation clock HCLK).

• Four different time intervals can be selected, for each of which an interrupt request can be generated.

• Operating clock signals are supplied to peripheral resources such as the oscillation stabilization wait timer and watchdog timer.

••••

Interval time of time-base timer

Internal count clock cycle Interval time

/HCLK (Approx. 0.68 ms)

2/HCLK (0.33 µs)

Notes : • HCLK : Oscillation clock frequency

• The parenthesized values assume an oscillator clock frequency of 6 MHz.

/HCLK (Approx. 2.7 ms)

/HCLK (Approx. 10.9 ms)

/HCLK (Approx. 87.4 ms)

••••

Clock cycles supplied from time-base timer

Where to supply clock Clock cycle

/HCLK (Approx. 1.36 ms)

Oscillation stabilization wait of

main clock

Watch dog timer

/HCLK (Approx. 5.46 ms)

/HCLK (Approx. 21.84 ms)

/HCLK (Approx. 0.68 ms)

/HCLK (Approx. 2.7 ms)

/HCLK (Approx. 10.9 ms)

/HCLK (Approx. 87.4 ms)

Notes : • HCLK : Oscillation clock frequency

• The parenthesized values assume an oscillator clock frequency of 6 MHz.

•

Time-base timer control register (TBTC)

15 14 13 12 11 10 9 8

Address : 0000A9H 1--00100B

RESV  TBIE TBOF TBR TBC1 TBC0

( R/W )



(  )(  ) ( R/W ) ( R/W ) ( W ) ( R/W ) ( R/W )

Initial Value

Note : F or the conditions for clearing the time-base timer, ref er to the chapter for the time-base timer in the hardware

manual.

• Block Diagram

MB90335 Series

Time-base timer counter

Dividing HCLK by 2

Power-on reset Stop mode start

CKSCR : MCS = 1→0*

Time-base timer control register (TBTC)

Time-base timer interrupt signal

 :Unused

OF :Overflow

HCLK :Oscillation clock

*1 :Switching the machine clock from main clock to PLL clock

× 21× 2

To PPG timer

clear control

× 28× 29× 210× 211× 212× 213× 214× 215× 216× 217× 2

Counter

circuit

Interval timer selector

TBOF clear

TBIE TBOF TBRRESV  TBC1 TBC0

To watchdog timer

To clock controller oscillation stabilizing wait time selector

TBOF

set

Actual interrupt request number of time-base timer is as follows:

Interrupt request number:#40 (28

MB90335 Series

3. Watchdog timer

• The watchdog timer is a timer counter prepared in case programs run out of control.

• The watchdog timer is a 2-bit counter using the time-base timer as the count clock.

• When started, the watchdog timer resets the CPU if it is not cleared before the two-bit counter overflows.

••••

Interval time of watchdog timer

HCLK: Oscillation clock (6 MHz)

Min Max Clock cycle

Approx. 2.39 ms Approx. 3.07 ms 2 Approx. 9.56 ms Approx. 12.29 ms 2

Approx. 38.23 ms Approx. 49.15 ms 2

Approx. 305.83 ms Approx. 393.22 ms 2

Notes : • The maximum and minimum time intervals for the watchdog timer depend on the counter clear timing.

• The watchdog timer contains a 2-bit counter that counts the carry signals of the time-base timer. When the device is operating with HCLK, theref ore, clearing the time-base timer lengthens the watchdog reset generation time interval.

± 211 / HCLK

± 213 / HCLK

± 215 / HCLK

± 218 / HCLK

Event that stop the watchdog timer

•

1 : Stop due to a Power-on reset 2 : watchdog reset

• Clear factor of watch dog timer

1 : External reset input by RST pin 2 : Writing “0” to the software reset bit 3 : Writing “0” to the watchdog control bit (second and subsequent times) 4 : Transition to sleep mode (Clearing the watchdog timer, and suspend counting) 5 : Transition to time-base timer mode (Clearing the watchdog timer, and suspend counting) 6 : Transition to stop mode (Clearing the watchdog timer, and suspend counting)

•

Watchdog timer control register (WDTC)

76543210

Address : 0000A8

H X-XXX111B

PONR WRST ERST SRST WTE WT1 WT0

( R )



(  ) ( R ) ( R ) ( R ) ( W ) ( W ) ( W )

Initial Value

• Block Diagram

Timer-base timer mode start

Sleep mode start

Stop mode start

Watchdog timer control register (WDTC)

PONR  WRST ERST SRST WTE WT1 WT0

Watchdog timer

Counter

clear control

circuit

Count clock

selector

CLR

CLR and start

2-bit

counter

MB90335 Series

CLR

watchdog timer

reset

generation

circuit

To internal reset generation circuit

Dividing HCLK by 2

HCLK: Oscillation clock

Clear

Time-base timer counter

× 2

× 28× 29× 210× 211× 212× 213× 214× 215× 216× 217× 2

MB90335 Series

4. 16 - bit Reload Timer

The 16-bit reload timer has the internal clock mode to be decrement in synchronization with three different internal clocks and the event count mode to decrement upon detection of an arbitrary edge of the pulse input to the external pin. Either can be selected. This timer defines when the count value changes from 0000 FFFF

H as an underflow. The timer therefore causes an underflow when the count reaches [reload register

setting +1]. Either mode can be selected for the count operation from the reload mode which repeats the count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as to correspond to the DTC.

• Register list

• Timer control status register

Timer control status register (Higher) (TMCSR0)

Initial Value

Address : 000063

15 14 13 12 11 10 9 8

H XXXX0000B

CSL1 CSL0 MOD2 MOD1

(  )



(  )(  )(  ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

H to

Timer control status register (Lower) (TMCSR0)

Initial Value

Address : 000062

76543210

H 00000000B

MOD0 OUTL RELD INTE UF CNTE TRG

( R/W )

OUTE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

• 16-bit timer register/16-bit reload register TMR0/TMRLR0 (Higher)

15 14 13 12 11 10 9 8

Address : 000065H XXXXXXXXB

D15 D13 D12 D11 D10 D09 D08

( R/W )

D14

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

TMR0/TMRLR0 (Lower)

Initial Value

Address : 000064

76543210

H XXXXXXXXB

D07 D05 D04 D03 D02 D01 D00

( R/W )

D06

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

• Block Diagram

TMRLR0

16-bit reload register

TMR0

16-bit timer register

Internal data bus

Reload signal

∗2

MB90335 Series

Reload

control circuit

Count clock generation circuit

CLK

Machine clock φ

Prescaler

Gate input

Valid clock

decision

circuit

Wait signal

Clear

TIN0

Trriger

Input

control

circuit

Internal clock

External clock

Clock

selector

CLK

Select signal

Output control circuit

Output signal

generation

circuit

EN TOT0

Select function

CSL1 CSL0 MOD2MOD1MOD0OUTE OUTL RELD UFINTE CNTE TRG

Timer control status register (TMCSR0)

*1 : Interrupt number *2 : Underflow

Operating

Control

circuit

Interrupt request output #23 (17

H)*1

MB90335 Series

5. Multifunction timer

• The multifunction timer can be used for waveform output, input pulse width measurement, and ex ternal clock cycle measurement.

••••

Configuration of a multi-functional timer

8/16 bit PPG timer 16 bit PWC timer

8 bit × 4 ch

(16 bit × 2 ch)

• 8/16 bit PPG timer (8 bit : 4 channels, 16 bit : 2 channels) 8/16 bit PPG timer consists of a 8 bit down counter (PCNT) , PPG control register (PPGC0 to PPGC3) , PPG

clock control register (PCS01, PCS23) and PPG reload register (PRLL0 to PRLL3, PRLH0 to PRLH3) . When used as an 8/16 bit reload timer, the PPG timer serves as an event timer. It can also output pulses of an

arbitrary duty ratio at an arbitrary frequency.

• 8 bit PPG mode

Each channel operates as an independent 8 bit PPG.

• 8 bit prescaler + 8 bit PPG mode

Operates as an arbitrary-cycle 8 bit PPG with ch0 (ch2) operating as an 8 bit prescaler and ch2 (ch3) counted by the borrow output of ch0 (ch2).

• 16 bit PPG mode

Operates as a 16 bit PPG with ch0 (ch2) and ch1 (ch3) connected.

• PPG Operation

The PPG timer outputs pulses of an arbitrary duty ratio (the ratio between the High and Low level periods of pulse waveform) at an arbitrary frequency. Can also be used as a D/A converter by an external circuit.

1 ch

• Register list

PPG operation mode control register (PPGC1/PPGC3)

15 14 13 12 11 10 9 8

Address :

000047 000049H

( R/W ) (  ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

(PPGC0/PPGC2)

76543210

( R/W ) (  ) ( R/W ) ( R/W ) ( R/W ) (  )(  ) ( R/W )

Address :

000046H 000048H

PPG output control register (PPG01/PPG23)

76543210

PCS1PCS2 PCS0 PCM2 PCM1 PCM0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Address :

00004CH 00004EH

PPG reload register (PRLH0 to PRLH3)

15 14 13 12 11 10 9 8

D14D15 D13 D12 D11 D10 D09 D08

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Address :

007901 007903H 007905H 007907H

MB90335 Series

PEN1 PE10 PIE1 PUF1 MD1 MD0

PEN0 PE0O PIE0 PUF0 

Reserved

Initial Value 0X000001B

Initial Value 0X000XX1B

Initial Value 000000XX

Initial Value

XXXXXXXX

(PRLL0 to PRLL3)

007900

Address :

007902H 007904H 007906H

76543210

D06D07 D05 D04 D03 D02 D01 D00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

XXXXXXXX

MB90335 Series

• 8 bit PPG ch0/2 block diagram

Count clock selector

Timebase counter output main clock × 512

L/H selector

Peripheral clock × 16 Peripheral clock × 8 Peripheral clock × 4 Peripheral clock × 2 Peripheral clock

PCNT

(down counter)

L/H selector

PRLL PRLHB

PRLL

PPG 0/2 output enable

PPG 0/2 output latch

PPG0/2

A/D converter

PEN0

S RQ

ch1/3/5 borrow

PIE0PUF0

PPGC0

(operation mode control)

IRQ

To interrupt #30 (1E #32 (20

H)*

* : Interrupt number

L data bus H data bus

• 8 bit PPG ch1/3 block diagram

MB90335 Series

Count clock selector

Timebase counter output main clock × 512

L/H selector

Peripheral clock × 16 Peripheral clock × 8 Peripheral clock × 4 Peripheral clock × 2 Peripheral clock

PCNT0

(down counter)

L/H selector

PRLL PRLHB

PRLL

PPG 1/3 output enable

PPG 1/3 output latch

PPG1/3

PEN1

S RQ

PIE1PUF1

PPGC0

(operation mode control)

IRQ

To interrupt #30 (1E #32 (20H)*

H)*

* : Interrupt number

L data bus H data bus

MB90335 Series

• PWC timer The PWC timer is a 16 bit multifunction up-count timer capable of measuring the input signal pulse width.

• Register list

PWC control status register (PWCSR)

Initial Value

Address : 00005D

15 14 13 12 11 10 9 8

H 0000000XB

STRT EDIR EDIE OVIR OVIE ERR

( R/W )

STOP

( R/W ) ( R ) ( R/W ) ( R/W ) ( R/W ) ( R ) ( R/W )

Reserved

Initial Value

Address : 00005C

76543210

H 00000000B

CKS1 PIS1 PIS0 S/C MOD2 MOD1 MOD0

( R/W )

CKS0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

PWC data buffer register (PWCR)

15 14 13 12 11 10 9 8

Address : 00005FH 00000000B

Address : 00005E

D15 D13 D12 D11 D10 D9 D8

( R/W )

H 00000000B

D7 D5 D4 D3 D2 D1 D0

( R/W )

D14

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

76543210

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

Ratio of dividing frequency control register (DIVR)

Initial Value

Address : 000060

76543210

H ------00B

DIV1 DIV0

(  )



(  )(  )(  )(  )(  ) ( R/W ) ( R/W )

• Block Diagram

MB90335 Series

PWCR read

MC-16 bus

Flag set etc...

Reload

Data transfer

Over-

flow

Control circuit

Start edge

Measurement starting edge

Measurement

termination edge

Measurement

Control bit output

termination interrupt

Overflow interrupt

selection

request

PWCSR

Error

detection

PWCR

16 bit up-count timer

end edge selection

Edge

detection

PIS0/PIS1

ERR

CKS0/CKS1

Clock

Timer

clear

Count enable

Divider ON/OFF

8-bit

divider

Divide ratio select

DIVR

CKS1/CKS0

Internal clock (Machine clock/4)

Clock

devider

Divider

Input

waveform

comparator

clear

PWC

MB90335 Series

6. UART

Overview of UA RT

• UART is a general purpose serial communication interface for synchronous or asynchronous (start-stop syn-

chronization) communications with external devices.

• It suppor ts bi-directional communication (normal mode) and master/slave communication (multi-processor

mode: supported on master side only).

• An interrupt can be generated upon completion of reception, detection of a reception errror , or upon completion

of transmission. EI

• UART functions UART, or a generic ser ial data communication interface that sends and receives serial data to and from other

CPU and peripherals, has the functions listed in following.

Data buffer Full-duplex double-buffered

Transmission mode

Baud rate

OS is supported also.

• Clock synchronous (without start/stop bit)

• Clock asynchronous (start-stop synchronous)

• Special-purpose baud-rate generator It is optional from eight kinds.

• Baud rate by external clock (cloc k of SCK0/SCK1 terminal input)

Function

Data length

• 8 bits or 7 bits (in the asynchronous normal mode only)

• 1 to 8 bits (in the synchronous mode only)

Signaling system Non Return to Zero (NRZ) system

• Framing error

Reception error detection

• Overrun error

• Parity error (Not supported in operation mode 1)

• Receive interrupt (reception completed, reception error detected)

Interrupt request

• Transmission interrupt (transmission completed)

• Both the transmission and reception support EI

OS.

Master/slave type

communication function

Capable of 1 (master) to n (slaves) communication (available just as master)

(multi processor mode)

Note : In clock synchronous transfer mode, the UART transfers only data with no start or stop bit added.

UART operation modes

Data length

Operation mode

Synchronization Stop bit length

Without parity With parity

0 Normal mode 7 bits or 8 bits Asynchronous 1 Multi processor mode 8 + 1 *

 Asynchronous

1 bit or 2 bits *

2 Normal mode 8  Synchronous No

 : Setting disabled *1 : + 1 is an address/data setting bit (A/D) which is used for communication control. *2 : Only one bit can be detected as a stop bit at reception.

• Register list Serial mode register (SMR0, SMR1)

Address : 00100000

000020

000026H

76543210

MD1 SCKL M2L2 M2L1 SCKE SOE

( R/W )

MD0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Serial control register (SCR0, SCR1)

Address : 00000100B

000021H 000027H

15 14 13 12 11 10 9 8

PEN SBL CL A/D REC RXE TXE

( R/W )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( W ) ( R/W ) ( R/W )

Serial input/output register (SIDR0, SIDR1 / SODR0, SODR1)

Address : XXXXXXXX

000022H 000028H

76543210

D7 D5 D4 D3 D2 D1 D0

( R/W )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Serial data register (SSR0, SSR1)

Address : 00001000

000023H 000029H

15 14 13 12 11 10 9 8

PE FRE RDRF TDRE BDS RIE TIE

( R )

ORE

( R ) ( R ) ( R ) ( R ) ( R/W ) ( R/W ) ( R/W )

MB90335 Series

Initial Value

M2L0

Initial Value

UART prescaler reload register (UTRLR0, UTRLR1)

Address : 00000000B

000024H 00002AH

76543210

D7 D5 D4 D3 D2 D1 D0

( R/W )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

UART prescaler control register (UTCR0, UTCR1)

Address : 0000-000

000025H 00002BH

15 14 13 12 11 10 9 8

MD CKS  D10 D9 D8

( R/W )

SRST

( R/W ) ( R/W ) ( R/W ) (  ) ( R/W ) ( R/W ) ( R/W )

Reserved

Initial Value

MB90335 Series

・Block Diagram

Special-purpose baud-rate generator (UART prescaler control register UTCR0, 1)

SCK0, SCK1

Clock

selector

Reception

clock

Start bit

detection circuit

Control bus

Reception

control

circuit

Transmission

clock

Transmission

start circuit

Transmission

control circuit

Reception interrupt signal

#39 (27

Send interrupt signal

#37 (25

∗

SIN0, SIN1

Receive status decision circuit

SMR0,

SMR1

Reception bit

counter

Reception parity

counter

Shift register for

reception

SIDR0, SIDR1

MD1 MD0 SCKL M2L2 M2L1 M2L0 SCKE SOE

Reception

complete

Internal data bus

SCR0,

SCR1

Transmission bit

counter

Transmission

parity counter

Shift register for

transmission

SODR0, SODR1

PEN P SBL CL A/D REC RXE TXE

SSR0,

SSR1

SOT0, SOT1

Start

transmission

Reception error occurrence signal for

OS (to CPU)

PE ORE FRE RDRF TDRE BDS RIE TIE

* : Interrupt number

MB90335 Series

7. Extended I/O serial interface

The extended I/O serial interface is a serial I/O interface that can transfer data through the adoption of 8-bit × 1 channel configured clock synchronization scheme. LSB-first or MSB-first transfer mode can be selected for data transfer.

There are two serial I/O operation modes available:

• Internal shift clock mode: Transfer data in synchronization with the internal clock.

• External shift clock mode: T r ansfer data in synchronization with the cloc k supplied via the e xternal pin (SCK). By manipulating the general-purpose por t sharing the external pin (SCK) in this mode, data can also be transferred by a CPU instruction.

• Register list Serial mode control status register (SMCS)

Initial Value

Address : 000059

15 14 13 12 11 10 9 8

H 00000010 B

SMD1SMD2 SMD0 SIE SIR BUSY STOP STRT

( R/W )( R/W )( R/W )

( R/W )

( R/W ) ( R/W )

76543210

Address : 000058

H XXXX0000 B

(  )

MODE BDS SOE SCOE

(  )

Serial data register (SDR)

76543210

Address : 00005A

H XXXXXXXXB

( R/W )

D6D7 D5 D4 D3 D2 D1 D0

Communication prescaler control register (SDCR)

15 14 13 12 11 10 9 8

Address : 00005B

H 0XXX0000B

MD DIV3 DIV2 DIV1 DIV0

( R/W )



(  )(  )(  ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

(  )

( R/W )

( R/W ) ( R/W )( R/W )( R/W )

Initial Value

( R/W )

Initial Value

MB90335 Series

• Block Diagram

Internal data bus

(MSB first) D0 to D7

SIN

SOT

SCK

Internal clock

SMD2

D7 to D0 (LSB first)

Transfer direction selection

SDR (serial data register)

Control circuit

21 0

SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS

Shift clock counter

Interrupt request

Internal data bus

Initial Value

Read Write

SOE SCOE

MB90335 Series

8. I2C Interface

The I2C interface is a serial I/O port suppor ting the Inter IC BUS. It serves as a master/slave device on the I2C bus and has the following features.

• Master/slave sending and receiving

• Arbitration function

• Clock synchronization function

• Slave address and general call address detection function

• Detecting transmitting direction function

• Start condition repeated generation and detection function

• Bus error detection function

• Register list

C bus status register (IBSR0)

Address : 000070

76543210

H 00000000B

BB AL LRB TRX AAS GCA FBT

( R )

RSC ( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R )

Initial Value

C bus control register (IBCR0)

15 14 13 12 11 10 9 8

Address : 000071H 00000000B

C bus clock selection register (ICCR0)

BER SCC MSS ACK GCAA INTE INT

( R/W )

Address : 000072H XXX0XXXXB

(  )

C bus address register (IADR0)

Address : 000073

C bus data register (IDAR0)

Address : 000074

H XXXXXXXXB

(  )

H XXXXXXXXB

( R/W )

BEIE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

76543210

 EN CS4 CS3 CS2 CS1 CS0

15 14 13 12 11 10 9 8

 A5 A4 A3 A2 A1 A0

76543210

D7 D5 D4 D3 D2 D1 D0



(

 ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

MB90335 Series

• Block Diagram

ICCR

I2C enable

Clock devide 1

56 78

Peripheral clock

MC-16 bus

CS4 CS3

CS2 CS1 CS0

IBSR

RSC LRB TRX

FBT

IBCR

BER

BEIE INTE

Clock selector 1

2 4 8 16 128

Bus busy

Repeat start

Last Bit

Send/receive

Clock devide 2

25632 64

Clock selector 2

Start stop condition

detection

First Byte

Arbitration lost detection

Interrupt request

Sync

Generating shift clock

Shift clock edge

change timing

Error

IRQ

SCL0

SDA0

INT

IBCR

SCC

MSS ACK

GCAA

IBSR

AAS

GCA

Start

Master

ACK enable

GC-ACK enable

Slave

Global call

End

Start stop condition

generation

IDAR

Slave address

compare

IADR

MB90335 Series

9. USB Function

The USB is an interface supporting the USB (Universal Serial Bus) communications protocol. Feature of USB function

• Conform to USB 2.0 Full Speed

• FULL speed (12 Mbps) is supported.

• The device status is auto-answer.

• Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16.

• Toggle check by data synchronization bit.

• Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these three commands can be processed the same way as the class vendor commands).

• The class vendor commands can be received as data and responded via firmware.

• Supports up to maximum six EndPoints (EndPoint0 is fixed to control transfer).

• Two transfer data buffers integrated for each end point (one IN buffer and one OUT buffer for end point 0).

• Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint0).

• Capable of detection of connection and disconnection by monitoring the USB bus power line.

• Register list UDC control register (UDCC)

Address : 0000D0

76543210

H 10100000B

( R/W )

RESUM

RST HCONX USTP RFBK PWC

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Reserved

Initial Value

EP0 control register (EP0C)

76543210

Address : 0000D2

Address : 0000D3H XXXX0000B

H X1000000B

Reserved

( R/W )

(  )

PKS0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15 14 13 12 11 10 9 8

 STAL

(  )(  )(  ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

PKS0 PKS0 PKS0 PKS0 PKS0



Reserved Reserved Reserved

PKS0

Initial Value

EP1 control register (EP1C)

76543210

Address : 0000D4H 00000000B

PKS1 PKS1 PKS1 PKS1 PKS1 PKS1 PKS1

( R/W )

PKS1

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

15 14 13 12 11 10 9 8

Address : 0000D5H 01100001B

EPEN TYPE DIR DMAE NULE STAL PKS1

( R/W )

TYPE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

(Continued)

MB90335 Series

EP2/3/4/5 control register (EP2C 〜EP5C)

76543210

Reserved

( R/W )

PKS2∼5

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Address :

0000D6 0000D8H 0000DAH 0000DCH

PKS2∼5 PKS2∼5 PKS2∼5 PKS2∼5 PKS2∼5 PKS2∼5

Initial Value

01000000B

Initial Value

01100000B

Address :

0000D7 0000D9H 0000DBH

15 14 13 12 11 10 9 8

EPEN TYPE DIR DMAE NULE STAL

( R/W )

TYPE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Reserved

0000DDH

Time stamp register (TMSP)

76543210

Address : 0000DE

Address : 0000DFH 00000000B

H 00000000B

TMSP

( R )

(  )

TMSP

( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R )

15 14 13 12 11 10 9 8

 TMSP TMSP TMSP

(

TMSP TMSP TMSP TMSP TMSP TMSP

  )(  )(  )(  ) ( R ) ( R ) ( R )

Initial Value

UDC status register (UDCS)

76543210

Address : 0000E0H 00000000B

VOFF SUSP SOF BRST WKUP SETP CONF

( R/W )

VON

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

Interrupt enable register (UDCIE)

Address : 0000E1

EP0I status register (EP0IS)

Address : 0000E2

Address : 0000E3H 10XXX1XXB

15 14 13 12 11 10 9 8

H 00000000B

VOFFIE SUSPIE SOFIE BRSTIE WKUPIE CONFN CONFIE

( R/W )

H XXXXXXXXB

( R/W )

VONIE ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R ) ( R/W )

76543210



(  )

15 14 13 12 11 10 9 8

BFINI DRQI 



(  )(  )(  )(  )(  )(  )(  )

DRQIIE

( R/W ) (  )(  )(  ) ( R/W ) (  )(  )



Initial Value

(Continued)

EP0O status register (EP0OS)

Address : 0000E4

H XXXXXXXXB

MB90335 Series

76543210

SIZE

 SIZE SIZE SIZE SIZE SIZE SIZE

(  )

( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R )

Initial Value

15 14 13 12 11 10 9 8

Address : 0000E5

H 100XX00XB

( R/W )

DRQOIE

BFINI SPKIE DRQO SPK 

( R/W ) ( R/W ) (  )(  ) ( R/W ) ( R/W ) (  )

EP1 status register (EP1S)

76543210

Address : 0000E6

Address : 0000E7

H XXXXXXXXB

H 1000000XB

SIZE

( R/W )

15 14 13 12 11 10 9 8

BFINI SPKIE  BUSY DRQ SPK SIZE

( R/W )

SIZE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DRQIE ( R/W ) ( R/W ) (

EP2/3/4/5 status register (EP2S to EP5S)

76543210

SIZE

 SIZE SIZE SIZE SIZE SIZE SIZE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

(  )

Address :

0000E8 0000EAH 0000ECH

0000EEH

Initial Value

SIZE SIZE SIZE SIZE SIZE SIZE

Initial Value

 ) ( R ) ( R/W ) ( R/W ) ( R/W )

Initial Value

XXXXXXXXB

15 14 13 12 11 10 9 8

Address :

0000E9 0000EBH 0000EDH

BFINI SPKIE  BUSY DRQ SPK 

( R/W )

DRQIE ( R/W ) ( R/W ) (  ) ( R ) ( R/W ) ( R/W ) (  )

0000EFH

EP0/1/2/3/4/5 data register (EP0DT to EP5DT)

0000F0H

Address :

0000F2H 0000F4 0000F6H 0000F8H

76543210

BFDT

( R/W )

BFDT

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

BFDT BFDT BFDT BFDT BFDT BFDT

0000FAH

0000F1H

Address :

0000F3H 0000F5 0000F7H 0000F9H

15 14 13 12 11 10 9 8

BFDT BFDT BFDT BFDT BFDT BFDT BFDT

( R/W )

BFDT

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

0000FBH

Initial Value

1000000XB

Initial Value

XXXXXXXXB

Initial Value

XXXXXXXXB

MB90335 Series

10. USB Mini-HOST

USB Mini-HOST provides minimal host operations required and is a function that enables data to be transf erred to and from Device without PC intervention.

Feature of USB Mini-HOST

• Automatic detection of Low Speed/Full Speed transfer

• Low Speed/Full Speed transfer support

• Automatic detection of connection and cutting device

• Reset sending function support to USB-bus

• Support of IN/OUT/SETUP/SOF token

• In-token handshake packet automatic transmission (excluding STALL)

• Handshake packet automatic detection at out-token

• Supports a maximum packet length of 256 bytes

• Error (CRC error/toggle error/time-out) various supports

• Wake-Up function support

Differences between the USB HOST and USB Mini-HOST

HOST Mini-HOST

Hub support ×

Bulk transfer

Transfer

Transfer speed

PRE packet support × SOF packet support

Error

Detection of connection and cutting of device Transfer speed detection

: Supported

× : Not supported

Control transfer Interrupt transfer ISO transfer × Low Speed Full Speed

CRC error Toggle error Time-out Maximum packet < receive

data

MB90335 Series

• Register list

USB HOST control register 0 (HCONT0)

76543210

Address : 0000C0

USB HOST control register 1 (HCONT1)

Address : 0000C1H 00000001B

USB HOST interruption register (HIRQ)

Address : 0000C2H 00000000B

USB HOST error status register (HERR)

Address : 0000C3H 00000011B

H 00000000B

RWKIRE CMPIRE CNNIRE DIRE SOFIRE URST HOST

( R/W )

Reserved Reserved Reserved Reserved Reserved

( R/W )

TCAN RWKIRQ URIRQ CMPIRQ CNNIRQ DIRQ SOFIRQ

( R/W )

LSTSOF TOUT CRC TGERR STUFF HS HS

( R/W )

URIRE ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15 14 13 12 11 10 9 8

SOFSTEPCANCEL RETRY

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

76543210

Reserved

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15 14 13 12 11 10 9 8

RERR

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

USB HOST state status register (HSTATE)

Address : 0000C4

76543210

H XX010010B

 ALIVE CLKSEL

(  )



(

 ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R ) ( R )

SOFBUSY SUSP TMODE CSTAT

Initial Value

USB SOF interruption FRAME comparison register (HFCOMP)

Address : 0000C5

15 14 13 12 11 10 9 8

FRAME

H 00000000B

COMP

( R/W )

FRAME

COMP

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

FRAME

COMP

FRAME

COMP

FRAME

COMP

FRAME

COMP

FRAME

COMP

FRAME

COMP

Initial Value

USB retry timer setting register 0/1/2 (HRTIMER)

76543210

Address : 0000C6H 00000000B

Address : 0000C7H 00000000B

RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0

( R/W )

RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1

Address : 0000C8H XXXXXX00B

RTIMER0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15 14 13 12 11 10 9 8

RTIMER1

( R/W )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

76543210



(  )



(  )(  )(  )(  )(  ) ( R/W ) ( R/W )

RTIMER2 RTIMER2

Initial Value

(Continued)

MB90335 Series

(Continued)

USB HOST address register (HADR)

15 14 13 12 11 10 9 8

Address : 0000C9

USB EOF setting register 0/1 (HEOF)

Address : 0000CAH 00000000B

H X0000000B



ADDRESS

(  )

76543210

EOF0 EOF0 EOF0 EOF0 EOF0 EOF0 EOF0

( R/W )

ADDRESSADDRESSADDRESSADDRESSADDRESSADDRESS

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

EOF0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

15 14 13 12 11 10 9 8

Address : 0000CBH XX000000B

 EOF1 EOF1 EOF1 EOF1 EOF1 EOF1

(  )



(

 ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

USB FRAME setting register (HFRAME)

76543210

Address : 0000CCH 00000000B

FRAME0 FRAME0FRAME0 FRAME0 FRAME0FRAME0 FRAME0

( R/W )

Address : 0000CDH XXXXX000B

FRAME0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15 14 13 12 11 10 9 8

 

(  )



(  )(  )(  )(  ) ( R/W ) ( R/W ) ( R/W )

FRAME1 FRAME1 FRAME1

Initial Value

USB token end point register (HTOKEN)

76543210

Address : 0000CEH 00000000B

TGGL TKNEN TKNEN ENDPT ENDPT ENDPT ENDPT

( R/W )

TKNEN

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

MB90335 Series

11. DTP/external interrupt circuit

Feature of DTP/external interrupt circuit

DTP (Data Transfer Peripheral)/external interrupt circuit detects the interrupt request input from the external interrupt input terminal INT7 to INT0, and outputs the interrupt request.

• DTP/external interrupt circuit function

The DTP/external interrupt function outputs an interrupt request upon detection of the edge or level signal input to the external interrupt input pins (INT7 to INT0).

If CPU accept the interrupt request, and if the extended intelligent I/O service (EI the interrupt handling routine after completing the automatic data transfer (DTP function) performed by EI And if EI (DTP function) performed by EI

••••

Feature of DTP/external interrupt circuit

OS is disabled, it branches to the interrupt handling routine without activating the automatic data transf er

OS.

External interrupt DTP function

Input pin

8 channels (P60/INT0, P61/INT1, P62/INT2/SIN, P63/INT3/SOT, P64/INT4/SCK, P65/INT5/PWC, P66/INT6/SCL0, P67/INT7/SDA0)

The detection level or the type of the edge for each terminals can be set in the

Interrupt source

request level setting register (ELVR) Input of “H” level/ “L” level/rising edge/falling edge.

Interrupt number #18 (12 Interrupt control

Enabling/Prohibit the interrupt request output using the DTP/interrupt enable register (ENIR)

H) , #20 (14H) , #22 (16H) , #24 (18H)

Interrupt flag Holding the interrupt source using the DTP/interrupt cause register (EIRR)

Process setting Prohibit EI Process

Branched to the interrupt handling routine

OS (ICR: ISE=“0”) Enable EI2OS (ICR: ISE=“1”)

After an automatic data transfer by EI Branched to the interrupt handling routine

OS) is enabled, branches to

OS,

OS.

• Register list

Interrupt/DTP enable register (ENIR)

76543210

Address : 00003C

H 00000000B

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

EN6EN7 EN5 EN4 EN3 EN2 EN1 EN0

Interrupt/DTP source register (EIRR)

15 14 13 12 11 10 9 8

Address : 00003DH 00000000B

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

ER6ER7 ER5 ER4 ER3 ER2 ER1 ER0

Request level setting register (ELVR)

76543210

Address : 00003EH 00000000B

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

15 14 13 12 11 10 9 8

Address : 00003F

H 00000000B

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

LA3LB3 LB2 LA2 LB1 LA1 LB0 LA0

LA7LB7 LB6 LA6 LB5 LA5 LB4 LA4

Initial Value

MB90335 Series

• Block Diagram

Request level setting register (ELVR)

LB7

LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

22222222

P67/INT7

SDA0

Selector

P66/INT6

SCL0

P65/INT5

PWC

P64/INT4

SCK

DTP/interrupt

Internal data bus

source register (EIRR)

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

DTP/interrupt enable register (ENIR)

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

Selector

DTP/external interrupt input detection circuit

Selector

P60/INT0

Selector

P61/INT1

Interrupt request signal

#18(12H)

#20(14H)

#22(16H)

#24(18H)

∗

P62/INT2

SIN

P63/INT3

SOT

* : Interrupt number

MB90335 Series

12. Interrupt controller

The interrupt control register is located inside the interrupt controller, it exists for every I/O having an interrupt function. This register has the following functions.

• Setting of the interrupt levels of relevant peripheral

••••

Interrupt control register Address：ICR01 : 0000B1

ICR03 : 0000B3H ICR05 : 0000B5H ICR07 : 0000B7H ICR09 : 0000B9H ICR11 : 0000BBH ICR13 : 0000BDH ICR15 : 0000BFH

Read/Write →

Initial Value →

15 14 13 12 11 10 9 8

ICS3 ICS1 ICS0 ISE IL2 IL1 IL0 ( W )

( 0 )

ICS2

( W )

( 0 )

( W )

( 0 )

( W )

( 0 )

( R/W )

( 0 )

( R/W )

( 1 )

( R/W )

( 1 )

( R/W )

( 1 )

ICR01, 03, 05, 07, 09, 11, 13, 15

Address：

ICR00 : 0000B0 ICR02 : 0000B2H

ICR04 : 0000B4H ICR06 : 0000B6H ICR08 : 0000B8H ICR10 : 0000BAH ICR12 : 0000BCH ICR14 : 0000BEH

Read/Write →

76543210

ICS3 ICS1 ICS0 ISE IL2 IL1 IL0

( W )

( 0 )

ICS2 ( W )

( 0 )

( W )

( 0 )

( W )

( 0 )

( R/W )

( 0 )

( R/W )

( 1 )

( R/W )

( 1 )

( R/W )

( 1 )

ICR00, 02, 04, 06, 08, 10, 12, 14

Initial Value →

Note : Do not access interrupt control registers using any read modify write instruction because it causes a

malfunction.

• Block Diagram

3 3 3 3 3 3 3 3 3

MC-16LX bus

3 3 3 3 3

IL2 IL1 IL0

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

Determine

priority

interrupt

Interrupt request

(peripheral resource)

(CPU)

Interrupt level

MB90335 Series

13. µµµµDMAC

µDMAC is simple DMA with the function equal with EI2OS. It has 16 channels DMA transfer channels with the following features.

• Performs automatic data transfer between the peripheral resource (I/O) and memory

• The program execution of CPU stops in the DMA startup

• Capable of selecting whether to increment the transfer source and destination addresses

• DMA transfer is controlled by the DMA enable register, DMA stop status register, DMA status register and descriptor

• A STOP request is available for stopping DMA transfer from the resource

• Upon completion of DMA transfer, the flag bit corresponding to the transfer completed channel in the DMA status register is set and a termination interrupt is output to the transfer controller.

• Register list DMA enable register higher (DERH)

Initial Value

Address : 0000AD

15 14 13 12 11 10 9 8

H 00000000B

EN15 EN13 EN12 EN11 EN10 EN9 EN8

( R/W )

EN14

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA enable register lower (DERL)

76543210

Address : 0000AC

H 00000000B

EN7 EN5 EN4 EN3 EN2 EN1 EN0

( R/W )

EN6

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA stop status register (DSSR)

76543210

Address : 0000A4H 00000000B

STP7

STP15

STP6

STP14 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )

STP5

STP13

STP4

STP12

STP3

STP11

STP2

STP10

STP1 STP9

STP0 STP8

DMA status register higher (DSRH)

15 14 13 12 11 10 9 8

Address : 00009D

H 00000000B

DTE14DTE15 DTE13 DTE12 DTE11 DTE10 DTE9 DTE8 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )

DMA status register lower (DSRL)

76543210

Address : 00009C

H 00000000B

DTE7 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0

( R/W )

DTE6

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA descriptor channel specification register (DCSR)

76543210

Address : 00009BH 00000000B

( R/W )

Reserved Reserved Reserved

STP DCSR3 DCSR2 DCSR1 DCSR0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

* : The DSSR is lower when the STP bit of DCSR in the DSSR is 0.

The DSSR is upper when the STP bit of DCSR in the DSSR is 1.

(Continued)

DMA buffer address pointer lower 8 bit (DBAPL)

76543210

Address : 007920

H XXXXXXXXB

DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL ( R/W )

DBAPL ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA buffer address pointer middle 8 bit (DBAPM)

15 14 13 12 11 10 9 8

Address : 007921

H XXXXXXXXB

DBAPMDBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )

DMA Buffer address pointer higher 8 bit (DBAPH)

76543210

Address : 007922H XXXXXXXXB

DBAPHDBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )

DMA control register (DMACS)

15 14 13 12 11 10 9 8

Address : 007923

H XXXXXXXXB

RDY1RDY2 BYTEL IF BW BF DIR SE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )

MB90335 Series

Initial Value

DMA I/O register address pointer lower 8 bit (DIOAL)

76543210

Address : 007924

H XXXXXXXXB

A07 A05 A04 A03 A02 A01 A00

( R/W )

A06

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA I/O register address pointer higher 8 bit (DIOAH)

15 14 13 12 11 10 9 8

Address : 007925H XXXXXXXXB

A14A15 A13 A12 A11 A10 A09 A08

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )

DMA data counter lower 8 bit (DDCTL)

76543210

Address : 007926

H XXXXXXXXB

B06B07 B05 B04 B03 B02 B01 B00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )

DMA data counter higher 8 bit (DDCTH)

15 14 13 12 11 10 9 8

Address : 007927H XXXXXXXXB

B14B15 B13 B12 B11 B10 B09 B08

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )( R/W )

Note : The above register is switched for each channel depending on the DCSR.

Initial Value

MB90335 Series

14. Address matching detection function

When the address is equal to the value set in the address detection register , the instruction code to be read into the CPU is forcibly replaced with the INT9 instruction code (01H). As a result, the CPU executes the INT9 instruction when executing the set instruction. By perfor ming processing by the INT#9 interrupt routine, the program patch function is enabled. T wo address detection registers are pro vided, for each of which there is an interrupt enable bit. When the address matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code to be read into the CPU is forcibly replaced with the INT9 instruction code.

• Register list

• Program address detect register 0 to 2 (PADR0)

PADR0 (lower) Initial Value

Address : 001FF0

76543210

H XXXXXXXXB

(R/W)

PADR0 (middle) Initial Value

Address : 001FF1

H XXXXXXXXB

(R/W)

PADR0 (higher) Initial Value

Address : 001FF2

H XXXXXXXXB

(R/W)

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

15 14 13 12 11 10 9 8

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

76543210

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

• Program address detect register 3 to 5 (PADR1) PADR1 (lower) Initial Value

Address : 001FF3

PADR1 (middle) Initial Value

Address : 001FF4

15 14 13 12 11 10 9 8

H XXXXXXXXB

(R/W)

H XXXXXXXXB

(R/W)

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

76543210

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

PADR1 (higher) Initial Value

15 14 13 12 11 10 9 8

Address : 001FF5H XXXXXXXXB

(R/W)

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

• Program address detect control status register (PACSR)

PACSR Initial Value

Address : 00009EH 00000000B

76543 210

Reserved

Reserved Reserved Reserved Reserved Reserved

(R/W)

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

R/W : Readable and Writable X : Undefined

AD1E AD0E

MB90335 Series

15. Delay interrupt generator module

• The delay interrupt generation module is a module that generates interrupts for switching tasks. A hardware interrupt can be generated by software.

•

Function of delay interrupt generator module

Function and control

• Setting the R0 bit in the delayed interrupt request generate/cancel register to

Interrupt source

Interrupt control • No setting of permission register is provided.

Interrupt flag • Set in bit R0 of the delayed interrupt request generation/clear register (DIRR : R0)

OS support • Not ready for expanded intelligent I/O service (EI2OS).

• Block Diagram

1 (DIRR: R0 = 1) generates a interrupt request.

• Setting the R0 bit in the delayed interrupt request generate/cancel register to 0 (DIRR: R0 = 0) cancels the interrupt request.

Internal data bus



Delayed Interrupt source/release register (DIRR)

 : Undefined bit

S Interrupt request

R Latch

Interrupt request signal

MB90335 Series

16. ROM mirroring function selection module

• The ROM mirror function select module can make a setting so that ROM data located in bank FF can be read by accessing bank 00.

•

ROM mirroring function selection module

Description

Mirror setting address

Interrupt source • None

OS support • Not ready for extended intelligent I/O service (EI2OS).

• Block Diagram

FFFFFF the 00 bank.

H to FF8000H in the FF bank can be read through 00FFFFH to 008000H in

ROM mirror function selection register (ROMM)

Address

Internal data bus

Data

FF bank



Address area

ROM

00 bank

Re-

served

MB90335 Series

17. Low power consumption (standby) mode

•The F2MC-16LX can be set to save power consumption by selecting and setting the low power consumption mode.

•

CPU operation mode and functional description

CPU

operating clock

Operation

mode

Description

PLL clock

Main clock

CPU intermittent

operation mode

• Register list

Normally

run

Sleep

Time-base

timer

Stop

normally

run

Sleep

Time-base

timer

Stop

Normally

run

The CPU and peripheral resources operate at the clock frequency obtained by PLL multiplication of the oscillator clock (HCLK) frequency.

Only peripheral resources operate at the clock frequency obtained by PLL multiplication of the oscillator clock (HCLK) frequency.

Only the time-base timer operates at the clock frequency obtained by PLL multiplication of the oscillator clock (HCLK) frequency.

The CPU and peripheral resources are suspended with the oscillator clock stopped.

The CPU and peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (HCLK) frequency by two.

Only peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (HCLK) frequency by two.

Only the time-base timer operates at the clock frequency obtained by dividing the oscillator clock (HCLK) frequency by two.

The CPU and peripheral resources are suspended with the oscillator clock stopped.

The halved or PLL-multiplied oscillator clock (HCLK) frequency is used for operation while being decimated in a certain period.

Lowe power consumption mode control register (LPMCR)

76543210

Address : 0000A0H 00011000B

STP SPL RST TMD CG1 CG0

( W )

SLP

( W ) ( R/W ) ( W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Reserved

Initial Value

MB90335 Series

18. Clock

The clock generator controls the internal clock as the operating clock f or the CPU and peripheral resources. The internal clock is referred to as machine clock whose one cycle is defined as machine cycle . The cloc k based on source oscillation is referred to as oscillator clock while the cloc k based on internal PLL oscillation as PLL clock.

• Register list Clock selection register (CKSCR)

Initial Value

Address : 0000A1

15 14 13 12 11 10 9 8

H 11111100B

SCM WS1 WS0 SCS MCS CS1 CS0

( R )

MCM

( R ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

MB90335 Series

19. 512 Kbits flash memory

The description that follows applies to the flash memory built in the MB90F334; it is not applicable to e v aluation ROM or masked ROM.

The method of data write/erase to flash memory is following three types.

• Parallel writer

• Serial dedicated writer

• Write/erase by executing program

• Description of 512 Kbits flash memory 512 Kbits flash memory is located in FF

circuit enables read and program access from CPU. Write/erase to flash interface is executed by instruction from CPU via flash memory interface, so rewrite of program and data is carried on in the mounting state effectively.

Data can be reprogrammed not only by program execution in existing RAM but by program execution in flash memory by dual operation. The different banks (the upper and lower banks) can be used to execute an erase/ program and a read concurrently. Also, erase/write and read in the defferent bank (Upper Bank/Lower Bank) is executed simultaneously.

• Features of 512 Kbits flash memory

• Sector configuration : 64 Kwords × 8 bits/32 words × 16 bits (4K × 4 + 16K × 2 + 4K × 4)

• Simultaneous execution of erase/write and read by 2-bank configuration

• Automatic program algorithm (Embeded Algorithm

• Built-in deletion pause/deletion resume function

• Detection of programming/erasure completion using data polling and the toggle bit

• At least 10,000 times guaranteed

• Minimum flash read cycle time : 2 machine cycles

* : Embedded Algorithm Note : The read function of manufacture code and device coad is not including.

Also, these code is not accessed by the command.

• Flash write/erase

• Flash memory can not execute write/erase and read by the same bank simultaneously.

• Data can be programmed/deleted into and erased from flash memory by executing either the program

residing in the flash memory or the one copied to RAM from the flash memory.

is a trade mark of Advanced Micro Devices Inc.

H bank in the CPU memory map. Function of flash memory interface

MB90335 Series

• Sector configuration of flash memoly

Flash Memory CPU address Writer address *

SA0 (4 Kbyte)

SA1 (4 Kbyte)

SA2 (4 Kbyte)

SA3 (4 Kbyte)

SA4 (16 Kbyte)

SA5 (16 Kbyte)

SA6 (4 Kbyte)

SA7 (4 Kbyte)

SA8 (4 Kbyte)

SA9 (4Kbyte)

FF0000 FF0FFFH FF1000H FF1FFFH FF2000H FF2FFFH FF3000 FF3FFFH FF4000H FF7FFFH FF8000H FFBFFFH FFC000H FFCFFFH FFD000 FFDFFFH FFE000H FFEFFFH FFF000H FFFFFFH

70000H 70FFFH 71000H 71FFFH 72000H 72FFFH 73000H 73FFFH 74000H 77FFFH 78000H 78FFFH 7C000H 7CFFFH 7D000H 7DFFFH 7E000H 7EFFFH 7F000H 7FFFFH

Lower BankUpper Bank

* : Flash memory writer address indicates the address equivalent to the CPU address when data is written

to the flash memory using a parallel writer. Programming and erasing by the general-purpose parallel programmer are executed based on writer addresses.

MB90335 Series

• Register list

Flash memory control register (FMCS)

76543210

Address : 0000AE

H 000X0000B

( R/W )

RDYINT

INTE WE RDY LPM1 LPM0

( R/W ) ( R/W ) ( R ) ( W ) ( R/W ) ( W ) ( R/W )

Reserved Reserved

Flash memory program control register (FWR0)

76543210

Address : 00790C

H 00000000B

SA7E SA5E SA4E SA3E SA2E SA1E SA0E

( R/W )

SA6E

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Flash memory program control register (FWR1)

15 14 13 12 11 10 9 0

Address : 00790DH 00000000B

  SA9E SA8E

( R/W )



( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

Sector conversion setting register (SSR0)

76543210

Address : 00790E

H 00XXXXX0B

 SEN0

( R/W )



( R/W ) (  )(  )(  )(  )(  ) ( R/W )

∗ When writing to SSR0 register, write “0” except for SEN0.

Initial Value

MB90335 Series

• Standard configuration for Fujitsu standard serial on-board writing

The flash microcontroller programmer (AF220/AF210/AF120/AF110) made by Yokogawa Digital Computer Corp . is used for Fujitsu standard serial onboard writing.

Host interface cable (AZ201)

Flash

RS232C

microcontroller

programmer

Memory card

General-purpose common cable (AZ210)

CLK synchronous

serial

MB90F337

user system

Can operate standalone

Note : Inquire of Yokogawa Digital Computer Corporation for details about the functions and operations of the

flash microcontroller programmer (AF220, AF210, AF120 and AF110) , general-purpose common cable for connection (AZ210) and connectors.

•

Pins Used for Fujitsu Standard Serial On-board Programming

Pin Function Description

MD2, MD1, MD0

Mode input pin

The device enters the serial program mode by setting MD2 = 1, MD1 = 1 and MD0 = 0.

Because the internal CPU operation clock is set to be the 1 multiplication

X0, X1 Oscillation pin

PLL clock in the serial write mode, the internal operation clock frequency

is the same as the oscillation clock frequency. P60, P61 Write program start pins Input a Low level to P60 and a High level to P61. RST SIN0 Serial data input pin SOT0 Serial data output pin SCK0 Serial clock input pin

Reset input pin 

UART0 is used as CLK synchronous mode.

In write mode, the pins used for the UART0 CLK synchronous mode are

SIN0, SOT0, and SCK0.

When supplying the write voltage (MB90F337 : 3.3 V±0.3 V) from the V

CC Power source input pin

user system, connection with the flash microcontroller programmer is

not necessary.

When connecting, do not short-circuit with the user power supply. V

SS GND Pin Share GND with the flash microcontroller programmer.

MB90335 Series

The control circuit shown in the diagram is required for using the P60, P61, SIN0, SOT0 and SCK0 pins on the user system. Isolate the user circuit during serial on-board writing, with the /TICS signal of the flash microcontroller programmer.

AF220/AF210/AF120/AF110 Write control pin

10 kΩ

AF220/AF210/AF120/AF110 /TICS pin

User

Control circuit

The MB90F337 serial clock frequency that can be input is determined by the following expression • Use the flash microcontroller programmer to change the serial clock input frequency setting depending on the oscillator clock frequency to be used.

Imputable serial clock frequency = 0.125 × oscillation clock frequency.

• Maximum serial clock frequency

Oscillation

clock

frequency

At 6 MHz 750 kHz 500 kHz 500 kHz

•

System configuration of the flash microcontroller programmer (AF220/AF210/AF120/AF110) (made by Yokogawa

Digital Computer Corp.)

Part number Function

AF220/AC4P Model with internal Ethernet interface /100 V to 220 V power adapter

Maximum serial clock

frequency acceptable to the

microcontroller

Maximum serial clock

frequency that can be set

with the AF220/AF210/

AF120/AF110

MB90F337 write control pin

Maximum serial clock

frequency that can be set

with the AF200

AF210/AC4P Standard model /100 V to 220 V power adapter

Unit

AF120/AC4P Single key internal Ethernet interface mode /100 V to 220 V power adapter

AF110/AC4P Single key model /100 V to 220 V power adapter AZ221 PC/AT RS232C cable for writer AZ210 Standard target probe (a) length : 1 m FF201 Control module for Fujitsu F AZ290 Remote controller /P2 2 MB PC Card (option) FLASH memory capacity to respond to 128 KB /P4 4 MB PC Card (option) FLASH memory capacity to respond to 512 KB

Contact to : Yokogawa Digital Computer Corp. TEL : (81)-42-333-6224

Note : The AF200 flash micon programmer is a retired product, but it can be supported using control module FF201.

MC-16LX flash microcontroller control module

MB90335 Series

ELECTRICAL CHARACTERISTICS

■■■■

1. Absolute Maximum Ratings

Parameter Symbol

(VCC = 3.3 V, VSS = 0.0 V)

Rating

Unit Remarks

Min Max

Power supply voltage V

Input voltage V

Output voltage V

L level maximum output current

L level average output current

L level maximum total output current

L level average total output current

H level maximum output current

H level average output current

H level maximum total output current

I IOL2  43 mA USB I/O*

IOLAV  3mA*3

ΣI

ΣIOLAV  30 mA *4

I IOH2  − 43 mA USB I/O*

IOHAV  − 3mA*3

ΣIOH  − 60 mA

CC VSS − 0.3 VSS + 4.0 V

VSS − 0.3 VSS + 4.0 V *1

SS − 0.3 VSS + 6.0 V

− 0.5 V

SS + 4.5 V USB I/O

Nch0.D (Withstand voltage I/O of 5 V)

VSS − 0.3 VSS + 4.0 V *1

OL1  10 mA Other than USB I/O*

OL  60 mA

OH1  − 10 mA Other than USB I/O*

− 0.5 V

SS + 4.5 V USB I/O

H level average total output current

ΣI

OHAV  − 30 mA *4

Power consumption Pd  351 mW Target value Operating temperature T

A − 40 + 85 °C

− 55 + 150 °C

Storage temperature Tstg

− 55 + 125 °C USB I/O

*1 : V

I and VO must not exceed VCC + 0.3 V. However, if the maximum current to/from an input is limited by some

means with external components, the I

CLAMP rating supersedes the VI rating.

*2 : A peak value of an applicable one pin is specified as a maximum output current. *3 : The average output current specifies the mean value of the current flowing in the relevant single pin during a

period of 100 ms.

*4 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins

during a period of 100 ms.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

2. Recommended Operating Conditions

Parameter Symbol

Power supply voltage V

Input H level voltage

Input L level voltage

VILUSB VSS 0.8 V USB input pin

IH 0.7 VCC VCC + 0.3 V CMOS input pin

VIHS 0.8 VCC VCC + 0.3 V CMOS hysteresis input pin

IHM VCC − 0.3 VCC + 0.3 V MD input pin

IHUSB 2.0 VCC + 0.3 V USB input pin

VIL VSS − 0.3 0.3 VCC V CMOS input pin

ILS VSS − 0.3 0.2 VCC V CMOS hysteresis input pin

ILM VSS − 0.3 VSS + 0.3 V MD input pin

Value

Min Max

3.0 3.6 V At normal operation (At USB is used)

2.7 3.6 V At normal operation (At USB is unused)

1.8 3.6 V Hold state of stop operation

MB90335 Series

(VSS = 0.0 V)

Unit Remarks

Differential input sensitivity

DI 0.2  V USB input pin

Differential common mode input voltage

CM 0.8 2.5 V USB input pin

range Series resistance R

Operating temperature

S 25 30 Ω Recommended value = 27 Ω at using USB

− 40 + 85 °C At USB is unused

0 + 70 °CAt USB is used

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

MB90335 Series

3. DC Characteristics

Parameter

Output H level voltage

Output L level voltage

Input leak current

Pull-up resistor

Open drain output current

Power supply current

Input capacitance

Pull-up resistor

Sym-

bol

Pin name Conditions

Output pin of other than P60 to P67, HVP,

HVM, DVP, DVM HVP, HVM, DVP, DVM RL = 15 kΩ ± 5% 2.8  3.6 V Output pin of other

than HVP, HVM, DVP,

DVM HVP, HVM, DVP, DVM RL = 1.5 kΩ ± 5% 0  0.3 V Output pin of other

than P60 to P67, HVP,

HVM, DVP, DVM HVP, HVM, DVP, DVM − 5  5 µA P00 to P07,

PULL

P10 to P17

LIOD P60 to P67 0.1 10 µA

VCC

ICCS

CTS

CCH

Other than Vcc and

Vss

up RST  25 50 100 kΩ

(TA = − 40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Value

Min Typ Max

OH = −4.0 mA

OL = 4.0 mA Vss 

CC = 3.3 V,

V Vss < V

I < VCC

VCC = 3.3 V, Ta = + 25 °C

VCC − 0.5

− 10  10 µA

25 50 100 kΩ

VCC = 3.3 V, Internal frequency 24 MHz,

 TBD  mA

At normal operating VCC = 3.3 V,

Internal frequency 24 MHz,

 70  mA

At normal operating VCC = 3.3 V,

Internal frequency 24 MHz,

 TBD  mA

At normal operating VCC = 3.3 V,

Internal frequency 24 MHz,

 27  mA

At sleep mode VCC = 3.3 V,

Internal frequency 24 MHz,

 3.5  mA

At timer mode

CC = 3.3 V,

V Internal frequency 3 MHz,

 1  mA

At timer mode Ta = +25 °C,

At Stop mode

 1 µA

515pF

Unit Remarks

 Vcc V

Vss + 0.4

At USB operating Max 90 mA (Target)

At nonoperating USB (USTP = 0)

At nonoperating USB (USTP = 1)

Note : P60 to P67 are N-ch open-drain pins usually used as CMOS.

4. AC Characteristics

(1) Clock input timing

Parameter

Sym-

bol

name

A = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Value

Min Typ Max

MB90335 Series

Unit Remarks

Clock frequency f

Clock cycle time t

Input clock pulse width Input clock rise time and fall

time Internal operating clock

frequency Internal operating clock

cycle time

• Clock timing

CH X0, X1

6  24 MHz External clock input

 166.7  ns External crystal oscillation

 6  MHz External crystal oscillation

HCYL X0, X1

166.7  41.7 ns External clock input

P PWL

tcr

tcf

CP  3  24 MHz At main clock is used

CP  42  333 ns At main clock is used

X0 10 ns

X0  5 ns At external clock

tHCYL

A reference duty ratio is 30% to 70%.

0.8 VCC

0.2 VCC

PWH PWL

tcf

tcr

MB90335 Series

• PLL operation guarantee range Relation between internal operation clock frequency and power supply voltage

3.6

3.0

2.7

Power supply voltage VCC (V)

3 6 12 24

PLL operation guarantee range

Normal operation assurance range

Internal clock fCP (MHz)

* : When the USB is used, operation is guaranteed at voltages between 3.0 V to 3.6 V.

Relation between oscillation frequency and internal operation clock frequency

Internal clock fCP (MHz)

Multiply by 4

Multiply by 2

Multiply by 1

The AC standards provide that the following measurement reference voltages.

•

• Input signal waveform

Hysteresis input pin

Output signal waveform

Output pin

External clock

Oscillation clock FC (MHz)

0.8 VCC

0.2 VCC

Hysteresis input/other than MD input pin

0.7 V

0.3 VCC

2.4 V

0.8 V

MB90335 Series

(2) Reset

CC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Parameter

Reset input time

Sym-

bol

RSTL RST 

name

Condi-

tions

Oscillation time of

oscillator* + 500 ns

* : Oscillation time of oscillator is the time that the amplitude reaches 90 %. It takes sev eral milliseconds to several

dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a FAR/ceramic oscillator, and 0 milliseconds on an external clock.

• During normal operation, in time-base timer mode, in main sleep mode and in PLL sleep mode

Value

Unit Remarks

Min Max

500  ns

µs At stop mode

At normal operating, At time base timer mode, At main sleep mode, At PLL sleep mode

RST

• In stop mode

RST

Internal operation clock

90% of amplitude

tRSTL

0.2 VCC

tRSTL

0.2 VCC

Oscillation time

of oscillator

0.2 VCC

500 ns

Oscillation stabilization wait time

Internal reset

Execute instruction

MB90335 Series

(3) Power-on reset

Parameter Symbol Pin name

A = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Condi-

tions

Value

Unit Remarks

Min Max

Power supply rising time t Power supply shutdown time t

Notes : • V

CC must be lower than 0.2 V before the power supply is turned on.

• The above standard is a value for performing a power - on reset.

• In the device, there are internal registers which is initialized only by a power-on reset. When the initial

ization of these items is expected, turn on the power supply according to the standards.

VCC

Sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during operation as illustrated below, voltage fluctuation should be minimized so that the voltage rises as smoothly as possible. When raising the power, do not use PLL clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation.

VCC

3.0 V V

R VCC

 30 ms



OFF VCC 1  ms

2.7 V

0.2 V0.2 V t

0.2 V

OFF

The rising edge should be 50 mV/ms or less.

RAM data hold

For repeated operation

(4) UART0, UART1 I/O extended serial timing

Parameter

Serial clock cycle time t SCK ↓ → SOT delay time t

Valid SIN → SCK ↑ t SCK ↑ → valid

SIN hold time Serial clock H pulse width t Serial clock L pulse width t

SCK ↓ → SOT delay time t

Valid SIN → SCK ↑ t SCK ↑ → valid

SIN hold time

Sym-

bol

SCYC SCKx

SLOV

IVSH

SHIX

SHSL SCKx, SINx SLSH SCKx, SINx 4 tCP  ns

SLOV

IVSH

SHIX

Pin name Conditions

SCKx SOTx

SCKx

SINx

SCKx

SINx

SCKx SOTx

SCKx

SINx

SCKx

SINx

MB90335 Series

A = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Internal shiftc lock Mode output pin is C

L = 80 pF + 1 TTL

External shift clock Mode output pin is C

L = 80 pF + 1 TTL

Value

Min Max

CP  ns

8 t

− 80 80 ns

100  ns

60  ns

CP  ns

4 t

 150 ns

60  ns

Unit Remarks

Notes : • AC rating in CLK synchronous mode.

L is a load capacitance value on pins for testing.

• C

• t

CP is the machine cycle period (unit : ns) .

• Internal shift clock mode

SCK

SOT

SIN

• External shift clock mode

SCK

SOT

tSCYC

2.4 V

0.8 V 0.8 V tSLOV

2.4 V

0.8 V

tIVSH tSHIX

0.8 V

0.2 VCC

tSLSH tSHSL

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC tSLOV

2.4 V

0.8 V

0.8 VCC

0.2 VCC

SIN

tIVSH tSHIX

0.8 V

0.2 VCC

0.8 VCC

0.2 VCC

MB90335 Series

C timing

(5) I

Parameter

Sym-

bol

name

Condi-

tions

CC = 3.3 V ± 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Unit Remarks

Min Max

SCL clock frequency f Bus-free time between stop

and start conditions

SCL 

BUS  4.7 µs

0 100 kHz

Hold time (resend) start tHDSTA  4.0 µs SCL clock “L” status hold time t

SCL clock “H” status hold time t Resend start condition setup

time Data hold time t Data set-up time t

LOW  4.7 µs

HIGH  4.0 µs



tSUSTA  4.7 µs

HDDAT  0 µs SUDAT  40  ns

SDA and SCL signal rise time tR 1000 ns SDA and SCL signal fall time t Stop condition setup time t

0.8 VCC

SDA

tBUS

0.2 VCC

F 300 ns

SUSTO  4.0 µs

tR tF

tLOW tHIGH tHDSTA

The first clock pulse is generated immediately after the period.

SCL

0.8 VCC

0.2 VCC

tHDSTA tHDDAT tSUDAT tSUSTA tSUSTO

fSCL

(6) Timer Input Timing

Parameter Symbol Pin name

Input pulse width

PWC

(7) Timer output timing

Parameter

Condi-

tions

TIWH

tTIWL

0.8 VCC 0.8 VCC

PWC  4 tCP  ns

0.2 VCC 0.2 VCC

tTIWH tTIWL

Sym-

bol

Pin name

Condi-

MB90335 Series

A = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Value

Min Max

A = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Value

tions

Min Max

Unit Remarks

CLK ↑ → T

OUT change time

PPG0 to PPG3 change time

CLK

PPGx

(8) Trigger Input Timing

Parameter Symbol Pin name

Input pulse width

INTx

tTO PPGx  30  ns

2.4 V

0.8 V

Condi-

tions

TRGH

tTRGL

0.8 VCC 0.8 VCC

INTx 

0.2 VCC 0.2 VCC

A = −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Value

Unit Remarks

Min Max

5 t

CP  ns At normal operating

1 µs At Stop mode

tTRGH tTRGL

MB90335 Series

5. USB characteristics

Parameter Symbol

(TA = 0 °C to +70 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Sym

bol

Value

Unit Remarks

Min Max

Input High level voltage V

Input characteristics

Input Low level voltage V Differential input sensitivity V Differential common mode range VCM 0.8 2.5 V Output High level voltage V Output Low level voltage V Cross over voltage VCRS 1.3 2.0 V

Rise time Output characteristics

Fall time

Rising/falling time matching

Output registance Z

• Data signal timing (Full Speed)

DVP/HVP

DVM/HVM

Vcrs

Rise time

10%

IH 2.0  V

IL  0.8 V

DI 0.2  V

OH 2.8 3.6 V IOH = −200 µA OL 0.0 0.3 V IOL = 2 mA

FR 4 20 ns Full Speed

LR 75 300 ns Low Speed

tFF 4 20 ns Full Speed t

LF 75 300 ns Low Speed

RFM 90 111.11 % (TFR/TFF)

t tRLM 80 125 % (TLR/TLF)

DRV 28 44 Ω Including Rs = 27 Ω

Fall time

90%

10%

• Data signal timing (Low Speed)

HVP

HVM

Vcrs

tFR

Rise time

10%

tLR

90%

tFF

Fall time

90%

10%

tLF

• Load condition (Full Speed)

MB90335 Series

• Load condition (Low Speed)

HVP

HVM

DVP/HVP

DVM/HVM

RS = 27 Ω

Testing point

L = 50 pF

Testing point

L = 50 pF

Testing point

L = 50 pF ∼ 150 pF

Testing point

L = 50 pF ∼ 150 pF

MB90335 Series

ORDERING INFORMATION

■■■■

• MB90335 Series

Part number Package Remarks

MB90F337PFM MB90337PFM

64-pin plastic LQFP

(FPT-64P-M09)

PACKAGE DIMENSION

■■■■

MB90335 Series

64-pin plastic LQFP

(FPT-64P-M09)

14.00±0.20(.551±.008)SQ

12.00±0.10(.472±.004)SQ

INDEX

116

0.65(.026)

0.32±0.05

(.013±.002)

Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.

0.145±0.055

3348

0.13(.005)

(.0057±.0022)

0.10(.004)

"A"

Details of "A" part

+0.20 –0.10

1.50

+.008 –.004

.059

0.25(.010)

0~8˚

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

(Mounting height)

0.10±0.10

(.004±.004)

(Stand off)

2003 FUJITSU LIMITED F64018S-c-3-5

Dimensions in mm (inches) Note : The values in parentheses are reference values.

MB90335 Series

MEMO

MB90335 Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale , CA 94088-3470, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://www.fme.fujitsu.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220

http://www.fmal.fujitsu.com/

Korea

FUJITSU MICROELECTRONICS K OREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.

F0312

 FUJITSU LIMITED Printed in Japan

FUJITSU MB90335 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual