FUJITSU MB90233, MB90234, MB90P234, MB90W234 DATA SHEET
查询MB90W234ZFV供应商
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13504-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16F MB90230 Series
MB90233/234/P234/W234
DESCRIPTION
■
The MB90230 series is a member of general-purpose, 16-bit microcontrollers designed for those applications which
require high-speed realtimeprocessing, proving to be suitable for various industrial machines, camera and video
devices, OA equipment, and for process control. The CPU used in this series is the F
set for the F
architecture of the F
speed.
2
MC-16F CPU core is designed to be optimized for controller applications while inheriting the AT
2
MC-16/16H series, allowing a wide range of control tasks to be processed efficiently at high
2
MC*-16F. The instruction
The peripheral resources integrated in the MB90230 series include: the UART (clock asynchronous/synchronous
transfer) × 1 channel, the extended serial I/O interface × 1 channel, the A/D converter (8/10-bit precision) × 8
channels, the D/A converter (8-bit precision) × 2 channels, the level comparator × 1 channel, the external interrupt
input × 4 lines, the 8-bit PPG timer (PWM/single-shot function) × 1 channel, the 8-bit PWM controller × 6 channels,
the 16-bit free run timer × 1 channel, the input capture unit × 4 channels, the output compare unit × 6 channels,
and the serial E
2
*: F
MC stands for FUJITSU Flexible Microcontroller.
FEATURES
■
F2MC-16F CPU block
• Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz)
• Instruction set optimized for controllers
Various data types supported (bit, byte, word, and long-word)
Extended addressing modes: 23 types
High coding efficiency
Higher-precision operation enhanced by a 32-bit accumulator
Signed multiplication and division instructions
PACKAGE
■
2
PROM interface.
100-pin Plastic LQFP
(Continued)
100-pin Ceramic LQFP
(FPT-100P-M05)
(FPT-100C-C01)
MB90230 Series
(Continued)
• Enhanced instructions applicable to high-level language (C) and multitasking
System stack pointer
Enhanced pointer-indirect instructions
Barrel shift instructions
• Increased execution speed: 8-byte instruction queue
• 8-level, 32-factor powerful interrupt service functions
• Automatic transfer function independent of the CPU (EI
• General-purpose ports: Up to 84 lines
Ports with input pull-up resistor available: 24 lines
Ports with output open-drain available: 9 lines
Peripheral blocks
• ROM:48 Kbytes (MB90233)
96 Kbytes (MB90234)
EPROM: 96 Kbytes (MB90W234)
One-time PROM: 96 Kbytes (MB90P234)
• RAM:2 Kbytes (MB90233)
3 Kbytes (MB90234/W234/P234)
• PWM control circuit: (simple 8 bits): 6 channels
• Serial interface
UART: 1 channel
Extended serial I/O interface
Switchable I/O port: 1 channel
Communication prescaler (Source clock generator for the UART, serial I/O interface, CKOT, and level
comparator): 1 channel
• Serial E
• A/D converter with 8/10-bit resolution: input 8 channels
• Level comparator: 1 channel
4-bit D/A converter integrated
• D/A converter with 8-bit resolution: 2 channels
8-bit PPG timer: 1 channel
• Input/output timer
16-bit free run timer: 1 channel
16-bit output compare unit: 6 channels
16-bit input capture unit: 4 channels
• 18-bit timebase timer
• Watchdog timer function
• Standby modes
Sleep mode
Stop mode
2
PROM interface: 1 channel
2
OS)
2
PRODUCT LINEUP
■
MB90230 Series
Part number
Parameter
Classification
ROM size 48 Kbytes 96 Kbytes 96 Kbytes 96 Kbytes —
RAM size 2 Kbytes 3 Kbytes 3 Kbytes 3 Kbytes 4 Kbytes
CPU functions Number of instructions: 420
Ports Up to 84 lines
UART Number of channels: 1 (switchable I/O)
Serial interface Number of channels: 1
A/D converter Resolution: 10 or 8 bits, Number of input lines: 4
D/A converter Resolution: 8 bits, Number of output pins: 2
Level
comparator
PWM Number of channels: 6
PPG timer Number of channels: 1 channel with 8-bit resolution
Serial E
interface
Timer Number of channels: 6
Free run timer Number of channels: 1
External interrupt
input
Standby mode Stop mode and sleep mode
Package FPT-100P-M05 FPT-100C-C01 PGA256-A02
2
PROM
MB90233
Mask ROM products
Clock synchronous communication (2404 to 38460 bps, full-duplex double buffering)
Clock asynchronous communication (500K to 5M bps, full-duplex double buffering)
Clock synchronous transfer (62.5 kHz to 1 MHz, “LSB first” or “MSB first” transfer)
Single conversion mode (conversion for a specified input channel)
Scan conversion mode (continuous conversion for specified consecutive channels)
Continuous conversion mode (repeated conversion for a specified channel)
PWM function: Continuous output of pulse synchronous to trigger
Variable address length: 8 to 11 bits (with address increment function)
16-bit reload timer operation (operation clock cycle of 0.25 µs to 1.05 s)
NB90234 MB90P234 MB90W234 MB90V230
One-time PROM
model
Instruction bit length: 8 or 16 bits
Instruction length: 1 to 7 bytes
Data bit length: 1, 4, 8, 16, or 32 bits
Minimum execution time: 62.5 ns at 16 MHz (internal)
I/O ports (CMOS): 51
I/O ports (CMOS) with pull-up resistor available: 24
I/O ports (open-drain): 9
Internal or external clock mode
Stop conversion mode (periodical conversion)
Comparison to internal D/A converter (4-bit resolution)
8-bit PWM control circuit (operation of 1×φ, 2×φ, 16×φ, 32×φ)
Single-shot function: Output of single pulse by trigger
Number of channels: 1
Instruction code (NS type)
Variable data length: 8 or 16 bits
16-bit input capture unit: 4 channels
16-bit output compare unit: 6 channels
Number of input pins: 4
EPROM model
Evaluation
model
3
MB90230 Series
PIN ASSIGNMENT
■
P21/A01
P20/A00
P17/D15
P16/D14
P15/D13
P14/D12
(TOP VIEW)
P13/D11
P12/D10
P11/D09
P10/D08
P07/D07
P06/D06
P05/D05
P04/D04
P03/D03
P02/D02
CC
P01/D01
P00/D00
V
X1X0VSSP57
P56/RD
P55/WRL
P22/A02
P23/A03
P24/A04
P25/A05
P26/A06
P27/A07
P30/A08
P31/A09
V
P32/A10
P33/A11
P34/A12
P35/A13
P36/A14
P37/A15
PWM0/P40/A16
PWM1/P41/A17
PWM2/P42/A18
PWM3/P43/A19
PWM4/P44/A20
PWM5/P45/A21
V
TRG/P46/A22
PPG/P47/A23
ATG/P70
9998979695949392919089888786858483828180797877
100
1
2
3
4
5
6
7
8
9
SS
10
11
12
13
14
15
16
17
18
19
20
21
CC
22
23
24
25
26272829303132333435363738394041424344454647484950
P71/EDI
P72/EDO
P75/DA0
P73/ESK
P74/ECS
CC
AV
AVRH
P76/DA1
SS
AV
AVRL
P60/AN0
P61/AN1
P62/AN2
SS
V
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7/CMP
P80/INT0
MD0
MD1
P81/INT1
MD2
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
HST
RST
P54/WRH
P53/HRQ
P52/HAK
P51/RDY
P50/CLK
PA5/SCK2
PA4/SOT2
PA3/SIN2
PA2/SCK1
PA1/SOT1
PA0/SIN1
P96/SCK0
P95/SOT0
P94/SIN0
P93/IN3/CKOT
P92/IN2
P91/IN1
P90/IN0
P87/OUT5
P86/OUT4
P85/OUT3
P84/OUT2
P83/OUT1/INT3
P82/OUT0/INT2
(FPT-100P-M05)
(FPT-100C-C01)
4
PIN DESCRIPTION
■
MB90230 Series
Pin no. Pin name
80 X0 A Oscillator pins
81 X1
82 V
83 to 90 P00 to P07 G General-purpose I/O port
91 to 98 P10 to P17 G General-purpose I/O port
99, 100
1 to 6
CC — Power supply pin
D00 to D07 I/O pins for the lower eight bits of the external data bus.
D08 to D15 I/O pins for the upper eight bits of the external data bus
P20 to P27 G General-purpose I/O port
A00 to A07 I/O pins for the lower eight bits of the external data bus
Circuit
type
An input pull-up resistor can be added to the port by setting the
pull-up resistor setting register.
These pins serve as D00 to D07 pins in bus modes other than the
single-chip mode.
These pins are enabled in an external-bus enabled mode.
An input pull-up resistor can be added to the port by setting the pull-up
resistor setting register.
These pins are enabled in the single-chip mode with the external-bus
enabled and the 8-bit data bus specified.
These pins are enabled in an external-bus enabled mode with the 16bit data bus specified.
An input pull-up resistor can be added to the port by setting the
pull-up resistor setting register.
These pins are enabled in the single-chip mode.
These pins are enabled in an external-bus enabled mode.
Function
7, 8 P30, P31 E General-purpose I/O port
This port is enabled in the single-chip mode or when the middle
address control register setting is “port.”
A08, A09 I/O pins for the middle eight bits of the external data bus
These pins are enabled in an external-bus enabled mode when the
middle address control register setting is “address.”
9V
10 to 15 P32 to P37 E General-purpose I/O port
SS — Power supply pin
This port is enabled in the single-chip mode or when the middle
address control register setting is “port.”
A10 to A15 I/O pins for the middle eight bits of the external data bus
These pins are enabled in an external-bus enabled mode when the
middle address control register setting is “address.”
(Continued)
5
MB90230 Series
Pin no. Pin name
16 P40 E General-purpose I/O port
A16 Output pin for external address A16
PWM0 This pin serves as the output pin for 8-bit PWM0
17 P41 E General-purpose I/O port
A17 Output pin for external address A17
PWM1 This pin serves as the output pin for 8-bit PWM1.
Circuit
type
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
The pin is enabled for output by the control status register.
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
The pin is enabled for output by the control status register.
Function
18 P42 E General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A18 Output pin for external address A18
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM2 This pin serves as the output pin for 8-bit PWM2.
This pin is enabled for output by the control status register.
19 P43 E General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A19 Output pin for external address A19
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM3 This pin serves as the output pin for 8-bit PWM3.
This pin is enabled for output by the control status register.
20 P44 E General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A20 Output pin for external address A20
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM4 This pin serves as the output pin for 8-bit PWM4.
The pin is enabled for output by the control status register.
21 V
CC — Power supply pin
(Continued)
6
Pin no. Pin name
22 P45 E General-purpose I/O port
A21 Output pin for external address A21
PWM5 This pin serves as the output pin for 8-bit PWM5.
23 P46
A22 Output pin for external address A22
TRG This pin serves as the external trigger pin for the 8-bit PPG timer
Circuit
type
1
L*
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
The pin is enabled for output by the control status register.
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
The pin is enabled for triggering by the control status register.
MB90230 Series
Function
24 P47 E General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A23 Output pin for external address A23
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PPG This pin serves as the output pin for the 8-bit PPG timer.
The pin is enabled for output by the control status register.
25 P70
ATG External trigger input pin for the A/D converter
26 P71 F General-purpose I/O port
EDI Data input pin for the serial EEPROM interface
27 P72 E General-purpose I/O port
EDO Data output pin for the serial EEPROM interface
28 P73 E General-purpose I/O port
ESK Clock output pin for the serial EEPROM interface
29 P74 E General-purpose I/O port
ECS Chip select signal output pin for the serial EEPROM interface
L*
1
General-purpose I/O port
This pin functions when enabled by the control status register.
This pin functions when enabled by the control status register.
This pin functions when enabled by the control status register.
This pin functions when enabled by the control status register.
This pin functions when enabled by the control status register.
(Continued)
7
MB90230 Series
Pin no. Pin name
Circuit
type
30, 31 P75, P76 K General-purpose I/O port
DA0
DA1
32 AV
33 AV
34 AV
35 AV
CC — A/D converter power supply pin
RH — “H” reference power supply pin for the A/D converter
RL — “L” reference power supply pin for the A/D converter
SS — A/D converter power pin (GND)
This pin serves as the D/A converter output pin.
The pin functions when enabled by the control status register.
36 to 39 P60 to P63 J General-purpose I/O port
This port is enabled when the analog input enable register setting is
“port.”
AN0 to AN3 A/D converter analog input pins
These pins are enabled when the analog input enable register setting
is “analog input.”
40 V
SS — Power pin (GND)
41 to 43 P64 to P66 J General-purpose I/O port
This port is enabled when the analog input enable register setting is
“port.”
AN4 to AN6 A/D converter analog input pins
These pins are enabled when the analog input enable register setting
is “analog input.”
44 P67 J General-purpose I/O port
This port is enabled when the analog input enable register setting is
“port.”
AN7 A/D converter analog input pin
This pin is enabled when the analog input enable register setting is
“analog input.”
CMP Comparator input pin
2
45 P80
L*
General-purpose I/O port
This port is always enabled.
INT0 External interrupt request input 0
Since this pin serves for interrupt request as required when external
interrupt is enabled, other outputs must be off unless used
intentionally.
2
46 P81
L*
General-purpose I/O port
This port is always enabled.
INT1 External interrupt request input 1
Since this pin serves for interrupt request as required when external
interrupt is enabled, other outputs must be off unless used
intentionally.
47 MD0 C Mode pin
This pin must be fixed to V
48 MD1 C Mode pin
This pin must be fixed to V
Function
CC or VSS.
CC or VSS.
(Continued)
8
MB90230 Series
Pin no. Pin name
Circuit
type
49 MD2 C Mode pin
This pin must be fixed to V
50 HST
51, 52 P82, P83
OUT0,
OUT1
INT2,
INT3
D Hardware standby input pin
2
L*
General-purpose I/O port
Output compare output pins
These pins function when enabled by the control status register.
External interrupt request inputs 2 and 3.
Since these pins serve for interrupt request as required when external
interrupt is enabled, other outputs must be off unless used
intentionally.
53 to 56 P84 to P87 E General-purpose I/O port
This pin is always enabled.
OUT2 to OUT5 Output compare output pins
These pins function when enabled by the control status register.
1
57 to 59 P90 to P92
L*
General-purpose I/O port
This port is always enabled.
IN0 to IN2 Input capture edge input pins
These pins function when enabled by the control status register.
1
60 P93
L*
General-purpose I/O port
This port is always enabled.
IN3 Input capture edge input pin
This pin functions when enabled by the control status register.
CKOT Prescaler output pin
This pin functions when enabled by the control status register.
61 P94 I General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SIN0 Serial data input pin for the UART
This pin functions when enabled by the control status register.
62 P95 H General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SOT0 Serial data output pin for the UART
This pin functions when enabled by the control status register.
63 P96 I General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SCK0 UART clock output pin
This pin functions when enabled by the control status register.
Function
SS.
(Continued)
9
MB90230 Series
Pin no. Pin name
64 PA0 I General-purpose I/O port
SIN1 Serial data input pin for the extended serial I/O interface
65 PA1 H General-purpose I/O port
SOT1 Serial data output pin for the extended serial I/O interface
66 PA2 I General-purpose I/O port
SCK1 Clock output pin for the extended serial I/O interface
67 PA3 I General-purpose I/O port
SIN2 Serial data input pin for the extended serial I/O interface
68 PA4 H General-purpose I/O port
SOT2 Serial data output pin for the extended serial I/O interface
69 PA5 I General-purpose I/O port
SCK2 Clock output pin for the extended serial I/O interface
Circuit
type
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
This pin functions when enabled by the control status register and by
the serial port switching register.
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
This pin functions when enabled by the control status register and by
the serial port switching register.
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
This pin functions when enabled by the control status register and by
the serial port switching register.
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
This pin functions when enabled by the control status register and by
the serial port switching register.
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
This pin functions when enabled by the control status register and by
the serial port switching register.
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
This pin functions when enabled by the control status register and by
the serial port switching register.
The pin is a general-purpose I/O port.
Function
(Continued)
10
(Continued)
MB90230 Series
Pin no. Pin name
70 P50 H This pin is enabled in the single-chip mode and when the CLK output
CLK CLK output pin
71 P51 F General-purpose I/O port
RDY Ready signal input pin
72 P52 E General-purpose I/O port
HAK
73 P53 E General-purpose I/O port
HRQ Hold acknowledge signal output pin
74 P54 E General-purpose I/O port
WRH
75 RST
76 P55 E This port is enabled in the single-chip mode, in external-bus 8-bit
WRL
77 P56 E This pin is enabled in the single-chip mode.
RD
78 P57 E General-purpose I/O port
79 V
SS — Power pin (GND)
Circuit
type
is disabled.
This pin is enabled in an external-bus enabled mode with the CLK
output enabled.
This port is enabled in the single-chip mode.
This pin is enabled in an external-bus enabled mode.
This port is enabled in the single-chip mode or when the hold function
is disabled.
Hold acknowledge signal output pin
This pin is enabled in the single-chip mode or when the hold function
is enabled.
This port is enabled in the single-chip mode or when the hold function
is disabled.
This pin is enabled in the single-chip mode or when the hold function
is enabled.
This port is enabled in the single-chip mode, in external-bus 8-bit
mode, or when the WR pin output is disabled.
Write strobe output pin for the upper eight bits of the data bus
This pin is enabled in an external-bus enabled mode and in external
bus 16-bit mode with the WR pin output enabled.
B Reset signal input pin
mode, or when the WR pin output is disabled
Write strobe output pin for the lower eight bits of the data bus
This pin is enabled in an external-bus enabled mode and in external
bus 16-bit mode with the WR pin output enabled.
The pin is a general-purpose I/O port.
Read strobe output pin for the data bus
This pin is enabled in an external-bus enabled mode.
Function
*1: Enabled in any standby mode
*2: Enabled only in the hardware standby mode
11
MB90230 Series
I/O CIRCUIT TYPE
■
Type Circuit Remarks
A • Oscillation feedback resistor:
Approx. 1 MΩ
X1
X0
Standby control
B • Hysteresis input with pull-up
resistor
C•CMOS input port
D • Hysteresis input port
E • CMOS level output
CMOS
Standby control
12
(Continued)
MB90230 Series
Type Circuit Remarks
F • CMOS level output
• Hysteresis input
Standby control
G • Input pull-up resistor control
provided
Pull-up control
• CMOS level input/output
CMOS
Standby control
H • CMOS level input/output
• Open-drain control provided
Open-drain control signal
CMOS
Standby control
(Continued)
13
MB90230 Series
(Continued)
Type Circuit Remarks
I • CMOS level output
Open-drain control signal
CMOS
Standby control
J • CMOS level input/output
• Hysteresis input
• Open-drain control provided
• Analog input
Analog input
CMOS
Standby control
K • CMOS level input/output
• Analog output
• Also serving for D/A output
DA output
CMOS
Standby control
L • CMOS level output
Open-drain control signal
• Hysteresis input
• Open-drain control provided
14
Standby control
MB90230 Series
HANDLING DEVICES
■
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage wihich shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between V
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
CC and VSS.
Also, tak e care to pre v ent the analog po wer supply (AV
CC and A VR) and analog input from e xceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. External Reset Input
To reset the internal circuit by the Low-level input to the RST pin, the Low-level input to the RST pin must be
maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.
4. VCC and VSS Pins
Apply equal potential to the VCC and VSS pins.
5. Notes on Using an External Clock
When using an external clock, drive the X0 pin as illustrated below:
Use of External Clock
MB90234
X0
X1
6. Power-on Sequence for A/D Converter Power Supplies and Analog Inputs
Be sure to turn on the digital power supply (VCC) before applying voltage to the A/D converter power supplies
(AV
CC, AVRH, and AVRL) and analog inputs (AN0 to AN15).
When turning power supplies off, turn off the A/D converter power supplies (AV
CC, AVRH, and AVRL) and analog
inputs (AN0 to AN15) first, then the digital power supply (AVCC).
When turning AVRH on or off, be careful not to let it exceed AV
CC.
7. Pin set when turning on power supplies
When turning on power supplies, set the hardware standby input pin (HST) to “H”.
15
MB90230 Series
8. Program Mode
When shipped from Fujitsu, and after each erasure, all bits (96K × 8 bits) in the MB90W234 and MB90P234 are
in the “1” state. Data is introduced by selectively programming “0’s” into the desired bit locations. Bits cannot
be set to 1 electrically.
9. Erasure Procedure
Data written in the MB90W234 is erased (from 0 to 1) by exposing the chip to ultraviolet rays with a wavelength
of 2,537Å through the translucent cover.
2
Recommended irradiation dosage for exposure is 10 Wsec/cm
with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface
illuminance is 1200 µW/cm
If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the lamp
increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent
part of the package is stained with oil or adhesive, transmission of ultraviolet rays is degraded, resulting in a
longer erasure time. In that case, clean the translucent part using alcohol (or other solvent not affecting the
package).
2
).
. This amount is reached in 15 to 20 minutes
The above recommended dosage is a value which takes the guard band into consideration and is a multiple of
the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure;
the purpose of the guard band is to ensure erasure in all temperature and supply voltage ranges. In addition,
check the lifespan of the lamp and control the illuminance appropriately.
Data in the MB90W234 is erased by exposure to light with a wavelength of 4000Å or less.
Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure
results in a much lower erasure rate than exposure to 2537Å ultraviolet rays. Note that exposure to such lights
for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light
with a wavelength of 4000Å or less, cover the translucent part, for example, with a protective seal to prevent
the chip from being exposed to the light.
Exposure to light with a wavelength of 4,000 to 5,000Å or more will not erase data in the device. If the light
applied to the chip has a very high illuminance, however, the device may cause malfunction in the circuit for
reasons of general semiconductor characteristics. Although the circuit will recover normal operation when
exposure is stopped, the device requires proper countermeasures for use in a place exposed continuously to
such light even though the wavelength is 4,000Å or more.
16
MB90230 Series
10. Recommended Screening Conditions
High-temperature aging is recommended for screening before packaging.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
11. Write Yield
OTPROM products cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always
be guaranteed to be 100%.
17
MB90230 Series
BLOCK DIAGRAM
■
X0, X1
RST
HST
SIN0
SOT0
SCK0
CKOT
SIN1, 2
SOT1, 2
SCK1, 2
AVcc
AVRH, AVRL
AVss
ATG
AN0 to AN7
4
Clock controller
Communication prescaler
Extended serial
I/O interface
10-bit A/D converter
RAM
ROM
UART
CPU
F2MC-16F
MC-16 bus
2
F
Interrupt controller
External interrupt
8-bit PWM
6 ch
8-bit PPG timer
I/O timer
16-bit input capture × 4
16-bit free run timer
16-bit output compare × 6
Serial E
2
PROM interface
4
2
INT0
to
INT3
PWM0
to
PWM5
TRG
PPG
IN0, 1
IN2, 3
OUT0, 1
OUT2, 3
OUT4, 5
ECS, ESK
EDO
EDI
18
DA0
DA1
D/A converter
I/O ports (84 lines)
8 8 8 8 8 8 8 78
P00
P10
P20
P30
P40
P50
P60
to
P07
to
P17
to
P27
to
P37
to
P47
to
P57
to
P67
P70
to
P76
Level comparator
7
P80
P90
to
to
P87
P96
6
PA0
to
PA5
P00 to P27 (24 lines): Provided with input pull-up resistor setting registers
P94 to P96, PA0 to PA5 (9 lines): Provided with open-drain setting registers
CMP
MEMORY MAP
■
MB90230 Series
FFFFFFH
Address1#
00FFFFH
Address#2
Address#3
000100
0000C0H
000000H
Single-chip mode
ROM area
ROM area
(FF bank image)
RAM
H
Peripherals Peripherals Peripherals
Registers
Internal ROM and
external bus
ROM area
ROM area
(FF bank image)
RAM
Registers
External ROM and
external bus
RAM
Registers
Internal External Inhibited area
000000H to 000005H and 000010H to 000015H are allocated for external use
Note:
when the external bus is enabled.
Address#3
000900H
MB90233
FF4000
Address#2Address#1Product type
H
004000H
MB90234
MB90P234
MB90W234
MB90V230
FE8000
H
FE8000H
(FE0000H)
004000
004000H
(004000H)
H
000D00
H
000D00H
(001100H)
The MB90230 series can access the 00 bank to read ROM data written to the upper 48-KB locations in the FF
bank. An advantage of reading written to data addresses FFFFFF
H-FF4000H from addresses 00FFFFH-004000H is
that you can use the small model of a C compiler.
Note, however, that the products with more than 48KB ROM space (MB90V230, MB90P/W234, MB90234) cannot
read data in addresses other than FFFFFF
H to FF4000H from the 00 bank.
19
MB90230 Series
I/O MAP
■
Address Register
00
H Port 0 data register PDR0 R/W Port 0 XXXXX X X X
01
H Port 1 data register PDR1 R/W Port 1 XXXXX X X X
Register
name
Access
Resouce
name
Initial value
02H Port 2 data register PDR2 R/W Port 2 XXXXX X X X
03
H Port 3 data register PDR3 R/W Port 3 XXXXX X X X
04
H Port 4 data register PDR4 R/W Port 4 XXXXX X X X
05H Port 5 data register PDR5 R/W Port 5 XXXXX X X X
06
H Port 6 data register PDR6 R/W Port 6 XXXXX X X X
07
H Port 7 data register PDR7 R/W Port 7 – XXXX X X X
08H Port 8 data register PDR8 R/W Port 8 XXXXX X X X
09
H Port 9 data register PDR9 R/W Port 9 – XXXX X X X
0A
H Port A data register PDRA R/W Port A – – XXXXXX
10H Port 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0
11
H Port 1 direction register DDR1 R/W Port 1 0 0 0 0 0 0 0 0
12
H Port 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 0 0
13H Port 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0
14
H Port 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0
15
H Port 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0
16
H Port 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0
17H Port 7 direction register DDR7 R/W Port 7 – 0 0 0 0 0 0 0
18
H Port 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0
19
H Port 9 direction register DDR9 R/W Port 9 – 0 0 0 0 0 0 0
1AH Port A direction register DDRA R/W Port A – – 0 0 0 0 0 0
1B
H Port 0 resistor register RDR0 R/W Port 0 0 0 0 0 0 0 0 0
1C
H Port 1 resistor register RDR1 R/W Port 1 0 0 0 0 0 0 0 0
1DH Port 2 resistor register RDR2 R/W Port 2 0 0 0 0 0 0 0 0
1E
H Port 9 pin register ODR9 R/W Port 9 – 0 0 0 – – – –
1F
H Port A pin register ODRA R/W Port A – – 0 0 0 0 0 0
20H Mode control register UMC R/W UART 0 0 0 0 0 1 0 0
21
H Status register USR R/W 0 0 0 1 0 0 0 0
22
H Serial input register
/Serial output register
H Rate and data register URD R/W 0 0 0 0 – – 0 0
23
24
H Serial mode control status register SMCS R/W
25
H 00000010
UIDR
/UODR
R/W
Extended serial
I/O interface
XXXXXXXX
–––00000
20
(Continued)
MB90230 Series
Address Register
26
H Serial data register SDR R/W Extended serial
Register
name
Access
Resouce
name
Initial value
XXXXXXXX
I/O interface
27
H Reserved area — — — —
28
H Cycle setting register PCSR W 8-bit
29
H Duty factor setting register PDUT W XXXX X X X X
PPG timer
XXXXXXXX
2AH Control status register PCNTL R/W 00000000
2B
H PCNTH 0000000–
2C
H Reserved area — — — —
2DH Communication prescaler CDCR R/W UART, CKOT,
0–––1111
I/O, serial IF
2E
H Clock control register CLKR R/W CKOT output – – – – – 0 0 0
2F
H Level comparator LVLC R/W Level
XXXX00 00
comparator
30
H Interrupt/DTP enable register ENIR R/W DTP/external
31
H Interrupt/DTP factor register EIRR R/W – – – – 0 0 0 0
32
H Request level setting register ELVR R/W 0 0 0 0 0 0 0 0
interrupt
––––0000
33H Reserved area — — — —
34
H Analog input enable register ADER R/W 10-bit A/D
35
H Reserved area — — —
36
H Control status data register ADCS0 R/W 0 0 0 0 0 0 0 0
converter
11111111
37H ADCS1 00000000
38
H Data register ADCR0 R XXXXXXXX
39
H ADCR1 000000XX
3AH Reserved area — — — —
3B
H Reserved area — — — —
3C
H D/A converter data register 0 DAT0 R/W 8-bit D/A
3DH D/A converter data register 1 DAT1 R/W 0 0 0 0 0 0 0 0
3E
H D/A control register DACR R/W ––––––00
3F
H Reserved area — — — —
converter
40H PWM data register 0 PWD0 R/W 8-bit
41
H PWM data register 1 PWD1 R/W 0 0 0 0 0 0 0 0
42
H Control status data register 0, 1 PWC01 R/W 0 0 0 0 0 0 0 0
43
H Reserved area — — — —
PWM0, 1
44H PWM data register 2 PWD2 R/W 8-bit
45
H PWM data register 3 PWD3 R/W 0 0 0 0 0 0 0 0
PWM2, 3
XXXXXXXX
00000000
00000000
46
H Control status register 2, 3 PWC23 R/W 0 0 0 0 0 0 0 0
(Continued)
21
MB90230 Series
Address Register
47
H Reserved area — — — —
48
H PWM data register 4 PWD4 R/W 8-bit
49
H PWM data register 5 PWD5 R/W 0 0 0 0 0 0 0 0
Register
name
Access
Resouce
name
PWM4, 5
Initial value
00000000
4AH Control status register 4, 5 PWC45 R/W 0 0 0 0 0 0 0 0
4B
H Reserved area — — — —
4C
H Data register TCDT R 16-bit free
4DH 00000000
4E
H Control status register TCCS R/W 0 0 0 0 0 0 0 0
4F
H Reserved area — — — —
run timer
50H Compare register 0 OCP0 R/W Output
51
H XXXXXXXX
52
H Compare register 1 OCP1 R/W XXXXXXXX
compare 0, 1
00000000
XXXXXXXX
53H XXXXXXXX
54
H Control status register 0, 1 CS00 R/W 0 0 0 0 – – 0 0
55
H CS01 –––00000
56H Reserved area — — — —
57
H Reserved area — — — —
58
H Compare register 2 OCP2 R/W Output
59
H XXXXXXXX
compare 2, 3
XXXXXXXX
5AH Compare register 3 OCP3 R/W XXXXXXXX
5B
H XXXXXXXX
5C
H Control status register 2, 3 CS10 R/W 0 0 0 0 – – 0 0
5DH CS11 –––00000
5E
H Reserved area — — — —
5F
H Reserved area — — — —
60H Compare register 4 OCP4 R/W Output
61
H XXXXXXXX
62
H Compare register 5 OCP5
compare 4, 5
XXXXXXXX
XXXXXXXX
R/W
63H XXXXXXXX
64
H
Control status register 4, 5
H CS21 –––00000
65
66
H Reserved area — — — —
67H to
6F
H
Reserved area
CS20
0000––00
R/W
—— — —
(Continued)
22
MB90230 Series
Address Register
70
H Capture register 0 ICP0 R/W Input capture 0,
71
H XXXXXXXX
72
H Capture register 1 ICP1 R/W XXXXXXXX
Register
name
Access
1
Resouce
name
Initial value
XXXXXXXX
73H XXXXXXXX
74
H Control status register 0, 1 ICS0 R/W 0 0 0 0 0 0 0 0
75
H to
Reserved area — — — —
77H
78
H Capture register 2 ICP2 R/W Input capture 2,
79
H XXXXXXXX
3
XXXXXXXX
7AH Capture register 3 ICP3 R/W XXXXXXXX
7B
H XXXXXXXX
7C
H Control status register 2, 3 ICS1 R/W 0 0 0 0 0 0 0 0
7DH to
7F
H
80
H OP code register EOPC R/W
H Format status register ECTS R/W 0 0 0 0 0 0 0 0
81
82
H Data register EDAT R/W XXXXXXXX
Reserved area — — — —
Serial E
2
PROM
––––0000
interface
83
H XXXXXXXX
84
H Address register EADR R/W 0 0 0 0 0 0 0 0
85H 00–––000
86
H to
8F
H
90
H to
9E
H
9F
H Delayed interrupt source generate/
A0
H Standby control register STBYC R/W Low-power
Reserved area — — — —
System reserved area — *1 — —
release register
DIRR R/W Del ay e d i n t e r ru p t
generation module
–––––––0
0001XXXX
consumption
mode
A1
H Reserved area — — — —
A2
H Reserved area — — — —
A3H Middle address control register MACR W External pin *2
A4
H Upper address control register HACR W External pin *2
A5
H External pin control register EPCR W External pin *2
A6
H Reserved area — — — —
A7H Reserved area — — — —
A8
H Watchdog timer control register TWC R/W Watchdog timer/
reset
XXXXXXXX
(Continued)
23
MB90230 Series
Address Register
A9
H Timebase timer control register TBTC R/W Timebase
Register
name
Access
Resouce
name
Initial value
–––00000
timer
AA
H to
Reserved area — — — —
AFH
B0
H Interrupt control register 00 ICR00 R/W Interrupt
B1
H Interrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1
controller
00000111
B2H Interrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1
B3
H Interrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1
B4
H Interrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1
B5H Interrupt control register 05 ICR05 R/W 0 0 0 0 0 1 1 1
B6
H Interrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1
B7
H Interrupt control register 07 ICR07 R/W 0 0 0 0 0 1 1 1
B8H Interrupt control register 08 ICR08 R/W 0 0 0 0 0 1 1 1
B9
H Interrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1
BA
H Interrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1
BBH Interrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1
BC
H Interrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1
BD
H Interrupt control register 13 ICR13 R/W 0 0 0 0 0 1 1 1
BE
H Interrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1
BFH Interrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1
C0
FF
H to
H
External area — — — *3
Initial values
0: The initial value for the bit is “0.”
1: The initial value for the bit is “1.”
X: The initial value for the bit is undefined.
–: The bit is not used; the initial value is undefined.
*1: Access inhibited
*2: The initial value depends on each bus mode.
*3: Only this area can be used as the external access area in the area that follows address 0000FF
H. Access to
any address in reserved areas specified in the I/O map table is handled as access to an internal area. An
access signal to the external bus is not generated.
24
MB90230 Series
INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS FOR INTERRUPT
■
SOURCES
Interrupt control
register
Interrupt source
2
OS
I
support
Interrupt vector
No. Address ICR Address
Reset × #08 08
H FFFFDCH ——
INT9 instruction × #09 09H FFFFD8H ——
Exceptional × #10 0A
External interrupt (INT0) 0 ch #11 0B
H FFFFD4H ——
H FFFFD0H
ICR00 0000B0H
External interrupt (INT1) 1 ch #12 0CH FFFFCCH
External interrupt (INT2) 2 ch #13 0DH FFFFC8H
ICR01 0000B1H
External interrupt (INT3) 3 ch #14 0EH FFFFC4H
Extended serial I/O interface #15 0FH FFFFC0H
Serial E2PROM interface
#17 11
H FFFFB8H ICR03
Input capture channel 0 #19 13H FFFFB0H
Input capture channel 1 #21 15H FFFFA8H ICR05
Input capture channel 2 #23 17H FFFFA0H
Input capture channel 3
#24 18
H FFFF9CH
Output compare channel 0 #25 19H FFFF98H
ICR02 0000B2H
0000B3
ICR04 0000B4H
0000B5
ICR06 0000B6H
ICR07 0000B7H
H
H
Output compare channel 1 #26 1AH FFFF94H
Output compare channel 2 #27 1BH FFFF90H
ICR08 0000B8H
Output compare channel 3 #28 1CH FFFF8CH
Output compare channel 4 #29 1DH FFFF88H
ICR09 0000B9H
Output compare channel 5 #30 1EH FFFF84H
16-bit free run timer overflow #31 1FH FFFF80H
ICR10 0000BAH
Timebase timer overflow #32 20H FFFF7CH
8-bit PPG timer #33 21H FFFF78H
ICR11 0000BBH
Level comparator #34 22H FFFF74H
UART reception #35 23H FFFF70H ICR12
UART transmission #37 25H FFFF68H
ICR13 0000BDH
End of A/D conversion #39 27H FFFF60H ICR14
0000BC
0000BE
H
H
Delayed interrupt × #42 2AH FFFF54H ICR15 0000BFH
Stack fault × #256 FFH FFFC00H ——
: The request flag is cleared by the EI2OS interrupt clear signal.
: The request flag is cleared by the EI
: The request flag is not cleared by the EI
2
OS interrupt clear signal. The stop request is available.
2
OS interrupt clear signal.
25
MB90230 Series
PERIPHERAL RESOURCES
■
1. I/O Ports
Each pin in each port can be specified for input or output by setting the direction register when the corresponding
peripheral resource is not set to use that pin. When the data register is read, the value depending on the pin
level is read whenever the pin serves for input. When the data register is read with the pin serving for output,
the latch value of the data register is read. This also applies to read operation by the read modify write instruction.
• General-purpose I/O port
Data register read
Data register
Data register write
Internal data bus
Direction register write
Direction register read
Direction register
• Port with pull-up resistor setting register
Data register
Pin
Pull-up resistor (Approx. 50 kΩ)
Port input/output
26
Direction register read
Internal data bus
Resistor register
Loading...