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FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13504-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16F MB90230 Series
MB90233/234/P234/W234
DESCRIPTION
■
The MB90230 series is a member of general-purpose, 16-bit microcontrollers designed for those applications which
require high-speed realtimeprocessing, proving to be suitable for various industrial machines, camera and video
devices, OA equipment, and for process control. The CPU used in this series is the F
set for the F
architecture of the F
speed.
2
MC-16F CPU core is designed to be optimized for controller applications while inheriting the AT
2
MC-16/16H series, allowing a wide range of control tasks to be processed efficiently at high
2
MC*-16F. The instruction
The peripheral resources integrated in the MB90230 series include: the UART (clock asynchronous/synchronous
transfer) × 1 channel, the extended serial I/O interface × 1 channel, the A/D converter (8/10-bit precision) × 8
channels, the D/A converter (8-bit precision) × 2 channels, the level comparator × 1 channel, the external interrupt
input × 4 lines, the 8-bit PPG timer (PWM/single-shot function) × 1 channel, the 8-bit PWM controller × 6 channels,
the 16-bit free run timer × 1 channel, the input capture unit × 4 channels, the output compare unit × 6 channels,
and the serial E
2
*: F
MC stands for FUJITSU Flexible Microcontroller.
FEATURES
■
F2MC-16F CPU block
• Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz)
• Instruction set optimized for controllers
Various data types supported (bit, byte, word, and long-word)
Extended addressing modes: 23 types
High coding efficiency
Higher-precision operation enhanced by a 32-bit accumulator
Signed multiplication and division instructions
PACKAGE
■
2
PROM interface.
100-pin Plastic LQFP
(Continued)
100-pin Ceramic LQFP
(FPT-100P-M05)
(FPT-100C-C01)
MB90230 Series
(Continued)
• Enhanced instructions applicable to high-level language (C) and multitasking
System stack pointer
Enhanced pointer-indirect instructions
Barrel shift instructions
• Increased execution speed: 8-byte instruction queue
• 8-level, 32-factor powerful interrupt service functions
• Automatic transfer function independent of the CPU (EI
• General-purpose ports: Up to 84 lines
Ports with input pull-up resistor available: 24 lines
Ports with output open-drain available: 9 lines
Peripheral blocks
• ROM:48 Kbytes (MB90233)
96 Kbytes (MB90234)
EPROM: 96 Kbytes (MB90W234)
One-time PROM: 96 Kbytes (MB90P234)
• RAM:2 Kbytes (MB90233)
3 Kbytes (MB90234/W234/P234)
• PWM control circuit: (simple 8 bits): 6 channels
• Serial interface
UART: 1 channel
Extended serial I/O interface
Switchable I/O port: 1 channel
Communication prescaler (Source clock generator for the UART, serial I/O interface, CKOT, and level
comparator): 1 channel
• Serial E
• A/D converter with 8/10-bit resolution: input 8 channels
• Level comparator: 1 channel
4-bit D/A converter integrated
• D/A converter with 8-bit resolution: 2 channels
8-bit PPG timer: 1 channel
• Input/output timer
16-bit free run timer: 1 channel
16-bit output compare unit: 6 channels
16-bit input capture unit: 4 channels
• 18-bit timebase timer
• Watchdog timer function
• Standby modes
Sleep mode
Stop mode
2
PROM interface: 1 channel
2
OS)
2
PRODUCT LINEUP
■
MB90230 Series
Part number
Parameter
Classification
ROM size 48 Kbytes 96 Kbytes 96 Kbytes 96 Kbytes —
RAM size 2 Kbytes 3 Kbytes 3 Kbytes 3 Kbytes 4 Kbytes
CPU functions Number of instructions: 420
Ports Up to 84 lines
UART Number of channels: 1 (switchable I/O)
Serial interface Number of channels: 1
A/D converter Resolution: 10 or 8 bits, Number of input lines: 4
D/A converter Resolution: 8 bits, Number of output pins: 2
Level
comparator
PWM Number of channels: 6
PPG timer Number of channels: 1 channel with 8-bit resolution
Serial E
interface
Timer Number of channels: 6
Free run timer Number of channels: 1
External interrupt
input
Standby mode Stop mode and sleep mode
Package FPT-100P-M05 FPT-100C-C01 PGA256-A02
2
PROM
MB90233
Mask ROM products
Clock synchronous communication (2404 to 38460 bps, full-duplex double buffering)
Clock asynchronous communication (500K to 5M bps, full-duplex double buffering)
Clock synchronous transfer (62.5 kHz to 1 MHz, “LSB first” or “MSB first” transfer)
Single conversion mode (conversion for a specified input channel)
Scan conversion mode (continuous conversion for specified consecutive channels)
Continuous conversion mode (repeated conversion for a specified channel)
PWM function: Continuous output of pulse synchronous to trigger
Variable address length: 8 to 11 bits (with address increment function)
16-bit reload timer operation (operation clock cycle of 0.25 µs to 1.05 s)
NB90234 MB90P234 MB90W234 MB90V230
One-time PROM
model
Instruction bit length: 8 or 16 bits
Instruction length: 1 to 7 bytes
Data bit length: 1, 4, 8, 16, or 32 bits
Minimum execution time: 62.5 ns at 16 MHz (internal)
I/O ports (CMOS): 51
I/O ports (CMOS) with pull-up resistor available: 24
I/O ports (open-drain): 9
Internal or external clock mode
Stop conversion mode (periodical conversion)
Comparison to internal D/A converter (4-bit resolution)
8-bit PWM control circuit (operation of 1×φ, 2×φ, 16×φ, 32×φ)
Single-shot function: Output of single pulse by trigger
Number of channels: 1
Instruction code (NS type)
Variable data length: 8 or 16 bits
16-bit input capture unit: 4 channels
16-bit output compare unit: 6 channels
Number of input pins: 4
EPROM model
Evaluation
model
3
MB90230 Series
PIN ASSIGNMENT
■
P21/A01
P20/A00
P17/D15
P16/D14
P15/D13
P14/D12
(TOP VIEW)
P13/D11
P12/D10
P11/D09
P10/D08
P07/D07
P06/D06
P05/D05
P04/D04
P03/D03
P02/D02
CC
P01/D01
P00/D00
V
X1X0VSSP57
P56/RD
P55/WRL
P22/A02
P23/A03
P24/A04
P25/A05
P26/A06
P27/A07
P30/A08
P31/A09
V
P32/A10
P33/A11
P34/A12
P35/A13
P36/A14
P37/A15
PWM0/P40/A16
PWM1/P41/A17
PWM2/P42/A18
PWM3/P43/A19
PWM4/P44/A20
PWM5/P45/A21
V
TRG/P46/A22
PPG/P47/A23
ATG/P70
9998979695949392919089888786858483828180797877
100
1
2
3
4
5
6
7
8
9
SS
10
11
12
13
14
15
16
17
18
19
20
21
CC
22
23
24
25
26272829303132333435363738394041424344454647484950
P71/EDI
P72/EDO
P75/DA0
P73/ESK
P74/ECS
CC
AV
AVRH
P76/DA1
SS
AV
AVRL
P60/AN0
P61/AN1
P62/AN2
SS
V
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7/CMP
P80/INT0
MD0
MD1
P81/INT1
MD2
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
HST
RST
P54/WRH
P53/HRQ
P52/HAK
P51/RDY
P50/CLK
PA5/SCK2
PA4/SOT2
PA3/SIN2
PA2/SCK1
PA1/SOT1
PA0/SIN1
P96/SCK0
P95/SOT0
P94/SIN0
P93/IN3/CKOT
P92/IN2
P91/IN1
P90/IN0
P87/OUT5
P86/OUT4
P85/OUT3
P84/OUT2
P83/OUT1/INT3
P82/OUT0/INT2
(FPT-100P-M05)
(FPT-100C-C01)
4
PIN DESCRIPTION
■
MB90230 Series
Pin no. Pin name
80 X0 A Oscillator pins
81 X1
82 V
83 to 90 P00 to P07 G General-purpose I/O port
91 to 98 P10 to P17 G General-purpose I/O port
99, 100
1 to 6
CC — Power supply pin
D00 to D07 I/O pins for the lower eight bits of the external data bus.
D08 to D15 I/O pins for the upper eight bits of the external data bus
P20 to P27 G General-purpose I/O port
A00 to A07 I/O pins for the lower eight bits of the external data bus
Circuit
type
An input pull-up resistor can be added to the port by setting the
pull-up resistor setting register.
These pins serve as D00 to D07 pins in bus modes other than the
single-chip mode.
These pins are enabled in an external-bus enabled mode.
An input pull-up resistor can be added to the port by setting the pull-up
resistor setting register.
These pins are enabled in the single-chip mode with the external-bus
enabled and the 8-bit data bus specified.
These pins are enabled in an external-bus enabled mode with the 16bit data bus specified.
An input pull-up resistor can be added to the port by setting the
pull-up resistor setting register.
These pins are enabled in the single-chip mode.
These pins are enabled in an external-bus enabled mode.
Function
7, 8 P30, P31 E General-purpose I/O port
This port is enabled in the single-chip mode or when the middle
address control register setting is “port.”
A08, A09 I/O pins for the middle eight bits of the external data bus
These pins are enabled in an external-bus enabled mode when the
middle address control register setting is “address.”
9V
10 to 15 P32 to P37 E General-purpose I/O port
SS — Power supply pin
This port is enabled in the single-chip mode or when the middle
address control register setting is “port.”
A10 to A15 I/O pins for the middle eight bits of the external data bus
These pins are enabled in an external-bus enabled mode when the
middle address control register setting is “address.”
(Continued)
5
MB90230 Series
Pin no. Pin name
16 P40 E General-purpose I/O port
A16 Output pin for external address A16
PWM0 This pin serves as the output pin for 8-bit PWM0
17 P41 E General-purpose I/O port
A17 Output pin for external address A17
PWM1 This pin serves as the output pin for 8-bit PWM1.
Circuit
type
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
The pin is enabled for output by the control status register.
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
The pin is enabled for output by the control status register.
Function
18 P42 E General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A18 Output pin for external address A18
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM2 This pin serves as the output pin for 8-bit PWM2.
This pin is enabled for output by the control status register.
19 P43 E General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A19 Output pin for external address A19
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM3 This pin serves as the output pin for 8-bit PWM3.
This pin is enabled for output by the control status register.
20 P44 E General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A20 Output pin for external address A20
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM4 This pin serves as the output pin for 8-bit PWM4.
The pin is enabled for output by the control status register.
21 V
CC — Power supply pin
(Continued)
6
Pin no. Pin name
22 P45 E General-purpose I/O port
A21 Output pin for external address A21
PWM5 This pin serves as the output pin for 8-bit PWM5.
23 P46
A22 Output pin for external address A22
TRG This pin serves as the external trigger pin for the 8-bit PPG timer
Circuit
type
1
L*
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
The pin is enabled for output by the control status register.
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
The pin is enabled for triggering by the control status register.
MB90230 Series
Function
24 P47 E General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A23 Output pin for external address A23
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PPG This pin serves as the output pin for the 8-bit PPG timer.
The pin is enabled for output by the control status register.
25 P70
ATG External trigger input pin for the A/D converter
26 P71 F General-purpose I/O port
EDI Data input pin for the serial EEPROM interface
27 P72 E General-purpose I/O port
EDO Data output pin for the serial EEPROM interface
28 P73 E General-purpose I/O port
ESK Clock output pin for the serial EEPROM interface
29 P74 E General-purpose I/O port
ECS Chip select signal output pin for the serial EEPROM interface
L*
1
General-purpose I/O port
This pin functions when enabled by the control status register.
This pin functions when enabled by the control status register.
This pin functions when enabled by the control status register.
This pin functions when enabled by the control status register.
This pin functions when enabled by the control status register.
(Continued)
7
MB90230 Series
Pin no. Pin name
Circuit
type
30, 31 P75, P76 K General-purpose I/O port
DA0
DA1
32 AV
33 AV
34 AV
35 AV
CC — A/D converter power supply pin
RH — “H” reference power supply pin for the A/D converter
RL — “L” reference power supply pin for the A/D converter
SS — A/D converter power pin (GND)
This pin serves as the D/A converter output pin.
The pin functions when enabled by the control status register.
36 to 39 P60 to P63 J General-purpose I/O port
This port is enabled when the analog input enable register setting is
“port.”
AN0 to AN3 A/D converter analog input pins
These pins are enabled when the analog input enable register setting
is “analog input.”
40 V
SS — Power pin (GND)
41 to 43 P64 to P66 J General-purpose I/O port
This port is enabled when the analog input enable register setting is
“port.”
AN4 to AN6 A/D converter analog input pins
These pins are enabled when the analog input enable register setting
is “analog input.”
44 P67 J General-purpose I/O port
This port is enabled when the analog input enable register setting is
“port.”
AN7 A/D converter analog input pin
This pin is enabled when the analog input enable register setting is
“analog input.”
CMP Comparator input pin
2
45 P80
L*
General-purpose I/O port
This port is always enabled.
INT0 External interrupt request input 0
Since this pin serves for interrupt request as required when external
interrupt is enabled, other outputs must be off unless used
intentionally.
2
46 P81
L*
General-purpose I/O port
This port is always enabled.
INT1 External interrupt request input 1
Since this pin serves for interrupt request as required when external
interrupt is enabled, other outputs must be off unless used
intentionally.
47 MD0 C Mode pin
This pin must be fixed to V
48 MD1 C Mode pin
This pin must be fixed to V
Function
CC or VSS.
CC or VSS.
(Continued)
8
MB90230 Series
Pin no. Pin name
Circuit
type
49 MD2 C Mode pin
This pin must be fixed to V
50 HST
51, 52 P82, P83
OUT0,
OUT1
INT2,
INT3
D Hardware standby input pin
2
L*
General-purpose I/O port
Output compare output pins
These pins function when enabled by the control status register.
External interrupt request inputs 2 and 3.
Since these pins serve for interrupt request as required when external
interrupt is enabled, other outputs must be off unless used
intentionally.
53 to 56 P84 to P87 E General-purpose I/O port
This pin is always enabled.
OUT2 to OUT5 Output compare output pins
These pins function when enabled by the control status register.
1
57 to 59 P90 to P92
L*
General-purpose I/O port
This port is always enabled.
IN0 to IN2 Input capture edge input pins
These pins function when enabled by the control status register.
1
60 P93
L*
General-purpose I/O port
This port is always enabled.
IN3 Input capture edge input pin
This pin functions when enabled by the control status register.
CKOT Prescaler output pin
This pin functions when enabled by the control status register.
61 P94 I General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SIN0 Serial data input pin for the UART
This pin functions when enabled by the control status register.
62 P95 H General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SOT0 Serial data output pin for the UART
This pin functions when enabled by the control status register.
63 P96 I General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SCK0 UART clock output pin
This pin functions when enabled by the control status register.
Function
SS.
(Continued)
9
MB90230 Series
Pin no. Pin name
64 PA0 I General-purpose I/O port
SIN1 Serial data input pin for the extended serial I/O interface
65 PA1 H General-purpose I/O port
SOT1 Serial data output pin for the extended serial I/O interface
66 PA2 I General-purpose I/O port
SCK1 Clock output pin for the extended serial I/O interface
67 PA3 I General-purpose I/O port
SIN2 Serial data input pin for the extended serial I/O interface
68 PA4 H General-purpose I/O port
SOT2 Serial data output pin for the extended serial I/O interface
69 PA5 I General-purpose I/O port
SCK2 Clock output pin for the extended serial I/O interface
Circuit
type
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
This pin functions when enabled by the control status register and by
the serial port switching register.
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
This pin functions when enabled by the control status register and by
the serial port switching register.
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
This pin functions when enabled by the control status register and by
the serial port switching register.
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
This pin functions when enabled by the control status register and by
the serial port switching register.
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
This pin functions when enabled by the control status register and by
the serial port switching register.
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
This pin functions when enabled by the control status register and by
the serial port switching register.
The pin is a general-purpose I/O port.
Function
(Continued)
10
(Continued)
MB90230 Series
Pin no. Pin name
70 P50 H This pin is enabled in the single-chip mode and when the CLK output
CLK CLK output pin
71 P51 F General-purpose I/O port
RDY Ready signal input pin
72 P52 E General-purpose I/O port
HAK
73 P53 E General-purpose I/O port
HRQ Hold acknowledge signal output pin
74 P54 E General-purpose I/O port
WRH
75 RST
76 P55 E This port is enabled in the single-chip mode, in external-bus 8-bit
WRL
77 P56 E This pin is enabled in the single-chip mode.
RD
78 P57 E General-purpose I/O port
79 V
SS — Power pin (GND)
Circuit
type
is disabled.
This pin is enabled in an external-bus enabled mode with the CLK
output enabled.
This port is enabled in the single-chip mode.
This pin is enabled in an external-bus enabled mode.
This port is enabled in the single-chip mode or when the hold function
is disabled.
Hold acknowledge signal output pin
This pin is enabled in the single-chip mode or when the hold function
is enabled.
This port is enabled in the single-chip mode or when the hold function
is disabled.
This pin is enabled in the single-chip mode or when the hold function
is enabled.
This port is enabled in the single-chip mode, in external-bus 8-bit
mode, or when the WR pin output is disabled.
Write strobe output pin for the upper eight bits of the data bus
This pin is enabled in an external-bus enabled mode and in external
bus 16-bit mode with the WR pin output enabled.
B Reset signal input pin
mode, or when the WR pin output is disabled
Write strobe output pin for the lower eight bits of the data bus
This pin is enabled in an external-bus enabled mode and in external
bus 16-bit mode with the WR pin output enabled.
The pin is a general-purpose I/O port.
Read strobe output pin for the data bus
This pin is enabled in an external-bus enabled mode.
Function
*1: Enabled in any standby mode
*2: Enabled only in the hardware standby mode
11
MB90230 Series
I/O CIRCUIT TYPE
■
Type Circuit Remarks
A • Oscillation feedback resistor:
Approx. 1 MΩ
X1
X0
Standby control
B • Hysteresis input with pull-up
resistor
C•CMOS input port
D • Hysteresis input port
E • CMOS level output
CMOS
Standby control
12
(Continued)
MB90230 Series
Type Circuit Remarks
F • CMOS level output
• Hysteresis input
Standby control
G • Input pull-up resistor control
provided
Pull-up control
• CMOS level input/output
CMOS
Standby control
H • CMOS level input/output
• Open-drain control provided
Open-drain control signal
CMOS
Standby control
(Continued)
13
MB90230 Series
(Continued)
Type Circuit Remarks
I • CMOS level output
Open-drain control signal
CMOS
Standby control
J • CMOS level input/output
• Hysteresis input
• Open-drain control provided
• Analog input
Analog input
CMOS
Standby control
K • CMOS level input/output
• Analog output
• Also serving for D/A output
DA output
CMOS
Standby control
L • CMOS level output
Open-drain control signal
• Hysteresis input
• Open-drain control provided
14
Standby control
MB90230 Series
HANDLING DEVICES
■
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage wihich shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between V
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
CC and VSS.
Also, tak e care to pre v ent the analog po wer supply (AV
CC and A VR) and analog input from e xceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. External Reset Input
To reset the internal circuit by the Low-level input to the RST pin, the Low-level input to the RST pin must be
maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.
4. VCC and VSS Pins
Apply equal potential to the VCC and VSS pins.
5. Notes on Using an External Clock
When using an external clock, drive the X0 pin as illustrated below:
Use of External Clock
MB90234
X0
X1
6. Power-on Sequence for A/D Converter Power Supplies and Analog Inputs
Be sure to turn on the digital power supply (VCC) before applying voltage to the A/D converter power supplies
(AV
CC, AVRH, and AVRL) and analog inputs (AN0 to AN15).
When turning power supplies off, turn off the A/D converter power supplies (AV
CC, AVRH, and AVRL) and analog
inputs (AN0 to AN15) first, then the digital power supply (AVCC).
When turning AVRH on or off, be careful not to let it exceed AV
CC.
7. Pin set when turning on power supplies
When turning on power supplies, set the hardware standby input pin (HST) to “H”.
15
MB90230 Series
8. Program Mode
When shipped from Fujitsu, and after each erasure, all bits (96K × 8 bits) in the MB90W234 and MB90P234 are
in the “1” state. Data is introduced by selectively programming “0’s” into the desired bit locations. Bits cannot
be set to 1 electrically.
9. Erasure Procedure
Data written in the MB90W234 is erased (from 0 to 1) by exposing the chip to ultraviolet rays with a wavelength
of 2,537Å through the translucent cover.
2
Recommended irradiation dosage for exposure is 10 Wsec/cm
with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface
illuminance is 1200 µW/cm
If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the lamp
increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent
part of the package is stained with oil or adhesive, transmission of ultraviolet rays is degraded, resulting in a
longer erasure time. In that case, clean the translucent part using alcohol (or other solvent not affecting the
package).
2
).
. This amount is reached in 15 to 20 minutes
The above recommended dosage is a value which takes the guard band into consideration and is a multiple of
the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure;
the purpose of the guard band is to ensure erasure in all temperature and supply voltage ranges. In addition,
check the lifespan of the lamp and control the illuminance appropriately.
Data in the MB90W234 is erased by exposure to light with a wavelength of 4000Å or less.
Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure
results in a much lower erasure rate than exposure to 2537Å ultraviolet rays. Note that exposure to such lights
for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light
with a wavelength of 4000Å or less, cover the translucent part, for example, with a protective seal to prevent
the chip from being exposed to the light.
Exposure to light with a wavelength of 4,000 to 5,000Å or more will not erase data in the device. If the light
applied to the chip has a very high illuminance, however, the device may cause malfunction in the circuit for
reasons of general semiconductor characteristics. Although the circuit will recover normal operation when
exposure is stopped, the device requires proper countermeasures for use in a place exposed continuously to
such light even though the wavelength is 4,000Å or more.
16
MB90230 Series
10. Recommended Screening Conditions
High-temperature aging is recommended for screening before packaging.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
11. Write Yield
OTPROM products cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always
be guaranteed to be 100%.
17
MB90230 Series
BLOCK DIAGRAM
■
X0, X1
RST
HST
SIN0
SOT0
SCK0
CKOT
SIN1, 2
SOT1, 2
SCK1, 2
AVcc
AVRH, AVRL
AVss
ATG
AN0 to AN7
4
Clock controller
Communication prescaler
Extended serial
I/O interface
10-bit A/D converter
RAM
ROM
UART
CPU
F2MC-16F
MC-16 bus
2
F
Interrupt controller
External interrupt
8-bit PWM
6 ch
8-bit PPG timer
I/O timer
16-bit input capture × 4
16-bit free run timer
16-bit output compare × 6
Serial E
2
PROM interface
4
2
INT0
to
INT3
PWM0
to
PWM5
TRG
PPG
IN0, 1
IN2, 3
OUT0, 1
OUT2, 3
OUT4, 5
ECS, ESK
EDO
EDI
18
DA0
DA1
D/A converter
I/O ports (84 lines)
8 8 8 8 8 8 8 78
P00
P10
P20
P30
P40
P50
P60
to
P07
to
P17
to
P27
to
P37
to
P47
to
P57
to
P67
P70
to
P76
Level comparator
7
P80
P90
to
to
P87
P96
6
PA0
to
PA5
P00 to P27 (24 lines): Provided with input pull-up resistor setting registers
P94 to P96, PA0 to PA5 (9 lines): Provided with open-drain setting registers
CMP
MEMORY MAP
■
MB90230 Series
FFFFFFH
Address1#
00FFFFH
Address#2
Address#3
000100
0000C0H
000000H
Single-chip mode
ROM area
ROM area
(FF bank image)
RAM
H
Peripherals Peripherals Peripherals
Registers
Internal ROM and
external bus
ROM area
ROM area
(FF bank image)
RAM
Registers
External ROM and
external bus
RAM
Registers
Internal External Inhibited area
000000H to 000005H and 000010H to 000015H are allocated for external use
Note:
when the external bus is enabled.
Address#3
000900H
MB90233
FF4000
Address#2Address#1Product type
H
004000H
MB90234
MB90P234
MB90W234
MB90V230
FE8000
H
FE8000H
(FE0000H)
004000
004000H
(004000H)
H
000D00
H
000D00H
(001100H)
The MB90230 series can access the 00 bank to read ROM data written to the upper 48-KB locations in the FF
bank. An advantage of reading written to data addresses FFFFFF
H-FF4000H from addresses 00FFFFH-004000H is
that you can use the small model of a C compiler.
Note, however, that the products with more than 48KB ROM space (MB90V230, MB90P/W234, MB90234) cannot
read data in addresses other than FFFFFF
H to FF4000H from the 00 bank.
19
MB90230 Series
I/O MAP
■
Address Register
00
H Port 0 data register PDR0 R/W Port 0 XXXXX X X X
01
H Port 1 data register PDR1 R/W Port 1 XXXXX X X X
Register
name
Access
Resouce
name
Initial value
02H Port 2 data register PDR2 R/W Port 2 XXXXX X X X
03
H Port 3 data register PDR3 R/W Port 3 XXXXX X X X
04
H Port 4 data register PDR4 R/W Port 4 XXXXX X X X
05H Port 5 data register PDR5 R/W Port 5 XXXXX X X X
06
H Port 6 data register PDR6 R/W Port 6 XXXXX X X X
07
H Port 7 data register PDR7 R/W Port 7 – XXXX X X X
08H Port 8 data register PDR8 R/W Port 8 XXXXX X X X
09
H Port 9 data register PDR9 R/W Port 9 – XXXX X X X
0A
H Port A data register PDRA R/W Port A – – XXXXXX
10H Port 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0
11
H Port 1 direction register DDR1 R/W Port 1 0 0 0 0 0 0 0 0
12
H Port 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 0 0
13H Port 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0
14
H Port 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0
15
H Port 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0
16
H Port 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0
17H Port 7 direction register DDR7 R/W Port 7 – 0 0 0 0 0 0 0
18
H Port 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0
19
H Port 9 direction register DDR9 R/W Port 9 – 0 0 0 0 0 0 0
1AH Port A direction register DDRA R/W Port A – – 0 0 0 0 0 0
1B
H Port 0 resistor register RDR0 R/W Port 0 0 0 0 0 0 0 0 0
1C
H Port 1 resistor register RDR1 R/W Port 1 0 0 0 0 0 0 0 0
1DH Port 2 resistor register RDR2 R/W Port 2 0 0 0 0 0 0 0 0
1E
H Port 9 pin register ODR9 R/W Port 9 – 0 0 0 – – – –
1F
H Port A pin register ODRA R/W Port A – – 0 0 0 0 0 0
20H Mode control register UMC R/W UART 0 0 0 0 0 1 0 0
21
H Status register USR R/W 0 0 0 1 0 0 0 0
22
H Serial input register
/Serial output register
H Rate and data register URD R/W 0 0 0 0 – – 0 0
23
24
H Serial mode control status register SMCS R/W
25
H 00000010
UIDR
/UODR
R/W
Extended serial
I/O interface
XXXXXXXX
–––00000
20
(Continued)
MB90230 Series
Address Register
26
H Serial data register SDR R/W Extended serial
Register
name
Access
Resouce
name
Initial value
XXXXXXXX
I/O interface
27
H Reserved area — — — —
28
H Cycle setting register PCSR W 8-bit
29
H Duty factor setting register PDUT W XXXX X X X X
PPG timer
XXXXXXXX
2AH Control status register PCNTL R/W 00000000
2B
H PCNTH 0000000–
2C
H Reserved area — — — —
2DH Communication prescaler CDCR R/W UART, CKOT,
0–––1111
I/O, serial IF
2E
H Clock control register CLKR R/W CKOT output – – – – – 0 0 0
2F
H Level comparator LVLC R/W Level
XXXX00 00
comparator
30
H Interrupt/DTP enable register ENIR R/W DTP/external
31
H Interrupt/DTP factor register EIRR R/W – – – – 0 0 0 0
32
H Request level setting register ELVR R/W 0 0 0 0 0 0 0 0
interrupt
––––0000
33H Reserved area — — — —
34
H Analog input enable register ADER R/W 10-bit A/D
35
H Reserved area — — —
36
H Control status data register ADCS0 R/W 0 0 0 0 0 0 0 0
converter
11111111
37H ADCS1 00000000
38
H Data register ADCR0 R XXXXXXXX
39
H ADCR1 000000XX
3AH Reserved area — — — —
3B
H Reserved area — — — —
3C
H D/A converter data register 0 DAT0 R/W 8-bit D/A
3DH D/A converter data register 1 DAT1 R/W 0 0 0 0 0 0 0 0
3E
H D/A control register DACR R/W ––––––00
3F
H Reserved area — — — —
converter
40H PWM data register 0 PWD0 R/W 8-bit
41
H PWM data register 1 PWD1 R/W 0 0 0 0 0 0 0 0
42
H Control status data register 0, 1 PWC01 R/W 0 0 0 0 0 0 0 0
43
H Reserved area — — — —
PWM0, 1
44H PWM data register 2 PWD2 R/W 8-bit
45
H PWM data register 3 PWD3 R/W 0 0 0 0 0 0 0 0
PWM2, 3
XXXXXXXX
00000000
00000000
46
H Control status register 2, 3 PWC23 R/W 0 0 0 0 0 0 0 0
(Continued)
21
MB90230 Series
Address Register
47
H Reserved area — — — —
48
H PWM data register 4 PWD4 R/W 8-bit
49
H PWM data register 5 PWD5 R/W 0 0 0 0 0 0 0 0
Register
name
Access
Resouce
name
PWM4, 5
Initial value
00000000
4AH Control status register 4, 5 PWC45 R/W 0 0 0 0 0 0 0 0
4B
H Reserved area — — — —
4C
H Data register TCDT R 16-bit free
4DH 00000000
4E
H Control status register TCCS R/W 0 0 0 0 0 0 0 0
4F
H Reserved area — — — —
run timer
50H Compare register 0 OCP0 R/W Output
51
H XXXXXXXX
52
H Compare register 1 OCP1 R/W XXXXXXXX
compare 0, 1
00000000
XXXXXXXX
53H XXXXXXXX
54
H Control status register 0, 1 CS00 R/W 0 0 0 0 – – 0 0
55
H CS01 –––00000
56H Reserved area — — — —
57
H Reserved area — — — —
58
H Compare register 2 OCP2 R/W Output
59
H XXXXXXXX
compare 2, 3
XXXXXXXX
5AH Compare register 3 OCP3 R/W XXXXXXXX
5B
H XXXXXXXX
5C
H Control status register 2, 3 CS10 R/W 0 0 0 0 – – 0 0
5DH CS11 –––00000
5E
H Reserved area — — — —
5F
H Reserved area — — — —
60H Compare register 4 OCP4 R/W Output
61
H XXXXXXXX
62
H Compare register 5 OCP5
compare 4, 5
XXXXXXXX
XXXXXXXX
R/W
63H XXXXXXXX
64
H
Control status register 4, 5
H CS21 –––00000
65
66
H Reserved area — — — —
67H to
6F
H
Reserved area
CS20
0000––00
R/W
—— — —
(Continued)
22
MB90230 Series
Address Register
70
H Capture register 0 ICP0 R/W Input capture 0,
71
H XXXXXXXX
72
H Capture register 1 ICP1 R/W XXXXXXXX
Register
name
Access
1
Resouce
name
Initial value
XXXXXXXX
73H XXXXXXXX
74
H Control status register 0, 1 ICS0 R/W 0 0 0 0 0 0 0 0
75
H to
Reserved area — — — —
77H
78
H Capture register 2 ICP2 R/W Input capture 2,
79
H XXXXXXXX
3
XXXXXXXX
7AH Capture register 3 ICP3 R/W XXXXXXXX
7B
H XXXXXXXX
7C
H Control status register 2, 3 ICS1 R/W 0 0 0 0 0 0 0 0
7DH to
7F
H
80
H OP code register EOPC R/W
H Format status register ECTS R/W 0 0 0 0 0 0 0 0
81
82
H Data register EDAT R/W XXXXXXXX
Reserved area — — — —
Serial E
2
PROM
––––0000
interface
83
H XXXXXXXX
84
H Address register EADR R/W 0 0 0 0 0 0 0 0
85H 00–––000
86
H to
8F
H
90
H to
9E
H
9F
H Delayed interrupt source generate/
A0
H Standby control register STBYC R/W Low-power
Reserved area — — — —
System reserved area — *1 — —
release register
DIRR R/W Del ay e d i n t e r ru p t
generation module
–––––––0
0001XXXX
consumption
mode
A1
H Reserved area — — — —
A2
H Reserved area — — — —
A3H Middle address control register MACR W External pin *2
A4
H Upper address control register HACR W External pin *2
A5
H External pin control register EPCR W External pin *2
A6
H Reserved area — — — —
A7H Reserved area — — — —
A8
H Watchdog timer control register TWC R/W Watchdog timer/
reset
XXXXXXXX
(Continued)
23
MB90230 Series
Address Register
A9
H Timebase timer control register TBTC R/W Timebase
Register
name
Access
Resouce
name
Initial value
–––00000
timer
AA
H to
Reserved area — — — —
AFH
B0
H Interrupt control register 00 ICR00 R/W Interrupt
B1
H Interrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1
controller
00000111
B2H Interrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1
B3
H Interrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1
B4
H Interrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1
B5H Interrupt control register 05 ICR05 R/W 0 0 0 0 0 1 1 1
B6
H Interrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1
B7
H Interrupt control register 07 ICR07 R/W 0 0 0 0 0 1 1 1
B8H Interrupt control register 08 ICR08 R/W 0 0 0 0 0 1 1 1
B9
H Interrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1
BA
H Interrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1
BBH Interrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1
BC
H Interrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1
BD
H Interrupt control register 13 ICR13 R/W 0 0 0 0 0 1 1 1
BE
H Interrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1
BFH Interrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1
C0
FF
H to
H
External area — — — *3
Initial values
0: The initial value for the bit is “0.”
1: The initial value for the bit is “1.”
X: The initial value for the bit is undefined.
–: The bit is not used; the initial value is undefined.
*1: Access inhibited
*2: The initial value depends on each bus mode.
*3: Only this area can be used as the external access area in the area that follows address 0000FF
H. Access to
any address in reserved areas specified in the I/O map table is handled as access to an internal area. An
access signal to the external bus is not generated.
24
MB90230 Series
INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS FOR INTERRUPT
■
SOURCES
Interrupt control
register
Interrupt source
2
OS
I
support
Interrupt vector
No. Address ICR Address
Reset × #08 08
H FFFFDCH ——
INT9 instruction × #09 09H FFFFD8H ——
Exceptional × #10 0A
External interrupt (INT0) 0 ch #11 0B
H FFFFD4H ——
H FFFFD0H
ICR00 0000B0H
External interrupt (INT1) 1 ch #12 0CH FFFFCCH
External interrupt (INT2) 2 ch #13 0DH FFFFC8H
ICR01 0000B1H
External interrupt (INT3) 3 ch #14 0EH FFFFC4H
Extended serial I/O interface #15 0FH FFFFC0H
Serial E2PROM interface
#17 11
H FFFFB8H ICR03
Input capture channel 0 #19 13H FFFFB0H
Input capture channel 1 #21 15H FFFFA8H ICR05
Input capture channel 2 #23 17H FFFFA0H
Input capture channel 3
#24 18
H FFFF9CH
Output compare channel 0 #25 19H FFFF98H
ICR02 0000B2H
0000B3
ICR04 0000B4H
0000B5
ICR06 0000B6H
ICR07 0000B7H
H
H
Output compare channel 1 #26 1AH FFFF94H
Output compare channel 2 #27 1BH FFFF90H
ICR08 0000B8H
Output compare channel 3 #28 1CH FFFF8CH
Output compare channel 4 #29 1DH FFFF88H
ICR09 0000B9H
Output compare channel 5 #30 1EH FFFF84H
16-bit free run timer overflow #31 1FH FFFF80H
ICR10 0000BAH
Timebase timer overflow #32 20H FFFF7CH
8-bit PPG timer #33 21H FFFF78H
ICR11 0000BBH
Level comparator #34 22H FFFF74H
UART reception #35 23H FFFF70H ICR12
UART transmission #37 25H FFFF68H
ICR13 0000BDH
End of A/D conversion #39 27H FFFF60H ICR14
0000BC
0000BE
H
H
Delayed interrupt × #42 2AH FFFF54H ICR15 0000BFH
Stack fault × #256 FFH FFFC00H ——
: The request flag is cleared by the EI2OS interrupt clear signal.
: The request flag is cleared by the EI
: The request flag is not cleared by the EI
2
OS interrupt clear signal. The stop request is available.
2
OS interrupt clear signal.
25
MB90230 Series
PERIPHERAL RESOURCES
■
1. I/O Ports
Each pin in each port can be specified for input or output by setting the direction register when the corresponding
peripheral resource is not set to use that pin. When the data register is read, the value depending on the pin
level is read whenever the pin serves for input. When the data register is read with the pin serving for output,
the latch value of the data register is read. This also applies to read operation by the read modify write instruction.
• General-purpose I/O port
Data register read
Data register
Data register write
Internal data bus
Direction register write
Direction register read
Direction register
• Port with pull-up resistor setting register
Data register
Pin
Pull-up resistor (Approx. 50 kΩ)
Port input/output
26
Direction register read
Internal data bus
Resistor register
• Port with open-drain setting register
MB90230 Series
Internal data bus
Data register
Direction register
Pin register
Port input/output
27
MB90230 Series
(1) Register Configuration
15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
bit
Address: 000000
Address: 000001H
Address: 000002H
Address: 000003H
Address: 000004H
Address: 000005H
Address: 000006H
Address: 000007H
Address: 000008H
Address: 000009H
Address: 00000AH
Address: 000010
Address: 000011H
Address: 000012H
Address: 000013H
Address: 000014H
Address: 000015H
Address: 000016H
Address: 000017H
Address: 000018H
Address: 000019H
Address: 00001AH
P07
H
P17
P27
P37
P47
P57
P67
—
P87
—
—
15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
bit
P07
H
P17
P27
P37
P47
P57
P67
—
P87
—
—
P06 P05 P04 P03 P02 P01
P16 P15 P14 P13 P12 P11
P26 P25 P24 P23 P22 P21
P36 P35 P34 P33 P32 P31
P46 P45 P44 P43 P42 P41
P56 P55 P54 P53 P52 P51
P66 P65 P64 P63 P62 P61
P76 P75 P74 P73 P72 P71
P86 P85 P84 P83 P82 P81
P96 P95 P94 P93 P92 P91
— PA5 PA4 PA3 PA2 PA1
P06 P05 P04 P03 P02 P01
P16 P15 P14 P13 P12 P11
P26 P25 P24 P23 P22 P21
P36 P35 P34 P33 P32 P31
P46 P45 P44 P43 P42 P41
P56 P55 P54 P53 P52 P51
P66 P65 P64 P63 P62 P61
P76 P75 P74 P73 P72 P71
P86 P85 P84 P83 P82 P81
P96 P95 P94 P93 P92 P91
— PA5 PA4 PA3 PA2 PA1
P00
Port 0 data register (PDR0)
P10
Port 1 data register (PDR1)
P20
Port 2 data register (PDR2)
P30
Port 3 data register (PDR3)
P40
Port 4 data register (PDR4)
P50
Port 5 data register (PDR5)
P60
Port 6 data register (PDR6)
P70
Port 7 data register (PDR7)
P80
Port 8 data register (PDR8)
P90
Port 9 data register (PDR9)
PA0
Port A data register (PDRA)
P00
Port 0 direction register (DDR0)
P10
Port 1 direction register (DDR1)
P20
Port 2 direction register (DDR2)
P30
Port 3 direction register (DDR3)
P40
Port 4 direction register (DDR4)
P50
Port 5 direction register (DDR5)
P60
Port 6 direction register (DDR6)
P70
Port 7 direction register (DDR7)
P80
Port 8 direction register (DDR8)
P90
Port 9 direction register (DDR9)
PA0
Port A direction register (DDRA)
28
bit
Address: 000034
bit
Address: 00001B
Address: 00001CH
Address: 00001DH
bit
Address: 00001E
Address: 00001FH
15 14 13 12 11 10 9 8
ADE6 ADE5 ADE4 ADE3 ADE2 ADE1
ADE7
H
15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
P06 P05 P04 P03 P02 P01
P07
H
P16 P15 P14 P13 P12 P11
P17
P26 P25 P24 P23 P22 P21
P27
15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
P96 P95 P94 — — —
—
H
— PA5 PA4 PA3 PA2 PA1
—
Analog input enable register (ADER)
ADE0
P00
Port 0 resistor register (RDR0)
P10
Port 1 resistor register (RDR1)
P20
Port 2 resistor register (RDR2)
—
Port 9 pin register (ODR9)
PA0
Port A pin register (ODRA)
MB90230 Series
Ports 0 to 5 in the MB90230 series share the external bus and pins. Each pin function is selected depending on
the bus mode and register settings.
Function
Pin name
Single-chip mode
External bus extended mode
EPROM write
8 bits 16 bits
P07 to P00
D07 to D00 D07 to D00
P17 to P10 Port D15 to D08 D15 to D08
P27 to P20 A07 to A00 A07 to A00
P37 to P30
A15 to A08*
1
A15 to A08
P47 to P45
A23 to A16*
1
A23 to A16P44
P43 to P40
P50
Port
P51
P52
P53
P54 Port
P55 WR
CLK*
RDY*
HAK
HRQ*
2
2
2
*
2
2
WRH
*
2
WRL*
Not used
CE
OE
P56 RD PGM
P57 Port “0”
*1: The pin can be used as an I/O port by setting the upper and middle address control registers.
*2: The pin can be used as an I/O port by setting the external pin control register.
29
MB90230 Series
2. 8-bit PWM (with 6 channels in this series)
The PWM module consists of a pair of 8-bit PWM output circuits. The MB90230 series incorporates a set of
three PWM modules. They can output a waveform continuously from the port at an arbitrary duty factor according
to the register settings.
• 8-bit down counter
• 8-bit data registers
• Compare circuit
• Control registers
(1) Register Configuration
bit
000041, 40H
000045, 44H
000049, 48H
000042
H
000046H
00004AH
(2) Block Diagram
Bus
15
87 0
PWDx PWDx
70
PWCxx
8-bit down counter
Comparator, PWM output section
8-bit data registers
PWM data registers 0 to 5
Control registers 0 to 5
PWM output
30
Control registers
MB90230 Series
3. UART
The UART is a serial I/O port for synchronous or asynchronous communication with external resources. It has
the following features:
• Full-duplex double buffering
• Data transfer synchronous or asynchronous with clock pulses
• Multiprocessor mode support (Mode 2)
• Internal dedicated baud-rate generator
• Arbitrary baud-rate setting from external clock input or internal timer
• Variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit))
• Error detection function (Framing, overrun, parity)
• Interrupt function (Two sources for transmission and reception)
• Transfer in NRZ format
(1) Register Configuration
bit
Address: 000020H
bit
Address: 000021H
bit
Address: 000022H
bit
Address: 000023H
bit
Address: 00002DH
15
USR
URD
8 bits
76543210
PEN SBL MC1 MC0 SMDE RFC SCKE SOE
15 14 13 12 11 10 9 8
RDRF ORFE PE TDRE RIE TIE RBF TBF
76543210
D7 D6 D5 D4 D3 D2 D1 D0
15 14 13 12 11 10 9 8
— RC2 RC1 RC0 — — P D8
15 14 13 12 11 10 9 8
MD — — — DIV3 DIV2 DIV1 DIV0
87 0
UMC
UIDR (R)/UODR (W)
8 bits
(R/W)
(R/W)
Mode control register
(UMC)
Status register
(USR)
Serial input data register
Serial output data register
(UIDR/UODR)
Rate and data register
(URD)
Communication prescaler
(CDCR)
31
MB90230 Series
(2) Block Diagram
CONTROL BUS
Reception interrupt
(To CPU)
Dedicated baud-rate clock
Internal timer
External clock
SIN0
Reception status
detection circuit
Clock selector
circuit
Receiving clock
Reception control circuit
Start bit detector
Received bit counter
Received parity counter
Reception shifter
Transmitting clock
Transmission control circuit
Transmission start circuit
Transmission bit counter
Transmission parity counter
SCK0
Transmission interrupt
(To CPU)
SOT0
Transmission shifter
32
UMC
register
Reception error
occurrence signal for EI
(To CPU)
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
2
OS
USR
register
End of reception
UIDR
Data bus
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
URD
register
Start of transmission
UODR
BCH
RC2
RC1
RC0
P
D8
CONTROL BUS
MB90230 Series
4. Extended Serial I/O Interface
This block is a serial I/O interface implemented on a single 8-bit channel that can transfer data in synchronization
with clock pulses. It allows the “LSB first” or “MSB first” option to be selected for data transfer. The serial I/O
port to be used can also be selected.
There are two serial I/O operation modes available:
• Internal shift clock mode: Transfers data in synchronization with internal clock pulses.
• External shift clock mode: Transfers data in synchronization with clock pulses entered from an external pin
(SCKx). In this mode, data can be transferred by instructions from the CPU by
operating the general-purpose port that shares the external pin (SCKx).
(1) Register Configuration
bit
Address: 000025
Address: 000024H
Address: 000026H
H
bit
bit
(2) Block Diagram
(MSB first) D0 to D7
SIN1, 2
SOT1, 2
15 14 13 12 11 10 9 8
SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT
76543210
— — — OUTC MODE BDS SOE SCOE
76543210
D7 D6 D5 D4 D3 D2 D1 D0
Internal data bus
D7 to D0 (LSB first)
Selecting transfer direction
SDR (Serial data register)
Serial mode control status
register (SMCS)
Serial data register
(SDR)
Read
Write
SCK1, 2
Internal clock
Control circuit
21 0
SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS
Interrupt
request
Internal data bus
Shift clock counter
SOE
SCOE
33
MB90230 Series
5. A/D Converter
The A/D converter converts the analog input voltage to a digital value. It has the following features:
• Conversion time: 5 µs min. per channel (at 16 MHz machine clock)
• RC-type successive approximation with sample-and-hold circuit
• 8-bit or 10-bit resolution
• Eight analog input channels programmable for selection
• A/D conversion mode selectable from the following three:
One-shot conversion mode: Converts a specified channel once.
Consecutive conversion mode: Converts a specified channel repeatedly.
Stop conversion mode: Converts one channel and suspends its own operation until the next activation (allowing
synchronized conversion start).
• Conversion mode:
Single conversion mode: Converts one channel (when the start and stop channels are the same).
Scan conversion mode: Converts multiple consecutive channels (when the star t and stop channels are
different).
• On completion of A/D conversion, the conver ter can generate an interrupt request for ter mination of A/D
conversion to the CPU. This interrupt generation can activate the EI
to memory, making the converter suitable for continuous operation.
• Conversion can be activ ated by software , external trigger (falling edge), and/or timer (rising edge) as selected.
2
OS to transfer the A/D con v ersion result
(1) Register Configuration
bit
15
000037, 36H
000039, 38H
000034
H
87 0
ADCS1 ADCS0
ADCR1 ADCR0
ADER
Analog input enable register
Control status register
Data register
34
(2) Block Diagram
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
MPX
Input circuit
Comparator
MB90230 Series
AVCC
AVRH,
AVRL
AVSS
D/A converter
Successive
approximation register
Sample-and-hold circuit
ATG
Interlocked with PPG timer
Activation trigger
Timer
φ
Data bus
Data register
ADCR1, 0
Decoder
A/D control register 0
A/D control register 1
ADCS1, 0
Activation by timer
Operation clock
Prescaler
35
MB90230 Series
6. 16-bit I/O Timer
The 16-bit I/O timer consists of 16-bit free run timer, 6-line output compare, and 4-line input capture modules.
The 16-bit I/O timer can output six independent waveforms based on the 16-bit free run timer, allowing the input
pulse width and external clock cycle to be measured.
(1) Outline of Functions
16-bit free run timer (× 1)
The 16-bit free run timer consists of a 16-bit up-count timer, a control register, and a prescaler. The value output
from this timer/counter is used as the base time by the input capture and output compare modules.
• The counter operation clock cycle can be selected from the following four:
Four internal clock cycles (φ/4, φ/16, φ/32, φ/64)
• The interrupt counter value can be generated by compare/match operation with the overflow register and
compare register 0 (compare/match operation requires the mode setting).
• The counter value can be initialized to “0000
clear register, and compare register 0.
Output compare module (× 6)
The output compare module consists of six 16-bit compare registers, compare output latches, and control
registers. When the compare value matches the 16-bit free run timer value, this module can generates an
interrupt while inverting the output level.
• Six compare registers can operate independently, and have each output pin and interrupt flag.
• Two compare resisters can be used to control the same output pin.
• The initial value for each output pin can be set.
• The interrupt can be generated by compare/match operation.
H” by compare/match operation with the reset register, software
Input capture module (× 4)
The input capture module consists of four external input pins and associated capture and control registers. This
module can detect an arbitrary edge of the signal input from each external input pin to generate an interrupt
while holding the 16-bit free run timer value in the capture register.
• The external input signal edge can be selected from the rising edge, failing edge or both edges.
• Four input capture lines can operate independently.
• The interrupts can be generated by a valid edge of external input signals. The extended intelligent I/O service
2
(EI
OS) can be activated.
36
(2) Register Configuration
• 16-bit free run timer
MB90230 Series
bit
00004C
00004E
15
H
H
• 16-bit output compare module
000050, 52, 58, 5A
000060, 62H
000054, 55
00005C, 5DH
000064, 65H
H
bit
15
H
CS × 1 CS × 0
• 16-bit input capture module
000070, 72, 78, 7A
000074, 7C
H
bit
15
H
TCDT
OCP0 to 5
IPCP0 to 3
TCCS
ICS0 to 3
0
Timer data register
Control status register
0
Compare register 0 to 5
Control status register 0 to 5
0
Compare register 0 to 3
Control status register 0 to 3
37
MB90230 Series
(3) Block Diagram
16-bit free run timer
Control logic
16-bit timer
Output compare 0
Bus
Output compare 1
Output compare 2
Input capture 0
Input capture 1
Compare register 0
Compare register 1
Compare register 2
Compare register 3
Compare register 4
Compare register 5
Capture register 0
Capture register 1
Capture register 2
Clear
To each block
TQ
TQ
TQ
TQ
TQ
TQ
Edge selection
Edge selection
Edge selection
OUT 0
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
IN 0
IN 1
IN 2
38
Capture register 3
Interrupt
10
Edge selection
IN 3
MB90230 Series
7. PPG Timer (Programmable Pulse Generator)
This module can output the pulse synchronized with an external or software trigger. The cycle and duty factor
of the output pulse can be changed arbitrarily by changing the values in two 8-bit registers.
PWM function: Outputs a pulse in programmable mode while changing the values in the two registers in
synchronization with the input trigger.
This module can also be used as a D/A converter using an external circuit.
Single-shot function: Detects the trigger input edge to output a single pulse.
(1) Module Configuration
This module consists of an 8-bit down counter, prescaler, 8-bit cycle setting register, 8-bit duty factor setting
register, 16-bit control register, external trigger input pin, and PPG output pin.
(2) Register Configuration
Address:
bit
000028
H
000029
H
00002BH, 2AH
15
87 0
PCSR
PDUT
PCNTH PCNTL
Cycle setting register
Duty factor setting register
Control status register
39
MB90230 Series
(3) Block Diagram
Prescaler
P D U TP C S R
1 / φ
4 / φ
16 / φ
64 / φ
ck Load
8-bit
down counter
Start Borrow
Enable
PPG mask
S Q
R
Inverted bit
cmp
PPG output
IRQ
40
TRG input
Edge detection
Interrupt selection
Software trigger
MB90230 Series
8. Serial E2PROM Interface
This module is the interface circuit dedicated to external bit-serial E2PROM.
(1) Features
• Instruction code support (compatible with the MB8557).
• Selectable address length: 8 to 11 bits
• Selectable data length: 8 or 16 bits
• Automatic address increment function
• Transmit/receive data transfer enabled by EI
• Up to 2048-by-16 bit access enabled (at an address length of 11 bits and a data length of 16 bits)
(2) Register Configuration
2
OS
bit
bit
Address: 000081
bit
Address: 000080H
bit
Address: 000083H
bit
Address: 000082H
bit
Address: 000085H
15
15 14 13 12 11 10 9 8
H
IFEN INT INTE BUSY ADL1 ADL0 DTL CON
76543210
— — — — OP3 OP2 OP1 OP0
15 14 13 12 11 10 9 8
D15 D14 D13 D12 D11 D10 D9 D8
76543210
D7 D6 D5 D4 D3 D2 D1 D0
15 14 13 12 11 10 9 8
CLK FRQ — — — A10 A9 A8
87 0
Status format register
Data register
Address register
Format status register
(ECTS)
Op code register
(EOPC)
Data register
(EDAT)
Data register
(EDAT)
Address register
(EADR)
bit
Address: 000084
76543210
H
A7 A6 A5 A4 A3 A2 A1 A0
Address register
(EADR)
41
MB90230 Series
(3) Block Diagram
Op code register
Address register
φ
Machine cycle
Bus
Data register
Data register
Format register
Status register
Prescaler
EDI
EDO
ECS
Operation clock
ESK
42
MB90230 Series
9. DTP/External Interrupt
The data transfer peripheral (DTP) is located between external peripherals and the F2MC-16F CPU. It receives
a DMA request or interrupt request generated by the external peripherals and reports it to the F
to activate the extended intelligent I/O service or interrupt handler. The user can select two request levels of
“H” and “L” for extended intelligent I/O service (EI
2
OS) or, four request levels of “H,” “L,” rising edge, and falling
edge for external interrupt requests.
(1) Register Configuration
2
MC-16F CPU
Address:
000031H, 30H
000032
(2) Block Diagram
4
4
MC-16 bus
2
F
4
8
bit
15
H
Interrupt DTP source register
Gate
Interrupt DTP source register
Request level setting register
87 0
EIRR ENIR
ELVR
Source F/F
Edge detection circuit
Interrupt/DTP enable register
Request level setting register
3
Request input
43
MB90230 Series
10.
D/A Converter
This block is an R-2R type D/A converter with 8-bit resolution.
The D/A converter incorporates two channels, each of which can be controlled for output independently by the
D/A control register.
(1) Register Configuration
DAT1
Address: 00003D
DAT0
Address: 00003CH
DACR
Address: 00003E
bit
H
H
(2) Block Diagram
DA17DA16DA15DA14DA13DA12DA11DA
DA17
DA16
15 14 13 12 11 10 9 8
DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10
76543210
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00
76543210
— — — — — — DAE1 DAE0
F2MC-16 bus
10
CC
AV
2R 2R
R
DA07DA06DA05DA04DA03DA02DA01DA
DA07
DA06
D/A converter data register 1
D/A converter data register 2
D/A control register
00
CC
AV
R
44
DA15
DA11
DA10
2R
2R
2R
2R
DAE1
Standby control
DA output
ch. 1
R
R
DA05
DA01
DA00
2R
2R
2R
2R
DAE0
Standby control
DA output
ch. 0
R
R
11.
Level Comparator
This module compares the input level (by checking whether it is high or low).
The module consists of a comparator, 4-bit resistor ladder, and control register.
• The external input can be compared to the internal 4-bit resistor ladder.
(1) Register Configuration
MB90230 Series
Address:
00002F
(2) Block Diagram
Analog input
CMP
bit
8
H
4-bit D/A
AVRH
Resistor ladder
AVRL
S/H
Comparator
LVLC
RD3 RD2 RD1 RD0
4
CPLV INT INTE CPEN
0
Level comparator
Bus
Interrupt
45
MB90230 Series
12.Watch dog Timer and Timebase Timer
The watchdog timer consists of a 2-bit watchdog counter using carry signals from an 18-bit timebase counter
as the clock source, a control register, and a watchdog reset control section. The timebase timer consists of
an 18-bit timer and an interval interrupt control circuit.
(1) Register Configuration
bit
Address:
0000A9H, A8H
(2) Block Diagram
TBTC
TBC1
TBC0
TBR
MC-16 bus
2
TBIE
F
TBOF
Timebase
interrupt
WTC
WT1
WT0
WTE
AND
15
87 0
TBTC WTC
12
2
14
Selector
S
QR
Selector
2
16
2
18
2
TBTRES
2-bit counter
CLR
Timebase timer
OF
Clock input
2142162172
Watchdog reset
generator
CLR
Timebase timer control register
Oscillation clock
18
WDGRST
To internal reset generator
46
PONR
STBR
WRST
ERST
SRST
From power-on occurrence
From hardware standby
control circuit
RST pin
From RST bit in STBYC register
MB90230 Series
13. Delay Interruupt Generation Module
The delayed interrupt generation module is used to generate an interrupt for task switching. Using this module
allows an interrupt request to the F
(1) Register Configuration
2
MC-16F CPU to be generated or canceled by software.
bit
Delayed interrupt source
generate/release register
Address: 00009F
Read/write →
Initial value →
H
15 14 13 12 11 10 9 8
———————R0
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(R/W)
(0)
(2) Block Diagram
Delayed interrupt source generate/release decoder
MC-16 bus
2
14.
Clock Output Control Register
F
Interrupt source latch
The clock output control register outputs the output from the communication prescaler to the pin.
(1) Register Configuration
DIRR
Clock control register
bit
Address: 00002E
Read/write →
Initial value →
15 14 13 12 11 10 9 8
H
— — — — — CKEN FRQ1 FRQ0
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(0)
(R/W)
(0)
(R/W)
CLKR
(0)
47
MB90230 Series
15.Low-power Consumption Control Circuit
The low-power consumption control circuit consists of a low-power consumption control register, clock generator,
standby status control circuit, and gear divider circuit. These internal circuits implements the sleep, stop, and
hardware standby modes as well as the clock gear function. The gear function allows the machine clock cycle
to be selected as a division of the frequency of crystal oscillation or external clock input by 1, 2, 4, or 16.
(1) Register Configuration
Address: 0000A0
(2) Block Diagram
STBYC
CLK1
CLK0
MC-16 bus
2
F
SLP
STP
bit
15
H
Gear divider circuit
1/1 1/2 1/4 1/16
Selector
Standby control circuit
RST Clear HST start
87 0
STBYC
CPU clock
generator
Resource clock
generator
Standby control register
Oscillation clock
CPU clock
Resource clock
HST pin
Interrupt request or RST
48
OSC1
OSC0
SPL
RST
0
2
16
2
Selector
Pin high-impedance control circuit
Internal reset generator
17
2
18
2
Clock input
Time-base timer
14
16217218
2
2
Pin HI-Z
RST pin
Internal RST
To watchdog timer
WDGRST
ELECTRICAL CHARACTERISTICS
■
1. Absolute Maximum Ratings
Parameter
Power supply voltage
Input voltage
Output voltage
“L” level output current I
Symbol
V
CC VSS – 0.3 VSS + 7.0 V
AVCC, AVSS
AVRH, AVRL
2
I*
V
2
V
O*
OL 20 mA
MB90230 Series
Value
Min. Max.
CC – 0.3*
V
1
VSS – 0.3 VCC + 0.3 V
VSS – 0.3 VCC + 0.3 V
VSS + 7.0 V
(VSS = 0.0 V)
Unit Remarks
“L” level average output current I
“L” level total output current ΣI
OLAV —4mA
OL 50 mA
“H” level output current IOH –10 mA
“H” level average output current I
“H” level total output current ΣI
OHAV —–4mA
OH —–50mA
Power consumption PD —400mW
Operating temperature T
Storage temperature T
*1: AVRH, AVRL, or AV
CC must not exceed VCC.
A –40 +70 °C
STG –55 +150 °C
AVSS and AVRH must not exceed AVRH and AVCC, respectively.
V
CC ≥ AVCC ≥ AVRH > AVRL ≥ AVSS ≥ VSS
*2: VI or VO must not exceed “VCC + 0.3 V.”
WARNING:
Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for exter nded periods may affect
device reliability.
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Symbol
Value
Unit Remarks
Min. Max.
Power supply voltage V
Operating temperature T
CC
4.75 5.25 V During normal operation
3.0 5.5 V In stop mode
A –40 +70 °C
49
MB90230 Series
3. DC Characteristics
Parameter Symbol
V
“H” level input
voltage
V
V
VIL *1
“L” level input
voltage
V
V
“H” level output
voltage
“L” level output
voltage
V
V
IH *1
IHS *2 0.8 VCC —VCC + 0.3 V Hysteresis input
IHM *3 VCC – 0.3 — VCC + 0.3 V MD0 to 2
ILS *2 VSS – 0.3 — 0.2 VCC V Hysteresis input
ILM *3 VSS – 0.3 — VSS + 0.3 V MD0 to 2
OH *1, *2
OL *1, *2
Pin
name
Condition
V
CC = 5.0 V±5%
V
CC = 5.0 V±5%
V
CC = 4.75 V
I
OH = –2.0 mA
CC = 4.75 V
V
IOL = 1.8 mA
(VCC = 5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Unit Remarks
Min. Typ. Max.
CC —VCC + 0.3 V
0.7 V
SS – 0.3 — 0.3 VCC V
V
2.4
——V
——0.4V
Input leakage
current
Power supply
current
IH
I
I
CC
I
CCS — 15 25 mA In sleep mode
*1, *2,
*3
VCC
VSS + 4.75 V
<V
I <VCC
VCC = 5.0 V±5%
fc = 16 MHz
–10 — 10 µA
—4880mA
ICCH —10—µA In stop mode
Other
Input capacity C
IN
than V
CC
——10—pF
and VSS
Open-drain
output leakage
current
I
LEAK *4 — — 0.1 10 µA
(N-channel Tr
OFF)
Pull-up current I
PULL *5 — –250 — –50 µA
*1: CMOS I/O pin (Other than hysteresis pins)
*2: Hysteresis input pins: P46/TRG, P70/ATG
, P71/ESI, P80/INT0, P81/INT1, P82/OUT0/INT2, P83/OUT1/INT3,
P90/IN0, P91/IN1, P92/IN2, P93/IN3/CKOT, P94/SIN0, P96/SCK0, PA0/SIN1,
PA2/SCK1, PA3/SIN2, PA5/SCK2
*3: Mode pins MD2 to MD0
*4: Open-drain pins P94 to P96 and PA0 to PA5: Set by registers
*5: Pins with pull-up resistor RST
and P00 to P27: Set by registers
50
4. AC Characteristics
(1) Clock Timing Standards
Parameter
(V
CC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Symbol Pin name Condition
MB90230 Series
Value
Unit Remarks
Min. Max.
Clock frequency f
Clock cycle time t
Input clock pulse width
Input clock rising/falling
time
C
C
WH
P
PWL
cr
t
tcf
X0
X1
X0
X1
V
CC = 5.0 V ±5% 1 16 MHz
CC = 5.0 V ±5% 62.5 — ns
V
X0 VCC = 5.0 V ±5% 25.0 — ns Duty = 60%
X0 — 5 10 ns
tc
0.8 VCC
0.2 VCC
PWH PWL
tcf tcr
51
MB90230 Series
(2) Reset, Hardware Standby, and Trigger Input Standards
Parameter
Symbol
Pin
name
Condition
(V
CC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Unit Remarks
Min. Max.
Reset input time t
Hardware standby input time t
RSTL RST — 5 — Machine cycle*
HSTL HST — 5 — Machine cycle*
A/D start trigger input time tATGX ATG — 5 — Machine cycle*
PPG start trigger input time t
Input capture input trigger t
*Machine cycle: t
CYC = 1/machine clock = 1/(fC ÷ N)
PPGL TRG — 5 — Machine cycle*
INP
IN0 to
IN3
f
C: Oscillation frequency
— 5 — Machine cycle*
N: Gear divide ratio (1, 2, 4, 16)
Note: Clock input is required during reset.
The machine cycle at hardware standby input is set to 1/32 divided oscillation.
tRSTL, tHSTL, tINP
RST
HST
ATG
TRG
IN0 to IN3
tATGX, tPPGT
52
(3) Power-on Reset
Parameter
(V
CC = +5.0 V ±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Symbol Pin name Condition
MB90230 Series
Value
Unit Remarks
Min. Max.
Power supply riseing time t
Power-off time t
Vcc
Keep in mind that abrupt changes in supply voltage may cause a power-on reset.
Vcc 5 V
3 V
Vss
R
—50ms
Vcc —
OFF 1—ms
R
t
4.5 V
0.2 V
t
OFF
It is recommended to keep the
rising speed of the supply voltage
RAM data refined
at 50 mV/ms or slower.
53
MB90230 Series
(4) UART Timing
Parameter
Symbol
Pin
name
(V
CC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Condition
Unit Remarks
Min. Max.
Serial clock cycle time t
SCK ↓ → SOT delay time t
SCYC —
SLOV — –80 80 ns
Internal clock
operation output
Valid SIN → SCK ↑ t
SCK ↑ → Valid SIN hold time t
Serial clock “H” pulse width t
Serial clock “L” pulse width t
IVSH — 100 — ns
SHIX —60—ns
SHSL —
SLSH —4 tCYC —ns
pin: C
L = 80 pF
External clock
SCK ↓ → SOT delay time t
Valid SIN → SCK ↑ t
SCK ↑ → Valid SIN hold time t
SLOV ——150ns
IVSH —60—ns
SHIX —60—ns
operation output
L = 80 pF
pin: C
Notes: • These AC characteristics assume the CLK synchronous mode.
•C
L is the value for load capacity applied to the pin under testing.
•t
CYC is the machine cycle (in nanoseconds).
• Internal shift clock mode
tSCYC
SCK
0.8 V
2.4 V
8 t
CYC —ns
4 t
CYC —ns
0.8 V
SOT
SIN
• External shift clock mode
SCK
SOT
SIN
tSLOV
2.4 V
0.8 V
tIVSH
2.4 V
0.8 V
tSLSH
0.8 V 0.8 V
tSLOV
2.4 V
0.8 V
tIVSH
2.4 V
0.8 V
2.4 V
tSHIX
2.4 V
0.8 V
tSHSL
2.4 V
tSHIX
2.4 V
0.8 V
54
(5) Extended Serial I/O Timing
Parameter
Symbol
Pin
name
MB90230 Series
(V
CC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Condition
Value
Unit Remarks
Min. Max.
Serial clock cycle time t
SCK ↓ → SOT delay time t
Valid SIN → SCK ↑ t
SCK ↑ → Valid SIN hold time t
Serial clock “H” pulse width t
Serial clock “L” pulse width t
SCK ↓ → SOT delay time t
Valid SIN → SCK ↑ t
SCK ↑ → Valid SIN hold time t
Notes: • C
L is the value for load capacity applied to the pin under testing.
•tCYC is the machine cycle (in nanoseconds).
• Internal shift clock mode
SCK
0.8 V
SCYC —
SLOV —50—ns
Internal clock
CYC —ns
8 t
operation output
pin: C
IVSH —1 tCYC —ns
SHIX —1 tCYC —ns
SHSL —
SLSH —250—ns
L = 80 pF
250 — ns
External clock:
2 MHz max.
External clock
SLOV —2 tCYC —ns
IVSH —1 tCYC —ns
SHIX —2 tCYC —ns
tSCYC
operation output
pin: C
L = 80 pF
2.4 V
0.8 V
SOT
SIN
• External shift clock mode
SCK
SOT
SIN
tSLOV
2.4 V
0.8 V
tIVSH
2.4 V
0.8 V
tSLSH
0.8 V 0.8 V
tSLOV
2.4 V
0.8 V
tIVSH
2.4 V
0.8 V
2.4 V
tSHIX
2.4 V
0.8 V
tSHSL
2.4 V
tSHIX
2.4 V
0.8 V
55
MB90230 Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +5.0 V ± 5%, AVSS = VSS = 0.0 V, +3.0 V ≤ AVRH – AVRL, TA = –40°C to +70°C)
Parameter
Symbol Pin name
Value
Unit
Min. Typ. Max.
Resolution
—1010bit
Total error — — ±3.0 LSB
——
Linearity error — — ±2.0 LSB
Differential linearity error — — ±1.5 LSB
Zero transition voltage V
OT
–1.5 +0.5 +2.5 LSB
AN0 to AN7
Full-scale transition voltage V
FST AVRH –4.5 AVRH –1.5 AVRH +0.5 LSB
Conversion time — fC = 16 MHz 5.00 — — µs
Analog port input current I
AIN
——10µA
AN0 to AN7
Analog input voltage
—
AVRH AVRL — AV
AVRL — AVRH V
CC V
Reference voltage
AVRL 0 — AVRH V
Power supply current
A
I
AVCC
—5—mA
IAS ——5*µA
Reference voltage supply
current
R
AVRH
RS ——5*µA
I
—200—µA
I
Variation between channels — AN0 to AN7 — — 4 LSB
* :Current applied in CPU stop mode with the A/D converter inactive (V
CC = AVCC = AVRH = 5.5 V).
Notes: • The error becomes larger as |AVRH–AVRL| becomes smaller.
• Use the output impedance of the external circuit for analog input under the following conditions: External
circuit output impedance < Approx. 7 kΩ
• If the output impedance the external circuit is too high, the analog voltage sampling time may be insufficient.
(Sampling time = 3.0 µs at a machine clock frequency of 16 MHz)
56
• Analog Input Circuit Mode
Analog input
RON2 + RON2 = Approx. 3 kΩ
C
0 = Approx. 60 pF
C
1 = Approx. 4 pF
Note: The values shown here are reference values.
RON1
RON2
C0
Comparator
1
C
MB90230 Series
6. A/D Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 10, analog voltage can be divided into 2
• Total error
Difference between actual and logical v alues. This error is caused by a zero tr ansition error, full-scale transition
error, linearity error, differential linearity error, or by noise.
• Linearity error
The deviation of the straight line connecting the ze ro transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1111” ↔
“11 1111 1110”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
10
= 1024
11 1111 1111
Digital output
11 1111 1110
•
•
•
•
•
•
•
•
•
•
•
00 0000 0010
00 0000 0001
00 0000 0000
(1LSB × N + VOT)
V
OT VNT V(N+1)T
V
1LSB
Linearity error
Differential linearity error =
FST − VOT
=
1022
VNT − (1LSB × N + VOT )
=
V
( N+1)T − VNT
Linearity error
1LSB
1LSB
− 1
(LSB)
(LSB)
Analog input
V
FST
57
MB90230 Series
7. D/A Converter Electrical Characteristics
(AVCC = VCC = +5.0 V±5%, AVSS = VSS = 0.0 V, TA = –40°C to +70°C)
Parameter
Resolution — — — 8 8 bit
Differential linearity error — — — — ±0.9 LSB
Conversion time — — — 10* 20* µs
Analog output impedance — — — 28 — KΩ
*: A load capacity of 20 pF is assumed.
Symbol Pin name
Min. Typ. Max.
Value
Unit
58
8. Serial E2PROM Interface Timing
(1) E2PROM interface at an operation clock frequency of 1 MHz
(V
CC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Parameter Symbol
Operation cycle t
Min. Typ. Max.
SK 1.0 — — µs
Value
MB90230 Series
Unit Remarks
Clock “H” time t
Clock “L” time t
SKH 0.4 0.5 — µs
SKL 0.4 0.5 — µs
ECS setup time tCSS 0.3 — — µs
ECS hold time t
EDO data decision time t
CSH 0.0 — — µs
PD 0.3 — — µs
EDO output hold time tOH 0.5 — — µs
EDI setup time t
EDI hold time t
DIS 0.0 — — µs
DIH 0.4 — — µs
READY ↑ → ECS ↓ tRCSH 0.4 — — µs
ECS “L” time t
2
(2) E
PROM interface at an operation clock frequency of 2 MHz
CSL 0.8 1.0 — µs
(V
CC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Parameter Symbol
Unit Remarks
Min. Typ. Max.
Operation cycle t
Clock “H” time t
SK 0.5 — — µs
SKH 0.2 0.25 — µs
Clock “L” time tSKL 0.2 0.25 — µs
ECS setup time t
ECS hold time t
CSS 0.15 — — µs
CSH 0.0 — — µs
EDO data decision time tPD 0.15 — — µs
EDO output hold time t
EDI setup time t
OH 0.25 — — µs
DIS 0.0 — — µs
EDI hold time tDIH 0.2 — — µs
READY ↑ → ECS ↓ t
ECS “L” time t
RCSH 0.2 — — µs
CSL 0.4 0.5 — µs
59
MB90230 Series
tSKH
ESK
tSK
tSKL
EDO
ECS
EDI
Input data Input data
ECS
DO
(E2PROM output)
tCSS
tPD
tCSL
Hi-z
tOH
tDIS
Determined dataDetermined data
tCSH
tDIH
tST
BUSY READY
60
MB90230 series E
ECS
ESK
EDO
EDI
2
PROM
ECS
ESK
EDI
EDO
MB90230 Series
INSTRUCTIONS (412 INSTRUCTIONS)
■
Table 1 Description of Instruction Table
Item Description
Mnemonic Upper-case letters and symbols: Described directry in assembly code
Lower-case letters: Replaced when described in assembly code
Numbers after lower-case letters: Indicates the bit width within the code
# Indicates the number of bytes
~ Indicates the number of cycles
See Table 4 for details about meanings of letters in items.
B Indicates the compensation value for calculating the number of actual cycles during
execution of instruction.
The number of actual cycles during execution of instruction is summed with the value in
the “cycles” column.
Operation Indicates operation of instruction.
LH Indicates special operations involving the bits 15 through 08 of the accumulator.
Z: Transfers “0”
X: Extends before transferring
—: No transfer
AH Indicates special operations involving the high-order 16 bits in the accumulator.
*: Transfers from AL to AH
—: No transfer
Z: Transfers 00
X: Transfers 00H or FFH to AH by extending AL
I Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky
S
T
N
Z
V
C
RMW Indicates whether the instruction is a read-modify-write instruction (a single instruction
bit), N (negative), Z (zero), V (overflow), and C (carry).
*: Changes due to execution of instruction.
—: No change.
S: Set by execution of instruction.
R: Reset by execution of instruction.
that reads data from memory, etc., processes the data, and then writes the result to
memory.).
*: Instruction is a read-modify-write instruction
—: Instruction is not a read-modify-write instruction
Note: Cannot be used for addresses that have different meanings depending on
whether they are read or written.
H to AH.
61
MB90230 Series
Table 2 Explanation of Symbols in Table of Instructions
Symbol Description
A 32-bit accumulator
The number of bits used varies according to the instruction.
Byte: Low order 8 bits of AL
Word: 16 bits of AL
Long: 32 bits of AL, AH
AH High-order 16 bits of A
AL Low-order 16 bits of A
SP Stack pointer (USP or SSP)
PC Program counter
SPCU Stack pointer upper limit register
SPCL Stack pointer lower limit register
PCB Program bank register
DTB Data bank register
ADB Additional data bank register
SSB System stack bank register
USB User stack bank register
SPB Current stack bank register (SSB or USB)
DPR Direct page register
brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2 DTB, ADB, SSB, USB, DPR, SPB
Ri R0, R1, R2, R3, R4, R5, R6, R7
RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj RW0, RW1, RW2, RW3
RLi RL0, RL1, RL2, RL3
dir
addr16
addr24
addr24 0 to 15
addr24 16 to 23
io I/O area (000000
#imm4
#imm8
#imm16
#imm32
ext (imm8)
disp8
disp16
bp Bit offset value
vct4
vct8
( )b Bit address
rel
ear
eam
rlst Register list
Compact direct addressing
Direct addressing
Physical direct addressing
Bits 0 to 15 of addr24
Bits 16 to 23 of addr24
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
8-bit displacement
16-bit displacement
Vector number (0 to 15)
Vector number (0 to 255)
Branch specification relative to PC
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
H to 0000FFH)
62
Table 3 Effective Address Fields
MB90230 Series
Code Notation Address format
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
@RW0
@RW1
@RW2
@RW3
@RW0 +
@RW1 +
@RW2 +
@RW3 +
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Register direct
“ea” corresponds to byte, word, and
long-word types, starting from the
left
Register indirect 0
Register indirect with post-increment 0
Register indirect with 8-bit
displacement
Register indirect with 16-bit
displacemen
Number of bytes in
address extemsion*
—
1
2
1C
1D
1E
1F
* :The number of bytes for address extension is indicated by the “+” symbol in the “#” (number of bytes) column in
the Table of Instructions.
@RW0 + RW7
@RW1 + RW7
@PC + dip16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
63
MB90230 Series
Table 4 Number of Execution Cycles for Each Form of Addressing
Code Operand
00 to 07 Ri
RWi
RLi
08 to 0B @RWj 1
0C to 0F @RWj + 4
10 to 17 @RWi + disp8 1
18 to 1B @RWj + disp16 1
1C
1D
1E
1F
* :“(a)” is used in the “cycles” (number of cycles) column and column B (correction value) in the Table of Instructions.
Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles
Operand
Internal register + 0 + 0 + 0
Internal RAM even address + 0 + 0 + 0
@RW0 + RW7
@RW1 + RW7
@PC + dip16
@addr16
Number of execution cycles for each from of addressing
Listed in Table of Instructions
(b)* (c)* (d)*
byte word long
(a)*
2
2
2
1
Internal RAM odd address + 0 + 1 + 2
Even address not in internal RAM + 1 + 1 + 2
Odd address not in internal RAM + 1 + 3 + 6
External data bus (8 bits) + 1 + 3 + 6
* :“(b)”, “(c)”, and “(d)” are used in the “cycles” (number of cycles) column and column B (correction value) in the
Table of Instructions.
64
MB90230 Series
Table 6 Transfer Instructions (Byte) [50 Instructions]
Mnemonic # ~ B Operation
byte (A) ← (dir)
(b)
2
MOV A, dir
MOV A, addr16
MOV A, Ri
MOV A, ear
MOV A, eam
MOV A, io
MOV A, #imm8
MOV A, @A
MOV A, @RLi+disp8
MOV A, @SP+disp8
MOVP A, addr24
MOVP A, @A
MOVN A, #imm4
MOVX A, dir
MOVX A, addr16
MOVX A, Ri
MOVX A, ear
MOVX A, eam
MOVX A, io
MOVX A, #imm8
MOVX A, @A
MOVX A,@RWi+disp8
MOVX A, @RLi+disp8
MOVX A, @SP+disp8
MOVPXA, addr24
MOVPXA, @A
2
3
1
2
2+
2
2
2
3
3
5
2
1
2
3
2
2
2+
2
2
2
2
3
3
5
2
2
1
1
2+ (a)
2
2
2
6
3
3
2
1
2
2
1
1
2+ (a)
2
2
2
3
6
3
3
2
byte (A) ← (addr16)
(b)
byte (A) ← (Ri)
0
byte (A) ← (ear)
0
byte (A) ← (eam)
(b)
byte (A) ← (io)
(b)
byte (A) ← imm8
0
byte (A) ← ((A))
(b)
byte (A) ← ((RLi))+disp8)
(b)
byte (A) ← ((SP)+disp8)
(b)
byte (A) ←(addr24)
(b)
byte (A) ← ((A))
(b)
byte (A) ← imm4
0
byte (A) ← (dir)
(b)
byte (A) ← (addr16)
(b)
byte (A) ← (Ri)
0
byte (A) ← (ear)
0
byte (A) ← (eam)
(b)
byte (A) ← (io)
(b)
byte (A) ← imm8
0
byte (A) ← ((A))
(b)
byte (A) ← ((RWi))+disp8)
(b)
byte (A) ← ((RLi))+disp8)
(b)
byte (A) ← ((SP)+disp8)
(b)
byte (A) ←(addr24)
(b)
byte (A) ← ((A))
(b)
LH AH I S T N Z V C RMW
–
–
–
*
*
–
–
–
*
Z
*
Z
*
Z
*
Z
*
Z
*
Z
*
Z
–
Z
*
Z
*
Z
*
Z
–
Z
*
Z
*
X
*
X
*
X
*
X
*
X
*
X
*
X
–
X
*
X
*
X
*
X
*
X
–
X
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
R
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV dir, A
MOV addr16, A
MOV Ri, A
MOV ear, A
MOV eam, A
MOV io, A
MOV @RLi+disp8, A
MOV @SP+disp8, A
MOVP addr24, A
MOV Ri, ear
MOV Ri, eam
MOVP @A, Ri
MOV ear, Ri
MOV eam, Ri
MOV Ri, #imm8
MOV io, #imm8
MOV dir, #imm8
MOV ear, #imm8
MOV eam, #imm8
MOV @AL, AH
XCH A, ear
XCH A, eam
XCH Ri, ear
XCH Ri, eam
For an explanation of “(a)” and “(b)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
2
3
1
2
2+
2
3
3
5
2
2+
2
2
2+
2
3
3
3
3+
2
2
2+
2
2+
2
1
2
2+ (a)
2
6
3
3
2
3+ (a)
3
3
3+ (a)
2
3
3
2
2+ (a)
2
3
3+ (a)
4
5+ (a)
(b)
0
0
(b)
(b)
(b)
(b)
(b)
0
(b)
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2× (b)
0
2× (b)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)) +disp8) ← (A)
byte ((SP)+disp8) ← (A)
byte (addr24) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte ((A)) ← (Ri)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
byte (dir) ← (A)
(b)
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Z
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
–
–
–
–
*
–
–
–
*
–
–
–
–
–
–
–
–
–
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
–
–
–
–
*
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
–
–
–
65
MB90230 Series
Table 7 Transfer Instructions (Word) [40 Instructions]
Mnemonic # ~ B Operation
MOVW A, dir
MOVW A, addr16
MOVW A, SP
MOVW A, RWi
MOVW A, ear
MOVW A, eam
MOVW A, io
MOVW A, @A
MOVW A, #imm16
MOVW A, @RWi+disp8
MOVW A, @RLi+disp8
MOVW A, @SP+disp8
MOVPWA, addr24
MOVPWA, @A
MOVW dir, A
MOVW addr16, A
MOVW SP, # imm16
MOVW SP, A
MOVW RWi, A
MOVW ear, A
MOVW eam, A
MOVW io, A
MOVW @RWi+disp8, A
MOVW @RLi+disp8, A
MOVW @SP+disp8, A
MOVPWaddr24, A
MOVPW@A, RWi
MOVW RWi, ear
MOVW RWi, eam
MOVW ear, RWi
MOVW eam, RWi
MOVW RWi, #imm16
MOVW io, #imm16
MOVW ear, #imm16
MOVW eam, #imm16
2
3
1
1
2
2+
2
2
3
2
3
3
5
2
2
3
4
1
1
2
2+
2
2
3
3
5
2
2
2+
2
2+
3
4
4
4+
2
2
2
1
1
2+ (a)
2
2
2
3
6
3
3
2
2
2
2
2
1
2
2+ (a)
2
3
6
3
3
3
2
3+ (a)
3
3+ (a)
2
3
2
2+ (a)
(c)
word (A) ← (dir)
(c)
word (A) ← (addr16)
0
word (A) ← (SP)
0
word (A) ← (RWi)
0
word (A) ← (ear)
(c)
word (A) ← (eam)
(c)
word (A) ← (io)
(c)
word (A) ← ((A))
0
word (A) ← imm16
(c)
word (A) ← ((RWi) +disp8)
(c)
word (A) ← ((RLi) +disp8)
(c)
word (A) ← ((SP) +disp8
(c)
word (A) ← (addr24)
(c)
word (A) ← ((A))
(c)
word (dir) ← (A)
(c)
word (addr16) ← (A)
0
word (SP) ← imm16
0
word (SP) ← (A)
0
word (RWi) ← (A)
0
word (ear) ← (A)
(c)
word (eam) ← (A)
(c)
word (io) ← (A)
(c)
word ((RWi) +disp8) ← (A)
(c)
word ((RLi) +disp8) ← (A)
(c)
word ((SP) +disp8) ← (A)
(c)
word (addr24) ← (A)
(c)
word ((A)) ← (RWi)
0
word (RWi) ← (ear)
(c)
word (RWi) ← (eam)
0
word (ear) ← (RWi)
(c)
word (eam) ← (RWi)
0
word (RWi) ← imm16
(c)
word (io) ← imm16
0
word (ear) ← imm16
(c)
word (eam) ← imm16
LH AH I S T N Z V C RMW
–
*
–
–
–
*
*
–
–
–
–
*
–
–
–
*
*
–
–
–
–
*
–
–
–
*
*
–
–
–
–
*
–
–
–
*
*
–
–
–
–
*
–
–
–
*
*
–
–
–
–
*
–
–
–
*
*
–
–
–
–
*
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
*
–
–
–
*
*
–
–
–
–
*
–
–
–
*
*
–
–
–
–
*
–
–
–
*
*
–
–
–
–
*
–
–
–
*
*
–
–
–
–
*
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW @AL, AH
XCHW A, ear
XCHW A, eam
XCHW RWi, ear
XCHW RWi, eam
Note: For an explanation of “(a)” and “(c)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual
Cycles.”
66
2
2
2+
2
2+
2
3
3+ (a)
4
5+ (a)
(c)
0
2× (c)
0
2× (c)
word ((A)) ← (AH)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MB90230 Series
Table 8 Transfer Instructions (Long Word) [11 Instructions]
Mnemonic # ~ B Operation
MOVL A, ear
MOVL A, eam
MOVL A, # imm32
MOVL A, @SP + disp8
MOVPL A, addr24
MOVPL A, @A
MOVPL@A, RLi
MOVL @SP + disp8, A
MOVPL addr24, A
MOVL ear, A
MOVL eam, A
For an explanation of “(a)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
2
2+
5
3
5
2
2
3
5
2
2+
1
3+ (a)
3
4
4
3
5
4
4
2
3+ (a)
0
long (A) ← (ear)
(d)
long (A) ← (eam)
0
long (A) ← imm32
(d)
long (A) ← ((SP) +disp8)
(d)
long (A) ← (addr24)
(d)
long (A) ← ((A))
(d)
long ((A)) ← (RLi)
(d)
long ((SP) + disp8) ← (A)
(d)
long (addr24) ← (A)
0
long (ear) ← (A)
(d)
long (eam) ← (A)
LH AH I S T N Z V C RMW
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
67
MB90230 Series
Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
Mnemonic # ~ B Operation
ADD A, #imm8
ADD A, dir
ADD A, ear
ADD A, eam
ADD ear, A
ADD eam, A
ADDC A
ADDC A, ear
ADDC A, eam
ADDDC A
SUB A, #imm8
SUB A, dir
SUB A, ear
SUB A, eam
SUB ear, A
SUB eam, A
SUBC A
SUBC A, ear
SUBC A, eam
SUBDC A
ADDW A
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam
2
2
2
2+
2
2+
1
2
2+
1
2
2
2
2+
2
2+
1
2
2+
1
1
2
2+
3
2
2+
2
2+
2
3
2
3+ (a)
2
3+ (a)
2
2
3+ (a)
3
2
3
2
3+ (a)
2
3+ (a)
2
2
3+ (a)
3
2
2
3+ (a)
2
2
3+ (a)
2
3+ (a)
0
(b)
0
(b)
0
2× (b)
0
0
(b)
0
0
(b)
0
(b)
0
2× (b)
0
0
(b)
0
0
0
(c)
0
0
2× (c)
0
(c)
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
byte (A) ← (A) + (eam) + (C)
byte (A) ← (AH) + (AL) + (C) (Decimal)
byte (A) ← (A) – imm8
byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
byte (eam) ← (eam) – (A)
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
byte (A) ← (A) – (eam) – (C)
byte (A) ← (AH) – (AL) – (C) (Decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
LH AH I S T N Z V C RMW
Z
–
–
–
–
*
*
*
*
–
Z
–
–
–
–
*
*
*
*
–
Z
–
–
–
–
*
*
*
*
–
Z
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
*
Z
–
–
–
–
*
*
*
*
*
Z
–
–
–
–
*
*
*
*
–
Z
–
–
–
–
*
*
*
*
–
Z
–
–
–
–
*
*
*
*
–
Z
–
–
–
–
*
*
*
*
–
Z
–
–
–
–
*
*
*
*
–
Z
–
–
–
–
*
*
*
*
–
Z
–
–
–
–
*
*
*
*
–
Z
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
*
–
–
–
–
–
*
*
*
*
*
Z
–
–
–
–
*
*
*
*
–
Z
–
–
–
–
*
*
*
*
–
Z
–
–
–
–
*
*
*
*
–
Z
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
*
–
–
–
–
–
*
*
*
*
*
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
SUBW A
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
ADDL A, ear
ADDL A, eam
ADDL A, #imm32
SUBL A, ear
SUBL A, eam
SUBL A, #imm32
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
68
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
2
2
3+ (a)
2
2
3+ (a)
2
3+ (a)
5
6+ (a)
4
5
6+ (a)
4
0
0
(c)
0
0
2× (c)
0
(c)
0
(d)
0
0
(d)
0
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
word (A) ← (A) – (eam)
word (A) ← (A) – imm16
word (ear) ← (ear) – (A)
word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
word (A) ← (A) – (eam) – (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) – (ear)
long (A) ← (A) – (eam)
long (A) ← (A) – imm32
–
–
–
–
–
*
*
*
–
–
–
–
–
*
*
*
–
–
–
–
–
*
*
*
–
–
–
–
–
*
*
*
–
–
–
–
–
*
*
*
–
–
–
–
–
*
*
*
–
–
–
–
–
*
*
*
–
–
–
–
–
*
*
*
–
–
–
–
–
*
*
*
–
–
–
–
–
*
*
*
–
–
–
–
–
*
*
*
–
–
–
–
–
*
*
*
–
–
–
–
–
*
*
*
–
–
–
–
–
*
*
*
*
–
*
–
*
–
*
–
*
*
*
*
*
–
*
–
*
–
*
–
*
–
*
–
*
–
*
–
MB90230 Series
Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
Mnemonic # ~ B Operation
INC ear
INC eam
DEC ear
DEC eam
INCW ear
INCW eam
DECW ear
DECW eam
INCL ear
INCL eam
DECL ear
DECL eam
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ B Operation
CMP A
CMP A, ear
CMP A, eam
CMP A, #imm8
CMPW A
CMPW A, ear
CMPW A, eam
CMPW A, #imm16
2
2
2+
3+ (a)
2
2
2+
3+ (a)
2
2
2+
3+ (a)
2
2
2+
3+ (a)
2
4
2+
5+ (a)
2
4
2+
5+ (a)
Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]
1
2
2
2
2+
2+ (a)
2
2
1
2
2
2
2+
2+ (a)
3
2
0
2× (b)
0
2× (b)
0
2× (c)
0
2× (c)
0
2× (d)
0
2× (d)
0
0
(b)
0
0
0
(c)
0
byte (ear) ← (ear) +1
byte (eam) ← (eam) +1
byte (ear) ← (ear) –1
byte (eam) ← (eam) –1
word (ear) ← (ear) +1
word (eam) ← (eam) +1
word (ear) ← (ear) –1
word (eam) ← (eam) –1
long (ear) ← (ear) +1
long (eam) ← (eam) +1
long (ear) ← (ear) –1
long (eam) ← (eam) –1
byte (AH) – (AL)
byte (A) – (ear)
byte (A) – (eam)
byte (A) – imm8
word (AH) – (AL)
word (A) – (ear)
word (A) – (eam)
word (A) – imm16
LH AH I S T N Z V C RMW
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
LH AH I S T N Z V C RMW
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
CMPL A, ear
CMPL A, eam
CMPL A, #imm32
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
2
2+
5
3
4+ (a)
3
0
long (A) – (ear)
(d)
long (A) – (eam)
0
long (A) – imm32
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
69
MB90230 Series
Table 12 Unsigned Multiplication and Division Instructions (Word/Long Word) [11 Instructions]
Mnemonic # ~ B Operation
DIVU A
1
1
0
*
word (AH) /byte (AL)
LH AH I S T N Z V C RMW
–
–
–
–
–
–
–
*
*
–
Quotient → byte (AL) Remainder → byte (AH)
2
DIVU A, ear
2
0
*
word (A)/byte (ear)
–
–
–
–
–
–
–
*
*
–
Quotient → byte (A) Remainder → byte (ear)
6
DIVU A, eam
2+
3
*
word (A)/byte (eam)
*
–
–
–
–
–
–
–
*
*
–
Quotient → byte (A) Remainder → byte (eam)
DIVUW A, ear
4
2
0
*
long (A)/word (ear)
–
–
–
–
–
–
–
*
*
–
Quotient → w ord (A) Remainder → word (ear)
5
DIVUW A, eam
MULU A
MULU A, ear
MULU A, eam
MULUW A
MULUW A, ear
MULUW A, eam
2+
2+
2+
*
1
*
2
*
*
1
*
2
*
*
7
long (A)/word (eam)
*
Quotient → word (A) Remainder → word (eam)
8
9
10
11
12
13
byte (AH) × byte (AL) → word (A)
0
byte (A) × byte (ear) → word (A)
0
byte (A) × byte (eam) → word (A)
(b)
word (AH) × word (AL) → long (A)
0
word (A) × word (ear) → long (A)
0
word (A) × word (eam) → long (A)
(c)
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
For an explanation of “(b)” and “(c), refer to Table 5, “Correction Values for Number of Cycle Used to Calculate
Number of Actual Cycles.”
*1: 3 when dividing into zero, 6 when an overflow occurs, and 14 normally.
*2: 3 when dividing into zero, 5 when an overflow occurs, and 13 normally.
*3: 5 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 17 + (a) normally.
*4: 3 when dividing into zero, 5 when an overflow occurs, and 21 normally.
*5: 4 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 25 + (a) normally.
*6: (b) when dividing into zero or when an overflow occurs, and 2 × (b) normally.
*7: (c) when dividing into zero or when an overflow occurs, and 2 × (c) normally.
*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not 0.
*9: 3 when byte (ear) is zero, and 7 when byte (ear) is not 0.
*10: 4 + (a) when byte (eam) is zero, and 8 + (a) when byte (eam) is not 0.
*11: 3 when word (AH) is zero, and 11 when word (AH) is not 0.
*12: 3 when word (ear) is zero, and 11 when word (ear) is not 0.
*13: 4 + (a) when word (eam) is zero, and 12 + (a) when word (eam) is not 0.
70
MB90230 Series
Table 13 Signed Multiplication and Division Instructions (Word/Long Word) [11 Insturctions]
Mnemonic # ~ B Operation
DIV A
1
2
0
*
word (AH) /byte (AL)
LH AH I S T N Z V C RMW
Z
–
–
–
–
–
–
*
*
–
Quotient → byte (AL) Remainder → byte (AH)
DIV A, ear
2
2
0
*
word (A)/byte (ear)
Z
–
–
–
–
–
–
*
*
–
Quotient → byte (A) Remainder → byte (ear)
3
DIV A, eam
2+
6
*
word (A)/byte (eam)
*
Z
–
–
–
–
–
–
*
*
–
Quotient → byte (A) Remainder → byte (eam)
DIVW A, ear
DIVW A, eam
2
2+
*
5
*
long (A)/word (ear)
0
Quotient → w ord (A) Remainder → word (ear)
7
*
long (A)/word (eam)
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
4
Quotient → word (A) Remainder → word (eam)
MUL A
MUL A, ear
MUL A, eam
MUL W A
MUL W A, ear
MUL W A, eam
2+
2+
8
2
2
2
2
0
*
9
*
10
*
11
*
12
*
13
*
byte (AH) × byte (AL) → word (A)
0
byte (A) × byte (ear) → word (A)
(b)
byte (A) × byte (eam) → word (A)
0
word (AH) × word (AL) → long (A)
0
word (A) × word (ear) → long (A)
(b)
word (A) × word (eam) → long (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
For an explanation of “(b)” and “(c)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate
Number of Actual Cycles.”
*1: 3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally.
*2: 3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally.
*3: 4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally.
*4: When the dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally.
When the dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally.
*5: When the dividend is positive: 4 + (a) when dividing into zero, 11 + (a) or 30 + (a) when an overflow occurs,
and 31 + (a) normally.
When the dividend is negative: 4 + (a) when dividing into zero, 12 + (a) or 31 + (a) when an overflow occurs,
and 32 + (a) normally.
*6: (b) when dividing into zero or when an overflow occurs, and 2 × (b) normally.
*7: (c) when dividing into zero or when an overflow occurs, and 2 × (c) normally.
*8: 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10: 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.
*11: 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12: 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13: 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative.
Note: Which of the two values given for the number of execution cycles applies when an overflow error occurs in
a DIV or DIVW instruction depends on whether the overflow was detected before or after the operation.
71
MB90230 Series
Table 14 Logical 1 Instructions (Byte, Word) [39 Instructions]
Mnemonic # ~ B Operation
AND A, #imm8
AND A, ear
AND A, eam
AND ear, A
AND eam, A
OR A, #imm8
OR A, ear
OR A, eam
OR ear, A
OR eam, A
XOR A, #imm8
XOR A, ear
XOR A, eam
XOR ear, A
XOR eam, A
NOT A
NOT ear
NOT eam
ANDW A
ANDW A, #imm16
ANDW A, ear
ANDW A, eam
ANDW ear, A
ANDW eam, A
2
2
2+
2
2+
2
2
2+
2
2+
2
2
2+
2
2+
1
2
2+
1
3
2
2+
2
2+
2
2
3+ (a)
3
3+ (a)
2
2
3+ (a)
3
3+ (a)
2
2
3+ (a)
3
3+ (a)
2
2
3+ (a)
2
2
2
3+ (a)
3
3+ (a)
0
0
(b)
0
2× (b)
0
0
(b)
0
2× (b)
0
0
(b)
0
2× (b)
0
0
2× (b)
0
0
0
(c)
0
2× (c)
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
byte (eam) ← (eam) and (A)
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
byte (eam) ← (eam) or (A)
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
byte (eam) ← (eam) xor (A)
byte (A) ← not (A)
byte (ear) ← not (ear)
byte (eam) ← not (eam)
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
word (eam) ← (eam) and (A)
LH AH I S T N Z V C RMW
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
*
–
–
–
–
–
*
*
R
–
*
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
*
–
–
–
–
–
*
*
R
–
*
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
*
–
–
–
–
–
*
*
R
–
*
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
*
–
–
–
–
–
*
*
R
–
*
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
*
–
–
–
–
–
*
*
R
–
*
ORW A
ORW A, #imm16
ORW A, ear
ORW A, eam
ORW ear, A
ORW eam, A
XORW A
XORW A, #imm16
XORW A, ear
XORW A, eam
XORW ear, A
XORW eam, A
NOTW A
NOTW ear
NOTW eam
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
1
3
2
2+
2
2+
1
3
2
2+
2
2+
1
2
2+
2
2
2
3+ (a)
3
3+ (a)
2
2
2
3+ (a)
3
3+ (a)
2
2
3+ (a)
0
0
0
(c)
0
2× (c)
0
0
0
(c)
0
2× (c)
0
0
2× (c)
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
word (A) ← not (A)
word (ear) ← not (ear)
word (eam) ← not (eam)
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
*
–
–
–
–
–
*
*
R
–
*
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
*
–
–
–
–
–
*
*
R
–
*
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
*
–
–
–
–
–
*
*
R
–
*
72
MB90230 Series
Table 15 Logical 2 Instructions (Long Wor d) [6 Instructions]
Mnemonic # ~ B Operation
ANDL A, ear
ANDL A, eam
ORL A, ear
ORL A, eam
XORL A, ear
XORL A, eam
For an explanation of “(a)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic # ~ B Operation
NEG A
NEG ear
NEG eam
NEGW A
NEGW ear
NEGW eam
2
5
2+
6+ (a)
2
5
2+
6+ (a)
2
5
2+
6+ (a)
Table 16 Sign Inversion Instructions (Byte/Word) [6 Instructions]
1
2
2
2
2+
3+ (a)
1
2
2
2
2+
3+ (a)
0
(d)
0
(d)
0
(d)
0
0
2× (b)
0
0
2× (c)
long (A) ← (A) and (ear)
long (A) ← (A) and (eam)
long (A) ← (A) or (ear)
long (A) ← (A) or (eam)
long (A) ← (A) xor (ear)
long (A) ← (A) xor (eam)
byte (A) ← 0 – (A)
byte (ear) ← 0 – (ear)
byte (eam) ← 0 – (eam)
word (A) ← 0 – (A)
word (ear) ← 0 – (ear)
word (eam) ← 0 – (eam)
LH AH I S T N Z V C RMW
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
–
–
–
–
–
*
*
R
–
–
LH AH I S T N Z V C RMW
X
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
*
–
–
–
–
–
*
*
*
*
*
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
*
–
–
–
–
–
*
*
*
*
*
For an explanation of “(a)”, “(b)” and “(c)” and refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 17 Absolute Value Instructions (Byte/Word/Long Word) [3 Insturctions]
Mnemonic # ~ B Operation
ABS A
ABSW A
ABSL A
Mnemonic # ~ B Operation
NRML A, R0 2 * 0 long (A) ← Shifts to the position at
* :5 when the contents of the accumulator are all zeroes, 5 + (R0) in all other cases.
2
2
2
2
2
4
Table 18 Normalize Instructions (Long Word) [1 Instruction]
0
byte (A) ← absolute value (A)
0
word (A) ← absolute value (A)
0
long (A) ← absolute value (A)
which “1” was set first
byte (R0) ← current shift count
LH AH I S T N Z V C RMW
Z
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
–
LH AH I S T N Z V C RMW
––––*–––– –
73
MB90230 Series
Table 19 Shift Instructions (Byte/Word/Long Word) [27 Instructions]
Mnemonic # ~ B Operation
RORC A
ROLC A
RORC ear
RORC eam
ROLC ear
ROLC eam
ASR A, R0
LSR A, R0
LSL A, R0
ASR A, #imm8
LSR A, #imm8
LSL A, #imm8
ASRW A
LSRW A/SHRW A
LSL W A/SHLW A
ASRW A, R0
LSRW A, R0
LSLW A, R0
ASRW A, #imm8
LSRW A, #imm8
LSL W A, #imm8
ASRL A, R0
LSRL A, R0
LSLL A, R0
2
2
2
2+
2
2+
2
2
2
3
3
3
1
1
1
2
2
2
3
3
3
2
2
2
2
2
2
3+ (a)
2
3+ (a)
1
*
1
*
1
*
3
*
3
*
3
*
2
2
2
1
*
1
*
1
*
3
*
3
*
3
*
2
*
2
*
2
*
0
0
0
2× (b)
0
2× (b)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
byte (ear) ← Right rotation with carry
byte (eam) ← Right rotation with carry
byte (ear) ← Left rotation with carry
byte (eam) ← Left rotation with carry
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
byte (A) ← Arithmetic right barrel shift (A, imm8)
byte (A) ← Logical right barrel shift (A, imm8)
byte (A) ← Logical left barrel shift (A, imm8)
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
word (A) ← Arithmetic right barrel shift (A, R0)
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
word (A) ← Arithmetic right barrel shift (A, imm8)
word (A) ← Logical right barrel shift (A, imm8)
word (A) ← Logical left barrel shift (A, imm8)
long (A) ← Arithmetic right shift (A, R0)
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
LH AH I S T N Z V C RMW
–
–
–
–
–
*
*
–
*
–
–
–
–
–
–
*
*
–
*
–
–
–
–
–
–
*
*
–
*
*
–
–
–
–
–
*
*
–
*
*
–
–
–
–
–
*
*
–
*
*
–
–
–
–
–
*
*
–
*
*
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
–
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
–
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
R
*
–
*
–
–
–
–
–
–
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
–
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
–
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
–
*
*
–
*
–
ASRL A, #imm8
LSRL A, #imm8
LSLL A, #imm8
4
3
*
3
*
3
*
0
4
long (A) ← Arithmetic right shift (A, imm8)
0
long (A) ← Logical right barrel shift (A, imm8)
4
0
long (A) ← Logical left barrel shift (A, imm8)
–
–
–
–
*
*
*
–
–
–
–
–
*
*
*
–
–
–
–
–
–
*
*
–
For an explanation of “(a)” and “(b)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
*1: 3 when R0 is 0, 3 + (R0) in all other cases.
*2: 3 when R0 is 0, 4 + (R0) in all other cases.
*3: 3 when imm8 is 0, 3 + (imm8) in all other cases.
*4: 3 when imm8 is 0, 4 + (imm8) in all other cases.
74
*
–
*
–
*
–
MB90230 Series
Table 20 Branch 1 Instructions [31 Instructions]
Mnemonic # ~ B Operation
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BV rel
BNV rel
BT rel
BNT rel
BLT rel
BGE rel
BLE rel
BGT rel
BLS rel
BHI rel
BRA rel
JMP @A
JMP addr16
JMP @ear
JMP @eam
JMPP @ear *
JMPP @eam *
JMPP addr24
CALL @ear *
CALL @eam *
CALL addr16 *
CALLV #vct4 *
CALLP @ear *
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
2
2+
3
2
3
2+
4
4
2
4
2+
5
3
5
1
6
2
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
1
*
2
2
3
4+ (a)
3
4+ (a)
3
4
5+ (a)
5
5
7
2× (c)
2× (c)
2× (c)
Branch when (Z) = 1
0
Branch when (Z) = 0
0
Branch when (C) = 1
0
Branch when (C) = 0
0
Branch when (N) = 1
0
Branch when (N) = 0
0
Branch when (V) = 1
0
Branch when (V) = 0
0
Branch when (T) = 1
0
Branch when (T) = 0
0
Branch when (V) xor (N) = 1
0
Branch when (V) xor (N) = 0
0
( (V) xor (N) ) or (Z) = 1
0
( (V) xor (N) ) or (Z) = 0
0
Branch when (C) or (Z) = 1
0
Branch when (C) or (Z) = 0
0
Branch unconditionally
0
word (PC) ← (A)
0
word (PC) ← addr16
0
word (PC) ← (ear)
0
word (PC) ← (eam)
(c)
word (PC) ← (ear), (PCB) ← (ear +2)
0
word (PC) ← (eam), (PCB) ← (eam +2)
(d)
word (PC) ← ad24 0 to 15
0
(PCB) ← ad24 16 to 23
word (PC) ← (ear)
(c)
word (PC) ← (eam)
word (PC) ← addr16
(c)
Vector call linstruction
word (PC) ← (ear) 0 to 15,
(PCB) ← (ear) 16 to 23
CALLP @eam *
6
2+
8+ (a)
2
word (PC) ← (eam) 0 to 15,
*
(PCB) ← (eam) 16 to 23
CALLP addr24 *
7
4
7
2× (c)
word (PC) ← addr 0 to 15,
(PCB) ← addr 16 to 23
LH AH I S T N Z V C RMW
–
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–
For an e xplanation of “(a)”, “(c)” and “(d)”, refer to T able 4, “Number of Ex ecution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
*1: 3 when branching, 2 when not branching.
*2: 3 × (c) + (b)
*3: Read (word) branch address.
*4: W: Save (word) to stack; R: Read (word) branch address.
*5: Save (word) to stack.
*6: W: Save (long word) to W stack; R: Read (long word) branch address.
*7: Save (long word) to stack.
75
MB90230 Series
Table 21 Branch 2 Instructions [20 Instructions]
Mnemonic # ~ B Operation
CBNE A, #imm8, rel
CWBNE A, #imm16, rel
CBNE ear, #imm8, rel
CBNE eam, #imm8, rel
CWBNE ear , #imm16, rel
CWBNE eam, #imm16, rel
DBNZ ear, rel
DBNZ eam, rel
DWBNZ ear, rel
3
4
4
4+
5
5+
3
3+
3
1
*
1
*
1
*
3
*
1
*
3
*
2
*
4
*
2× (b)
2
*
4
*
Branch when byte (A) ≠ imm8
0
Branch when byte (A) ≠ imm16
0
Branch when byte (ear) ≠ imm8
0
Branch when byte (eam) ≠ imm8
(b)
Branch when word (ear) ≠ imm16
0
Branch when word (eam) ≠ imm16
(c)
Branch when byte (ear) =
0
(ear) – 1, and (ear) ≠ 0
Branch when byte (ear) =
(eam) – 1, and (eam) ≠ 0
Branch when word (ear) =
0
(ear) – 1, and (ear) ≠ 0
DWBNZ eam, rel
3+
14
2× (c)
Branch when word (eam) =
(eam) – 1, and (eam) ≠ 0
12
13
INT #vct8
INT addr16
INTP addr24
INT9
RETI
RETIQ *
6
LINK #imm8
2
3
4
1
1
2
14
11
8× (c)
6× (c)
9
6× (c)
8× (c)
6× (c)
6
2
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
5
Return from interrupt
*
(c)
At constant entry, save old
frame pointer to stack, set
5
new frame pointer, and
allocate local pointer area
UNLINK
1
(c)
4
At constant entry , retriev e old
frame pointer from stack.
5
RET *
RETP *
7
8
1
1
(c)
Return from subroutine
(d)
Return from subroutine
LH AH I S T N Z V C RMW
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
–
–
R
S
–
–
–
–
–
–
–
–
R
S
–
–
–
–
–
–
–
–
R
S
–
–
–
–
–
–
–
–
R
S
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
–
–
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
For an e xplanation of “(b)”, “(c)” and “(d)”, refer to T ab le 5, “Correction V alues for Number of Cycles Used to Calculate
Number of Actual Cycles.”
*1: 4 when branching, 3 when not branching
*2: 5 when branching, 4 when not branching
*3: 5 + (a) when branching, 4 + (a) when not branching
*4: 6 + (a) when branching, 5 + (a) when not branching
*5: 3 × (b) + 2 × (c) when an interrupt request is generated, 6 × (c) when returning from the interrupt.
*6: High-speed interr upt return instruction. When an interrupt request is detected during this instruction, the
instruction branches to the interrupt vector without performing stack operations when the interrupt is generated.
*7: Return from stack (word)
*8: Return from stack (long word)
76
MB90230 Series
Table 22 Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
Mnemonic # ~ B Operation
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
POPW A
POPW AH
POPW PS
POPW rlst
JCTX @A
AND CCR, #imm8
OR CCR, #imm8
MOV RP, #imm8
MOV ILM, #imm8
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam
ADDSP #imm8
ADDSP #imm16
2+
2+
1
1
1
2
1
1
1
2
1
2
2
2
2
2
2
2
3
3
3
3
3
*
3
3
3
2
*
9
3
3
2
2
3
2+ (a)
2
1+ (a)
3
3
word (SP) ← (SP) –2, ((SP)) ← (A)
(c)
word (SP) ← (SP) –2, ((SP)) ← (AH)
(c)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(c)
4
(SP) ← (SP) –2n, ((SP)) ← (rlst)
*
word (A) ← ((SP)), (SP) ← (SP) +2
(c)
word (AH) ← ((SP)), (SP) ← (SP) +2
(c)
word (PS) ← ((SP)), (SP) ← (SP) +2
(c)
4
(rlst) ← ((SP)) , (SP) ← (SP)
*
Context switch instruction
6× (c)
byte (CCR) ← (CCR) and imm8
0
byte (CCR) ← (CCR) or imm8
0
byte (RP) ← imm8
0
byte (ILM) ← imm8
0
word (RWi) ← ear
0
word (RWi) ← eam
0
word(A) ← ear
0
word (A) ← eam
0
word (SP) ← ext (imm8)
0
word (SP) ← imm16
0
LH AH I S T N Z V C RMW
–
–
–
–
–
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–
–
–
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–
–
*
–
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–
–
–
–
–
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–
–
–
–
–
–
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
–
–
*
*
*
*
*
*
*
–
–
–
*
*
*
*
*
*
*
–
–
–
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–
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*
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*
–
–
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–
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–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV A, brgl
MOV brg2, A
MOV brg2, #imm8
NOP
ADB
DTB
PCB
SPB
NCC
CMR
MOVW SPCU, #imm16
MOVW SPCL, #imm16
SETSPC
CLRSPC
BTSCN A
BTSCNSA
BTSCNDA
1
2
*
2
1
3
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
2
4
2
2
2
2
2
5
2
*
6
2
*
7
2
*
byte (A) ← (brgl)
0
byte (brg2) ← (A)
0
byte (brg2) ← imm8
0
No operation
0
Prefix code for AD space access
0
Prefix code for DT space access
0
Prefix code for PC space access
0
Prefix code for SP space access
0
Prefix code for no flag change
0
Prefix code for the common register bank
0
word (SPCU) ← (imm16)
0
word (SPCL) ← (imm16)
0
Stack check operation enable
0
Stack check operation disable
0
byte (A) ← position of “1” bit in word (A)
0
byte (A) ← position of “1” bit in word (A) × 2
0
byte (A) ← position of “1” bit in word (A) × 4
0
Z
*
–
–
–
*
–
–
–
–
–
*
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Z
–
–
–
–
–
Z
–
–
–
–
–
Z
–
–
–
–
–
For an explanation of “(a)” and “(c)”, refer to Tables 4 and 5.
*1: PCB, ADB, SSB, USB, and SPB: 1 cycle *4: Pop count × (c), or push count × (c)
DTB: 2 cycles *5: 3 when AL is 0, 5 when AL is not 0.
DPR: 3 cycles *6: 4 when AL is 0, 6 when AL is not 0.
*2: 3 + 4 × (pop count) *7: 5 when AL is 0, 7 when AL is not 0.
*3: 3 + 4 × (push count)
*
–
–
–
*
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
–
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
77
MB90230 Series
Table 23 Bit Manipulation Instructions [21 Instructions]
Mnemonic # ~ B Operation
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
SETB dir:bp
SETB addr16:bp
SETB io:bp
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
BBC dir:bp, rel
BBC addr16:bp, rel
BBC io:bp, rel
BBS dir:bp, rel
BBS addr16:bp, rel
BBS io:bp, rel
SBBS addr16:bp, rel
3
3
(b)
byte (A) ← (dir:bp) b
4
3
(b)
byte (A) ← (addr16:bp) b
3
3
(b)
byte (A) ← (io:bp) b
3
4
2× (b)
4
4
2× (b)
3
4
2× (b)
3
4
2× (b)
4
4
2× (b)
3
4
2× (b)
3
4
2× (b)
4
4
2× (b)
3
4
2× (b)
4
5
4
4
5
4
5
1
*
1
*
1
*
1
*
1
*
1
*
2
2× (b)
*
bit (dir:bp) b ← (A)
bit (addr16:bp) b ← (A)
bit (io:bp) b ← (A)
bit (dir:bp) b ← 1
bit (addr16:bp) b ← 1
bit (io:bp) b ← 1
bit (dir:bp) b ← 0
bit (addr16:bp) b ← 0
bit (io:bp) b ← 0
(b)
Branch when (dir:bp) b = 0
(b)
Branch when (addr16:bp) b = 0
(b)
Branch when (io:bp) b = 0
(b)
Branch when (dir:bp) b = 1
(b)
Branch when (addr16:bp) b = 1
(b)
Branch when (io:bp) b = 1
Branch when (addr16:bp) b = 1, bit = 1
LH AH I S T N Z V C RMW
Z
*
–
–
–
*
*
–
–
–
Z
*
–
–
–
*
*
–
–
–
Z
*
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
*
–
–
–
–
–
*
*
–
–
*
–
–
–
–
–
*
*
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
*
WBTS io:bp
WBTC io:bp
3
3
3
*
3
*
4
Wait until (io:bp) b = 1
*
4
Wait until (io:bp) b = 0
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
For an e xplanation of “(b)”, refer to Table 5, “Correction V alues for Number of Cycles Used to Calculate Number of
Actual Cycles.”
*1: 5 when branching, 4 when not branching
*2: 7 when condition is satisfied, 6 when not satisfied
*3: Undefined count
*4: Until condition is satisfied
78
MB90230 Series
Table 24 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
Mnemonic # ~ B Operation
SWAP
SWAPW
EXT
EXTW
ZEXT
ZEXTW
1
3
0
byte (A) 0 to 7 ← → (A) 8 to 15
1
2
0
word (AH) ← → (AL)
1
1
0
Byte code extension
1
2
0
Word code extension
1
1
0
Byte zero extension
1
2
0
Word zero extension
Table 25 String Instructions [10 Instructions]
Mnemonic # ~ B Operation
2
MOVS/MOVSI
MOVSD
SCEQ/SCEQI
SCEQD
FILS/FILSI
MOVSW/MOVSWI
MOVSWD
SCWEQ/SCWEQI
SCWEQD
2
2
2
2
2
2
2
2
2
5m +3
3
*
2
*
1
*
1
*
2
*
2
*
1
*
1
*
Byte transfer @AH+ ← @AL+, counter = RW0
*
3
Byte transfer @AH– ← @AL–, counter = RW0
*
4
*
Byte retrieval @AH+ – AL, counter = RW0
4
Byte retrieval @AH– – AL, counter = RW0
*
5
Byte filling @AH+ ← AL, counter = RW0
*
6
Word transfer @AH+ ← @AL+, counter = RW0
*
6
Word transfer @AH– ← @AL–, counter = RW0
*
7
*
Word retrieval @AH+ – AL, counter = RW0
7
Word retrieval @AH– – AL, counter = RW0
*
LH AH I S T N Z V C RMW
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
X
–
–
–
–
*
*
–
–
–
–
X
–
–
–
*
*
–
–
–
Z
–
–
–
–
R
*
–
–
–
–
Z
–
–
–
R
*
–
–
–
LH AH I S T N Z V C RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
*
*
*
*
–
FILSW/FILSWI
2
5m +3
8
Word filling @AH+ ← AL, counter = RW0
*
–
–
m: RW0 value (counter value)
*1: 3 when RW0 is 0, 2 + 6 × (RW0) for count out, and 6n + 4 when match occurs
*2: 4 when RW0 is 0, 2 + 6 × (RW0) in any other case
*3: (b) × (RW0)
*4: (b) × n
*5: (b) × (RW0)
*6: (c) × (RW0)
*7: (c) × n
*8: (c) × (RW0)
–
–
–
*
*
–
–
–
79
MB90230 Series
Table 26 Multiple Data Transfer Instructions [18 Instructions]
Mnemonic # ~ B Operation
1
MOVM @A, @RLi, #imm8
MOVM @A, eam, #imm8
MOVM addr16, @RLi, #imm8
MOVM addr16, eam, #imm8
MOVMW @A, @RLi, #imm8
MOVMW @A, eam, #imm8
MOVMW addr16, @RLi, #imm8
MOVMW addr16, eam, #imm8
MOVM @RLi, @A, #imm8
MOVM eam, @A, #imm8
MOVM @RLi, addr16, #imm8
MOVM eam, addr16, #imm8
MOVMW @RLi, @A, #imm8
MOVMW eam, @A, #imm8
MOVMW @RLi, addr16, #imm8
MOVMW eam, addr16, #imm8
MOVM bnk : addr16, *
bnk : addr16, #imm8
MOVMW bnk : addr16, *
bnk : addr16, #imm8
5
5
3
3+
5
5+
3
3+
5
5+
3
3+
5
5+
3
3+
5
5+
7
7
3
*
2
*
1
*
2
*
1
*
2
*
1
*
2
*
1
*
2
*
1
*
2
*
1
*
2
*
1
*
2
*
1
*
1
*
Multiple data trasfer byte ((A)) ← ((RLi))
*
3
Multiple data trasfer byte ((A)) ← (eam)
*
3
Multiple data trasfer byte (addr16) ← ((RLi))
*
3
Multiple data trasfer byte (addr16) ← (eam)
*
4
Multiple data trasfer word ((A)) ← ((RLi))
*
4
Multiple data trasfer word ((A)) ← (eam)
*
4
Multiple data trasfer word (addr16) ← ((RLi))
*
4
Multiple data trasfer word (addr16) ← (eam)
*
3
Multiple data trasfer byte ((RLi)) ← ((A))
*
3
Multiple data trasfer byte (eam) ← ((A))
*
3
Multiple data transfer byte ((RLi)) ← (addr16)
*
3
Multiple data transfer byte (eam) ← (addr16)
*
4
Multiple data trasfer word ((RLi)) ← ((A))
*
4
Multiple data trasfer word (eam) ← ((A))
*
4
Multiple data transfer word ((RLi)) ← (addr16)
*
4
Multiple data transfer word (eam) ← (addr16)
*
3
Multiple data transfer
*
byte (bnk:addr16) ← (bnk:addr16)
4
Multiple data transfer
*
word (bnk:addr16) ← (bnk:addr16)
LH AH I S T N Z V C RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*1: 5 + imm8 × 5, 256 times when imm8 is zero.
*2: 5 + imm8 × 5 + (a), 256 times when imm8 is zero.
*3: Number of transfers × (b) × 2
*4: Number of transfers × (c) × 2
*5:The bank register specified by “bnk” is the same as for the MOVS instruction.
–
–
–
–
–
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–
–
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–
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–
–
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–
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–
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80
ORDERING INFORMATION
■
Model Package Remarks
MB90230 Series
MB90233PFV-XXX
MB90234PFV-XXX
MB90234PFV
MB90W234ZFV
100-pin Plastic LQFP
(FPT-100P-M05)
100-pin Plastic LQFP
(FPT-100P-M05)
100-pin Ceramic SQFP
(FPT-100C-C01)
Only ES
Only ES
81
MB90230 Series
PACKAGE DIMENSIONS
■
100-pin Plastic LQFP
(FPT-100P-M05)
75
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
+0.20
−0.10
1.50
(Mounting height)
51
5076
.059
+.008
−.004
100
LEAD No.
C
1
0.50(.0197)TYP
1995 FUJITSU LIMITED F100007S-2C-3
100-pin Ceramic LQFP
(FPT-100C-C01)
12.00(.472)REF
0.50(.0197)TYP 0.20±0.05
INDEX
0.10(.004)
16.00±0.20
(.630±.008)
+0.25
13.60
−0.15
+.010
.535
−.006
SQ
SQ
"A"
0.18
.007
+0.08
−0.03
+.003
−.001
(.008±.002)
26
25
0.08(.003)
"B"
M
1.70(.067)MAX
(Mounting height)
0.90(.035)REF
0.127
.005
(.472)
REF
+0.05
−0.02
+.002
−.001
15.0012.00
(.591)
NOM
Details of "B" part
0~10˚
Details of "A" part
0.15(.006)MAX
0.40(.016)MAX
0.10±0.10
(.004±.004)
(STAND OFF)
0.50±0.20(.020±.008)
0.15(.006)
0.15(.006)
Dimensions in mm (inches)
82
INDEX AREA
C
1995 FUJITSU LIMITED F100015SC-1-3
"A"
15.00±0.25
(.591±0.10)
SQ
Details of "A" part
0.125±0.05
(.005±.002)
0(0)MIN
STAND OFF
0.50±0.20
(.020±.008)
Dimensions in mm (inches)
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Te ch Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
MB90230 Series
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
measurement equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
F9901
FUJITSU LIMITED Printed in Japan
83
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