FUJITSU MB90220 DATA SHEET

查询MB90223供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13502-5E

16-bit Proprietary Microcontroller

CMOS

F2MC-16F MB90220 Series

MB90223/224/P224A/W224A
MB90P224B/W224B/V220

■ OUTLINE

The MB90220 ser ies of g eneral-pur pose hi gh-per formance 16 -bit mi crocon trollers ha s bee n develo ped prim arily
for applications that demand high-speed real-time processing and is suited for industrial applications, office
automation equipme nt, process control , and other appli cations. The F
Family with improved high- level language support functions and task switching functions, as well as addit ional
addressing modes.

2

MC-16F CPU is based on the F2MC*-16

On-chip perip heral resour ces in clude a 4-c hanne l PWC timer, a 4-channel ICU (In put Capt ure Un it), a 1-chann el
24-bit timer counter, an 8-channel OCU (Output Compare Unit), a 6-channel 16-bit reload timer, a 2-channel
16-bit PPG timer, a 10-bit A/D co nverter with 16 inputs, and a 4-ch annel serial po rt with a UART function (one
channel includes the CTS function).

The MB90P224B, MB90W224B, MB90224 is under development.

2

*: F

MC stands for FUJITSU Flexible Microcontroller.

■ PACKAGE

120-pin Plastic QFP

120-pin Ceramic QFP

(FPT-120P-M03)

(FPT-120C-C02)

MB90220 Series

■ FEATURES

F2MC-16F CPU

• Minimum execution time: 62.5 ns/16 MHz oscillation (using a duty control system)

• Instruction sets optimized for controllers

2

Upward object-compatible with the F
Various data types (bit, byte, word, and long-word)
Instruction cycle improved to speed up operation
Extended addressing modes: 25 types
High coding efficiency
Access method (bank access with linear pointer)
Enhanced multiplication and division instructions (with signed instructions added)
Higher-precision operation using a 32-bit accumulator

• Extended intelligent I/O service (automatic transfer function independent of instructions)
Access area expanded to 64 Kbytes

• Enhanced instruction set applicable to high-level language (C) and multitasking
System stack pointer
Enhanced pointer-indirect instructions
Barrel shift instruction
Stack check function

• Increased execution speed: 8-byte instruction queue

• Powerful interrupt functions: 8 levels and 28 sources

MC-16(H)

Peripheral resources

• Mask ROM : 64 Kbytes (MB90223)

96 Kbytes (MB90224)

EPROM : 96 Kbytes (MB90W224A/W224B)

• One-time PROM : 96 Kbytes (MB90P224A/P224B)

• RAM: 3 Kbytes (MB90223)

4.5 Kbytes (MB90224/MB90W 224 A/ P22 4A /W2 24B /P 224B )
5 Kbytes (MB90V220)

• General-purpose ports: max. 102 channels

• ICU (Input Capture Unit): 4 channels

• 24-bit timer counter: 1 channel

• OCU (Output Compare Unit): 8 channels

• PWC timer with time measurement function: 4 channels

• 10-bit A/D converter: 16 channels

• UART: 4 channels (one channel includes CTS function)

• 16-bit reload timer
Toggled output, external clock, and gate functions: 6 channels

• 16-bit PPG timer: 2 channels

• DTP/External-interrupt inputs: 8 channels (of which five have edge detection function only)

• Write-inhibit RAM: 0.5 Kbytes (1 Kbyte for MB90V220)

• Timebase counter: 18 bits

• Clock gear function

• Low-power consumptio n mode
Sleep mode
Stop mode
Hardware standby mode

2

Product description

• MB90223/224 are mask ROM product.

• MB90P224A/P224B are one-time PROM products.

• MB90W224A/W224B are EPROM products. ES only.

• Operating temperature of MB90P224A/W224A is –40°C to +85°C.
(However, the AC characteristics is assured in –40°C to +70°C)

• Operation clock cycle of MB90223 is 10 MHz to 12 MHz.

• MB90V220 is a evaluation device for the program development. ES only.

■ PRODUCT LINEUP

MB90220 Series

Part number

Item

Classification Mask ROM

ROM size 64 Kbytes 96 Kbytes 96 Kbytes 96 Kbytes None
RAM size 3 Kbytes 4.5 Kbytes 4.5 Kbytes 4.5 Kbytes 5 Kbytes
CPU functions The number of instructions: 412

Ports I/O ports (N-ch open-drain): 16

ICU

(Input Capture Unit)

24-bit timer
counter

OCU

(Output Compare Unit)

PWC timer Number of channels: 4

MB90223 MB90224

Mask ROM

product

Instruction bit length: 8 or 16 bits
Instruction length: 1 to 7 bytes
Data bit length: 1, 4, 8, 16, or 32 bits
Minimum execution time: 62.5 ns/16 MHz
Interrupt processing time: 1.0 µs/16 MHz (min.)

I/O ports (CMOS): 86
Total: 102

Pin change source (match signal causes register value transfer/general-purpose port)

16-bit reload timer operation (operation clock cycle: 0.25 µs to 1.31 ms)

16-bit pulse-width count operation (Allowing continuous/one-shot measurement, H/L width

measurement, inter-edge measurement, and divided-frequency measurement)

product

Rising edge/falling edge/both edges selectable

Overflow interrupt, intermediate bit interrupt

MB90P224A
MB90P224B

One-time

PROM product

Number of channels: 4

Number of channels: 1

Number of channels: 8

MB90W224A
MB90W224B

EPROM

product

MB90V220

Evaluation

device

10-bit
A/D converter

Single conversion mode (conversion of each channel)

Scan conversion mode (continuous conversion for up to 16 consecutive channels)

Continuous conversion mode (repeated conversion of specified channel)

Stop conversion mode (conversion every fixed cycle)

UART Number of channels: 4 (1 channel with CTS function)

Clock-synchronous transfer mode

(full-duplex double buffering, 7 to 9-bit data length, 2400 to 62500 bps)
(full-duplex double buffering, 7 to 9-bit data length, 2400 to 62500 bps)

16-bit reload
timer

16-bit reload timer operation (operation clock cycle: 0.25 µs to 1.05 s)

Resolution: 10 bits

Number of inputs: 16

Asynchronous transfer mode

Number of channels: 6

(Continued)

3

MB90220 Series

(Continued)

Part number

Item

16-bit PPG timer Number of channels: 2

DTP/External
interrupts

Write-inhibited
RAM

Standby mode stop mode (activated by software or hardware) and sleep mode
Gear function Machine clock operation frequency switching: 16 MHz, 8 MHz, 4 MHz, 1 MHz (at

Package FPT-120P-M03 FPT-120C-C02 PGA-256C-A02

Note: MB90V220 is a evaluation device, therefore, the electrical characteristics are not assured.

MB90223 MB90224

16-bit PPG operation (operation clock cycle: 0.25 µs to 6 s)

Number of inputs: 8 (of which five have edge detection function only)

External interrupt mode (allowing interrupts to activate at four different request levels)

Simple DMA transfer mode (allowing ext ended I

RAM size: 512 bytes (1 Kbyte for MB90V220)

RAM write-protectable with WI

16-MHz oscillation)

■ DIFFERENCES BETWEEN MB90223/224 (MASK ROM PRODUCT) AND MB90P224A/

W224A/P224B/W224B

MB90P224A
MB90P224B

2

OS to activate at two d ifferent r equest le vels)

MB90W224A
MB90W224B

pin

MB90V220

Part number

Item

ROM Mask ROM

Pin functions: pin 87 MD2 pin MD2/V

MB90223 MB90224

Mask ROM

64 Kbytes

96 Kbytes

MB90P224A
MB90P224B

OTPROM
96 Kbytes

MB90W224A
MB90W224B

EPROM

96 Kbytes

PP pin

4

■ PIN ASSIGNMENT

90 RST

89 MD0

88 MD1

87 MD2

86 HST

85 P57/WI

84 P56/RD

83 P55/WRL

82 P54/WRH

(Top view)

81 P53/HRQ

80 P52/HAK

79 P51/RDY

78 P50/CLK

77 PC5/TRG0

76 PC4/CTS0

75 PC3/SCK3

74 PC2/SID3

73 PC1/SOD3

72 PC0/SCK2

71 PB7/SID2

70 PB6/SOD2

69 PB5/SCK1

68 PB4/SID1

67 PB3/SOD1

66 PB2/SCK0

65 PB1/SID0

MB90220 Series

SS

62 PA7/INT2/ATG

61 PA6/INT1

64 PB0/SOD0

63 V

SS 91

V

X0 92
X1 93

V

CC 94

P00/D00 95
P01/D01 96
P02/D02 97
P03/D03 98
P04/D04 99
P05/D05 100
P06/D06 101
P07/D07 102
P10/D08 103
P11/D09 104
P12/D10 105
P13/D11 106
P14/D12 107
P15/D13 108
P16/D14 109
P17/D15 110
P20/A00 111
P21/A01 112
P22/A02 113
P23/A03 114
P24/A04 115
P25/A05 116
P26/A06 117
P27/A07 118

V

SS 119

P30/A08 120

60 PA5/INT0
59 PA4/PWC3/POT3/ASR3
58 PA3/PWC2/POT2/ASR2
57 PA2/PWC1/POT1/ASR1
56 PA1/PWC0/POT0
55 PA0/ASR0
54 V

CC

53 P67/AN07
52 P66/AN06
51 P65/AN05
50 P64/AN04
49 P63/AN03
48 P62/AN02
47 P61/AN01
46 P60/AN00
45 AV

SS

44 AVRL
43 AVRH
42 AV

CC

41 P97/AN15
40 P96/AN14
39 P95/AN13
38 P94/AN12
37 P93/AN11
36 P92/AN10
35 P91/AN09
34 P90/AN08
33 V

SS

32 P87/PPG1
31 P86/PPG0

P31/A09 1

P32/A10 2

P33/A11 3

P34/A12 4

P35/A13 5

CC 8

V

P40/A16 9

P36/A14 6

P37/A15 7

P41/A17 10

P42/A18 11

P43/A19/TIN1/INT3 12

P44/A20/TIN2/INT4 13

P70/DOT0 17

P71/DOT1 18

P45/A21/TIN3/INT5 14

P46/A22/TIN4/INT6 15

P47/A23/TIN5/INT7 16

(FPT-120P-M03)
(FPT-120C-C02)

P72/DOT2 19

P73/DOT3 20

P74/DOT4 21

P75/DOT5 22

P76/DOT6 23

P77/DOT7 24

P80/TOT0 25

P81/TOT1 26

P82/TOT2 27

P83/TOT3 28

P84/TOT4 29

P85/TOT5 30

5

MB90220 Series

■ PIN DESCRIPTION

Pin no.

QFP*

92,

93

89 to 87 MD0 to MD2 D Operation mode specification input pins

90 RST
86 HST

95 to 102 P00 to P07 C General-purpose I/O ports

103 to 110 P10 to P17 C General-purpose I/O ports

111 to 118 P20 to P27 C General-purpose I/O ports

Pin name

X0,
X1

D00 to D07 Output pins for low-order 8 bits of the external address bus.

D08 to D15 I/O pins for higher-order 8 bits of the external data bus

Circuit

type

A Crystal oscillation pins (16 MHz)

Connect directly to V
G External reset request input
E Hardware standby input pin

This function is valid only in single-chip mode.

This function is valid only in modes where the external bus is

enabled.

This function is valid only in single-chip mode or when the external bus

is enabled and the 8-bit data bus specification has been made.

This function is valid only when the external bus is enabled and the

16-bit bus specification has been made.

This function is valid only in single-chip mode.

CC or VSS.

Function

A00 to A07 Output pins for lower-order 8 bits of the external address bus

This function is valid only in modes where the external bus is

enabled.

120,

1 to 7

9 to 11 P40 to P42 C General-purpose I/O ports

12 to 16 P43 to P47 C General-purpose I/O ports

P30,
P31 to P37

A08,
A09 to A15

A16 to A18 Output pins for higher-order 8 bits of the external address bus

A19 to A23 Output pins for higher-order 8 bits of the external address bus

TIN1 to TIN5 16-bit reload timer input pins

C General-purpose I/O ports

This function is valid either in single-chip mode or when the address

mid-order control register specification is “port”.

Output pins for mid-order 8 bits of the external address bus

This function is valid in modes where the external bus is enabled and

the address mid-order control register specification is “address”.

This function is valid either in single-chip mode or when the address

high-order control register specification is “port”.

This function is valid in modes where the external bus is enabled and

the address high-order control register specification is “address”.

This function is valid when either single-chip mode is enabled or the

address higher-order control register specification is “port”.

This function is valid in modes where the external bus is enabled and

the address higher-order control register specification is “address”.

This function is valid when the timer input specification is “enabled”.

The data on the pins is read as timer input (TIN1 to TIN5).

* :FPT-120P-M03, FPT-120C-C02

6

(Continued)

Pin no.

Pin name

QFP*

12 to 16 INT3 to INT7 C External interrupt request input pins

78 P50 C General-purpose I/O port

CLK CLK output pin

79 P51 C General-purpose I/O port

RDY Ready input pin

Circuit

type

Function

When external interrupts are enabled, these inputs may be used

suddenly at any time; therefore, it is necessary to stop output by other

functions on these pins, except when using them for output

deliberately.

This function is valid in single-chip mode and when the CLK output

specification is disabled.

This function is valid in modes where the external bus is enabled and

the CLK output specification is enabled.

This function is valid in single-chip mode or when the ready function

is disabled.

This function is valid in modes where the external bus is enabled and

the ready function is enabled.

MB90220 Series

80 P52 C General-purpose I/O port

This function is valid in single-chip mode or when the hold function is

disabled.

HAK

81 P53 C General-purpose I/O port

HRQ Hold request input pin

82 P54 C General-purpose I/O port

WRH

83 P55 C General-purpose I/O port

WRL

Hold acknowledge output pin

This function is valid in modes where the external bus is enabled and

the hold function is enabled.

This function is valid in single-chip mode or external bus mode and

when the hold function is disabled.

This function is valid in modes where the external bus is enabled and

the hold function is enabled.

During this operation, the input may be used suddenly at any time;

therefore, it is necessary to stop output by other fuctions on this pin,

except when using it for output deliberately.

This function is valid in single-chip mode, when the external bus is in

8-bit mode, or when WRH

Write strobe output pin for the high-order 8 bits of the data bus

This function is valid in modes where the external bus is enabled, the

external bus is in 16-bit mode, and WRH

This function is valid in single-chip mode or when WRL

disabled.

Write strobe output pin for the low-order 8 bits of the data bus

This function is valid in modes where the external bus is enabled and

WRL

pin output is enabled.

pin output is disabled.

pin output is enabled.

pin output is

* :FPT-120P-M03, FPT-120C-C02

(Continued)

7

MB90220 Series

Pin no.

Pin name

QFP*

84 P56 C General-purpose I/O port

RD

85 P57 B General-purpose I/O port

WI

46 to 53 P60 to P67 F Open-drain I/O ports

AN00 to AN07 10-bit A/D converter analog input pins

17 to 24 P70 to P77 C General-purpose I/O ports

DOT0 to DOT7 This function is valid when OCU (output compare unit) output is

Circuit

type

This function is valid in single-chip mode. This function is valid in

modes where the external bus is valid.

Read strobe output pin for the data bus

This function is valid in modes where the external bus is enabled.

This function is always valid.

When these pins are open in input mode, through current may leak in

stop mode/reset mode, be sure to fix these pins to V

use these pins in input mode.

RAM write disable request input

During this operation, the input may be used suddenly at any time;

therefore, it is necessary to stop output by other fuctions on this pin,

except when using it for output deliberately.

This function is valid when the analog input enable register

specification is “port”.

This function is valid when the analog input enable register

specification is “analog input”.

This function is valid when the output specification for DOT0 to DOT7

is “disabled”.

enabled.

Function

CC/VSS level to

25 to 30 P80 to P85 C General-purpose I/O ports

This function is valid when the output specification for TOT0 to TOT5

is “disabled”.

TOT0 to TOT5 16-bit reload timer output pins (TOT0 to TOT5)

31,

32

34 to 41 P90 to P97 F Open-drain I/O ports

* :FPT-120P-M03, FPT-120C-C02

8

P86,
P87

PPG0,
PPG1

AN08 to AN15 10-bit A/D converter analog input pins

C General-purpose I/O ports

This function is valid when the PPG0, and PPG1 output specification

is “disabled”.

16-bit PPG timer output pins

This function is valid when the PPG control/status register

specification is “PPG output pins”.

This function is valid when the analog input enable register

specification is “port”.

This function is valid when the analog input enable register

specification is “analog input”.

(Continued)

Pin no.

Pin name

QFP*

Circuit

type

55 PA0 C General-purpose I/O port

This function is always valid.

ASR0 ICU (input capture unit) input pin

This function is valid during ICU (input capture unit) input operations.

56 PA1 C General-purpose I/O port

This function is always valid.

PWC0 PWC input pin

During PWC0 input operations, this input may be used suddenly at

any time; therefore, it is necessary to stop output by other functions

on this pin, except when using it for output deliberately.

POT0 PWC output pin

This function is valid during PWC output operations.

57 to 59 PA2 to PA4 C General-purpose I/O ports

This function is always valid.

PWC1 to PWC3 PWC input pins

This function is valid during PWC input operations.

During PWC1 to PWC3 input operations, this input may be used

suddenly at any time; therefore, it is necessary to stop output by other

functions on this pin, except when using it for output deliberately.

MB90220 Series

Function

POT1 to POT3 PWC output pins

This function is valid during PWC output operations.

ASR1 to ASR3 ICU (input capture unit) input pins

This function is valid during ICU (input capture unit) input operations.

60,

61

PA5,
PA6

B General-purpose I/O ports

This function is always valid.

When these pins are open in input mode, through current may leak in

stop mode/reset mode, be sure to fix these pins to V

use these pins in input mode.

INT0,
INT1

DTP/External interrupt request input pins

When DTP/external interrupts are enabled, these inputs may be used

suddenly at any time; therefore, it is necessary to stop output by other

functions on these pins, except when using them for output

deliberately.

When these pins are open in input mode, through current may leak in

stop mode/reset mode, be sure to fix these pins to V

use these pins in input mode.

62 PA7 B General-purpose I/O port

This function is always valid.

When these pins are open in input mode, through current may leak in

stop mode/reset mode, be sure to fix these pins to V

use these pins in input mode.

* :FPT-120P-M03, FPT-120C-C02

CC/VSS level to

CC/VSS level to

CC/VSS level to

(Continued)

9

MB90220 Series

Pin no.

Pin name

QFP*

62 INT2 B DTP/External interrupt request input pin

ATG

64 PB0 C General-purpose I/O port

SOD0 UART0 (ch.0) serial data output

65 PB1 C General-purpose I/O port

SID0 UART0 (ch.0) serial data input pin

Circuit

type

Function

When DTP/external interrupts are enabled, these inputs may be used

suddenly at any time; therefore, it is necessary to stop output by other

functions on these pins, except when using them for output

deliberately.

When these pins are open in input mode, through current may leak in

stop mode/reset mode, be sure to fix these pins to V

use these pins in input mode.

10-bit A/D converter external trigger input pin

When these pins are open in input mode, through current may leak in

stop mode/reset mode, be sure to fix these pins to V

use these pins in input mode.

This function is valid when the UART0 (ch.0) serial data output

specification is “disabled”.

This function is valid when the UART0 (ch.0) serial data output

specification is “enabled”.

This function is always valid.

During UART0 (ch.0) input operations, this input may be used

suddenly at any time; therefore, it is necessary to stop output by other

functions on this pin, except when using it for output deliberately.

CC/VSS level to

CC/VSS level to

66 PB2 C General-purpose output port

This function is valid when the UART0 (ch.0) clock output

specification is “disabled”.

SCK0 UART0 (ch.0) clock output pin

The clock output function is valid when the UART0 (ch.0) clock output

specification is “enabled”.

UART0 (ch.0) external clock input pin. This function is valid when the

port is in input mode and the UART0 (ch.0) specification is external

clock mode.

67 PB3 C General-purpose I/O port

This function is valid when the UART0 (ch.1) serial data output

specification is “disabled”.

SOD1 UART0 (ch.1) serial data output pin

This function is valid when the UART0 (ch.1) serial data output

specification is “enabled”.

68 PB4 C General-purpose I/O port

This function is always valid.

SID1 UART0 (ch.1) serial data input pin

During UART0 (ch.1) input operations, this input may be used

suddenly at any time; therefore, it is necessary to stop output by other

functions on this pin, except when using it for output deliberately.

* :FPT-120P-M03, FPT-120C-C02

(Continued)

10

MB90220 Series

Pin no.

Pin name

QFP*

69 PB5 C General-purpose I/O port

SCK1 UART0 (ch.1) clock output pin

70 PB6 C General-purpose I/O port

SOD2 UART0 (ch.2) serial data output pin

71 PB7 C General-purpose I/O port

SID2 UART0 (ch.2) serial data input pin

72 PC0 C General-purpose I/O port

SCK2 UART0 (ch.2) clock output pin

73 PC1 C General-purpose I/O port

SOD3 UART1 serial data output pin

74 PC2 C General-purpose I/O port

Circuit

type

This function is valid when the UART0 (ch.1) clock output specification

is “disabled”.

The clock output function is valid when the UART0 (ch.1) clock output

specification is “enabled”.

UART0 (ch.1) external clock input pin

This function is valid when the port is in input mode and the UART0

(ch.1) specification is external clock mode.

This function is valid when the UART0 (ch.2) serial data output

specification is “disabled”.

This function is valid when the UART0 (ch.2) serial data output

specification is “enabled”.

This function is always valid.

During UART0 (ch.2) input operations, this input may be used

suddenly at any time; therefore, it is necessary to stop output by other

functions on this pin, except when using it for output deliberately.

This function is valid when the UART0 (ch.2) clock output

specification is “disabled”.

The clock output function is valid when the UART0 (ch.2) clock output

specification is “enabled”.

UART0 (ch.2) external clock input pin

This function is valid when the port is in input mode and the UART0

(ch.2) specification is external clock mode.

This function is valid when the UART1 serial data output specification

is “disabled”.

This function is valid when the UART1 serial data output specification

is “enabled”.

This function is always valid.

Function

SID3 UART1 serial data input pin

* :FPT-120P-M03, FPT-120C-C02

During UART1 input operations, this input may be used suddenly at

any time; therefore, it is necessary to stop output by other functions

on this pin, except when using it for output deliberately.

(Continued)

11

MB90220 Series

(Continued)

Pin no.

Pin name

QFP*

Circuit

type

75 PC3 C General-purpose I/O port

This function is valid when the UART1 clock output specification is

“disabled”.

SCK3 UART1 clock output pin

The clock output function is valid when the UART1 clock output

specification is “enabled”.

UART1 external clock input pin

This function is valid when the port is in input mode and the UART1

specification is external clock mode.

76 PC4 C General-purpose I/O port

This function is always valid.

CTS0 UART0 (ch.0) Clear To Send input pin

When the UART0 (ch.0) CTS function is enabled, this input may be

used sudde nly at any ti me; th eref or e, i t i s n ece ss ary t o s top ou tp ut by

other functions on this pin, except when using it for output

deliberately.

77 PC5 C General-purpose I/O port

This function is always valid.

TRG0 16-bit PPG timer trigger input pin

This function is valid when the 16-bit PPG timer trigger input

specification is enabled.

The data on this pin is read as 16-bit PPG timer trigger input (TRG0).

During this operation, the input may be used suddenly at any time;

therefore, it is necessary to stop output by other functions on this pin,

except when using it for output deliberately.

Function

8,

V

CC Power

54,

94

V

33,

SS Power

63,
91,

119

42 AV

CC Power

43 AVRH Power

44 AVRL Power

45 AV

SS Power

* :FPT-120P-M03, FPT-120C-C02

supply

supply

supply

supply

supply

supply

Power supply for digital circuitry

Ground level for digital circuitry

Power supply for analog circuitry

When turning this power supply on or off, always be sure to first apply

electric potential equal to or greater than AV

During normal operation AV

CC should be equal to VCC.

CC to VCC.

Reference voltage input for analog circuitry

When turning this pin on or off, always be sure to first apply electric

potential equal to or greater than AVRH to AV

CC.

Reference voltage input for analog circuitry

Ground level for analog circuitry

(Continued)

12

MB90220 Series

■ I/O CIRCUIT TYPE

Type Circuit Remarks

A • Oscillation feedback resistor: Approx. 1 MΩ

MB90223
MB90224

X1

X0

Standby control signal

X1

MB90P224B
MB90W224B

• Oscillation feedback resistor: Approx. 1 MΩ
MB90P224A
MB90W224A

X0

Standby control signal

B • CMOS-level output

• CMOS-level hysteresis input with no standby
control

Digital output

Digital output

R

Digital input

Note: The pull-up and pull-down resistors are always connected, regardless of the state.

(Continued)

13

MB90220 Series

Type Circuit Remarks

C • CMOS-level output

• CMOS-level hysteresis input with standby

Digital output

Digital output

R

Digital input

D • CMOS-level input with no standby control

control

Mask ROM products only:
MD2: with pull-down resistor
MD1: with pull-up resistor
MD0: with pull-down resistor

R

Digital input

• CMOS-level input with no standby control
MD2 of OTPROM products/EPROM products
only

R

Digital input
VPP power supply

E • CMOS-level hysteresis input with no standby

control

• With input analog filter (40 ns Typ.)

R

Analog filter

Digital input

Note: The pull-up and pull-down resistors are always connected, regardless of the state.

14

(Continued)

MB90220 Series

(Continued)

Type Circuit Remarks

F • N-channel open-drain output

• CMOS-level hysteresis i nput with A/D
control and with standby control

Digital output

R

A/D input
Digital input

G • CMOS-level hyste resi s input with no

Pull-up
resistor

standby control and with pull-up resistor

• With input analog filter (40 ns Typ.)

R

MB90223, MB90224: RST
to with or without a pull-up resistor by a
mask option.

R

MB90P224A: With pull-up resistor
MB90W224A: With pull-up resistor
MB90P224B: With no pull-up resistor
MB90W224B: With no pull-up resistor

Analog filter

: P-type transistor : N-type transistor

Digital input

Note: The pull-up and pull-down resistors are always connected, regardless of the state.

pin can be set

15

MB90220 Series

■ HANDLING DEVICES

1. Preventing Latchup

CMOS ICs may c ause latch up when a voltag e higher t han VCC or lower th an VSS is appl ied to i nput or ou tput
pins other than medium-and high-voltage pins, or when a voltage exceeding the rating is applied between V
and VSS.

If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Use meticulous care not to let any voltage exceed the maximum rating.
Also, take care to preven t the analog power supply (AV
digital power supply (V

CC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.

3. Treatment of Pins when A/D is not Used

Connect to be AVCC = AVRH = VCC and AVSS = AVRL = VSS even if the A/D converter is not in use.

CC and AVRH) and a nalog input from exceeding the

CC

4. Precautions when Using an External Input

To reset the internal circuit properly by the “L” level input to the RST pin, the “L” level input to the RST pin must
be maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.

5. VCC and VSS Pins

Apply equal potential to the VCC and VSS pins.

6. Supply Voltage Variation

The operation assurance range for the VCC supply voltage is as given in the ratings. Howev er, sudden changes
in the supply voltage can cause miso peration, even if the voltage remains within the rated range. Therefore, it
is impor tant to su pply a stable voltage to t he IC. The recommende d power supply co ntrol guideli nes are that
the commercial frequency (50 to 6 0 Hz) ripple var iation (P-P value) on V
standard V

CC value and that the transient rate of change during sudden changes, such as during power supply

CC should be less than 10% of the

switching, should be less than 0.1 V/ms.

7. Notes on Using an External Clock

When using an external clock, drive the X0 pin as illustrated below. When an external clock is used, oscillation
stabilization time is required even for power-on reset and wake-up from stop mode.

Use of External Clock

•

MB90220

X0

X1

Note: Wh en using an exter nal clock, be sure to in put external clo ck more than 6 machin e cycles after

setting the HST

pin to “L” to transfer to the hardware standby mode.

16

MB90220 Series

8. Power-on Sequence for A/D Converter Power Supplies and Analog Inputs

Be sure to turn on the digital power supply (VCC) before applying voltage to the A/D converter power supplies
(AV

CC, AVRH, and AVRL) and analog inputs (AN00 to AN15).

When turning power supplies off, turn off the A/D converter power supplies (A V
inputs (AN00 to AN15) first, then the digital power supply (V

When turning AVRH on or off, be careful not to let it exceed AV

CC).

CC.

CC, A VRH, and A VRL) and analog

17

MB90220 Series

■ PROGRAMMING FOR MB90P224A/P224B/W224A/W224B

In EPROM mode, the MB9 0P224A/P224B/W224A/W224B func tions equivalent to the MBM27C1000. This
allows the EPROM to be programmed with a general-pur pose EPROM programmer by using the dedicated
socket adapter (do not use the electronic signature mode).

1. Program Mode

When shipped from Fujitsu, an d after eac h erasure, all bits (96 K × 8 bits) in the MB9 0P224A /P224 B/W224 A/
W224B are in the “1” sta te. Data is written to the ROM by selectively programming “0’s” into the desired bit
locations. Bits cannot be set to “1” electrically.

2. Programming Procedure

(1) Set the EPROM programmer to MBM27C1000.
(2) Load program data into the EPROM programmer at 08000

H to 1FFFFH.

Note that ROM addresses FE8000
W224B series assign to 08000

FFFFFFH

H

FE8000

Operation mode

* : Be sure to set the programming, the start address and the stop address on the EPROM programmer to 08000

H to FFFFFFH in the operation mode in the MB90P224A/P224B/W224A/

H to 1FFFFH in the EPROM mode (on the EPROM programmer).

H *

1FFFF

08000H *

(Corresponding addresses on the EPROM mode)

EPROM mode

H/1FFFFH.

(3) Mount the MB90P224A/P224B/W224A/W224B on the adapter socket, then fit the adapter socket onto the

EPROM programmer. When mounting the device and the adapter socket, pay attention to their mounting

orientations.
(4) Start programming the program data to the device.
(5) If programming has not successfully resulted, connect a capacitor of approx. 0.1 µF between V

between V

PP and GND.

CC and GND,

Note: The mask ROM products (MB90223, MB90224) does not support EPROM mode. Data cannot, therefore, be

read by the EPROM programmer.

18

MB90220 Series

3. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer

Part No.
Package
Compatible socket adapter

Sun Hayato Co., Ltd.
Recommended

programmer
manufacturer
and
programmer
name

Inquiry: Sun Hayato Co., Ltd.: TEL: [phone]

Advantest Corp.: TEL: Except JAPAN (81)-3-3930-4111

Advantest corp.

FAX: [phone]

R4945A

(main unit)

R49451A
(adapter)

+

MB90P224B

QFP-120

ROM-120QF-32DP-16F

Recommended

4. Erase Procedure

Data written in the MB90W224A/W224B is erased (from “0” to “1”) by exposing the chip to ultraviolet rays with
a wavelength of 2,537 Å through the translucent cover.

2

Recommended irradiati on dosage for exposure is 10 Wsec/cm
with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface illuminance
is 1200 µW/cm

If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the la mp
increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent
par t of the package is stained with oil o r adhesive, transmiss ion of ultraviolet rays is de graded, resulting in a
longer erasure time. In that case, clean the t ranslucent part usi ng alcohol (or other solvent not affecting the
package).

2

).

. This amount is reached in 15 to 20 mi nutes

The above recommended dosage is a value which takes the guard band into consideration and is a multiple of
the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure;
the purpo se of the guard band is to ensure erasur e in all temperature and supply voltage ranges. In addition,
check the life span of the lamp and control the illuminance appropriately.

Data in the MB90W224A/W224B is erased by exposure to light with a wavelength of 4,000 Å or less.
Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure

results in a much lower erasure rate than exposure to 2,537 Å ultraviolet rays. Note that exposure to such lights
for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light
with a wavelength of 4,000 Å or less, cover the translucent part, for example, with a protective seal to pr event
the chip from being exposed to the light.

Exposure to light with a wavelength of 4,000 to 5,000 Å or more will not erase data in the device. If the light
applied to the chip has a ver y high illuminance, however, the device may cause malfunction in the circuit for
reasons of general semiconductor characteristics. Although the circuit will recover normal operation when
exposure is stopped, the device require s proper co unter meas ures for use in a place exposed continuously to
such light even though the wavelength is 4,000 Å or more.

19

MB90220 Series

5. Recommended Screening Conditions

High temperature aging is recommended as the pre-assembly screening procedure.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

6. Programming Yeild

MB90P224A/P224B cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always
be guaranteed to be 100%.

7. Pin Assignments in EPROM Mode

(1) Pins Compatible with MBM27C1000

MBM27C1000

MB90P224A/P224B/

MB90W224A/W224B

MBM27C1000

Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name

1V

PP 87 MD2 (VPP)32VCC 8, 54, 94 VCC

2OE 83P55 31PGM 84P56
3 A15 7 P37 30 N.C. — —
4 A12 4 P34 29 A14 6 P36
5 A07 118 P27 28 A13 5 P35
6 A06 117 P26 27 A08 120 P30
7 A05 116 P25 26 A09 1 P31
8 A04 115 P24 25 A11 3 P33

9 A03 114 P23 24 A16 9 P40
10 A02 113 P22 23 A10 2 P32
11 A01 112 P21 22 CE 82 P54
12 A00 111 P20 21 D07 102 P07
13 D00 95 P00 20 D06 101 P06

MB90P224A/P224B/

MB90W224A/W224B

14 D01 96 P01 19 D05 100 P05
15 D02 97 P02 18 D04 99 P04
16 GND

33, 63, 91,119

VSS 17 D03 98 P03

20

(2) Power Supply and GND Connection Pins

Type Pin no. Pin name

Power supply 89

88
86

8, 54, 94

MB90220 Series

MD0
MD1
HST

VCC

GND 33, 63, 91, 119

44
45
80
81
90

(3) Pins other than MBM27C1000-compatible Pins

Pin no. Pin name Treatment

92 X0 Pull up with 4.7 KΩ resistor
93 X1 OPEN

109
110
10 to 16
42
43
46
47
48 to 53
17 to 24
25 to 32
34 to 41
55 to 61
63 to 70
71 to 76
78
79
85
103 to 108

P16
P17
P41 to P47
AV

CC

AVRH
P60
P61
P62 to P67
P70 to P77
P80 to P82
P90 to P97
PA0 to PA7
PB0 to PB7
PC0 to PC5
P50
P51
P57
P10 to P15

Connect pull-up resistor of about 1 MΩ to each pin

V

SS

AVRL

SS

AV

P52
P53

RST

21

MB90220 Series

■ BLOCK DIAGRAM

X1
X0
RST
HST
MD0 to MD2

WI

CTS0
SID0 to SID2

SOD0 to SOD2

SCK0 to SCK2
SID3

SOD3
SCK3

5

4

3

3

UART0 × 3

Clock controller

Write-inhibit

RAM

UART1

PWC timer × 4

ICU (Input

Capture Unit)

Internal data bus

24-bit timer counter

OCU (Output

Compare Unit)

4

PWC0 to PWC3

4

POT0 to POT3

4

ASR0 to ASR3

× 4

8

DOT0 to DOT7

× 4

TOT0 to TOT5
TIN1 to TIN5

ATG
AN00 to AN15
AVCC
AVRH
AVRL
AV

SS

P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA7
PB0 to PB7
PC0 to PC5

PPG0
PPG1

TRG0

16-bit reload timer

6

21

102

2

× 6

5

10-bit

A/D converter

16 channels

16-bit PPG timer

I/O ports

× 2

DTP/External

interrupt

× 8

External bus

interface

2

MC-16F CPU

F

RAM

ROM

8

16

2

29

INT0 to INT7

D00 to D15
RDY

HRQ
A00 to A23

CLK
HAK
WRH
WRL
RD

22

■ PROGRAMMING MODEL

MB90220 Series

Dedicated Registers

AH

AL

USP
SSP
PS

PC
USPCU
SSPCU
USPCL
SSPCL

DPR

PCB
DTB
USB
SSB
ADB

Accumulator

User stack pointer
System stack pointer
Processor status
Program counter
User stack upper register
System stack upper register
User stack lower register
System stack lower register

Direct page register

Program bank register
Data bank register
User stack bank register
System stack bank register
Additional bank register

General-purpose Registers

000180

Processor Status (PS)

ILM

Upper

Lower

H + RP × 10H

8 bit

32 bit

RP

16 bit

Max.32 banks

R 7
R 5
R 3
R 1

MSB LSB

— I S T N Z V C

R 6
R 4
R 2

R 0
RW3
RW 2
RW 1
RW 0

16 bit

RW 7
RW 6
RW 5

RW 4

RL 3

RL 2

RL 1

RL 0

C C R

23

MB90220 Series

■ MEMORY MAP

H

FFFFFF

Address #1

010000

H

Address #2

002000

H

001F00H

Single chip

ROM area ROM area

ROM area

FF bank

image

Internal
register area

Internal ROM

and external bus

ROM area

FF bank

image

Internal
register area

External ROM

and external bus

Internal
register area

Address #3

Address #4

000380

H

000180H
000100H

0000C0H

000000H

MB90223
MB90224

MB90P224A/P224B
MB90W224A/W224B

MB90V220

Write-inhibit

RAM

RAM

Peripherals Peripherals Peripherals

Write-inhibit

RAM

RAM

Registers

Write-inhibit

RAM

RAM

RegistersRegisters

: Internal

: External

: No access

Type Address #1 Address #2 Address #3 Address #4

FF0000
FE8000H

(FE0000

H

004000H
004000H

H)

004000H

000F00H
001500H

001900H

000D00H
001300H

001500H

24

■ I/O MAP

MB90220 Series

Address Register

*3

000000
000001
000002
000003
000004
000005
000006
000007
000008
000009
00000A
00000B
00000C
00000D

Port 0 data register PDR0 R/W Port 0

H

*3

Port 1 data register PDR1 R/W Port 1

H

*3

Port 2 data register PDR2 R/W Port 2

H

*3

Port 3 data register PDR3 R/W Port 3

H

*3

Port 4 data register PDR4 R/W Port 4

H

*3

Port 5 data register PDR5 R/W Port 5

H

H Port 6 data register PDR6 R/W Port 6 11111111
H Port 7 data register PDR7 R Port 7 XXXXXXXX
H Port 8 data register PDR8 R/W Port 8 XXXXXXXX
H Port 9 data register PDR9 R/W Port 9 11111111

H Port A data register PDRA R/W Port A XXXXXXXX
H Port B data register PDRB R/W Port B XXXXXXXX
H Port C data register PDRC R/W Port C ––XXXXXX

H

to 0FH

*3

000010H
000011
000012
000013
000014
000015

Port 0 data direction register DDR0 R/W Port 0

*3

Port 1 data direction register DDR1 R/W Port 1

H

*3

Port 2 data direction register DDR2 R/W Port 2

H

*3

Port 3 data direction register DDR3 R/W Port 3

H

*3

Port 4 data direction register DDR4 R/W Port 4

H

*3

Port 5 data direction register DDR5 R/W Port 5

H

Register

name

Access

(Reserved area)

Resouce

name

Initial value

XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX

*1

00000000
00000000
00000000
00000000
00000000

00000000
000016
000017
000018
000019
00001A
00001B
00001C

00001D
to 1FH

H Port 6 analog input enable register ADER0 R/W Port 6 11111111
H Port 7 data direction register DDR7 R/W Port 7 1 1111111
H Port 8 data direction register DDR8 R/W Port 8 0 0000000
H Port 9 analog input enable register ADER1 R/W Port 9 11111111

H Port A data direction register DDRA R/W Port A 00000000
H Port B data direction register DDRB R/W Port B 00000000

H

Port C data direction register DDRC R/W Port C

H

(Reserved area)

*1

000020H Mode control register 0 UMC0 R/W
000021

000022

H Status register 0 USR0 R/W 00010000

Input data register 0

H

/output data register 0

UIDR0

/UODR0

R/W XXXXXXXX

––000000

00000100

UART 0 (ch.0)

(Continued)

25

MB90220 Series

Address Register

000023
000024
000025

000026
000027

000028
000029

00002A
00002B

00002C
00002D

H Rate and data register 0 URD0 R/W UART0 (ch.0) 0 000000X
H Mode control register 1 UMC1 R/W
H Status register 1 USR1 R/W 00010000

Input data register 1

H

/output data register 1

H Rate and data register 1 URD1 R/W 0 000000X
H Mode control register 2 UMC2 R/W
H Status register 2 USR2 R/W 00010000

Input data register 2

H

/output data register 2

H Rate and data register 2 URD2 R/W 0 000000X
H UART CTS control register UCCR R/W UART0 (ch.0) – ––000––

H

Register

name

Access

UIDR1

/UODR1

UIDR2

/UODR2

(Reserved area)

R/W

R/W

*1

00002EH Mode register SMR R/W
00002F

000030

H Control register SCR R/W 00000100

Input data register

H

/output data register

SIDR

/SODR

R/W

Resouce

name

UART0 (ch.1)

UART0 (ch.2)

UART1

Initial value

00000100

XXXXXXXX

00000100

XXXXXXXX

00000000

XXXXXXXX
000031

000032
000033
000034
000035

H Status register SSR R/W 00001–00
H A/D channel setting regist er ADCH R/W
H A/D mode register ADMD R/W –––X0000
H A/D control status register ADCS R/W 0000––00

H

(Reserved area)

*1

000036H

A/D data register ADCD R

000037
000038

H 000000XX

H

(Reserved area)

*1

000039H
00003AH DTP/interrupt enable register ENIR R/W
00003B
00003C

H DTP/interrupt source register EIRR R/W 00000000

H

Request level setting register ELVR R/W

00003D
00003E

to 3FH

H 00000000

H

(Reserved area)

*1

000040H

Timer control status register 0 TMCSR0 R/W

000041

H ––––0000

10-bit A/D
converter

10-bit A/D
converter

DTP/external
interrupt

16-bit reload
timer 0

00000000

XXXXXXXX

00000000

00000000

00000000

(Continued)

26

MB90220 Series

Address Register

000042

H

Timer control status register 1 TMCSR1 R/W

000043
000044

H ––––0000

H

Timer control status register 2 TMCSR2 R/W

000045
000046

H ––––0000

H

Timer control status register 3 TMCSR3 R/W

000047
000048

H ––––0000

H

Timer control status register 4 TMCSR4 R/W

000049
00004A

H ––––0000

H

Timer control status register 5 TMCSR5 R/W

00004B
00004C

H ––––0000

H

PPG control status register 0 PCNT0 R/W

00004D
00004E

H 00000000

H

PPG control status register 1 PCNT1 R/W

00004F
000050

H 00000000

H

PWC control status register 0 PWCSR0 R/W PWC timer 0

000051

H 00000000

Register

name

Access

Resouce

name

16-bit reload
timer 1

16-bit reload
timer 2

16-bit reload
timer 3

16-bit reload
timer 4

16-bit reload
timer 5

16-bit PPG
timer 0

16-bit PPG
timer 1

Initial value

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

000052

H

PWC control status register 1 PWCSR1 R/W PWC timer 1

000053
000054

H 00000000

H

PWC control status register 2 PWCSR2 R/W PWC timer 2

000055
000056

H 00000000

H

PWC control status register 3 PWCSR3 R/W PWC timer 3

000057
000058
000059

H 00000000
H ICU control register 0 ICC0 R/W

H

(Reserved area)

*1

00005AH Input capture control register 1 ICC1 R/W
00005B

H

00005CH
00005DH

(Reserved area)

*1

00005EH
00005FH
000060H

OCU control register 00 CCR00 R/W

000061

H ––––0000

ICU (Input
Capture Unit)

ICU (Input
Capture Unit)

OCU (Output
Compare Unit)

00000000

00000000

00000000

00000000

00000000

11110000

(Continued)

27

MB90220 Series

Address Register

000062

H

OCU0 control register 01 CCR01 R/W

000063
000064

H ––––0000

H

000065H
000066H
000067H
000068H

OCU0 control register 10 CCR10 R/W

000069
00006A

H 00000000

H

OCU0 control register 11 CCR11 R/W

00006B
00006C

H 00000000

H

00006DH
00006EH
00006FH
000070H

Free-run timer control register TCCR R/W

000071

H ––111111

Register

name

Access

(Reserved area)

(Reserved area)

Resouce

name

OCU (Output

Initial value

11110000

Compare Unit)

*1

––––0000

OCU (Output
Compare Unit)

*1

––––0000

11000000

000072
000073

H

Free-run timer lower-order data
register

H 00000000

TCRL

24-bit timer
counter

00000000

R

000074
000075
000076
000077H

H

Free-run timer upper-order data
register

H 00000000

H

TCRH

(Reserved area)

*1

00000000

000078H
000079H
00007AH PWC divider ratio control register 0 DIVR0 R/W PWC timer 0 ––––––00
00007B

H

Reserved area

*1

00007CH PWC divider ratio control register 1 DIVR1 R/W PWC timer 1 ––––––00
00007D

H

Reserved area

*1

00007EH PWC divider ratio control register 2 DIVR2 R/W PWC timer 2 ––––––00
00007F

H

Reserved area

*1

000080H PWC divider ratio control register 3 DIVR3 R/W PWC timer 3 ––––––00
000081

to 8DH

H

(Reserved area)

*1

(Continued)

28

MB90220 Series

Address Register

00008E
00008F

H WI control registe r WICR R/W

H

000090H
to 9EH

00009FH

0000A0
0000A3
0000A4
0000A5
0000A8

0000A9
0000B0

Delay interrupt source generation
/release register

H Standby control regis t e r STBY C R/W
H Address mid-order control register MACR W External pin ########

Address higher-order control

H

register

H External pin control register EPCR W External pin ##0–0#00
H Watchdog timer control register WDTC R/W

H Timebase timer control register TBTC R/W
H Interrupt control register 00 ICR00 R/W

Register

name

Access

(Reserved area)

*1

Resouce

name

Write-inhibit
RAM

Initial value

–––X––––

Delay in te rrupt

DIRR R/W

generation

–––––––0

module
Low power

consumption

0001****

HACR W External pin ########

Watchdog
timer

Timebase
timer

XXXXXXXX

–––00000

00000111
0000B1
0000B2
0000B3
0000B4
0000B5
0000B6
0000B7
0000B8
0000B9
0000BA
0000BB
0000BC
0000BD
0000BE
0000BF
0000C0

to FFH
001F00H
001F01

H Interrupt control register 01 ICR01 R/W 00000111
H Interrupt control register 02 ICR02 R/W 00000111
H Interrupt control register 03 ICR03 R/W 00000111
H Interrupt control register 04 ICR04 R/W 00000111
H Interrupt control register 05 ICR05 R/W 00000111
H Interrupt control register 06 ICR06 R/W 00000111
H Interrupt control register 07 ICR07 R/W 00000111
H Interrupt control register 08 ICR08 R/W 00000111
H Interrupt control register 09 ICR09 R/W 00000111

H Interrupt control register 10 ICR10 R/W 00000111
H Interrupt control register 11 ICR11 R/W 00000111
H Interrupt control register 12 ICR12 R/W 00000111
H Interrupt control register 13 ICR13 R/W 00000111
H Interrupt control register 14 ICR14 R/W 00000111

H Interrupt control register 15 ICR15 R/W 00000111

H

(External area)

*2

Interrupt
controller

00000000

PWC data buffer register 0 PWCR0 R/W PWC timer 0

H 00000000

(Continued)

29

MB90220 Series

Address Register

001F02

H

PWC data buffer register 1 PWCR1 R/W PWC timer 1

001F03
001F04

H 00000000

H

PWC data buffer register 2 PWCR2 R/W PWC timer 2

001F05
001F06

H 00000000

H

PWC data buffer register 3 PWCR3 R/W PWC timer 3

001F07
001F08

H 00000000

H

to 1F0FH
001F10H
001F11
001F12
001F13
001F14
001F15
001F16
001F17

OCU compare lower-order data
register 00

H 00000000

H

OCU compare higher-order data
register 00

H 00000000

H

OCU compare lower-order data
register 01

H 00000000

H

OCU compare higher-order data
register 01

H 00000000

Register

name

Access

(Reserved area)

CPR00L

CPR00

CPR01L

CPR01

*1

R/W

R/W

Resouce

name

Output
compare 00

Output
compare 01

Initial value

00000000

00000000

00000000

00000000

00000000

00000000

00000000

001F18
001F19
001F1A
001F1B
001F1C
001F1D
001F1E
001F1F
001F20
001F21
001F22
001F23
001F24
001F25
001F26
001F27

H

OCU compare lower-order data
register 02

H 00000000

H

OCU compare higher-order data
register 02

H 00000000

H

OCU compare lower-order data
register 03

H 00000000

H

OCU compare higher-order data
register 03

H 00000000

H

OCU compare lower-order data
register 04

H 00000000

H

OCU compare higher-order data
register 04

H 00000000

H

OCU compare lower-order data
register 05

H 00000000

H

OCU compare higher-order data
register 05

H 00000000

CPR02L

CPR02

CPR03L

CPR03

CPR04L

CPR04

CPR05L

CPR05

R/W

R/W

R/W

R/W

Output
compare 02

Output
compare 03

Output
compare 10

Output
compare 11

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

(Continued)

30

MB90220 Series

Address Register

001F28
001F29
001F2A
001F2B
001F2C
001F2D
001F2E
001F2F
001F30

H

OCU compare lower-order data
register 06

H 00000000

H

OCU compare higher-order data
register 06

H 00000000

H

OCU compare lower-order data
register 07

H 00000000

H

OCU compare higher-order data
register 07

H 00000000

H

16-bit timer register 0 TMR0 R

001F31
001F32

H XXXXXXXX

H

16-bit reload register 0 TMRLR0 W

001F33
001F34

H XXXXXXXX

H

16-bit timer register 1 TMR1 R

001F35
001F36

H XXXXXXXX

H

16-bit timer reload register 1 TMRLR1 W

001F37

H XXXXXXXX

Register

name

CPR06L

CPR06

CPR07L

CPR07

Access

R/W

R/W

Resouce

name

Output
compare 12

Output
compare 13

16-bit reload
timer 0

16-bit reload
timer 1

Initial value

00000000

00000000

00000000

00000000

XXXXXXXX

XXXXXXXX

XXXXXXXX

XXXXXXXX

001F38
001F39
001F3A
001F3B
001F3C
001F3D
001F3E
001F3F
001F40
001F41
001F42
001F43
001F44
001F45
001F46
001F47

H

XXXXXXXX

16-bit timer register 2 TMR2 R

H XXXXXXXX

H

16-bit reload
timer 2

XXXXXXXX

16-bit timer reload register 2 TMRLR2 W

H XXXXXXXX

H

XXXXXXXX

16-bit timer register 3 TMR3 R

H XXXXXXXX

H

16-bit reload
timer 3

XXXXXXXX

16-bit timer reload register 3 TMRLR3 W

H XXXXXXXX

H

XXXXXXXX

16-bit timer register 4 TMR4 R

H XXXXXXXX

H

16-bit reload
timer 4

XXXXXXXX

16-bit timer reload register 4 TMRLR4 W

H XXXXXXXX

H

XXXXXXXX

16-bit timer register 5 TMR5 R

H XXXXXXXX

H

16-bit reload
timer 0

XXXXXXXX

16-bit timer reload register 5 TMRLR5 W

H XXXXXXXX

(Continued)

31

MB90220 Series

(Continued)

Address Register

001F48

H

PPG cycle setting register 0 PCSR0 W

001F49
001F4A

H XXXXXXXX

H

PPG duty setting register 0 PDUT0 W

001F4B
001F4C

H XXXXXXXX

H

PPG cycle setting register 1 PCSR1 W

001F4D
001F4E

H XXXXXXXX

H

PPG duty setting register 1 PDUT1 W

001F4F
001F50

H XXXXXXXX

H

ICU lower-order data register 0 ICRL0 R

001F51
001F52

H XXXXXXXX

H

ICU higher-order data register 0 ICRH0 R

001F53
001F54

H 00000000

H

ICU lower-order data register 1 ICRL1 R

001F55
001F56

H XXXXXXXX

H

ICU higher-order data register 1 ICRH1 R

001F57

H 00000000

Register

name

Access

Resouce

name

16-bit PPG
timer 0

16-bit PPG
timer 1

Input capture 0

Input capture 1

Initial value

XXXXXXXX

XXXXXXXX

XXXXXXXX

XXXXXXXX

XXXXXXXX

XXXXXXXX

XXXXXXXX

XXXXXXXX

001F58

H

XXXXXXXX

ICU lower-order data register 2 ICRL2 R

001F59

H XXXXXXXX

Input capture 2

001F5A

H

XXXXXXXX

ICU higher-order data register 2 ICRH2 R

001F5B
001F5C

H 00000000

H

XXXXXXXX

ICU lower-order data register 3 ICRL3 R

001F5D

H XXXXXXXX

Input capture 3

001F5E

H

XXXXXXXX

ICU higher-order data register 3 ICRH3 R

001F5F
001F60

to 1FFFH

H 00000000

H

(Reserved area)

*1

Initial value
0: The initial value of this bit is “0”.
1: The initial value of this bit is “1”.
X: The initial value of this bit is undefined.
–: This bit is not used. The initial value is undefined.
*: The initial value of this bit varies with the reset source.
#: The initial value of this bit varies with the operation mode.
*1: Access prohibi ted
*2: Only this area is open to external access in the area below address 0000FF

H (inclusive). All addresses which

are not described in the table are reserved areas, and accesses to these areas are handled in the same
manner as for internal areas. The access signal for the external bus is not generated.

*3: When an external bus is enable mode, never access to resisters which are not used as general ports in areas

address 000000

H to 000005H or 000010H to 000015H.

32

MB90220 Series

■ INTERRUPT SOURCES AND INTERRUPT VECTORS/INTERRUPT CONTROL

REGISTERS

Interrupt source

2

EI

OS

support

Interrupt vector
No. Address ICR Address

Reset × #08 08
INT9 instruction × #09 09
Exception × #10 0A
External interrupt #0 #11 0B

H FFFFDCH ——
H FFFFD8H ——

H FFFFD4H ——
H FFFFD0H

External interrupt #1 #12 0CH FFFFCCH
External interrupt #2 #13 0DH FFFFC8H
Input capture 0 #14 0EH FFFFC4H
PWC0 count completed/overflow #15 0FH FFFFC0H
PWC1 count completed/overflow/input capture 1 #16 10H FFFFBCH
PWC2 count completed/overflow/input capture 2 #17 11H FFFFB8H
PWC3 count completed/overflow/input capture 3 #18 12H FFFFB4H
24-bit timer, overflow #19 13H FFFFB0H
24-bit timer, intermediate bit/timebase timer,

interval interrupt

#20 14

H FFFFACH

Compare 0 #21 15H FFFFA8H
Compare 1 #22 16H FFFFA4H

Interrupt control

register

ICR00 0000B0H

ICR01 0000B1H

ICR02 0000B2H

ICR03 0000B3H

ICR04 0000B4H

ICR05 0000B5H

Compare 2 #23 17H FFFFA0H

ICR06 0000B6H

Compare 3 #24 18H FFFF9CH
Compare 4/6 #25 19H FFFF98H

ICR07 0000B7H

Compare 5/7 #26 1AH FFFF94H
16-bit timer 0/1/2, overflow/PPG0 #27 1BH FFFF90H

ICR08 0000B8H

16-bit timer 3/4/5, overflow/PPG1 #28 1CH FFFF8CH
10-bit A/D converter count completed #29 1DH FFFF88H ICR09 0000B9H
UART1 transmission completed #31 1FH FFFF80H

ICR10 0000BAH

UART1 reception completed #32 20H FFFF7CH
UART0 (ch.1) transmission completed #33 21H FFFF78H

ICR11 0000BBH

UART0 (ch.2) transmission completed #34 22H FFFF74H
UART0 (ch.1) reception completed #35 23H FFFF70H

ICR12 0000BCH

UART0 (ch.2) reception completed #36 24H FFFF6CH
UART0 (ch.0) transmission completed #37 25H FFFF68H ICR13 0000BDH

(Continued)

33

MB90220 Series

(Continued)

Interrupt control

register

Interrupt source

2

OS

EI

support

Interrupt vector
No. Address ICR Address

UART0 (ch.0) reception completed #39 27

H FFFF60H ICR14 0000BEH

Delay interrupt generation module × #42 2AH FFFF54H ICR15 0000BFH
Stack fault × #255 FFH FFFC00H ——

: EI2OS is supported (with stop request).

2

OS is supported (without stop request).

: EI

2

: EI

OS is supported; however, since two interrupt sources ar e al lo cat ed to a si ngl e ICR, in ca se EI2OS is used

for one of the two, EI

2

: EI

OS is supported; however, since two interrupt sources ar e al lo cat ed to a si ngl e ICR, in ca se EI2OS is used

for one of the two, EI

2

: EI

OS is not supported.

2

OS and ordinary interrupt are not both available for the other (with stop request).

2

OS and ordinary interrupt are not both available for the other (without stop request).

Note: Since the interrup t so urce s having i nter r u p t vector Nos. 15 t o 18 , 20 , and 25 to 28 are OR’ed, re sp ec tively,

select them by means of the interrupt enable bits of each resource.

2

OS is used with the above-mentioned interr upt s ources O R’ed wi th the in terr upt vector Nos. 15 to 18,

If EI
20, and 25 to 28, be sure to activate one of the interrupt sources.

Also in this case, a request flag in the same series as the one interrupt source is likely to be cleared
automatically by EI

2

OS.

Assume for example that an interrupt for compare 4 of the interrupt vector No. 25 is activated at this time by

2

ICR07, so that the compare 6 is disabled. If EI

OS is activated at this time by ICR07, so that the compare 6
interrupt takes place during generation of or simultaneously with the compare 4 interrupt, not only the interrupt
flag for the compare 4 but also that for the compare 6 will be automatically cleared after EI

2

OS is automatically

transferred due to the compare 4 interrupt.

34

■ PERIPHERAL RESOURCES

1. Parallel Ports

The MB90220 series has 86 I/O pins and 16 open-drain I/O pins.

(1) Register Configuration

• Port 0 to C Data Register (PDR0 to PDRC)

MB90220 Series

Register name Address

PDR1
PDR3
PDR5
PDR7
PDR9
PDRB

Register name Address

PDR0
PDR2
PDR4
PDR6
PDR8
PDRA
PDRC

Note: There are no register bits for bits 7 and 6 of port C.

000001 H
000003 H
000005 H
000007 H
000009 H
00000B H

000000
000002 H
000004 H
000006 H
000008 H
00000A H
00000C H

PDR7 only:

H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

PD x 7 PD x 6 PD x 5 PD x 4 PD x 3 PD x 2 PD x 1 PD x 0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(R) (R) (R) (R) (R) (R) (R) (R)

bit7 bit6 bit5 bit 4 bit3 bit2 bit1 bit0

PD x 7 PD x 6 PD x 5 PD x 4 PD x 3 PD x 2 PD x 1 PD x 0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

• Port 0 to C Data Register (PDR0 to PDRC)

Register name Address

DDR1
DDR3
DDR5
DDR7
DDRB

000011 H
000013 H
000015 H
000017 H
00001B H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

DD x 7 DD x 6 DD x 5 DD x 4 DD x 3 DD x 2 DD x 1 DD x 0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Initial value

(PDR9 only: 11111111)

XXXXXXXX

Initial value

XXXXXXXX

(PDR6 only: 11111111)

Initial value

00000000

(PDR7 only: 11111111)

B

B

B

Register name Address

DDR0
DDR2
DDR4
DDR8
DDRA
DDRC

Note: There are no register bits for bits 7 and 6 of port C.

000010 H
000012 H
000014 H
000018 H
00001A H
00001C H

bit7 bit6 bit5 bit 4 bit3 bit2 bit1 bit0

DD x 7 DD x 6 DD x 5 DD x 4 DD x 3 DD x 2 DD x 1 DD x 0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

• Port 6, 9 Analog Input Enable Register (ADER0, ADER1)

Register name Address

ADER0

Register name Address

ADER1 000019

000016

H

H

bit7 bit6 bit5 bit 4 bit3 bit2 bit1 bit0

AE07 AE06 AE05 AE04 AE03 AE02 AE01 AE00

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

bit7 bit6 bit5 bit 4 bit3 bit2 bit1 bit0

AE15 AE14 AE13 AE12 AE11 AE10 AE09 AE08

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Initial value

00000000

Initial value

11111111

Initial value
11111111 B

B

B

35

MB90220 Series

(2) Block Diagram

• I/O Port (Port 0 to 5, 8, and A to C)

Data register read

Data register

Data register write

Direction register

Internal data bus

Direction register write

Direction register read

• I/O Ports with an Open-drain output (Port 6, and 9)

RMW
(read-modify-write instruction)

Data register read

Data register

Data register write

ADER

Internal data busInternal data bus

ADER register write

Pin

Pin

• I/O Port (Port 7)

36

ADER register read

DOT0 to DOT3 (OCU)

4

4

4

Port 7

Note: Port 7 is input port. This pin also usable as I/O port for OCU internal function.

Data register read

Direction register

Direction register write

Direction register read

Pin

MB90220 Series

2. 16-bit Reload Timer (with Event Count Function)

The 16-bit reload timer 1 consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), an output
pin (TOT), and a control r egister. The input clock can be selected f rom among three i nternal cl ocks and one
external clock. At the output pin (TOT), the pulses in the toggled output waveform are output in the reload mode;
the rectangular pulses indicating that the timer is counting are in the single-shot mode. The input pin (TIN) can
be used for event input in the event count mode, and for trigger input or gate input in the internal clock mode.

The MB90220 series has six channels for this timer.

(1) Register Configuration

• Timer Control Status Register 0 to 5 (TMCSR0 to TMCSR5)

Register name Address

TMCSR0
TMCSR1
TMCSR2
TMCSR3
TMCSR4
TMCSR5

Register name Address

TMCSR0
TMCSR1
TMCSR2
TMCSR3
TMCSR4
TMCSR5

000041 H
000043 H
000045 H
000047 H
000049 H
00004B H

000040
000042 H
000044H
000046 H
000048 H
00004A H

bit15 bit14 bit13 bit12 bit11 bit10 bit9

————CSL1 CSL0 MOD2

(—) (R/W)(—) (—) (—) (R/W) (R/W) (R/W)

H

bit7 bit6 bit5 bit4 bit3 bit2 bit1

MOD0 OUTE OUTL RELD INTE UF CNTE

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

• 16-bit Timer Register 0 to 5 (TMR0 to TMR5)

Register name Address

TMR0
TMR1
TMR2
TMR3
TMR4
TMR5

Register name Address

TMR0
TMR1
TMR2
TMR3
TMR4
TMR5

001F31 H
001F35 H
001F39H
001F3D H
001F41 H
001F45H

001F30 H
001F34 H
001F38H
001F3C H
001F40H
001F44 H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

(R) (R) (R) (R) (R) (R) (R) (R)

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

(R) (R) (R) (R) (R) (R) (R) (R)

MOD1

bit8

TRG

bit0

Initial value

- - - - 0000

Initial value

00000000 B

Initial value
XXXXXXXX

Initial value
XXXXXXXX

B

B

B

• 16-bit Timer Reload Register 0 to 5 (TMRLR0 to TMRLR5)

Register name Address

TMRLR0
TMRLR1
TMRLR2
TMRLR3
TMRLR4
TMRLR5

001F33 H
001F37 H
001F3BH
001F3F H
001F43 H
001F47 H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

(W) (W) (W) (W) (W) (W) (W) (W)

Initial value
XXXXXXXX

B

37

MB90220 Series

Register name Address

TMRLR0
TMRLR1
TMRLR2
TMRLR3
TMRLR4
TMRLR5

001F32
001F36 H
001F3A H
001F3E H
001F42 H
001F46 H

(2) Block Diagram

16

8

16

Internal data bus

2

H

16-bit reload register

16-bit down counter

2

Clock selector

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

(W) (W) (W) (W) (W) (W) (W) (W)

Reload

UF

OUT
CTL.

2

Retrigger

EXCK

GATE

CSL1
CSL0

IN CTL.

RELD
OUTE
OUTL

INTE

UF

CNTE

TRG

Initial value
XXXXXXXX

Port (TIN)

IRQ

2

EI

OS clear

B

38

φφφ

21232

Internal clock

3

5

Prescaler clear

3

MOD2
MOD1
MOD0

A/D (timer ch3 output)
UART0 (timer ch5 output)
UART1 (timer ch4 output)

Port (TOT)

MB90220 Series

3. UART0

UART0 is a serial I/O port for synchronous or asynchronous communication with external resources. It has the
following features:

• Full duplex double buffer

• CLK synchronous and CLK asynchronous data transfers capable

• Multiprocessor mode support (Mode 2)

• Built-in dedicated baud-rate generator (12 rates)

• Arbitrary baud-rate setting from external clock input or internal timer

• Variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit))

• Error detection function (Framing, overrun, parity)

• Interrupt function (Two sources for transmission and reception)

• Transfer in NRZ format
The MB90220 has three of these modules on chip.

(1) Register Configuration

• Mode Control Register 0 to 2 (UMC0 to UMC2)

Serial mode control register
Register name Address

UMC0
UMC1
UMC2

000020 H
000024 H
000028 H

bit7 bit6 bit5 bit4 bit3 bit2 bit1

PEN SBL MC1 MC0 SMDE RFC SCKE

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

SOE

bit0

Initial value
00000100

• Status Register 0 to 2 (USR0 to USR2)

Register name Address

USR0
USR1
USR2

000021
000025 H
000029 H

H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

RDRF ORFE PE TDRE RIE TIE RBF TBF

(R) (R)(R) (R) (R) (R/W) (R/W) (R)

Initial value

00001000 B

• Input Data Register 0 to 2 (UIDR0 to UIDR2)/Ouput Data Register 0 to 2 (UODR0 to UODR2)

Register name Address
UIDR0/UODR0
UIDR1/UODR1
UIDR2/UODR2

000022
000026 H
00002A H

H

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

D7 D6 D5 D4 D3 D2 D1 D0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Initial value

XXXXXXXX

• Rate and Data Register 0 to 2 (URD0 to URD2)

Register name Address

URD0
URD1
URD2

000023
000027 H
00002B H

H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

BCH RC3 RC2 RC1 RC0 BCH0 P D8

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Initial value

0000000X

B

B

B

• UART CTS Control Register (UCCR)

Register name Address

UCCR

00002C H

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

———

(—) (—) (—) (R/W) (R/W) (R/W) (—) (—)

CTE CSP CTSE

——

Initial value

- - - 000 - -

B

39

MB90220 Series

(2) Block Diagram

CONTROL BUS

Receiving interrupt
(to CPU)

Dedicated baud rate clock

16-bit reload timer 5
(internally connected)

External clock

SID

Received status

determination circuit

Clock selector

Receiving clock

Receiving controller

Start bit detector

Received bit counter

parity counter

Receiving shifter

Received

Transmitting clock

Transmitted bit counter

SCK

Transmission interrupt
(to CPU)

Transmission controller

Transmission

start circuit

Transmission
parity counter

SOD

Transmitting shifter

40

UMC

register

Signal indicating occurrence
of receiving error for EI

PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE

2

OS (to CPU)

End of
reception

UIDR

Internal data bus

USR

register

RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF

URD

register

Start of
transmission

UODR

BCH
RC3
RC2
RC1
RC0
BCH
P
D8

CONTROL BUS

MB90220 Series

4. UART1

The UART1 is a serial I/O port for asynchronous communications (start-stop synchronization) or CLK
synchronized communications. It has the following features:

• Full-duplex double buffering

• Permits asynchronous (start-stop synchronization) and CLK synchronous communications

• Multiprocessor mode support

• Built-in dedicated baud rate generator
Asynchronous: 9615, 31250, 4808, 2404, and 1202 bps
CLK synchronization: 1 M, 500 K, 250 K bps

• Arbitray baud-rate setting from external clock input or internal timer

• Error detection function (parity errors, framing errors, and overrun errors)

• Transfer in format NRZ

• Extended supports intelligent I/O service

(1) Register Configuration

• Mode Register (SMR)

Register name Address

SMR

00002E

bit7 bit6 bit5 bit4 bit3 bit2 bit1

H

MD1 MD0 CS2 CS1 CS0 BCH SCKE SOE

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

• SCR (Control Register)

Register name Address

SCR

00002F

bit15 bit14 bit13 bit12 bit11 bit10 bit9

H

PEN P SBL CL A/D REC RXE TXE

(R/W) (R/W) (R/W) (R/W) (R/W) (R) (R/W) (R/W)

• Input Data Register (SIDR)/Serial Output Data Register (SODR)

Register name Address

SIDR

Register name Address

SODR

000030

000030

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

H

D7 D6 D5 D4 D3 D2 D1 D0

(R) (R) (R) (R) (R) (R) (R) (R)

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

H

D7 D6 D5 D4 D3 D2 D1 D0

(W) (W) (W) (W) (W) (W) (W) (W)

• SSR (Status Register)

bit0

bit8

Initial value
00000000

Initial value
00000100

Initial value
XXXXXXXX

XXXXXXXXB

B

B

B

Register name Address

SSR

000031

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

H

PE ORE FRE RDRF TDRE — RIE TIE

(R) (R) (R) (R) (R) (R/W) (R/W)

Initial value
00001-00

B

41

MB90220 Series

(2) Block Diagram

Control signals

Receiving interrupt
(to CPU)

Dedicated baud rate generator

16-bit reload timer 4
(internally connected)

Clock selector

External clock

SID3

Received status

determination circuit

Receiving clock

Receiving controller

Start bit detector

Receiving shifter

Received

bit counter

Received

parity counter

Transmitting clock

Transmission controller

SCK3

Transmission interrupt
(to CPU)

Transmission

start circuit

Transmitted

bit counter

Transmission
parity counter

SOD3

Transmitting shifter

42

SMR

register

Signal indicating occurrence
of receiving error for EI

MD1
MD0
CS2
CS1
CS0
BCH
SCKE
SOE

2

OS (to CPU)

End of
reception

SIDR

Internal data bus

SCR

register

PEN
P
SBL
CL
A/D
REC
RXE
TXE

SSR

register

Start of
transmission

SODR

PE
ORE
FRE
RDRF
TDRE

RIE
TIE

Control signals

MB90220 Series

5. 10-bit A/D Converter

The 10-bit A/D converter converts analog in put voltage into a digital va lue. The features of this module are
described below:

• Conversion time: 6.125 µs/channel (min.) (with machine clock running at 16 MHz)

• Uses RC-type sequential comparison and conversion method with built-in sample and hold circuit

• 10-bit resolution

• Analog input can be selected by software from among 16 channels

Single-conversion mode: Selects and converts one channel.
Scan conversion mode: Converts several consecutive channels (up to 16 can be programmed).
One-shot mode: Converts the specified channel once and terminates.
Continuous conversion mode: Repeatedly converts the specified channel.
Stop conversion mode: Pauses after converting one channel and waits until the next startup (permits

synchronization of start of conversion).

• When A/D conversion is completed, an “A/D conversion complete” interrupt request can be issued to the CPU.

Because the generation of this in terrupt can be used to star t up the EI
results to memory, this function is suitable for continuous processing.

• Startup triggers c an be selec ted from among so ftware, an ex ternal tri gger (fall ing edge), and a time r (rising

edge).

2

OS and transfer the A/D conversion

(1) Register Configuration

• A/D Channel Setting Register (ADCH)

This register specfies the A/D converter conversion channel.

Register name Address

ADCH

000032

bit7 bit6 bit5 bit4 bit3 bit2 bit1

H

ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

• A/D Mode Register (ADMD)

This register specfies the A/D converter operation mode and the startup source.

Register name Address

ADMD

Note: Program “0” to bit 12 when write. Read value is indeterminated.

000033H

bit15 bit14 bit13 bit12 bit11 bit10 bit9

— — — MOD1 MOD0 STS1 STS0

• A/D Control Status Register (ADCS)

This register is the A/D converter control and status register.
Register name Address

ADCS

000034H

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

BUSY INT INTE PAUS — — STRT

• A/D Data Register (ADCD)

Reserved

bit0

bit8

(R/W)(—) (R/W)(—) (—) (W) (R/W) (R/W)

Reserved

(—)(R/W) (W)(R/W) (R/W) (R/W) (—) (R/W)

Initial value
00000000

Initial value

- - - X0000 B

Initial value
0000 - - 00 B

B

This register stores the A/D converter conversion data.

Register name Address

ADCD

000036H

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

D7 D6 D5 D4 D3 D2 D1 D0

(R) (R) (R) (R) (R) (R) (R) (R)

Initial value
XXXXXXXX B

43

MB90220 Series

Register name Address

ADCD

(2) Block Diagram

MPX

AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15

000037

Input circuit

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

H

——————

(R) (R) (R) (R) (R) (R) (R) (R)

AVCC

AVRH/AVRL

D/A converter

Sequential

comparison register

Comparator

Sample and hold circuit

D9 D8

SS

AV

Initial value
000000XX B

44

ATG

Trigger startup

Timer startup

Timer
(16-bit reload timer 3 output)

φ

Machine clock

Decoder

Internal data bus

A/D data register

ADCD

A/D channel setting register

ADCH

A/D mode register

ADMD

A/D control status register

ADCS

Operation clock

Prescaler

MB90220 Series

6. PWC (Pulse Width Count) Timer

The PWC (pulse width count) timer is a 16-bit multifunction up-count timer with an input-signal pulse-width count
function and a reload timer function. The hardware co nfiguration of this module is a 16-bi t up-count timer, an
input pulse divi der with divide ratio control regist er, four count input pins, and a 16-bit contro l register. Using
these components, the PWC timer provides the following features:

• Timer functions: An interrupt request can be generated at set time intervals.

Pulse signals synchronized with the timer cycle can be output.
The reference internal clock can be selected from among three internal clocks.

• Pulse-width count functions: The time between arbitrary pulse input events can be counted.

The reference internal clock can be selected from among three internal clocks.
Various count modes:

“H” pulse width (↑ to ↓)/“L” pulse width (↓ to ↑)
Rising-edge cycle (↑ to ↑/Falling-edge cycle (↓ to ↓)
Count between edges (↑ or ↓ to ↓ or ↑)

2n

Cycle count can be performed by 2
pulse, with an 8 bit input divider.
An interrupt request can be generated once counting has been performed.
The number of times counting is to be performed (once or subsequently) can
be selected.

division (n = 1, 2, 3, 4) of the input

The MB90220 series has four channels for this module.

(1) Register Configuration

• PWC Control Status Register 0 to 3 (PWCSR0 to PWCSR3)

Register name Address

PWCSR0
PWCSR1
PWCSR2
PWCSR3

Register name Address

PWCSR0
PWCSR1
PWCSR2
PWCSR3

000051
000053 H
000055 H
000057 H

000050
000052 H
000054 H
000056 H

H

H

bit15 bit14 bit13 bit12 bit11 bit10 bit9

STRT STOP EDIR EDIE OVIR OVIE ERR POUT

(R/W) (R/W) (R) (R/W) (R/W) (R/W) (R) (R/W)

bit7 bit6 bit5 bit4 bit3 bit2 bit1

CKS1 CKS0 PIS1 PIS0 S/C MOD1 MOD1 MOD0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

• PWC Data Buffer Register 0 to 3 (PWCR0 to PWCR3)

Register name Address

PWCR0
PWCR1
PWCR2
PWCR3

Register name Address

PWCR0
PWCR1
PWCR2
PWCR3

001F01 H
001F03 H
001F05 H
001F07 H

001F00 H
001F02 H
001F04 H
001F06 H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

bit8

bit0

Initial value
00000000B

Initial value

00000000

Initial value
00000000

Initial value
00000000

B

B

B

45

MB90220 Series

• PWC Division Ratio Control Register 0 to 3 (DIVR0 to DIVR3)

Register name Address

DIVR0
DIVR1
DIVR2
DIVR3

00007A H
00007C H
00007E H
000080 H

(2) Block Diagram

PWCR read

Write enable

Overflow

16

16

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

——————MOD1 MOD0

(—) (—) (—) (—) (—) (—)

Error detector

Reload
Data transfer

16-bit up-count timer

Controller

ERR

PWCR

16

16

Timer clear

Clock

Count enable

(R/W) (R/W)

Internal clock
(machine clock/4)

CKS 1
CKS 0

Divider clear

2

2

3

2

Initial value

- - - - - - 00

Clock divider

B

Start edge

Internal data bus

Flag set, etc.

15

*: In the MB90220 series, only the module input PWC 0 of each channel is connected to the respective external pins.

Count end edge

Count end interrupt request

Control bit output

Overflow interrupt
request

Count
start edge

PWCSR

select

Edge
detector

ERR

End edge
select

Channel

PWC ch. 0
PWC ch. 1
PWC ch. 2

PWC ch. 3

Division on/off

CKS 1

PIS 1

CKS 0

PIS 0

Divider

selection

2

DIVR

POT pin

PA 1/PWC 0/POT 0
PA 2/PWC 1/POT 1/ASR 1
PA 3/PWC 2/POT 2/ASR 2
PA 4/PWC 3POT 3/ASR 3

8-bit
divider

Overflow

PIS 1
PIS 0

F.F.

POT

PWC 0
PWC 1
PWC 2
PWC 3

*

46

MB90220 Series

7. DTP/External Interrupts

DTP (Data Transfer Peripheral) is located between external per ipherals and the F2MC-16F CPU. It receives a

2

DMA request or an interrupt request generated by the external peripherals and reports it to the F
to activate the extended intelligent I/O service or interrupt handler. The user can select two request levels of “H”
and “L” for extended intelligent I/O service or, and four request lev els of “H,” “L,” rising edge and falling edge for
external interrupt requests. In MB90220, only par ts corresponding to INT2 to INT0 are usable as external
interrupt/DTP request.

Parts corresponding to INT7 to INT3 cannot be used as external interrupt/DTP request, but only for edge
detection at external terminals.

Note: INT7 to INT3 are not usable as DTP/external interrupts.

(1) Register Configuration

• DTP/Interrupt Enable Register (ENIR)

MC-16F CPU

Register name Address

ENIR

00003A

H

bit7 bit6 bit5 bit4 bit3 bit2 bit1

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

• DTP/Interrupt Source Register (EIRR)

Register name Address

EIRR

00003B

bit15 bit14 bit13 bit12 bit11 bit10 bit9

H

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

• Request Level Setting Register (ELVR)

Register name Address

ELVR

Register name Address

ELVR

00003D

00003C H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

H

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(2) Block Diagram

bit0

bit8

Initial value
00000000

Initial value
00000000B

Initial value
00000000

Initial value

00000000

B

B

B

4

4

4

Internal data bus

8

Interrupt/DTP enable register

Gate

Interrupt/DTP source register

Request level setting register

Source F/F

Edge detector

8

INT

47

MB90220 Series

8. 24-bit Timer Counter

The 24-bit time r counte r c onsists of a 24-b it up-c ounter , an 8-bit o utput b uffer registe r, an d a c ontro l regis ter.
The count value output by this timer counter is used to generate the base time used for input capture and output
compare.

The interrupt functions provided are timer overflow interrupts and timer intermediate bit interrupts. The
intermediate bit interrupt permits four time settings.

The 24-bit timer counter value is cleared to all zeroes by a reset.

(1) Register Configuration

• Free-run Timer Control Register (TCCR)

Register name Address

TCCR

Register name Address

TCCR

000071 H

000070

bit15 bit14 bit13 bit12 bit11 bit10 bit9

—

bit7 bit6 bit5 bit4 bit3 bit2 bit1

H

CLR2 CLR IVF IVFE TIM TIME TIS1 TIS0

Reserved Reserved Reserved ReservedReserved

— PR0

• Free-run Timer Low-order Data Register (TCRL)

Register name Address

TCRL

000072
000073 H

bit15 bit0

H

TCRL

• Free-run Timer High-order Data Register (TCRH)

Register name Address

TCRH

000074
000075 H

bit15 bit0

H

—

bit8 bit7

bit8

(R/W)(—) (R/W)(—) (W) (W) (R/W) (R/W)

bit0

(R/W)(W) (R/W)(W) (R/W) (R/W) (R/W) (R/W)

TCRH

Initial value

- - 111111B

Initial value
11000000B

Initial value
00000000 B

Initial value
00000000 B

Access

R

Access

R

48

(2) Block Diagram

Internal
basic
clock

2

2

Clear bit

CLR
CLR2

φ/3
φ/4

2

CK0
CK1

PR0

MB90220 Series

Timer counter clocks

2

CK0
CK1
CLR (prescaler clear)
CLR2 (prescaler clear, 24-bit timer counter STOP bit)

CLR/CLR2

2

Lower-order 16-bit counter

2

4

Higher-order 8-bit counter

Carry

8

CK0, CK1

Timer counter bit output

8

T23 to T16

16

T0 to T15

16

Internal data bus

16

2

4

TIS1
TIS0

Intermediate bit interrupt
cycle setting

IVF IVFE TIM TIME

“0”

10th bit
11th bit
12th bit
13th bit

Interrupt enable
Interrupt flag

Output buffer

16

23rd bit

Intermediate bit interrupt request

TIM

Overflow interrupt request

IVF

49

MB90220 Series

9. OCU (Output Compare Unit)

The OCU (Output Compa re Unit) consists of a 24-bit o utput compare register, a com parator, and a control
register.

The match detection sign al is output when the conten ts of the output compare regi ster match the contents of
the 24-bit timer counter. This match detection signal can be used to change the output value of the corresponding
pin, or can be used to gener ate an interrupt. One block c onsists of four output comp are units, and the four
output compare registers use one comparator to perform time division comparisons.

(1) Register Configuration

• OCUO Control Register 00, 01 (CCR00, CCR01)

Register name Address

CCR00
CCR02

Register name Address

CCR00
CCR02

000061 H
000063 H

000060
000062 H

H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

————MD3MD2MD1MD0

(—) (—) (—) (—) (R/W) (R/W) (R/W) (R/W)

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

SEL3 SEL2 SEL1 SEL0 CPE3 CPE2 CPE1 CPE0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

• OCUO Control Register 10, 11 (CCR10, CCR11)

Register name Address

CCR10
CCR11

Register name Address

CCR10
CCR11

000069
00006B H

000068
00006A H

H

H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

ICE3 ICE2 ICE1 ICE0 IC3 IC2 IC1 IC0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

————DOT3 DOT2 DOT1 DOT0

(—) (—) (—) (—) (R/W) (R/W) (R/W) (R/W)

• OCU Compare Low-order Data Register 00 to 07 (CPR00L to CPR07L)

Register name Address

CPR00L
CPR01L
CPR02L
CPR03L
CPR04L
CPR05L
CPR06L
CPR07L

Register name Address

CPR00L
CPR01L
CPR02L
CPR03L
CPR04L
CPR05L
CPR06L
CPR07L

001F11
001F15 H
001F19 H
001F1D H
001F21 H
001F25 H
001F29 H
001F2D H

001F10 H
001F14 H
001F18 H
001F1C H
001F20 H
001F24 H
001F28 H
001F2C H

H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

——

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Initial value

- - - - 0000

Initial value

11110000

Initial value

00000000

Initial value

- - - - 0000

Initial value
00000000

Initial value
00000000

50

MB90220 Series

• Output Compare High-order Data Register 00 to 07 (CPR00H to CPR07H)

Register name Address

CPR00
CPR01
CPR02
CPR03
CPR04
CPR05
CPR06
CPR07

Register name Address

CPR00
CPR01
CPR02
CPR03
CPR04
CPR05
CPR06
CPR07

001F13 H
001F17 H
001F1B H
001F1F H
001F23 H
001F27 H
001F2B H
001F2F H

001F12 H
001F16 H
001F1A H
001F1E H
001F22 H
001F26 H
001F2A H
001F2E H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

(R) (R) (R) (R) (R) (R) (R) (R)

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

——

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Initial value
00000000

Initial value
00000000

51

MB90220 Series

(2) Block Diagram

24-bit timer counter

22

Comparator controller

814

Output latch Output latch

8

24
24
24
24

Match source signals
EXT0 to 3

Match detection signal selection

8

CPR03
CPR02
CPR01
CPR00

Output

compare register

higher-order 8 bits

8
4

SEL3 SEL2 SEL1 SEL0 CPE3 CPE2 CPE1 CPE0

T2 to T23

compare register

lower-order 16 bits

14

CPR03L
CPR02L
CPR01L
CPR00L

Output

Compare unit*

Match signal

ICE3
ICE2
ICE1
ICE0

IC3
IC2
IC1
IC0

4

4

Source

selector

Match operation enable

Interrupt enable ICE0 to 3

Interrupt flags IC0 to 3

4

4

MATCH0 to 3

Interrupt
request signals

4

ICMP0 to 3

24-bit timer counter

Internal data bus

data T0

4

4

4

4

Data register read

Direction register write

4

Direction register read

Port 7

Port general purpose/compare dedicated switching

MD3 MD2 MD1 MD0

DOT pin data output
(also serves as general-purpose port data register)

DOT3 DOT2 DOT1 DOT0

Direction register

Clock

selector

Pin

44

Output latch

DOT0 to 3

52

(Continued)

(Continued)

Internal data bus
timer count data

*: There are two compare units drawn as below.

OPEN

Compare unit

MATCH 0 to 3
T1 to T23
RB15 to 0

EXT 0 to 3
MATCH 0 to 3

T1 to T23
RB15 to 0

EXT 0 to 3

Compare 00 to 03

Compare 10 to 13

23

4

16

16

ICOMP 0 to 3

DOT 0 to 3

ICOMP 0 to 3

DOT 0 to 3

MB90220 Series

Interrupt request ICOMP 0 to 3

4

Pin output
DOT 0 to 3

ICOMP 0, 2

4
4

Pin output
DOT 4 to 7

2
2

ICOMP 1, 3

OR
OR

Interrupt request

ICOMP 4/6
ICOMP 5/7

53

MB90220 Series

10. ICU (Input Capture Unit)

This module detects either the rising edge, falling edge, or both edges of an externally input waveform and holds
the value of the 24-bit timer counter at that time, while at the s ame time the module g enerates an interrupt
request for the CPU. The module consists of a 24-bit input capture data register and a control register. There
are four external input pins (ASR0 to ASR3); the operation of each input is described below.

ASR0 to ASR3: Each of these input pins has a corresponding input capture register. When the specified

valid edge (↑ or ↓ or ↑ ↓) is detected, the register can be used to store the 24-bit timer
counter value.

(1) Register Configuration

• ICU Control Register 0 (ICC0)

Register name Address

ICCO

000058 H

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

EG3B EG3A EG2B EG2A EG1B EG1A EG0B EG0A

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

• ICU Control Register 1 (ICC1)

Register name Address

ICCI

00005A

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

H

IRE3 IRE2 IRE1 IRE0 IR3 IR2 IR1 IR0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

• ICU Low-order Data Register (ICRL0 to ICRL3)

Register name Address

ICRL0
ICRL1
ICRL2
ICRL3

Register name Address

ICRL0
ICRL1
ICRL2
ICRL3

001F50
001F54 H
001F58 H
001F5C H

001F51 H
001F55 H
001F59 H
001F5D H

H

bit15 bit14 bit13 bit12 bit11 bit10 bit9

D15 D14 D13 D12 D11 D10 D09

(R) (R) (R) (R) (R) (R) (R) (R)

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

D07 D06 D05 D04 D03 D02 D01 D00

(R) (R) (R) (R) (R) (R) (R) (R)

D08

Initial value

00000000

Initial value

00000000B

bit8

B

Initial value
XXXXXXXX

Initial value

XXXXXXXX

B

B

• ICU High-order Data Register (ICRH0 to ICRH3)

Register name Address

ICRH0
ICRH1
ICRH2
ICRH3

Register name Address

ICRH0
ICRH1
ICRH2
ICRH3

001F52
001F56 H
001F5A H
001F5E H

001F53 H
001F57 H
001F5B H
001F5F H

H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

————————

(R) (R) (R) (R) (R) (R) (R) (R)

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

D23 D22 D21 D20 D19 D18 D17 D16

(R) (R) (R) (R) (R) (R) (R) (R)

54

Initial value

XXXXXXXXB

Initial value
00000000B

(2) Block Diagram

MB90220 Series

8

24-bit timer counter input
T23
to T0

Internal data bus

24

8

ICRH0
ICRH1
ICRH2
ICRH3

8

16

4

4

Output latch

Capture

T23 to
T16

EG3B EG3A EG2B EG2A EG1B EG1A EG0B EG0A

16

ICRL0
ICRL1
ICRL2
ICRL3

IR0
IR1
IR2
IR3

T15 to T00

Interrupt request flags (ICC1)

8

Edge detection 0
Edge detection 1
Edge detection 2
Edge detection 3

Edge detection 0 to 3:

↑ or ↓ or ↑↓

4

4

IRE3 IRE2 IRE1 IRE0 Interrupt enable

(ICC1)

Edge detection
polarity (ICC0)

ASR0

ASR1

ASR2

ASR3

EGO0 to EGO3

EGI0 to EGI3

4

IRQ0 to IRQ3

55

MB90220 Series

11. 16-bit PPG Timer

This module can output a pulse synchronized with an external trigger or a software trigger. In addition, the cycle
and duty ratio of the output pulse can be changed as desired by overwriting the two 16-bit register values.

PWM function: Synchronizes pulse with trigger, and permits programming of the pulse output by

overwriting the register values mentioned above.
This function permits use as a D/A converter with the addition of external circuits.

One-shot function: Detects the edge of trigger input, and permits single-pulse output. There is no

trigger input for PPG1.

This module consi sts of a 16-bit down- counter, a presca ler, a 16-bit s ynchronizat ion setting re gister, a 16-bit
duty register, a 16-bit control register, one external trigger input pin, and one PPG output pin.

(1) Register Configuration

• PPG Control Status Register (PCNT0, PCNT1)

Register name Address

PCNT0
PCNT1

Overwrite during operation→

Register name Address

PCNT0
PCNT1

Overwrite during operation→

0004D H
0004F H

0004C
0004E H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

CNTE STGR MDSE RTRG CKS1 CKS0 PGMS —

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

H

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

EGS1 EGS0 IREN IRQF IRS1 IRS0 POEN OSEL

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

• PPG0, PPG1 Cycle Setting Register (PCSP0, PCSP1)

Register name Address

PCSP0
PCSP1

Register name Address

PCSP0
PCSP1

001F49
001F4D H

001F48 H
001F4C H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

H

(W) (W) (W) (W) (W) (W) (W) (W)

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

(W) (W) (W) (W) (W) (W) (W) (W)

• PPG0, PPG1 Duty Setting Register (PDUT0, PDUT1)

Register name Address

PDUT0
PDUT1

001F4B H
001F4F H

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

(W) (W) (W) (W) (W) (W) (W) (W)

Initial value
00000000B

Initial value

00000000B

Initial value
XXXXXXXX

Initial value
XXXXXXXXB

Initial value
XXXXXXXXB

B

Register name Address

PDUT0
PDUT1

56

001F4A H
001F4E H

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

(W) (W) (W) (W) (W) (W) (W) (W)

Initial value
XXXXXXXXB

(2) Block Diagram

Prescaler

MB90220 Series

PDUTPCSR

1/1
1/4
1/16
1/64

Oscillation clock

TRG input

ck Load

16-bit down-counter

Start Borrow

Enable

Edge detection

PPG mask

S Q

R

Reverse bit

Interrupt

selector

cmp

PPG output

IRQ

Software trigger

57

MB90220 Series

(—)(—)(—)(

)(

)(R)(

)(

)

12. Watchdog Timer and Timebase Timer Functions

The watchdog timer consists of a 2-bit watchdog counter using carry from an 18-bit timebase timer as the clock
source, a control register, and a watchdog reset control section. The timebase timer consists of an 18-bit timer
and an interval interrupt control circuit.

(1) Register Configuration

• Watchdog Timer Control Register (WDTC)

Register name Address

WDTC

0000A8 H

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

PONR STBR WRST ERST SRST WTE WT1 WT0

(R) (R) (R) (R) (R) (W) (W) (W)

• Timebase Timer Control Register (TBTC)

Register name Address

TBTC

0000A9

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

H

———

(2) Block Diagram

TBTC
TBC1

TBC0
TBR

TBIE

AND

TBOF

Selector

S

QR

12

2

14

2

16

2

18

2
TBTRES

TBIE TBOF TBR TBC1 TBC0
R/W

R/W

Clock input

Timebase timer

2142162172

R/W

18

R/W

Oscillation clock

Initial value

XXXXXXXX

Initial value

- - - XXXXX

58

Timebase
interrupt

WDTC

WT1

Internal data bus

WT0

WTE

PONR

STBR

WRST

ERST
SRST

Selector

2-bit counter

OF

CLR

Watchdog reset
signal generator

CLR

WDGRST
To internal reset signal generator

From power-on signal generator
From hardware standby controller

RST pin
From RST bit of STBYC register

MB90220 Series

(—)(—)(—)(—)(—)(—)(—)(

)

13. Delay Interruupt Generation Module

The delayed i nterrupt generation module is use d to generate an interrupt task switching. U sing this module
allows an interrupt request to the F

(1) Register Configuration

• Delay Interrupt Source Generation/Cancel Register (DIRR)

2

MC-16F CPU to generated or cancel by software.

Register name Address

DIRR

(2) Block Diagram

00009F H

Internal data bus

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

———————R0

R/W

Delay interrupt source generation/cancel decoder

Source latch

Initial value

- - - - - - - 0

59

MB90220 Series

(—)(—)(—)(

)(—)(—)(—)(—)

14. Write-inhibit RAM

The write-inhibit RAM is write-prote ctable with the WI pin input . Maintaining the “L” level in put to the WI pin
prevents a certain area of RAM from being written. The WI

(1) Register Configuration

• WI Control Register (WICR)

pin has a 4-machine-cycle filter.

Register name Address

WICR

00008E H

(2) Write-inhibit RAM Areas

Write-inhibit RAM areas: 000D00

001300
001500

(3) Block Diagram

WI

4-machine cycle smoothing circuit
4-machine cycle smoothing circuitSR

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

———WI————

R/W

H to 000EFFH (MB90223)
H to 0014FFH (MB90224/P224A/P224B/W224A/W224B)
H to 0018FFH (MB90V220)

Q

Write-inhibit

circuit

Select

RAM

decoder

WR

Other area access

L

H

Q

Priority

S
R

Internal data bus

Initial value

- - - X - - - -

Write-inhibit

RAM

60

MB90220 Series

15. Low-power Consumption Modes, Osci llation Stabil ization Delay Time, and Gear Function

The MB90220 series has three low-power consumption modes: the sleep mode, the stop mode, the hardware
standby mode, and gear function.

Sleep mode is used to suspend only the CPU operation clock; the other components remain in operation. Stop
mode and hardware standby mode stop oscillation, minimizing the power consumption while holding data.

The gear function divides the external clock frequency, which is used usually as it is, to provide a lower machine
clock frequency. This function can th er efore lower the overall operation spee d wi tho ut c ha ngi ng the os ci llati on
frequency. The function can select the machine clo ck as a division of the freque ncy of crystal oscillation or
external clock input by 1, 2, 4, or 16.

The OSC1 and OSC0 bits can be used to set the oscillation stabilization delay time for wake-up from stop mode
or hardware standby mode.

(1) Register Configuration

• Standby Control Register (STBYC)

Register name Address

STBYC

0000A0 H

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

STP SLP SPL RST OSC1 OSC0 CLK1 CLK0

(W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Note: The initial value (*) of bit0 to bit3 is changed by reset source.

Initial value

0001* * * *

61

MB90220 Series

(2) Block Diagram

STBYC

CLK1

CLK0

SLP
STP

Internal data bus

OSC1

OSC0

Gear divider

1/1 1/2 1/4 1/16

Selector

Standby controller

Release HST start

RST

Selector

Oscillation clock

CPU clock

CPU clock

generator

Peripheral clock

Peripheral clock

generator

HST pin

Interrupt request or RST

0

2

16

2

17

2

18

2

Timebase timer

Clock input

14

16217218

2

2

SPL

RST

Pin high impedance controller

Internal reset

signal generator

Pin Hi-Z

RST pin

Internal RST

To watchdog timer
WDGRST

62

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Parameter

Symbol Pin name

MB90220 Series

(VSS = AVSS = 0.0 V)

Value

Unit Remarks

Min. Max.

Power supply voltage V
Program voltage V

Analog power su pply
voltage

Input voltage
Output voltage V
“L” level output current I
“L” level total output

current
“H” level output current I
“H” level total output

current
Power consumption P

Operating temperature T

CC VCC VSS – 0.3 VSS + 7.0 V
PP VPP VSS – 0.3 13.0 V

CC AVCC VSS – 0.3 VCC + 0.3 V

AV

MB90P224A/P224B
MB90W224A/W224B

Power supply voltage
for A/D converter

Reference voltage for

AVRH
AVRL

1

V

I*

O

OL

ΣI

OL

OH

ΣI

OH

D ——650mW

A —

AVRH
AVRL

V

SS – 0.3 AVCC V

—VSS – 0.3 VCC + 0.3 V

2

*

3

*

3

*

2

*

2

*

VSS – 0.3 VCC + 0.3 V

— 20 mA Rush current
— 50 mA Total output current
— –10 mA Rush current
— –48 mA Total output current

–40 +105 °C

A/D converter

MB90223/224/P224B
/W224B

–40 +85 °C MB90P224A/W224A

Storage temperature Tstg — –55 +150 °C

*1: V

1 must not exceed VCC + 0.3 V.

*2: Output pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77, P80 to

P87, PA0 to PA7, PB0 to PB7, PC0 to PC5

*3: Output pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to

P77, P80 to P87, P90 to P97, PA0 to PA7, PB0 to PB7, PC0 to PC5

WARNING:Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

63

MB90220 Series

2. Recommended Operating Condition

Parameter

Power supply voltage V

Analog power supply
voltage

Symbol

CC VCC

AV

CC AVCC 4.5 VCC + 0.3 V

AVRH AVRH AVRL AV
AVRL AVRL AV

Pin

name

(VSS = AVSS = 0.0 V)

Value

Unit Remarks

Min. Max.

4.5 5.5 V When operating

3.0 5.5 V

Retains the RAM state in
stop mode

Power supply voltage for
A/D converter

CC V

SS AVRH V

Reference voltage for A/D
converter

MB90224/P224A/W224A
MB90P224B/W224B

Clock frequency F

C —

10 16 MHz
10 12 MHz MB90223

Single-chip mode

–40 +105 °C

MB90223/224/P224B/
W224B

Operating temperature T

A*—

–40 +85 °C

Single-chip mode
MB90P224A/W224A

–40 +70 °C External bus mode

* :Excluding the temperature rise due to the heat produced.
WARNING:Recommended operating conditions are normal operating ranges for the semiconductor device. All the

device’s electrical characteristics are warranted when operated within these ranges.
Always use semico nductor devic es within the reco mmended opera ting conditio ns. Operation ou tside

these ranges may adversely affect reliability and could result in device failure.
No warranty is made with resp ect to uses, o perating cond itions, or comb inations no t represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.

64

MB90220 Series

3. DC Characteristics

Single-chip mode MB90223/224/ P22 4B /W2 24B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –4 0°C to +105°C)

MB90P224A/W224A : (V

External bus mode : (V

Parameter Symbol Pin name Condition

V

IH X0 — 0.7 VCC —VCC + 0.3 V CMOS level input

“H” level input
voltage

“L” level input
voltage

“H” level
output voltage

“L” level
output voltage

Input leackage

V

IHS

IHM MD0 to MD2 — VCC – 0.3 — VCC + 0.3 V

V
V

IL X0 — VSS – 0.3 — 0.3 VCC V CMOS lev el input

ILS

V
V

ILM

V

OH

V

OH1 X1

V

OL

V

OL1 X1

I

I

1

*

1

*
MD0 to MD2

2

*

3

*

1

*

—0.8 VCC —VCC + 0. 3 V Hysteresis input

—VSS – 0.3 — 0.2 VCC V Hysteresis input
—V

VCC = 4.5 V
I

OH = –4.0 mA

CC = 4.5 V

V
I

OH = –2.0 mA

VCC = 4.5 V
I

OL = 4.0 mA

CC = 4.5 V

V
I

OL = 2.0 mA

VCC = 5.5 V

0.2 V

CC < VI < 0.8 VCC

current

CC = 5.5 V

I

I2 X0

V

0.2 V

CC < VI2 < 0.8 VCC

RST — 22 50 110 kΩ

Pull-up resistor R

pulU

MD1 — 22 50 150 kΩ

Pull-down
resistor

R

pulD

MD0
MD2

— 22 50 150 kΩ

FC = 12 MHz —
F

C = 16 MHz —

ICC VCC

F

C = 16 MHz —

Power supply
voltage*

8

I

CCS VCC

I

CCH VCC ——510µA

fC = 16 MHz*

CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

Value

Unit Remarks

Min. Typ. Max.

SS – 0.3 — VSS + 0.3 V
CC – 0.5 — VCC V

V

CC – 2.5 — VCC V

V

0—0.4V

0—V

CC – 2.5 V

Hysteresis input
Except pins with

——±10 µA

pull-up/pull­down resistor
and RST

——±20 µA

4

*
MB90223/224
MB90P224A/
W224A

4

*
MB90223/224

4

*
MB90223/224

5

70*
70*

100 mA MB90223

5

100 mA MB90224

MB90P224A/

90*

5

125 mA

P224B
MB90W224A/
W224B

9

— — 60 mA At sleep mode

In stop mode

A = +25°C

T
At hardware
standby

(Continued)

pin

65

MB90220 Series

(Continued)

Parameter Symbol Pin name Condition

Unit Remarks

Min. Typ. Max.

Value

Analog power
supply voltage

Input
capacitance

I

A

fC = 16 MHz*

AVCC

AH ———

I
C

IN

7

*

9

—3 7mA

6

5*

µA At stop mode

——10—pF

*1: Hysteresis input pins

RST

, HST, P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P80 to P87,

P90 to P97, PA0 to PA7, PB0 to PB7, PC0 to PC5

*2: Ouput pins

P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77, P80 to P87, PA0 to
PA7, PB0 to PB7, PC0 to PC5

*3: Output pins

P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to
P87, P90 to P97, PA0 to PA7, PB0 to PB7, PC0 to PC5

*4: A list of availabilities of pull-up/pull-down resistors

Pin name MB90223/224 MB90P224A/W224A MB90P224B/W224B

RST

Availability of pull-up resistors is optionally
defined.

Pull-up resist or s
available

Unavailable

MD1 Pull-up resistors available Unavailable Unavai la ble
MD0, MD2 Pull-up resistors available Unavailable Unavailable

*5: V

CC = +5.0 V, VSS = 0.0 V, TA = +25°C, FC = 16 MHz

*6: The current value applies to the CPU stop mode with A/D converter inactive (V
*7: Other than V

CC, VSS, AVCC and AVSS

CC = AVCC = AVRH = +5.5 V).

*8: Measurement condition of power supply current; external clock pin and output pin are open.

Measurement condition of V

*9: F

C = 12 MHz for MB90223

CC; see the table above mentioned.

66

4. AC Characteristics

(1) Clock Timing Standards

MB90220 Series

Single-chip mode MB90223/224/P224B/W224B : (V

MB90P224A/W224A : (V

External bus mode : (V

Parameter

Clock frequency F

Clock cycl e time t

Input clock pulse width
Input clock rising/falling

times

C = 1/fC

t

Symbol

C X0, X1 —

C X0, X1 —

P

WH

PWL
t

cr

tcf

Pin

name

Condition

X0 — 0.4 tc —0.6 tc ns

X0 — — — 8 ns tcr + tcf

CC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
CC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

CC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

Value

Unit Remarks

Min. Typ. Max.

MB90224/

10 — 16 MHz

P224A/P224B
MB90W224A/
W224B

10 — 12 MHz MB90223

MB90224/

62.5 — 100 ns

P224A/P224B
MB90W224A/
W224B

83.4 — 100 ns MB90223
Equivalent to

60% duty ratio

• Clock Input Timings

• Clock Conditions

ceramic resonator is used

tc

0.7 VCC0.7 VCC

0.3 VCC

PWH PWL

tcf

When a crystal

or

C1

C1 = C2 = 10 pF
Select the optimum capacity value for the resonator

2

C

When an external clock is used

0.7 VCC

0.3 VCC

tcr

X0 X1X0 X1

Open

67

MB90220 Series

• Relationship between Clock Frequency and Supply Voltage

Single-chip mode

VCC

[V]

5.5

4.5

016

(MB90224/P224B/W224B)
(MB90223)
(MB90P224A/W224A)
External bus mode

Operation assurance range

10 12

: TA = –40°C to +105°C, Fc = 10 to 16 MHz
: TA = –40°C to +105°C, Fc = 10 to 12 MHz
: T

A = –40°C to +85°C, Fc = 10 to 16 MHz

: TA = –40°C to +70°C, Fc = 10 to 16 MHz
(Fc = 10 to 12 MHz, only for MB90223)

Fc
[MHz]

68

(2) Clock Output Timing

(External bus mode: V

Parameter

Symbol

Machine cycle time t

CYC CLK

Pin

name

Condition

Load
condition:
80 pF

MB90220 Series

CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

Value

Min. Typ. Max.

62.5 — 1600 ns

83.4 — 1600 ns MB90223

Unit Remarks

MB90224/
P224A/P224B
MB90W224A/
224B

CLK ↑ → CLK↓ t

t

CYC = n/FC, n gear ratio (1, 2, 4, 16)

CHCL CLK tCYC/2 – 20 — tCYC/2 ns

tCYC

tCHCL

CLK

(3) Reset and Hardware Standby Input Standards

Single-chip mode MB90223/224/P224B/W224B: (V

MB90P224A/W224A : (V

External bus mode : (V

Parameter

Symbol

Reset input time t

RSTL RST

Pin

name

Condition

—

Hardware standby input time t

HSTL HST 5 tCYC ——ns*

1/2 VCC

CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +105°C)
CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +85°C)

CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +70°C)

Value

Unit Remarks

Min. Typ. Max.

5 t

CYC ——ns

*: The machine cycle time (t

RST
HST

CYC) at hardware standby is set to 1/16 divided oscillation.

tRSTL, tHSTL

0.2 VCC

0.2 VCC

69

MB90220 Series

(4) Power on Supply Specifications (Power-on Reset)

Single-chip mode MB90223/224/P224B/W224B: (V

MB90P224A/W224A : (V

External bus mode : (V

Parameter

Power supply rising time t
Power supply cut-off time t

* :Before power supply rising, it is required to be V

Symbol Pin name Condition

R VCC ———30ms*

OFF VCC —1——ms

CC < 0.2 V.

Notes: • Power-on reset assumes the above values.

• Whether the power-on reset is requi red o r not, turn the power on according to these character i stics and
trigger the power-on reset.

• There are internal registers (STBYC, etc.) which is initialized only by the power-on reset in the device.

• Power-on Reset

tR

VCC

4.5 V

0.2 V

CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +105°C)
CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +85°C)

CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +70°C)

Value

Unit Remarks

Min. Typ. Max.

0.2 VCC

0.2 VCC

tOFF

Note: Note on changing power supply

Even if above characteristics are not insufficient, abrupt changes in power supply voltage may cause a power­on reset. Therefore, at the time of a momentar y chang es such as when power is tur ned on , ris e the power
smoothly as shown below.

• Changing Power Supply

Main power supply voltage

Subpower supply voltage

Vss

This rising edge should be
50 mV/ms or less

70

MB90220 Series

(5) Bus Read Timing

CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

(V

Parameter

Valid address → RD
RD

pulse width tRLRH RD tCYC – 25 — ns

↓ time tAVRL A23 to A00

Symbol Pin name Condition

t

CYC/2 – 20 — ns

Value

Min. Max.

Unit Remarks

RD

↓ → Valid data input tRLDV
↑ → Data hold time tRHDX 0—ns

RD
Valid address → Valid data input t

AVDV —

D15 to D00

Load
condition:

—t

CYC – 30 ns

3 tCYC/2 – 40

ns

80 pF

RD

↑ → Address valid time tRHAX A23 to A00 tCYC/2 – 20 — ns

Valid address → CLK ↑ time t

↓ → CLK ↓ time tRLCL RD, CLK tCYC/2 – 25 — ns

RD

CLK

RD

A23 to A00

AVCH

A23 to A00
CLK

tAVCH tRLCL

0.7 VCC

tAVRL tRLRH

0.3 VCC

0.7 VCC

0.3 VCC

0.3 VCC

t

CYC/2 – 25 — ns

0.7 VCC

tRHAX

0.7 VCC

0.3 VCC

D15 to D00

tAVDV

tRLDV

0.8 VCC

0.2 VCC

Read data

tRHDX

0.8 VCC

0.2 VCC

71

MB90220 Series

(6) Bus Write Timing

CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

(V

Parameter

Valid address → WR
WR

pulse width tWLWH WRL, WRH tCYC – 25 — ns

↓ time tAVWL A23 to A00

Symbol Pin name Condition

tCYC/2 – 20 — ns

Value

Min. Max.

Unit Remarks

Valid data output → WR

↑ → Data hold time tWHDX D15 to D00 tCYC/2 – 20 — ns

WR

↑ time tDVWH D15 to D00 tCYC – 40 — ns

Load
condition:
80 pF

WR

↑ → Address valid time tWHAX A23 to A00 tCYC/2 – 20 — ns
↓ → CLK ↓ time tWLCL

WR

CLK

WR
(WRL, WRH)

A23 to A00

WRL,
WRH

tAVWL

0.7 VCC

0.3 VCC

, CLK

tWLCL

tWLWH

0.3 VCC

t

CYC/2 – 25 — ns

0.3 VCC

0.7 VCC

tWHAX

tWHDXtDVWH

0.7 VCC

0.3 VCC

72

D15 to D00

Indeter-

minate

0.7 VCC

0.3 VCC

Read data

0.7 VCC

0.3 VCC

(7) Ready Input Timing

CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

(V

Parameter

Symbol

RDY setup time t
RDY hold time t

RYHS RDY
RYHH RDY 0 — ns

Pin

name

Condition

Load condition:
80 pF

Note: Use the auto-ready function if the RDY setup time is insufficient.

MB90220 Series

Value

Unit Remarks

Min. Max.

40 — ns

CLK

A23 to A00

RD/WR
(WRL, WRH)

RDY
No wait

One wait

tRYHS tRYHS

0.8 VCC

0.2 VCC

0.7 VCC 0.7 VCC

tRYHH tRYHH

0.8 VCC

0.8 VCC

(8) Hold Timing

CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

(V

Parameter

Pin floating → HAK
HAK

↑ time → pin valid time tHAHV HAK tCYC 2 tCYC ns

↓ time tXHAL HAK

Symbol

Pin

name

Condition

Load condition:
80 pF

Value

Min. Max.

30 t

0.8 VCC

Unit Remarks

CYC ns

Note: It takes at least one machine cycle for HAK

HRQ

HAK

Each pin

0.8 VCC

tXHAL

to vary after HRQ is fetched.

0.2 VCC

0.7 VCC

0.3 VCC

tHAHV

High impedance

73

MB90220 Series

(9) UART Timing

Single-chip mode MB90223/224/P224B/W224B: (V

MB90P224A/W224A : (V

External bus mode : (V

Parameter

Serial clock cycle time t
SCLK ↓ → SOUT delay time t
Valid SIN → SCLK ↑ t
SCLK ↑ → Valid SIN hold time t
Serial clock “H” pulse width t
Serial clock “L” pulse wid th t
SCLK ↓ → SOUT delay time t
Valid SIN → SCLK ↑ t
SCLK ↑ → valid SIN hold time t

Symbol

SCYC —
SLOV — –80 80 ns
IVSH — 100 — ns
SHIX —60—ns
SHSL —
SLSH —4 tCYC —ns
SLOV — — 150 ns
IVSH —60—ns
SHIX —60—ns

Pin

name

Load condition:
80 pF

Load condition:
80 pF

CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +105°C)
CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +85°C)
CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +70°C)

Condition

Notes: •These AC characteristics assume in CLK synchronization mode.

•“t

CYC” is the machine cycle (unit: ns).

Value

Unit Remarks

Min. Max.

8 t

CYC —ns

Internal
clock
operation
output pin

4 tCYC —ns

External
clock
operation
output pin

74

• Internal Shift Clock Mode

SCK

0.3 VCC 0.3 VCC

tSLOV

SOD

MB90220 Series

tSCYC

0.7 VCC

0.7 VCC

0.3 VCC

SID

• External Shift Clock Input Mode

tSLSH

SCK

0.2 VCC 0.2 VCC

tSLOV

SOD

SID

0.8 VCC

0.2 VCC

0.7 VCC

0.3 VCC

0.8 VCC

0.2 VCC

tIVSH

tIVSH

tSHIX

0.8 VCC

0.2 VCC

tSHSL

0.8 VCC 0.8 VCC

tSHIX

0.8 VCC

0.2 VCC

75

MB90220 Series

(10) Resourse Input Timing

Single-chip mode MB90223/224/P224B/W224B: (V

MB90P224A/W224A : (V

External bus mode : (V

Parameter Symbol Pin name Condition

TIN1 to TIN5

TIWH

Input pulse width

t
tTIWL

PWC0 to PWC3 2 t
ASR0 to ASR3 2 t
INT0 to INT7 3 t

Load
condition:
80 pF

TRG0 2 t
ATG

t

WIWL WI 4 tCYC ——ns

TIN1 to TIN5
PWC0 to PWC3
ASR0 to ASR3
INT0 to INT7
WI
TRG0
ATG

tTIWH

CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +105°C)
CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +85°C)

CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +70°C)

Value

Min. Typ. Max.

4 t

CYC ——ns

CYC ——ns

2 t

CYC ——ns
CYC ——ns
CYC ——ns
CYC ——ns

Unit Remarks

External event
count input mode

T rigger input/gate
input mode

2 tCYC ——ns

0.8 VCC0.8 VCC

0.2 VCC0.2 VCC

tTIWL, tWIWL

(11) Resourse Output Timing

Single-chip mode MB90223/224/P224B/W224B: (V

MB90P224A/W224A : (V

External bus mode : (V

Parameter Symbol Pin name Condition

CLK ↑ → T

OUT

transition time

TOT0 to TOT5

TO

t

PPG0 to PPG1
POT0 to POT3
DOT0 to DOT7

CLK

T

OUT

Load
condition:
80 pF

0.7 VCC

0.7 VCC

0.3 VCC

tTO

CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +105°C)
CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +85°C)

CC = +4.5 V to +5.5 V , VSS = 0.0 V, T A = –40°C to +70°C)

Value

Min. Typ. Max.

Unit Remarks

— — 30 ns

76

5. A/D Converter Electrical Characteristics

MB90220 Series

Single-chip modeMB90223/224/P224B/W224B

MB90P224A/W224A

External bus mode : (AV

Parameter Symbol

CC = VCC = +4.5 V to + 5.5 V, A VSS =V SS = 0.0 V, T A = –40°C to +1 05°C, +4.5 V ≤ AVRH – AVRL)

: (A V

CC = VCC = +4.5 V to +5.5 V, AVSS = VSS =0.0 V , T A = –40 °C to +85°C, +4.5 V ≤ AVRH – A VRL)

: (A V

CC = VCC = +4.5 V to +5.5 V, AVSS = VSS =0.0 V , T A = –40 °C to +70°C, +4.5 V ≤ AVRH – A VRL)

Pin

name

Condition

Min. Typ. Max.

Value

Unit Remarks

Resolution n — — — — 10 bit
Total erro r — — — — — ±3.0 LSB
Linearity error — — — — — ±2.0 LSB
Differential linearity error — — — — — ±1.5 LSB
Zero transition voltage V

0T

—

AVRL – 1.5 AVRL + 0.5 AVRL + 2.5

LSB

AN00 to

Full-scale transition
voltage

Conversion time*

1

V

FST —

TCONV —

AN15

t

CYC

AVRH – 3.5 AVRH – 1.5 AVRH + 0.5

6.125 — — µs

LSB

= 62.5 ns

Sampling period T
Analog port input current I

Analog input voltage V

SAMP —3.75——µs

AIN

AIN —AVRL—AVRHV

AN00 to
AN15

———±0.1 µA

98 machine
cycles

60 machine
cycles

Analog reference voltage —

AVRH — AVRL — AV

SS —AVRHV

Reference voltage supply
current

Variation between
channels

AVRL — AV

I

R

— — 200 500 µA

AVRH

I

RH ———

AN00 to

—

AN15

———4LSB

*1: These standards in this table are for MB90224/P224A/P224B/W224A/W224B.

MB90223: Minimum conversion time is 8.17 µs and minimum sampling time is 5 µs at t
*2: The current value applies to the CPU stop mode with the A/D converter inactive (V
Notes: (1) The error becomes larger as | AVRH – AVRL | becomes smaller.

(2) Use the output impedance of the external circuit for analog input under the following conditions:

External circuit output impedance < approx. 10 kΩ (Sampling time approx. 3.75 µs, t
(3) Precision values are standard values applicable to sleep mode.
(4) If V

CC/AVCC or VSS/AVSS is caused by a noise to drop to below the analog input vol gtage, the analog

input current is l ikely to incr ease. In su ch cases , a bypas s capacitor or the like should be p rovided in

the external circuit to suppress the noise.

CC V

2

5*

CC = A VCC = A VR H = +5.5 V).

µA

CYC = 83.4 ns.

CYC = 62.5 ns)

77

MB90220 Series

• Analog Input Circuit Mode

Analog input

C0

Comparator

RON1

RON1: Approx. 1.5 k
RON2: Approx. 1.5 k

C

0: Approx. 60 pF

Ω
Ω

RON2

1

C

C1: Approx. 4 pF

Note: The values shown here are reference values.

6. A/D Converter Glossary

Resolution: Analog changes that are identifiable with the A/D converter

When the number of bits is 10, analog voltage can be divided into 2

T otal error: Difference between actual and logical values. This error is caused by a zero transition

error, full-scale transition error, linearity error, differential linearity error, or by noise.

Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000”

↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1111” ↔
1110”) from actual conversion characteristics

Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the

theoretical value

Digital output

11 1111 1111
11 1111 1110
11 1111 1101

•

•

•

•

N + 1

N

N – 1

•

•

•

•

•

00 0000 0010
00 0000 0001
00 0000 0000

AVRL AVRH (V)

Theoretical value
Actual conversion value

V

0T

V

1T

V

2T

V

FST

– V

1 LSB

=

0T

, 1 LSB theoretical value

1022

Linearity error

Differential linearity error

Total error

V

(N – 1)T

V

NT

– (N × 1 LSB + V0T)

=

=

=

1 LSB

NT

– V

(N–1)T

V

1 LSB

V

NT

– {(N + 0.5) × 1 LSB theoretical value}

– 1

1 LSB theoretical value

Theoretical value (VNT)

Total error

Linearity error

N × 1LSB + V

V

NT

V

(N + 1)T

AVRH

– AVRL

=

1022

0T

V

N = 0 to 1022

NT (N = 0)

= V

V
V

NT (N = 1022)

0T

= V

N = 1 to 1022

N = 0 to 1022

FST

FST

10

= 1024.

“11 1111

78

■ EXAMPLE CHARACTERISTICS

(1) Power Supply Current

CC vs. TA example characteristics

I

CC (mA) ICCH (µA)

I

120
110

100

Fc = 16 MHz
External clock input
V

CC = 5.0 V

MB90220 Series

CCH vs. TA example characteristics

I

40

30

VCC = 5 V

90
80
70
60
50
40

–50 0 50 100 150

T

MB90P224A

MB90223

A (°C)

20

10

0

–10

–50 0 50 100 150

T

A (°C)

Note: These are not assured value of characteristics but example characteristics.

(2) Output Voltage

V

OH (V)

5.5

5.0

4.5

OH vs. IOH example characteristics

V

TA = +25°C
VCC = 5.0 V

OL (V)

V

2.0

1.5

1.0

OL vs. IOL example characteristics

V

TA = +25°C
VCC = 5.0 V

4.0

3.5

3.0
–15 –10 –5 0 5

I

OH (mA)

0.5

0.0

–0.5

–5 0 5 10 15 20 25

Note: These are not assured value of characteristics but example characteristics.

I

OL (mA)

79

MB90220 Series

(V)

(3) Pull-up/Pull-down Resistor

Pull-down resistor example characteristics Pull-up resistor example characteristics

pulD (kΩ)RpulU (kΩ)

R

100

90
80
70
60
50

VCC = 4.5 V

V

CC = 5.0 V

V

CC = 5.5 V

100

90
80
70
60
50

VCC = 4.5 V
V

CC = 5.0 V

V

CC = 5.5 V

40
30
20

–50 0 50 100 150

T

A (°C)

40
30
20

–50 0 50 100 150

T

Note: These are not assured value of characteristics but example characteristics.

(4) Analog Filter

Analog filter example characteristics

Input pulse width (ns)

80

70

60

50
40

30

Filtering enable

20

TA = +25°C

A (°C)

10

4.0 4.5 5.0 5.5 6.0
V

CC

Note: These are not assured value of characteristics but example characteristics.

80

MB90220 Series

■ INSTRUCTION SET (412 INSTRUCTIONS)

Table 1 Explanation of Items in Table of Instructions

Item Explanation

Mnemonic Upper-case letters and symbols: Represented as they appear in assembler

Lower-case letters: Replaced when described in assembler.

Numbers after lower-case letters: Indicate the bit width within the instruction.
# Indicates the number of bytes.
~ Indicates the number of cycles.

See Table 4 for details about meanings of letters in items.
B Indicates the correction value for calculating the number of actual cycles during

execution of instruction.

The number of actual cycles during execution of instruction is summed with the value in

the “cycles” column.

Operation Indicates operation of instruction.

LH Indicates special operations involving the bits 15 through 08 of the accumulator.

Z: Transfers “0”.
X: Extends before transferring.
—: Transfers nothing.

AH Indicates special operations involving the high-order 16 bits in the accumulator.

*: Transfers from AL to AH.
—: No transfer.
Z: Transfers 00
X: Transfers 00

I Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky
S
T

N

Z
V

C

RMW Indicates whether the instruction is a read-modify-write instruction (a single instruction

bit), N (negative), Z (zero), V (overflow), and C (carry).

*: Changes due to execution of instruction.
—: No change.
S: Set by execution of instruction.
R: Reset by execution of instruction.

that reads data from memory, etc., processes the data, and then writes the result to
memory.).

*: Instruction is a read-modify-write instruction
—: Instruction is not a read-modify-write instruction
Note: Cannot be used for addresses that have different meanings depending on

whether they are read or written.

H

to AH.

H

or FFH to AH by extending AL.

81

MB90220 Series

Table 2 Explanation of Symbols in Table of Instructions

Symbol Explanation

A 32-bit accumulator

The number of bits used varies according to the instruction.

Byte: Low order 8 bits of AL
Word: 16 bits of AL
Long: 32 bits of AL, AH

AH High-order 16 bits of A

AL Low-order 16 bits of A
SP Stack pointer (USP or SSP)
PC Program counter

SPCU Stack pointer upper limit register
SPCL Stack pointer lower limit register

PCB Program bank register
DTB Data bank register
ADB Additional data bank register
SSB System stack bank register
USB User stack bank register
SPB Current stack bank register (SSB or USB)
DPR Direct page register
brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2 DTB, ADB, SSB, USB, DPR, SPB

Ri R0, R1, R2, R3, R4, R5, R6, R7
RW i RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RW j RW0, RW1, RW2, RW3

RLi RL0, RL1, RL2, RL3

dir
addr16
addr24

addr24 0 to 15

addr24 16 to 23

io I/O area (000000

Compact direct addressin g
Direct addressing
Physical direct addressing
Bits 0 to 15 of addr24
Bits 16 to 23 of addr24

H

to 0000FFH)

(Continued)

82

(Continued)

Symbol Explanation

MB90220 Series

#imm4
#imm8

#imm16
#imm32

ext (imm8)

disp8

disp16

bp Bit offset value

vct4
vct8

( )b Bit address

rel

ear

eam

rlst Register list

4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data

8-bit displacement
16-bit displacement

Vector number (0 to 15)
Vector number (0 to 255)

Branch specification relative to PC
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)

83

MB90220 Series

Table 3 Effective Address Fields

Code Notation Address format

00
01
02
03
04
05
06
07

08
09
0A
0B

0C
0D

0E
0F

10
11
12
13
14
15
16
17

18
19
1A
1B

R0
R1
R2
R3
R4
R5
R6
R7

RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7

@RW0
@RW1
@RW2
@RW3

@RW0 +
@RW1 +
@RW2 +
@RW3 +

@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8

@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16

RL0

(RL0)

RL1

(RL1)

RL2

(RL2)

RL3

(RL3)

Register direct
“ea” corresponds to byte, word, and
long-word types, starting from the
left

Register indirect 0

Register indirect with post-increment 0

Register indirect with 8-bit
displacement

Register indirect with 16-bit
displacemen

Number of bytes in

address extemsion*

—

1

2

1C
1D

1E
1F

* : The number of bytes for address extension is indicated by the “+” symbol in the “#” (number of bytes) column in

the Table of Instructions.

84

@RW0 + RW7
@RW1 + RW7
@PC + dip16
addr16

Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct add ress

0
0
2
2

MB90220 Series

Table 4 Number of Execution Cycles for Each Form of Addressing

Code Operand

00 to 07 Ri

RWi
RLi

08 to 0B @RWj 1

0C to 0F @RWj + 4

10 to 17 @RWi + disp8 1
18 to 1B @RWj + disp16 1

1C
1D

1E
1F

* :“(a)” is used in the “ cycles” (numb er of cycles) c olumn and colu mn B (correctio n value) in th e Table of In structions.

Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles

Operand

Internal register + 0 + 0 + 0
Internal RAM even address + 0 + 0 + 0
Internal RAM odd address + 0 + 1 + 2

@RW0 + RW7
@RW1 + RW7
@PC + dip16
@addr16

Number of execution cycles for each from of addressing

Listed in Table of Instructions

(b)* (c)* (d)*

byte word long

(a)*

2
2
2
1

Even address not in internal RAM + 1 + 1 + 2
Odd address not in inter na l RAM + 1 + 3 + 6
External data bus (8 bits) + 1 + 3 + 6

* :“(b)”, “( c)”, an d “(d)” ar e used i n the “cyc les” (n umber of cycles ) column and col umn B (c orrec tion va lue) i n the

Table of Instructions.

85

MB90220 Series

Table 6 Transfer Instructions (Byte) [50 Instructions]

Mnemonic #

MOV A, dir
MOV A, addr16
MOV A, Ri
MOV A, ear
MOV A, eam
MOV A, io
MOV A, #imm8
MOV A, @A
MOV A, @RLi+disp8
MOV A, @SP+disp8
MOVP A, addr24
MOVP A, @A
MOVN A, #im m4

MOVX A, dir
MOVX A, addr16
MOVX A, Ri
MOVX A, ear
MOVX A, eam
MOVX A, io
MOVX A, #imm8
MOVX A, @A
MOVX A,@RWi+disp8
MOVX A, @RLi+disp8
MOVX A, @SP+disp8
MOVPX A, addr24
MOVPX A, @A

2
3
1
2

2+

2
2
2
3
3
5
2
1

2
3
2
2

2+

2
2
2
2
3
3
5
2

cycles

2
2
1
1

2+ (a)

2
2
2
6
3
3
2
1

2
2
1
1

2+ (a)

2
2
2
3
6
3
3
2

BOperation

byte (A) ← (dir)

(b)

byte (A) ← (addr16)

(b)

byte (A) ← (Ri)

0

byte (A) ← (ear)

0

byte (A) ← (eam)

(b)

byte (A) ← (io)

(b)

byte (A) ← imm8

0

byte (A) ← ((A))

(b)

byte (A) ← ((RLi))+disp8)

(b)

byte (A) ← ((SP)+disp8)

(b)

byte (A) ←(addr24)

(b)

byte (A) ← ((A))

(b)

byte (A) ← imm4

0

byte (A) ← (dir)

(b)

byte (A) ← (addr16)

(b)

byte (A) ← (Ri)

0

byte (A) ← (ear)

0

byte (A) ← (eam)

(b)

byte (A) ← (io)

(b)

byte (A) ← imm8

0

byte (A) ← ((A))

(b)

byte (A) ← ((RWi))+disp8)

(b)

byte (A) ← ((RLi))+disp8)

(b)

byte (A) ← ((SP)+disp8)

(b)

byte (A) ←(addr24)

(b)

byte (A) ← ((A))

(b)

LH AH

Z
Z
Z
Z
Z
Z
Z

–

Z
Z
Z
Z

–

Z
Z

X
X
X
X
X
X
X

–

X
X
X
X
X

–

X

ISTNZVC

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

R

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

RMW

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

MOV dir, A
MOV addr16, A
MOV Ri, A
MOV ear, A
MOV eam, A
MOV io, A
MOV @RLi+disp8, A
MOV @SP+disp8, A
MOVP addr24, A

MOV Ri, ear
MOV Ri, eam
MOVP @A, Ri
MOV ear, Ri
MOV eam, Ri
MOV Ri, #imm8
MOV io, #imm8
MOV dir, #imm8
MOV ear, #imm8
MOV eam, #imm8

MOV @AL, AH

2
3
1
2

2+

2
3
3
5

2

2+

2
2

2+

2
3
3
3

3+

2

2
2
1
2

2+ (a)

2
6
3
3

2

3+ (a)

3
3

3+ (a)

2
3
3
2

2+ (a)

2

byte (dir) ← (A)

(b)

byte (addr16) ← (A)

(b)

byte (Ri) ← (A)

0

byte (ear) ← (A)

0

byte (eam) ← (A)

(b)

byte (io) ← (A)

(b)

byte ((RLi)) +disp8) ← (A)

(b)

byte ((SP)+disp8) ← (A)

(b)

byte (addr24) ← (A)

(b)

byte (Ri) ← (ear)

0

byte (Ri) ← (eam)

(b)

byte ((A)) ← (Ri)

(b)

byte (ear) ← (Ri)

0

byte (eam) ← (Ri)

(b)

byte (Ri) ← imm8

0

byte (io) ← imm8

(b)

byte (dir) ← imm8

(b)

byte (ear) ← imm8

0

byte (eam) ← imm8

(b)

byte ((A)) ← (AH)

(b)

–

*

–

–

–

–

–

*

–

–

–

–

–

*

–

–

–

–

–

*

–

–

–

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*

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*

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*

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–

*

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*

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*

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*

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*

–

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*

–

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–

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–

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*

–

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–

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–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

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–

*

–

–

–

*

–

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–

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–

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–

–

–

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–

*

*

–

–

–

–

(Continued)

86

(Continued)

MB90220 Series

2

2+

2

2+

cycles

3

3+ (a)

4

5+ (a)

Mnemonic #

XCH A, ear
XCH A, eam
XCH Ri, ear
XCH Ri, eam

For an explanation of “(a)” and “(b)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressi ng, ”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

BOperation

byte (A) ↔ (ear)

0

2× (b)
2× (b)

byte (A) ↔ (eam)
byte (Ri) ↔ (ear)

0

byte (Ri) ↔ (eam)

LH AH

–

Z

–

Z

–

–

–

–

ISTNZVC

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

RMW

–
–
–
–

87

MB90220 Series

Table 7 Transfer Instructions (Word) [40 Instructions]

Mnemonic #

MOVW A, dir
MOVW A, addr16
MOVW A, SP
MOVW A, RWi
MOVW A, ear
MOVW A, eam
MOVW A, io
MOVW A, @A
MOVW A, #imm16
MOVW A, @RWi+disp8
MOVW A, @RLi+disp8
MOVW A, @SP+disp8
MOVPW A, addr24
MOVPW A, @A

MOVW dir, A
MOVW addr16, A
MOVW SP, # imm16
MOVW SP, A
MOVW RWi, A
MOVW ear, A
MOVW eam, A
MOVW io, A
MOVW @RWi+disp8, A
MOVW @RLi+disp8, A
MOVW @SP+disp8, A
MOVPW addr24, A
MOVPW @ A, RWi
MOVW RWi, ear
MOVW RWi, eam
MOVW ear, RWi
MOVW eam, RWi
MOVW RWi, #imm16
MOVW io, #imm16
MOVW ear, #imm16
MOVW eam, #imm16

2
3
1
1
2

2+

2
2
3
2
3
3
5
2

2
3
4
1
1
2

2+

2
2
3
3
5
2
2

2+

2

2+

3
4
4

4+

cycles

2
2
2
1
1

2+ (a)

2
2
2
3
6
3
3
2

2
2
2
2
1
2

2+ (a)

2
3
6
3
3
3
2

3+ (a)

3

3+ (a)

2
3
2

2+ (a)

BOperation

word (A) ← (dir)

(c)

word (A) ← (addr16)

(c)

word (A) ← (SP)

0

word (A) ← (RWi)

0

word (A) ← (ear)

0

word (A) ← (eam)

(c)

word (A) ← (io)

(c)

word (A) ← ((A))

(c)

word (A) ← imm16

0

word (A) ← ((RWi) +disp8)

(c)

word (A) ← ((RLi) +disp8)

(c)

word (A) ← ((SP) +disp8

(c)

word (A) ← (addr24)

(c)

word (A) ← ((A))

(c)

word (dir) ← (A)

(c)

word (addr16) ← (A)

(c)

word (SP) ← imm16

0

word (SP) ← (A)

0

word (RWi) ← (A)

0

word (ear) ← (A)

0

word (eam) ← (A)

(c)

word (io) ← (A)

(c)

word ((R Wi ) +di sp8) ← (A)

(c)

word ((RLi) +disp8) ← (A)

(c)

word ((SP) +disp8) ← (A)

(c)

word (addr24) ← (A)

(c)

word ((A)) ← (RWi)

(c)

word (RWi) ← (ear)

0

word (RWi) ← (eam)

(c)

word (ear) ← (RWi)

0

word (eam) ← (RWi)

(c)

word (RWi) ← imm16

0

word (io) ← imm16

(c)

word (ear) ← imm16

0

word (eam) ← imm16

(c)

LH AH

–
–
–
–
–
–
–

–

–
–
–
–
–
–

–

–

–

–

–

–

–

–

–

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–

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–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVC

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

–

–

–

*

*

–

–

–

*

*

–

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–

*

*

–

–

–

*

*

–

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–

*

*

–

–

–

*

*

–

–

–

*

*

–

–

–

*

*

–

–

–

*

*

–

–

–

*

*

–

–

–

*

*

–

–

–

*

*

–

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–

*

*

–

–

–

*

*

–

–

–

*

*

–

–

–

*

*

–

–

–

*

*

–

–

–

–

–

–

–

–

*

*

–

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–

–

–

–

–

–

RMW

–

–

–

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–

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–

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–

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–

–

–

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–

–

–

–

–

–

–

–

–

MOVW @AL, AH
XCHW A, ear

XCHW A, eam
XCHW RWi, ear
XCHW RWi, eam

Note: For an explanation of “(a)” and “(c)”, refer to Table 4, “Number of Execution Cycles for Each Form of

Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actu al
Cycles.”

88

2
2

2+

2

2+

3

3+ (a)

4

5+ (a)

0

2× (c)

0

2× (c)

word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)

word ((A)) ← (AH)

(c)

2

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

*

–

–

–

–

–
–

–
–
–

MB90220 Series

Table 8 Transfer Instructions (Long Word) [11 Instructions]

2

2+

5
3
5
2

2
3

5
2

2+

cycles

1

3+ (a)

3
4
4
3

5
4

4
2

3+ (a)

BOperation

long (A) ← (ear)

0

long (A) ← (eam)

(d)

long (A) ← imm32

0

long (A) ← ((SP) +disp8)

(d)

long (A) ← (addr24)

(d)

long (A) ← ((A))

(d)

long ((A)) ← (RLi)

(d)

long ((SP) + disp8) ← (A)

(d)

long (addr24) ← (A)

(d)

long (ear) ← (A)

0

long (eam) ← (A)

(d)

Mnemonic #

MOVL A, ear
MOVL A, eam
MOVL A, # imm32
MOVL A, @SP + disp8
MOVPL A, addr24
MOVPL A, @A

MOVPL @A, RLi
MOVL @SP + disp8, A

MOVPL addr24, A
MOVL ear, A
MOVL eam, A

For an explanation of “(a)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressi ng, ”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

LH AH

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVC

–

–

*

*

–

–

–

–

–

*

*

–

–

–

–

–

*

*

–

–

–

–

–

*

*

–

–

–

–

–

*

*

–

–

–

–

–

*

*

–

–

–

–

–

*

*

–

–

–

–

–

*

*

–

–

–

–

–

*

*

–

–

–

–

–

*

*

–

–

–

–

–

*

*

–

–

–

RMW

–
–
–
–
–
–

–
–

–
–
–

89

MB90220 Series

Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]

Mnemonic #

ADD A, #imm8
ADD A, dir
ADD A, ear
ADD A, eam
ADD ear, A
ADD eam, A
ADDC A
ADDC A, ear
ADDC A, eam
ADDDC A

SUB A, #imm8
SUB A, dir
SUB A, ear
SUB A, eam
SUB ear, A
SUB eam, A
SUBC A
SUBC A, ear
SUBC A, eam
SUBDC A

ADDW A
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam

2
2
2

2+

2

2+

1
2

2+

1
2

2
2

2+

2

2+

1
2

2+

1
1

2

2+

3
2

2+

2

2+

cycles

2
3
2

3+ (a)

2

3+ (a)

2
2

3+ (a)

3
2

3
2

3+ (a)

2

3+ (a)

2
2

3+ (a)

3
2

2

3+ (a)

2
2

3+ (a)

2

3+ (a)

B Operation

byte (A) ← (A) +imm8

0

byte (A) ← (A) +(dir)

(b)

byte (A) ← (A) +(ear)

0

byte (A) ← (A) +(eam)

(b)

byte (ear) ← (ear) + (A)

0

2× (b)

2× (b)

2× (c)

byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)

0

byte (A) ← (A) + (ear) + (C)

0

byte (A) ← (A) + (eam) + (C)

(b)

byte (A) ← (AH) + (AL) + (C) (Decimal)

0

byte (A) ← (A) –imm8

0

byte (A) ← (A) – (dir)

(b)

byte (A) ← (A) – (ear)

0

byte (A) ← (A) – (eam)

(b)

byte (ear) ← (ear) – (A)

0

byte (eam) ← (eam) – (A)
byte (A) ← (AH) – (AL) – (C)

0

byte (A) ← (A) – (ear) – (C)

0

byte (A) ← (A) – (eam) – (C)

(b)

byte (A) ← (AH) – (AL) – (C) (Decimal)

0

word (A) ← (AH) + (AL)

0

word (A) ← (A) +(ear)

0

word (A) ← (A) +(eam)

(c)

word (A) ← (A) +imm16

0

word (ear) ← (ear) + (A)

0

word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)

0

word (A) ← (A) + (eam) + (C)

(c)

LH AH

–

Z

–

Z

–

Z

–

Z

–

–

–

Z

–

Z

–

Z

–

Z

–

Z

–

Z

–

Z

–

Z

–

Z

–

–

–

–

–

Z

–

Z

–

Z

–

Z

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVC

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

RMW

–
–
–
–

*

*
–
–
–
–

–
–
–
–

*

*
–
–
–
–

–
–
–
–

*

*
–
–

word (A) ← (AH) – (AL)

2

SUBW A
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam

ADDL A, ear
ADDL A, eam
ADDL A, #imm32

SUBL A, ear
SUBL A, eam
SUBL A, #imm32

For an explanation of “(a)”, “(b) ”, “(c)” and “(d)”, refer to Tabl e 4, “Number of Executio n Cycles for Each For m of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

90

1
2

2+

3
2

2+

2

2+

2

2+

5
2

2+

5

2

3+ (a)

2
2

3+ (a)

2

3+ (a)

5

6+ (a)

4
5

6+ (a)

4

0
0

(c)

0
0

2× (c)

0

(c)

0

(d)

0
0

(d)

0

word (A) ← (A) – (ear)
word (A) ← (A) – (eam)
word (A) ← (A) –imm16
word (ear) ← (ear) – (A)
word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
word (A) ← (A) – (eam) – (C)

long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) +imm32

long (A) ← (A) – (ear)
long (A) ← (A) – (eam)
long (A) ← (A) –imm32

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–
–
–
–

*

*
–
–

–
–
–

–
–
–

MB90220 Series

Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]

Mnemonic #

INC ear
INC eam

DEC ear
DEC eam

INCW ear
INCW eam

DECW ear
DECW eam

INCL ear
INCL eam

DECL ear
DECL eam

2

2+

2

2+

2

2+

2

2+

2

2+

2

2+

cycles

2

3+ (a)

2

3+ (a)

2

3+ (a)

2

3+ (a)

4

5+ (a)

4

5+ (a)

B Operation

byte (ear) ← (ear) +1

0

2× (b)

2× (b)

2× (c)

2× (c)

2× (d)

2× (d)

byte (eam) ← (eam) +1
byte (ear) ← (ear) –1

0

byte (eam) ← (eam) –1
word (ear) ← (ear) +1

0

word (eam) ← (eam) +1
word (ear) ← (ear) –1

0

word (eam) ← (eam) –1
long (ear) ← (ear) +1

0

long (eam) ← (eam) +1
long (ear) ← (ear) –1

0

long (eam) ← (eam) –1

LH AH

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVC

–

*

*

*

–

–

–

–

*

*

*

–

–

–

–

*

*

*

–

–

–

–

*

*

*

–

–

–

–

*

*

*

–

–

–

–

*

*

*

–

–

–

–

*

*

*

–

–

–

–

*

*

*

–

–

–

–

*

*

*

–

–

–

–

*

*

*

–

–

–

–

*

*

*

–

–

–

–

*

*

*

–

–

–

RMW

*

*

*

*

*

*

*

*

*

*

*

*

For an explanation of “(a)”, “(b)”, “(c)” and “(d) ”, refer to Table 4, “Number of E xecution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]

Mnemonic #

CMP A
CMP A, ear
CMP A, eam
CMP A, #imm8

CMPW A
CMPW A, ear
CMPW A, eam
CMPW A, #imm16

CMPL A, ear
CMPL A, eam
CMPL A, #imm32

1
2

2+

2
1

2

2+

3
2

2+

5

cycles

2
2

2+ (a)

2
2

2

2+ (a)

2
3

4+ (a)

3

B Operation

byte (AH) – (AL)

0

byte (A) – (ear)

0

byte (A) – (eam)

(b)

byte (A) – imm8

0

word (AH) – (AL)

0

word (A) – (ear)

0

word (A) – (eam)

(c)

word (A) – imm16

0

long (A) – (ear)

0

long (A) – (eam)

(d)

long (A) – imm32

0

LH AH

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVC

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

RMW

–
–
–
–

–
–
–
–

–
–
–

For an explanation of “(a)”, “(b)”, “(c)” and “(d) ”, refer to Table 4, “Number of E xecution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

91

MB90220 Series

Table 12 Unsigned Multiplication and Division Instructions (Word/Long Word) [11 Instructions]

Mnemonic #

DIVU A

cycles

1

B Oper ation

1

*

word (AH) /byte (AL)

0

LH AH

–

–

ISTNZVC

*

*

–

–

–

–

–

RMW

–

Quotient → byte (AL) Remainder → byte (AH)

DIVU A, ear

0

2

*

word (A)/byte (ear)

–

–

–

–

–

–

*

–

–

*

2

Quotient → byte (A) Remainder → byte (ear)

DIVU A, eam

2+

3

*

word (A)/byte (eam)

*

–

–

–

–

–

–

*

–

–

*

6

Quotient → byte (A) Remainder → byte (eam)

DIVUW A, ear

4

0

2

*

long (A)/word (ear)

–

–

–

–

–

–

*

–

–

*

Quotient → word (A) Remainder → word (ear)

5

DIVUW A, eam

2+

7

long (A)/word (eam)

*

*

–

–

–

–

–

–

*

–

–

*

Quotient → word (A) Remainder → word (eam)

MULU A
MULU A, ear
MULU A, eam
MULUWA
MULUWA, ear
MULUW A, eam

2+

2+

8

1

*

9

2

*

10

*

11

1

*

12

2

*

13

*

byte (AH) × byte (AL) → word (A)

0
0

byte (A) × byte (ear) → word (A)

(b)

byte (A) × byte (eam) → w ord (A)

0

word (AH) × word (AL) → long (A)

0

word (A) × word (ear) → long (A)

(c)

word (A) × word (eam) → long (A)

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

For an explanation of “(b)” and “ (c), refer to Table 5, “C orrection Values for Number of Cycle Used to Ca lculate
Number of Actual Cycles.”

*1: 3 when dividing into zero, 6 when an overflow occurs, and 14 normally.
*2: 3 when dividing into zero, 5 when an overflow occurs, and 13 normally.
*3: 5 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 17 + (a) normally.
*4: 3 when dividing into zero, 5 when an overflow occurs, and 21 normally.
*5: 4 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 25 + (a) normally.
*6: (b) when dividing into zero or when an overflow occurs, and 2 × (b) normally.
*7: (c) when dividing into zero or when an overflow occurs, and 2 × (c) normally.
*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not 0.

*9: 3 when byte (ear) is zero, and 7 when byte (ear) is not 0.
*10: 4 + (a) when byte (eam) is zero, and 8 + (a) when byte (eam) is not 0.
*11: 3 when word (AH) is zero, and 11 when word (AH) is not 0.
*12: 3 when word (ear) is zero, and 11 when word (ear) is not 0.
*13: 4 + (a) when word (eam) is zero, and 12 + (a) when word (eam) is not 0.

92

MB90220 Series

Table 13 Signed Multiplication and Division Instructions (Word/Long Word) [11 Insturctions]

Mnemonic #

DIV A

2

cycles

1

*

B Operation

0

word (AH) /byte (AL)

LH AH

Z

–

ISTNZVC

–

–

–

–

–

*

*

RMW

–

Quotient → byte (AL) Remainder → byte (AH)

DIV A, ear

2

2

*

word (A)/byte (ear)

0

Z

–

–

–

–

–

–

*

*

–

Quotient → byte (A) Remainder → byte (ear)

DIV A, eam

2+

6

*

word (A)/byte (eam)

*

Z

–

–

–

–

–

–

*

*

–

3

Quotient → byte (A) Remainder → byte (eam)

DIVWA, ear
DIVWA, eam

2+

4

2

*

5

*

long (A)/word (ear)

0

Quotient → word (A) Remainder → word (ear)

7

*

long (A)/word (eam)

–

–

–

–

–

–

–

*

*

–

–

–

–

–

–

–

–

*

*

–

Quotient → w ord (A) Remainder → word (eam)

MUL A
MUL A, ear
MUL A, eam

MUL W A
MUL W A, ear
MUL W A, eam

2+

2+

8

2

*

9

2

*

10

*

11

2

*

12

2

*

13

*

byte (AH) × byte (AL) → word (A)

0

byte (A) × byte (ear) → word (A)

0

byte (A) × byte (eam) → word (A)

(b)

word (AH) × word (AL) → long (A)

0

word (A) × word (ear) → long (A)

0

word (A) × word (eam) → long (A)

(b)

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

For an explanation of “(b)” and “(c)”, refer to Table 5, “Cor rection Values for Number of Cycles Used to Calcul ate
Number of Actual Cycles.”

*1: 3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally.

*2: 3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally.

*3: 4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally.

*4: When the dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally.

When the dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally .

*5: When the dividend is po sitive: 4 + (a ) when di vidi ng int o zero, 11 + (a) or 30 + (a) when a n overflow occurs,

and 31 + (a) normally.
When the dividend is negati ve: 4 + (a) when d ividi ng into zero, 12 + (a) or 31 + (a) when an overflow occurs,

and 32 + (a) normally.
*6: (b) when dividing into zero or when an overflow occurs, and 2 × (b) normally.
*7: (c) when dividing into zero or when an overflow occurs, and 2 × (c) normally.
*8: 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.

*10: 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.
*11: 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12: 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13: 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative.

Note: W hi ch of the two va lu es giv en fo r the nu mbe r of exe cut io n cyc les ap plies when an ov er flow er ror occur s in

a DIV or DIVW instruction depends on whether the overflow was detected before or after the operation.

93

MB90220 Series

Table 14 Logical 1 Instructions (Byte, Word) [39 Instructions]

Mnemonic #

AND A, #imm8
AND A, ear
AND A, eam
AND ear, A
AND eam, A

OR A, #imm8
OR A, ear
OR A, eam
OR ear, A
OR eam, A

XOR A, #imm8
XOR A, ear
XOR A, eam
XOR ear, A
XOR eam, A
NOT A
NOT ear
NOT eam

ANDW A
ANDW A, #imm16
ANDW A, ear
ANDW A, eam
ANDW ear, A
ANDW eam, A

2
2

2+

2

2+

2
2

2+

2

2+

2
2

2+

2

2+

1
2

2+

1
3
2

2+

2

2+

cycles

2
2

3+ (a)

3

3+ (a)

2
2

3+ (a)

3

3+ (a)

2
2

3+ (a)

3

3+ (a)

2
2

3+ (a)

2
2
2

3+ (a)

3

3+ (a)

B Operation

byte (A) ← (A) and imm8

0

byte (A) ← (A) and (ear)

0

byte (A) ← (A) and (eam)

(b)

byte (ear) ← (ear) and (A)

0

2× (b)

2× (b)

2× (b)

2× (b)

2× (c)

byte (eam) ← (eam) and (A)
byte (A) ← (A) or imm8

0

byte (A) ← (A) or (ear)

0

byte (A) ← (A) or (eam)

(b)

byte (ear) ← (ear) or (A)

0

byte (eam) ← (eam) or (A)
byte (A) ← (A) xor imm8

0

byte (A) ← (A) xor (ear)

0

byte (A) ← (A) xor (eam)

(b)

byte (ear) ← (ear) xor (A)

0

byte (eam) ← (eam) xor (A)
byte (A) ← not (A)

0

byte (ear) ← not (ear)

0

byte (eam) ← not (eam)
word (A) ← (AH) and (A)

0

word (A) ← (A) and imm16

0

word (A) ← (A) and (ear)

0

word (A) ← (A) and (eam)

(c)

word (ear) ← (ear) and (A)

0

word (eam) ← (eam) and (A)

LH AH

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVC

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

RMW

–
–
–

*
*

–
–
–

*
*

–
–
–

*
*

–

*
*

–
–
–
–

*
*

word (A) ← (AH) or (A)

2

ORW A
ORW A, #imm16
ORW A, ear
ORW A, eam
ORW ear, A
ORW eam, A

XORW A
XORW A, #imm16
XORW A, ear
XORW A, eam
XORW ear, A
XORW eam, A
NOTW A
NOTW ear
NOTW eam

For an explanation of “(a)”, “(b)”, “(c)” and “(d) ”, refer to Table 4, “Number of E xecution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

1
3
2

2+

2

2+

1
3
2

2+

2

2+

1
2

2+

2
2

3+ (a)

3

3+ (a)

2
2
2

3+ (a)

3

3+ (a)

2
2

3+ (a)

0
0
0

(c)

0

2× (c)

0
0
0

(c)

0

2× (c)

0
0

2× (c)

word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)

word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
word (A) ← not (A)
word (ear) ← not (ear)
word (eam) ← not (eam)

–

–

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

–

*

–

R

*

*

–

–

–

–

–

*

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

–

*

–

R

*

*

–

–

–

–

–

*

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

–

*

–

R

*

*

–

–

–

–

–

*

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

94

MB90220 Series

Table 15 Logical 2 Instructions (Long Word) [6 Instructions]

Mnemonic #

ANDL A, ear
ANDL A, eam

ORL A, ear
ORL A, eam

XORL A, ear
XORL A, eam

2

2+

2

2+

2

2+

cycles

5

6+ (a)

5

6+ (a)

5

6+ (a)

B Operation

long (A) ← (A) and (ear)

0

long (A) ← (A) and (eam)

(d)

long (A) ← (A) or (ear)

0

long (A) ← (A) or (eam)

(d)

long (A) ← (A) xor (ear)

0

long (A) ← (A) xor (eam)

(d)

LH AH

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVC

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

–

R

*

*

–

–

–

RMW

–
–

–
–

–
–

For an explanation of “(a)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressi ng, ”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 16 Sign Inversion Instructions (Byte/Word) [6 Instructions]

Mnemonic #

NEG A
NEG ear

NEG eam
NEGW A

NEGW ear
NEGW eam

1
2

2+

1
2

2+

cycles

2
2

3+ (a)

2
2

3+ (a)

B Operation

0

byte (A) ← 0 – (A)

0

byte (ear) ← 0 – (ear)

2× (b)

2× (c)

byte (eam) ← 0 – (eam)

0

word (A) ← 0 – (A)

0

word (ear) ← 0 – (ear)
word (eam) ← 0 – (eam)

LH AH

X

–

–

–

–

–

–

–

–

–

–

–

ISTNZVC

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

RMW

–

*
*

–

*
*

For an explanation of “(a)”, “(b)” and “(c )” and refer to Table 4, “Number of E xecution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 17 Absolute Value Instructions (Byte/Word/Long Word) [3 Insturctions]

Mnemonic #

ABS A
ABSW A
ABSL A

cycles

2

2

2

2

4

2

B Operation

byte (A) ← absolute value (A)

0

word (A) ← absolute value (A)

0

long (A) ← absolute value (A)

0

LH AH

–

Z

–

–

–

–

ISTNZVC

–

*

*

*

–

–

–

–

*

*

*

–

–

–

–

*

*

*

–

–

–

RMW

–
–
–

Table 18 Normalize Instructions (Long Word) [1 Instruction]

Mnemonic #

cycles

B Operation

NRML A, R0 2 * 0 long (A) ← Shifts to the position at

LH AH

ISTNZVC

RMW

––––*–––– –
which “1” was set first
byte (R0) ← current sh ift count

* :5 when the contents of the accumulator are all zeroes, 5 + (R0) in all other cases.

95

MB90220 Series

Table 19 Shift Instructions (Byte/Word/Long Word) [27 Instructions]

Mnemonic #

RORC A
ROLC A

RORC ear
RORC eam
ROLC ear
ROLC eam

ASR A, R0
LSR A, R0
LSL A, R0

ASR A, #imm8
LSR A, #imm8
LSL A, #imm8

ASRW A

LSRW A/SHRW A
LSLW A/SHLW A

ASRW A, R0
LSRW A, R0
LSLW A, R0

ASRW A, #imm8
LSRW A, #imm8
LSLW A, #imm8

ASRL A, R0
LSRL A, R0
LSLL A, R0

2
2

2

2+

2

2+

2
2
2

3
3
3

1
1
1

2
2
2

3
3
3

2
2
2

cycles

2
2

2

3+ (a)

2

3+ (a)

1

*

1

*

1

*

3

*

3

*

3

*

2
2
2

1

*

1

*

1

*

3

*

3

*

3

*

2

*

2

*

2

*

B Operation

byte (A) ← Right rotation with carry

0

byte (A) ← Left rotation with carry

0

byte (ear) ← Right rotation with carry

0

byte (eam) ← Right rotation with carry

2× (b)

byte (ear) ← Left rotation with carry

0

byte (eam) ← Left rotation with carry

2× (b)

byte (A) ← Arithmetic right barrel shift (A, R0)

0

byte (A) ← Logical right barrel shift (A, R0)

0

byte (A) ← Logical left barrel shift (A, R 0)

0

byte (A) ← Arithmetic right barrel shift (A, imm8)

0

byte (A) ← Logical right barrel shift (A, imm8)

0

byte (A) ← Logical left barrel shift (A, imm8)

0

word (A) ← Arithmetic right shift (A, 1 bit )

0

word (A) ← Logical right shift (A, 1 bit)

0

word (A) ← Logical left shift (A, 1 bit)

0

word (A) ← Arithmetic right barrel shift (A, R0)

0

word (A) ← Logical right barrel shift (A, R0)

0

word (A) ← Logical left barrel shift (A, R0)

0

word (A) ← Arithmetic right barrel shift (A, imm8)

0

word (A) ← Logical right barrel shift (A, imm8)

0

word (A) ← Logical left barrel shift (A, imm8)

0

long (A) ← Arithmetic right shift (A, R0)

0

long (A) ← Logical right barrel shift (A, R0)

0

long (A) ← Logical left barrel shift (A, R0)

0

LH AH

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVC

*

–

*

*

–

–

–

*

–

*

*

–

–

–

*

–

*

*

–

–

–

*

–

*

*

–

–

–

*

–

*

*

–

–

–

*

–

*

*

–

–

–

*

–

*

*

*

–

–

*

–

*

*

*

–

–

*

–

*

*

–

–

–

*

–

*

*

*

–

–

*

–

*

*

*

–

–

*

–

*

*

–

–

–

*

–

*

*

*

–

–

*

–

*

R

*

–

–

*

–

*

*

–

–

–

*

–

*

*

*

–

–

*

–

*

*

*

–

–

*

–

*

*

–

–

–

*

–

*

*

*

–

–

*

–

*

*

*

–

–

*

–

*

*

–

–

–

*

–

*

*

*

–

–

*

–

*

*

*

–

–

*

–

*

*

–

–

–

RMW

–
–

*
*
*
*

–
–
–

–
–
–

–
–
–

–
–
–

–
–
–

–
–
–

ASRL A, #imm8
LSRL A, #imm 8
LSLL A, #imm8

4

3

*

4

3

*

4

3

*

long (A) ← Arithmetic right shift (A, imm8)

0

long (A) ← Logical right barrel shift (A, imm8)

0

long (A) ← Logical left barrel shift (A, imm8)

0

–
–
–

–

–

–

–

–

–

*

–

*

–

–

–

*

*

*

*

*

*

*

–

*

–

*

–

For an explanation of “(a)” and “(b)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressi ng, ”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

*1: 3 when R0 is 0, 3 + (R0) in all other cases.
*2: 3 when R0 is 0, 4 + (R0) in all other cases.
*3: 3 when imm8 is 0, 3 + (imm8) in all other cases.
*4: 3 when imm8 is 0, 4 + (imm8) in all other cases.

96

–
–
–

MB90220 Series

Table 20 Branch 1 Instructions [31 Instructions]

Mnemonic # cycles B Operation

BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BV rel
BNV rel
BT rel
BNT rel
BLT rel
BGE rel
BLE rel
BGT rel
BLS rel
BHI rel
BRA rel

JMP @A
JMP addr16
JMP @ear
JMP @eam
JMPP @ear *
JMPP @eam *
JMPP addr24

CALL @ear *
CALL @eam *
CALL addr16 *
CALLV #vct4 *
CALLP @ear *

CALLP @eam *
CALLP addr24 *

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

1
3
2

2+

3

2

3

2+

4

4

2

4

2+

5

3

5

1

6

2

6

2+

7

4

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

2
2
3

4+ (a)

3

4+ (a)

3
4

5+ (a)

5
5
7

8+ (a)

7

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0

(c)

0

(d)

0

(c)

2× (c)

(c)
2× (c)
2× (c)

2

*

2× (c)

Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
( (V) xor (N) ) or (Z) = 1
( (V) xor (N) ) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally

word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← (ear), (PCB) ← (ear +2)
word (PC) ← (eam), (PCB) ← (eam +2)
word (PC) ← ad24 0 to 15
(PCB) ← ad24 16 to 23
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← addr16
Vector call linstruction
word (PC) ← (ear) 0 to 15,
(PCB) ← (ear) 16 to 23
word (PC) ← (eam) 0 to 15,
(PCB) ← (eam) 16 to 23
word (PC) ← addr 0 to 15,
(PCB) ← addr 16 to 23

LH AH

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVC

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

RMW

–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

–
–
–
–
–
–
–

–
–
–
–
–

–
–

For an explanation of “(a)”, “(c)” and “(d)”, refer to T able 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

*1: 3 when branching, 2 when not branching.
*2: 3 × (c) + (b)
*3: Read (word) branch address.
*4: W: Save (word) to stack; R: Read (word) branch address.
*5: Save (word) to stack.
*6: W: Save (long word) to W stack; R: Read (long word) branch address.
*7: Save (long word) to stack.

97

MB90220 Series

Table 21 Branch 2 Instructions [20 Instructions]

Mnemonic #

CBNE A, #imm8, rel
CWBNE A, #imm16, rel

CBNE ear, #imm8, rel
CBNE eam, #imm8, rel
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel

DBNZ ear, rel
DBNZ eam, rel
DWBNZear, rel
DWBNZ eam, rel

INT #vct8
INT addr16
INTP addr24
INT9
RETI
RETIQ *

6

LINK #imm8

UNLINK

7

RET *
RETP *

8

3
4

4

4+

5

5+

3

3+

3

3+

2
3
4
1
1
2

2

1

1
1

cycles

1

*

1

*

1

*

3

*

1

*

3

*

2

*

4

*

2

*

4

*

14
12
13
14

9

11

6

5

4
5

B Operation

0

Branch when byte (A) ≠ imm8

0

Branch when byte (A) ≠ imm16

0

Branch when byte (ear) ≠ imm8

(b)

Branch when byte (eam) ≠ imm8

0

Branch when word (ear) ≠ imm16

(c)

Branch when word (eam) ≠ imm16

0

Branch when byte (ear ) =
(ear) – 1, and (ear) ≠ 0

2× (b)

Branch when byte (ear ) =
(eam) – 1, and (eam) ≠ 0
Branch when word (ear) =

0

(ear) – 1, and (ear) ≠ 0
Branch when word (eam) =

2× (c)

(eam) – 1, and (eam) ≠ 0
Software interrupt

8× (c)

Software interrupt

6× (c)

Software interrupt

6× (c)

Software interrupt

8× (c)

Return from interrupt

6× (c)

5

Return from interrupt

*

(c)

At constant entry, save old
frame pointer to stac k, se t ne w
frame pointer, and allocate
local pointer area

(c)

At constant entry, retrieve old
frame pointer from stack.

(c)

Return from subroutine

(d)

Return from subroutine

LH AH

–
–

–
–
–
–

–
–
–
–

–
–
–
–
–
–

–

–

–
–

ISTNZVC

*

*

–

–

–

–

*

*

–

–

–

–

*

*

–

–

–

–

*

*

–

–

–

–

*

*

–

–

–

–

*

*

–

–

–

–

*

*

–

–

–

–

*

*

–

–

–

–

*

*

–

–

–

–

*

*

–

–

–

–

–

–

–

S

R

–

–

–

–

S

R

–

–

–

–

S

R

–

–

–

–

S

R

–

*

*

*

*

*

–

*

*

*

*

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

RMW

–

*

*

–

*

*

–

*

*

–

*

*

–

*

*

–

*

*

–

–

*

*

–

*

–

–

*

*

–

*

–

–

–

–

–

–

–

–

–

–

–

–

–

*

*

–

*

*

–

–

–

–

–

–

–

–

–

–

–

–

For an explanation of “(b)”, “(c)” and “(d)”, refer to T able 5, “Correction V alues for Number of Cycles Used to Calculate
Number of Actual Cycles.”

*1: 4 when branching, 3 when not branching
*2: 5 when branching, 4 when not branching
*3: 5 + (a) when branching, 4 + (a) when not branching
*4: 6 + (a) when branching, 5 + (a) when not branching
*5: 3 × (b) + 2 × (c) when an interrupt request is generated, 6 × (c) when returning from the interrupt.
*6: High-speed interrupt return instruction. When an interrupt request is detected during this instruction, the

instruction branches to the interrupt vector without performing stack operations when the interrupt is generated.
*7: Return from stack (word)
*8: Return from stack (long word)

98

MB90220 Series

Table 22 Other Control Instructions (Byte/Word/Long Word) [36 Instructions]

Mnemonic #

PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst

POPW A
POPW AH
POPW PS
POPW rlst

JCTX @A
AND CCR, #imm8

OR CCR, #imm8
MOV RP, #imm8

MOV ILM, #imm8
MOVEA RWi, ear

MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam

ADDSP #imm8
ADDSP #imm16

1
1
1
2

1
1
1
2

1
2

2
2

2
2

2+

2

2+

2
3

cycles

3
3
3

3

*

3
3
3

2

*

9
3

3
2

2
3

2+ (a)

2

1+ (a)

3
3

B Operation

word (SP) ← (SP) –2, ((SP)) ← (A)

(c)

word (SP) ← (SP) –2, ((SP)) ← (AH)

(c)

word (SP) ← (SP) –2, ((SP)) ← (PS)

(c)

4

(SP) ← (SP) –2n, ((SP)) ← (rlst)

*

word (A) ← ((SP)), (SP) ← (SP) +2

(c)

word (AH) ← ((SP)), (SP) ← (SP) +2

(c)

word (PS) ← ((SP)), (SP) ← (SP) +2

(c)

4

(rlst) ← ((SP)) , (SP) ← (SP)

*

Context switch instruction

6× (c)

byte (CCR) ← (CCR) and imm8

0

byte (CCR) ← (CCR) or imm8

0

byte (RP) ←imm8

0

byte (ILM) ←imm8

0

word (RWi) ←ear

0

word (RW i) ←eam

0

word(A) ←ear

0

word (A) ←eam

0

word (SP) ← ext (imm8)

0

word (SP) ← imm16

0

LH AH

–

–

–

–

–

–

–

–

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

–

*

–

–

–

–

–

ISTNZVC

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

*

*

*

*

*

*

–

–

–

–

–

–

–

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

RMW

–
–
–
–

–
–
–
–

–
–

–
–

–
–

–
–
–

–
–

MOV A, brgl
MOV brg2, A
MOV brg2, #imm8

NOP
ADB
DTB
PCB
SPB
NCC
CMR

1

2

*

2

1

3

2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

byte (A) ← (brgl)

0

byte (brg2) ← (A)

0

byte (brg2) ← imm8

0

No operation

0

Prefix code for AD space access

0

Prefix code for DT space access

0

Prefix code for PC space access

0

Prefix code for SP space access

0

Prefix code for no flag change

0

Prefix code for the common

0

*

Z

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

–

*

–

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

register bank

MOVW SPCU , #imm16
MOVW SPCL, #imm16
SETSPC
CLRSPC

BTSCN A
BTSCNS A
BTSCND A

4

2

4

2

2

2

2

2

5

2

*

6

2

*

7

2

*

word (SPCU) ← (imm16)

0

word (SPCL) ← (imm16)

0

Stack check ooperation enable

0

Stack check ooperation disable

0

byte (A)← position of “1” bit in word (A)

0

byte (A)← position of “1” bit in word (A)

0

byte (A)← position of “1” bit in word (A)

0

–
–
–
–

Z

2

×

Z
Z

4

×

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

For an explanation of “(a)” and “(c)”, refer to Tables 4 and 5.
*1: PCB, ADB, SSB, USB, and SPB: 1 cycle *4: Pop count × (c), or push count × (c)

DTB: 2 cycles *5: 3 when AL is 0, 5 when AL is not 0.

DPR: 3 cycles *6: 4 when AL is 0, 6 when AL is not 0.
*2: 3 + 4 × (pop count) *7: 5 when AL is 0, 7 when AL is not 0.
*3: 3 + 4 × (push count)

–

–

–

*

–

–

–

*

–

–

–

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

–

*

–

*

–
–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

99

MB90220 Series

Table 23 Bit Manipulation Instructions [21 Instructions]

Mnemonic #

MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp

MOVB dir:bp, A
MOVB addr16:bp , A
MOVB io:bp, A

SETB dir:bp
SETB addr16:b p
SETB io:bp

CLRB dir:bp
CLRB addr16:bp
CLRB io:bp

BBC dir:bp, rel
BBC addr16:bp, rel
BBC io:bp, rel

BBS dir:bp, rel
BBS addr16:bp, rel
BBS io:bp, rel

SBBS addr16:bp, rel

cycles

3

3

3

4

3

3

4

3

4

4

4

3

4

3

4

4

4

3

4

3

4

4

4

3
4

*

5

*

4

*

4

*

5

*

4

*

5

*

B Operation

(b)

byte (A) ← (dir:bp) b

(b)

byte (A) ← (addr16:bp) b

(b)

byte (A) ← (io:bp) b

2× (b)
2× (b)
2× (b)

2× (b)
2× (b)
2× (b)

2× (b)
2× (b)
2× (b)

1
1
1

1
1
1

2

2× (b)

bit (dir:bp) b ← (A)
bit (addr16:bp) b ← (A)
bit (io:bp) b ← (A)

bit (dir:bp) b ← 1
bit (addr16:bp) b ← 1
bit (io:bp) b ← 1

bit (dir:bp) b ← 0
bit (addr16:bp) b ← 0
bit (io:bp) b ← 0

(b)

Branch when (dir:bp) b = 0

(b)

Branch when (addr16:bp) b = 0

(b)

Branch when (io:bp) b = 0

(b)

Branch when (dir:bp) b = 1

(b)

Branch when (addr16:bp) b = 1

(b)

Branch when (io:bp) b = 1

Branch when (add r16:bp) b = 1, bit = 1

LH AH

Z
Z
Z

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVC

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

*

–

–

–

*

*

–

–

–

*

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

–

–

–

–

*

–

–

–

–

*

–

–

–

–

*

–

–

–

–

*

–

–

–

–

*

–

–

–

–

*

–

–

–

–

RMW

–

–

–

–

–

–

–

–

–

*

–

–

*

–

–

*

–

–

*

–

–

*

–

–

*

–

–

*

–

–

*

–

–

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

–

–
WBTS io:bp
WBTC io:bp

3
3

3

*

3

*

4

Wait until (io:bp) b = 1

*

4

Wait until (io:bp) b = 0

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

For an explanation of “(b)”, refer to Table 5, “Correction V alues for Number of Cycles Used to Calculate Number of
Actual Cycles.”

*1: 5 when branching, 4 when not branching
*2: 7 when condition is satisfied, 6 when not satisfied
*3: Undefined count
*4: Until condition is satisfied

100