FUJITSU MB90220 DATA SHEET

查询MB90223供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13502-5E

16-bit Proprietary Microcontroller

CMOS

F2MC-16F MB90220 Series

MB90223/224/P224A/W224A
MB90P224B/W224B/V220

■ OUTLINE

The MB90220 ser ies of g eneral-pur pose hi gh-per formance 16 -bit mi crocon trollers ha s bee n develo ped prim arily
for applications that demand high-speed real-time processing and is suited for industrial applications, office
automation equipme nt, process control , and other appli cations. The F
Family with improved high- level language support functions and task switching functions, as well as addit ional
addressing modes.

2

MC-16F CPU is based on the F2MC*-16

On-chip perip heral resour ces in clude a 4-c hanne l PWC timer, a 4-channel ICU (In put Capt ure Un it), a 1-chann el
24-bit timer counter, an 8-channel OCU (Output Compare Unit), a 6-channel 16-bit reload timer, a 2-channel
16-bit PPG timer, a 10-bit A/D co nverter with 16 inputs, and a 4-ch annel serial po rt with a UART function (one
channel includes the CTS function).

The MB90P224B, MB90W224B, MB90224 is under development.

2

*: F

MC stands for FUJITSU Flexible Microcontroller.

■ PACKAGE

120-pin Plastic QFP

120-pin Ceramic QFP

(FPT-120P-M03)

(FPT-120C-C02)

MB90220 Series

■ FEATURES

F2MC-16F CPU

• Minimum execution time: 62.5 ns/16 MHz oscillation (using a duty control system)

• Instruction sets optimized for controllers

2

Upward object-compatible with the F
Various data types (bit, byte, word, and long-word)
Instruction cycle improved to speed up operation
Extended addressing modes: 25 types
High coding efficiency
Access method (bank access with linear pointer)
Enhanced multiplication and division instructions (with signed instructions added)
Higher-precision operation using a 32-bit accumulator

• Extended intelligent I/O service (automatic transfer function independent of instructions)
Access area expanded to 64 Kbytes

• Enhanced instruction set applicable to high-level language (C) and multitasking
System stack pointer
Enhanced pointer-indirect instructions
Barrel shift instruction
Stack check function

• Increased execution speed: 8-byte instruction queue

• Powerful interrupt functions: 8 levels and 28 sources

MC-16(H)

Peripheral resources

• Mask ROM : 64 Kbytes (MB90223)

96 Kbytes (MB90224)

EPROM : 96 Kbytes (MB90W224A/W224B)

• One-time PROM : 96 Kbytes (MB90P224A/P224B)

• RAM: 3 Kbytes (MB90223)

4.5 Kbytes (MB90224/MB90W 224 A/ P22 4A /W2 24B /P 224B )
5 Kbytes (MB90V220)

• General-purpose ports: max. 102 channels

• ICU (Input Capture Unit): 4 channels

• 24-bit timer counter: 1 channel

• OCU (Output Compare Unit): 8 channels

• PWC timer with time measurement function: 4 channels

• 10-bit A/D converter: 16 channels

• UART: 4 channels (one channel includes CTS function)

• 16-bit reload timer
Toggled output, external clock, and gate functions: 6 channels

• 16-bit PPG timer: 2 channels

• DTP/External-interrupt inputs: 8 channels (of which five have edge detection function only)

• Write-inhibit RAM: 0.5 Kbytes (1 Kbyte for MB90V220)

• Timebase counter: 18 bits

• Clock gear function

• Low-power consumptio n mode
Sleep mode
Stop mode
Hardware standby mode

2

Product description

• MB90223/224 are mask ROM product.

• MB90P224A/P224B are one-time PROM products.

• MB90W224A/W224B are EPROM products. ES only.

• Operating temperature of MB90P224A/W224A is –40°C to +85°C.
(However, the AC characteristics is assured in –40°C to +70°C)

• Operation clock cycle of MB90223 is 10 MHz to 12 MHz.

• MB90V220 is a evaluation device for the program development. ES only.

■ PRODUCT LINEUP

MB90220 Series

Part number

Item

Classification Mask ROM

ROM size 64 Kbytes 96 Kbytes 96 Kbytes 96 Kbytes None
RAM size 3 Kbytes 4.5 Kbytes 4.5 Kbytes 4.5 Kbytes 5 Kbytes
CPU functions The number of instructions: 412

Ports I/O ports (N-ch open-drain): 16

ICU

(Input Capture Unit)

24-bit timer
counter

OCU

(Output Compare Unit)

PWC timer Number of channels: 4

MB90223 MB90224

Mask ROM

product

Instruction bit length: 8 or 16 bits
Instruction length: 1 to 7 bytes
Data bit length: 1, 4, 8, 16, or 32 bits
Minimum execution time: 62.5 ns/16 MHz
Interrupt processing time: 1.0 µs/16 MHz (min.)

I/O ports (CMOS): 86
Total: 102

Pin change source (match signal causes register value transfer/general-purpose port)

16-bit reload timer operation (operation clock cycle: 0.25 µs to 1.31 ms)

16-bit pulse-width count operation (Allowing continuous/one-shot measurement, H/L width

measurement, inter-edge measurement, and divided-frequency measurement)

product

Rising edge/falling edge/both edges selectable

Overflow interrupt, intermediate bit interrupt

MB90P224A
MB90P224B

One-time

PROM product

Number of channels: 4

Number of channels: 1

Number of channels: 8

MB90W224A
MB90W224B

EPROM

product

MB90V220

Evaluation

device

10-bit
A/D converter

Single conversion mode (conversion of each channel)

Scan conversion mode (continuous conversion for up to 16 consecutive channels)

Continuous conversion mode (repeated conversion of specified channel)

Stop conversion mode (conversion every fixed cycle)

UART Number of channels: 4 (1 channel with CTS function)

Clock-synchronous transfer mode

(full-duplex double buffering, 7 to 9-bit data length, 2400 to 62500 bps)
(full-duplex double buffering, 7 to 9-bit data length, 2400 to 62500 bps)

16-bit reload
timer

16-bit reload timer operation (operation clock cycle: 0.25 µs to 1.05 s)

Resolution: 10 bits

Number of inputs: 16

Asynchronous transfer mode

Number of channels: 6

(Continued)

3

MB90220 Series

(Continued)

Part number

Item

16-bit PPG timer Number of channels: 2

DTP/External
interrupts

Write-inhibited
RAM

Standby mode stop mode (activated by software or hardware) and sleep mode
Gear function Machine clock operation frequency switching: 16 MHz, 8 MHz, 4 MHz, 1 MHz (at

Package FPT-120P-M03 FPT-120C-C02 PGA-256C-A02

Note: MB90V220 is a evaluation device, therefore, the electrical characteristics are not assured.

MB90223 MB90224

16-bit PPG operation (operation clock cycle: 0.25 µs to 6 s)

Number of inputs: 8 (of which five have edge detection function only)

External interrupt mode (allowing interrupts to activate at four different request levels)

Simple DMA transfer mode (allowing ext ended I

RAM size: 512 bytes (1 Kbyte for MB90V220)

RAM write-protectable with WI

16-MHz oscillation)

■ DIFFERENCES BETWEEN MB90223/224 (MASK ROM PRODUCT) AND MB90P224A/

W224A/P224B/W224B

MB90P224A
MB90P224B

2

OS to activate at two d ifferent r equest le vels)

MB90W224A
MB90W224B

pin

MB90V220

Part number

Item

ROM Mask ROM

Pin functions: pin 87 MD2 pin MD2/V

MB90223 MB90224

Mask ROM

64 Kbytes

96 Kbytes

MB90P224A
MB90P224B

OTPROM
96 Kbytes

MB90W224A
MB90W224B

EPROM

96 Kbytes

PP pin

4

■ PIN ASSIGNMENT

90 RST

89 MD0

88 MD1

87 MD2

86 HST

85 P57/WI

84 P56/RD

83 P55/WRL

82 P54/WRH

(Top view)

81 P53/HRQ

80 P52/HAK

79 P51/RDY

78 P50/CLK

77 PC5/TRG0

76 PC4/CTS0

75 PC3/SCK3

74 PC2/SID3

73 PC1/SOD3

72 PC0/SCK2

71 PB7/SID2

70 PB6/SOD2

69 PB5/SCK1

68 PB4/SID1

67 PB3/SOD1

66 PB2/SCK0

65 PB1/SID0

MB90220 Series

SS

62 PA7/INT2/ATG

61 PA6/INT1

64 PB0/SOD0

63 V

SS 91

V

X0 92
X1 93

V

CC 94

P00/D00 95
P01/D01 96
P02/D02 97
P03/D03 98
P04/D04 99
P05/D05 100
P06/D06 101
P07/D07 102
P10/D08 103
P11/D09 104
P12/D10 105
P13/D11 106
P14/D12 107
P15/D13 108
P16/D14 109
P17/D15 110
P20/A00 111
P21/A01 112
P22/A02 113
P23/A03 114
P24/A04 115
P25/A05 116
P26/A06 117
P27/A07 118

V

SS 119

P30/A08 120

60 PA5/INT0
59 PA4/PWC3/POT3/ASR3
58 PA3/PWC2/POT2/ASR2
57 PA2/PWC1/POT1/ASR1
56 PA1/PWC0/POT0
55 PA0/ASR0
54 V

CC

53 P67/AN07
52 P66/AN06
51 P65/AN05
50 P64/AN04
49 P63/AN03
48 P62/AN02
47 P61/AN01
46 P60/AN00
45 AV

SS

44 AVRL
43 AVRH
42 AV

CC

41 P97/AN15
40 P96/AN14
39 P95/AN13
38 P94/AN12
37 P93/AN11
36 P92/AN10
35 P91/AN09
34 P90/AN08
33 V

SS

32 P87/PPG1
31 P86/PPG0

P31/A09 1

P32/A10 2

P33/A11 3

P34/A12 4

P35/A13 5

CC 8

V

P40/A16 9

P36/A14 6

P37/A15 7

P41/A17 10

P42/A18 11

P43/A19/TIN1/INT3 12

P44/A20/TIN2/INT4 13

P70/DOT0 17

P71/DOT1 18

P45/A21/TIN3/INT5 14

P46/A22/TIN4/INT6 15

P47/A23/TIN5/INT7 16

(FPT-120P-M03)
(FPT-120C-C02)

P72/DOT2 19

P73/DOT3 20

P74/DOT4 21

P75/DOT5 22

P76/DOT6 23

P77/DOT7 24

P80/TOT0 25

P81/TOT1 26

P82/TOT2 27

P83/TOT3 28

P84/TOT4 29

P85/TOT5 30

5

MB90220 Series

■ PIN DESCRIPTION

Pin no.

QFP*

92,

93

89 to 87 MD0 to MD2 D Operation mode specification input pins

90 RST
86 HST

95 to 102 P00 to P07 C General-purpose I/O ports

103 to 110 P10 to P17 C General-purpose I/O ports

111 to 118 P20 to P27 C General-purpose I/O ports

Pin name

X0,
X1

D00 to D07 Output pins for low-order 8 bits of the external address bus.

D08 to D15 I/O pins for higher-order 8 bits of the external data bus

Circuit

type

A Crystal oscillation pins (16 MHz)

Connect directly to V
G External reset request input
E Hardware standby input pin

This function is valid only in single-chip mode.

This function is valid only in modes where the external bus is

enabled.

This function is valid only in single-chip mode or when the external bus

is enabled and the 8-bit data bus specification has been made.

This function is valid only when the external bus is enabled and the

16-bit bus specification has been made.

This function is valid only in single-chip mode.

CC or VSS.

Function

A00 to A07 Output pins for lower-order 8 bits of the external address bus

This function is valid only in modes where the external bus is

enabled.

120,

1 to 7

9 to 11 P40 to P42 C General-purpose I/O ports

12 to 16 P43 to P47 C General-purpose I/O ports

P30,
P31 to P37

A08,
A09 to A15

A16 to A18 Output pins for higher-order 8 bits of the external address bus

A19 to A23 Output pins for higher-order 8 bits of the external address bus

TIN1 to TIN5 16-bit reload timer input pins

C General-purpose I/O ports

This function is valid either in single-chip mode or when the address

mid-order control register specification is “port”.

Output pins for mid-order 8 bits of the external address bus

This function is valid in modes where the external bus is enabled and

the address mid-order control register specification is “address”.

This function is valid either in single-chip mode or when the address

high-order control register specification is “port”.

This function is valid in modes where the external bus is enabled and

the address high-order control register specification is “address”.

This function is valid when either single-chip mode is enabled or the

address higher-order control register specification is “port”.

This function is valid in modes where the external bus is enabled and

the address higher-order control register specification is “address”.

This function is valid when the timer input specification is “enabled”.

The data on the pins is read as timer input (TIN1 to TIN5).

* :FPT-120P-M03, FPT-120C-C02

6

(Continued)

Pin no.

Pin name

QFP*

12 to 16 INT3 to INT7 C External interrupt request input pins

78 P50 C General-purpose I/O port

CLK CLK output pin

79 P51 C General-purpose I/O port

RDY Ready input pin

Circuit

type

Function

When external interrupts are enabled, these inputs may be used

suddenly at any time; therefore, it is necessary to stop output by other

functions on these pins, except when using them for output

deliberately.

This function is valid in single-chip mode and when the CLK output

specification is disabled.

This function is valid in modes where the external bus is enabled and

the CLK output specification is enabled.

This function is valid in single-chip mode or when the ready function

is disabled.

This function is valid in modes where the external bus is enabled and

the ready function is enabled.

MB90220 Series

80 P52 C General-purpose I/O port

This function is valid in single-chip mode or when the hold function is

disabled.

HAK

81 P53 C General-purpose I/O port

HRQ Hold request input pin

82 P54 C General-purpose I/O port

WRH

83 P55 C General-purpose I/O port

WRL

Hold acknowledge output pin

This function is valid in modes where the external bus is enabled and

the hold function is enabled.

This function is valid in single-chip mode or external bus mode and

when the hold function is disabled.

This function is valid in modes where the external bus is enabled and

the hold function is enabled.

During this operation, the input may be used suddenly at any time;

therefore, it is necessary to stop output by other fuctions on this pin,

except when using it for output deliberately.

This function is valid in single-chip mode, when the external bus is in

8-bit mode, or when WRH

Write strobe output pin for the high-order 8 bits of the data bus

This function is valid in modes where the external bus is enabled, the

external bus is in 16-bit mode, and WRH

This function is valid in single-chip mode or when WRL

disabled.

Write strobe output pin for the low-order 8 bits of the data bus

This function is valid in modes where the external bus is enabled and

WRL

pin output is enabled.

pin output is disabled.

pin output is enabled.

pin output is

* :FPT-120P-M03, FPT-120C-C02

(Continued)

7

MB90220 Series

Pin no.

Pin name

QFP*

84 P56 C General-purpose I/O port

RD

85 P57 B General-purpose I/O port

WI

46 to 53 P60 to P67 F Open-drain I/O ports

AN00 to AN07 10-bit A/D converter analog input pins

17 to 24 P70 to P77 C General-purpose I/O ports

DOT0 to DOT7 This function is valid when OCU (output compare unit) output is

Circuit

type

This function is valid in single-chip mode. This function is valid in

modes where the external bus is valid.

Read strobe output pin for the data bus

This function is valid in modes where the external bus is enabled.

This function is always valid.

When these pins are open in input mode, through current may leak in

stop mode/reset mode, be sure to fix these pins to V

use these pins in input mode.

RAM write disable request input

During this operation, the input may be used suddenly at any time;

therefore, it is necessary to stop output by other fuctions on this pin,

except when using it for output deliberately.

This function is valid when the analog input enable register

specification is “port”.

This function is valid when the analog input enable register

specification is “analog input”.

This function is valid when the output specification for DOT0 to DOT7

is “disabled”.

enabled.

Function

CC/VSS level to

25 to 30 P80 to P85 C General-purpose I/O ports

This function is valid when the output specification for TOT0 to TOT5

is “disabled”.

TOT0 to TOT5 16-bit reload timer output pins (TOT0 to TOT5)

31,

32

34 to 41 P90 to P97 F Open-drain I/O ports

* :FPT-120P-M03, FPT-120C-C02

8

P86,
P87

PPG0,
PPG1

AN08 to AN15 10-bit A/D converter analog input pins

C General-purpose I/O ports

This function is valid when the PPG0, and PPG1 output specification

is “disabled”.

16-bit PPG timer output pins

This function is valid when the PPG control/status register

specification is “PPG output pins”.

This function is valid when the analog input enable register

specification is “port”.

This function is valid when the analog input enable register

specification is “analog input”.

(Continued)

Pin no.

Pin name

QFP*

Circuit

type

55 PA0 C General-purpose I/O port

This function is always valid.

ASR0 ICU (input capture unit) input pin

This function is valid during ICU (input capture unit) input operations.

56 PA1 C General-purpose I/O port

This function is always valid.

PWC0 PWC input pin

During PWC0 input operations, this input may be used suddenly at

any time; therefore, it is necessary to stop output by other functions

on this pin, except when using it for output deliberately.

POT0 PWC output pin

This function is valid during PWC output operations.

57 to 59 PA2 to PA4 C General-purpose I/O ports

This function is always valid.

PWC1 to PWC3 PWC input pins

This function is valid during PWC input operations.

During PWC1 to PWC3 input operations, this input may be used

suddenly at any time; therefore, it is necessary to stop output by other

functions on this pin, except when using it for output deliberately.

MB90220 Series

Function

POT1 to POT3 PWC output pins

This function is valid during PWC output operations.

ASR1 to ASR3 ICU (input capture unit) input pins

This function is valid during ICU (input capture unit) input operations.

60,

61

PA5,
PA6

B General-purpose I/O ports

This function is always valid.

When these pins are open in input mode, through current may leak in

stop mode/reset mode, be sure to fix these pins to V

use these pins in input mode.

INT0,
INT1

DTP/External interrupt request input pins

When DTP/external interrupts are enabled, these inputs may be used

suddenly at any time; therefore, it is necessary to stop output by other

functions on these pins, except when using them for output

deliberately.

When these pins are open in input mode, through current may leak in

stop mode/reset mode, be sure to fix these pins to V

use these pins in input mode.

62 PA7 B General-purpose I/O port

This function is always valid.

When these pins are open in input mode, through current may leak in

stop mode/reset mode, be sure to fix these pins to V

use these pins in input mode.

* :FPT-120P-M03, FPT-120C-C02

CC/VSS level to

CC/VSS level to

CC/VSS level to

(Continued)

9

MB90220 Series

Pin no.

Pin name

QFP*

62 INT2 B DTP/External interrupt request input pin

ATG

64 PB0 C General-purpose I/O port

SOD0 UART0 (ch.0) serial data output

65 PB1 C General-purpose I/O port

SID0 UART0 (ch.0) serial data input pin

Circuit

type

Function

When DTP/external interrupts are enabled, these inputs may be used

suddenly at any time; therefore, it is necessary to stop output by other

functions on these pins, except when using them for output

deliberately.

When these pins are open in input mode, through current may leak in

stop mode/reset mode, be sure to fix these pins to V

use these pins in input mode.

10-bit A/D converter external trigger input pin

When these pins are open in input mode, through current may leak in

stop mode/reset mode, be sure to fix these pins to V

use these pins in input mode.

This function is valid when the UART0 (ch.0) serial data output

specification is “disabled”.

This function is valid when the UART0 (ch.0) serial data output

specification is “enabled”.

This function is always valid.

During UART0 (ch.0) input operations, this input may be used

suddenly at any time; therefore, it is necessary to stop output by other

functions on this pin, except when using it for output deliberately.

CC/VSS level to

CC/VSS level to

66 PB2 C General-purpose output port

This function is valid when the UART0 (ch.0) clock output

specification is “disabled”.

SCK0 UART0 (ch.0) clock output pin

The clock output function is valid when the UART0 (ch.0) clock output

specification is “enabled”.

UART0 (ch.0) external clock input pin. This function is valid when the

port is in input mode and the UART0 (ch.0) specification is external

clock mode.

67 PB3 C General-purpose I/O port

This function is valid when the UART0 (ch.1) serial data output

specification is “disabled”.

SOD1 UART0 (ch.1) serial data output pin

This function is valid when the UART0 (ch.1) serial data output

specification is “enabled”.

68 PB4 C General-purpose I/O port

This function is always valid.

SID1 UART0 (ch.1) serial data input pin

During UART0 (ch.1) input operations, this input may be used

suddenly at any time; therefore, it is necessary to stop output by other

functions on this pin, except when using it for output deliberately.

* :FPT-120P-M03, FPT-120C-C02

(Continued)

10

MB90220 Series

Pin no.

Pin name

QFP*

69 PB5 C General-purpose I/O port

SCK1 UART0 (ch.1) clock output pin

70 PB6 C General-purpose I/O port

SOD2 UART0 (ch.2) serial data output pin

71 PB7 C General-purpose I/O port

SID2 UART0 (ch.2) serial data input pin

72 PC0 C General-purpose I/O port

SCK2 UART0 (ch.2) clock output pin

73 PC1 C General-purpose I/O port

SOD3 UART1 serial data output pin

74 PC2 C General-purpose I/O port

Circuit

type

This function is valid when the UART0 (ch.1) clock output specification

is “disabled”.

The clock output function is valid when the UART0 (ch.1) clock output

specification is “enabled”.

UART0 (ch.1) external clock input pin

This function is valid when the port is in input mode and the UART0

(ch.1) specification is external clock mode.

This function is valid when the UART0 (ch.2) serial data output

specification is “disabled”.

This function is valid when the UART0 (ch.2) serial data output

specification is “enabled”.

This function is always valid.

During UART0 (ch.2) input operations, this input may be used

suddenly at any time; therefore, it is necessary to stop output by other

functions on this pin, except when using it for output deliberately.

This function is valid when the UART0 (ch.2) clock output

specification is “disabled”.

The clock output function is valid when the UART0 (ch.2) clock output

specification is “enabled”.

UART0 (ch.2) external clock input pin

This function is valid when the port is in input mode and the UART0

(ch.2) specification is external clock mode.

This function is valid when the UART1 serial data output specification

is “disabled”.

This function is valid when the UART1 serial data output specification

is “enabled”.

This function is always valid.

Function

SID3 UART1 serial data input pin

* :FPT-120P-M03, FPT-120C-C02

During UART1 input operations, this input may be used suddenly at

any time; therefore, it is necessary to stop output by other functions

on this pin, except when using it for output deliberately.

(Continued)

11

MB90220 Series

(Continued)

Pin no.

Pin name

QFP*

Circuit

type

75 PC3 C General-purpose I/O port

This function is valid when the UART1 clock output specification is

“disabled”.

SCK3 UART1 clock output pin

The clock output function is valid when the UART1 clock output

specification is “enabled”.

UART1 external clock input pin

This function is valid when the port is in input mode and the UART1

specification is external clock mode.

76 PC4 C General-purpose I/O port

This function is always valid.

CTS0 UART0 (ch.0) Clear To Send input pin

When the UART0 (ch.0) CTS function is enabled, this input may be

used sudde nly at any ti me; th eref or e, i t i s n ece ss ary t o s top ou tp ut by

other functions on this pin, except when using it for output

deliberately.

77 PC5 C General-purpose I/O port

This function is always valid.

TRG0 16-bit PPG timer trigger input pin

This function is valid when the 16-bit PPG timer trigger input

specification is enabled.

The data on this pin is read as 16-bit PPG timer trigger input (TRG0).

During this operation, the input may be used suddenly at any time;

therefore, it is necessary to stop output by other functions on this pin,

except when using it for output deliberately.

Function

8,

V

CC Power

54,

94

V

33,

SS Power

63,
91,

119

42 AV

CC Power

43 AVRH Power

44 AVRL Power

45 AV

SS Power

* :FPT-120P-M03, FPT-120C-C02

supply

supply

supply

supply

supply

supply

Power supply for digital circuitry

Ground level for digital circuitry

Power supply for analog circuitry

When turning this power supply on or off, always be sure to first apply

electric potential equal to or greater than AV

During normal operation AV

CC should be equal to VCC.

CC to VCC.

Reference voltage input for analog circuitry

When turning this pin on or off, always be sure to first apply electric

potential equal to or greater than AVRH to AV

CC.

Reference voltage input for analog circuitry

Ground level for analog circuitry

(Continued)

12

MB90220 Series

■ I/O CIRCUIT TYPE

Type Circuit Remarks

A • Oscillation feedback resistor: Approx. 1 MΩ

MB90223
MB90224

X1

X0

Standby control signal

X1

MB90P224B
MB90W224B

• Oscillation feedback resistor: Approx. 1 MΩ
MB90P224A
MB90W224A

X0

Standby control signal

B • CMOS-level output

• CMOS-level hysteresis input with no standby
control

Digital output

Digital output

R

Digital input

Note: The pull-up and pull-down resistors are always connected, regardless of the state.

(Continued)

13

MB90220 Series

Type Circuit Remarks

C • CMOS-level output

• CMOS-level hysteresis input with standby

Digital output

Digital output

R

Digital input

D • CMOS-level input with no standby control

control

Mask ROM products only:
MD2: with pull-down resistor
MD1: with pull-up resistor
MD0: with pull-down resistor

R

Digital input

• CMOS-level input with no standby control
MD2 of OTPROM products/EPROM products
only

R

Digital input
VPP power supply

E • CMOS-level hysteresis input with no standby

control

• With input analog filter (40 ns Typ.)

R

Analog filter

Digital input

Note: The pull-up and pull-down resistors are always connected, regardless of the state.

14

(Continued)

MB90220 Series

(Continued)

Type Circuit Remarks

F • N-channel open-drain output

• CMOS-level hysteresis i nput with A/D
control and with standby control

Digital output

R

A/D input
Digital input

G • CMOS-level hyste resi s input with no

Pull-up
resistor

standby control and with pull-up resistor

• With input analog filter (40 ns Typ.)

R

MB90223, MB90224: RST
to with or without a pull-up resistor by a
mask option.

R

MB90P224A: With pull-up resistor
MB90W224A: With pull-up resistor
MB90P224B: With no pull-up resistor
MB90W224B: With no pull-up resistor

Analog filter

: P-type transistor : N-type transistor

Digital input

Note: The pull-up and pull-down resistors are always connected, regardless of the state.

pin can be set

15

MB90220 Series

■ HANDLING DEVICES

1. Preventing Latchup

CMOS ICs may c ause latch up when a voltag e higher t han VCC or lower th an VSS is appl ied to i nput or ou tput
pins other than medium-and high-voltage pins, or when a voltage exceeding the rating is applied between V
and VSS.

If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Use meticulous care not to let any voltage exceed the maximum rating.
Also, take care to preven t the analog power supply (AV
digital power supply (V

CC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.

3. Treatment of Pins when A/D is not Used

Connect to be AVCC = AVRH = VCC and AVSS = AVRL = VSS even if the A/D converter is not in use.

CC and AVRH) and a nalog input from exceeding the

CC

4. Precautions when Using an External Input

To reset the internal circuit properly by the “L” level input to the RST pin, the “L” level input to the RST pin must
be maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.

5. VCC and VSS Pins

Apply equal potential to the VCC and VSS pins.

6. Supply Voltage Variation

The operation assurance range for the VCC supply voltage is as given in the ratings. Howev er, sudden changes
in the supply voltage can cause miso peration, even if the voltage remains within the rated range. Therefore, it
is impor tant to su pply a stable voltage to t he IC. The recommende d power supply co ntrol guideli nes are that
the commercial frequency (50 to 6 0 Hz) ripple var iation (P-P value) on V
standard V

CC value and that the transient rate of change during sudden changes, such as during power supply

CC should be less than 10% of the

switching, should be less than 0.1 V/ms.

7. Notes on Using an External Clock

When using an external clock, drive the X0 pin as illustrated below. When an external clock is used, oscillation
stabilization time is required even for power-on reset and wake-up from stop mode.

Use of External Clock

•

MB90220

X0

X1

Note: Wh en using an exter nal clock, be sure to in put external clo ck more than 6 machin e cycles after

setting the HST

pin to “L” to transfer to the hardware standby mode.

16

MB90220 Series

8. Power-on Sequence for A/D Converter Power Supplies and Analog Inputs

Be sure to turn on the digital power supply (VCC) before applying voltage to the A/D converter power supplies
(AV

CC, AVRH, and AVRL) and analog inputs (AN00 to AN15).

When turning power supplies off, turn off the A/D converter power supplies (A V
inputs (AN00 to AN15) first, then the digital power supply (V

When turning AVRH on or off, be careful not to let it exceed AV

CC).

CC.

CC, A VRH, and A VRL) and analog

17

MB90220 Series

■ PROGRAMMING FOR MB90P224A/P224B/W224A/W224B

In EPROM mode, the MB9 0P224A/P224B/W224A/W224B func tions equivalent to the MBM27C1000. This
allows the EPROM to be programmed with a general-pur pose EPROM programmer by using the dedicated
socket adapter (do not use the electronic signature mode).

1. Program Mode

When shipped from Fujitsu, an d after eac h erasure, all bits (96 K × 8 bits) in the MB9 0P224A /P224 B/W224 A/
W224B are in the “1” sta te. Data is written to the ROM by selectively programming “0’s” into the desired bit
locations. Bits cannot be set to “1” electrically.

2. Programming Procedure

(1) Set the EPROM programmer to MBM27C1000.
(2) Load program data into the EPROM programmer at 08000

H to 1FFFFH.

Note that ROM addresses FE8000
W224B series assign to 08000

FFFFFFH

H

FE8000

Operation mode

* : Be sure to set the programming, the start address and the stop address on the EPROM programmer to 08000

H to FFFFFFH in the operation mode in the MB90P224A/P224B/W224A/

H to 1FFFFH in the EPROM mode (on the EPROM programmer).

H *

1FFFF

08000H *

(Corresponding addresses on the EPROM mode)

EPROM mode

H/1FFFFH.

(3) Mount the MB90P224A/P224B/W224A/W224B on the adapter socket, then fit the adapter socket onto the

EPROM programmer. When mounting the device and the adapter socket, pay attention to their mounting

orientations.
(4) Start programming the program data to the device.
(5) If programming has not successfully resulted, connect a capacitor of approx. 0.1 µF between V

between V

PP and GND.

CC and GND,

Note: The mask ROM products (MB90223, MB90224) does not support EPROM mode. Data cannot, therefore, be

read by the EPROM programmer.

18

MB90220 Series

3. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer

Part No.
Package
Compatible socket adapter

Sun Hayato Co., Ltd.
Recommended

programmer
manufacturer
and
programmer
name

Inquiry: Sun Hayato Co., Ltd.: TEL: [phone]

Advantest Corp.: TEL: Except JAPAN (81)-3-3930-4111

Advantest corp.

FAX: [phone]

R4945A

(main unit)

R49451A
(adapter)

+

MB90P224B

QFP-120

ROM-120QF-32DP-16F

Recommended

4. Erase Procedure

Data written in the MB90W224A/W224B is erased (from “0” to “1”) by exposing the chip to ultraviolet rays with
a wavelength of 2,537 Å through the translucent cover.

2

Recommended irradiati on dosage for exposure is 10 Wsec/cm
with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface illuminance
is 1200 µW/cm

If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the la mp
increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent
par t of the package is stained with oil o r adhesive, transmiss ion of ultraviolet rays is de graded, resulting in a
longer erasure time. In that case, clean the t ranslucent part usi ng alcohol (or other solvent not affecting the
package).

2

).

. This amount is reached in 15 to 20 mi nutes

The above recommended dosage is a value which takes the guard band into consideration and is a multiple of
the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure;
the purpo se of the guard band is to ensure erasur e in all temperature and supply voltage ranges. In addition,
check the life span of the lamp and control the illuminance appropriately.

Data in the MB90W224A/W224B is erased by exposure to light with a wavelength of 4,000 Å or less.
Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure

results in a much lower erasure rate than exposure to 2,537 Å ultraviolet rays. Note that exposure to such lights
for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light
with a wavelength of 4,000 Å or less, cover the translucent part, for example, with a protective seal to pr event
the chip from being exposed to the light.

Exposure to light with a wavelength of 4,000 to 5,000 Å or more will not erase data in the device. If the light
applied to the chip has a ver y high illuminance, however, the device may cause malfunction in the circuit for
reasons of general semiconductor characteristics. Although the circuit will recover normal operation when
exposure is stopped, the device require s proper co unter meas ures for use in a place exposed continuously to
such light even though the wavelength is 4,000 Å or more.

19

MB90220 Series

5. Recommended Screening Conditions

High temperature aging is recommended as the pre-assembly screening procedure.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

6. Programming Yeild

MB90P224A/P224B cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always
be guaranteed to be 100%.

7. Pin Assignments in EPROM Mode

(1) Pins Compatible with MBM27C1000

MBM27C1000

MB90P224A/P224B/

MB90W224A/W224B

MBM27C1000

Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name

1V

PP 87 MD2 (VPP)32VCC 8, 54, 94 VCC

2OE 83P55 31PGM 84P56
3 A15 7 P37 30 N.C. — —
4 A12 4 P34 29 A14 6 P36
5 A07 118 P27 28 A13 5 P35
6 A06 117 P26 27 A08 120 P30
7 A05 116 P25 26 A09 1 P31
8 A04 115 P24 25 A11 3 P33

9 A03 114 P23 24 A16 9 P40
10 A02 113 P22 23 A10 2 P32
11 A01 112 P21 22 CE 82 P54
12 A00 111 P20 21 D07 102 P07
13 D00 95 P00 20 D06 101 P06

MB90P224A/P224B/

MB90W224A/W224B

14 D01 96 P01 19 D05 100 P05
15 D02 97 P02 18 D04 99 P04
16 GND

33, 63, 91,119

VSS 17 D03 98 P03

20

(2) Power Supply and GND Connection Pins

Type Pin no. Pin name

Power supply 89

88
86

8, 54, 94

MB90220 Series

MD0
MD1
HST

VCC

GND 33, 63, 91, 119

44
45
80
81
90

(3) Pins other than MBM27C1000-compatible Pins

Pin no. Pin name Treatment

92 X0 Pull up with 4.7 KΩ resistor
93 X1 OPEN

109
110
10 to 16
42
43
46
47
48 to 53
17 to 24
25 to 32
34 to 41
55 to 61
63 to 70
71 to 76
78
79
85
103 to 108

P16
P17
P41 to P47
AV

CC

AVRH
P60
P61
P62 to P67
P70 to P77
P80 to P82
P90 to P97
PA0 to PA7
PB0 to PB7
PC0 to PC5
P50
P51
P57
P10 to P15

Connect pull-up resistor of about 1 MΩ to each pin

V

SS

AVRL

SS

AV

P52
P53

RST

21

MB90220 Series

■ BLOCK DIAGRAM

X1
X0
RST
HST
MD0 to MD2

WI

CTS0
SID0 to SID2

SOD0 to SOD2

SCK0 to SCK2
SID3

SOD3
SCK3

5

4

3

3

UART0 × 3

Clock controller

Write-inhibit

RAM

UART1

PWC timer × 4

ICU (Input

Capture Unit)

Internal data bus

24-bit timer counter

OCU (Output

Compare Unit)

4

PWC0 to PWC3

4

POT0 to POT3

4

ASR0 to ASR3

× 4

8

DOT0 to DOT7

× 4

TOT0 to TOT5
TIN1 to TIN5

ATG
AN00 to AN15
AVCC
AVRH
AVRL
AV

SS

P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA7
PB0 to PB7
PC0 to PC5

PPG0
PPG1

TRG0

16-bit reload timer

6

21

102

2

× 6

5

10-bit

A/D converter

16 channels

16-bit PPG timer

I/O ports

× 2

DTP/External

interrupt

× 8

External bus

interface

2

MC-16F CPU

F

RAM

ROM

8

16

2

29

INT0 to INT7

D00 to D15
RDY

HRQ
A00 to A23

CLK
HAK
WRH
WRL
RD

22

■ PROGRAMMING MODEL

MB90220 Series

Dedicated Registers

AH

AL

USP
SSP
PS

PC
USPCU
SSPCU
USPCL
SSPCL

DPR

PCB
DTB
USB
SSB
ADB

Accumulator

User stack pointer
System stack pointer
Processor status
Program counter
User stack upper register
System stack upper register
User stack lower register
System stack lower register

Direct page register

Program bank register
Data bank register
User stack bank register
System stack bank register
Additional bank register

General-purpose Registers

000180

Processor Status (PS)

ILM

Upper

Lower

H + RP × 10H

8 bit

32 bit

RP

16 bit

Max.32 banks

R 7
R 5
R 3
R 1

MSB LSB

— I S T N Z V C

R 6
R 4
R 2

R 0
RW3
RW 2
RW 1
RW 0

16 bit

RW 7
RW 6
RW 5

RW 4

RL 3

RL 2

RL 1

RL 0

C C R

23

MB90220 Series

■ MEMORY MAP

H

FFFFFF

Address #1

010000

H

Address #2

002000

H

001F00H

Single chip

ROM area ROM area

ROM area

FF bank

image

Internal
register area

Internal ROM

and external bus

ROM area

FF bank

image

Internal
register area

External ROM

and external bus

Internal
register area

Address #3

Address #4

000380

H

000180H
000100H

0000C0H

000000H

MB90223
MB90224

MB90P224A/P224B
MB90W224A/W224B

MB90V220

Write-inhibit

RAM

RAM

Peripherals Peripherals Peripherals

Write-inhibit

RAM

RAM

Registers

Write-inhibit

RAM

RAM

RegistersRegisters

: Internal

: External

: No access

Type Address #1 Address #2 Address #3 Address #4

FF0000
FE8000H

(FE0000

H

004000H
004000H

H)

004000H

000F00H
001500H

001900H

000D00H
001300H

001500H

24

■ I/O MAP

MB90220 Series

Address Register

*3

000000
000001
000002
000003
000004
000005
000006
000007
000008
000009
00000A
00000B
00000C
00000D

Port 0 data register PDR0 R/W Port 0

H

*3

Port 1 data register PDR1 R/W Port 1

H

*3

Port 2 data register PDR2 R/W Port 2

H

*3

Port 3 data register PDR3 R/W Port 3

H

*3

Port 4 data register PDR4 R/W Port 4

H

*3

Port 5 data register PDR5 R/W Port 5

H

H Port 6 data register PDR6 R/W Port 6 11111111
H Port 7 data register PDR7 R Port 7 XXXXXXXX
H Port 8 data register PDR8 R/W Port 8 XXXXXXXX
H Port 9 data register PDR9 R/W Port 9 11111111

H Port A data register PDRA R/W Port A XXXXXXXX
H Port B data register PDRB R/W Port B XXXXXXXX
H Port C data register PDRC R/W Port C ––XXXXXX

H

to 0FH

*3

000010H
000011
000012
000013
000014
000015

Port 0 data direction register DDR0 R/W Port 0

*3

Port 1 data direction register DDR1 R/W Port 1

H

*3

Port 2 data direction register DDR2 R/W Port 2

H

*3

Port 3 data direction register DDR3 R/W Port 3

H

*3

Port 4 data direction register DDR4 R/W Port 4

H

*3

Port 5 data direction register DDR5 R/W Port 5

H

Register

name

Access

(Reserved area)

Resouce

name

Initial value

XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX

*1

00000000
00000000
00000000
00000000
00000000

00000000
000016
000017
000018
000019
00001A
00001B
00001C

00001D
to 1FH

H Port 6 analog input enable register ADER0 R/W Port 6 11111111
H Port 7 data direction register DDR7 R/W Port 7 1 1111111
H Port 8 data direction register DDR8 R/W Port 8 0 0000000
H Port 9 analog input enable register ADER1 R/W Port 9 11111111

H Port A data direction register DDRA R/W Port A 00000000
H Port B data direction register DDRB R/W Port B 00000000

H

Port C data direction register DDRC R/W Port C

H

(Reserved area)

*1

000020H Mode control register 0 UMC0 R/W
000021

000022

H Status register 0 USR0 R/W 00010000

Input data register 0

H

/output data register 0

UIDR0

/UODR0

R/W XXXXXXXX

––000000

00000100

UART 0 (ch.0)

(Continued)

25

MB90220 Series

Address Register

000023
000024
000025

000026
000027

000028
000029

00002A
00002B

00002C
00002D

H Rate and data register 0 URD0 R/W UART0 (ch.0) 0 000000X
H Mode control register 1 UMC1 R/W
H Status register 1 USR1 R/W 00010000

Input data register 1

H

/output data register 1

H Rate and data register 1 URD1 R/W 0 000000X
H Mode control register 2 UMC2 R/W
H Status register 2 USR2 R/W 00010000

Input data register 2

H

/output data register 2

H Rate and data register 2 URD2 R/W 0 000000X
H UART CTS control register UCCR R/W UART0 (ch.0) – ––000––

H

Register

name

Access

UIDR1

/UODR1

UIDR2

/UODR2

(Reserved area)

R/W

R/W

*1

00002EH Mode register SMR R/W
00002F

000030

H Control register SCR R/W 00000100

Input data register

H

/output data register

SIDR

/SODR

R/W

Resouce

name

UART0 (ch.1)

UART0 (ch.2)

UART1

Initial value

00000100

XXXXXXXX

00000100

XXXXXXXX

00000000

XXXXXXXX
000031

000032
000033
000034
000035

H Status register SSR R/W 00001–00
H A/D channel setting regist er ADCH R/W
H A/D mode register ADMD R/W –––X0000
H A/D control status register ADCS R/W 0000––00

H

(Reserved area)

*1

000036H

A/D data register ADCD R

000037
000038

H 000000XX

H

(Reserved area)

*1

000039H
00003AH DTP/interrupt enable register ENIR R/W
00003B
00003C

H DTP/interrupt source register EIRR R/W 00000000

H

Request level setting register ELVR R/W

00003D
00003E

to 3FH

H 00000000

H

(Reserved area)

*1

000040H

Timer control status register 0 TMCSR0 R/W

000041

H ––––0000

10-bit A/D
converter

10-bit A/D
converter

DTP/external
interrupt

16-bit reload
timer 0

00000000

XXXXXXXX

00000000

00000000

00000000

(Continued)

26

MB90220 Series

Address Register

000042

H

Timer control status register 1 TMCSR1 R/W

000043
000044

H ––––0000

H

Timer control status register 2 TMCSR2 R/W

000045
000046

H ––––0000

H

Timer control status register 3 TMCSR3 R/W

000047
000048

H ––––0000

H

Timer control status register 4 TMCSR4 R/W

000049
00004A

H ––––0000

H

Timer control status register 5 TMCSR5 R/W

00004B
00004C

H ––––0000

H

PPG control status register 0 PCNT0 R/W

00004D
00004E

H 00000000

H

PPG control status register 1 PCNT1 R/W

00004F
000050

H 00000000

H

PWC control status register 0 PWCSR0 R/W PWC timer 0

000051

H 00000000

Register

name

Access

Resouce

name

16-bit reload
timer 1

16-bit reload
timer 2

16-bit reload
timer 3

16-bit reload
timer 4

16-bit reload
timer 5

16-bit PPG
timer 0

16-bit PPG
timer 1

Initial value

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

000052

H

PWC control status register 1 PWCSR1 R/W PWC timer 1

000053
000054

H 00000000

H

PWC control status register 2 PWCSR2 R/W PWC timer 2

000055
000056

H 00000000

H

PWC control status register 3 PWCSR3 R/W PWC timer 3

000057
000058
000059

H 00000000
H ICU control register 0 ICC0 R/W

H

(Reserved area)

*1

00005AH Input capture control register 1 ICC1 R/W
00005B

H

00005CH
00005DH

(Reserved area)

*1

00005EH
00005FH
000060H

OCU control register 00 CCR00 R/W

000061

H ––––0000

ICU (Input
Capture Unit)

ICU (Input
Capture Unit)

OCU (Output
Compare Unit)

00000000

00000000

00000000

00000000

00000000

11110000

(Continued)

27

MB90220 Series

Address Register

000062

H

OCU0 control register 01 CCR01 R/W

000063
000064

H ––––0000

H

000065H
000066H
000067H
000068H

OCU0 control register 10 CCR10 R/W

000069
00006A

H 00000000

H

OCU0 control register 11 CCR11 R/W

00006B
00006C

H 00000000

H

00006DH
00006EH
00006FH
000070H

Free-run timer control register TCCR R/W

000071

H ––111111

Register

name

Access

(Reserved area)

(Reserved area)

Resouce

name

OCU (Output

Initial value

11110000

Compare Unit)

*1

––––0000

OCU (Output
Compare Unit)

*1

––––0000

11000000

000072
000073

H

Free-run timer lower-order data
register

H 00000000

TCRL

24-bit timer
counter

00000000

R

000074
000075
000076
000077H

H

Free-run timer upper-order data
register

H 00000000

H

TCRH

(Reserved area)

*1

00000000

000078H
000079H
00007AH PWC divider ratio control register 0 DIVR0 R/W PWC timer 0 ––––––00
00007B

H

Reserved area

*1

00007CH PWC divider ratio control register 1 DIVR1 R/W PWC timer 1 ––––––00
00007D

H

Reserved area

*1

00007EH PWC divider ratio control register 2 DIVR2 R/W PWC timer 2 ––––––00
00007F

H

Reserved area

*1

000080H PWC divider ratio control register 3 DIVR3 R/W PWC timer 3 ––––––00
000081

to 8DH

H

(Reserved area)

*1

(Continued)

28

MB90220 Series

Address Register

00008E
00008F

H WI control registe r WICR R/W

H

000090H
to 9EH

00009FH

0000A0
0000A3
0000A4
0000A5
0000A8

0000A9
0000B0

Delay interrupt source generation
/release register

H Standby control regis t e r STBY C R/W
H Address mid-order control register MACR W External pin ########

Address higher-order control

H

register

H External pin control register EPCR W External pin ##0–0#00
H Watchdog timer control register WDTC R/W

H Timebase timer control register TBTC R/W
H Interrupt control register 00 ICR00 R/W

Register

name

Access

(Reserved area)

*1

Resouce

name

Write-inhibit
RAM

Initial value

–––X––––

Delay in te rrupt

DIRR R/W

generation

–––––––0

module
Low power

consumption

0001****

HACR W External pin ########

Watchdog
timer

Timebase
timer

XXXXXXXX

–––00000

00000111
0000B1
0000B2
0000B3
0000B4
0000B5
0000B6
0000B7
0000B8
0000B9
0000BA
0000BB
0000BC
0000BD
0000BE
0000BF
0000C0

to FFH
001F00H
001F01

H Interrupt control register 01 ICR01 R/W 00000111
H Interrupt control register 02 ICR02 R/W 00000111
H Interrupt control register 03 ICR03 R/W 00000111
H Interrupt control register 04 ICR04 R/W 00000111
H Interrupt control register 05 ICR05 R/W 00000111
H Interrupt control register 06 ICR06 R/W 00000111
H Interrupt control register 07 ICR07 R/W 00000111
H Interrupt control register 08 ICR08 R/W 00000111
H Interrupt control register 09 ICR09 R/W 00000111

H Interrupt control register 10 ICR10 R/W 00000111
H Interrupt control register 11 ICR11 R/W 00000111
H Interrupt control register 12 ICR12 R/W 00000111
H Interrupt control register 13 ICR13 R/W 00000111
H Interrupt control register 14 ICR14 R/W 00000111

H Interrupt control register 15 ICR15 R/W 00000111

H

(External area)

*2

Interrupt
controller

00000000

PWC data buffer register 0 PWCR0 R/W PWC timer 0

H 00000000

(Continued)

29

MB90220 Series

Address Register

001F02

H

PWC data buffer register 1 PWCR1 R/W PWC timer 1

001F03
001F04

H 00000000

H

PWC data buffer register 2 PWCR2 R/W PWC timer 2

001F05
001F06

H 00000000

H

PWC data buffer register 3 PWCR3 R/W PWC timer 3

001F07
001F08

H 00000000

H

to 1F0FH
001F10H
001F11
001F12
001F13
001F14
001F15
001F16
001F17

OCU compare lower-order data
register 00

H 00000000

H

OCU compare higher-order data
register 00

H 00000000

H

OCU compare lower-order data
register 01

H 00000000

H

OCU compare higher-order data
register 01

H 00000000

Register

name

Access

(Reserved area)

CPR00L

CPR00

CPR01L

CPR01

*1

R/W

R/W

Resouce

name

Output
compare 00

Output
compare 01

Initial value

00000000

00000000

00000000

00000000

00000000

00000000

00000000

001F18
001F19
001F1A
001F1B
001F1C
001F1D
001F1E
001F1F
001F20
001F21
001F22
001F23
001F24
001F25
001F26
001F27

H

OCU compare lower-order data
register 02

H 00000000

H

OCU compare higher-order data
register 02

H 00000000

H

OCU compare lower-order data
register 03

H 00000000

H

OCU compare higher-order data
register 03

H 00000000

H

OCU compare lower-order data
register 04

H 00000000

H

OCU compare higher-order data
register 04

H 00000000

H

OCU compare lower-order data
register 05

H 00000000

H

OCU compare higher-order data
register 05

H 00000000

CPR02L

CPR02

CPR03L

CPR03

CPR04L

CPR04

CPR05L

CPR05

R/W

R/W

R/W

R/W

Output
compare 02

Output
compare 03

Output
compare 10

Output
compare 11

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

(Continued)

30