FUJITSU MB90210 DATA SHEET

查询MB90214供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13501-6E

16-bit Proprietary Microcontroller

CMOS

F2MC-16F MB90210 Series

MB90214/P214A/P214B/W214A/W214B/V210

■ OUTLINE

The MB90210 series is a line of 16-bit microcontrollers particularly suitable for system control of video cameras,

VTRs, and copiers. The F enhanced instructions for high-level languages and supporting extended addressing modes.

MC-16F CPU integrated in this s eries is based on the F2MC*-16, while providing

The MB90210 series incorporates a variety of peripheral resources such as a PWC timer with 4 channels, a 10bit A/D converter with 8 channels, UART serial ports with 3 channels (1 channel for CTS and 1 channel for dual input/output pin switching), 16-bit reload timers with 8 channels, and an 8-bit PPG timer with 1 channel.

MB90P214B/W214B is under development.

MC stands for FUJITSU Flexible Microcontroller.

*: F

■ PACKAGE

80-pin Plastic QFP

80-pin Ceramic QFP

(FPT-80P-M06)

(FPT-80C-C02)

MB90210 Series

■ FEATURES

F2MC-16F CPU

• Minimum execution time: 62.5 ns/16-MHz oscillation (using a duty control system)

• Instruction sets optimized for controllers Upward object-compatible with the F Various data types (bit, byte, word, and long-word) Instruction cycle improved to speed up operation Extended addressing modes: 25 types High coding efficiency Access method (bank access with linear pointer) Enhanced multiplication and division instructions (with signed instructions added) Higher-precision operation using a 32-bit accumulator

• Extended intelligent I/O service (Automatic transfer function independent of instructions) access area expanded to 64 Kbytes

• Enhanced instruction set applicable to high-level language (C) and multitasking System stack pointer Enhanced pointer-indirect instructions Barrel shift instruction Stack check function

• Increased execution speed: 8-byte instruction queue

• Powerful interrupt functions: 8 levels and 29 sources

MC-16(H)

Integrated Peripheral Resources

• ROM : 64 Kbytes (MB90214) EPROM : 64 Kbytes (MB90W214A/W214B) OTPROM: 64Kbytes (MB90P214A/P214B)

• RAM: 3 Kbytes (MB90214)

4 Kbytes (MB90P214A/P214B/W214A/W214B/V210)

• General-purpose ports: max. 65 channels

• PWC timer with time measurement function: 4 channels

• 10-bit A/D converter: 8 channels

• UART: 3 channels

• Including: 1 channel with CTS function

1 channel with I/O pin switching function

• 16-bit reload timer Toggled output, external clock, and gate functions: 4 channels

External clock and gate functions: 4 channels

• 8-bit PPG timer: 1 channel

• DTP/External-interrupt inputs: 4 channels

• Write-inhibit RAM: 256 bytes (MB90V210: 512 bytes)

• Timebase counter: 18 bits

• Clock gear function

• Low-power consumption mode Sleep mode Stop mode Hardware standby mode

MB90210 Series

Product Description

• MB90214 is a mask ROM product.

• MB90P214A/P214B are OTPROM products.

• MB90W214A/W214B are EPROM products. ES only.

• Operating temperature of MB90P214A/W214A is –40°C to +85°C. (Howev er, the A C characteristics is assured in –40°C to +70°C)

• MB90V210 is a evaluation device for the program development. ES only.

MB90210 Series

■ PRODUCT LINEUP

Part numb er

Item

Classification Mask ROM product OTPROM product EPROM product For evaluation ROM size 64 Kbytes 64 Kbytes 64 Kbytes — RAM size 3 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes CPU functions The number of instructions: 412

Ports I/O ports (N-ch open-drain): 8

PWC timer Number of channels: 4

10-bit A/D converter

MB90214

Instruction bit length: 8 or 16 bits Instruction length: 1 to 7 bytes Data bit length: 1, 4, 8, 16, or 32 bits Minimum execution time: 62.5 ns/16 MHz Interrupt processing time: 1.0 µs/16 MHz (min.)

I/O ports (CMOS): 57 Total: 65

16-bit reload timer operation (operating clock cycle: 0.25 µs to 1.31 ms)

16-bit pulse-width count operation (Allowing continuous/one-shot measurement, H/L width

measurement, inter-edge measurement, and divided-frequency measurement)

Single conversion mode (conversion for each input channel)

Scan conversion mode (continuous conversion for up to 8 consecutive channels)

Continuous conversion mode (repeated conversion for a selected channel)

Stop conversion mode (conversion every fixed cycle)

MB90P214A MB90P214B

Resolution: 10 or 8 bits, Number of inputs: 8

MB90W214A MB90W214B

MB90V210

UART Number of channels: 3

(1 channel with CTS function; 1 channel with I/O pin switching function)

Clock-synchronous trans fer mode

(full-duplex double buffering, 7- to 9-bit data length, 2400 to 62500 bps)

Asynchronous transfer mode

(full-duplex double buffering, 7- to 9-bit data length, 2400 to 62500 bps)

Timer Number of channels: 4 channels × 2 types

16-bit reload timer operation (operating clock cycle: 0.25 µs to 1.05 s)

8-bit PPG timer Number of channels: 1

8-bit PPG operation (operating clock cycle: 0.25 µs to 6 s)

DTP/External interrupt

Write-inhibit RAM RAM size: 256 bytes (MB90V210: 512 bytes)

Standby mode Stop mode (activated by software or hardware) and sleep mode Gear function Machine clock operating frequency switching: 16, 8, 4, or 1 MHz (at 16 MHz oscillation) Package FPT-80P-M06 FPT-80C-C02 PGA-256C-A02

External interrupt mode (allowing interrupts to activate at four different request levels)

Simple DMA start mode (allowing extended I

RAM write-protectable with WI

Number of inputs: 4

OS to activate at two different request levels)

MB90210 Series

■ DIFFERENCES BETWEEN MB90214 (MASK ROM PRODUCT) AND MB90P214A/P214B/

W214A/W214B

Part numb er

Item

ROM Mask ROM

Pin function 43 pins

Note: MB90V210, device used for evaluation, is not warranted for electrical specifications.

MB90214

64 Kbytes

MD2 pin MD2/V

MB90P214A MB90P214B

OTPROM 64 Kbytes

PP pin

MB90W214A MB90W214B

EPROM

64 Kbytes

MB90210 Series

■ PIN ASSIGNMENT

VSSRST

6463626160595857565554535251504948474645444342

P57/WI

P56/RD

P55/WRL

P54/WRH/CTS0/INT3

P53/HRQ

P52/HAK

P51/RDY

P50/CLK

(Top view)

P82/INT2/ATG

P81/INT1

P80/INT0

P75/SOD0

P74/SID0

P73/SCK0

P72/SOD1

P71/SID1

P70/SCK1

HST

MD2

MD1

MD0

V P00/D00 P01/D01 P02/D02 P03/D03 P04/D04 P05/D05 P06/D06 P07/D07 P10/D08

P11/D09 P12/D10 P13/D11 P14/D12 P15/D13

65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

123456789

P17D15

P16D14

P20A00/TIN0

P23/A03/TIN3

P24/A04/TIN4

P21/A01/TIN1

P25/A05/TIN5

P22/A02/TIN2

101112131415161718192021222324

PPG

I D3

I D2

P30/A08

P26/A06/TIN6

P27/A07/TIN7

P32/A10/TOUT0

P36/A14/SCK3

P37/A15/S

P33/A11/TOUT1

P34/A12/TOUT2

P40/A16/SOD3

P35/A13/TOUT3

P41/A17/SC

P42/A18/S

31/A09/ P

(FPT-80P-M06) (FPT-80C-C02)

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

OD2

PWC0/POUT0

P43/A19/S

P44/A20/

P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2

V P61/AN1 P60/AN0

AV AVRL AVRH

AV PWC3/P47/A23/POUT3 PWC2/P46/A22/POUT2 PWC1/P45/A21/POUT1

■ PIN DESCRIPTION

MB90210 Series

Pin no.

QFP*

64,

65 62 RST 66 V

11, 34,

67 to 74 P00 to P07 B General-purpose I/O ports

75 to 80,

3 to 6 P20 to P23 E General-purpose I/O ports

7 to 10 P24 to P27 E General-purpose I/O ports

12 P30 E General-purpose I/O port

Pin name

X0, X1

D00 to D07 I/O pins for the lower eight bits of external data bus

P10 to P15, P16, P17

D08 to D13, D14, D15

A00 to A03 Output pins for external address buses A00 to A03

TIN0 to TIN3 16-bit reload timer 1 (ch.0 to ch.3) input pins

A04 to A07 Output pins for external address buses A04 to A07

TIN4 to TIN7 16-bit reload timer 2 (ch.4 to ch.7) input pins

A08 Output pin for external address bus A08

Circuit

type

A Crystal oscillator pins (16 MHz)

H External reset request input pin

Power supply Power supply

B General-purpose I/O ports

Digital circuit power supply pin Digital circuit grounding level

These ports are available only in the single-chip mode.

These pins are available in an external-bus mode.

These ports are available in the single-chip mode and in an external-bus mode with the 8-bit data bus specified.

I/O pins for the upper eight bits of external data bus These pins are available in an external-bus mode with the 16-bit

data bus specified.

These ports are available only in the single-chip mode.

These pins are available in an external-bus mode.

These pins are available when the 16-bit reload timer 1 (ch.0 to ch.3) input specification is “enabled”. The data on the pin is read as the 16-bit reload timer 1 (ch.0 to ch.3) input (TIN0 to TIN3).

These ports are available only in the single-chip mode.

These pins are available in an external-bus mode.

These pins are available when the 16-bit reload timer 2 (ch.4 to ch.7) input specification is “enabled”. The data on the pin is read as the 16-bit reload timer 2 (ch.4 to ch.7) input (TIN4 to TIN7).

This port is available in the single-chip mode or when the middle address control register setting is “port.”

This pin is available in an external-bus mode and when the middle address control register set to “address.”

Function

* :FPT-80P-M06, FPT-80C-C02

(Continued)

MB90210 Series

Pin no.

Pin name

QFP*

13 P31 E General-purpose I/O port

A09 Output pin for external address bus A09

PPG PPG timer output pin

14 to 17 P32 to P35 E General-purpose I/O ports

A10 to A13 Output pins for external address buses A10 to A13

Circuit

type

This port is available in the single-chip mode or when the middle address control register setting is “port”, with the 8-bit PPG output is disabled.

This pin is available in an external-bus mode and when the middle address control register setting is “address.”

This pin is available when the PPG operation mode control register specification is the PPG output pin.

These ports are available in the single-chip mode or when the middle address control register setting is “port”, with the 16-bit reload timer 1 (ch.0 to ch.3) output is disabled.

These pins are available in an external-bus mode and when the middle address control register setting is “address.”

Function

TOUT0 to TOUT3 16-bit reload timer 1 (ch.0 to ch.3) output pin

These pins are available when the 16-bit reload timer 1 (ch.0 to ch.3) is output operation.

18 P36 E General-purpose I/O port

This port is available when the UART (ch.2) clock output is disabled either in the single-chip mode or when the middle address control register setting is “port.”

A14 Output pin for external address bus A14

This pin is available when the UART (ch.2) clock output is disabled in an external-bus mode and when the middle address control register setting is “address.”

SCK3 UART (ch.2) clock output pin (SCK3)

This pin is available when the UART (ch.2) clock output is enabled. UART (ch.2) external clock input pin (SCK3) This pin is available when the port is in input mode and the UART (ch.2) specification is external clock mode.

19 P37 E General-purpose I/O port

This port is available in the single-chip mode or when the middle address control register setting is “port.”

A15 Output pin for external address bus A15

This pin is available in an external-bus mode and when middle address control register setting is “address.”

SID3 UART (ch.2) serial data input pin (SID3)

* :FPT-80P-M06, FPT-80C-C02

Since this input is used whenever the SID3 is in input operation, the output by any other function must be suspended unless the output is intentionally performed.

(Continued)

Pin no.

Pin name

QFP*

20 P40 E General-purpose I/O port

A16 Output pin for external address bus A16

SOD3 UART (ch.2) serial data output pin (SOD3)

21 P41 E General-purpose I/O port

A17 Output pin for external address bus A17

SCK2 UART (ch.2) clock output pin (SCK2)

Circuit

type

This port is available when the UART (ch.2) serial data output from SOD3 is disabled either in the single-chip mode or when the upper address control register setting is “port.”

This pin is available when the UART (ch.2) serial data output from SOD3 is disabled in an external-bus mode and when the upper address control register setting is “address.”

This pin is available when the UART (ch.2) serial data output is enabled.

This port is available when the UART (ch.2) clock output is disabled either in the single-chip mode or when the upper address control register setting is “port.”

This pin is available when the UART (ch.2) clock output is disabled in an external-bus mode and when the upper address control register setting is “address.”

This pin is available when the UART (ch.2) clock output is enabled. UART (ch.2) external clock input pin (SCK2) This pin is available when the port is in input mode and the UART (ch.2) specification is external clock mode.

MB90210 Series

Function

22 P42 E General-purpose I/O port

This port is available in the single-chip mode or when the upper address control register setting is “port.”

A18 Output pin for external address bus A18

This pin is available in an external-bus mode and when the upper address control register setting is “address.”

SID2 UART (ch.2) serial data input pin (SID2)

Since this input is used whenever the SID2 is in input operation, the output by any other function must be suspended unless the output is intentionally performed.

23 P43 E General-purpose I/O port

This port is available when the UART (ch.2) serial data output from SOD2 is disabled either in the single-chip mode or when the upper address control register setting is “port.”

A19 Output pin for external address bus A19

This pin is available when the UART (ch.2) serial data output from SOD2 is disabled in an external-bus mode and when the upper address control register setting is “address.”

SOD2 UART (ch.2) serial data output pin (SOD2)

This pin is available when the UART (ch.2) serial data output from SOD2 is enabled.

* :FPT-80P-M06, FPT-80C-C02

(Continued)

MB90210 Series

Pin no.

Pin name

QFP*

24 PWC0 E PWC timer input pin

POUT0 PWC timer output pin

25 P45 E General-purpose I/O port

A21 Output pin for external address bus A21

PWC1 PWC timer data sample input pin

POUT1 PWC timer output pin

26 P46 E General-purpose I/O port

A22 Output pin for external address bus A22

PWC2 PWC timer input pin

POUT2 PWC timer output pin

27 P47 E General-purpose I/O port

A23 Output pin for external address bus A23

PWC3 PWC timer input pin

POUT3 PWC timer output pin

Circuit

type

Since this input is used whenever the PWC0 timer is in input operation, the output by any other function must be suspended unless the output is intentionally performed.

This pin is available when the PWC0 is output operation.

This port is available in the single-chip mode or when the upper address control register setting is “port.”

This pin is available in an external-bus mode and when the upper address control register setting is “address.”

Since this input is used whenever the PWC1 timer is in input operation, the output by any other function must be suspended unless the output is intentionally performed.

This pin is available when the PWC1 is output operation.

This port is available in the single-chip mode or when the upper address control register setting is “port.”

This pin is available in an external-bus mode and when the upper address control register setting is “address.”

Since this input is used whenever the PWC2 timer is in input operation, the output by any other function must be suspended unless the output is intentionally performed.

This pin is available when the PWC2 is output operation.

This port is available in the single-chip mode or when the upper address control register setting is “port.”

This pin is available in an external-bus mode and when the upper address control register setting is “address.”

Since this input is used whenever the PWC3 timer is in input operation, the output by any other function must be suspended unless the output is intentionally performed.

This pin is available when the PWC3 is output operation.

Function

* :FPT-80P-M06, FPT-80C-C02

(Continued)

Pin no.

Pin name

QFP*

54 P50 E General-purpose I/O port

CLK CLK output pin

55 P51 E General-purpose I/O port

RDY Ready signal input pin

56 P52 E General-purpose I/O port

Circuit

type

This port is available in the single-chip mode and when the CLK output is disabled.

This pin is available in an external-bus mode with the CLK output enabled.

This port is available in the single-chip mode or when the ready function is disable.

This pin is available in an external-bus mode and when the ready function is enabled.

This port is available in the single-chip mode or when the hold function is disabled.

MB90210 Series

Function

HAK

57 P53 E General-purpose I/O port

HRQ Hold request input pin

58 P54 D General-purpose I/O port

CTS0 UART (ch.0) clear-to-send input pin

Hold acknowledge output pin This pin is available in an external-bus mode and when the hold

function is enabled.

This port is available in the single-chip mode or when the hold function is disabled in an external-bus mode.

This pin is available in an external-bus mode and when the hold function is enabled. Since this input is used during this operation at any time, the output by any other function must be suspended unless the output is intentionally performed.

This port is available in the single-chip mode, in the external bus 8-bit mode, or when the WRH When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to V level to use these pins in input mode.

Since this input is used whenever the UART (ch.0) CTS function is enabled, the output by any other function must be suspended unless the output is intentionally performed. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to V level to use these pins in input mode.

pin output is disabled.

CC/VSS

WRH

* :FPT-80P-M06, FPT-80C-C02

Write strobe output pin for the upper eight bits of data bus This pin is available in the external bus 16-bit mode with the WRH

pin output enabled in an external-bus mode.

(Continued)

MB90210 Series

Pin no.

Pin name

QFP*

58 INT3 D External interrupt request input pin

59 P55 E General-purpose I/O port

Circuit

type

Since this input is used whenever external interrupts are enabled, the output by any other function must be suspended unless the output is intentionally performed. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to V level to use these pins in input mode.

This port is available in the single-chip mode or when the WRL pin output is disabled.

Function

CC/VSS

WRL

Write strobe output pin for the lower eight bits of data bus This pin is available in an external-bus mode and when the WRL pin output is enabled.

60 P56 E General-purpose I/O port

This port is available in the single-chip mode.

Data bus read strobe output pin This pin is available in an external-bus mode.

61 P57 D General-purpose I/O port

This port is always available. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to V level to use these pins in input mode.

RAM write disable request input Since this input is used during this operation at any time, the output by any other function must be suspended unless the output is intentionally performed. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to V level to use these pins in input mode.

32, 33,

35 to 40

P60, P61, P62 to P67

AN0, AN1, AN2 to AN7

C Open-drain I/O ports

These ports are available when the analog input enable register setting is “port.”

10-bit A/D converter analog input pins These pins are available when the analog input enable register

setting is “analog input.”

CC/VSS

41 to 43 MD0 to MD2 F Operation mode select signal input pins

Connect these pins directly to V

44 HST

G Hardware standby input pin

45 P70 E General-purpose I/O port

This port is available when the UART (ch.1) clock output is disabled.

* :FPT-80P-M06, FPT-80C-C02

CC or VSS.

(Continued)

Pin no.

Pin name

QFP*

45 SCK1 E UART (ch.1) clock output pin

46 P71 E General-purpose I/O port

SID1 UART (ch.1) serial data input pin

47 P72 E General-purpose I/O port

Circuit

type

This pin is available when the UART (ch.1) clock output is enabled. UART (ch.1) external clock input pin This pin is available when the port is in input mode and the UART (ch.1) specification is external clock mode.

This port is always available.

Since this input is used whenever the UART (ch.1) is in input operation, the output by any other function must be suspended unless the output is intentionally performed.

This port is available when the UART (ch.1) serial data output is disabled.

MB90210 Series

Function

SOD1 UART (ch.1) serial data output pin

This pin is available when the UART (ch.1) serial data output is enabled.

48 P73 E General-purpose I/O port

This port is available when the UART (ch.0) clock output is disabled.

SCK0 UART (ch.0) clock output pin

This pin is available when the UART (ch.0) clock output is enabled. UART (ch.0) external clock input pin This pin is available when the port is in input mode and the UART (ch.0) specification is external clock mode.

49 P74 E General-purpose I/O port

This port is always available.

SID0 UART (ch.0) serial data input pin

Since this input is used whenever the UART (ch.0) is in input operation, the output by any other function must be suspended unless the output is intentionally performed.

50 P75 E General-purpose I/O port

This port is available when the UART (ch.0) serial data output is disabled.

SOD0 UART (ch.0) serial data output pin

This pin is available when the UART (ch.0) serial data output is enabled.

51,

P80, P81

D General-purpose I/O port

This port is always available. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to V level to use these pins in input mode.

CC/VSS

* :FPT-80P-M06, FPT-80C-C02

(Continued)

MB90210 Series

(Continued)

Pin no.

QFP*

51,

Pin name

INT0, INT1

Circuit

type

D External interrupt request input pin

53 P82 D General-purpose I/O port

This port is always available. When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to V level to use these pins in input mode.

INT2 External interrupt request input pin

ATG

10-bit A/D converter trigger input pin When these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to V level to use these pins in input mode.

28 AV

Power supply

Analog circuit power supply pin This power supply must be turned on or off with a potential equal to or higher than AV

29 AVRH

Power supply

Be sure that AV Analog circuit reference voltage input pin

CC= VCC before use and during operation.

This pins must be turned on or off with a potential equal to or

higher than AVRH applied to AV 30 AVRL 31 AV

Power supply Power supply

Analog circuit reference voltage input pin

Analog circuit grounding level

Function

CC/VSS

CC applied to VCC.

CC.

* :FPT-80P-M06, FPT-80C-C02

MB90210 Series

■ I/O CIRCUIT TYPE

Type Circuit Remarks

A • Oscillation feedback resistor: Approx.1 MΩ

MB90214 MB90P214B

Standby control

MB90W214B

• Oscillation feedback resistor: Approx.1 MΩ MB90P214A MB90W214A

Standby control

B • CMOS-level I/O

Digital output

Standby control provided MB90214: With or without pull-up/pull-down

reisistor optional

Digital output

Digital input

MB90P214A/P214B: Without pull-up/pull-down

resistor

MB90W214A/W214B: Without pull-up/pull-down

resistor

Standby control

C • N-ch open-drain output

• CMOS-level hysteresis input A/D control provided

Digital output

A/D input Digital input

D • CMOS-level output

Digital output

• CMOS-level hysteresis input Standby control not provided MB90214: With or without pull-up/pull-down

reisistor optional

Digital output

Digital input

MB90P214A/P214B: Without pull-up/pull-down

resistor

MB90W214A/W214B: Without pull-up/pull-down

resistor

(Continued)

MB90210 Series

(Continued)

Type Circuit Remarks

E • CMOS-level output

Digital output

Digital input

F • CMOS-level input with no standby control

Digital input

• CMOS-level hysteresis input Standby control provided MB90214: With or without pull-up/pull-down

reisistor optional

MB90P214A/P214B: Without pull-up/pull-down

resistor

MB90W214A/W214B: Without pull-up/pull-down

resistor

Mask ROM products only: MD2: With pull-down resistor MD1: With pull-up resistor MD0: With pull-down resistor

• COMS-level input with no standby control MD2 of OTPROM products/EPROM products

Digital input VPP power supply

only

G • CMOS-level hysteresis input

Standby control not provided

• With input analog filter (40 ns Typ.)

Analog filter

H • CMOS-level hysteresis input

Pull-up resistor

Digital input

Standby control not provided

• With input analog filter (40 ns Typ.)

• With pull-up resistor MB90214: With or without pull-up/pull-down

resistor optional

Analog filter

Digital input

MB90P214A/W214A/P 214B /W214 B:

With pull-up resistor

: P-type transistor

: N-type transistor

Note: The pull-up and pull-down resistors are always connected, regardless of the state.

MB90210 Series

■ HANDLING DEVICES

1. Preventing Latchup

CMOS ICs may c ause latch up when a voltag e higher t han VCC or lower th an VSS is appl ied to i nput or ou tput pins, or when a voltage exceeding the rating is applied between V

If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let any voltage exceed the maximum rating.

CC and VSS.

Also, take care to prevent the analog power supply (AV power supply (V

CC) when the analog system power supply is turned on and off.

CC and A VRH) and analog input from exceeding the digital

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor .

3. Treatment of Pins when A/D is not Used

Connect to be AVCC = AVRH = VCC and AVSS = AVRL = VSS even if the A/D converter is not in use.

4. Precautions when Using an External Clock

To reset the internal c ircuit properly by the Lo w-level input to the RST pin , the “L” level input to th e RST pin must be maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.

5. VCC and VSS Pins

Apply equal potential to the VCC and VSS pins.

6. Supply Voltage Variation

The operation assurance range for the VCC supply voltage is as given in the ratings. Howev er, sudden changes in the supply voltage can cause miso peration, even if the voltage remains within the rated range. Therefore, it is impor tant to su pply a stable voltage to t he IC. The recommende d power supply co ntrol guideli nes are that the commercial frequency (50 to 6 0 Hz) ripple var iation (P-P value) on V standard V

CC value and that the transient rate of change during sudden changes, such as during power supply

switching, should be less than 0.1 V/ms.

CC should be less than 10% of the

7. Notes on Using an External Clock

When using an external clock, drive the X0 pin as illustrated below. When an external clock is used, oscillation stabilization time is required even for power-on reset and wake-up from stop mode.

• Use of External Clock

MB90210

Note: When using an external clock, be sure to input external clock more than 6 machine cycles after

setting the HST pin to “L” to transfer to the hardware standby mode.

MB90210 Series

8. Power-on Sequence for A/D Converter Power Supplies and Analog Inputs

Be sure to turn on the digital power supply (VCC) before applying voltage to the A/D conver ter power supplies (AV

CC, AVRH, and AVRL) and analog inputs (AN0 to AN7).

When turning power supplies off, turn off the A/D converter power supplies (A V inputs (AN0 to AN7) first, then the digital power supply (V

When turning AVRH on or off, be careful not to let it exceed AV

CC).

CC.

CC, A VRH, and A VRL) and analog

MB90210 Series

■ PROGRAMMING FOR MB90P214A/P214B/W214A/W214B

In EPROM mode, the MB9 0P214A/P214B/W214A/W214B func tions equivalent to the MBM27C1000. This allows the EPROM to be programmed with a general-pur pose EPROM programmer by using the dedicated socket adapter (do not use the electronic signature mode).

1. Program Mode

When shipped from Fujitsu, an d after eac h erasure, all bits (64 K × 8 bits) in the MB9 0P214A /P214 B/W214 A/ W214B are in the “1” sta te. Data is written to the ROM by selectively programming “0’s” into the desired bit locations. Bits cannot be set to “1” electrically.

2. Programming Procedure

(1) Set the EPROM programmer to MBM27C1000. (2) Load program data into the EPROM programmer at 10000

H to 1FFFFH.

Note that ROM addresses FF0000 W214B series assign to 10000

FFFFFFH

FF0000

Operation mode EPROM mode

* : Be sure to set the programming, the start address and the stop address on the EPROM programmer to 10000H/1FFFFH.

H to FFFFFFH in the operation mode in the MB90P214A/P214B/W214A/

H to 1FFFFH in the EPROM mode (on the EPROM programmer).

1FFFF

10000H*

(Corresponding addresses on the EPROM mode)

(3) Mount the MB90P214A/P214B/W214A/W214B on the adapter socket, then fit the adapter socket onto the

EPROM programmer. When mounting the device and the adapter socket, pay attention to their mounting

orientations. (4) Start programming the program data to the device. (5) If programming has not successfully resulted, connect a capacitor of approx. 0.1 µF between V

between V

PP and GND.

CC and GND,

(6) Since the MB90P214A and MB90W214A have CMOS-level input, programming to them may be impossible

depending on the output level of the general-purpose programmer. In that case, connect a pull-up resistor

to the adapter socket side.

Note: The mask ROM products (MB90214) d oes not sup por t EPROM mo de. Data cannot , therefore, be read by

the EPROM programmer.

MB90210 Series

3. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer

Part No. MB90P214B Package QFP-80 Compatible socket adapter

Sun Hayato Co., Ltd. Recommended

programmer manufacturer and programmer name

Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403

Advantest Corp.: TEL: Except JAPAN (81)-3-3930-4111

Advantest corp.

FAX: (81)-3-5 3 96-9106

R4945A

(main unit)

R49451A (adapter)

ROM-80QF-32DP-16F

Recommended

4. Erase Procedure

Data written in the MB90W214A/W214B are erased (from “0” to “1”) by exposing the chip to ultraviolet rays with a wavelength of 2,537 Å through the translucent cover.

Recommended irradiati on dosage for exposure is 10 Wsec/cm with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface illuminance is 1200 µW/cm

If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the la mp increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent par t of the package is stained with oil o r adhesive, transmiss ion of ultraviolet rays is de graded, resulting in a longer erasure time. In that case, clean the t ranslucent part usi ng alcohol (or other solvent not affecting the package).

. This amount is reached in 15 to 20 mi nutes

The above recommended dosage is a value which takes the guard band into consideration and is a multiple of the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure; the purpo se of the guard band is to ensure erasur e in all temperature and supply voltage ranges. In addition, check the life span of the lamp and control the illuminance appropriately.

Data in the MB90W214A/W214B are erased by exposure to light with a wavelength of 4000 Å or less. Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure

results in a much lower erasure rate than exposure to 2537 Å ultraviolet rays. Note that ex posure to such lights for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light with a wavelength of 4000 Å or less, cover the translucent part, for example, with a protective seal to prevent the chip from being exposed to the light.

Exposure to light with a wavelength of 4,000 to 5,000 Å or more will not erase data in the device. If the light applied to the chip has a ver y high illuminance, however, the device may cause malfunction in the circuit for reasons of general semiconductor characteristics. Although the circuit will recover normal operation when exposure is stopped, the device require s proper co unter meas ures for use in a place exposed continuously to such light even though the wavelength is 4,000 Å or more.

MB90210 Series

5. Recommended Screening Conditions

High temperature aging is recommended as the pre-assembly screening procedure.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

6. Programming Yeild

MB90P214A/P214B cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always be guaranteed to be 100%.

7. Pin Assignment in EPROM Mode

(1) Pins compatible with MBM27C1000

MBM27C1000

MB90P214A, MB90P214B,

MB90W214A, MB90W214B

MBM27C1000

Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name

PP 43 MD2 (VPP)32 VCC

2 OE 59 P55 31 PGM 60 P56 3A1519P37 30N.C. 4 A12 16 P34 29 A14 18 P36 5 A07 10 P27 28 A13 17 P35 6 A06 9 P26 27 A08 12 P30 7 A05 8 P25 26 A09 13 P31 8 A04 7 P24 25 A11 15 P33

9 A03 6 P23 24 A16 20 P40 10 A02 5 P22 2 3 A10 14 P32 11 A01 4 P21 2 2 CE 58 P54 12 A00 3 P20 2 1 D07 74 P07 13 D00 67 P00 20 D06 73 P06

MB90P214A, MB90P214B,

MB90W214A, MB90W214B

14 D01 68 P01 19 D05 72 P05 15 D02 69 P02 18 D04 71 P04 16 GND 17 D03 70 P03

MB90210 Series

(2) Power supply and ground connection pins

Type Pin no. Pin name

Power supply 41

42 44 66

MD0 MD1 HST VCC

GND 11

30 31 34 56 57 62 63

(3) Pins other than MBM27C1000-compatible pins

Pin no. Pin name Treatment

64 X0 Pull up to 4.7 kΩ. 65 X1 Open

1 2

to 27 28 29 32 33 35

to 40 45

to 50 51 to 53 54 55 61 75

to 80

P16 P17 P41 to P47 AV

AVRH P60 P61 P62 to P67 P70 to P75 P80 to P82 P50 P51 P57 P10 to P15

Connect a pull-up resistor of approximately 1 MΩ to each pin.

AVRL

AV VSS P52 P53 RST VSS

■ BLOCK DIAGRAM

X1 X0 RST HST MD2 MD1 MD0

CTS0 SCK3 SID3 SOD3 SCK2 SID2 SOD2 SCK1 SID1 SOD1 SCK0 SID0 SOD0

TOUT0 to TOUT3 TIN0 to TIN3

Clock controller

Write-inhibit

RAM

UART × 3

16-bit timer 1 × 4

PWC timer

× 4

Internal data bus

DTP/External interrupt

× 4

External bus interface

MC-16F

CPU

MB90210 Series

PWC0 to PWC3 /POUT0 to POUT3

INT0 to INT3

D00 to D15 A00 to A23 CLK RDY

HAK HRQ WRH WRL RD

TIN4 to TIN7

ATG AN0 to AN7 AV

AVRH AVRL AVSS

P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P75 P80 to P82

PPG

16-bit timer 2 × 4

10-bit A/D converter 8 ch.

8-bit

I/O port

PPG timer

8-bit

8-bit PPG timer

PPG timer

RAM

ROM

MB90210 Series

■ PROGRAMMING MODEL

Dedicated Registers

USP SSP PS

PC USPCU SSPCU USPCL SSPCL

DPR

PCB DTB USB SSB ADB

Accumulator

User stack pointer System stack pointer Processor status Program counter User stack upper register System stack upper register User stack lower register System stack lower register

Direct page register

Program bank register Data bank register User stack bank register System stack bank register Additional data bank register

General-purpose Registers

000180

Processor Status (PS)

ILM

Upper

Lower

H + RP × 10H

32 bits

16 bits

R 7 R 5 R 3 R 1

MSB LSB

—

8 bits

Max.32 banks

R 6 R 4 R 2

R 0 RW3 RW 2 RW 1 RW 0

16 bits

ISTNZVC

RW 7 RW 6 RW 5

RW 4

RL 3

RL 2

RL 1

RL 0

C C R

■ MEMORY MAP

MB90210 Series

FFFFFF

Address #1

010000H

Address #2

Address #3 Address #4

Single chip

ROM area ROM area

ROM area

FF bank

image

Internal ROM and external bus

ROM area

FF bank

image

External ROM and external bus

Address #5

Address #6 000380H

000180H 000100H

0000C0H

000000H

Type

Write-inhibit RAM

RAM

Peripherals

Registers

Address #1 Address #2 Address #3 Address #4 Address #5 Address #6

Write-inhibit RAM Write-inhibit RAM

RAM RAM

Registers Registers

Peripherals Peripherals

: Internal

: External

: No access

MB90214 FF0000H 004000H 001300H 001200H 001100H 000D00H MB90P214A/P214B

MB90W214A/W214B

FF0000

H 004000H 001300H 001200H 001100H 001100H

MB90V210 (FE0000H) 004000H 001300H 001300H 001100H 001100H

MB90210 Series

■ I/O MAP

Address Register

Port 0 data register PDR0 R/W

000000 000001 000002 000003 000004 000005 000006 000007 000008 000009

Port 1 data register PDR1 R/W

Port 2 data register PDR2 R/W

Port 3 data register PDR3 R/W

Port 4 data register PDR4 R/W

Port 5 data register PDR5 R/W

H Port 6 data r egister PDR6 R/W Port 6 11111111 H Port 7 data register PDR7 R/W Port 7 ––XXXXXX H Port 8 data register PDR8 R/W Port 8 –––––XXX

to 0FH

000010H 000011 000012 000013 000014 000015 000016

Port 0 data direction register DDR0 R/W

Port1 data direction register DDR1 R/W

Port 2 data direction register DDR2 R/W

Port 3 data direction register DDR3 R/W

Port 4 data direction register DDR4 R/W

Port 5 data direction register DDR5 R/W

H Analog input enable register ADER R/W Port 6 11111111

name

Access

(Reserved area) *

Resource

name

Initial value

Port 0 XXXXXXXX Port 1 XXXXXXXX Port 2 XXXXXXXX Port 3 XXXXXXXX Port 4 XXXXXXXX Port 5 XXXXXXXX

Port 0 00000000 Port 1 00000000 Port 2 00000000 Port 3 00000000 Port 4 00000000 Port 5 00000000

000017 000018 000019

H Port 7 data direction register DDR7 R/W Port 7 ––000000 H Port 8 data direction register DDR8 R/W Port 8 – ––––000

to 1FH

(Reserved area) *

000020H Mode control register 0 UMC0 R/W UART (ch.0) 00000100 000021

000022 000023

000024 000025

000026 000027

H Status register 0 USR0 R/W 00010000

Input data register 0/output data

H Rate and data register 0 URD0 R/W 00000000 H Mode control register 1 UMC1 R/W UART (ch.1) 00000100 H Status register 1 USR1 R/W 00010000

Input data register 1/output data

H Rate and data register 1 URD1 R/W 00000000

UIDR0/

UODR0

UIDR1/

UODR1

R/W

XXXXXXXX

(Continued)

Address Register

name

MB90210 Series

Access

Resource

name

Initial value

000028

000029 00002A 00002B

00002C 00002D

H Mode control register 2 UMC2 R/W UART (ch.2) 00000100 H Status register 2 USR2 R/W 00010000

Input data register 2/output data

H Rate and data register 2 URD2 R/W 00000000 H UART redirect control register URDR R/W UART (ch.0/2) –––0 0000

to 2FH

UIDR2/

UODR2

(Reserved area) *

R/W XXXXXXXX

000030H Interrupt/DTP enable register ENIR R/W DTP/external

000031

000032

000033

H Interrupt/DTP factor register EIRR R/W ––––0000 H Reque st level setting register ELVR R/W 00000000

(Reserved area) *

interrupt

000034H AD control status register ADCS R/W 10-bit A/D

000035

000036

to 37H

000038

to 39H

00003A

to 3BH

H 00000000

AD data register ADCD R/W

Timer control status register 0 TMCSR0 R/W 16-bit reload

Timer control status register 1 TMCSR1 R/W 16-bit reload

converter

timer 1 (ch.0)

timer 1 (ch.1)

––––0000

00000000

XXXXXXXX 0–––––XX

00000000 ––––0000

00003C

to 3DH

00003E

to 3FH 000040 000041 000042 000043 000044 000045 000046 000047

Timer control status register 2 TMCSR2 R/W 16-bit reload

timer 1 (ch.2)

Timer control status register 3 TMCSR3 R/W 16-bit reload

timer 1 (ch.3)

H Timer 0 timer register TMR0 R 16-bit reload H XXXXXXXX H Timer 0 reload register TMRLR0 W XXXXXXXX H XXXXXXXX H Timer 1 timer register TMR1 R 16-bit reload H XXXXXXXX H Timer 1 reload register TMRLR1 W XXXXXXXX H XXXXXXXX

timer 1 (ch.0)

timer 1 (ch.1)

00000000 ––––0000

XXXXXXXX

(Continued)

MB90210 Series

Address Register

name

Access

Resource

name

Initial value

000048 000049

00004A 00004B 00004C 00004D 00004E

00004F 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059

00005A

H Timer 2 timer register TMR2 R 16-bit reload H XXXXXXXX H Timer 2 reload register TMRLR2 W XXXXXXXX H XXXXXXXX H Timer 3 timer register TMR3 R 16-bit reload H XXXXXXXX H Timer 3 reload register TMRLR3 W XXXXXXXX H XXXXXXXX H Timer 4 timer register TMR4 R 16-bit reload H XXXXXXXX H Timer 4 reload register TMRLR4 W XXXXXXXX H XXXXXXXX H Timer 5 timer register TMR5 R 16-bit reload H XXXXXXXX H Timer 5 reload register TMRLR5 W XXXXXXXX H XXXXXXXX H Timer 6 timer register TMR6 R 16-bit reload H XXXXXXXX H Timer 6 reload register TMRLR6 W XXXXXXXX

timer 1 (ch.2)

timer 1 (ch.3)

timer 2 (ch.4)

timer 2 (ch.5)

timer 2 (ch.6)

XXXXXXXX

00005B 00005C 00005D 00005E

00005F 000060 000061 000062H 000063 000064H 000065

H XXXXXXXX H Timer 7 timer register TMR7 R 16-bit reload H XXXXXXXX H Timer 7 reload register TMRLR7 W XXXXXXXX H XXXXXXXX

Timer control status register 4 TMCSR4 R/W 16-bit reload

(Reserved area) *

timer 2 (ch.7)

timer 2 (ch.4)

Timer control status register 5 TMCSR5 R/W 16-bit reload

timer 2 (ch.5)

(Reserved area) *

Timer control status register 6 TMCSR6 R/W 16-bit reload

timer 2 (ch.6)

(Reserved area) *

XXXXXXXX

00000000

(Continued)

Address Register

name

MB90210 Series

Access

Resource

name

Initial value

000066 000067 000068H

000069 00006AH 00006B 00006CH 00006D 00006EH

00006F

Timer control status register 7 TMCSR7 R/W 16-bit reload

(Reserved area) *

PWC0 divide ratio register DIVR0 R/W PWC timer

(Reserved area) *

PWC1 divide ratio register DIVR1 R/W PWC timer

(Reserved area) *

PWC2 divide ratio register DIVR2 R/W PWC timer

(Reserved area) *

PWC3 divide ratio register DIVR3 R/W PWC timer

(Reserved area) *

timer 2 (ch.7)

(ch.0)

(ch.1)

(ch.2)

(ch.3)

000070H PWC0 control status register PWCSR0 R/W PWC timer

000071

000072

000073

H 00000000 H PWC0 data buffer register PWCR0 R/W 00000000 H 00000000

(ch.0)

00000000

––––––00

00000000

000074

000075

000076

000077

000078

000079 00007A 00007B 00007C 00007D 00007E

00007F

000080

H PWC1 control status register PWCSR1 R/W PWC timer H 00000000 H PWC1 data buffer register PWCR1 R/W 00000000 H 00000000 H PWC2 control status register PWCSR2 R/W PWC timer H 00000000 H PWC2 data buffer register PWCR2 R/W 00000000 H 00000000 H PWC3 control status register PWCSR3 R/W PWC timer H 00000000 H PWC3 data buffer register PWCR3 R/W 00000000 H 00000000

to 87H

(Reserved area) *

(ch.1)

(ch.2)

(ch.3)

00000000

000088H PPG operation mode control register PPGC R/W 8-bit PPG timer 00000––1

000089

(Reserved area) *

(Continued)

MB90210 Series

Address Register

name

Access

Resource

name

Initial value

00008A 00008B 00008C

00008EH WI control register WICR R/W

00008F

00009FH

H PPG reload register PRL R/W 8-bit PPG timer XXXXXXXX H XXXXXXXX

to 8DH

(Reserved area) *

Write-inhibit RAM

to 9EH

Delayed interrupt source generate/ release register

(Reserved area) *

DIRR R/W

Delayed interrupt generation module

–––X––––

–––––––0

Standby control register STBYC R/W Low-power

0000A0

consumption

0001∗∗∗∗

mode

to A2H

(Reserved area) *

0000A1

0000A3H Middle address control register MACR W External pin ######## 0000A4 0000A5 0000A6

H Upper address control regist er HACR W ######## H External pin control register EPCR W ##0–0#00

to A7H

(Reserved area) *

0000A8H Watchdog timer control register WTC R/W Watchdog timer XXXXXXXX 0000A9

0000AA

H Timebase timer control register TBTC R/W Timebase timer 1––00000

to AFH

(Reserved area) *

0000B0H Interrupt control register 00 ICR00 R/W Interrupt 0000B1 0000B2 0000B3 0000B4 0000B5 0000B6 0000B7 0000B8 0000B9

H Interrupt control register 01 ICR01 R/W 00000111 H Interrupt control register 02 ICR02 R/W 00000111 H Interrupt control register 03 ICR03 R/W 00000111 H Interrupt control register 04 ICR04 R/W 00000111 H Interrupt control register 05 ICR05 R/W 00000111 H Interrupt control register 06 ICR06 R/W 00000111 H Interrupt control register 07 ICR07 R/W 00000111 H Interrupt control register 08 ICR08 R/W 00000111 H Interrupt control register 09 ICR09 R/W 00000111

controller

00000111

(Continued)

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