FUJITSU MB90099 DATA SHEET

查询MB90099供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP For Screen Display Control

CMOS

On-Screen Display Controller

MB90099

DESCRIPTION

■

The MB90099 is an on-screen display controller for displaying text and graphics on the TV screen. The three­channel output control function, compact package and low vo ltage operation make this device suitable for on­screen displays in portable devices including camera-integrated VTRs and digital still cameras.

DS04-28828-3E

The MB90099 controls a display area of 28 characters b y 12 lines, and provides 1,024 diff erent char acters, each
composed of 12 × 18 dots. All 1,024 characters in font R OM can be set b y the user . The displa y functions include
a wealth of characters with qualifying functions such as character background shading (shadow casting) and
individual character size setting, with 16-color display selection for each character. Also included are the line
background, screen background, and sprite character functions, pro viding a wide v ariety of screen displa y capa­bilities.

FEATURES

■

• Character screen
configuration :

• Character types : 1,024 characters (integrated in ROM, user definable through the entire area)

PACKAGE

■

28 characters × 12 lines (maximum)

(Continued)

20-pin plastic SSOP 20-pin plastic FLGA

(FPT-20P-M03) (LGA-20P-M01)

MB90099

(Continued)

• Font configuration : 12 × 18 dots (font ROM comfiguration)
Horizontal/vertical character display size setting enabled.

Two horizontal width settings (S/L) per character.

S size : 6 dots
L size : 12 dots

Two vertical height settings (HA/HB) per line.

HA : 18 dots
HB : 12 dots

• Display modes : Character trimming : Enabled/Disabled (set for each line)
Character background :

None/Solid-fill/Shaded background (concave) /Shaded background (convex)
(set for each character)

Horizontal character merge/independent display with shaded bac kground (set f or
each character)

V ertical line merge/independent display with shaded background (set for each line)
Character background displa y extended to line spacings : Enabled/Disabled (set f or

each line)

• Character screen

display position
control :

• Sprite character

control :

Line background :

None/Solid-fill/Shaded background (concave) /Shaded background (convex)
(set for each line)
(Display extends into left and right screen margins and into line spacings)

Character enlargement :

4 types : Normal, Double width, Double height, Double width × double height (set
for each line)
Enlarged character dot interpolation function (set for each line)

Horizontal display position :

Control in 2-dot units (movable through the entire screen)

Vertical display position :

Control in 2-dot units (movable through the entire screen)

Line spacing control :

Control in 1-dot units (set between 0 to 7 dots for each line, applied simultaneously
to two areas above and below the line)

Sprite character display : Enable/Disabled
Sprite character types : 256 types (character codes 000
Sprite character trimming : Enabled/Disabled
Sprite character configuration : 2 types : 1 character/Stack of 2 characters
Sprite character horizontal display position : Control in 1-dot units (mov ab le through

the entire screen)

to 0FFH)

H

• Screen background

control :

2

Sprite character vertical display position : Control in 1-dot units (movable through
the entire screen)

Screen background color : Enabled/Disabled

• Display colors : Character color : 16 colors (set for each character)
Character trimming color : 16 colors (set for each line)
Character background color : 16 colors (set for each character) *
Line background color : 16 colors (set for each line)
Screen background color : 16 colors
Sprite character color : 16 colors
Sprite character trimming color : 16 colors
Shaded background frame highlight color : 16 colors
Shaded background frame shadow color : 16 colors

• Display signal

output :

• External interface : 16-bit serial input :

• Package : SSOP-20

• Supply voltage : 2.4 V to 3.6 V

Color signal output : 4 bits (supports 16 colors)
Display period signals : 3 channels (output selector circuit provided)

Chip select
Serial clock
Serial data

FLGA-20

MB90099

* : Character background color (color code) = “0” is transparent (displays lower-layer color) .

3

MB90099

PIN ASSIGNMENTS

■

(TOP VIEW)

SCLK

CS

SIN

RESET

V

DD

SDR

N.C.

EXD

TEST

GND

SIN

1
2

3
4

5
6

7
8
9

10

20
19
18
17
16
15
14
13
12
11

SSOP-20

(FPT-20P-M03)

(TOP VIEW)

CS

HSYNC

SCLK

A2 A3 A4 A5

B1 B6

VSYNC

HSYNC
VSYNC
VC0

VC1
VC2
BLKA
VC3
BLKB
TESTO
BLKC

VC0

RESET

V

DD

SDR

N.C.

EXD

C1 C6
D1 D6
E1 E6
F1 F6
G1 G6

H2 H3 H4 H5

TEST

GND

BLKC

TESTO

FLGA-20

(LGA-20P-M01)

VC1
VC2
BLKA
VC3
BLKB

4

PIN DESCRIPTIONS

■

MB90099

Pin no.

SSOP FLGA

1A3SCLK I A

2A2 CS
3 B1 SIN I A Serial data input pin. This pin has an internal pull-up resistor.

4 C1 RESET
5D1 V

6E1SDR I C

7F1N.C. Not connected. This pin should be left open.
8 G1 EXD I B Display dot clock input pin.

9 H2 TEST I C LSI test input pin. Input a low level signal during normal use.
10 H3 GND Ground pin.
11 H4 BLKC O D Display period signal output pin for output channel C.
12 H5 TESTO O D LSI test output pin. This pin should be left open during normal use.
13 G6 BLKB O D Display period signal output pin for output channel B.

Pin name I/O

DD

+3 V power supply pin.

Circuit

type

Shift clock input pin for serial transfer. This pin has an internal pull­up resistor.

IA

I B Reset input pin. Input a low level signal at power-on time.

Chip select pin. Input a low level signal during serial transfer. This
pin has an internal pull-up resistor.

Data input direction select pin for serial transfer. Input a low level
signal at LSB-first transfer mode, or a high level signal at MSB-first
transfer mode.

Function

15 E6 BLKA O D Display period signal output pin for output channel A.
14

16
17
18

19 A5 VSYNC
20 A4 HSYNC I B Horizontal synchronization signal input pin.

F6
D6
C6
B6

VC3
VC2
VC1
VC0

O
O
O
O

I B Vertical synchronization signal input pin.

D Color code signal output pins.

5

MB90099

I/O CIRCUIT TYPES

■

Type Circuit Remarks

CMOS level, h ysteresis input, pull­up resistance

R

A

(25 kΩ to 200 kΩ) .

CMOS level, hysteresis input.

B

CMOS level input.

C

CMOS level output.

D

Output

6

BLOCK DIAGRAM

■

MB90099

SCLK
CS
SIN
SDR

EXD

HSYNC
VSYNC

Serial input control

Display control

Display
memory
(VRAM)

Font ROM

To controllers

Output
control

VC3
VC2
VC1
VC0
BLKC
BLKB
BLKA

TEST

RESET

Test control block

TESTO

7

MB90099

COMPONENT ELEMENTS

■

• Serial input control block
Receives serial commands and data. Decodes commands, and allocates commands and data to the appro­priate control blocks.

• Display control block
Performs display control functions synchronized with the input sync signals.

• Display memory (VRAM) block
VRAM memory for character data (24 bits × 28 characters × 12 lines) and line data (24 bits × 12 lines) .

•Font ROM block
ROM memory for display character fonts. Configured for 1,024 characters of 12 dots × 18 dots.

• Output control block
Generates output signals by applying display processing to the font data read from the font ROM.

• Test control block
Circuits for factory testing of the LSI before delivery.

8

ABSOLUTE MAXIMUM RATINGS

■

MB90099

(V

= 0 V)

GND

Parameter Symbol

Unit Remarks

Min. Max.

Rating

Power supply voltage V
Input voltage V
Output voltage V

DD

IN

OUT

V

− 0.5 V

GND

V

− 0.5 VDD + 0.5 V

GND

V

− 0.5 VDD + 0.5 V

GND

+ 4.0 V

GND

Power consumption Pd  100 mW
Operating temperature Ta −20 +70 °C
Storage temperature Tstg −55 +150 °C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

■

(V

= 0 V)

GND

Value

Parameter Symbol

Unit Remarks

Min. Max.

Power supply voltage V
“H” level input voltage 1 V
“L” level input voltage 1 V
“H” level input voltage 2 V

DD

IHS

ILS

IH

2.4 3.6 V

0.8 × V
V

GND

0.7 × V

DD

DD

VDD + 0.3 V *1

0.2 × V

DD

VDD + 0.3 V *2

V*1

“L” level input voltage 2 V

IL

V

GND

0.3 × V

DD

V*2

Operating temperature Ta −20 +70 °C

*1 : Input pins excluding TEST and SDR pins.
*2 : TEST and SDR input pins.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

9

MB90099

ELECTRICAL CHARACTERISTICS

■

1. DC Characteristics

(V

= 0 V, Ta = −20 °C to +70 °C)

GND

Parameter

“H” level output voltage V

Sym-

bol

OH

Pin name Conditions

VC3, VC2, VC1, VC0,
BLKC, BLKB, BLKA

“L” level output voltage V

“H” level input current I

OL

IH

SDR,
HSYNC
EXD, TEST,

“L” level input current I
Pull-up resistance R

Power supply current I

IL

RESET
SIN, SCLK, CS VDD = 3.3 V 25 50 200 kΩ

PULL

V

CC

DD

Input capacitance C Except V

Value

Min. Typ. Max.

= 3.3 V

V

DD

I

= −4 mA

OH

VDD = 3.3 V
I

= 4 mA

OL

VDD = 3.3 V
V

= V

IH

, VSYNC,

DD

VDD = 3.3 V
V

= 0 V

IL

VDD = 2.4 V
f

= 8 MHz

DC

V

= 3.6 V

DD

f

= 8 MHz

DC

, GND 16 pF

DD

− 0.5  V

V

DD

V

GND

 0.4 V

DD

+10 µA

−10 µA

 5mA

 6mA

Unit

V

10

2. AC Characteristics

(1) Serial input timings

(V

= 2.4 V to 3.6 V, V

DD

MB90099

= 0 V, Ta = −20 °C to +70 °C)

GND

Parameter Symbol Pin name

Shift clock cycle time t

t

Shift clock pulse width

Shift clock signal rise/fall time

Shift clock start time t
Data setup time t
Data hold time t
Chip select end time t

Chip select signal rise/fall time

CS

0.8 VDD

0.2 VDD

CYC

WCH

t

WCL

t
t

t

CRC

t

CFC

CR

CF

SS

SU

EC

Value

Unit

Min. Max.

SCLK 250  ns

100  ns

SCLK

100  ns

 200 ns

SCLK

 200 ns

SCLK 100  ns

100  ns

SIN

H

50  ns

CS 100  ns

 200 ns

CS

 200 ns

0.8 VDD

0.2 VDD

SCLK

SIN

tCFC

tSS

tCR tCR

tSU

tWCH

tCYC

tWCL

tCF

tH

0.8 VDD

0.2 VDD

tCRC

tEC

0.8 VDD

0.2 VDD

11

MB90099

(2) Vertical and horizontal sync signal input timing

(V

= 2.4 V to 3.6 V, V

DD

= 0 V, Ta = −20 °C to +70 °C)

GND

Parameter Symbol Pin name

Unit

Min. Max.

Value

Horizontal sync signal rise time t

HR

 200 ns

HSYNC

Horizontal sync signal fall time t
Vertical sync signal rise time t

HF

VR

 200 ns
 200 ns

VSYNC

Vertical sync signal fall time t

Horizontal sync signal pulse width *

1

VF

t

WH

HSYNC

 200 ns
18  Dot clock
 6 µs

Vertical sync signal setup time1 *
(Except for VVE = 1, VHE = 1, HE = 1) *

Vertical sync signal setup time2 *
(VVE = 1, VHE = 1, HE = 1) *

Vertical sync signal detection hold time t
Vertical sync signal pulse width t

2

3

2

3

t

t

VS

VS

VH

WV

VSYNC 41H − 4 Dot clock

VSYNC − 61H − 14 Dot clock
VSYNC 2  H

VSYNC 220H

*1 : During the horizontal sync signal pulse period, the MB90099 stops its internal operation, disabling writing to the

internal VRAM. Therefore, the horizontal sync signal pulse width and VRAM write cycle (command 2 or command
4 issuance cycle) should be set so that the horizontal sync signal pulse width is shorter than the VRAM write cycle.

*2 : In the vertical sync signal detection cycle, do not change the vertical sync signal (detection edge) when it is

close to the horizontal sync signal edge. This may result in distortion of the display due to fluctuations in the
sync signal.

*3 : VVE, VHE and HE are control bits of Command 13-0 (I/O pin control) .

VSYNC : Leading-edge operation (VVE = 0)
HSYNC

VSYNC

HSYNC

: VSYNC detection at the trailing edge (VHE = 1)

tVF

tVS

0.8 VDD

0.2 VDD

tHF tHR

tWH

0.8 VDD

0.2 VDD

tWV

0.8 VDD

0.2 VDD

tVH

tVR

0.8 VDD

0.2 VDD

(Continued)

12

(Continued)

MB90099

VSYNC
HSYNC

VSYNC

HSYNC

: Trailing-edge operation (VVE = 1)
: VSYNC detection at the trailing edge (VHE = 1 and HE = 0)

tVR

tWV

0.2 VDD

0.8 VDD

tVS

0.8 VDD

tHF tHR

tWH

0.2 VDD

VSYNC : Leading-edge operation (VVE = 0)
HSYNC

VSYNC

: VSYNC detection at the leading edge (VHE = 0)

tVF

tVS

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

tWV

tVF

tVH

0.8 VDD

0.2 VDD

tVR

tVH

0.8 VDD

0.2 VDD

tHF tHR

tWH

HSYNC

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

VSYNC : Trailing-edge operation (VVE = 1)
HSYNC

VSYNC

HSYNC

: VSYNC detection at the leading edge (VHE = 0) or (VHE = 1 and HE = 1)

tVR

tWV

0.2 VDD

tVS

0.8 VDD

tHF tHR

tWH

0.8 VDD

0.2 VDD

tVH

0.8 VDD

0.8 VDD

0.2 VDD

tVF

0.2 VDD

Note : The above diagrams assume that I/O pin control command (command 13-0) has set the sync signal input

logic control setting (SIX bit) to negative logic (“0”) . However, if the positive logic setting (SIX bit = “1”) is
used, the H and L levels are reversed.

13

MB90099

(3) Dot clock external input timing

(V

= 2.7 V to 3.3 V, V

DD

= 0 V, Ta = −20 °C to +70 °C)

GND

Parameter Symbol Pin name

t

DCYC1

EXD 112 166 ns *1

Dot clock cycle time

t

DCYC2

t

DWH1

EXD 56 83 ns *2

EXD

t

DWL1

Dot clock pulse time

t

DWH2

EXD

t

DWL2

HSYNC, VSYNC setup time t
HSYNC

, VSYNC hold time t
Data output delay time 1 t
Data output delay time 2 t

Note : The above items assume a supply voltage of V

DS

DH

DD1

DD2

HSYNC,

VSYNC

VC3, VC2, VC1, VC0,

BLKA, BLKB, BLKC

= 2.7 V to 3.3 V.

DD

*1 : Assuming input frequency = dot clock × 1.
*2 : Assuming input frequency = dot clock × 2.
*3 : Assuming input frequency = dot clock × 1 or dot clock × 2.

Value

Unit Note

Min. Max.

48  ns
48  ns
24  ns
24  ns
13  ns *3

0  ns *3
7t

t

DD1

DD2

45 ns

ns

*1

*2

*3

14

tDCYC1,tDCYC2

MB90099

tDWH1, tDWH2

tDWH1, tDWH2

EXD input

tDH

tDS

HSYNC input
VSYNC input

Data output

Sync signal

detection period *

tDD1

0.8 VDD

0.2 VDD

tDD2

Output undefined period

(Output transition period)

AC measurement conditions

C = 70 pF
t

= 5 ns

r

t

= 5 ns

f

= 0.8 V

V

OH

VOL = 0.2 V
VIH = 0.8 V
VIL = 0.2 V

DD
DD

DD

DD

* : Do not vary the input sync signal during the sync signal detection period.

Changes in the signal during this period may cause distortion in the display.

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

15

MB90099

(4) Reset input timing

(V

= 2.4 V to 3.6 V, V

DD

= 0 V, Ta = −20 °C to +70 °C)

GND

Parameter Symbol Pin name

Reset pulse width t
Clock input t

* : Clock input is required during reset.

RESET

EXD

WRST

WRSD

Value

Unit Note

Min. Max.

RESET 1 µs

EXD 5  Dot clock *

tWRST

tWRSD

0.2 VDD

16

DISPLAY CONTROL COMMANDS

■

1. Command list

MB90099

Com­mand

no.

0

1

2

3

4

5-00

5-01

5-02

5-2

5-3

Function

VRAM write
address setting

Character data
setting 1

Character data
setting 2

Line control data
setting 1

Line control data
setting 2

Screen output
control 1A

Screen output
control 1B

Screen output
control 1C

Vertical display
position control

Horizontal display
position control

Command code/data

15 to 1211109876543210

0 0 0 0 AY3 AY2 AY1 AY0 FL 0 0 AX4 AX3 AX2 AX1 AX0

0 0 0 1 MO1 MO0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0

0 0 1 0MRMSM9M8M7M6M5M4M3M2M1M0

0 0 1 1 LHS LW2 LW1 LW0 LFD LFC LFB LFA LF3 LF2 LF1 LF0

0 1 0 0 LDS LGS LG1 LG0 LD LE LM1 LM0 L3 L2 L1 L0

0 1 0 1 0 0 0 0 SDS UDS 0 DSP 0 OA2 OA1 OA0

0 1 0 1 0 0 0 1 SOB BGB BLB 0 0 OB2 OB1 OB0

0 1 0 1 0 0 1 0 SOC BGC BLC 0 0 OC2 OC1 OC0

0 1 0 1 1 0 0 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 1 0 1 1 1 0 X8 X7 X6 X5 X4 X3 X2 X1 X0

Shaded

6-1

7-3

8-0

8-1

9-0

9-1

11-0
11-2Dot clock control 11 0 1 1100000000DC2DC1DC0

background frame
color control

Screen
background
control

Sprite character
control 1

Sprite character
control 2

Sprite character
control 4

Sprite character
control 5

Screen extension
control

0 1 1 0 0 1 0 0 BH3 BH2 BH1 BH0 BS3 BS2 BS1 BS0

0 1 1 111000000U3U2U1U0

1 0 0 0 0 0 SFB SFA SF3 SF2 SF1 SF0 SC3 SC2 SC1 SC0

1 0 0 0 0 1 SD1 SD0 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0

1 0 0 1 0 0 SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0

1 0 0 1 1 0 SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0

1 0 1 100000EG0000000

(Continued)

17

MB90099

(Continued)

Com­mand

no.

13-0 I/O pin control 1 1 0 1 0 0 VVE VHE HE 0 SIX 0 0 0 DBX DCX
13-1

13-2

Function

Horizontal
blanking control 1

Horizontal
blanking control 2

15 to 1211109876543210

1 1 0 1010000BB5BB4BB3BB2BB1BB0

1 1 0 1 1 0 0 BF8BF7BF6BF5BF4BF3BF2BF1BF0

Command code/data

18

MB90099

2. Command Description

• Command 0 (VRAM write address setting)

Command 0 sets the write address in VRAM, and controls the execution of “VRAM fill”. The write address is
specified by row and column addresses. VRAM fill is activ ated by executing char acter data setting 2 (command 2) .

1514131211109876543210

0000AY3AY2AY1AY0FL00AX4AX3AX2AX1AX0

AY3 to AY0 : Row address (0 to B
AX4 to AX0 : Column address (0 to 1B
FL : VRAM Fill control (0 : OFF, 1 : ON)

• Command 1 (Character data setting 1)

Command 1 specifies character data. The character data is written to VRAM and reflected on the screen by the
execution of command 2 (character data setting 2) .

1514131211109876543210

0001MO1MO0MM1MM0MB3MB2MB1MB0MC3MC2MC1MC0

MO1, MO0 : Character output control
MM1, MM0 : Character background control

(0, 0 : Off)
(0, 1 : Solid fill)
(1, 0 : Concaved shaded)

(1, 1 : Convexed shaded)
MC3 to MC0 : Character color (16 colors)
MB3 to MB0 : Background color (16 colors)

• Command 2 (Character data setting 2)

)

H

)

H

Command 2 writes additional character data to the location in VRAM spacified by command 0 (VRAM write
address setting ),along with the character data set by command 1 (character data setting 1).

The VRAM write address is automatically incremented after command 2 is executed.

1514131211109876543210

0010MRMSM9M8M7M6M5M4M3M2M1M0

MR : Shaded background succeeding character merge control

(0 : Not merged with succeeding character)

(1 : Merged with succeeding character)
MS : Character horizontal size control

(0 : S size, 6 dots)

(1 : L size, 12 dots)
M9 to M0 : Character code

19

MB90099

• Command 3 (Line control data setting 1)

Command 3 specifies line control data. The line control data is written to VRAM and reflected on the screen by
the execution of command 4 (line control data setting 2) .

1514131211109876543210

0011LHSLW2LW1LW0LFDLFCLFBLFALF3LF2LF1LF0

LHS : Line character vertical size type control

(0 : Character vertical size A)

(1 : Character vertical size B)
LW2 to LW0 : Line spacing control

(0 to 7 dots, in 1-dot units)
LF3 to LF0 : Trimming color (16 colors)
LFD, LFC : Trimming output control

(0, 0 : All Off)

(0, 1 : Trimming On for a character only, no character background)

(1, 0 : Trimming On for a solid-fill character or no character background)

(1, 1 : All On)
LFB, LFA : Trimming control

(0, 0 : Trimming Off)

(0, 1 : Reserved (setting prohibited) )

(1, 0 : Reserved (setting prohibited) )

(1, 1 : Eight-direction trimming)

• Command 4 (Line control data setting 2)

Command 4 specifies additional line control data and writes this data, along with the line control data set by
command 3 (line control data setting 1) to the row address in VRAM specified by command 0 (VRAM write
address setting) .

Executing this command will not alter the VRAM write address.

1514131211109876543210

0100LDSLGSLG1LG0LDLELM1LM0L3L2L1L0

LDS : Line character output control (control of a character + trimming + character background)

(0 : Off, 1 : On)
LGS : Line enlargement interpolation control

(0 : Off, 1 : On)
LG1, LG0 : Line enlargement control

(0, 0 : Normal)

(0, 1 : Double width)

(1, 0 : Double height)

(1, 1 : Double width × double height)
LE : Character background extension control

(0 : Normal, 1 : Extended)
LD : Shaded background succeeding line merge control

(0 : Independent)

(1 : Merged with succeeding line)

20

MB90099

LM1, LM0 : Line background control

(0, 0 : Off)

(0, 1 : Solid fill)

(1, 0 : Concaved shaded)

(1, 1 : Convexed shaded)
L3 to L0 : Line background color (16 colors)

• Command 5-00 (Screen output control 1A)

Command 5-00 controls screen display output.

1514131211109876543210

01010000SDSUDS0DSP0OA2OA1OA0

SDS : Sprite character output control

(0 : Off, 1 : On) *
UDS : Screen background output control

(0 : Off, 1 : On) *
DSP : Display output control (Control of a character + trimming + character background + line background)

(0 : Off, 1 : On) *
OA2 to OA0 : Output-A character control (8 types)
* : Input of an ’L’ level signal to the RESET

• Command 5-01 (Screen output control 1B)

Command 5-01 controls output-B screen display output.

1514131211109876543210

01010001SOBBGBBLB00OB2OB1OB0

SOB : Output-B sprite character output control

(0 : Off, 1 : On)
BGB : Output-B screen background output control

(0 : Off, 1 : On)
BLB : Output-B line background output control

(0 : Off, 1 : On)
OB2 to OB0 : Output-B character control (8 types)

pin will initialize SDS = 0, UDS = 0, and DSP = 0.

21

MB90099

• Command 5-02 (Screen output control 1C)

Command 5-02 controls output-C screen display output.

1514131211109876543210

01010010SOCBGCBLC00OC2OC1OC0

SOC : Output-C sprite character output control

(0 : Off, 1 : On)
BGC : Output-C screen background output control

(0 : Off, 1 : On)
BLC : Output-C line background output control

(0 : Off, 1 : On)
OC2 to OC0 : Output-C character control (8 types)

• Command 5-2 (Vertical display position control)

Command 5-2 controls the vertical display position on the screen.

1514131211109876543210

0101100Y8Y7Y6Y5Y4Y3Y2Y1Y0

Y8 to Y0 : Vertical display position control (0 to 1022 in 2-dot units)

• Command 5-3 (Horizontal display position control)

Command 5-3 controls the horizontal display position on the screen.

1514131211109876543210

0101110X8X7X6X5X4X3X2X1X0

X8 to X0 : Horizontal display position control (0 to 1022 in 2-dot units)

• Command 6-1 (Shaded background frame color control)

Command 6-1 controls the frame color of the shaded background.

1514131211109876543210

01100100BH3BH2BH1BH0BS3BS2BS1BS0

BH3 to BH0 : Shaded background frame highlight color (16 colors)
BS3 to BS0 : Shaded background frame shadow color (16 colors)

• Command 7-3 (Screen background control)

Command 7-3 controls the screen background color.

1514131211109876543210

011111000000U3U2U1U0

U3 to U0 : Screen background color (16 colors)

22

MB90099

• Command 8-0 (Sprite character control 1)

Command 8-0 controls sprite characters.

1514131211109876543210

100000SFBSFASF3SF2SF1SF0SC3SC2SC1SC0

SFB, SFA : Sprite character trimming control

(0, 0 : Trimming Off)

(0, 1 : Reserved)

(1, 0 : Reserved)

(1, 1 : Eight-direction trimming)
SF3 to SF0 : Sprite character trimming color (16 colors)
SC3 to SC0 : Sprite character color (16 colors)

• Command 8-1 (Sprite character control 2)

Command 8-1 controls sprite characters.

1514131211109876543210

100001SD1SD0SM7SM6SM5SM4SM3SM2SM1SM0

SD1, SD0 : Sprite character configuration control

(0, 0 : 1 character)

(0, 1 : Reserved (setting prohibited) )

(1, 0 : Stack of 2 characters)

(1, 1 : Reserved (setting prohibited) )
SM7 to SM0 : Sprite character code

(000

to 0FFH for 256 different characters)

H

• Command 9-0 (Sprite character control 4)

Command 9-0 controls the vertical display position of sprite characters.

1514131211109876543210

100100SY9SY8SY7SY6SY5SY4SY3SY2SY1SY0

SY9 to SY0 : Sprite character vertical display position control

(0 to 1023 in 1-dot units)

• Command 9-1 (Sprite character control 5)

Command 9-1 controls the horizontal display position of sprite characters.

1514131211109876543210

100110SX9SX8SX7SX6SX5SX4SX3SX2SX1SX0

SX9 to SX0 : Sprite character horizontal display position control

(0 to 1023 in 1-dot units)

23

MB90099

• Command 11-0 (Screen extension control)

(Reserved)

1514131211109876543210

101100000EG0000000

EG0 : (Reserved)

(0 : Normal)

(1 : Reserved (setting prohibited) )

• Command 11-2 (Dot clock control 1)

Command 11-2 controls dot clock selection.

1514131211109876543210

1011100000000DC2DC1DC0

DC2 to DC0 : Dot clock selection control

(0, 1, 0) : External dot clock input

(0, 1, 1) : Frequency-doubled external dot clock input

•

Command 13-0 (I/O pin control

)

Command 13-0 controls I/O pin functions.

1514131211109876543210

110100VVEVHEHE0SIX000DBXDCX

VVE : Edge selection for vertical synchronization detection*

1

(0 : Leading edge, 1 : Trailing edge)
VHE : HSYNC edge selection for vertical synchronization detection*

1

(0 : Leading edge, 1 : Trailing edge)
HE : Edge selection for horizontal synchronization operation*

1

(0 : Trailing edge, 1 : Leading edge)
SIX : Logic control for sync signal input

(0 : Negative logic, 1 : Positive logic)
DCX : Logic control for display color signal output

(0 : Positive logic, 1 : Negative logic) *

2

DBX : Logic control for display output period signal

(0 : Positive logic, 1 : Negative logic) *

2

24

MB90099

*1 : When it is set up VVE = 1, VHE = 1 and HE = 1, the vertical sync detection HSYNC edge is the standard of

“Leading edge”.

VVE VHE HE Contents of vertical sync detection Position of vertical sync detection*

0 0 0 Detection of VSYNC Leading edge HSYNC Leading edge
0 0 1 Detection of VSYNC Leading edge HSYNC Leading edge
0 1 0 Detection of VSYNC Leading edge HSYNC Trailing edge
0 1 1 Detection of VSYNC Leading edge HSYNC Trailing edge
1 0 0 Detection of VSYNC Trailing edge HSYNC Leading edge
1 0 1 Detection of VSYNC Trailing edge HSYNC Leading edge
1 1 0 Detection of VSYNC Trailing edge HSYNC Trailing edge
1 1 1 Detection of VSYNC Trailing edge HSYNC Leading edge + 10 clock

* : If there is the change of level for direction of VSYNC pin signal detection in the vicinity of vertical sync

detection, it may occur disorder in the display (deflection of vertical direction) . Input the meaningful edge
of VSYNC signal without this position of vertical sync detection.

*2 : Input of an ’L’ level signal to the RESET

• Command 13-1 (Horizontal blanking control 1)

Command 13-1 controls the back porch of the horizontal blanking function.

1514131211109876543210

1101010000BB5BB4BB3BB2BB1BB0

BB5 to BB0 : Back porch control (0 to 126, in 2-dot units)

• Command 13-2 (Horizontal blanking control 2)

Command 13-2 controls the front porch of the horizontal blanking function.

1514131211109876543210

1101100BF8BF7BF6BF5BF4BF3BF2BF1BF0

BF8 to BF0 : Front porch control (0 to 1022, in 2-dot units)

pin will initialize DCX = 0, and DBX = 0.

25

MB90099

3. Notes on Issuing Commands

(1) Initialization

When a reset signal is input (“L” level signal input to the RESET
The contents of VRAM (the character RAM and the line RAM) are undefined.

Immediately after release of the input signal to the MB90099, issue the following commands to initializ e control
operation.

• Dot clock control 1 (command 11-2)

• I/O pin control (command 13-0)
This must be done before setting all command data and all RAM contents. (VRAM settings require normal dot

clock input and normal sync signal input.)

* : The reset input initializes control bits as follows.

Screen output control 1A (command 5-00)

SDS = 0Sprite Off
UDS = 0 Screen background Off
DSP = 0 Character, character background, line background Off

I/O pin control (command 13-0)

DCX = 0 VC0, VC1, VC2, VC3 pins set to positive logic output
DBX = 0 BLKA, BLKB, BLKC pins set to positive logic output

(2) Command refresh

Command data to the MB90099 and the contents of internal VRAM are stored as long as power is supplied to
the MB90099. However, there may be cases in which the serial control, sync, or dot clock signals become
abnormal due to causes such as external noise, preventing the internal registers and VRAM from being set
properly . It is therefore recommended that all command data and VRAM data be refreshed periodically to ensure
that this data is correct.

pin) , the MB90099 enters display-off state(*).

(3) Command issue timing

When any control command, including a VRAM write command such as a character data setting or line control
data setting command is issued, the command is ex ecuted immediately and the result is reflected on the screen.
When such a command is issued during a display period, the display in the relevant field may experience
momentary distor tion. To avoid this, it is recommended that commands be issued during the vertical blanking
interval. However that with a command 5-00 (screen output control 1A) in which one or more of the DSP, SDS,
or UDS control bits is switched from OFF to ON, the display will wait until the next vertical sync signal after the
command is issued and the display will start from the top of the scanning field.

26

CONTENTS OF MB90099-001 (STANDARD PRODUCT) FONT DATA

■

MB90099

27

MB90099

28

MB90099

29

MB90099

30

MB90099

FONT DEVELOPMENT AND DATA RELEASE

■

The MB90099 features the f ont ROM in which all 1024 characters are user-definable . For f ont data dev elopment,
use the OSDC pattern editor Ped/Win. Ped/Win is an OSCD proprietar y pattern editor for use on personal
computers operating Windows95/98/NT4.0 (Japanese language) environments.

The font development and data release flow is illustrated below.

Font development input

OSCD

pattern editor

Ped/Win

(supplied by FUJITSU)

Install

Run

Personal computer

(Windows95/98/NT)

Pattern printing

Printer

Project file Pattern file

Font data release

(register with FUJITSU)

3-point data extraction for data release

Mask data specification writing

(1) Font data release

Font data is released in project files only. Pattern files should not be released. A portion of the pattern file data
will be used for data matching in order to verify registration of release data by FUJITSU. For this reason, users
are requested to write a portion of the pattern data content in mask data specifications.

Note : Pattern data output should not be generated until after the completion of font creation and project creation.

Also, the project file should not be updated after pattern file generation is completed. If the project contents
are updated after pattern file generation, pattern files should be generated again.

(2) Project files

After font data and other supplementary data is created, it is stored in a project file. Normally one project file is
created for each model.

•

Project file names

Project file names should be in the format “MB90099-XXX” where “XXX” is a ROM number assigned by
FUJITSU. Users should contact their FUJITSU sales representative. If no ROM number has been assigned,
any number preceded by an alphabetic character may be used. Project files which are developed solely for
test purposes and not intended for font release may be assigned any file name.

•

Comments related to new project files

Comment lines in the form of any desired character strings may be added at the time a project file is created.
Comments will be printed when the font is printed, and can be modified as needed whenev er that Ped/Win is
operating.

31

MB90099

(3) Pattern files

Font data may be placed in patter n files. Because pattern data is saved in the project file, normally it is only
necessary to create a pattern file at the time of font release for the purpose of extracting verification data (writing
to mask data specifications) . Pattern files should not be released.

•

Pattern file loading

Pattern files can be loaded for some OSCD models other than the MB90099.

•

Pattern file output generation

Do not create more than one pattern file for the same project. This may cause errors . In such cases, the
project name should be altered to create another project.

•

Extracting verification data

Three data points, the first and last addresses and one other random address, should be extracted from pattern
file data and written into the mask data specifications. The random address should not include the data values
“00” or “FF.”

Note : P ed/Win displa y functions are based on OSDC specifications, howe ver some displa y specifications ma y not

be identical to actual OSDC specifications. Users should consult specification documents for details.

(Data comparison)

After data release, once ROM mask processing is completed FUJITSU will extract the ROM data used in this
process. Users should verify that the extracted data is identical to the pattern file data that was submitted, and
return a written statement of data comparison indicating whether that data is identical or not . If the data is not
identical, contact FUJITSU’s sales representative immediately . Data errors may cause errors in ES production.

32

ORDERING INFORMATION

■

Part Number Package Remarks

MB90099PFV

MB90099

20-pin Plastic SSOP

(FPT-20P-M03)

MB90099LGA

20-pin Plastic FLGA

(LGA-20P-M01)

33

MB90099

PACKAGE DIMENSION

■

20-pin Plastic SSOP

(FPT-20P-M03)

*

6.50±0.10(.256±.004)

20

INDEX

LEAD No.

1 10

0.65(.026)

0.10(.004)

11

0.24±0.08

(.009±.003)

*

4.40±0.10 6.40±0.20

0.13(.005)

(.252±.008)(.173±.004)

M

* : These dimensions do not include resin protrusion.

0.17±0.03

(.007±.001)

Details of "A" part

+0.20
–0.10

1.25

(Mounting height)

+.008

.049 –.004

"A"

0~8°

0.50±0.20

(.020±.008)

0.45/0.75

(.018/.030)

0.10±0.10

(.004±.004)

0.25(.010)

(Stand off)

C

1999 FUJITSU LIMITED F20012S-3C-5

Dimensions in mm (inches)

(Continued)

34

(Continued)

20-pin plastic FLGA

(LGA-20P-M02)

5.50(.217)

INDEX AREA

4.00(.157)

1.30(.051)
Max.

3.25(.128)

4.55(.179)

3.25(.128)

0.65

(.026)

20-ø0.35(20-ø.014)

3-ø0.45(4-ø.018)

MB90099

6
5
4
3

0.45(.018)

2
1

ABCDEFGH

0.45(.018)

0.08(.003)

C

2001 FUJITSU LIMITED L20001S-c-1-1

Dimensions in mm (inches)

35

MB90099

FUJITSU LIMITED

All Rights Reserved.

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.

The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.

F0202

FUJITSU LIMITED Printed in Japan

