FUJITSU MB90098A DATA SHEET

查询MB90098供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP For Screen Display Control

CMOS

On-Screen Display Controller

MB90098A

DESCRIPTION

■■■■

The FUJITSU MB90098A on-screen display controller is designed for use with LCD monitors, operates at a
maximum dot clock frequency of 140 MHz, and provides demultiplexed output (2-pixel parallel output) .

DS04-28827-1E

The maximum display screen configuration is 32 characters × 16 rows, with a maximum resolution of 24 × 32
dots per character making the MB90098A ideal for use with SVGA, XGA, SXGA etc. LCD displays.

A variety of display functions are enab led including sprite characters, bac kground char acters, gr aphics functions
etc.

FEATURES

■■■■

• Main screen display capacity Maximum 32 characters × 16 rows

• Character configuration L size : 24 dots (h) × 2h* dots (v)
M size : 18 dots (h) × 2h* dots (v)
S size : 12 dots (h) × 2h* dots (v) * : h = 9 to 16
L, M, S sizes can be selected by character
h can be set to 2 values per screen

• Character type 512 character types built in

(Continued)

PACKAGE

■■■■

28-pin plastic SOP

(FPT-28P-M17)

MB90098A

(Continued)

• Display modes Normal/graphic characters (set for each character)
Border display (horizontal border

/pattern background)
Character background

(solid-fill/shaded)
Row background (solid-fill/shaded) (set for each row)
Enlarged (standard, double height,

double width, double height & width)
Blinking : Select blinking character,

period, duty ratio

• Sprite character display

(graphic display only)

• Screen background character

display (graphic display only)

• Display color Character color/background color

• Display position control

• Character/color signal output Choice of straight output or demultiplexed output

• Clock frequency 140 MHz

• Microcontroller interface 16-bit serial input (3 signal input pins)

• Package SOP-28

• Supply voltage +3.3 V

Can display 1 block on main screen (Max. 2 characters wide × 2 high) .
Only the first 256 characters can be used (code : 000

Repeated pattern below main screen (Max. 2 characters wide × 2 high) .
Only the first 256 characters can be used (code : 000

Row background/character border color
Screen background color
Graphic character dot color
Shadow background border color

Horizontal display start position
Vertical display start position
Row spacing control

DA3-DA0 (color signal) , VOBA (OSD display period output signal)
DB3-DB0 (color signal) , VOBB (OSD display period output signal)

(set for each screen)

(set for each character)

(set for each row)

(set for each character)
(set for each screen)

H to 0FFH)

H to 0FFH)

16 colors each (set for each character)
16 colors each (set for each row)
16 colors (set for each screen)
16 colors (set for each dot)
16 colors (set for each screen)

Control in 4-dot units (set for each
screen)
Control in 4-dot units (set for each
screen)
Control in 2-dot units (set for each
row)

2

PIN ASSIGNMENT

■■■■

MB90098A

(TOP VIEW)

CS

SIN

SCLK

SS

V

DCLKI

V

SS

VDD

TCLKI

V
HSYNC
VSYNC

DISP

RESET

TEST

1
2
3
4
5
6
7
8

DD

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

DA0
DA1
DA2
DA3
VOBA
V

SS

DCLKO

DD

V
DB0
DB1
DB2
DB3
VOBB
BUSY

(FPT-28P-M17)

3

MB90098A

PIN DESCRIPTIONS

■■■■

Pin Pin no. I/O

DCLKI 5 Input B Dot clock input pin
DCLKO 22 Output A Dot clock output pin
HSYNC
VSYNC 11 Input B Vertical sync signal input pin. The active level is programmable.

DISP 12 Input B

DA3
DA2
DA1
DA0

VOBA 24 Output A

DB3
DB2
DB1
DB0

10 Input B Horizontal sync signal input pin. The active level is programmable.

25
26
27
28

17
18
19
20

Output A

Output A

Circuit

type

Description

Display output control signal input pin. Input a high level signal to
enable display output. Input a low level signal to set the display
output (DA3-0, VOBA, DB3-0, VOBB pin output) to inactive level.
The active level is programmable.

Color signal output pins. In straight output mode, the all-dot signal
is output. In demultiplexed output mode, the even dot signal is out­put. The active level is programmable.

Display period signal output pin. In straight output mode, the all­dot display period signal is output. In demultiplexed output mode,
the even dot display period signal is output. The active level is pro­grammable.

Color signal output pins. In demultiplexed output mode, the odd
dot signal is output. In straight output mode, the output is fixed at
inactive level. The active level is programmable.

Display period signal output pin. In demultiplexed output mode, the

VOBB 16 Output A

BUSY 15 Output A

CS

SIN 2 Input C Serial data input pin.

SCLK 3 Input C Shift clock input pin for serial transfer.

RESET

TEST

V

DD 7, 9, 21 +3.3 V power supply pins.

VSS 4, 6, 23 Ground pins

TCLKI 8 Input B

1 Input C

13 Input C Reset signal input pin. Input a low level signal at power-on.
14 Input C

odd dot display period signal is output. In straight output mode, the
output is fixed at inactive level. The active level is programmable.

Busy signal output pin. During internal VRAM fill operation, or in­ternal command ROM transfer, a high level signal is output.

Chip select pin. During serial instruction transfer, a low level signal
is input.

Test signal input pin. Input a (fixed) high level signal during normal
operation.

Test clock input pin. Input a (fixed) low level signal during normal
operation.

4

INPUT/OUTPUT CIRCUIT TYPES

■■■■

Type Circuit diagram Remarks

• CMOS output

Pch

A

Nch

• CMOS hysteresis input

B

• CMOS hysteresis input with pull-up
resistance (approx. 50 kΩ)

MB90098A

C

5

MB90098A

BLOCK DIAGRAM

■■■■

DISP

RESET

VSYNC
HSYNC

CS

SIN

SCLK

BUSY

DCLKI

Serial

input

control

Command

ROM

transfer

control

Command

ROM

(16 Kbyte)

Display control

Display

memory VRAM

(32 ch. × 16 row)

Clock

Dot clock control

Font

ROM

(512 fonts)

EVEN

display

output

control

ODD

display

output

control

DA0
DA1

DA2
DA3
VOBA

DB0
DB1
DB2
DB3

VOBB

DCLKO

6

ABSOLUTE MAXIMUM RATINGS

■■■■

Parameter Symbol

MB90098A

(VSS = 0 V Typ.)

Rating

Unit Remarks

Min. Max.

Power supply voltage V
Input voltage V
Output voltage V

DD VSS − 0.5 VSS + 4.0 V

IN VSS − 0.5 VDD + 0.5 V

OUT VSS − 0.5 VDD + 0.5 V

Power consumption Pd  400 mW
Operating temperature Ta 0 70 °C
Storage temperature Tstg −55 +125 °C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

■■■■

(VSS = 0 V Typ.)

Values

Parameter Symbol

Unit Remarks

Min. Max.

Power supply voltage V
“H” level input voltage V
“L” level input voltage V

DD 3.0 3.6 V

IH 0.8 × VDD VDD + 0.3 V
IL VSS − 0.3 0.2 × VDD V

Operating temperature Ta 0 70 °C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

7

MB90098A

ELECTRICAL CHARACTERISTICS

■■■■

1. DC Characteristics

Parameter Symbol Pin Conditions

(VSS = 0 V, Ta = 0 to 70 °C)

Values

Unit

Min. Typ. Max.

“H” level
output voltage

“L” level
output voltage

V

VOL

Pull-up resistance R

Input leak current I

Power supply current I

All output

OH

pins
All output

pins
CS, SIN,

SCLK,

P

RESET
TEST

DCLKI
HSYNC

IL

VSYNC
DISP

DD VDD

VDD = 3.3 V
I

OH = −8.0 mA

VDD = 3.3 V
I

OL = 8.0 mA

VDD = 3.3 V 25 50 200 kΩ

,

I = 0 V to VDD −0.5  5.0 µA

V

VDD = 3.6 V
Dot clock 140 MHz

V

DD = 3.6 V

Dot clock 100 MHz
V

DD = 3.6 V

Dot clock 60 MHz
V

DD = 3.6 V

Dot clock 10 MHz

VDD − 0.5 V

0.4 V

95 mA

70 mA

45 mA

15 mA

2. Input/Output Pin Capacitance

Parameter Symbol Measurement conditions

Input pins C
Output pins C

8

IN

OUT  16 pF

VI = 0 V, VDD = 0 V
f = 1 MHz, Ta = 25 °C

Values

Unit

Min. Max.

 16 pF

3. AC Characteristics

AC characteristics are measured under the following conditions :

MB90098A

Measurement conditions : C = 28 pF, t

r = 1 ns , tf = 1 ns, VOH = 0.8 VDD, VOL = 0.2 VDD, VIH = 0.8 VDD, VIL = 0.2 VDD

(1) Serial Input Timing

(V

DD = 3.3 V ± 0.3 V, VSS = 0 V, Ta = 0 to 70 °C)

Values

Parameter Symbol Pin

Unit Remarks

Min. Max.

Shift clock cycle time t

Shift clock pulse width

Shift clock signal rise-fall time

Shift clock start time t

CYC SCLK 250  ns

WCH

t

100  ns

SCLK

WCL 100  ns

t

tCR

 200 ns

SCLK

CF  200 ns

t

SS SCLK 100  ns

Data setup time tSU SIN 100  ns
Data hold time t
Chip select end time t

Chip select signal rise-fall time

H SIN 50  ns

EC CS 100  ns

tCRC

 200 ns

CS

t

CFC  200 ns

•

Serial input timing

CS

SCLK

SIN

0.8 VDD

tCFC

0.2 VDD

tSS

tCR

tWCH

tCYC

tCF

tSU

0.8 VDD

0.2 VDD

tCRC

tEC

0.8 VDD

0.2 VDD

tWCL

tH

0.8 VDD

0.2 VDD

9

MB90098A

(2) Vertical Synchronization, Horizontal Synchronization, Display Output Control Signal Input Timing

(V

DD = 3.3 V ± 0.3 V, VSS = 0 V, Ta = 0 to 70 °C)

Parameter Symbol Pin

Values

Unit Remarks

Min. Max.

Horizontal sync signal cycle time t

HCYC HSYNC 100 + tWH  Dot clock

20  Dot clock

Horizontal sync signal pulse width t

WH HSYNC

*

 6 µs

Horizontal sync signal setup time t

DHST

4  ns

HSYNC

Horizontal sync signal hold time t
Vertical sync signal setup time tHVST

DHHD 0  ns

51H − 5 Dot clock

VSYNC

Vertical sync signal hold time t
Display output control signal setup time t

HVHD 3  H

DDST

4  ns

DISP

Display output control signal hold time t

Input sync signal rise-fall time

DDHD 0  ns

t

DR

tDF

HSYNC
VSYNC

DISP

 2ns

* : During the horizontal synchronization pulse width, the MB90098A internal operations are temporarily paused

and writing to the internal VRAM is disabled. For this reason it is necessary to set both the horizontal synchro­nization signal pulse width and the VRAM write cycle so that :

Horizontal sync signal pulse width < VRAM write cycle
Specifically, the period between instructions should be adjusted so that instruction 2 or instruction 4 (the VRAM

write instruction) is not repeated during the period of one horizontal sync signal pulse width.
If the above condition is not satisfied, writing to VRAM will not be executed normally.

10

•

Horizontal synchronization signal, display output control signal input timing

DCLKI

tDHST

0.8 VDD

HSYNC

0.2 VDD

tDR, tDF

tDDST

0.8 VDD

DISP

0.2 VDD

tDR, tDF

0.8 VDD

0.2 VDD

tDHHD

0.8 VDD

0.2 VDD

tDDHD

0.8 VDD

0.2 VDD

•

Horizontal synchronization signal input

MB90098A

tHCYC

HSYNC

0.8 VDD

• Vertical synchronization signal input timing

VSYNC detection at HSYNC leading-edge

HSYNC

tDF

VSYNC

0.8 VDD

0.2 VDD

VSYNC detection at HSYNC trailing edge

0.8 VDD

0.2 VDD

tDF

0.8 VDD

0.2 VDD

tDF

tWH

tWH

tHVHDtHVST

tDR

0.8 VDD

0.2 VDD

tDR

0.8 VDD

0.2 VDD

tDR

0.8 VDD

0.2 VDD

HSYNC

VSYNC

tDF

0.8 VDD

0.2 VDD

tDF

0.8 VDD

0.2 VDD

tWH

tDR

0.8 VDD

0.2 VDD

tHVHDtHVST

tDR

0.8 VDD

0.2 VDD

11

MB90098A

(3) Display Signal Timing

Parameter Symbol Pin

(V

DD = 3.3 V ± 0.3 V, VSS = 0 V, Ta = 0 to 70 °C)

Values

Unit Remarks

Min. Max.

Dot clock input cycle time
(straight output)

Dot clock input pulse width
(straight output)

Dot clock input cycle time
(demultiplexed output)

Dot clock input pulse width
(demultiplexed output)

Display output control on/off delay
time

t

DIFS DCLKI 10 90 MHz

t

DIWHS

5  ns

DCLKI

t

DIWLS 5  ns

t

DIFD DCLKI 10 140 MHz

DIWHD

t

3  ns

DCLKI

t

DIWLD 3  ns

DON

t

DOFF  6

t

DA3 to DA0, VOBA
DB3 to DB0, VOBB

6 

clock

Dot

* 1
* 3

* 1
* 3

* 2
* 3

* 2
* 3

*4

Dot clock output delay time 1 tPDCS DCLKO 3 6 ns *1
Dot clock output delay time 2 t
Display signal output delay time I1

(straight output)
Display signal output delay time I2

(straight output)
Display signal output delay time O1

(straight output)
Display signal output delay time O2

(straight output)

PDCD DCLKO 3 7 ns *2

t

PDIS1

t

PDIS2

t

PDOS1

t

PDOS2

DA3 to DA0, VOBA
DB3 to DB0, VOBB

DA3 to DA0, VOBA
DB3 to DB0, VOBB

DA3 to DA0, VOBA
DB3 to DB0, VOBB

DA3 to DA0, VOBA
DB3 to DB0, VOBB

27ns*1

16ns*1

−45ns*1

−54ns*1

Display signal output delay time I1
(demultiplexed output)

Display signal output delay time I2
(demultiplexed output)

Display signal output delay time O1
(demultiplexed output)

Display signal output delay time O2
(demultiplexed output)

t

PDID1

t

PDID2

t

PDOD1

t

PDOD2

DA3 to DA0, VOBA
DB3 to DB0, VOBB

DA3 to DA0, VOBA
DB3 to DB0, VOBB

DA3 to DA0, VOBA
DB3 to DB0, VOBB

DA3 to DA0, VOBA
DB3 to DB0, VOBB

27ns*2

16ns*2

−55ns*2

−64ns*2

*1 : The maximum output frequency for straight output is 90 MHz.
*2 : The maximum output frequency for demultiplexed output is 70 MHz.
*3 : Use a continuous dot clock input signal without interruptions.
*4 : Actual display output varies according to control content, including displa y output control for each displa y lay er,

display position control, etc.

12

•

Display output control ON timing

MB90098A

DCLKI

DISP

DA3 to DA0
VOBA
DB3 to DB0
VOBB

PDIXX represents tPDIS1, tPDIS2, tPDID1, or tPDID2 depending on the operating mode.

* : t

•

Display output control OFF timing

0.2 VDD

0.8 VDD

tDDST tPDIXX

0.8 VDD

tDON

*

0.8 VDD

DCLKI

0.2 VDD

DISP

0.2 VDD

tDDST tPDIXX

DA3 to DA0
VOBA
DB3 to DB0
VOBB

* : t

PDIXX represents tPDIS1, tPDIS2, tPDID1, or tPDID2 depending on the operating mode.

0.8 VDD

tDOFF

*

0.8 VDD

13