FUJITSU MB90097 DATA SHEET

查询MB90097供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP For Screen Display Control

CMOS

ON-Screen Display Controller

MB90097

DESCRIPTION

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The MB90097 is the on-screen display controller for displaying text and graphics on the TV screen. Since it has a three-channel output control function, small package, and low voltage requirement for operation, it is suitable for on-screen display on video equipment such as camera-integrated VTRs.

DS04-28825-4E

The MB90097 provides a display screen made up of 28 characters by 12 lines, capable of displaying 512 different characters each consisting of 12 × 18 dots. The display functions of the MB90097 includes a wealth of character qualifying functions such as character background shading (shadow casting) and individual character size setting, supporting 16-color display for each character. They also include the line background, screen background, and sprite character display functions, enabling the screen to be displayed in a variety of configurations. The integrated font ROM contains 512 different character patterns all of which can be set by the user.

FEATURES

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• Character screen configuration: 28 characters × 12 lines (maximum)

• Character types: 512 different characters (integrated in ROM, user-definable through the entire area)

(Continued)

PACKAGE

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20-pin Plastic SSOP

(FPT-20P-M03)

MB90097

(Continued)

• Font configuration: 12 × 18 dots (font ROM configuration) Capable of specifying the horizontal and vertical sizes of characters to be displayed.

• One of the following three horizontal sizes (S, M, L) can be set for each character: S size : 6 dots M size : 9 dots L size : 12 dots

• Either of the following two vertical sizes (HA, HB) can be set for each line. HA : 18 dots HB : 12 dots

• Display modes: Character trimming Enabled/Disabled (Set for each line) Character background None/Solid-fill/Shaded background (concaved)/Shaded

background (convexed) (Set for each line) Horizontal character merge/independent display with shaded background (Set for each character) Vertical line merge/independent display with shaded background (Set for each line) Character background extended display ON/OFF for line spacings (Set for each line)

Line background None/Solid-fill/Shaded background (concaved)/Shaded

background (convexed) (Set for each line) (Display extended to the left and right margins of the screen and to the line spacing)

Character enlargement: Four types supported: Normal, Double width, Double height,

Enlarged display dot interpolation function (Set for each line)

• Character screen display position control:

Horizontal display position Control in 2-dot units (movable through the entire screen) Vertical display position Control in 2-dot units (movable through the entire screen) Line spacing control Control in 1-dot units (Set between 0 to 7 dots for each

line; Displayed simultaneously at two areas above and below the line.)

• Sprite character control:

Sprite character display OFF/ON Sprite character types 256 types (character codes: 000 Sprite character trimming Enabled/Disabled Sprite character configuration Two types: 1 character/Stack of 2 characters Sprite character horizontal display position Control in 1-dot units (movable through the entire screen) Sprite character vertical display position Control in 1-dot units (movable through the entire screen)

Double width × double height (Set for each line)

H to 0FFH)

(Continued)

• Screen background control: Screen background color OFF/ON

Display colors Character color: 16 colors (Set for each character)

Character trimming color: 16 colors (Set for each line) Character background color: 16 colors (Set for each character) * Line background color: 16 colors (Set for each line) Screen background color: 16 colors Sprite character color: 16 colors Sprite character trimming color: 16 colors Shaded background frame highlight color: 16 colors Shaded background frame shadow color: 16 colors *: Transparent (Displaying the lower-layer color) when the character

background color (color code) = “0”

• Display signal output: Color signal output: 4 bits (Supporting 16 colors)

Display period signals: 3 channels (Output selector circuit provid ed)

• External interface: 16-bit serial inputs

• Chip select

• Serial clock

• Serial data

•Package: SSOP-20

• Supply voltage: 3.3 V

MB90097

PIN ASSIGNMENT

■

(Top view)

SCLK

SIN

RESET

SDR

EXD

TEST

GND

1 2

3 4

6 7

8 9

(FPT-20P-M03)

20 19 18 17 16 15 14 13 12 11

HSYNC VSYNC VC0

VC1 VC2 BLKA VC3 BLKB TESTO BLKC

PIN DESCRIPTIONS

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Pin no. Pin name I/O Function

1 SCLK I Shift clock input pin for serial transfer

This pin has an internal pull-up resistor.

MB90097

2CS

3 SIN I Serial data input pin

4 RESET

5V 6 SDR I Data input direction select pin for serial transfer

7 8

9 TEST I LSI test input pin

10 GND — Ground pin 20 HSYNC 19 VSYNC I Vertical sync signal input pin 18

17 16 14

DD — + 3 V power supply pin

EXD

VC0 VC1 VC2 VC3

I Chip select pin

This pin inputs a Low level signal for serial transfer. The pin has an internal pull-up resistor.

This pin has an internal pull-up resistor.

I Reset input pin

This pin inputs a Low level signal when turning the power on.

This pin inputs the Low level signal in the LSB-first transfer mode for data input; it inputs the High level signal in the MSB-first transfer mode.

OIExternal circuit pins for display dot clock generator

Connect these pins to external “L” and “C” to form an LC oscillator circuit. For external input of a display dot clock, input the clock signal to the EXD pin and leave the XD pin open.

Input the Low level signal during normal use.

I Horizontal sync signal input pin

O O

Color code signal output pin

O 15 BLKA O Display period signal output pin for output channel A 13 BLKB O Display period signal output pin for output channel B 11 BLKC O Display period signal output pin for output channel C 12 TESTO O LSI test output pin

Leave this pin open (unconnected) during normal use.

MB90097

ABSOLUTE MAXIMUM RATINGS

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Parameter Symbol

(VGND = 0 V)

Rating

Unit Remarks

Min. Max.

Power supply voltage V

DD VGND – 0.3 VGND + 4.5 V

Input voltage VIN VGND – 0.3 VDD + 0.3 V Output voltage V

OUT VGND – 0.3 VDD + 0.3 V

Power consumption Pd — 100 mW Operating temperature Ta – 40 + 85 °C Storage temperature Tstg – 55 + 150 °C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

■

(VGND = 0 V)

Value

Parameter Symbol

Unit Remarks

Min. Max.

Power supply voltage V “H” level input voltage V “L” level input voltage V

DD 3.0 3.6 V IHS 0.8 × VDD VDD + 0.3 V ILS VGND 0.2 × VDD V

Operating temperature Ta – 40 + 85 °C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

ELECTRICAL CHARACTERISTICS

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1. DC Characteristics

Parameter Symbol Pin name Conditions

MB90097

(VGND = 0 V, Ta = – 40°C to + 85°C)

Value

Unit

Min. Typ. Max.

“H” level output voltage 1

“L” level output voltage 1 V

“H” level output voltage 2 V

“L” level output voltage 2 V

“H” level input current

“L” level input current I

PULL-UP resistance R

Power supply current I

Input capacitance C

VC3

VOH1

VC2 VC1 VC0 BLKC

OL1

BLKB BLKA

OH2

OL2

SDR

IIH

HSYNC VSYNC EXD

TEST RESET

SIN

PULL

SCLK CS

CC VDD

except V GND

DD = 3.0 V

IOH = – 4.0 mA

VDD = 3.0 V I

OL = 4.0 mA

DD = 3.0 V

IOH = – 0.5 mA VDD = 3.0 V

OL = 0.5 mA

VDD = 3.3 V V

IH = VDD

VDD = 3.3 V V

IL = 0 V

DD – 0.5 — — V

——0.4V

DD – 0.5 — — V

——0.4V

——– 10µA

——10µA

VDD = 3.3 V 20 — 110 kΩ

VDD = 3.0 V fDC = 8 MHZ

V f

DD,

DD = 3.6 V

DC = 8 MHZ

—4 6mA

—5 7mA

—10—pF

MB90097

2. AC Characteristics

(1) Serial input timings

DD = 3.0 V to 3.6 V, VGND = 0 V, Ta = – 40°C to + 85°C)

Parameter Symbol Pin name

Unit

Min. Max.

Value

Shift clock cycle time t

Shift clock pulse width

Shift clock signal rise/fall time

CYC SCLK 250 — ns

WCH

100 — ns

SCLK

WCL 100 — ns

—200ns

SCLK

CF —200ns

t Shift clock start time tSS SCLK 100 — ns Data setup time t Data hold time t

SU SIN 100 — ns H SIN 50 — ns

Chip select end time tEC CS 100 — ns

Chip select signal rise/fall time

0.8 VDD

0.2 VDD

CRC

CFC —200ns

—200ns

0.8 VDD

0.2 VDD

SCLK

SIN

tCFC

tSS

tCR tCR

tSU

tWCH

tCYC

tWCL

tCF

0.8 VDD

0.2 VDD

tCRC

tEC

0.8 VDD

0.2 VDD

(2) Vertical and horizontal sync signal input timings

MB90097

DD = 3.0 V to 3.6 V, VGND = 0 V, Ta = – 40°C to + 85°C)

Parameter Symbol Pin name

Unit

Min. Max.

Value

Horizontal sync signal rise time t

— 200 ns

HSYNC

Horizontal sync signal fall time tHF — 200 ns Vertical sync signal rise time t

— 200 ns

VSYNC

Vertical sync signal fall time t

Horizontal sync signal pulse width

VF — 200 ns

18 — Dot clock

tWH HSYNC

—6µs

Vertical sync signal detection setup time Vertical sync signal detection hold time t

tVS VSYNC 4 1H – 4 Dot clock

VH VSYNC 220H

*1: During the horizontal sync signal pulse period, the MB90097 stops its internal operation, disabling writing to

the internal VRAM. Therefore, set the horizontal sync signal pulse width and VRAM write cycle (command 2 or command 4 issuance cycle) to ensure that: horizontal sync signal pulse width < VRAM write cycle.

*2: Do not change the vertical sync signal (detection edge) in the vicinity of the horizontal sync signal edge of

vertical sync signal detection. Otherwise, it results in a deflection in the display when the sync signal fluctuates.

(1) VSYNC: Leading-edge operation

HSYNC: VSYNC detection at the trailing edge

VSYNC

HSYNC

0.8 VDD

tVF

tVS

0.2 VDD

tHF tHR

tWH

0.2 VDD

tVH

0.8 VDD

tVR

0.8 VDD

0.2 VDD

Note: The above diagrams assume that sync signal input control (SIX bit) of I/O pin control (command 13-0) has

been set to negative logic (0). The H and L levels are inverted if it has been set to positive logic.

(Continued)

MB90097

(Continued)

(2) VSYNC: Trailing-edge operation

HSYNC: VSYNC detection at the trailing edge

VSYNC

HSYNC

0.2 VDD

0.8 VDD

tHF tHR

0.2 VDD

(3) VSYNC: Leading-edge operation

HSYNC: VSYNC detection at the leading edge

VSYNC

0.8 VDD

0.2 VDD

tVR

tVF

tWH

tVS

tVF

tVH

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

tVR

tVH

0.8 VDD

0.2 VDD

tHF tHR

tWH

HSYNC

(4) VSYNC: Trailing-edge operation

HSYNC: VSYNC detection at the leading edge

VSYNC

HSYNC

0.2 VDD

tVR

0.8 VDD

tVS

0.8 VDD

0.2 VDD

tVH

tHF tHR

tWH

0.2 VDD

0.8 VDD

0.2 VDD

tVF

0.8 VDD

0.2 VDD

0.8 V DD

0.2 VDD

(3) Dot clock input timing

Parameter Symbol Pin name

Dot clock cycle time

Dot clock pulse time

HSYNC HSYNC

, VSYNC setup time tDS , VSYNC hold time tDH 0—ns*3

Data output delay time 1

Data output delay time 2 t

MB90097

DD = 3.0 V to 3.6 V, VGND = 0 V, Ta = – 40°C to + 85°C)

Value

Min. Max.

DCYC1 EXD 112 166 ns *1

t t

DCYC2 EXD 56 83 ns *2

DWH1

DWL1 48 — ns

t t

DWH2

DWL2 24 — ns

EXD

EXD HSYNC

48 — ns

24 — ns

13 — ns *3

VSYNC VC3,

tDD1

VC2,

DD2 ns

VC1, VC0, BLKA,

DD2 tDD1 45 ns

BLKB, BLKC

Unit Remarks

*1: Assumes a dot clock LC oscillator circuit or external dot clock input. *2: Assumes frequency-doubled external dot clock input.

*3: Assumes dot clock external input.

tDCYC1, 2

tDWL1, 2

EXD input

tDH

tDS

HSYNC VSYNC

Inputs

tDD1

Data output

AC measurement conditions C = 70 pF t

r = 5 ns

tf = 5 ns V

OH = 0.8 VDD

VOL = 0.2 VDD VIH = 0.8 VDD VIL = 0.2 VDD

Note: Applicable only when the MB90097 is operating with external dot clock input (not applicable with the LC oscillator circuit).

data

tDWH1, 2

0.8 VDD

0.2 VDD

tDD2

Undefined period Valid data

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

MB90097

(4) Reset input timing

DD = 3.0 V to 3.6 V, VGND = 0 V, Ta = – 40°C to + 85°C)

Parameter Symbol Pin name

Unit Remarks

Min. Max.

Value

Reset pulse width t

WRST RESET 1—µs

Clock input time tWRSD EXD 5 — Dot clock Note

Note: To feed the EXD pin with the dot clock, it is necessary to input the clock during RESEST. Configuring LC

oscillator circuit using the external L and C will eliminate this need because it will automatically oscillate.

t WRST

t WRSD

0.2 V DD

RESET

EXD

MB90097

COMMAND LIST

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1. Display Control Commands

Command

no.

5-00

5-01

5-02

5-2

5-3

6-1

7-3

8-0

8-1

9-0

9-1

11-0 11-2 Dot clock control 1 1011 100000000DC2DC1DC0

13-0 I/O pin control 1101 0 0 VVE VHE HE 0 SIX 0 0 0 DBX DCX 13-1

13-2

Function

VRAM write address setting

Character data setting 1

Character data setting 2

Line control data setting 1

Line control data setting 2

Screen output control 1A

Screen output control 1B

Screen output control 1C

Vertical display position control

Horizontal display position control

Shaded background frame color control

Screen background control

Sprite character control 1

Sprite character control 2

Sprite character control 4

Sprite character control 5

Screen extension control

Horizontal blanking control 1

Horizontal blanking control 2

15 to 1211109876543210

0000 AY3 AY2 AY1 AY0 FL 0 0 AX4 AX3 AX2 AX1 AX0

0001 MS1 MS0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0

0010 MR MO1 MO0 M8 M7 M6 M5 M4 M3 M2 M1 M0

0011 LHS LW2 LW1 LW0 LFD LFC LFB LFA LF3 LF2 LF1 LF0

0100 LDS LGS LG1 LG0 LD LE LM1 LM0 L3 L2 L1 L0

0101 0000SDSUDS0DSP0OA2OA1OA0

0101 0001SOBBGBBLB00OB2OB1OB0

0101 0010SOCBGCBLC00OC2OC1OC0

0101 1 0 0 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0101 1 1 0 X8 X7 X6 X5 X4 X3 X2 X1 X0

0110 0100BH3BH2BH1BH0BS3BS2BS1BS0

0111 11000000U3U2U1U0

1000 0 0 SFB SFA SF3 SF2 SF1 SF0 SC3 SC2 SC1 SC0

1000 0 1 SD1 SD0 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0

1001 0 0 SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0

1001 1 0 SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0

1011 00000EG0000000

1101 010000BB5BB4BB3BB2BB1BB0

1101 1 0 0 BF8 BF7 BF6 BF5 BF4 BF3 BF2 BF1 BF0

Command code/data

MB90097

2. Command Description

• Command 0 (VRAM write address setting)

Command 0 sets the write address in VRAM and controls execution of “VRAM fill.” The sets the write address by specifying the row and column addresses. VRAM fill is activated by executing command 2 (character data setting 2).

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 AY3 AY2 AY1 AY0 FL 0 0 AX4 AX3 AX2 AX1 AX0

AY3 to AY0: Row address

(0 to B

AX4 to AX0: Column address

(0 to 1BH)

FL: VRAM fill control

(0: OFF, 1: ON)

• Command 1 (Character data setting 1)

Command 1 sets character data. Executing command 2 (character data setting 2) sets VRAM to reflect it on the screen.

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 1 MS1 MS0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0

MC3 to MC0: Character color (From among 16 colors) MB3 to MB0: Character background color (From among 16 colors) MM1, MM0: Character background control (0, 0: OFF) (0, 1: Solid-fill display) (1, 0: Concaved, shaded background) (1, 1: Convexed, shaded back

round)

MS1, MS0: Character horizontal size control (0, 0: S size, 6 dots) (0, 1: M size, 9 dots) (1, 0: L size, 12 dots) (1, 1: Setting prohibited)

• Command 2 (Character data setting 2)

Command 2 writes additional character data to the location in VRAM specified by command 0 (VRAM write address setting 1), along with the character data set by command 1 (character data setting 1). The VRAM write address is incremented automatically after execution of command 2.

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 MR MO1 MO0 M8 M7 M6 M5 M4 M3 M2 M1 M0

MR: Shaded background succeeding character merge control (0: Disables succeeding character merge display.) (1: Enables succeeding character merge display.) M8 to M0: Character code

MO1, MO0: Character output control

• Command 3 (Line control data setting 1)

)

Command 3 sets line control data. Executing command 4 (line control data setting 2) sets VRAM to reflect it on the screen.

MB90097

LHS: Line character vertical size type control (0: Character vertical size A) (1: Character vertical size B) LW2 to LW0: Line spacing control (0 to 7 dots in 1-dot units) LF3 to LF0: Trimming color (From among 16 colors)

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 1 LHS LW2 LW1 LW0 LFD LFC LFB LFA LF3 LF2 LF1 LF0

LFD, LFC: Trimming output control (0, 0: All OFF) (0, 1: Trimming ON for character with no character background) (1, 0: Trimming ON for solid-filled character with no character background (1, 1: All ON) LFB, LFA: Trimming control (0, 0: Trimming OFF) (0, 1: Reserved (Setting prohibited)) (1, 0: Reserved (Setting prohibited)) (1, 1: Eight-direction trimming)

• Command 4 (Line control data setting 2)

Command 4 writes additional line control data to the row address in line RAM specified by command 0 (VRAM write address setting), along with the line control data set by command 3 (line control data setting1). Executing this command will not alter the VRAM write address.

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 0 0 LDS LGS LG1 LG0 LD LE LM1 LM0 L3 L2 L1 L0

LDS: Line character output control (Control of character + trimming + character background) (0: OFF, 1: ON) LGS: Line enlargement interpolation control (0: OFF, 1: ON) LG1, LG0: Line enlargement control (0, 0: Normal) (0, 1: Double width) (1, 0: Double height) (1, 1: Double width × double height)

LE: Character background extension control (0: Normal, 1: Extended) LD: Shaded background succeeding line merge control (0: Independent, 1: Merge with the next line) LM1, LM0: Line background control (0, 0: OFF) (0, 1: Solid-fill display) (1, 0: Concaved, shaded display) (1, 1: Convexed, shaded display) L3 to L0: Line background color (From amon

16 colors)

• Command 5-00 (Screen output control 1A)

Command 5-00 controls screen display output.

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 0 1 0 0 0 0 SDS UDS 0 DSP 0 OA2 OA1 OA0

SDS: Sprite character output control (0: OFF, 1: ON)* UDS: Screen background output control (0: OFF, 1: ON)* DSP: Display output control (Control of character + trimming + character background + line background) (0: OFF, 1: ON)*

*: The low level input to the RESET pin initializes the SDS, UDS, and DSP bits to 0.

OA2 to OA0: Output-A character control (From among eight types)

MB90097

• Command 5-01 (Screen output control 1B)

Command 5-01 controls output-B screen display output.

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 0 1 0 0 0 1 SOB BGB BLB 0 0 OB2 OB1 OB0

SOB: Output-B sprite character output control (0: OFF, 1: ON) BGB: Output-B screen background output control (0: OFF, 1: ON) BLB : Output-B line background output control (0: OFF, 1: ON)

OB2 to OB0: Output-B character control (From among eight types)

• Command 5-02 (Screen output control 1C)

Command 5-02 controls output-C screen display output.

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 0 1 0 0 1 0 SOC BGC BLC 0 0 OC2 OC1 OC0

SOC: Output-C sprite character output control (0: OFF, 1: ON) BGC: Output-C screen background output control (0: OFF, 1: ON) BLC : Output-C line background output control (0: OFF, 1: ON)

OC2 to OC0: Output-C character control (From among eight types)

• Command 5-2 (Vertical display position control)

This command controls the vertical display position of the screen.

14131211109 876543210

1 0 1 1 0 0 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

Y8 to Y0: Vertical display position control (0 to 1022 in 2-dot units)

• Command 5-3 (Horizontal display position control)

This command controls the horizontal display position of the screen.

14131211109 876543210

1 0 1 1 1 0 X8 X7 X6 X5 X4 X3 X2 X1 X0

X8 to X0: Horizontal display position control (0 to 1022 in 2-dot units)

• Command 6-1 (Shaded background frame color control)

Command 6-1 controls the frame color of a shaded background.

14131211109 876543210

1 1 0 0 1 0 0 BH3 BH2 BH1 BH0 BS3 BS2 BS1 BS0

BH3 to BH0: Shaded background frame highlight color (From among 16 colors) BS3 to BS0: Shaded background frame shadow color (From among 16 colors)

• Command 7-3 (Screen background control)

Command 7-3 controls the screen background color.

14131211109 876543210

11111000000U3U2U1U0

U3 to U0: Screen background color (From among 16 colors)

MB90097

• Command 8-0 (Sprite character control 1)

This command controls sprite characters.

14131211109 876543210

0 0 0 0 0 SFB SFA SF3 SF2 SF1 SF0 SC3 SC2 SC1 SC0

SFB, SFA: Sprite character trimming control (0, 0: Trimming OFF) (0, 1: Reserved) (1, 0: Reserved) (1, 1: Eight-direction trimming)

• Command 8-1 (Sprite character control 2)

Command 8-1 controls sprite characters.

14131211109 876543210

0 0 0 0 1 SD1 SD0 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0

SD1, SD0: Sprite character configuration control (0, 0: 1 character) (0, 1: Reserved (Setting prohibited)) (1, 0: Stack of 2 characters) (1, 1: Reserved (Setting prohibited))

SF3 to SF0 : Sprite character trimming color (From among 16 colors) SC3 to SC0: Sprite character color (From among 16 colors)

SM7 to SM0: Sprite character code (000

H to 0FFH for 256 different characters)

MB90097

• Command 9-0 (Sprite character control 4)

Command 9-0 controls sprite characters.

14131211109 876543210

0 0 1 0 0 SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0

• Command 9-1 (Sprite character control 5)

This command controls sprite characters.

14131211109 876543210

0 0 1 1 0 SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0

SY9 to SY0: Sprite character vertical display position control (0 to 1023 in 1-dot units)

SX9 to SX0: Sprite character horizontal display position control (0 to 1023 in 1-dot units)

• Command 11-0 (Screen extension control)

(Reserved)

141312111098 76543210

01100 000EG0000000

• Command 11-2 (Dot clock control 1)

Command 11-2 controls the dot clock.

14131211109 876543210

0 1 1 1 0 0 0 0 0 0 0 0 DC2 DC1 DC0

EG0: (Reserved) (0: Normal) (1: Reserved (Setting prohibited))

: Set the EG0 bit to “0”.

DC2 to DC0: Dot clock selection control (0, 0, 0: LC oscillation) (0, 1, 0: External dot clock input) (0, 1, 1: Frequency-doubled external dot clock input)

• Command 13-0 (I/O pin control)

Command 13-0 controls input/output pins.

14131211109 876543210

1 0 1 0 0 VVE VHE HE 0 SIX 0 0 0 DBX DCX

MB90097

VVE: Edge selection for vertical synchronization detection (0: Leading edge, 1: Trailing edge) VHE: HSYNC edge selection for vertical synchronization detection (0: Leading edge, 1: Trailing edge) HE: Edge selection for horizontal synchronization operation (0: Trailing edge, 1: Leading edge)

*: The low level input to the RESET pin initializes the DCX and DBX bits to 0.

SIX : Logic control for sync signal input (0: Negative logic, 1: Positive logic) DCX: Logic control for display color signal output (0: Positive logic, 1: Negative logic)* DBX: Logic control for display output period signal output (0: Positive logic, 1: Negative logic)*

• Command 13-1 (Horizontal blanking control 1)

Command 13-1 controls horizontal blanking (back porch).

14131211109 876543210

1 0 1 0 1 0 0 0 0 BB5 BB4 BB3 BB2 BB1 BB0

BB5 to BB0: Back porch control (0 to 126 in 2-dot units)

• Command 13-2 (Horizontal blanking control 2)

Command 13-2 controls horizontal blanking (front porch).

14131211109 876543210

1 0 1 1 0 0 BF8 BF7 BF6 BF5 BF4 BF3 BF2 BF1 BF0

BF8 to BF0: Front porch control (0 to 1022 in 2-dot units)

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