FUJITSU MB90096 DATA SHEET

查询MB90096供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP For Screen Display Control

CMOS

On-screen Display Controller

MB90096

DESCRIPTION

■

The MB90096 is a multi-scan on-screen display controller that supports horizontal sync signal frequencies of 15
kHz to 120 kHz.The on-screen display configuration is up to 32 characters x 16 lines . The character configuration
is up to 24 dots x 32 dots for high resolution, ideal f or wide-screen TV , HDTV , and high-resolution personal computer
displays.

DS04-28826-5E

The character display functions include sprite character, character background display, and graphics functions,
contributing to the use of colorful GUI displays.

The MB90096 contains display memory (VRAM), character font ROM, and VCO, allowing characters to be dis­played with a minimum of external components. This device also includes command table ROM for storage of
display command data, greatly reducing the load on the microcontroller.

PACKAGES

■

28-pin plastic SH-DIP

(DIP-28P-M03)

28-pin plastic SOP

(FPT-28P-M17)

MB90096

FEATURES

■

• Screen display capacity: Up to 32 characters x 16 lines (512 characters)

• Character configuration:
L size: 24 dots (horizontal) x 2h * dots (vertical)
M size: 18 dots (horizontal) x 2h * dots (vertical)
S size: 12 dots (horizontal) x 2h * dots (vertical)

*: h = 9 to 16

• L, M, S sizes can be selected by individual character

• Graphics characters can be displayed in L or S size only

• Two h values can be set per screen, and either of the two can be selected f or each line on the screen.

• Font types: 512 different fonts included (user selectable over entire screen)

•Display modes:
Normal characters/graphic characters: (set for each character)
Trimmed display (horizontal trimming/pattern back ground): (set for each screen)
Character background (fill/shaded background): (set for each character)
Line background (fill/shaded back ground): (set for each line)
Enlarged (normal, double width, double height, double width x double height): (set for each line)
Blinking: Blinking characters: (set for each character)

Blink period, duty ratio: (set for each screen)

• Sprite character display (graphics display only):

Capable of displaying one b loc k of characters (maximum 2 x 2 char acters) on main screen.
(Can move horizontally and vertically in 2-dot increments.)
Setting applies to the first 256 characters only (character codes 000 to 0FFH).

• Background character display (graphics display only):

Capable of displaying a repeated pattern (2 x 2 characters) on main screen.
Setting applies to the first 256 characters only (character codes 000 to 0FFH).

• Display colors: Character/background colors: 16 colors each (set for each character)

Line background/fill colors: 16 characters each (set for each line)
Screen background colors: 16 colors (set for each screen)
Graphics character dot colors: 16 colors (set for each dot)
Shading background frame colors (highlight/shadow ):

16 colors each (set for each screen)

• Display position control:

Horizontal display start position:Set in 4-dot units (for each screen)
Vertical display start position: Set in 4-dot units (for each screen)
Line spacing control: Set in 2-dot units (for each line)

• Character/color signal output:

ROUT, GOUT, BOUT, IOUT (color signals)
VOB1 (OSD display period output signal)
VOB2 (semi-transparent color period output signal)

• Command transfer function (macro service):

Command table ROM, 16Kbyte included

• Compatible horizontal sync signal frequencies:

15 kHz to 120 kHz (PLL circuit included)

• Microcontroller interface:

16-bit serial input (3 signal input pins)

• Packages: SH-DIP-28, SOP-28

• Power supply voltage: +5 V

2

PIN ASSIGNMENTS

■

MB90096

(TOP VIEW)

CPOUT

AV

VCOIN

AV

RESET

TEST

V

DOCKI

DOCKO

FH

EVEN

1

2

SS

3

4

SS

5

6

7

SS

8

9

10

11

28

27

26

25

24

23

22

21

20

19

18

AV3V

CC

AV

CS

SIN

SCLK

TRE

V

CC

V3V

BOUT (C0)

ROUT (C1)

GOUT (C2)

HSYNC

VSYNC

DISP

12

13

14

(DIP-28P-M03)

(FPT-28P-M17)

17

16

15

IOUT (C3)

VOB1

VOB2

3

MB90096

PIN DESCRIPTIONS

■

Pin
no.

Pin name I/O

1CPOUTO A

3VCOINI B

8DOCKII D

9DOCKOO C

10 FH

11 EVEN I D

12 HSYNC

Circuit

type

O C Output pin for the horizontal sync signal generated by the PLL circuit.

ID

Function

Horizontal sync phase comparison result signal output pin.
Connects to external low-pass filter.

Internal VCO voltage input pin.
Receives voltage signal input from external low-pass filter

Dot clock input pin.
Used only when operating on an externally generated dot clock signal. *
When unused, the horizontal sync signal *2 should be input at this pin.
Internal pull-up resistance included.

Output pin for the dot clock signal generated by the internal VCO.
This signal can be fixed at “H” level by a command.

Field control signal input pin.
This pin is disabled when noninterlaced display or internally generated
field control signals are selected by command.
Internal pull-up resistance included.

Horizontal sync signal input pin.
The period of this signal is used to generate the dot clock signal. The
active level is programmable.
Internal pull-up resistance included.

1

13 VSYNC

14 DISP I D

17

IOUT (C3)

18

GOUT (C2)

19

ROUT (C1)

20

BOUT (C0)

16 VOB1 O C

15 VOB2 O C

24 SCLK I D

25 SIN I D

26 CS

ID

OC

ID

Vertical sync signal input pin.
The active level is programmable.
Internal pull-up resistance included.

Display output (ROUT, GOUT, BOUT, IOUT, VOB1, VOB2) control pin.
When this pin is set to “L” level, the display control is forcibly set to
inactive. Normally, the horizontal and vertical blanking signals are input

3

here. *
Internal pull-up resistance included.

Color signal output pins.
The active level is programmable.

Display period output pin.
The active level is programmable.

Semi-transparent period output signal.
The active level is programmable.

Serial transfer shift clock input pin.
Internal pull-up resistance included.

Serial data input pin.
Internal pull-up resistance included.

Chip select pin.
Set to “L” level for serial transfer.
Internal pull-up resistance included.

(Continued)

4

(Continued)

Pin
no.

Pin name I/O

Circuit

type

MB90096

Function

23 TRE O C

5 RESET

ID

Output pin for indicator that command transfer and fill operations are in
progress. Active “H” level output.

Reset input pin.
Input a “L” level signal *

4

at power-on. Internal pull-up resistance included.

Test signal input pin.

6TEST

ID

Input “H” level (fixed) for normal operation.

Internal pull-up resistance included.
22 VCC +5 V power supply pin.
21 V3V Connect 0.1 µF capacitance between this pin and V

7V

SS Ground pin.

SS.

27 AVCC +5 V power supply pin for VCO.
28 AV3V Connect 0.1 µF capacitance between this pin and AV

2, 4 AV

SS Ground pin for VCO.

SS.

*1: The clock signal should be input even during a reset interval.
*2: The active lev el of the horizontal sync signal input ma y be either “H” or “L” lev el. During reset intervals, including

power-on resets, apply a “L” level fixed signal or a horizontal sync signal with one or more “L” lev el intervals at
the DOCKI pin.

*3: The MB90096 display signals (IOUT, ROUT, GOUT, BOUT, VOB1, VOB2) may be output during horizontal or

vertical blanking intervals. Normally devices such as TV or monitors use a reverence color setting during hori­zontal and vertical blanking intervals, so that during this period the MB90096 display signals must be masked
at the DISP pin signal.

*4: When power is switched on, apply a “L” level signal for 1ms or longer after the V

CC (AVCC) is stabilized.

5

MB90096

I/O CIRCUIT TYPES

■

Type Circuit Remarks

(internal 3 V)

Pch

A

Nch

• CMOS output (internal 3 V)
3-state output

• Analog input

Nch

Pch

B

(5 V)

Pch

• CMOS output (5 V)

C

Nch

• CMOS hysteresis input

(5 V)

Pull-up resistance (approx. 50 kΩ) included

D

6

BLOCK DIAGRAM

■

DISP BOUT

MB90096

VSYNC

EVEN

RESET

CS

SIN

SCLK

TRE

DOCKI

HSYNC

CPOUT

VCOIN

Serial input

control

Command

table ROM

control

Command

table ROM

(16 KByte)

Display control

Display memory

VRAM

(32 char. x 16 line)

Dot clock

Dot clock generator circuit

(PLL circuit)

Font

ROM

(512 char.)

Display

output

control

ROUT

GOUT

IOUT

VOB1

VOB2

FH

DOCKO

7

MB90096

ABSOLUTE MAXIMUM RATINGS

■

Parameter Symbol

CC VSS − 0.3 VSS + 6.0 V *

Power supply voltage

V

AVCC VSS − 0.3 VSS + 6.0 V *

(VSS = AVSS = 0 V Typ)

Rating

Unit Remarks

Min Max

Capacitance pins V3V, AV3V V
Input voltage V

IN VSS − 0.3 VCC + 0.3 V

SS − 0.3 VSS + 3.6 V

Output voltage VOUT VSS − 0.3 VCC + 0.3 V
Power consumption Pd  600 mW
Operating temperature Ta −40 +85 °C
Storage temperature Tstg −55 +150 °C

*: AVcc and Vcc must have equal potential.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

■

(VSS ==== AVSS ==== 0 V Typ)

Value

Parameter

Symbol

Unit

Remarks

Min Max

V

CC 4.5 5.5 V Specification guarantee range

Power supply voltage

AV

CC 4.5 5.5 V *1

“H” level input voltage V
“L” level input voltage V

IHS 0.8 × VCC VCC + 0.3 V

ILS2 VSS − 0.3 0.2 × VCC V

Operating temperature Ta −40 +85 °C
Analog input voltage V

IN 0 3.0 V VCOIN input *

2

Smoothing
capacitor
(capacitance pin)

C

S 0.1 1.0 µF

Use a ceramic capacitor or other capacitor having
equivalent frequency characteristics. The capacitance
at the Vcc and AVcc pins must be greater than Cs.

*1: AVcc and Vcc must have equal potential.
*2: This recommended input voltage range does not imply that stable PLL operation is warranted. For stable PLL

operation it is recommended that input voltage be between 1.0 V and 2.5 V. Note however that PLL operating
status is greatly affected by variations in the input horizontal sync signal period, as well as external filter settings
and operating temperature, etc. Thorough testing and evaluation is recommended.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

8

ELECTRICAL CHARACTERISTICS

■

1. DC Characteristics

Parameter

Symbol

(VSS = AVSS = 0 V, Ta = -40 °C to +85 °C)

Pin name Condition

MB90096

Value

Unit

Min Typ Max

“H” level output voltage 1 V

All output pins

OH1

except CPOUT pin

“H” level output voltage 2 VOH2 CPOUT pin

“L” level output voltage V

Pull-up resistance R

Input leak current I

Power supply current I

Input capacitance C

*: Power supply pins: V

CC, AVCC, VSS, AVSS, Capacitance pins: V3V, AV3V

OL All output pins

All input pins

PULL

except VCOIN pin

IL VCOIN pin

CC VCC + AVCC

Other than power
supply and

IN

capacitance pins

VCC = AVCC = 4.5 V,
I

OH = −4.0 mA

VCC = AVCC = 4.5 V,
I

OH = −4.0 mA

VCC = AVCC = 4.5 V,
I

OL = 4.0 mA

4.0 V

2.5 V

0.4 V

VCC = AVCC = 5.5 V 20  100 kΩ
VCC = AVCC = 5.5 V,

V

SS < VIL < VCC

VCC = AVCC = 5.5 V (no load),
Dot clock 60 MHz

−10  10 µA

40 mA

Dot clock 40 MHz 30 mA
Dot clock 20 MHz 20 mA

10  pF

*

9

MB90096

2. AC Characteristics

(1) Serial Input Timing

Parameter Symbol Pin name

Shift clock cycle time t

(V

CC =

= AVCC ==== 5.0 V ± 10%, VSS = AVSS = 0 V, Ta ==== −40 °°°°C to +85 °°°°C)

==

Value

Unit Remarks

Min Max

CYC SCLK 250  ns

Shift clock pulse width

Shift clock signal rise/fall time

Shift clock start time t

WCH

t

SCLK

WCL 100  ns

t

tCR

SCLK

CF  200 ns

t

SS SCLK 100  ns

100  ns

 200 ns

Data setup time tSU SIN 100  ns
Data hold time t
Chip select end time t

Chip select signal rise/fall time

••••

Serial input timing

CS

tCFC

0.8 VCC

0.2 VCC

tSS

H SIN 50  ns

EC CS 100  ns

tCRC

 200 ns

CS

t

CFC  200 ns

tCYC

tEC

0.8 VCC

0.2 VCC

tCRC

10

SCLK

SIN

tCR

tWCH

tCF

tSU

0.8 VCC

0.2 VCC

tWCL

tH

0.8 VCC

0.2 VCC

(2) Vertical and horizontal sync signal input timing

(V

CC =

= AVCC ==== 5.0 V ±±±± 10%, VSS ==== AVSS ==== 0 V, Ta ==== −40 °°°°C to +85 °°°°C)

==

Parameter Symbol Pin name

Value

Min Max

MB90096

Unit

Remarks

Horizontal sync signal rise time t

HR

 500 ns

HSYNC

Horizontal sync signal fall time t
Vertical sync signal rise time t

HF  500 ns

VR

 500 ns

VSYNC

Vertical sync signal fall time tVF  500 ns
Horizontal sync signal pulse

1

width *
Vertical sync signal pulse width t

Horizontal sync signal setup time t

tWH HSYNC

WV VSYNC 220 H

DHST

18  Dot clock
 6 µs

6  ns *2

HSYNC

Horizontal sync signal hold time t
Vertical sync signal setup time tHVST

DHHD 3  ns *2

41H − 4 Dot clock

VSYNC

Vertical sync signal hold time t
Vertical sync signal setup time

when field signal is generated
Vertical sync signal hold time

when field signal is generated

HVHD 220 H

t

EVST VSYNC 18  Dot clock *3

tEVHD VSYNC 18  Dot clock *3

*1: The horizontal sync pulse time is applied after MB90096 internal operations have paused and horizontal operation

has been synchronized. For this reason it is necessary to leav e an interval between commands so that writing
to VRAM (command 2, 4) is not performed more than once.
It is necessary to set the horizontal sync signal pulse width and interval f or writing to VRAM so that the horizontal

sync signal pulse width is less than the writing interval to VRAM.
*2: Applied when an external dot clock signal is input.
*3: Applied in interlaced display, when the EVEN signal is applied from an external source.

••••

Vertical and horizontal sync signal input timing

HSYNC

VSYNC

tHF

tVF

0.8 VCC

0.2 VCC

tWH

0.8 VCC

0.2 VCC

tWV

0.8 VCC

0.2 VCC

tHR

0.8 VCC

0.2 VCC

tVR

11

MB90096

••••

Horizontal sync signal setup and hold timing

DOCKI

0.8 VCC

0.2 VCC

tDHST

0.8 VCC

HSYNC

••••

Vertical sync signal setup and hold timing

HSYNC

VSYNC

HSYNC

: VSYNC detection at front edge (VHE = 0)

0.2 VCC

tHVST

0.8 VCC

tDHHD

0.8 VCC

0.2 VCC

tHVHD

0.2 VCC0.2 VCC

0.2 VCC

12

••••

Vertical sync signal setup and hold timing

HSYNC

VSYNC

HSYNC

: VSYNC detection at back edge (VHE = 1)

tHVST

0.2 VCC

tHVHD

0.2 VCC0.2 VCC

0.8 VCC

MB90096

••••

EVEN signal generation timing

Detection of EVEN = 1
(V alid with settings for internal field signal generation [FLD = 0], and dot clock internal generation [DCO = 0].)

3H/4

H/4

HSYNC

0.2 VCC

VSYNC

0.8 VCC

t

EVHD

0.2 VCC

tEVST

Chip internal generation

field signal *

••••

EVEN signal generation timing

Detection of EVEN = 0
(V alid with settings for internal field signal generation [FLD = 0], and dot clock internal generation [DCO = 0].)

H/4H/4

HSYNC

0.2 VCC

VSYNC

Chip internal generation

field signal *

0.8 VCC

t

EVHD

0.2 VCC

tEVST

*: Sample of internal generation without field signal correction (command 11-0 FC = 0)
Note: In a normal NTSC signal, H/4 = 63.5 µs / 4 := 15.9 µs, 3H/4 := 47.6 µs.

13

MB90096

••••

EVEN signal input timing

(Valid with settings for external field signal input [FLD = 1].)

VSYNC

Video signal

EVEN

Note: There is no numerical standard for EVEN signal input timing.

Set so that the signal changes during the V blanking interval when no video signal is output.

V blanking

V blanking

14

(3) Display signal timing

Parameter Symbol Pin name

MB90096

(V

CC =

= AVCC ==== 5.0 V ±±±± 10%, VSS ==== AVSS ==== 0 V, Ta ==== −40 °°°°C to +85 °°°°C)

==

Value

Min Max

Unit Remarks

Dot clock input frequency f
Dot clock input cycle time t

Dot clock input pulse width

DCK DOCKI 7 60 MHz
DCK DOCKI 16.7 142.8 ns

DIWH

t

7  ns

DOCKI

DIWL 7  ns

t

ROUT, GOUT,

Display signal output mask timing t

MASK

BOUT, IOUT,

530ns

VOB1, VOB2
Dot clock output delay t
Display signal output delay 1 tRGB1 ROUT, GOUT,

DLIO DOCKO 12 24 ns

21 33 ns

BOUT, IOUT,
Display signal output hold time 1 t

Display signal output delay 2 t

RGB1HD tRGB1 − 11 ns

RGB2 ROUT, GOUT,

VOB1, VOB2

 9ns

BOUT, IOUT,
Display signal output hold time 2 t

output delay tDLFH FH −55ns

FH

••••

Display signal output mask timing

DISP

RGB2HD − 2  ns

0.2 VCC

VOB1, VOB2

0.8 VCC

tMASK tMASK

ROUT, GOUT
IOUT, BOUT
VOB1, VOB2

0.2 VCC

0.8 VCC

Note: • Display related output logic is written in normal logic settings[command 13-0: DHX = DBX = DCX = 0].

• Sync signal input logic is written in inverse logic settings [command 13-0: SIX = 0].

15

MB90096

••••

Display signal output delay

Prescaler setting: 1/1 (DP1 = 0, DP0 = 0)

CC

DOCKI

DOCKO

ROUT, GOUT
IOUT, BOUT
VOB1,VOB2

0.8 V

tDLIO

0.8 VCC

tRGB2

tRGB1

0.8 VCC

0.2 VCC

VALID

tDCK

tDIWH

0.8 VCC

0.2 VCC 0.2 VCC 0.2 VCC

tRGB1HD

0.8 VCC

0.2 VCC

tDIWL

0.8 VCC

0.8 VCC

tRGB2HD

16

••••

FH output delay

DOCKO

FH

0.8 VCC

tDLFH

0.8 VCC

tDLFH

0.8 VCC

0.2 VCC

(4) Power supply input, reset input timing

(V

Parameter Symbol Pin name

MB90096

CC =

= AVCC ==== 5.0 V ±±±± 10 %, VSS ==== AVSS ==== 0 V, Ta ==== −40 °°°°C to +85 °°°°C)

==

Vlaue

Min Max

Unit Remarks

Power supply rise time t
Reset input at power on t
Reset input with power stabilized t

PON VCC, AVCC 100 µs*
PRT RESET 1  ms
RST RESET 10 µs

*: Ensure that the slope of the power supply rise (∆V/∆t) does not exceed 0.05 V/µs.

••••

Po wer-on and reset input timing

tPON

VCC, AVCC

RESET

0.2 V

CC

0.8 VCC

tPRT tRST

0.2 VCC 0.2 VCC 0.2 VCC

AC rating measurement conditions
C = 28 pF
t

r = 5 ns

t

f = 5 ns

V

OH = 0.8 VCC

VOL = 0.2 VCC
VIH = 0.8 VCC
VIL = 0.2 VCC

17

MB90096

COMMAND LIST

■

1. Command List

Command

no.

0 Set VRAM write address 0000 AY3 AY2 AY1 AY0 FL 0 0 AX4 AX3 AX2 AX1 AX0
1 Character data 1 0001 MS1 MS0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0
2 Character data 2 0010 MR MG MBL M8 M7 M6 M5 M4 M3 M2 M1 M0
3 Line control data 1 0011 LHS LW2 LW1 LW0 LFD LFC LFB LFA LF3 LF2 LF1 LF0
4 Line control data 2 0100 LDS 0 LG1 LG0 LD LE LM1 LM0 L3 L2 L1 L0
5-0 Screen output control 1 0101 0 0 0 0 SDS UDS PDS DSP 0 0 0 0
5-1 Screen output control 2 0101 0 1 FM1 FM0 BT1 BT0 BD1 BD0 0 0 0 0

5-2

5-3

6-0

6-1

6-2
6-3 Graphic color control 0110 1 1 GF GC GF3 GF2 GF1 GF0 GC3 GC2 GC1 GC0
7-1

7-3
8-1 Sprite character control 1 1000 0 1 SD1 SD0 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0

8-2 Sprite character control 2 1000 1 0 1 SBL 0 SH2 SH1 SH0 0 0 0 0
9-0 Sprite character control 3 1001 0 0 SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0
9-1 Sprite character control 4 1001 1 0 SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0
11-0 Sync control 1011 0 0 0 0 EG1 EG0 0 FC0 FLD 0 0 0
11-2 Dot clock control 1 1011 1 0 DO 0 0 0 DP1 DP0 0 0 0 DC0
11-3 Dot clock control 2 1011 1 1 DK9 DK8 DK7 DK6 DK5 DK4 DK3 DK2 DK1 DK0
13-0 I/O pin control 1101 0 0 0 VHE 0 0 SIX 0 0 DHX DBX DCX

14-0

14-1

14-2

14-3

Function

Vertical display position
control

Horizontal display
position control

Character vertical size
control

Shading background
frame color control

Transparent / semi­transparent color control

Screen background
character control 1

Screen background
character control 2

CROM transfer start
address 1

CROM transfer start
address 2

CROM transfer end
address 1

CROM transfer end
address 2

15 to 12 11 10 9 8 7 6 5 4 3 2 1 0

0101 1 0 0 Y8Y7Y6Y5Y4Y3Y2Y1Y0

0101 1 1 0 X8X7X6X5X4X3X2X1X0

0110 0 0 0 0 0 HB2 HB1 HB0 0 HA2 HA1 HA0

0110 0 1 0 0 BH3 BH2 BH1 BH0 BS3 BS2 BS1 BS0

0110 1 0 TC HC TC3 TC2 TC1 TC0 HC3 HC2 HC1 HC0

0111 0 1 1 1 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

0111 1 1 1 0 0 PH2 PH1 PH0 U3 U2 U1 U0

1110 0 0 0 0 0 0 TSD TSC TSB TSA TS9 TS8

1110 0 0 1 0 TS7 TS6 TS5 TS4 TS3 TS2 TS1 0

1110 0 1 0 0 0 0 TED TEC TEB TEA TE9 TE8

1110 0 1 1 TSV TE7 TE6 TE5 TE4 TE3 TE2 TE1 1

Command code/data

(Continued)

18

MB90096

(Continued)

Notes: • Initial values are undefined for the VRAM and line VRAM settings in commands 0, 1, 2, 3, and 4. Therefore

all VRAM and line VRAM values must be initialized by issuing commands. (FIL functions are valid for all
VRAM initializations.)

• The initial value for command 5-0 and command 13-0 is "0" f or all bits. Howev er, to protect against abnormal
operation due to causes such as external noise, initial settings should be made to all commands *.

*: Initial settings should be made for all commands other than the command ROM transf er commands (command

14-0 through 14-3). Note that initial settings for command 0 through command 9-1 ma y be stored in command
ROM, and initialized by command ROM transfer.

2. Command content

••••

Command 0 (Set VRAM write address)

1514131211109876543210

0000AY3AY2AY1AY0FL00AX4AX3AX2AX1AX0

AY3-AY0 : Line address (0 to F

[Functions]

Command 0 specifies the write address in VRAM memory.
This command is used to specify the line and column address before using commands 1 and 2 to set character

data, and to specify the line address before using commands 3 and 4 to set line control data.

[Description]

• Normal writing (writing in units of 1 character data or 1 line control data) is done with the VRAM fill setting
OFF (FL = 0).

• After executing command 2, the VRAM address is incremented automatically. (At the end of a column, the
address is incremented to the head of the next column, and at the end of the last line the address is incremented
to the head of the next page.)

• If the VRAM fill setting (FL=1) is used, the same character data (specified by commands 1, 2) is written to all
addresses from the line and column address specified by command 0 to the end of the page. VRAM fill is
ex ecuted b y the set char acter data 2 command (command 2). When this command is executing, the TRE pin
output is at "H" level.

Notes: • When command 3 and 4 settings (line control data) are in effect, the column address values in this command

(AX4-AX0) are ignored.

• VRAM addresses are not incremented automatically by executing commands 3 and 4 (line control data).

• VRAM fill settings are valid only for commands 1 and 2 (character data).

• When VRAM fill is executing, commands 1-4 may not be issued.

H) AX4-AX0 : Column address (0 to 1FH)

FL : VRAM file setting (0 : OFF, 1 : ON)

19

MB90096

••••

Command 1 (Character data 1)

1514131211109876543210

0001MS1MS0MM1MM0MB3MB2MB1MB0MC3MC2MC1MC0

MC3-MC0: Character color (16 colors)
MB3-MB0: Character background color

(16 colors)

MM1, MM0:Character background control

(0, 0 : OFF)
(0, 1 : Fill in)
(1, 0 : Shaded concave)
(1, 1 : Shaded convex)

[Function]

Command 1 sets character data. This data is written in VRAM and displayed on the screen by executing the
character data 2 command (command 2).

[Description]

• The character color, background color, character background type, and horizontal size can be set in any
combination, for each character separately.

• Shading can be oriented towards, top, bottom, r ight, or left using a combination of the MR bit in command 2
and the LD and LE bits in command 4.

• Shading background frame color settings are made using command 6-1.

Note: These settings are not available for M size graphics characters.

MS1, MS0: Character horizontal size control

0, 0: 12-dot
0, 1: 18-dot
1, 0: 24-dot
1, 1: (prohibited)

20

••••

Command 2 (Character data 2)

1514131211109876543210

0010MRMGMBLM8M7M6M5M4M3M2M1M0

MB90096

MR: Shaded background right-character fusion

control
(0: No fusion with right-character)
(1: Fusion with right-character)

M8-M0: Character code

[Function]

Command 2 writes the character data set by the character data 1 command (command 1) as well as the data
contained in this command to the VRAM address specified by the VRAM write address command (command 0).

After command 2 is executed, the VRAM write address is automatically incremented.

[Description]

• The blinking control setting (MBL=1) causes the display to blink according to the settings of the BT1, BT0,
BD1, BD0 bits in command 5-1.

• The shaded background right-character fusion control bit (MR) is used only with characters having the shading
setting specified in command 1 (MM1=1).

Notes: • Because all VRAM settings are undefined after a reset, it is necessary to enter all VRAM settings bef ore

executing a display.

•These settings are not available for M size graphics characters.

••••

Command 3 (Line control data 1)

1514131211109876543210

MG: Character/graphics character control

(0: character, 1: graphics character)

MBL: Blinking control (0: OFF, 1: ON)

0011LHSLW2LW1LW0LFDLFCLFBLFALF3LF2LF1LF0

LHS: Line character vertical size type

(0: Character vertical size A)
(1: Character vertical size B)

LW2-LW0: Line spacing control

(0-14 dots, in 2-dot increments)

LF3-LF0: Trimming color (16 colors)

[Function]

Command 3 sets line control data. This data is written in VRAM and reflected on the screen display when the
line data 2 command (command 4) is executed.

[Description]

• Command 6-0 (Character vertical size control) determines the specification of the actual size of the characters
controlled by the line character vertical size type setting (LHS).

• The trimming format is specified by the FM1, FM0 bits in command 5-1 (Trimming format control).

LFD, LFC: Trimming output control

(0,0: All OFF)
(0,1: Trimming ON for characters without

background only)

(1,0: Trimming ON for characters without

background and filled characters only)

(1,1: Trimming output ON)

LFB, LFA: Trimming control

(0,0: Trimming OFF)
(0,1: Right trimming)
(1,0: Left trimming)
(1,1: Left and right trimming)

21

MB90096

••••

Command 4 (Line control data 2)

1514131211109876543210

0100LDS0LG1LG0LDLELM1LM0L3L2L1L0

LDS: Line character output control

(0: OFF, 1: ON)

LG1, LG0: Line expansion control

(0:,0: Normal)
(0,1: Double width)
(1,0: Double height)
(1,1: Double height and width)

[Function]

Command 4 writes the line control data set by the line control data 1 command (command 3) as well as the data
contained in this command to the VRAM address specified by the VRAM write address command (command 0).

Notes: • Because all VRAM settings are undefined after a reset, it is necessary to enter all VRAM settings before

executing a display.

• Executing this command does not cause automatic incrementing of the VRAM write address. The address
must be set by command 0 for each line for which this command is executed.

••••

Command 5-0 (Screen output control 1)

1514131211109876543210

LE: Character background expansion control

(0: Normal, 1: Expanded)

LD: Shaded background lower side fusion control

(0: Not fused, 1: Lower side fused)

LM1, LM0: Line background control

(0,0: OFF)
(0,1: Fill display)
(1,0: Shaded concave display)
(1,1: Shaded convex display)

L3-L0: Line background color (16 colors)

01010000SDSUDSPDSDSP0000

SDS: Sprite character output control

(0: OFF, 1: ON)

UDS: Screen background output control

(0: OFF, 1: ON)

[Function]

Command 5-0 controls screen display output.

Note: When the display is turned ON by turning the SDS, PDS, UDS, DSP bits ON, starting from a state in which

at least one of those bits is already ON, it may happen that the displa y screen (characters) appear displaced
vertically by the amount of the initial field in the setting.

PDS: Screen background character output control

(0: OFF, 1: ON)

DSP: Display output control

(Character + trimming + character
background + line background control)
(0: OFF, 1: ON)

22

••••

Command 5-1 (Screen output control 2)

1514131211109876543210

010101FM1FM0BT1BT0BD1BD00000

MB90096

BT1, BT0: Blinking period control

(0,0: 16 V)
(0,1: 32 V)
(1,0: 48 V)
(1,1: 64 V)

BD1, BD0: Blinking duty control

(0,0: On:off = 1:0 (always on))
(0,1: On:off = 1:1)
(1,0: On:off = 1:3)
(1,1: On:off = 3:1)

[Function]

Command 5-1 controls screen display output.

[Description]

The blinking control bits of this command are applied to characters f or which blinking control is specified (MBL=1)
in command 2, as well as sprite characters for which blinking control is specified (SBL=1) in command 8-2.

••••

Command 5-2 (Vertical display position control)

1514131211109876543210

0101100Y8Y7Y6Y5Y4Y3Y2Y1Y0

FM1, FM0: Trimming format control

(0,0: Horizontal trimming 1 dot)
(0,1: Horizontal trimming 2 dots)
(1,0: Pattern background 1)
(1,1: Pattern background 2)

Y8-Y0: Vertical display position control

(0-2044, in 4-dot units)

[Function]

Command 5-2 controls the vertical display position on the screen.

••••

Command 5-3 (Horizontal display position control)

1514131211109876543210

0101110X8X7X6X5X4X3X2X1X0

X8-X0: Horizontal display position control

[Function]

Command 5-3 controls the horizontal display position on the screen.

(0-2044, in 4-dot units)

23

MB90096

••••

Command 6-0 (Character vertical size control)

1514131211109876543210

011000000HB2HB1HB00HA2HA1HA0

HB2-HB0: Character vertical size control B

(18-32 dots, in 2-dot units)

HA2-HA0: Character vertical size control A

(18-32 dots, in 2-dot units)

[Function]

Command 6-0 controls the vertical size of character types A and B.

[Description]

This command specifies the actual values of the vertical size settings (LHS=0: Size A, LHS=1: Size B) for
individual lines in command 3.

••••

Command 6-1 (Shading background frame color)

1514131211109876543210

01100100BH3BH2BH1BH0BS3BS2BS1BS0

BH2-BH0: Shaded background frame highlight

color (16 colors)

BS2-BS0: Shaded background frame shadow

color (16 colors)

[Function]

Command 6-1 controls the frame color of the shading background.

[Description]

• This command sets the frame color for characters for which shaded character background is specified in
command 1 (MM1=1), as well as shading background for lines for which shaded line background is specified
in command 4 (LM1=1).

• The highlight color indicates the color of the left and top edges of the character area when convex shaded
character background is selected, or the color of the top edge of the line area when convex shaded line
background is selected.

• The shadow color indicates the color of the right and bottom sides of the character area when conve x shaded
character background is selected, or the color of the bottom edge of the line area when convex shaded line
background is selected.

• When concave shaded character background or concave shaded line background is selected, the highlight
and shadow colors are the reverse of those selected for convex display.

24

••••

Command 6-2 (Transparent / semi-transparent color control)

1514131211109876543210

011010TCHCTC3TC2TC1TC0HC3HC2HC1HC0

MB90096

TC: Transparent color control (0: OFF, 1: ON)
HC: Semi-transparent color control (0: OFF, 1: ON)

[Function]

Command 6-2 controls the transparent and semi-transparent color settings.

[Description]

• The setting TC=1 causes areas of the designated transparent color (TC3-TC0) to be excluded (so that the
color behind those areas shows through).

• The setting HC=1 causes areas of the designated semi-transparent color (HC3-HC0) to be excluded at the
same time a semi-transparent interval signal output from the VOB2 pin, so that the signal can be used by
external circuits to reduce brightness, etc.

Notes: • If both the transparent and semi-transparent settings are selected at the same time, they should be set f or

different colors.

• The semi-transparent interval signal output from the VOB2 pin is applied to areas other than the main
screen character, trimming, and graphics areas.

••••

Command 6-3 (Graphic color control)

1514131211109876543210

011011GFGCGF3GF2GF1GF0GC3GC2GC1GC0

GF: Graphic color trimming color replacement

control (0: OFF, 1: ON)

GC:Graphic color character color replacement

control (0: OFF, 1: ON)

[Function]

TC3-TC0: Transparent color code (16 colors)
HC3-HC0: Semi-transparent color code (16 colors)

GF3-GF0: Trimming color replacement color code

(16 colors)

GC3-GC0:Character color replacement color code

(16 colors)

Command 6-3 controls the replacement of a specified color in graphics characters with the character color or
trimming color.

[Description]

• Graphics characters are registered in font ROM in fixed colors, but this command allows two of the 16 colors
to be designated for replacement as the trimming color and character color.

• The setting GF=1 causes areas of the color specified as the trimming color to be replaced by the color that is
designated as the trimming color for that line (by command 3).

• The setting GC=1 causes areas of the color specified as the character color to be replaced by the color that
is designated as the character color for that line (by command 1).

Notes: • This command applies only to colors of graphics characters in a main screen display.

• If both the trimming color replacement and character color replacement settings are selected at the same
time, they should be set for different colors.

• Transparent and semi-transparent colors are applied to colors after replacement.

25

MB90096

••••

Command 7-1 (Screen background character control 1)

1514131211109876543210

01110111PM7PM6PM5PM4PM3PM2PM1PM0

PM7-PM0: Screen background character code

(000

H to 0FFH, 256 types)

[Function]

Command 7-1 controls screen background characters.

[Description]

• The display can be started by using command 5-0 to turn screen background character output control ON
(PDS-1).

• V ertical character size can be set by command 7-3 f or screen background character v ertical size control (PH2­PH0).

Notes: • Screen background characters can only be selected from the first 256 or the 512 characters , using character

codes in multiples of 4 (PM1=0, PM0=0).

• Only graphics character arrays of 2 characters wide x 2 characters high may be designated.

• Screen background character replacement colors (command 6-3) may not be applied.

••••

Command 7-3 (Screen background character control 2)

1514131211109876543210

011111100PH2PH1PH0U3U2U1U0

PH2-PH0: Screen background character vertical

size control (18-32 dots, in 2-dot units)

U3-U0: Screen background color (16 colors)

[Function]

Command 7-3 controls screen background characters and the screen background color.

[Description]

• The screen background color is displa yed by using command 5-0 to turn the screen background output control
ON (UDS=1).

• The screen background characters are displayed by using command 5-0 to turn the screen background
character output control ON (PDS=1).

26

••••

Command 8-1 (Sprite character control 1)

1514131211109876543210

100001SD1SD0SM7SM6SM5SM4SM3SM2SM1SM0

MB90096

SD1, SD0: Sprite character configuration control

(0,0: 1 character)
(0,1: Horizontal 2 characters)
(1,0: Vertical 2 characters)
(1,1: Vertical 2 x horizontal 2 characters)

[Function]

Command 8-1 controls sprite characters.

[Description]

• Sprite character display is started by using command 5-0 to turn sprite character output control ON (SDS=1).

• The sprite character start position is set by command 9-0 and command 9-1.

• Ver tical size is controlled by using command 8-2 to set the sprite character vertical size control (SH2-SH0),
and blinking is controlled by the sprite character blinking control bit (SBL).

• The sprite character blinking period and duty are controlled by the BT1, BT0, BD1, and BD0 bits in command
5-1.

Notes: • Sprite characters may only be selected from the first 256 of the 512 characters.

• For configurations of 2 characters or greater , only characters codes in multiples of 4 (SM1=0, SM0=0) ma y
be used.

• Sprite characters are always displayed in graphic character displays

• Replacement color control (command 6-3) cannot be applied to sprite characters.

SM7-SM0:Sprite character codes

(000

H to 0FFH, 256 types)

••••

Command 8-2 (Sprite character control 2)

1514131211109876543210

1000101SBL0SH2SH1SH00000

SBL:Sprite character blinking control

(0: OFF, 1: ON)

[Function]

Command 8-2 controls sprite characters.

••••

Command 9-0 (Sprite character control 3)

1514131211109876543210

100100SY9SY8SY7SY6SY5SY4SY3SY2SY1SY0

[Function]

Command 9-0 controls the sprite character vertical display position.

SH2-SH0:Sprite character vertical size control

SY9-SY0: Sprite character vertical display position

(18-32 dots, in 2-dot units)

control (0-2046, in 2-dot units)

27

MB90096

••••

Command 9-1 (Sprite character control 4)

1514131211109876543210

100110SX9SX8SX7SX6SX5SX4SX3SX2SX1SX0

SX9-SX0: Sprite character horizontal display

position control (0-2046, in 2-dot units)

[Function]

Command 9-1 controls the sprite character horizontal display position.

[Description]

For information related to sprite character settings, see the description under command 8-1.

••••

Command 11-0 (Sync control)

1514131211109876543210

10110000EG1EG00FC0FLD000

EG1, EG0: Vertical enlargement control

(0,0: Interlaced)
(0,1: Non-interlaced )
(1,0: Setting prohibited)
(1,1: Vertical 2x)

[Function]

Command 11-0 controls the synchronization system.

[Description]

• The vertical display area is adjusted by the combination of vertical enlargement control (EG1, EG0) and the
scan method. This setting is applied to all vertical count parameters (display position, dot size).

• If interlaced display (EG1=0, EG0=0) is used, the field 0 signal input control (FLD) is used to select either an
internally generated field signal or an externally input signal. If an external input is used the field signal must
be input from the EVEN pin.

FC0: Field 0 correction control

Field E-0 conversion
(0: No correction, 1: Correction)

FLD: Field 0 signal input control

(0: Internal separation generation,
1: External input)

28

••••

Command 11-2 (Dot clock control 1)

1514131211109876543210

101110DO000DP1DP0000DC0

MB90096

DO: Dot clock pin output control

(0: OFF, 1: ON)

DP1, DP0: Dot clock prescaler control

(0,0: 1/1)
(0,1: 1/2)
(1,0: 1/4)
(1,1: 1/8)

[Function]

Command 11-2 controls the dot clock signal.

[Description]

The internal dot clock signal can be output from the DOCKO pin by setting the dot clock pin output control to
ON (DO=1).

Note: If no external dot clock signal is needed, it is recommended that the dot clock pin output control be set to

OFF (DO=0) to keep noise to a minimum.

••••

Command 11-3 (Dot clock control 2)

1514131211109876543210

101111DK9DK8DK7DK6DK5DK4DK3DK2DK1DK0

DC0: Dot clock selection control

(0: external input, 1: internal VCO (H-PLL)

DK9-DK0: Dot clock multiplier value (4-dot units)

[Function]

Command 11-3 adjusts the dot clock frequency.

[Description]

This command sets the number by which the prescaler multiplies the input dot clock signal to produce the
horizontal sync signal period (in 4-dot units).

Notes: • Settings lower than 040

• This setting is necessary only when an internal VCO signal is used.

H may not be used.

29

MB90096

••••

Command 13-0 (I/O pin control)

1514131211109876543210

1101000VHE00SIX00DHXDBXDCX

SIX: Sync signal input logic control

(0: inverse logic, 1: normal logic)

DCX: Display color signal output logic control

VHE: Vertical sync detection HSYNC edge

selection (0: Front edge, 1: back edge)

[Function]

Command 13-0 controls the input-output pin functions.

[Description]

This command can eliminate vertical movement (dancing) by using the ver tical sync detection HSYNC edge
selection (VHE) to adjust the vertical sync signal and horizontal sync signal input timing.

(0: normal logic, 1: inverse logic)

DBX: Display output period signal logic control

(0: normal logic, 1: inverse logic)

DHX: Semi-transparent period signal output logic

control (0: normal logic, 1: inverse logic)

Note: The sync signal input logic control bit (SIX) is applied to both the vertical sync signal and horizontal sync signal.

••••

Command 14-0 (Command ROM transfer start address 1)

1514131211109876543210

1110000000TSDTSCTSBTSATS9TS8

TSD-TS8: Command ROM transfer start address 1

(high address)

[Function]

Command 14-0 is used for the command ROM transfer start address 1 setting.

[Description]

This command sets the upper half of the starting address for a command ROM transfer.

••••

Command 14-1 (Command ROM transfer start address 2)

1514131211109876543210

11100010TS7TS6TS5TS4TS3TS2TS10

TS7-TS1: Command ROM transfer start address 2

(low address)

[Function]

Command 14-1 is used for the command ROM transfer start address 2 setting.

[Description]

This command sets the lower half of the starting address for a command ROM transfer.

30

••••

Command 14-2 (Command ROM transfer end address 1)

1514131211109876543210

1110010000TEDTECTEBTEATE9TE8

TED-TE8: Command ROM transfer end address 1

(high address)

[Function]

Command 14-2 is used for the command ROM transfer end address 1 setting.

[Description]

This command sets the upper half of the ending address for a command ROM transfer.

••••

Command 14-3 ( Command ROM transfer end address 2)

1514131211109876543210

1110011TSVTE7TE6TE5TE4TE3TE2TE11

MB90096

TSV: Command ROM transfer sync control

(0: Not synchronized, 1: V synchronized)

[Function]

Command 14-3 is used for the command ROM transfer end address 2 setting.

[Description]

• This command sets the lower half of the ending address for a command ROM transfer.

• Turn the command ROM transf er sync control ON (TSV=1) to start a transfer in sync with the front edge of the
vertical sync signal.

• When the command ROM transfer sync control is OFF (TSV=0), a transfer is started when this command is
issued.

Note: If command ROM transfer sync control is used, it is necessary to use the screen output control command

(command 5-0) to turn one of the output control bits (SDS, PDS, UDS, DSP) ON.

TE7-TE1: Command ROM transfer end address 2

(low address)

31

MB90096

■ SAMPLE APPLICATION CIRCUIT

12 20

HSYNC

13

14

VSYNC

DISP

Sync

separation

MB90096

BOUT

ROUT

GOUT

19

18

VCC : +5 V (digital)
GND : Ground (digital)
AV

CC : +5 V (analog)

AGND : Ground (analog)

Display

controller

Microcontroller

VCC

10 µF

+

GND

0.1 µF

0.1 µF

11

26

25

24

23

22

21

EVEN

8

DOCKI

CS

SIN

SCLK

TRE

VCC

V3V

V

SS

7

VOB1

VOB2

DOCKO

TEST

RESET

IOUT

17

16

15

9

CC

V

6

5

Reset

32

AVCC

27

AVCC

+

AGND

10 µF

0.1 µF

0.1 µF

28

AV3V

2

AV

SS

4

AVSS

* : Must be adjusted according to usage conditions

VCOIN

CPOUT

3

*

R1

1

C2

R2

AGND

C1

AGND

ORDERING INFORMATIONS

■

Part number Package Remarks

MB90096

MB90096P

MB90096PF

28-pin plastic SH-DIP

(DIP-28P-M03)

28-pin plastic SOP

(FPT-28P-M17)

33

MB90096

PACKAGE DIMENSIONS

■

28-pin plastic SH-DIP

(DIP-28P-M03)

26.00

1.024

+0.20
–0.30

+.008
–.012

INDEX-1

INDEX-2

4.85(.191)MAX

3.00(.118)MIN

1.00
.039

1.778±0.18
(.070±.007)

1.778(.070)
MAX

C

1994 FUJITSU LIMITED D28012S-3C-3

23.114(.910)REF

+0.50
–0

+.020
–0

9.10±0.25

(.358±.010)

0.51(.020)MIN

0.45±0.10

(.018±.004)

0.25±0.05

(.010±.002)

10.16(.400)
TYP

15°MAX

Dimensions in mm (inches) .

(Continued)

34

(Continued)

007

002

28

28-pin plastic SOP

(FPT-28P-M17)

INDEX

15

*

11.80±0.30

(.465±.012)

2

8.60±0.20

(.339±.008)

.

–.

Details of "A" part

(.104±.006)

MB90096

2.65±0.15

(Mounting height)

0.25(.010)

1

1.27(.050)

C

2002 FUJITSU LIMITED F28048S-c-3-4

0.47±0.08

(.019±.003)

0.10(.004)

0.13(.005)

14

M

"A"

0~8˚

0.80±0.20

(.031±.008)

0.88±0.15

(.035±.006)

0.20±0.15

(.008±.006)

(Stand off)

Dimensions in mm (inches) .

35

MB90096

FUJITSU LIMITED

All Rights Reserved.

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.

F0303

 FUJITSU LIMITED Printed in Japan