FUJITSU MB90096 DATA SHEET

查询MB90096供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP For Screen Display Control

CMOS

On-screen Display Controller

MB90096

DESCRIPTION

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The MB90096 is a multi-scan on-screen display controller that supports horizontal sync signal frequencies of 15 kHz to 120 kHz.The on-screen display configuration is up to 32 characters x 16 lines . The character configuration is up to 24 dots x 32 dots for high resolution, ideal f or wide-screen TV , HDTV , and high-resolution personal computer displays.

DS04-28826-5E

The character display functions include sprite character, character background display, and graphics functions, contributing to the use of colorful GUI displays.

The MB90096 contains display memory (VRAM), character font ROM, and VCO, allowing characters to be displayed with a minimum of external components. This device also includes command table ROM for storage of display command data, greatly reducing the load on the microcontroller.

PACKAGES

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28-pin plastic SH-DIP

(DIP-28P-M03)

28-pin plastic SOP

(FPT-28P-M17)

MB90096

FEATURES

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• Screen display capacity: Up to 32 characters x 16 lines (512 characters)

• Character configuration: L size: 24 dots (horizontal) x 2h * dots (vertical) M size: 18 dots (horizontal) x 2h * dots (vertical) S size: 12 dots (horizontal) x 2h * dots (vertical)

*: h = 9 to 16

• L, M, S sizes can be selected by individual character

• Graphics characters can be displayed in L or S size only

• Two h values can be set per screen, and either of the two can be selected f or each line on the screen.

• Font types: 512 different fonts included (user selectable over entire screen)

•Display modes: Normal characters/graphic characters: (set for each character) Trimmed display (horizontal trimming/pattern back ground): (set for each screen) Character background (fill/shaded background): (set for each character) Line background (fill/shaded back ground): (set for each line) Enlarged (normal, double width, double height, double width x double height): (set for each line) Blinking: Blinking characters: (set for each character)

Blink period, duty ratio: (set for each screen)

• Sprite character display (graphics display only):

Capable of displaying one b loc k of characters (maximum 2 x 2 char acters) on main screen. (Can move horizontally and vertically in 2-dot increments.) Setting applies to the first 256 characters only (character codes 000 to 0FFH).

• Background character display (graphics display only):

Capable of displaying a repeated pattern (2 x 2 characters) on main screen. Setting applies to the first 256 characters only (character codes 000 to 0FFH).

• Display colors: Character/background colors: 16 colors each (set for each character)

Line background/fill colors: 16 characters each (set for each line) Screen background colors: 16 colors (set for each screen) Graphics character dot colors: 16 colors (set for each dot) Shading background frame colors (highlight/shadow ):

16 colors each (set for each screen)

• Display position control:

Horizontal display start position:Set in 4-dot units (for each screen) Vertical display start position: Set in 4-dot units (for each screen) Line spacing control: Set in 2-dot units (for each line)

• Character/color signal output:

ROUT, GOUT, BOUT, IOUT (color signals) VOB1 (OSD display period output signal) VOB2 (semi-transparent color period output signal)

• Command transfer function (macro service):

Command table ROM, 16Kbyte included

• Compatible horizontal sync signal frequencies:

15 kHz to 120 kHz (PLL circuit included)

• Microcontroller interface:

16-bit serial input (3 signal input pins)

• Packages: SH-DIP-28, SOP-28

• Power supply voltage: +5 V

PIN ASSIGNMENTS

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MB90096

(TOP VIEW)

CPOUT

VCOIN

RESET

TEST

DOCKI

DOCKO

EVEN

AV3V

SIN

SCLK

TRE

V3V

BOUT (C0)

ROUT (C1)

GOUT (C2)

HSYNC

VSYNC

DISP

(DIP-28P-M03)

(FPT-28P-M17)

IOUT (C3)

VOB1

VOB2

MB90096

PIN DESCRIPTIONS

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Pin no.

Pin name I/O

1CPOUTO A

3VCOINI B

8DOCKII D

9DOCKOO C

10 FH

11 EVEN I D

12 HSYNC

Circuit

type

O C Output pin for the horizontal sync signal generated by the PLL circuit.

Function

Horizontal sync phase comparison result signal output pin. Connects to external low-pass filter.

Internal VCO voltage input pin. Receives voltage signal input from external low-pass filter

Dot clock input pin. Used only when operating on an externally generated dot clock signal. * When unused, the horizontal sync signal *2 should be input at this pin. Internal pull-up resistance included.

Output pin for the dot clock signal generated by the internal VCO. This signal can be fixed at “H” level by a command.

Field control signal input pin. This pin is disabled when noninterlaced display or internally generated field control signals are selected by command. Internal pull-up resistance included.

Horizontal sync signal input pin. The period of this signal is used to generate the dot clock signal. The active level is programmable. Internal pull-up resistance included.

13 VSYNC

14 DISP I D

IOUT (C3)

GOUT (C2)

ROUT (C1)

BOUT (C0)

16 VOB1 O C

15 VOB2 O C

24 SCLK I D

25 SIN I D

26 CS

Vertical sync signal input pin. The active level is programmable. Internal pull-up resistance included.

Display output (ROUT, GOUT, BOUT, IOUT, VOB1, VOB2) control pin. When this pin is set to “L” level, the display control is forcibly set to inactive. Normally, the horizontal and vertical blanking signals are input

here. * Internal pull-up resistance included.

Color signal output pins. The active level is programmable.

Display period output pin. The active level is programmable.

Semi-transparent period output signal. The active level is programmable.

Serial transfer shift clock input pin. Internal pull-up resistance included.

Serial data input pin. Internal pull-up resistance included.

Chip select pin. Set to “L” level for serial transfer. Internal pull-up resistance included.

(Continued)

Pin no.

Pin name I/O

Circuit

type

MB90096

Function

23 TRE O C

5 RESET

Output pin for indicator that command transfer and fill operations are in progress. Active “H” level output.

Reset input pin. Input a “L” level signal *

at power-on. Internal pull-up resistance included.

Test signal input pin.

6TEST

Input “H” level (fixed) for normal operation.

Internal pull-up resistance included. 22 VCC +5 V power supply pin. 21 V3V Connect 0.1 µF capacitance between this pin and V

SS Ground pin.

SS.

27 AVCC +5 V power supply pin for VCO. 28 AV3V Connect 0.1 µF capacitance between this pin and AV

2, 4 AV

SS Ground pin for VCO.

SS.

*1: The clock signal should be input even during a reset interval. *2: The active lev el of the horizontal sync signal input ma y be either “H” or “L” lev el. During reset intervals, including

power-on resets, apply a “L” level fixed signal or a horizontal sync signal with one or more “L” lev el intervals at the DOCKI pin.

*3: The MB90096 display signals (IOUT, ROUT, GOUT, BOUT, VOB1, VOB2) may be output during horizontal or

vertical blanking intervals. Normally devices such as TV or monitors use a reverence color setting during horizontal and vertical blanking intervals, so that during this period the MB90096 display signals must be masked at the DISP pin signal.

*4: When power is switched on, apply a “L” level signal for 1ms or longer after the V

CC (AVCC) is stabilized.

MB90096

I/O CIRCUIT TYPES

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Type Circuit Remarks

(internal 3 V)

Pch

Nch

• CMOS output (internal 3 V) 3-state output

• Analog input

Nch

Pch

(5 V)

Pch

• CMOS output (5 V)

Nch

• CMOS hysteresis input

(5 V)

Pull-up resistance (approx. 50 kΩ) included

BLOCK DIAGRAM

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DISP BOUT

MB90096

VSYNC

EVEN

RESET

SIN

SCLK

TRE

DOCKI

HSYNC

CPOUT

VCOIN

Serial input

control

Command

table ROM

control

Command

table ROM

(16 KByte)

Display control

Display memory

VRAM

(32 char. x 16 line)

Dot clock

Dot clock generator circuit

(PLL circuit)

Font

ROM

(512 char.)

Display

output

control

ROUT

GOUT

IOUT

VOB1

VOB2

DOCKO

MB90096

ABSOLUTE MAXIMUM RATINGS

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Parameter Symbol

CC VSS − 0.3 VSS + 6.0 V *

Power supply voltage

AVCC VSS − 0.3 VSS + 6.0 V *

(VSS = AVSS = 0 V Typ)

Rating

Unit Remarks

Min Max

Capacitance pins V3V, AV3V V Input voltage V

IN VSS − 0.3 VCC + 0.3 V

SS − 0.3 VSS + 3.6 V

Output voltage VOUT VSS − 0.3 VCC + 0.3 V Power consumption Pd  600 mW Operating temperature Ta −40 +85 °C Storage temperature Tstg −55 +150 °C

*: AVcc and Vcc must have equal potential. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

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(VSS ==== AVSS ==== 0 V Typ)

Value

Parameter

Symbol

Unit

Remarks

Min Max

CC 4.5 5.5 V Specification guarantee range

Power supply voltage

CC 4.5 5.5 V *1

“H” level input voltage V “L” level input voltage V

IHS 0.8 × VCC VCC + 0.3 V

ILS2 VSS − 0.3 0.2 × VCC V

Operating temperature Ta −40 +85 °C Analog input voltage V

IN 0 3.0 V VCOIN input *

Smoothing capacitor (capacitance pin)

S 0.1 1.0 µF

Use a ceramic capacitor or other capacitor having equivalent frequency characteristics. The capacitance at the Vcc and AVcc pins must be greater than Cs.

*1: AVcc and Vcc must have equal potential. *2: This recommended input voltage range does not imply that stable PLL operation is warranted. For stable PLL

operation it is recommended that input voltage be between 1.0 V and 2.5 V. Note however that PLL operating status is greatly affected by variations in the input horizontal sync signal period, as well as external filter settings and operating temperature, etc. Thorough testing and evaluation is recommended.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

ELECTRICAL CHARACTERISTICS

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1. DC Characteristics

Parameter

Symbol

(VSS = AVSS = 0 V, Ta = -40 °C to +85 °C)

Pin name Condition

MB90096

Value

Unit

Min Typ Max

“H” level output voltage 1 V

All output pins

OH1

except CPOUT pin

“H” level output voltage 2 VOH2 CPOUT pin

“L” level output voltage V

Pull-up resistance R

Input leak current I

Power supply current I

Input capacitance C

*: Power supply pins: V

CC, AVCC, VSS, AVSS, Capacitance pins: V3V, AV3V

OL All output pins

All input pins

PULL

except VCOIN pin

IL VCOIN pin

CC VCC + AVCC

Other than power supply and

capacitance pins

VCC = AVCC = 4.5 V, I

OH = −4.0 mA

VCC = AVCC = 4.5 V, I

OH = −4.0 mA

VCC = AVCC = 4.5 V, I

OL = 4.0 mA

4.0 V

2.5 V

0.4 V

VCC = AVCC = 5.5 V 20  100 kΩ VCC = AVCC = 5.5 V,

SS < VIL < VCC

VCC = AVCC = 5.5 V (no load), Dot clock 60 MHz

−10  10 µA

40 mA

Dot clock 40 MHz 30 mA Dot clock 20 MHz 20 mA

10  pF

MB90096

2. AC Characteristics

(1) Serial Input Timing

Parameter Symbol Pin name

Shift clock cycle time t

CC =

= AVCC ==== 5.0 V ± 10%, VSS = AVSS = 0 V, Ta ==== −40 °°°°C to +85 °°°°C)

Value

Unit Remarks

Min Max

CYC SCLK 250  ns

Shift clock pulse width

Shift clock signal rise/fall time

Shift clock start time t

WCH

SCLK

WCL 100  ns

tCR

SCLK

CF  200 ns

SS SCLK 100  ns

100  ns

 200 ns

Data setup time tSU SIN 100  ns Data hold time t Chip select end time t

Chip select signal rise/fall time

••••

Serial input timing

tCFC

0.8 VCC

0.2 VCC

tSS

H SIN 50  ns

EC CS 100  ns

tCRC

 200 ns

CFC  200 ns

tCYC

tEC

0.8 VCC

0.2 VCC

tCRC

SCLK

SIN

tCR

tWCH

tCF

tSU

0.8 VCC

0.2 VCC

tWCL

0.8 VCC

0.2 VCC

(2) Vertical and horizontal sync signal input timing

CC =

= AVCC ==== 5.0 V ±±±± 10%, VSS ==== AVSS ==== 0 V, Ta ==== −40 °°°°C to +85 °°°°C)

Parameter Symbol Pin name

Value

Min Max

MB90096

Unit

Remarks

Horizontal sync signal rise time t

 500 ns

HSYNC

Horizontal sync signal fall time t Vertical sync signal rise time t

HF  500 ns

 500 ns

VSYNC

Vertical sync signal fall time tVF  500 ns Horizontal sync signal pulse

width * Vertical sync signal pulse width t

Horizontal sync signal setup time t

tWH HSYNC

WV VSYNC 220 H

DHST

18  Dot clock  6 µs

6  ns *2

HSYNC

Horizontal sync signal hold time t Vertical sync signal setup time tHVST

DHHD 3  ns *2

41H − 4 Dot clock

VSYNC

Vertical sync signal hold time t Vertical sync signal setup time

when field signal is generated Vertical sync signal hold time

when field signal is generated

HVHD 220 H

EVST VSYNC 18  Dot clock *3

tEVHD VSYNC 18  Dot clock *3

*1: The horizontal sync pulse time is applied after MB90096 internal operations have paused and horizontal operation

has been synchronized. For this reason it is necessary to leav e an interval between commands so that writing to VRAM (command 2, 4) is not performed more than once. It is necessary to set the horizontal sync signal pulse width and interval f or writing to VRAM so that the horizontal

sync signal pulse width is less than the writing interval to VRAM. *2: Applied when an external dot clock signal is input. *3: Applied in interlaced display, when the EVEN signal is applied from an external source.

••••

Vertical and horizontal sync signal input timing

HSYNC

VSYNC

tHF

tVF

0.8 VCC

0.2 VCC

tWH

0.8 VCC

0.2 VCC

tWV

0.8 VCC

0.2 VCC

tHR

0.8 VCC

0.2 VCC

tVR

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