FUJITSU MB90092 DATA SHEET
查询MB90092PF 供应商
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP for Screen Display Control
CMOS
ON-Screen Display Controller
MB90092
DESCRIPTION
■■■■
The MB90092 is the display controller for displaying text and graphics on the TV screen.
The MB90092 incorporates display memory (VRAM), a font memory interface, and a video signal generator,
allowing text and graphics to be displayed in conjunction with a small number of external components.
The MB90092 can provide two screens, called the main screen and the sub-screen, either independently or
overlayed one on top of the other.
The main screen consists of 24 characters by 12 lines and allows data to be set for each character. The subscreen consists of 32 characters by 12 lines or up to 32 characters by 16 lines. Data can be set either for each
line in the former configuration or collectively for the entire screen in the latter configuration.
For output of video signals, the MB90092 has the composite video signal, Y/C-separated video signal, and RGB
digital output pins. The MB90092 also has video signal input pins, allowing superimpose display over either
composite video signals and Y/C-separated video signals.
DS04-28824-3E
PACKAGE
■■■■
80-pin Plastic QFP
(FPT-80P-M06)
MB90092
FEATURES
■
• Main Screen Display
• Screen display capacity:24 characters × 12 lines (up to 288 characters)
• Character dot configuration:24 × 32 dots (per character)
• Character types: 16384 different characters (when using a 16 M bit external clock)
• Character sizes: Standard, double width, double height, double width × double height,
quadruple width × double height (Setting possible for each line)
• Display position control :Horizontal display position :Set in 1/3-character units
Vertical display position :Set in raster units
Line spacing control :Set in raster units (0 to 15 rasters)
• Display priority control:Capable of controlling display priority over the sub-screen (for each line)
• Sub-Screen Display
Screen display position: Settable horizontally and vertically in 2-dot units
• Normal screen mode:Screen capacity:32 characters × 12 lines (up to 384 characters)
256 horizontal dots × 384 vertical dots (graphics characters only) (The
actual display screen depends on the television system and dot clock
frequency.) Normal character/graphic character display selectable for
each line (Header display character code is specified for each line.)
Character string length:Selectable from among 1, 2, 4, 8, 16, 24, and 32 digits
• Full-screen mode
Screen capacity:32 characters × 16 lines (up to 512 characters)
256 horizontal dots × 512 vertical dots
(The actual display screen depends on the television
system and dot clock frequency.)
Virtual screen capacity:Mode A:32 characters × 16 lines (× 32 screens)
256 horizontal dots × 512 vertical dots
Mode B:512 characters × 32 lines
4096 horizontal dots × 1024 vertical dots
Screen Background Display
Screen background color: 8 colors (set for the entire screen)
Analog Inputs
• Composite video signal input
• Y/C-separated inputs
Analog Outputs
• Composite video signal output
• Y/C-separated outputs
Digital Outputs
• G (Green), R (Red), and B (Blue) output
• VOC (character) output, VOB (character + background) output
• Characters, character backg round, line backg round, and screen backg round each capable of being displa y ed
in eight colors
Internal Synchronization Control (Video Signal Generator)
• Internal video signal generator supporting the NTSC and PAL systems
• Interlaced/noninterlaced display selectable
2
(Continued)
(Continued)
External Synchronization Control
• Separated sync signal input/composite sync signal input selectable
External Interface
• 8-bit serial inputs (3 signal input pins)
Chip select: CS
Serial clock: SCLK
Serial data: SIN
Package
•QFP-80
Miscellaneous
• Internal power-on reset circuit
MB90092
3
MB90092
PIN ASSIGNMENT
■■■■
(TOP VIEW)
TESTI
VOC
VOB
V
CS
SCLK
SIN
V
EXHSYN
EXVSYN
HSYNC
VSYNC
VBLNK
EXS
XS
TEST1
FSCO
CBCK
PDS
V
AVSS
XD
EXD
TEST
TSC
VCCADR20
ADR19
ADR18
ADR17
ADR16
ADR15
ADR14
807978777675747372717069686766
1
2
3
SS
B
R
G
4
5
6
7
8
9
10
CC
11
12
13
14
15
16
17
18
19
20
21
22
SS
23
24
252627282930313233343536373839
ADR13
ADR12
SS
ADR11
V
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
ADR10
ADR9
V
CC
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
V
SS
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
READ
V
CC
AVCC1
TEST2
TEST3
TEST4
TEST5
SS
AV
AVSS
YIN
YOUT
AVCC2
CIN
COUT
SS
AV
VKIN
VOUT
VIN
VKOUT
(FPT-80P-M06)
4
PIN DESCRIPTION
■■■■
MB90092
Pin no. Pin name I/O
1 TESTI
2VOC O C
3VOB O C
5
6
7
8CS
9SCLK I B
10 SIN I B
12 EXHSYN
B
R
G
Circuit
type
IB
OC
IB
IB
Function
Test signal input pin. Input High level signal during normal operation.
This pin also can be used as a reset signal input pin by Low-level input
to the TEST pin. That is effective only after release of power-on reset.
This pin is a hysteresis input with an internal pull-up resistor.
Character interval signal output pin.
The output signal represents the character dot output interval.
Character/background internal signal output pin.
During internal synchronization control operation, the output signal represents the character, character background, line background, or screen
background output interval.
Color signal output pins.
These pins output the character, character background, line background, and screen background color signals.
Chip select pin.
For serial transfer, set this pin to the Low level.
This pin is also used to release a power-on reset.
The pin is a hysteresis input with an internal pull-up resistor.
Shift clock input pin for serial transfer.
This pin is a hysteresis input with an internal pull-up resistor.
Serial data input pin.
The pin is a hysteresis input with an internal pull-up resistor.
External horizontal sync signal input pin.
Input negative logic signal.
This pin can also serve as a composite sync signal input pin depending
on the internal register setting.
The pin is a hysteresis input with an internal pull-up resistor.
13 EXVSYN
14 HSYNC
15 VSYNC
16 VBLNK
IB
OC
OC
OC
External vertical sync signal input pin.
Input negative logic signal.
Input to this pin is disabled when composite sync signal input has been
selected by setting the internal register. The pin is a hysteresis input with
an internal pull-up resistor.
Horizontal sync signal output pin.
This pin can also output composite sync signals depending on the internal register setting.
The pin outputs the signal (FSC) resulting from dividing the 4FSC clock
frequency by setting the TEST
Vertical sync signal output pin.
This pin is fixed at the High level when composite sync signal output has
been selected by setting the internal register.
The pin outputs the dot clock oscillator signal when the TEST
into Low.
Vertical blanking interval signal output pin.
This pin outputs the Low-level signal in the vertical blanking interval.
pin to the Low level.
pin goes
(Continued)
5
MB90092
Pin no. Pin name I/O
Circuit
type
Function
External circuit pins for color burst clock generator.
17
18
EXS
XS
I
O
H
Connect an external crystal oscillator (14.31818 MHz for NTSC or
17.734475 MHz for PAL) and load capacitance (C) to these pins to form
a crystal oscillator circuit.
Internal color burst clock output pin.
20 FSCO O C
This pin controls internal color burst clock output depending on the FO
bit of command 7.
21 CBCK I G External color burst clock input pin
22 PDS O D Pin for output of the result of color burst clock phase comparison
Luminance signal output pin.
31 YOUT O F
This pin outputs a signal of 2 V
P-P (pedestal level 1.57 V, sync tip level 1
V).
Luminance signal input pin for superimpose display.
32 YIN I E
This pin inputs a DC-reproduced (DC-clamped) signal of 2 V
level 1.57 V, sync tip level 1 V).
Saturation signal output pin.
34 COUT O F
This pin outputs a signal at 1.57 VDC and a color burst signal amplitude
of 0.57 V
P-P.
Saturation signal input pin for superimpose display.
35 CIN I E
This pin inputs a signal at 1.57 VDC and a color burst signal amplitude
of 0.57 V
P-P.
P-P (pedestal
37 VOUT O F
38 VKIN I E
39 VKOUT O F
40 VIN I E
43 READ
OD
Composite video signal output pin.
This pin outputs a signal of 2 V
P-P (pedestal level 1.57 V, sync tip level
1 V).
Background level control input pin for halftone background display of ex-
ternal input composite video signals (input to the VIN pin and output
from the VOUT pin).
Halftone background display is controlled by setting the KID bit of com-
mand 5 to “1”.
Background level control output pin for halftone background display of
external input composite video signals (input to the VIN pin and output
from the VOUT pin).
Halftone background display is controlled by setting the KID bit of com-
mand 5 to “1”.
Composite video signal input pin for superimpose display.
This pin inputs a DC-reproduced (DC-clamped) signal of 2 V
P-P (pedestal
level 1.57 V, sync tip level 1 V).
External font memory read control pin.
This pin outputs the Low-level signal in the font memory read period.
The pin enters the high impedance state when the TSC pin inputs a
Low-level signal.
(Continued)
6
MB90092
Pin no. Pin name I/O
44
45
46
47
48
49
50
51
53
54
55
56
57
58
59
60
61
63
64
66
67
68
69
70
71
72
73
74
75
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
ADR0
ADR1
ADR2
ADR3
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
ADR10
ADR11
ADR12
ADR13
ADR14
ADR15
ADR16
ADR17
ADR18
ADR19
ADR20
OD
Circuit
type
IA
Function
External font memory data input pins.
These pins are inputs with an internal pull-up resistor.
External font memory address output pins.
These pins enter the high impedance state when the TSC
Low-level signal.
ADR0
ADR1
ADR2 Raster address
ADR3
ADR4
1
∗
2
∗
ADR5 M0, SM0
ADR6 M1, SM1
ADR7 M2, SM2
ADR8 M3, SM3 Character code (Lower bits)
ADR9 M4, SM4
ADR10 M5, SM5
ADR11 M6, SM6
ADR12 Data distinction bits
ADR13 (12,13 = 00: Left, 10: Center, 01: Right)
ADR14 M7, SM7
ADR15 M8, SM8
ADR16 M9, SM9
ADR17 MA, SMA Character code (Higher bits)
ADR18 MB, SMB
ADR19 MC, SMC
ADR20 MD, SMD
*1: M0 to MD are control bits for main screen character
control data setting (the commands 1-1 and 2-1)
*2: SM0 to SMD are control bits for sub-screen character
control data setting (the commands 1-2 and 2-2)
pin inputs a
77 TSC
78 TEST
79
80
EXD
XD
IB
IB
I
O
I
Tristate control input pin for external font memory control bus.
When this pin inputs a Low-level signal, the ADR0 to ADR20 pins and
the READ pin enter the high impedance state.
The pin is a hysteresis input with an internal pull-up resistor.
Test signal input pin.
This pin usually inputs a High-level (fixed) signal.
External circuit pins for display dot clock generator.
Connect these pins to external “L” and “C” to form an LC oscillator cir-
cuit.
(Continued)
7
MB90092
(Continued)
Pin no. Pin name I/O
19
25
26
27
28
11
42
62
76
4
23
52
65
TEST1
TEST2
TEST3
TEST4
TEST5
V
CC — — Power-supply pins (+5 V)
V
SS — — Ground pins
Circuit
type
O — Leave these pins unconnected.
Function
41 AV
33 AVCC2——
CC1 — — Analog power pin for composite video signals (VIN-VOUT)
Analog power pin for luminance (YIN-YOUT) and chroma (CIN-COUT)
signals
24
29
30
AV
SS ——
Analog circuit ground pins.
Set these pins to the same level as the VSS pin.
36
8
I / O CIRCUIT TYPE
■■■■
Type Circuit Remarks
CMOS level input
A
B
With pull-up resistor: approximately 50 kΩ
CMOS level, hysteresis input
With pull-up resistor: approximately 50 kΩ
MB90092
CCMOS output
D CMOS three state output
(Continued)
9
MB90092
(Continued)
Control signal
E
Analog input
Control signal
F
Analog output
Control signal
G CMOS level, hysteresis input
Analog input
CMOS analog SW
Analog output
CMOS analog SW
10
XS
H Crystal oscillation circuit
I LC oscillation circuit
EXS
XD
EXD
Control signal
Control signal
Inside
clock signal
BLOCK DIAGRAM
■
MB90092
SIN
SCLK
CS
TEST
VIN VOUT
YIN
CIN
VKIN
EXHSYN
EXVSYN
HSYNC
VSYNC
VBLNK
Serial input
control
H/V separation
circuit
NTSC/PAL
signal
generator
Display memory
control
Display memory
(
VRAM)
Each control and data
Analog
SW
Video signal
generator
Output
control
Font
memory
control
YOUT
COUT
VKOUT
B
R
G
VOB
VOC
ADR0 ~ ADR20
READ
DA0 ~ DA7
TSC
XS
EXS
XD
EXD
4FSC clock
oscillator
Dot clock
oscillator
Each block
Each block
Phase
comparator
(color burst)
CBCK
PDS
FSCO
11
MB90092
DISPLAY CONTROL COMMANDS
■■■■
Command
no.
0
1-1
2-1
1-2
2-2
1-3
2-3
3
Function
VRAM address setting
Main screen
character control
data setting 1*
Main screen
character control
data setting 2
Sub-screen line
control data setting
1
Sub-screen line
control data setting
2
Main screen line
control data setting
1
Main screen line
control data setting
2
VRAM write
control
76543 2 1 0 7 6 5 4 3 2 1 0
10000 VSL RA8 RA7 0 RA6 RA5 CA4 CA3 CA2 CA1 CA0
10001 MA MB AT 0 CG CR CB MC
10010 M9 M8 M7 0 M6 M5 M4 M3 M2 M1 M0
10001 SMA SMB 0 0 SCG SCR SCB SMC SGR SDC SMD
10010 SM9 SM8 SM7 0 SM6 SM5 SM4 SM3 SM2 SM1 SM0
10001 OF1 OF0 0 0 0 0 0 PC PG PR PB
10010 G2 G1 G0 0 SOC VD DG KC KG KR KB
10011 FIL 0 0 0 0 0 0 0 0 0 0
First byte Second byte
Command code/data Data
BG
(GR)*BR(BS)*BB(MD)*
4 Screen control 1 10100 IE IN EB 0 EO CM ZM NP P2 P0 DC
5 Screen control 2 10101 KID APC GYZ 0 BH2 BH1 BH0 W3 W2 W1 W0
6
7
8
Main screen line
control
Main screen vertical
display position
control
Main screen horizontal
display position control
10110 G2 G1 G0 0 SOC VD DG N3 N2 N1 N0
10111 EC LP FO 0 0 Y5 Y4 Y3 Y2 Y1 Y0
11000 SC 0 FC 0 0 X5 X4 X3 X2 X1 X0
Main screen
9
display mode
11001 0 0 GRM 0 RP1 RP0 S16 SF1 DW4 RM1 RM0
control
10 Color control 11010 0 0 RB 0 BK CC BC UC UG UR UB
11
12
13
Sub-screen
control
Sub-screen vertical
display position
control
Sub-screen horizontal
display position control
11011 SG2 SG1 SG0 0 0 SCC SBC SGC SBG SBR SBB
11100 SGA 0 SY7 0 SY6 SY5 SY4 SY3 SY2 SY1 SY0
11101 0 SX8 SX7 0 SX6 SX5 SX4 SX3 SX2 SX1 SX0
14 (Reserved) 11110 — — — 0 — — — — — — —
15 (Reserved) 11111 — — — 0 — — — — — — —
*: Parenthesized bit names are used for extended graphics mode.
Note: DC bit of screen control 1 (command 4) is initialized at “0” and display is off b y reset. All command data and
all VRAM are needed to set after release of power-on reset.
12
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