FUJITSU MB90091A DATA SHEET

查询MB90091供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

DS04-28823-2E

ASSP Image Control

CMOS

Intelligent On-screen Display
Controller (IOSDC)

MB90091A

DESCRIPTION

■

The MB90091A is the multisync, on-screen display controller that supports a variety of TV systems such as
NTSC, PAL, double-scan NTSC, double-scan PAL, 1250HDTV, and 1125HDTV as well as personal computer
monitor display systems such as VGA and XGA.

The MB90091A contains display memory (VRAM) and character font R OM, allowing characters to be displa y ed
with few external devices. The device also contains command table ROM storing display command data,
minimizing the load on the microcomputer.

The on-screen display configuration is up to 24 characters × 12 lines, with each character consisting of 24 × 32
dots. The font ROM integrates 512 different character patterns.

The character signal output is an RGB1 digital output. The display color of each character can be specified
from among 16 colors. A color/monochrome select signal output is also provided f or display either in 16 diff erent
colors or in 16-level gray scale.

The character display functions include character background display, shaded background display, and sprite
character display functions, contributing to providing colorful display screens.

PACKAGES

■

64 pin, Plastic SH-DIP

64 pin, Plastic QFP

(DIP-64P-M01)

(FPT-64P-M06)

MB90091A

FEATURES

■

• Screen display capacity : Up to 24 characters x 12 lines (288 characters)

• Font size : 24 x 32 dots (horizontal x vertical)

• Font types : 512 different characters (character codes 000H to 1FFH)
8 different sprite characters (character codes 1F8H to 1FFH)

(Internal or external ROM selectable)

• Display modes : Trimmed display (pattern background 0, 1, or none)
Character background (settable for each character)

Shaded background (settable for each character)

• Sprite character display : Capable of displaying one character (selectab le from among 8 types of char­acters) on the screen

Sprite character colors : 8 colors
Sprite trimming colors : 8 colors
Sprite display position : Settable in 2-dot units on the screen

• Character sizes : Normal, double width, double height, double width x double height, quadruple
width, quadruple width x double height

(Set for each line)

• Display colors : Character color : 16 colors (set for each character)
Trimmed background color : 16 colors (set for each line)
Character background color : 16 colors (set for each character)
Screen background color : 16 colors

• Display position control : Horizontal display start position : Set in 8-dot units
Vertical display start position : Set in 2-dot units

Line spacing control : Set in 2-dot units (0 to 30 dots)

• Character/color signal output : ROUT, GOUT, BOUT, IOUT (color signals)
COLOR (color/monochrome control signal)

VOB1 (character + pattern background + character background + screen
background: all-output signal)

VOB2 (character + pattern backg round + character background: specified­character output signal)

• Supported TV systems : NTSC, PAL, double-scan NTSC, double-scan PAL, 1250HDTV, 1125HDTV,
etc.

Personal computer monitor display systems such as VGA

• Intelligent features : Automatic control of operation using on command table ROM
Command table ROM: Internal 32K bytes + external 32K bytes available

• Microcontroller/microcomputer interface : 8-bit serial input (3 signal input pins

Chip select: SCS
Serial clock: SCLK
Serial data: SIN

• Package : SH-DIP-64, QFP-64

• Miscellaneous : Power-on reset circuit integrated

2

PIN ASSIGNMENTS

■

MB90091A

(TOP VIEW)

1COLOR VOB264
2DOCK VOB163
3V SS IOUT62
4TESTCK BOUT61
5TESTSW GOUT60
6HBLNK ROUT59
7VBLNK TRE58
8HSYNC V CC57
9VSYNC SCS56
10EVEN SIN55
11FLTIN SCLK54
12AV SS FSEL53
13FLTOUT TSEL52
14AV CC RA1551
15FH RA1450
16RESET RA1349
17V CC RA1248
18RD0 V SS47
19RD1 RA1146
20RD2 RA1045
21RD3 RA944
22RD4 RA843
23RD5 RA742
24RD6 RA641
25RD7 RA540
26TEST V SS39
27V SS RA438
28TA16 V CC37
29TA17 RA336
30TA18 RA235
31FCS RA134
32TCS RA033

(SH-DIP-64P)

(Continued)

3

MB90091A

(

)

(Continued)

(TOP VIEW)

VBLNK64

HBLNK63

TESTSW62

TESTCK61

V SS60

DOCK59

COLOR58

VOB257

VOB156

IOUT55

BOUT54

GOUT53

ROUT52

1HSYNC TRE51
2VSYNC V CC50
3EVEN SCS49
4FLTIN SIN48
5AV SS SCLK47
6FLTOUT FSEL46
7AV CC TSEL45
8FH RA1544
9RESET RA1443
10V CC RA1342
11RD0 RA1241
12RD1 V SS40
13RD2 RA1139
14RD3 RA1038
15RD4 RA937
16RD5 RA836
17RD6 RA735
18RD7 RA634
19TEST RA533

20V SS

21TA16

22TA17

23TA18

FPT-64P-M06

24FCS

25TCS

26RA0

27RA1

28RA2

29RA3

30V

CC

31RA4

32V

SS

4

PIN DESCRIPTION

■

MB90091A

Pin No.

DIP QFP

8 1 HSYNC
9 2 VSYNC

10 3 EVEN I

11 4 FLTIN O

13 6 FLTOUT I
15 8 FH
16 9 RESET
18

19
20
21
22
23
24
25

11
12
13
14
15
16
17
18

Pin name I/O Function

RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7

Horizontal sync signal input pin

I

Dot clock generation is based on the cycle of the signal.

I Vertical sync signal input pin

Field control signal input pin
Input of an “L” level signal to this pin causes the font ROM address
LSB pin (RA0) to output an “L” level signal.
Input of an “H“ level signal to this pin causes the font ROM address
LSB pin (RA0) to output an “H” level signal (when normal-size
characters are displayed).
This pin is disabled in noninterlaced mode.

Output pin for horizontal-sync phase comparison result signal
This pin is connected to an external lowpass filter.

Internal VCO voltage input pin
This pin inputs the voltage signal from the external lowpass filter.

O Output pin for AFC-generated horizontal sync signal

Reset pin

I

This pin is enabled after release from a power-on reset.

External ROM data input pin

I

This pin inputs data from external font ROM or external command
data ROM.

26 19 TEST I
28

29
30

31 24 FCS
32 25 TCS

21
22
23

TA16
TA17
TA18

Test signal input pin
This pin inputs an “L” level (fixed) signal during normal operation.

O Test signal output pin

O External font ROM chip select pin
O Chip select pin for external command table ROM

(Continued)

5

MB90091A

(Continued)

Pin No.

DIP QFP

Pin name I/O Function

33
34
35
36
38
40
41
42
43
44
45
46
48
49
50
51

52 45 TSEL I

53 46 FSEL I

54 47 SCLK I Shift clock input pin for serial transfer

26
27
28
29
31
33
34
35
36
37
38
39
41
42
43
44

RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8

RA9
RA10
RA11
RA12
RA13
RA14
RA15

External ROM address signal output pin
This pin outputs the signal specifying the external font ROM or
external command table ROM address.

External font ROM addresses

O

RA0 to RA4 : Raster addresses
RA5 to RA11 : Character codes (M0 to M6)
RA12, RA13 : Character horizontal address

= (0, 0): Left byte
= (1, 0): Center byte
= (0, 1): Right byte

RA14, RA15 : Character codes (M7, M8)

Address control input pin for command table ROM
“L” level input : 0000H to 7FFFH Internal ROM

8000H to FFFFH External ROM

“H” level input : 0000H to 7FFFH External ROM

8000H to FFFFH Internal ROM

Internal/external font ROM select pin
“L” level input : Select internal ROM.
“H” level input : Select external ROM.

55 48 SIN I Serial data input pin

Chip select pin

56 49 SCS

58 51 TRE O

59
60
61
62

63 56 VOB1 O

64 57 VOB2 O

52
53
54
55

ROUT
GOUT
BOUT

IOUT

I

For serial transfer, set this pin to the “L” level.
This pin is also used to cancel a power-on reset.

Output pin for the signal indicating internal operation
This pin outputs an “H” level signal during data transfer from
command table ROM.

Chrominance signal output pin
For output of a character, character background, pattern background,

O

shaded background, screen background, or sprite character
(including a pattern background), this pin outputs the chrominance
signal.

Pin for specifying the chrominance signal output period
This pin outputs an “H” level signal f or output of a char acter , character
background, pattern background, shaded background, screen
background, or sprite character (including a pattern background.

Pin for specifying the specified character output period
When the command 6: ATH bit = “1”, this pin outputs an “H” level
signal in the character output period (24 x 32 dot period) when the
command 1: AT bit = “1”.
The pin can be used for display control by an external circuit, for
example, for halftone display control.

(Continued)

6

(Continued)

Pin No.

Pin name I/O Function

DIP QFP

1 58 COLOR O

MB90091A

Color/monochrome select signal output pin
This pin allows “H” or “L” level output in each of the character,
character background, line background, screen background, and
sprite output periods to be specified depending on the internal
register setting.
Color/monochrome display is controlled by an external circuit.
(The following correspondence is used for convenience:

“L” level: Monochrome display
“H” level: Color display)

259DOCKO

461TESTCKI

562TESTSWI

Dot clock output pin
This pin outputs a dot clock signal when the command 11:DOT = “1”.

Test signal input pin
This pin inputs an “H” level (fixed) signal during normal operation.

Test signal input pin
This pin inputs an “H” level (fixed) signal during normal operation.

Horizontal blanking signal input pin

6 63 HBLNK

I

This pin stops display signal output (“L” lev el output) when it inputs an
“L” level signal.

Vertical blanking signal input pin

7 64 VBLNK

I

This pin stops display signal output (“L” lev el output) when it inputs an
“L” level signal.

17
37
57

27
39
47

3
14 7 AV
12 5 AV

10
30
50

20
32
40
60

CC

V

SS

V

CC
SS

— +5 V power supply pin

— Ground pin

— +5V power supply pin for VCO
— Ground pin for VCO

7

MB90091A

BLOCK DIAGRAM

■

SCS

SIN

SCLK

FLTIN

LPF

FLTOUT

FH

MB90091A

Serial input

control

Dot clock
generator

Command

table ROM

control

Command

table ROM

TRE
TSEL

TCS

RA0 to 15
RD0 to 7

Command

table ROM

DOCK

HSYNC
VSYNC

EVEN

RESET

Display

memory

control

Display
memory

(VRAM)

Resets each block.

Font ROM

control

Font ROM

Display data

output control

FCS

Font ROM

FSEL

BOUT
ROUT
GOUT
IOUT
VOB 1
VOB 2
COLOR

8

ABSOLUTE MAXIMUM RATINGS

■

Parameter Symbol

MB90091A

(VSS = AVSS = 0 V)

Ratings

Unit

Min. Max.

Power supply voltage *

Input voltage *
Output voltage *

2

3

CC

1

V

AV

V

V

CC

IN

OUT

SS –

V

0.3 V

SS –

V

0.3 V

SS –

V

0.3 V

SS –

V

0.3 V

SS +

7.0 V

SS +

7.0 V

SS +

7.0 V

SS +

7.0 V
Power consumption Pd — 500 mW
Operating temperature Ta 0 +
Storage temperature Tstg –

CC

*1: AV
*2: Neither V

and VCC must have equal potential.

IN

nor V

OUT

must exceed “VCC + 0.3 V”.

55 + 150 °C

70 °C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

■

(VSS = AVSS = 0 V)

Values

Parameter Symbol

Unit Remarks

Min. Max.

CC

V

4.75 5.25 V Specification guarantee range

Power supply voltage *

AV

CC

4.75 5.25 V

V

IHS1

2.4 V

CC +

0.3 V RD0 to RD7 inputs

“H” level input voltage

V

V

IHS2
ILS1

0.8 × V

CC

CC +

V

0.3 V Other inputs

– 0.3 0.45 V RD0 to RD7 inputs

“L” level input voltage

ILS2

V
Operating temperature Ta 0 +
Analog input voltage V

CC

* :AV

and VCC must have equal potential.

IN

SS –

V

0.3 0.2 × V

CC

70 °C

V Other inputs

0VCCV FLTOUT input

WARNING: Recommended operating conditions are nor mal operating ranges for the semiconductor device. All

the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.
No warranty is made with repect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.

9

MB90091A

ELECTRICAL CHARACTERISTICS

■

1. DC Characteristics

Parameter Symbol Pin Conditions

CC

= 4.75 V

“H” level output voltage V

“L” level output voltage V

OH

All out-

put pins

OL

V

OH

I

= – 2.0 mA

VCC = 4.75 V

OL

I

= 4.0 mA

HSYNC
VSYNC

EVEN

RESET

RD0 to

Input current I

RD7

IL

TSEL
FSEL

VCC = 5.25 V

IL

I

= 4.0 mA

SCLK

SIN

SCS
HBLNK
VBLNK

VCC = AVCC = 5.25 V

CC

Supply current I

CC

V

AV

DOCK = 42 MHz

CC

No load

Values

Unit

Min. Typ. Max.

4.0 — — V

——0.4V

— — – 50 mA

——40mA

10

2. AC Characteristics

(1) Serial input timing

Parameter Symbol Pin

MB90091A

CC

(V

= AVCC = 5.0 V ± 5%, VSS = AVSS = 0 V, Ta = 0°C to +70°C)

Values

Min. Max.

Unit

Shift clock cycle time t

t

Shift clock pulse width

Shift clock signal rise/fall time

Shift clock start time t
Data setup time t
Data hold time t
Chip select end time t

Chip select signal rise/fall time

SCS

0.8 V CC

t CFC

0.2 V CC

t SS

t CYC

CVC

WCH

WCL

t

CR

t

CF

t

SS

SU

H

EC

CRC

t

CFC

t

SCLK 1000 — ns

450 — ns

SCLK

450 — ns

—200ns

SCLK

—200ns

SCLK 200 — ns

SIN 200 — ns
SIN 100 — ns

SCS 500 — ns

—200ns

SCS

—200ns

0.8 V CC

0.2 V CC

t CRC

t EC

SCLK

SIN

t CR t CF

0.8 V CC

0.2 V CC

t WCLt WCH

t H

t SU

0.8 V CC

0.2 V CC

11

MB90091A

(2) Vertical and horizontal sync signal input timings

Parameter Symbol Pin

CC

(V

= AVCC = 5.0 V ± 5%, VSS = AVSS = 0 V, Ta = 0°C to +70°C)

Values

Min. Max.

Unit

Horizontal sync signal rise time t
Horizontal sync signal fall time t
Vertical sync signal rise time t
Vertical sync signal fall time t
Horizontal sync signal pulse width t
Vertical sync signal pulse width t
Horizontal sync signal setup time t
Vertical sync signal setup time t

HSYNC

t HF

VSYNC

HR

HF

VR

VF
WH
WV

HVST
HVHD

0.8 V CC

0.2 V CC

0.8 V CC

0.2 V CC

HSYNC —200ns
HSYNC —200ns
VSYNC —200ns
VSYNC —200ns
HSYNC 1—µs
VSYNC 2—H
VSYNC 5—µs
VSYNC 5—µs

0.8 V CC

0.2 V CC

t WH

t HR

0.8 V CC

0.2 V CC

12

HSYNC

VSYNC

t VF

t HVST

t WV

t VR

0.8 V CC

t HVHD

0.8 V CC

0.2 V CC

MB90091A

The MB90091A outputs display signals in synchronization with sync signals input from external circuits. The
signals required for controlling synchronization are the horizontal sync signal (input via the HSYNC
sync signal (input via the VSYNC pin), and field control signal (input via the EVEN pin).

The following examples illustrate external sync signal input timings applicable to general interlaced display.
Noninterlaced display does not require the EVEN pin signal.

• External sync signal input timing examples

(1) Field A

2

VSYNC

Slow *

pin), vertical

FH
(HSYNC)

EVEN

(2) Field B

VSYNC

FH
(HSYNC)

EVEN

*1

2

*

2

Fast *

*1

2

*

*1: Input the horizontal sync signal to the HSYNC pin.

Input of a composite sync signal may change the FH
the VSYNC

pulse, requiring a caution to be used for the timing of input to the EVEN pin. (See *2 below.)

signal cycle due to the PLL lock disturbed around

*2: The input levels of the EVEN pin input signal in fields A and B are determined depending on the

relationship between the VSYNC
the field in which the FH

pulse after the rise of the VSYNC pulse appears fast. Pin the “H” level signal

and FH pulse positions. To the EVEN pin, input the “L” level signal in

in the field in which it appears slow.
The EVEN pin input signal should vary in the undisplay period such as around the VSYNC

pulse.

13

MB90091A

(3) RESET signal input timing

Parameter Symbol Pin

CC

(V

= AVCC = 5.0 V ± 5%, VSS = AVSS = 0 V, Ta = 0°C to +70°C)

Values

Min. Max.

Unit

Reset input pulse width t

RESET

WR

RESET 10 — µs

0.2 V CC0.2 V CC

t WR

14

(4) Address data hold timing

Parameter Symbol Pin

MB90091A

CC

(V

= AVCC = 5.0 V ± 5%, VSS = AVSS = 0 V, Ta = 0°C to +70°C)

Values

Min. Max.

Unit

ROM read cycle t
Address valid dela y t
Address invalid delay t
Read data setup t
Read data hold t
TCS, FCS active delay t
TCS

, FCS inactive delay t

* :Dot clock = 84 to 42 MHz

8123456781

DOCK

rcyc

av
ai
ds

dh

ca

ci

RD0 to RD7

t rcyc

— Dot clock* x 8 —

RA0 to

RA15

—30ns

0—ns

30 — ns

0—ns

—22ns

TCS, FCS

0—ns

0.2 V CC

RA0 to 15

TCS, FCS

RD0 to 7

0.8 V CC

0.2 V CC

t av t ai

0.8 V CC

0.2 V CC

t ci t ca

0.8 V CC

0.2 V CC

t ds t dh

15

MB90091A

(5) Display data output timing

Parameter Symbol Pin

Display data output delay t

d1

CC

(V

= AVCC = 5.0 V ± 5%, VSS = AVSS = 0 V, Ta = 0°C to +70°C)

Values

Min. Max.

ROUT, GOUT, BOUT

IOUT, VOB1, VOB2

022ns

COLOR

Unit

DOCK

ROUT, GOUT, BOUT
IOUT, VOB1, VOB2
COLOR

0.2 V CC

t d1

0.8 V CC

0.2 V CC

16

3. Power-on Reset Specifications

(1) Power ON-OFF timing

Parameter Symbol Pin

MB90091A

(Ta = 0°C to +70°C)

Values

Unit Remarks

Min. Max.

Power-supply rise time t

Power-supply shut-off time t

0.2 V 0.2 V

V CC

Note: The power supply must be activated smoothly

r

VCC, AV

off

CC

0.05 50 ms

1—ms

Power-on reset circuit
activating conditions

Conditions in which the
circuit repeatedly
operate normally

4.75 V

0.2 V

t r

t off

17

MB90091A

(1)

(2) Power-on reset cancel timing

Parameter Symbol Pin

(Ta = 0°C to +70°C)

Values

Unit Remarks

Min. Max.

Time after rise t

Reset cancel pulse width

V CC

Internal reset

SCS

WIT

WRH

t

WRL

t

4.75 V

SCS

450 — ns
450 — ns
450 — ns

Power-on reset cancel
timing

SCS

*: See the table in "

t WIT

t WRL

t CRC* t CFC*

Serial timing" in Section 2 "AC Characteristics".

t WRH

0.8 V CC

0.2 V CC

18

MB90091A

Command List

■

• List of display control commands
First byte Second byte

Command code/data Data

No.

7654321076543210

Command

0 10000 0 A8 A7 0 A6 A5 A4 A3 A2 A1 A0 Set write address
1 10001 AT BS B1 0 BG BR BB CI CG CR CB Set character color
2 10010 0 M8 M7 0 M6 M5 M4 M3 M2 M1 M0 Set character code
3 10011 X9 X8 X7 0 0 G2 G1 G0 KGR KGD KGU Line control 1
4 10100 0 0 0 0 0 0 PC PI PG PR PB Line control 2
5 10101 ATK ATR ATB 0 W3 W2 W1 W0 K24 P0 DC Screen control 1
6 10110 SC CC BC 0 ATH UC UON UI UG UR UB Screen control 2

Function

10111 0 0 0 0 Y6 Y5 Y4 Y3 Y2 Y1 Y0

7

10111 1 0 0 0 X6 X5 X4 X3 X2 X1 X0
8 11000 SP2 SP1 SP0 0 SCG SCR SCB SBP SBG SBR SBB Sprite control
9 11001 0 SY8 SY7 0 SY6 SY5 SY4 SY3 SY2 SY1 SY0

10 11010 0 SX8 SX7 0 SX6 SX5 SX4 SX3 SX2 SX1 SX0

2

11011 0 DOT 0 0

11

11011 1 0

11100 0 0 SA7 0 SA6 SA5 SA4 SA3 SA2 SA1

12

11100 1 0 SAF 0 SAE SAD SAC SAB SAA SA9 SA8 Set transfer start address 2

11101 0 0 EA7 0 EA6 EA5 EA4 EA3 EA2 EA1 EA0 Set transfer end address 1

13

11101 1 VBS EAF 0 EAE EAD EAC EAB EAA EA9 EA8 Set transfer end address 2

14 11110 — — — — — — — — — — — (Reserved)
15 11111 — — — — — — — — — — — (Reserved)

*1: The SA0 and EA0 bits can only be set to “0“ and “1”, respectively.
*2: Set the bits to “1”.

1*

2

1*

0 DK6 DK5 DK4 DK3 DK2 DK1 DK0 Synchronization control 2

0 PR1 PR0 0 SC1 SC0 Synchronization control 1

Set vertical display start
position

Set horizontal display start
position

Set sprite vertical display
position

Set sprite horizontal display
position

2

Set transfer start address 1

SA0*

19

MB90091A

1. Command 0 (Set Write Address)

• Command format

MSB LSB

First byte

Second byte

• Function

Command 0 specifies the write address in display memory (VRAM). Before writing data using commands 1
and 2, use this command to determine the address to write that data at.

• Description

To set the VRAM address, specify the vertical column address (A8 to A5) and horizontal row address (A4 to
A0). The VRAM address is incremented automatically when a character code is set (by command 2).

A8 to A0: VRAM address

Set the VRAM address.
The A8 to A5 bits specify the vertical column address; the A4 to A0 bits specify the horizontal row address.
The row address is valid between 00H to 17H.
The column address is valid between 0H to BH.
Do not set the column or row address to any value outside the above valid range.

1

MSB LSB

0

A8 to A0: VRAM address

00000A8A7

A6 A4A5 A3 A2

A1 A0

20

2. Command 1 (Set Character Color)

• Command format

MSB LSB

MB90091A

First byte

Second byte

1

MSB LSB

0

AT
BS

B1 to BB
C1 to CB

0 0 0 1 AT BI

BG BBBR CI CG

: Specify character qualification display.
(Specify display of a character background, blinking, inverted shading.)
: Specify shaded background display.
: Set a character background color.
: Set a character color.

BS

CR CB

• Function

Command 1 sets the character color and character background color and specifies character qualification
display and shaded background display.

• Description

The character color , char acter background color , char acter qualification display, and shaded background dis­play can be set/specified for each character. Character background display, blinking, and inverted shading
can be used for characters for which character qualification display is specified.
These settings are written to VRAM and applied to the display screen the moment command 2 (Set Character
Code) is issued.

AT: Specify character qualification display.

(Specify display of a character background, blinking, inverted shading.)

AT = 0: Normal display (without character qualification)

This setting suppresses character background display, blinking, and inverted shading in shaded
background display.
The output level at the VOB2 pin becomes “L“.

AT = 1: Character qualification display

This setting enables character backg round display, blinking, and inverted shading in shaded back­ground display.
“H“ level output is enabled at the VOB2 pin.
Setting the command 5 (Screen Control 1) ATR bit to “1“ specifies character background display.

Setting the ATB bit for command 5 (Screen Control 1) to “1“ specifies blinking.
Setting both the ATK and BS bits for command 5 (Screen Control 1) to “1“ specifies inverted
shading.
Setting the command 6 (Screen Control 2) A TH bit to “1“ sets the output le vel at the VOB2 pin to “H“.

BS: Specify shaded background display.

BS = 0: Normal display (without shaded background display)
BS = 1: Shaded background display

Setting both the ATK and AT bits for command 5 (Screen Control 1) to “1“ specifies inverted
shading.

C1, CG, CR, CB: Set the character color.

B1, BG, BR, BB: Set the background color.

21

MB90091A

3. Command 2 (Set Character Code)

• Command format

MSB LSB

First byte

Second byte

• Function

Command 2 writes a character code to display memory (VRAM).

• Description

The character code data set by this command is written to display memory (VRAM) along with the character
color, char acter bac kground color, shaded background display, and character qualification display data set by
command 1 (Set Character Color).
Character code is represented by nine bits from M8 to M0, enabling use of 512 different character patterns
from 000H to 1FFFH stored in internal or external font ROM.
Upon completion of writing data, the write address is incremented automatically.

M8 to M0: Character code

1

MSB LSB

0

M8 to M0: Character code

000H to 1FFFH can be set to specify 512 different characters.

00100M8M7

M6 M4M5 M3 M2

M1 M0

22

4.Command 3 (Line Control 1)

y

y

•Command format

MSB LSB

MB90091A

First byte

Second byte

1

MSB LSB

0

X9 to X7
G2 to G0
KGR
KGD
KGU

0 0 1 1 X9 X7

0G1G2 G0 KGR

: Line horizontal display start position
: Character size
: Specify shaded background left/right joint display
: Specify shaded background downward joint display
: Specif

shaded background upward joint displa

X8

KGD KGU

•Function

Command 3 sets the line horizontal display start position, character size, and shaded background joint display
for each line.

•Description

Line control data set by this command is applied to the display screen when command 4 (Line Control 2) is
issued.

X9 to X7: Line horizontal display start position

The offset value can be set for each line, relative to the horizontal display start position set by
command 7-1 (Set Horizontal Display Start Position).

The valid range of values is 0 to 7H (In 2-character units: 0 to 14 characters)

•Line horizontal display start position

(X6 to X7)

(X9, X8, X7)

= (0, 0, 0)

= (0, 0, 1)

= (1, 0, 0)

012345678910

2 characters

ABCDEFGHI

8 characters

ABC

23

MB90091A

G2 to G0: Character size

G2 G1 G0 Character size

0 0 0 Normal
0 0 1 Single height x double width
0 1 0 Double height x single width
0 1 1 Double height x double width
1 0 0 Single height x quadruple width
1 0 1 (Setting prohibited)
1 1 0 Double height x quadruple width
1 1 1 (Setting prohibited)

Note: The horizontal display start position for “double width x single or double height“ display is shifted three dots

to the right from that for normal-size display. The horizontal display start position for “quadruple width x single

or double height“ display is shifted nine dots to the right from that for normal-size display. Be careful when

displaying normal-size and enlarged lines at the same time.

KGR: Specify shaded background left/right joint display.

KGR = 0: Display the shaded backgrounds horizontally adjacent to each other, joined together (without

display their adjacent, vertical sides).

KGR = 1: Display the shaded backgrounds horizontally adjacent to each other , separately for each character

(while displaying their adjacent, vertical sides).

KGD: Specify shaded background downward joint display.

KGD = 0: Display the shaded background including its lower side.
KGD = 1: Display the shaded background excluding its lower side.

KGU: Specify shaded background upward joint display

KGU = 0: Display the shaded background including its lower side.
KGU = 1: Display the shaded background excluding its lower side.

24

5. Command 4 (Line Control 2)

• Command format

MSB LSB

MB90091A

First byte

Second byte

1

MSB LSB

0

PC
PI to PB

0100000

0PC0PIPG

: Control the pattern background color.
: Set the pattern background color.

PR PB

• Function

Command 4 sets the pattern background color and controls it between color and monochrome modes.

• Description

The data set by this command is written to the column RAM specified by the VRAM column address set by
command 0 (Set Write Address), along with the line control data set by command 3 (Line Control 1).

The Line Control 1 and 2 data is applied to the display screen and the column address is incremented the
moment this command is issued.

PC: Control the pattern background color.

PC = 0: Display the pattern background in monochrome.

During the pattern background color output period, the COLOR pin remains at the “L“ output level.

PC = 1: Display the pattern background in color.

During the pattern background color output period, the COLOR pin remains at the “H“ output level.

PI, PG, PR, PG: Set the pattern background color.

25

MB90091A

6. Command 5 (Screen Control 1)

• - Command format

MSB LSB

First byte

Second byte

1

MSB LSB

0

ATK
ATR
ATB
W3 to W0
K24
P0
DC

0 1 0 1 ATK ATB

W3 W1W2 W0 K24

: Control inverted shading.
: Control character background display.
: Control blinking.
: Control the line spacing.
: Specify the shadow frame szize.
: Control the pattern background.
: Control displ

• Function

Command 5 controls the display screen.

• Description

ATK: Control inverted shading.

ATK = 0: Normal display

Inverted display is disabled.

ATK = 1: Enable inverted display.

This mode displays those characters in reverse video (with the inverted, shaded background)

for which the BS and AT bits for command 1 (Set Character Color) have been both set to “1“.

ATR

P0 DC

26

ATR: Control character background display.

ATR = 0: Normal display

Character background display is disabled.

ATR = 1: Enable character background display.

Character background display applies to those characters for which the BS and AT bits for

command 1 (Set Character Color) have been set to “0“ and “1“, respectively.

ATB: Control blinking.

ATB = 0: Normal display

Blinking is disabled.

ATB = 1: Enable blinking.

This mode causes those characters to blink f or which the AT bit for command 1 (Set Character

Color) has been set to “1“.

W3 to W0: Control the line spacing.

Set the line spacing in 2-dot units.
0 to 30 dots can be specified.

MB90091A

K24: Specify the shadow frame size.

K24 = 0: Set the height of shadow frames for shaded background display to 32 dots.
K24 = 1: Set the height of shadow frames for shaded background display to 24 dots.

P0: Control the pattern background.

P0 = 0: Set pattern background mode “pattern background 0“.

ROM data “1“ is displayed as a character dot.

P0 = 1: Set pattern background mode “pattern background 1“.

Character and pattern background dots are separately generated automatically from a ROM

data array.

Note: Note: As the pattern background mode, set the mode used when the relevant font was designed.

DC: Control display.

DC = 0: Disable output operation for displaying characters and sprite characters.

Only the screen background color can be output.

DC = 0: Enable output operation for displaying characters and sprite characters.

The screen background color can also be output.

27

MB90091A

7. Command 6 (Screen Control 2)

• Command format

MSB LSB

First byte

Second byte

1

MSB LSB

0

SC
CC
BC
ATH
UC
UON
UI to UB

0 1 1 0 SC BC

ATH UONUC UI UG

: Control the sprite character color.
: Control the character color.
: Control the character background.
: Control specified character output.
: Control the screen background color.
: Control screen beckground color output.
: Set the screen background color.

CC

UR UB

• Function

Command 6 specifies the character color, character background color, screen background color, sprite char­acter color, color/monochrome mode, specified character output. This command also enables or disables
screen background color output and sets the screen background color.

• Description

SC: Control the sprite character color.

SC = 0: Display the sprite character and sprite pattern background in monochrome.

During the sprite character/pattern background output period, the COLOR pin outputs the “L“

level signal.

SC = 1: Display the sprite character and sprite pattern background in color.

During the sprite character/pattern background output period, the COLOR pin outputs the “H“

level signal.

CC: Control the character color.

CC = 0: Display characters in monochrome.

During the character output period, the COLOR pin outputs the “L“ level signal.

CC = 1: Display characters in color.

During the character output period, the COLOR pin outputs the “H“ level signal.

BC: Control the character background.

BC = 0: Display the character background in monochrome.

During the character background output period, the COLOR pin outputs the “L“ level signal.

BC = 1: Display the character background in color.

During the character background output period, the COLOR pin outputs the “H“ level signal.

Note: Note: Use an external circuit to control display mode between monochrome and color using the COLOR pin.

28

MB90091A

ATH: Control specified character output.

ATH = 0: Normal display

The VOB2 pin outputs the “L“ level signal.

ATH = 1: The VOB2 pin outputs the “H“ level signal during the output period (24 x 32b dots period) for

those characters for which the AT bit for command 1 (Set Character Color) has been set to 1.

Note: Note: Use an external circuit to handle the VOB2 pin signal, allowing the specified character to be display ed

in halfbright, translucent, and other special display mode.

UC: Control the screen background color.

UC = 0: Display the screen background in monochrome.

During the screen background output period, the COLOR pin outputs the “L“ level signal.

UC = 1: Display the screen background in color.

During the screen background output period, the COLOR pin outputs the “H“ level signal.

UON: Control screen background color output.

UON = 0: Prevent the screen background color from being output.

During the screen background color output period, the IOUT , GOUT, ROUT, BOUT, and VOB1

pins output “L“ level signals.

UON = 1: Output the screen background color.

During the screen background color output period, the IOUT, GOUT, ROUT, and BOUT pins

output the screen background color and the VOB1 pin outputs the “L“ level signal.

UI, UG, UR, UB: Set the screen background color.

29

MB90091A

y

8. Command 7-0 (Set Vertical Display Start Position)

• Command format

MSB LSB

First byte

Second byte

1

MSB LSB

0

Y6 to Y0: Set the vertical displa

01110 0

Y6 Y4Y5 Y3 Y2

• Function

Command 7-0 sets the vertical display start position.

• Description

Y6 to Y0: Set the vertical display start position.

Set the position to start vertical display . The valid range of values is 00H to 7FH f or setting in 2-dot

units (0 to 254 dots).

The following illustrates the relationship betw een the vertical display start position and the *VSYNC

signal.

• Vertical display start position

0

Y1 Y0

start position.

30

VSYNC

20H

Vertical display

start position

9. Command 7-1 (Set Horizontal Display Start Position)

y

• Command format

MSB LSB

MB90091A

First byte

Second byte

1

MSB LSB

0

X6 to X0: Set the horizontal displa

01111 0

X6 X4X5 X3 X2

• Function

Command 7-0 sets the horizontal display start position.

• Description

X6 to X0: Set the horizontal display start position.

Set the position to start horizontal display. The valid range of values is 00H to 7FH for setting in 8-

dot units.

The following illustrates the relationship betw een the horizontal display start position and the YSYNC

signal.

• Horizontal display start position

0

X1 X0

start position.

Horizontal operation

started*

Horizontal display start position

HSYNC

* :Character size: About 100-dot clock for normal display

Double or quadruple width display is shifted further to the right from the above value.
For details, see Page 24

31

MB90091A

g

10.Command 8 (Sprite Control)

• Command format

MSB LSB

First byte

Second byte

1

MSB LSB

0

SP2 to SP0
SCG to SCB
SBP
SBG to SBB

1 0 0 0 SP2 SP0

SCG SCBSCR SBP SBG

: Set sprite character code.
: Set the sprite character color.
: Set the sprite pattern background.
: Set the sprite pattern back

SP1

SBR SBB

round color.

• Function

Command 8 sets the sprite character code, character color, pattern background display, and pattern back­ground color.

• Description

SP2 to SP0: Set sprite character code.

Specify the sprite character type from among character codes 1F8H to 1FFH representing eight
character types.

SP2 SP1 SP0 Sprite character

000 1F8

H

32

001 1F9
010 1FA
011 1FB
100 1FC
101 1FD
110 1FE
111 1FF

H
H
H

H

H
H
H

SCG to SCB: Set the sprite character color.

SBP: Control sprite pattern background display.

SBP = 0: Display no pattern background for the sprite.

This display mode is “No pattern background“ (displa ying only those character dots displayed
in “Pattern background 1“ mode).

SBP = 1: Display a pattern background for the sprite.

This display mode is “Pattern background 1“.

SBG to SBB: Set the sprite pattern background color.

11.Command 9 (Set Sprite Vertical Display Position)

y

• Command format

MSB LSB

MB90091A

First byte

Second byte

1

MSB LSB

0

SY8 to SY0: Set the sprite vertical displa

10010 SY7

SY6 SY4SY5 SY3 SY2

position.

• Function

Command 9 sets the sprite character vertical display position.

• Description

SY8 to SY0: Set the sprite vertical display position.

Set the vertical display position of the sprite character.
The valid range of values is 000H to 1FFH for setting in 2-dot units (0 to 1022 dots).
The following illustrates the relationship between the sprite vertical display position and the
VSYNC

signal.

• Sprite vertical display position

SY8

SY1 SY0

VSYNC

20H

Sprite vertical

display position

33

MB90091A

y

12.Command 10 (Set Sprite Horizontal Display Position)

• Command format

MSB LSB

First byte

Second byte

1

MSB LSB

0

SX8 to SX0: Set the sprite horizontal displa

10100 SX7

SX6 SX4SX5 SX3 SX2

position.

• Function

Command 10 sets the sprite character horizontal display position.

• Description

SY8 to SY0: Set the sprite horizontal display position.

Set the horizontal display position of the sprite character.
The valid range of values is 000H to 1FFH for setting in 2-dot units (0 to 1022 dots).
Setting these bits to 000H disables sprint display.
The following illustrates the relationship between the sprite horizontal display position and the
HSYNC

signal.

• Sprite horizontal display position

SX8

SX1 SX0

* :About 80-dot clock.

34

Sprite horizontal display started*

Sprite horizontal display position

HSYNC

13.Command 11-0 (Synchronization Control 1)

• Command format

MSB LSB

MB90091A

First byte

Second byte

1

MSB LSB

0

DOT
PR1, PR0
SC1, SC0
*: Set this bit to "1".

10110

1* PR10 PR0 0

: Control dot clock output.
: Control the prescaler.
: Control the scan system.

DOT

SC1 SC0

0

• Function

Command 10 controls synchronization.

• Description

DOT: Control dot clock output.

DOT = 0: Do not output the dot clock signal to the DOCK pin.
DOT = 1: Output the dot clock signal to the dock pin.

PR1, PR0: Control the prescaler.

PR1 PR0 Prescaler operation Corresponding dot clock

00 ÷2 25.0 to 42.0 MHz
01 ÷3 16.7 to 28.3 MHz
10 ÷5 10.0 to 17.0 MHz
11 ÷6 8.4 to 14.1 MHz

SC1, SC0: Control the scan system.

SC1 SC2 Scan system

0 0 Interlaced scan
0 1 Noninterlaced scan
1 0 Step scan
1 1 (Setting prohibited)

Interlaced or step scan operation requires the field control signal to be input to the EVEN pin.

35

MB90091A

y

14.Command 11-1 (Synchronization control 2)

• Command format

MSB LSB

First byte

Second byte

1

MSB LSB

0

DK6 to DK0: Control dot clock signals.
*: Set this bit to "1".

10111

DK6 DK4DK5 DK3 DK2

• Function

Command 11-1 controls dot clock signals.

• Description

DK6 to DK0: Control dot clock signals.

Set the divisor in 16-dot units for generating dot clock signals by dividing the FH (horizontal
frequency). The valid range of values is 00H to 7FH.
This enables the horizontal frequency to be divided by up to 2032.

15.Command 12-0 (Set Tr ansfer Start Address 1)

• Command format

MSB LSB

0

DK1 DK0

1*

36

First byte

Second byte

1

MSB LSB

0

SA7 to SA0: Lower address for starting transfer from command table ROM
*: The SA0 bit can onl

11000

SA6 SA4SA5 SA3 SA2

be set to "0".

SA1 SA0*

SA7

0

• Function

Command 12-0 sets the lower address for starting transfer of data from command table ROM.

• Description

SA7 to SA0: Lower address for starting transfer from command table ROM

These bits can be set only to an even address. The SA0 bit is set internally to “0“.
Data transfer from ROM is initiated by issuing command 13-1 (Set Transfer End Address 2).

16.Command 12-1 (Set Tr ansfer Start Address 2)

g

y

• Command format

MSB LSB

MB90091A

First byte

Second byte

1

MSB LSB

0

SAF to SA8: Upper address for startin

11001

SAE SACSAD SAB SAA

transfer from command table ROM

SA9 SA8

SAF

0

• Function

Command 12-1 sets the upper address for starting transfer of data from command table ROM.

• Description

SAF to SA8: Upper address for starting transfer from command table ROM

Data transfer from ROM is initiated by issuing command 13-1 (Set Transfer End Address 2).

17.Command 13-0 (Set Transfer End Address 1)

• Command format

MSB LSB

First byte

1

11010

EA7

0

MSB LSB

Second byte

0

EA6 EA4EA5 EA3 EA2

EA7 to SA0: Lower address for ending transfer from command table ROM
*: The EA0 bit can onl

be set to "1".

EA1 EA0*

• Function

Command 13-0 sets the lower address for ending transfer of data from command table ROM.

• Description

EA7 to EA0: Lower address for ending transfer from command table ROM

These bits can be set only to an odd address. The EA0 bit is set internally to “1“.
Data transfer from ROM is initiated by issuing command 13-1 (Set Transfer End Address 2).

37

MB90091A

g

18.Command 13-1 (Set Transfer End Address 2)

• Command format

MSB LSB

First byte

Second byte

1

MSB LSB

0

VBS
EAF to EA8

11011

EAE EACEAD EAB EAA

: Control the ROM transfer period.
: Upper address for endin

transfer from command table ROM

VBS

EA9 EA8

EAF

• Function

Command 13-1 sets the upper address for ending data transfer from command table ROM and specifies the
ROM transfer period to initiate ROM data transfer.

• Description

VBS: Control the ROM transfer period.

VBS = 0: Transfer data during the horizontal and vertical blanking intervals.
VBS = 1: Transfer data during the vertical blanking interval.

EAF to EA8: Upper address for ending transfer from command table ROM

Issuing this command initiates command table ROM transf er oper ation and sets the TRE pin output to the “H“
level. Upon completion of transfer operation, the TRE pin output becomes the “L“ level.

When the TRE pin output is at the “H“ level, do not issue command 0 to 4, 11, 12, or 13 by serial input
(commands 5 to 10 can be issued).

38

MB90091A

APPLICATION EXAMPLES

■

This section provides useful information for designing application systems using the MB90091A.

1. Power Supply

The MB90091A pairs of digital (VCC, VSS) and analog (A VCC, A VSS) power-supply and ground pins. The VCC and

CC

AV

power-supply pins are independent of each other; the VSS and AVSS ground pins are internally common.

Since the analog power supply supplies power and control voltage to the internal VCO, it requires special
consideration separately from the digital power supply.

In general, pay attention to the following points:

• Design the system so that the ground and power supply impedances are suppressed. In addition, the ground
line should be laid out on a ground plane including peripheral analog circuits.

CC

• The digital (V
and AVCC pins, and the VSS and AVSS pins must not have a potential different in between.

• To supply digital and analog power from the same power source, separately route the wires from the source
and use a choke coil to prev ent digital noise from interfering with the analog subsystem via the power source.

• Insert a relatively high-capacity (20 to 100 µF) electrolytic capacitor as a bypass capacitor between the pow er
supply and ground, separately between the digital and analog subsystems.

, VSS) and analog (AVCC, AVSS) power supplies must be separated from each other. The V

CC

2. Interface with a Microcontroller or Microcomputer

Operation of the MB90091 is controlled by a micro (controller or microcomputer). The MB90091 interf aces with
the micro by 8-bit serial transfer using four signal liens as shown below:

• Microcontroller/microcomputer interface

Micro

Data

SO

Serial clock

TC

Chip select

Port

Internal operation flag

Port

(or interrupt input)

Although most micros can be used for controlling the MB90091A, the one with an 8-bit serial interface (serial
port) is recommended because it can be connected directly to the MB90091A for high-speed command/data
transfer b y means of hardware. (The micro with a 4-bit serial interf ace can transfer data in tw o separate bloc ks.)

MB90091A

SIN

SCLK

SCS

TRE

Note: Keep in mind that some micros cannot be connected to the serial port depending on the type. Fujitsu 4- and

8-bit microcontrollers have no problem with the MB90091A.

39

MB90091A

3. Treatment of Unused Pins

Pins unused on the MB90091A must be treated as follows.

• Treatment of unused pins

Pin No.

DIP QFP

Pin name I/O Treatment

8 1 HSYNC
9 2 VSYNC

10 3 EVEN I Connect the pin to V

I—
I—

CC

or leave it open.
11 4 FLTIN O —
13 6 FLTOUT I —
15 8 FH
16 9 RESET
18

19
20
21
22
23
24
25

11
12
13
14
15
16
17
18

RD0
RD1
RD2
RD3
RD4
RD5
RD6

RD7
26 19 TEST I Connect the pin to V
28

29
30

21
22
23

TA16
TA17

TA18
31 24 FCS
32 25 TCS
33

34
35
36
38
40
41
42
43
44
45
46
48
49
50
51

26
27
28
29
31
33
34
35
36
37
38
39
41
42
43
44

RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8

RA9
RA10
RA11
RA12
RA13
RA14
RA15

O Leave the pin open.

I Connect the pin to VCC or leave it open.
I

Connect the pin to V

I

Connect the pin to V

I

Connect the pin to V

I

Connect the pin to V

I

Connect the pin to V

I

Connect the pin to V

I

Connect the pin to V

I

Connect the pin to V

O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

CC

or leave it open.

CC

or leave it open.

CC

or leave it open.

CC

or leave it open.

CC

or leave it open.

CC

or leave it open.

CC

or leave it open.

CC

or leave it open.

SS

.

O Leave the pin open.
O Leave the pin open.
O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

O

Leave the pin open.

40

52 45 TSEL I —
53 46 FSEL I —
54 47 SCLK I —
55 48 SIN I —

(Continued)

(Continued)

Pin No.

DIP QFP

MB90091A

Pin name I/O Treatment

56 49 SCS
58 51 TRE O Leave the pin open.
59 52 ROUT O Leave the pin open.
60 53 GOUT O Leave the pin open.
61 54 BOUT O Leave the pin open.
62 55 IOUT O Leave the pin open.
63 56 VOB1 O Leave the pin open.
64 57 VOB2 O Leave the pin open.

1 58 COLOR O Leave the pin open.
2 59 DOCK O Leave the pin open.
4 61 TESTCK I Connect the pin to V
5 62 TESTSW I Connect the pin to V
663 HBLNK
7 64 VBLNK

I—

I Connect the pin to VCC or leave it open.
I Connect the pin to VCC or leave it open.

CC

or leave it open.

CC

.

41

MB90091A

■ APPLIED CIRCUIT EXAMPLE

Sync signal

separation

Micro

GND

GND

V

CC

10µ

GND

47

GND

AV

10µ

AGND

V

GND

+

−

CC

CC

+

−

V

V

NC
NC
NC

NC

10 K

0.1µ

CC

CC

V

0.1µ

CC

+

1µ

−

GND

V

10 K

10 K

CC

63
64

49
48
47
51

46

45

21
22
23
19

62
61

10
30
50

20
32
40
60

1
2
3

8

9

7

5

MB90091A

HSYNC
VSYNC
EVEN
HBLNK
VBLNK

SCS
SIN
SCLK
TRE

FSEL

TSEL

TA16
TA17
TA18
TEST

TESTSW
TESTCK

FH

CC

V
V

CC

V

CC

V

SS

V

SS

V

SS

V

SS

RESET

CC

AV

AV

SS

ROUT
GOUT
BOUT

IOUT

VOB1

COLOR

VOB2

DOCK

RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8

RA9
RA10
RA11
RA12
RA13
RA14
RA15

FCS

TCS

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

52
53
54
55
56
58
57
59

Display control

This circuit is not required when internal ROM is used.

(512-character font ROM)

64K-byte ROM

26
27
28
29
31
33
34
35
36
37
38
39
41
42
43
44

24

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

OE
CE

GND

(Command table ROM)

32K-byte ROM

A0
A1
A2
A3
A4
A5
A6
A7
A8

A9
A10
A11
A12
A13
A14

25

OE

CE

GND

18
17
16
15
14
13
12
11

V

: +5 V (digital)

CC

: Ground (digital)

GND

: +5 V (analog)

CC

AV
AGND

: Grond (analog)

O1
O2
O3
O4
O5
O6
O7
O8

O1
O2
O3
O4
O5
O6
O7
O8

42

6

FLTOUT

FLTIN

4

330

51

+

−

1µ
AGND

Adjustment is required depending on synchronization system.

ORDERING INFORMATION

■

Part number Package Remarks

MB90091A

MB90091AP

MB90091APF

64-pin plastic SH-DIP

(DIP-64P-M01)

64-pin plastic QFP

(FPT-64P-M06)

43

MB90091A

PACKAGE DIMENSIONS

■

64 pin, Plastic SH-DIP

(DIP-64P-M01)

58.00

2.283

+0.22
–0.55

+.008
–.022

INDEX-1

INDEX-2

5.65(.222)MAX

3.00(.118)MIN

+0.50

1.00

–0
+.020

.039

–0

1.778±0.18

1.778(.070)
MAX

C

1994 FUJITSU LIMITED D64001S-3C-4

(.070±.007)

0.45±0.10

(.018±.004)

55.118(2.170)REF

0.51(.020)MIN

17.00±0.25
(.669±.010)

0.25±0.05

(.010±.002)

19.05(.750)

15°MAX

TYP

Dimensions in mm (inches).

(Continued)

44

64 pin, Plastic QFP

(FPT-64P-M06)

51

52 32

24.70±0.40(.972±.016)

20.00±0.20(.787±.008)

MB90091A

3.35(.132)MAX

33

(Mounting height)

0.05(.002)MIN
(STAND OFF)

INDEX

64

LEAD No.

C

1994 FUJITSU LIMITED F64013S-3C-2

1

1.00(.0394)
TYP (.016±.004)

0.10(.004)

18.00(.709)REF

22.30±0.40(.878±.016)

0.40±0.10

"A"

19

0.20(.008)

14.00±0.20

(.551±.008)

20

M

"B"

18.70±0.40

(.736±.016)

Details of "A" part

0.18(.007)MAX

0.63(.025)MAX

0.25(.010)

0.30(.012)

12.00(.472)
REF

0.15±0.05(.006±.002)

Details of "B" part

16.30±0.40
(.642±.016)

0 10°

1.20±0.20

(.047±.008)

Dimensions in mm (inches).

45

MB90091A

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: [phone]
Fax: [phone]

All Rights Reserved.

The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.

North and South America

FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: [phone]
Fax: [phone]

Europe

FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: [phone]
Fax: [phone]

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: [phone]
Fax: [phone]

The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.

FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.

Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.

48

F9704



FUJITSU LIMITED Printed in Japan

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.