FUJITSU MB90091A DATA SHEET

查询MB90091供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

DS04-28823-2E

ASSP Image Control

CMOS

Intelligent On-screen Display
Controller (IOSDC)

MB90091A

DESCRIPTION

■

The MB90091A is the multisync, on-screen display controller that supports a variety of TV systems such as
NTSC, PAL, double-scan NTSC, double-scan PAL, 1250HDTV, and 1125HDTV as well as personal computer
monitor display systems such as VGA and XGA.

The MB90091A contains display memory (VRAM) and character font R OM, allowing characters to be displa y ed
with few external devices. The device also contains command table ROM storing display command data,
minimizing the load on the microcomputer.

The on-screen display configuration is up to 24 characters × 12 lines, with each character consisting of 24 × 32
dots. The font ROM integrates 512 different character patterns.

The character signal output is an RGB1 digital output. The display color of each character can be specified
from among 16 colors. A color/monochrome select signal output is also provided f or display either in 16 diff erent
colors or in 16-level gray scale.

The character display functions include character background display, shaded background display, and sprite
character display functions, contributing to providing colorful display screens.

PACKAGES

■

64 pin, Plastic SH-DIP

64 pin, Plastic QFP

(DIP-64P-M01)

(FPT-64P-M06)

MB90091A

FEATURES

■

• Screen display capacity : Up to 24 characters x 12 lines (288 characters)

• Font size : 24 x 32 dots (horizontal x vertical)

• Font types : 512 different characters (character codes 000H to 1FFH)
8 different sprite characters (character codes 1F8H to 1FFH)

(Internal or external ROM selectable)

• Display modes : Trimmed display (pattern background 0, 1, or none)
Character background (settable for each character)

Shaded background (settable for each character)

• Sprite character display : Capable of displaying one character (selectab le from among 8 types of char­acters) on the screen

Sprite character colors : 8 colors
Sprite trimming colors : 8 colors
Sprite display position : Settable in 2-dot units on the screen

• Character sizes : Normal, double width, double height, double width x double height, quadruple
width, quadruple width x double height

(Set for each line)

• Display colors : Character color : 16 colors (set for each character)
Trimmed background color : 16 colors (set for each line)
Character background color : 16 colors (set for each character)
Screen background color : 16 colors

• Display position control : Horizontal display start position : Set in 8-dot units
Vertical display start position : Set in 2-dot units

Line spacing control : Set in 2-dot units (0 to 30 dots)

• Character/color signal output : ROUT, GOUT, BOUT, IOUT (color signals)
COLOR (color/monochrome control signal)

VOB1 (character + pattern background + character background + screen
background: all-output signal)

VOB2 (character + pattern backg round + character background: specified­character output signal)

• Supported TV systems : NTSC, PAL, double-scan NTSC, double-scan PAL, 1250HDTV, 1125HDTV,
etc.

Personal computer monitor display systems such as VGA

• Intelligent features : Automatic control of operation using on command table ROM
Command table ROM: Internal 32K bytes + external 32K bytes available

• Microcontroller/microcomputer interface : 8-bit serial input (3 signal input pins

Chip select: SCS
Serial clock: SCLK
Serial data: SIN

• Package : SH-DIP-64, QFP-64

• Miscellaneous : Power-on reset circuit integrated

2

PIN ASSIGNMENTS

■

MB90091A

(TOP VIEW)

1COLOR VOB264
2DOCK VOB163
3V SS IOUT62
4TESTCK BOUT61
5TESTSW GOUT60
6HBLNK ROUT59
7VBLNK TRE58
8HSYNC V CC57
9VSYNC SCS56
10EVEN SIN55
11FLTIN SCLK54
12AV SS FSEL53
13FLTOUT TSEL52
14AV CC RA1551
15FH RA1450
16RESET RA1349
17V CC RA1248
18RD0 V SS47
19RD1 RA1146
20RD2 RA1045
21RD3 RA944
22RD4 RA843
23RD5 RA742
24RD6 RA641
25RD7 RA540
26TEST V SS39
27V SS RA438
28TA16 V CC37
29TA17 RA336
30TA18 RA235
31FCS RA134
32TCS RA033

(SH-DIP-64P)

(Continued)

3

MB90091A

(

)

(Continued)

(TOP VIEW)

VBLNK64

HBLNK63

TESTSW62

TESTCK61

V SS60

DOCK59

COLOR58

VOB257

VOB156

IOUT55

BOUT54

GOUT53

ROUT52

1HSYNC TRE51
2VSYNC V CC50
3EVEN SCS49
4FLTIN SIN48
5AV SS SCLK47
6FLTOUT FSEL46
7AV CC TSEL45
8FH RA1544
9RESET RA1443
10V CC RA1342
11RD0 RA1241
12RD1 V SS40
13RD2 RA1139
14RD3 RA1038
15RD4 RA937
16RD5 RA836
17RD6 RA735
18RD7 RA634
19TEST RA533

20V SS

21TA16

22TA17

23TA18

FPT-64P-M06

24FCS

25TCS

26RA0

27RA1

28RA2

29RA3

30V

CC

31RA4

32V

SS

4

PIN DESCRIPTION

■

MB90091A

Pin No.

DIP QFP

8 1 HSYNC
9 2 VSYNC

10 3 EVEN I

11 4 FLTIN O

13 6 FLTOUT I
15 8 FH
16 9 RESET
18

19
20
21
22
23
24
25

11
12
13
14
15
16
17
18

Pin name I/O Function

RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7

Horizontal sync signal input pin

I

Dot clock generation is based on the cycle of the signal.

I Vertical sync signal input pin

Field control signal input pin
Input of an “L” level signal to this pin causes the font ROM address
LSB pin (RA0) to output an “L” level signal.
Input of an “H“ level signal to this pin causes the font ROM address
LSB pin (RA0) to output an “H” level signal (when normal-size
characters are displayed).
This pin is disabled in noninterlaced mode.

Output pin for horizontal-sync phase comparison result signal
This pin is connected to an external lowpass filter.

Internal VCO voltage input pin
This pin inputs the voltage signal from the external lowpass filter.

O Output pin for AFC-generated horizontal sync signal

Reset pin

I

This pin is enabled after release from a power-on reset.

External ROM data input pin

I

This pin inputs data from external font ROM or external command
data ROM.

26 19 TEST I
28

29
30

31 24 FCS
32 25 TCS

21
22
23

TA16
TA17
TA18

Test signal input pin
This pin inputs an “L” level (fixed) signal during normal operation.

O Test signal output pin

O External font ROM chip select pin
O Chip select pin for external command table ROM

(Continued)

5

MB90091A

(Continued)

Pin No.

DIP QFP

Pin name I/O Function

33
34
35
36
38
40
41
42
43
44
45
46
48
49
50
51

52 45 TSEL I

53 46 FSEL I

54 47 SCLK I Shift clock input pin for serial transfer

26
27
28
29
31
33
34
35
36
37
38
39
41
42
43
44

RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8

RA9
RA10
RA11
RA12
RA13
RA14
RA15

External ROM address signal output pin
This pin outputs the signal specifying the external font ROM or
external command table ROM address.

External font ROM addresses

O

RA0 to RA4 : Raster addresses
RA5 to RA11 : Character codes (M0 to M6)
RA12, RA13 : Character horizontal address

= (0, 0): Left byte
= (1, 0): Center byte
= (0, 1): Right byte

RA14, RA15 : Character codes (M7, M8)

Address control input pin for command table ROM
“L” level input : 0000H to 7FFFH Internal ROM

8000H to FFFFH External ROM

“H” level input : 0000H to 7FFFH External ROM

8000H to FFFFH Internal ROM

Internal/external font ROM select pin
“L” level input : Select internal ROM.
“H” level input : Select external ROM.

55 48 SIN I Serial data input pin

Chip select pin

56 49 SCS

58 51 TRE O

59
60
61
62

63 56 VOB1 O

64 57 VOB2 O

52
53
54
55

ROUT
GOUT
BOUT

IOUT

I

For serial transfer, set this pin to the “L” level.
This pin is also used to cancel a power-on reset.

Output pin for the signal indicating internal operation
This pin outputs an “H” level signal during data transfer from
command table ROM.

Chrominance signal output pin
For output of a character, character background, pattern background,

O

shaded background, screen background, or sprite character
(including a pattern background), this pin outputs the chrominance
signal.

Pin for specifying the chrominance signal output period
This pin outputs an “H” level signal f or output of a char acter , character
background, pattern background, shaded background, screen
background, or sprite character (including a pattern background.

Pin for specifying the specified character output period
When the command 6: ATH bit = “1”, this pin outputs an “H” level
signal in the character output period (24 x 32 dot period) when the
command 1: AT bit = “1”.
The pin can be used for display control by an external circuit, for
example, for halftone display control.

(Continued)

6

(Continued)

Pin No.

Pin name I/O Function

DIP QFP

1 58 COLOR O

MB90091A

Color/monochrome select signal output pin
This pin allows “H” or “L” level output in each of the character,
character background, line background, screen background, and
sprite output periods to be specified depending on the internal
register setting.
Color/monochrome display is controlled by an external circuit.
(The following correspondence is used for convenience:

“L” level: Monochrome display
“H” level: Color display)

259DOCKO

461TESTCKI

562TESTSWI

Dot clock output pin
This pin outputs a dot clock signal when the command 11:DOT = “1”.

Test signal input pin
This pin inputs an “H” level (fixed) signal during normal operation.

Test signal input pin
This pin inputs an “H” level (fixed) signal during normal operation.

Horizontal blanking signal input pin

6 63 HBLNK

I

This pin stops display signal output (“L” lev el output) when it inputs an
“L” level signal.

Vertical blanking signal input pin

7 64 VBLNK

I

This pin stops display signal output (“L” lev el output) when it inputs an
“L” level signal.

17
37
57

27
39
47

3
14 7 AV
12 5 AV

10
30
50

20
32
40
60

CC

V

SS

V

CC
SS

— +5 V power supply pin

— Ground pin

— +5V power supply pin for VCO
— Ground pin for VCO

7

MB90091A

BLOCK DIAGRAM

■

SCS

SIN

SCLK

FLTIN

LPF

FLTOUT

FH

MB90091A

Serial input

control

Dot clock
generator

Command

table ROM

control

Command

table ROM

TRE
TSEL

TCS

RA0 to 15
RD0 to 7

Command

table ROM

DOCK

HSYNC
VSYNC

EVEN

RESET

Display

memory

control

Display
memory

(VRAM)

Resets each block.

Font ROM

control

Font ROM

Display data

output control

FCS

Font ROM

FSEL

BOUT
ROUT
GOUT
IOUT
VOB 1
VOB 2
COLOR

8

ABSOLUTE MAXIMUM RATINGS

■

Parameter Symbol

MB90091A

(VSS = AVSS = 0 V)

Ratings

Unit

Min. Max.

Power supply voltage *

Input voltage *
Output voltage *

2

3

CC

1

V

AV

V

V

CC

IN

OUT

SS –

V

0.3 V

SS –

V

0.3 V

SS –

V

0.3 V

SS –

V

0.3 V

SS +

7.0 V

SS +

7.0 V

SS +

7.0 V

SS +

7.0 V
Power consumption Pd — 500 mW
Operating temperature Ta 0 +
Storage temperature Tstg –

CC

*1: AV
*2: Neither V

and VCC must have equal potential.

IN

nor V

OUT

must exceed “VCC + 0.3 V”.

55 + 150 °C

70 °C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

■

(VSS = AVSS = 0 V)

Values

Parameter Symbol

Unit Remarks

Min. Max.

CC

V

4.75 5.25 V Specification guarantee range

Power supply voltage *

AV

CC

4.75 5.25 V

V

IHS1

2.4 V

CC +

0.3 V RD0 to RD7 inputs

“H” level input voltage

V

V

IHS2
ILS1

0.8 × V

CC

CC +

V

0.3 V Other inputs

– 0.3 0.45 V RD0 to RD7 inputs

“L” level input voltage

ILS2

V
Operating temperature Ta 0 +
Analog input voltage V

CC

* :AV

and VCC must have equal potential.

IN

SS –

V

0.3 0.2 × V

CC

70 °C

V Other inputs

0VCCV FLTOUT input

WARNING: Recommended operating conditions are nor mal operating ranges for the semiconductor device. All

the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.
No warranty is made with repect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.

9

MB90091A

ELECTRICAL CHARACTERISTICS

■

1. DC Characteristics

Parameter Symbol Pin Conditions

CC

= 4.75 V

“H” level output voltage V

“L” level output voltage V

OH

All out-

put pins

OL

V

OH

I

= – 2.0 mA

VCC = 4.75 V

OL

I

= 4.0 mA

HSYNC
VSYNC

EVEN

RESET

RD0 to

Input current I

RD7

IL

TSEL
FSEL

VCC = 5.25 V

IL

I

= 4.0 mA

SCLK

SIN

SCS
HBLNK
VBLNK

VCC = AVCC = 5.25 V

CC

Supply current I

CC

V

AV

DOCK = 42 MHz

CC

No load

Values

Unit

Min. Typ. Max.

4.0 — — V

——0.4V

— — – 50 mA

——40mA

10

2. AC Characteristics

(1) Serial input timing

Parameter Symbol Pin

MB90091A

CC

(V

= AVCC = 5.0 V ± 5%, VSS = AVSS = 0 V, Ta = 0°C to +70°C)

Values

Min. Max.

Unit

Shift clock cycle time t

t

Shift clock pulse width

Shift clock signal rise/fall time

Shift clock start time t
Data setup time t
Data hold time t
Chip select end time t

Chip select signal rise/fall time

SCS

0.8 V CC

t CFC

0.2 V CC

t SS

t CYC

CVC

WCH

WCL

t

CR

t

CF

t

SS

SU

H

EC

CRC

t

CFC

t

SCLK 1000 — ns

450 — ns

SCLK

450 — ns

—200ns

SCLK

—200ns

SCLK 200 — ns

SIN 200 — ns
SIN 100 — ns

SCS 500 — ns

—200ns

SCS

—200ns

0.8 V CC

0.2 V CC

t CRC

t EC

SCLK

SIN

t CR t CF

0.8 V CC

0.2 V CC

t WCLt WCH

t H

t SU

0.8 V CC

0.2 V CC

11

MB90091A

(2) Vertical and horizontal sync signal input timings

Parameter Symbol Pin

CC

(V

= AVCC = 5.0 V ± 5%, VSS = AVSS = 0 V, Ta = 0°C to +70°C)

Values

Min. Max.

Unit

Horizontal sync signal rise time t
Horizontal sync signal fall time t
Vertical sync signal rise time t
Vertical sync signal fall time t
Horizontal sync signal pulse width t
Vertical sync signal pulse width t
Horizontal sync signal setup time t
Vertical sync signal setup time t

HSYNC

t HF

VSYNC

HR

HF

VR

VF
WH
WV

HVST
HVHD

0.8 V CC

0.2 V CC

0.8 V CC

0.2 V CC

HSYNC —200ns
HSYNC —200ns
VSYNC —200ns
VSYNC —200ns
HSYNC 1—µs
VSYNC 2—H
VSYNC 5—µs
VSYNC 5—µs

0.8 V CC

0.2 V CC

t WH

t HR

0.8 V CC

0.2 V CC

12

HSYNC

VSYNC

t VF

t HVST

t WV

t VR

0.8 V CC

t HVHD

0.8 V CC

0.2 V CC

MB90091A

The MB90091A outputs display signals in synchronization with sync signals input from external circuits. The
signals required for controlling synchronization are the horizontal sync signal (input via the HSYNC
sync signal (input via the VSYNC pin), and field control signal (input via the EVEN pin).

The following examples illustrate external sync signal input timings applicable to general interlaced display.
Noninterlaced display does not require the EVEN pin signal.

• External sync signal input timing examples

(1) Field A

2

VSYNC

Slow *

pin), vertical

FH
(HSYNC)

EVEN

(2) Field B

VSYNC

FH
(HSYNC)

EVEN

*1

2

*

2

Fast *

*1

2

*

*1: Input the horizontal sync signal to the HSYNC pin.

Input of a composite sync signal may change the FH
the VSYNC

pulse, requiring a caution to be used for the timing of input to the EVEN pin. (See *2 below.)

signal cycle due to the PLL lock disturbed around

*2: The input levels of the EVEN pin input signal in fields A and B are determined depending on the

relationship between the VSYNC
the field in which the FH

pulse after the rise of the VSYNC pulse appears fast. Pin the “H” level signal

and FH pulse positions. To the EVEN pin, input the “L” level signal in

in the field in which it appears slow.
The EVEN pin input signal should vary in the undisplay period such as around the VSYNC

pulse.

13

MB90091A

(3) RESET signal input timing

Parameter Symbol Pin

CC

(V

= AVCC = 5.0 V ± 5%, VSS = AVSS = 0 V, Ta = 0°C to +70°C)

Values

Min. Max.

Unit

Reset input pulse width t

RESET

WR

RESET 10 — µs

0.2 V CC0.2 V CC

t WR

14