FUJITSU MB90050 DATA SHEET

查询MB90050供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP For Screen Display Control

CMOS

On-Screen Display Controller

MB90050

DESCRIPTION

■

The MB90050 is an on-screen display controller for displaying text and graphics on the TV screen. The MB90050 controls a display area of 35 characters b y 16 lines, and provides each char acter composed of 24

× 32 dots at most. The display functions include a wealth of characters with qualifying functions such as char acter background shading (shadow casting) , sprite character functions and graphic character functions, contr ibuting to the use of control GUI displays. The MB90050 incorporates display memory (VRAM) , character font ROM, and sync signal generation circuit and video signal generation circuit supporting the NTSC and PAL systems, allowing text and graphics to be displayed in conjunction with a small number of external components.

DS04-28829-2E

FEATURES

■

• Main screen display capacity 35 characters × 16 lines (maximum 560 characters)

• Character configuration Normal characters : 24 × 32 dots Graphic characters : 12 × 16 dots* (colorable per 1 dot)

PACKAGE

■

48-pin plastic QFP

(FPT-48P-M15)

(Continued)

MB90050

• Font display configuration Three horizontal width settings (selectable setting L/M/S for each character) per character.

L size : 24 dots M size : 18 dots S size : 12 dots

Two vertical height settings (selectable A/B for each line) per line.

A : 18 to 32 dots (setting per 2 dots)

B : 18 to 32 dots (setting per 2 dots) (These sizes are dot sizes of typical character. Each size of graphic characters uses half the number of dots of typical characters. Note, ho we ver, that both of the typical and graphic characters are the same in character area size.)

• Character types Usable all 512 character types (font ROM+, font RAM) Font ROM : 512 character types (all area user setting) Font RAM : 8 character types (all area user command setting) Capable of setting a specific eight-character area in font ROM so that the area is replaced with font RAM.

•Display modes Character : Normal character/graphic character (set for each character) Character trimming : Side trimming 1/side trimming 2/patern background 1/patern background 2

(set for each screen)

Character background : None/Solid-fill/Shaded background (concave) /Shaded background (convex)

(set for each character)

Line background : None/Solid-fill/Shaded background (concave) /Shaded background (convex)

(set for each line) Character enlargement : Normal, Double width, Double height, Double width × doub le height (set for each line) Brink : OFF/ON (set for each character)

• Main screen display position control Horizontal display position : Control in 2-dot units (movable through the entire screen) Vertical display position : Control in 2-dot units (movable through the entire screen) Line spacing control : 0 to 14 dots, 2-dot units (set for each line) Sprite character display control Capable of displaying one block for an arbitrary character on the topmost layer on the screen. Sprite character display : OFF/ON (graphic character display) Sprite character types : 256 types (character codes 000 Sprite character configuration : 1 character/2 characters horizontal/2 characters vertical/

2×2 characters Sprite character horizontal display position : Control in 1-dot units Sprite character vertical display position : Control in 1-dot units Screen background color display control Capable of displaying an arbitrary color on the entire bottommost layer on the screen. Screen background color display : OFF/ON

• Display colors Digital output : 16 colors selectable from among 64 colors (built in palette circuit) Video output : Any 16 colors selectable (Command setting enable)

to 0FFH)

(Continued)

• Display colors and setting units Character color : 16 colors (set for each character) Character background color : 16 colors (set for each character) Character trimming color : 16 colors (set for each line) Line background color : 16 colors (set for each line) Graphic character color : 16 colors (set for each dot) Sprite character color : 16 colors (set for each dot) Screen background character color : 16 colors (set for each dot) Screen background color : 16 colors (set for all screen) Shaded background frame highlight color : 16 colors (set for all screen) Shaded background frame shadow color : 16 colors (set for all screen)

• Digital display signal output Color signal output : DCOL5 to DCOL0 pins (6 bits) Display period signal output : DB pin Translucent display period signal output : DH pin

• Analog (video) signal input/output Composit video input/output : VIN, VOUT pins Y/C video input/output : YIN, YOUT pins, CIN, COUT pins

• Internal sync control Internal sync signal generator and video signal generator supporting the NTSC and PAL systems.

• External interface 16-bit serial input (3-signal input)

Chip select signal Serial clock signal Serial data signal

• Package QFP-48P (FPT-48P-M15)

• Supply voltage +5 V±10%

MB90050

* : 1 dot of graphic characters is the same size as 2 × 2 dots of normal characters.

MB90050

PIN ASSIGNMENT

■

(TOP VIEW)

FLDI VSYNCI HSYNCI

VSS

EXS

FSC4O VSYNCO HSYNCO CSYNCO

VBLKO

1 2 3 4 5 6 7 8 9 10 11 12

YOUT

TESTI2

YIN

SS2

CC2

CIN

MB90050

COUT

SS1

VOUT

CC1

VIN

TESTI1

36 35 34 33 32 31 30 29 28 27 26 25

PO3 PO2 DCOL5 DCOL4 DCOL3 DCOL2 DCOL1 DCOL0 DCLKO DB DH RESET

FLDO

SYNCST

SCLK

SIN

BUSY

EXD

VCC

PO0

PO1

(FPT-48P-M15)

PIN DESCRIPTIONS

■

MB90050

Pin name I/O

no.

20,

19 15 CS

16 SCLK I C

17 SIN I C

18 BUSY O F

2 VSYNCI

3 HSYNCI

1FLDIID

EXS,

EXD,

Circuit

type

I/O A

I/O B

Function

Crystal oscillation circuit pins for color burst clock generator. Connect an external crystal oscillator (14.31818 MHz for NTSC or 17.734475 MHz for PAL) and load capacitance (C) to these pins to form a crystal oscillation circuit.

LC oscillation circuit pins for display dot clock generator. Connect these pins to external “L” and “C” to from an LC oscillation circuit.

Chip select signal input pin. For serial command transfer, set this pin to the Low level.

Serial clock signal input pin. This pin feeds a clock signal upon transfer of a serial command. It feeds serial data at the rising edge.

Serial data signal input pin. Input data during serial command transfer.

Busy signal output pin. This pin outputs a significant level signal during VRAM filling. Do not input a serial command while the pin outputs the significant level signal. Supplying a low level signal to the CS put period terminates the VRAM fill operation and causes this pin to output an insignificant level signal. The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting. When the RESET turns off the internal pull-up resistor, and sets the output to OFF (output tied to the low).

Vertical sync signal input pin. Active low signal or active high signal input is command-selectable for the pin. When the RESET pin inputs the low level signal, this pin inputs the active low signal.

Horizontal sync signal input pin. Active low signal or active high signal input is command-selectable for the pin. When the RESET pin inputs the low level signal, this pin inputs the active low, horizontal sync signal.

Field signal input pin. The internal field signal identically detected from among input sync signals or the input signal to this pin is command-selectable for field control. During operation under external synchronization control, the input signal is used to control the least significant bit of the font ROM/RAM raster address. The input signal to this pin is disabled during operation under internal synchronization control.

pin inputs a low level signal, this pin outputs the busy signal,

pin during the significant level signal out-

(Continued)

MB90050

Pin no.

9VSYNCO

10 HSYNCO

11 CSYNCO

12 VBLKO O F

13 FLDO O F

14 SYNCST O F

name

Circuit

I/O

type

Function

Vertical sync signal output pin. The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting. When the RESET pull-up resistor and sets the output to OFF (output tied to the high).

Horizontal sync signal output pin. The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting. When the RESET pull-up resistor and sets the output to OFF (output tied to the high).

Composite sync signal output pin. The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting. When the RESET pull-up resistor and sets the output to OFF (output tied to the high).

Vertical blanking interval (VBI) output pin. The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting. When the RESET pull-up resistor and sets the output to OFF (output tied to the low).

Field signal output pin. During operation under internal synchronization control, this pin outputs the internally generated field signal. During operation under external synchronization control, the pin outputs the field signal (internally detected field signal or external input field signal) used for internal operations. The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting. When the RESET pull-up resistor and sets the output to OFF (output tied to the low).

Synchronization detection signal output pin. This pin outputs a significant level signal with a sync signal detected and an insignificant level signal with no sync signal detected. The pin enables output (ON/OFF) control, output logic control, and internal pullup ON/OFF control depending on the command setting. When the RESET pull-up resistor and sets the output to OFF (output tied to the low).

pin inputs the low level signal, this pin turns off the internal

(Continued)

MB90050

Pin no.

28 DCLKO O G

8FSC4OO G

26 DH O (I) H

27 DB O (I) H

34, 33, 32, 31, 30,

36, 35, 24,

name

DCOL5, DCOL4, DCOL3, DCOL2, DCOL1,

DCOL0

PO3, PO2, PO1,

PO0

Circuit

I/O

type

O (I) H

Function

Dot clock signal output pin. This pin outputs an LC oscillation clock signal. The pin enables output (ON/OFF) control depending on the command setting. The normal clock (that stops oscillation during horizontal synchronization) or continuous clock (that does not stop oscillation during horizontal synchronization*) can be command-selected for the output using the command setting for output selection control (CKS). When the TESTI2 clock signal that does not stop oscillation during horizontal synchronization (where the output selection control (CKS) setting is disabled). When the RESET * : For continuous clock, this pin is used for frequency measurement. To measure

the dot clock, the pin sets display signal output that is not the standard and cannot display correctly.

Crystal oscillator 4FSC clock signal output pin. This pin enables output (ON/OFF) control depending on the command setting. The crystal oscillation clock (4FSC) or its 1/4 frequency clock (FSC) can be command-selected for the output using the command setting for output selection control (FSS). When the TESTI2 signal (where the output selection control (FSS) setting is disabled). When the RESET signal.

Halftone display period signal output pin. This pin enables output (ON/OFF) control and output logic control depending on the command setting. When the RESET (output tied to the low). (The input feature of the pin is a test function. Use the pin usually only for output.)

Display period signal output pin. This pin enables output (ON/OFF) control and output logic control depending on the command setting. When the RESET sets the output to OFF (entering the low level signal fixed output state). (The input feature of the pin is a test function. Use the pin usually only for output.)

Display color signal output pin. This pin enables output (ON/OFF) control and output logic control depending on the command setting. When the RESET sets the output to OFF (entering the low level signal fixed output state). (The input feature of the pin is a test function. Use the pin usually only for output.)

Port signal output pin. This pin enables output level (High/Low) control depending on the command setting. When the RESET OFF (entering the low level signal fixed output state). (The input feature of the pin is a test function. Use the pin usually only for output.)

pin inputs a low level signal, this pin outputs the continuous

pin inputs the low level signal, the pin outputs a dot clock signal.

pin inputs the low level signal, this pin outputs the 4FSC clock pin inputs the low level signal, this pin outputs the 4FSC clock

pin inputs the low level signal, this pin sets the output to OFF

pin inputs the low level signal, this pin

pin inputs the low level signal, this pin sets the output to

(Continued)

MB90050

(Continued)

Pin no.

25 RESET

37 TESTI1 47 TESTI2

name

I/O

Circuit

IE I E Test signal input pin. Input High level signal during normal operation.

38 VIN I I

46 YIN I I

44 CIN I I

40 VOUT O I

type

Function

Reset signal input pin. Upon input of the low level signal, this pin causes an internal reset. After the power supply is inserted, the reset input is required for normal operation. During regular operation, the pin inputs the high level signal.

Test signal input pin. Input High level signal during normal operation. (Input of the Low level signal activates test mode operation.)

Composite video signal input pin. This pin inputs a DC-reproduced signal of 2 V

(pedestal level 1.57 V, sync tip level 1 V) .

P-P

Luminance video signal (Y video signal) input pin. This pin inputs a DC-reproduced signal of 2 V

(pedestal level 1.57 V, sync

P-P

tip level 1 V) . Saturation video signal (C video signal) input pin.

This pin inputs a signal at 1.57 VDC and a color burst signal amplitude of 0.57 V

P-P

Composite video signal output pin. This pin outputs a signal of 2 V When the RESET

signal inputs the low level signal, this pin outputs the black

(pedestal level 1.57 V, sync tip level 1 V) .

P-P

video (pedestal level without color burst) signal.

48 YOUT O I

42 COUT O I

39 AV

43 AV

41,45AV

CC1

CC2

SS1

SS2

⎯⎯

Luminance video signal (Y video signal) output pin. This pin outputs a signal of 2 V When the RESET

pin inputs the low level signal, this pin outputs the black

(pedestal level 1.57 V, sync tip level 1 V) .

P-P

video (pedestal level) signal. Saturation video signal (C video signal) output pin.

This pin outputs a signal at 1.57 VDC and a color burst signal amplitude of

0.57 V When the RESET

P-P

pin inputs the low level signal, this pin outputs the black

video signal (a DC voltage of 1.57 V without color burst). Power supply pin for digital circuit. These pins supply

5 V and make all VCC

pins same potential. Digital ground pins. These pins make all V

pins and AV

SS1

/AV

pins same

SS2

potential. Power supply pin for analog circuit and composite video signal Input/Output

(VIN-VOUT) circuit. This pin supplies +5 V. Input analog ground level when not using this analog circuit.

Power supply pin for analog circuit, luminance video signal Input/Output (YIN-YOUT) circuit, and saturation video signal Input/Output (CIN-COUT) circuit. This pin supplies +5 V. Input analog ground level when not using this analog circuit.

Analog ground pins. AV V

pins make these pins same potential.

pin makes AV

SS1

pin same potential.

SS2

I/O CIRCUIT TYPES

■

Type Circuit Remarks

• Crystal oscillation Oscillator feedback resistor

EXS

(approx. 1MΩ)

MB90050

TEST signal

• LC oscillation

EXD

STOP signal

• TTL level, Hysteresis input

TTL

• CMOS level, Hysteresis input

CMOS

• CMOS level, Hysteresis input

5 V

with pull-up resistor (approx. 50 kΩ)

CMOS

(Continued)

MB90050

(Continued)

Type Circuit Remarks

• Nch open-drain output

5 V

Pch

Nch

5 V

Pch

Pull-up control signal

Nch

with pull-up resistor SW (approx. 50 kΩ)

• CMOS output

•CMOS I/O

5 V

Pch

Input is for test.

Nch

TEST signal

Input (TEST)

• Analog I/O CMOS analog SW

Control signa

■ BLOCK DIAGRAM

SIN

SCLK

Serial input control

MB90050

Each block

VIN YIN CIN

HSYNCI

VSYNCI

FLDI

SYNCST

HSYNCO VSYNCO CSYNCO

FLDO

VBLKO

BUSY

Sync control

NTSC/PAL

signal

generator

circuit

Video signal generator circuit

Palette (4 bits→6 bits)

Display Memory control

Analog

switch

Output control

VOUT YOUT COUT

DCOL5 to DCOL0 DB DH

EXS

FSC4O

EXD

DCLKO

RESET

VRAM (35 characters × 16 lines)

4FSC clock

oscillation

circuit

Dot clock

oscillation

circuit

Font ROM (512 characters)

Each block

All reset

Font RAM (8 characters)

Port control

PO3 PO2 PO1 PO0

MB90050

ABSOLUTE MAXIMUM RATINGS

■

Parameter Symbol

Unit Remarks

Min Max

Rating

Power supply voltage*

AV Input voltage* Output voltage*

V “L” level maximum output current I “H” level maximum output current I Power consumption P

CC1

CC2

OUT

VSS − 0.5 VSS + 7.0 V *2 VSS − 0.5 VSS + 7.0 V *2 VSS − 0.5 VSS + 7.0 V *2 VSS − 0.5 VCC + 0.5 V VSS − 0.5 VCC + 0.5 V

⎯ 15 mA ⎯−15 mA ⎯ 500 mW

Operating temperature Ta −40 +85 °C Storage temperature Tstg −55 +125 °C

*1 : The parameter is based on VSS = AV *2 : Do not make a potential difference between AV

SS1

= AV

SS2

= 0 V.

(AV

SS1

/AV

) pins and VSS pin.

SS2

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

■

MB90050

(VSS = AV

SS1

= AV

SS2

= 0 V)

Parameter Symbol

Unit

Min Max

Value

Power supply voltage

“H” level input voltage

“L” level input voltage

AV AV

V V

V V A

CC1

CC2

IH1

IH1S

IH2S

IL1

IL1S

IL2S

VIN1

4.5 5.5 V

4.5 5.5 V *1, *2

4.5 5.5 V *1, *3

0.7 × V

0.8 × V

0.6 × V

VSS − 0.3 0.3 × V VSS − 0.3 0.2 × V

VCC + 0.3 V (H) VCC + 0.3 V (D, E) VCC + 0.3 V (C)

VSS − 0.3 0.6 V (C)

0AV

CC1

Analog input voltage

VIN2

0AV

CC2

Operating temperature Ta −40 +85 °C

*1 : Do not make a potential difference between AV *2 : It is possible to set AV *3 : It is possible to set A V

= AVSS (AV

CC1

= AVSS (A V

CC2

SS1

/AV

SS2

(AV

/AV

SS1

) when not using composite video signal (VIN pin, VOUT pin) .

SS2

) pins and VSS pin.

SS2

) when not using Y/C separated video signals (YIN pin, Y OUT pin,

CIN pin and COUT pin) .

Remarks

(circuit type)

V(H) V(D, E)

V VIN pin V YIN pin, CIN pin

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

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