Fujitsu F2MC-8L Family series, MB89950 Series Hardware Manual

FUJITSU SEMICONDUCTOR

CONTROLLER MANUAL

MICROCONTROLLERS

CM25-10130-1E

F2MC-8L FAMILY

MB89950 SERIES

HARDWARE MANUAL

PREFACE

The MB89950 series of microcontrollers are mid-range of microcontroller. They are
general-purpose and high-speed products in the F2MC-8L Family series of 8-bit single-

chip microcontr ollers operating at lo w voltages . It has UA RT, PWM, LCD cont roller and etc.
This manual covers the functions and operations of the MB89950 series of microcontrollers.

Refer to the

F2MC-8L Family Software Manual

for instructions.

iii

Table of Contents

1. GENERAL ......................................................................................................................1-1

1.1 Features ...................................................................................................................1-3

1.2 Product Series .........................................................................................................1-4

1.3 Block Diagram ..........................................................................................................1-5

1.4 Pin Assignment ........................................................................................................1-6

1.5 Pin Description .........................................................................................................1-8

1.6 Handling Devices ...................................................................................................1-12

2. HARDWARE CONFIGURATION .................................................................................... 2-1

2.1 CPU .........................................................................................................................2-3

2.1.1 Memory Space ...............................................................................................2-3

2.1.3 Internal Registers in CPU ...............................................................................2-6

2.1.4 Clock Control Block ........................................................................................2-9

2.1

2.2 Peripherals .............................................................................................................2-18

2.2.2 8-bit PWM Timer (Timer 1) ...........................................................................2-25

2.2.3 Pulse-width Count Timer (Timer 2) ..............................................................2-30

2.2.4 UART ...........................................................................................................2-37

2.2.5 8-bit Serial I/O ..............................................................................................2-50

2.2.6 External Interrupt ..........................................................................................2-56

2.2.7 LCD Controller/driver ....................................................................................2-59

2.2.8 Time-base Timer ..........................................................................................2-69

2.2.9 Watchdog Timer Reset .................................................................................2-71

3. OPERATION ..................................................................................................................3-1

4. INSTRUCTIONS ............................................................................................................. 4-1

5. MASK OPTIONS ............................................................................................................. 5-1

APPENDIX ..................................................................................................................... App-1

2.1.2 Arrangement of 16-bit Data in Memory Space ...............................................2-5

.

5 Interrupt Controller ....................... ............................................. ....... ............ 2- 15

2.2.1 I/O Ports .......................................................................................................2-18

3.1 Clock Pulse Generator .............................................................................................3-3

3.2 Reset .......................................................................................................................3-4

3.2.1 Reset Operation ..............................................................................................3-4

3.2.2 Reset Sources ................................................................................................3-5

3.3 Interrupt ...................................................................................................................3-6

3.4 Low-power Consumption Modes .............................................................................3-8

3.5 Pin States for Sleep, Stop and Reset ......................................................................3-9

4.1 Legend .....................................................................................................................4-3

4.2 Transfer Instructions ................................................................................................4-4

4.3 Operation Instructions ..............................................................................................4-5

4.4 Branch Instructions .......................... ...... ............................................. ....... ..............4-6

4.5 Other Instructions .....................................................................................................4-7

2

4.6 F

MC-8L Family Instruction Map .............................................................................4-8

Appendix A I/O Map ................................................................................................. App-3

Appendix B Writing EPROM .................................................................................... App-5

iv

Tables

Table 1–1 Types and Functions of MB89950 Series of Microcontrollers ...........................1-4

Table 1–2 Pin Description ..................................................................................................1-8

Table 1–3 Pin Description for External ROM ......................................................................1-9

Table 2–1 Table of Reset and Interrupt Vectors .................................................................2-4

Table 2–2 Operating Mode of Low-power Consumption Modes ......................................2-11

Table 2–3 Selection of Oscillation Stabilization Time .......................................................2-12

Table 2–4 Sources of Reset .............................................................................................2-14

Table 2–5 List of Port Functions .......................................................................................2-18

Table 2–6 Operation Modes of UART ..............................................................................2-46

Table 2–7 Clock Division Ratio..........................................................................................2-48

Table 2–8 Input Clock of Baud Rate Generator ...............................................................2-48

Table 2–9 Selection of Baud Rate (When Dedicated Baud Rate Generate Used) ..........2-49

Table 3–1 Interrupt Sources and Interrupt Vectors ............................................................3-7

Table 3–2 Low-power Consumption Mode at Each Clock Mode ........................................3-8

Table 3–3 Pin State of MB89950 ........................................................................................3-9

Table 5–1 Mask Options .....................................................................................................5-3

Table 5–2 Recommended Port/Segment Mask Option Combinations ...............................5-3

v

Figures

Fig. 1.1 Block Diagram (MB89953) .............................................................................................1-5

Fig. 1.2 Pin Assignment of MB89953 and MB89P955 (QFP-64, pitch: 0.65 mm) .......................1-6

Fig. 1.3 Pin Assignment of MB89PV950 (MQFP-64, pitch: 0.8 mm) ...........................................1-7

Fig. 1.4 I/O Circuits ....................................................................................................................1-10

Fig. 2.1 Memory Space of MB89950 Series Microcontrollers .....................................................2-3

Fig. 2.2 Arrangement of 16 bit Data in Memory Space ...............................................................2-5

Fig. 2.3 Arrangement of 16 bit Data during Execution of Instruction ...........................................2-5

Fig. 2.4 Structure of Processor Status .........................................................................................2-7

Fig. 2.5 Rule for Translating Real Addresses at General-purpose Register Area .......................2-7

Fig. 2.6 Register Bank Configuration ...........................................................................................2-8

Fig. 2.7 Interrupt-processing Flowchart .....................................................................................2-17

Fig. 2.8 Ports 0, 1 and 2 ............................................................................................................2-20

Fig. 2.9 Port 3 ............................................................................................................................2-22

Fig. 2.10 Port 4 ..........................................................................................................................2-24

Fig. 2.11 Timer Operation ..........................................................................................................2-28

Fig. 2.12 PWM Pulse Output .....................................................................................................2-29

Fig. 2.13 Measurement of High Pulse Width .............................................................................2-35

Fig. 2.14 Operation of Noise Clearing Circuit ............................................................................2-36

Fig. 2.15 RDRF Flag Set Timing ...............................................................................................2-46

Fig. 2.16 ORFE Flag Set Timing ...............................................................................................2-47

Fig. 2.17 TDRE Flag Set Timing ................................................................................................2-47

Fig. 2.18 Transfer Data Format (Synchronous Transfer) ..........................................................2-47

Fig. 2.19 Shift Start/Stop Timing ................................................................................................2-55

Fig. 2.20 Input/Output Shift Timing ............................................................................................2-55

Fig. 2.21 LCD Controller /Driver Block Diagram ........................................................................2-59

Fig. 2.22 Example of Waveform at Pin Corresponding to the RAM Data for Display ................2-64

Fig. 2.23 Example of Waveform at Pin Corresponding to the RAM Data for Display ................2-65

Fig. 2.24 Example of Waveform at Pin Corresponding to the RAM Data for Display ................2-66

Fig. 2.25 Connection Examples for Supply Power for Driving LCD ...........................................2-67

Fig. 2.26 Built-in Voltage Dividing resistors ...............................................................................2-68

Fig. 3.1 Clock Pulse Generator ...................................................................................................3-3

Fig. 3.2 Outline of Reset Operation .............................................................................................3-4

Fig. 3.3 Reset Vector Structure ...................................................................................................3-4

Fig. 3.4 Interrupt-processing Flowchart .......................................................................................3-6

vi

1. GENERAL

1.1 Features ................................................................................ 1-3

1.2 Product Series ........................................................ ............... 1-4

1.3 Block Diagram .................................................... .... ..... .......... 1-5

1.4 Pin Assignment ....................................................... ..... ..... ..... 1-6

1.5 Pin Description ..................................... .... ..... ..... ................... 1-8

1.6 Handling Devices ........................ ..... ....................................1-12

GENERAL

2

The MB89950 series of single-chip compact microcontroller using the F

MC-8L core for which can operate
at high-speeds and low voltages. They contain peripheral such as timers, UART, serial interfaces, and
external interrupts, including a 168-pixel LCD controller/driver; they are best suited for use in LCD panels.

1.1 Features

•

High-speed processing even at low voltages

Minimum instruction execution time: 0.8 µs/5 MHz (V

2

•

F

MC-8L family CPU core

Instruction system most suited to controller

- Multiplication and division instructions

- 16-bit arithmetic operation

- Instruction test and branch instruction

- Bit manipulation instruction, etc.

•

LCD controller/driver

- Maximum 42 segment outputs × 4 common outputs

- Built-in LCD driver split resistor

CC

= 5 V)

•

Three-channel timer unit

- 8-bit PWM timer: (usable as both reload timer and PWM timer)

- 8-bit pulse width count timer: (usable as both reload timer)

- 20-bit time-based counter

•

Two serial interfaces

- 8-bit synchronous serial interface (The transfer direction can be selected to communicate with various
equipment.)

- UART (5, 7, and 8-bit transfers possible)

•

External-interrupt input: 2 channels

- 2 channels can be used to clear the low-power consumption modes.
(An edge-detection function is provided)

•

Low-power consumption modes

- Stop mode (Oscillation stops to minimize the current consumption.)

- Sleep mode (The CPU stops to reduce current consumption to about 30% of normal.)

1– 3

GENERAL

1.2 Product Series

Table 1–1 lists the types and functions of the MB89950 series of microcontrollers.

Table 1–1 Types and Functions of MB89950 Series of Microcontrollers

Model name MB89951 MB89953 M B89P 955 MB89PV950

Classification

ROM capacity

RAM capacity

CPU function

Port

PWM Timer

Pulse-width Counter

Timer

Serial I/O

UART

LCD controller/driver

External Interrupt

Standby Mode

Package

Operation Voltage

EPROM

*2

Mass-produced product

(Mask ROM product)

4K × 8 bits

(internal ROM)

128 × 8 bits 256 × 8 bits 512 × 8 bits 1024 × 8 bits

Number of basic instructions:136
Instruction bit length:8 bits
Instruction length:1 to 3 bytes
Data bit length:1, 8, 16 bits
Minimum instruction execution time:0.8 µs at 5 MHz (V
Interrupt processing time:7.2 µs at 5 MHz (V

I/O port (N-ch open drain): 22 (also used as segment pin)
I/O port (N-ch open drain): 4 (two of them are also used as LCD bias pins)
I/O port (CMOS): 7 (6 used as peripheral)
Total: 33 (Maximum)

8-bit reload timer operation (toggle output possible)
8-bit resolution PWM operation

Operation clock (pulse-width count timer output: 0.8
8-bit reload timer operation

8-bit pulse width measurement (continuous measurement, High- and Low-width measurement, and
one-cycle measurement)
Operation clock (0.8

8-bit length, selectable from least significant bit (LSB) first or most significant bit (MSB) first, transfer
clock (external, 1.6

5-, 7-, 8-bit transfers possible, internal baud-rate generator (Max. 78125 bps/5 MHz)
Common output: 4

Segment output: 42 (max.)
Operation mode: 1/2 bias and 1/2 duty, 1/3 bias and 1/3 duty, 1/3 bias and 1/4 duty
LCD controller display RAM capacity: 42 × 4 bits
LCD driver split resistor: built-in (external resistor selectable)

2 (edge selectable: one serving as pulse-width count timer input)
Sleep mode, stop mode

µ

µ

s, 6.4 µs, 25.6 µs/5 MHz)

2.2 V to 6.0 V 2.7 V to 6.0 V

8K × 8 bits

(internal ROM)

s, 3.2 µs, 25.6 µs/5 MHz)

FPT-64-M09 MQP-64C-P01

not applicable

*1 Mask Option.

*2 Varies according to conditions such as frequency.

One-time programmable Piggyback/Evaluation

16K × 8 bits

(Internal PROM; writable

by general-purpose

writers)

= 5 V)

CC

= 5 V)

CC

*1

µ

s, 12.8 µs, 51.2 µs/5 MHz)

and development

product

32K × 8 bits

(External ROM)

MBM27C256A-25

(LCC package)

1– 4

1.3 Block Diagram

GENERAL

Internal bus

RST

P20 to P25/

SEG36 to

SEG41

P30, P31

P33/V2
P32/V1

X0
X1

Main oscillator

circuit

Clock control

Reset circuit

(WDT)

Port 2

6

N-ch open-drain I/O port

Port 3

N-ch open-drain I/O port

Time-base timer

8-bit PWM timer

External interrupt

8-bit
pulse width
count timer

8-bit serial

UART

CMOS I/O port

Noise

clear

Port

4

P41/PWM

P40

P42/PWC/
INT1

P45/SCK
P44/SO
P43/SI

P46/INT0

R A M (256 × 8 bits)

F

CPU

R O M (8 K × 8 bits)

Other pins

MODA

V

, VSS

CC

2

MC-8L

N-ch open-drain I/O port

LCD controller driver

Fig. 1.1 Block Diagram (MB89953)

1– 5

Port

0/1

8

P00/SEG20 to
P07/SEG27

8
P10/SEG28 to

P17/SEG35

20

SEG0 to
SEG19

4

COM0 to
COM3

V3

1.4 Pin Assignment

SEG5

SEG6

SEG7

SEG8

GENERAL

SEG9

SEG10

SEG11

SEG12

VCCSEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG4
SEG3
SEG2
SEG1

SEG0
COM3
COM2
COM1
COM0

V3
P33/V2
P32/V1

P31
P30
P40

P41/PWM

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

646362616059585756555453525150

Top view

QFP-64

171819202122232425262728293031

X1

V

SS

P45/SCK

P46/INT0

P25/SEG41

P24/SEG40

P23/SEG39

P22/SEG38

P21/SEG37

RST

P43/SI

P42/INT1/PWC

X0

MODA

P44/SO

32

P20/SEG36

49

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P00/SEG20
P01/SEG21
P02/SEG22
P03/SEG23
P04/SEG24
P05/SEG25
P06/SEG26
P07/SEG27
P10/SEG28
P11/SEG29
P12/SEG30
P13/SEG31
P14/SEG32
P15/SEG33
P16/SEG34
P17/SEG35

Fig. 1.2 Pin Assignment of MB89953 and MB89P955 (QFP-64, pitch: 0.65 mm)

1– 6

GENERAL

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

Vcc

SEG13

SEG14

SEG15

SEG16

SEG17

64636261605958575655545352

SEG5
SEG4
SEG3
SEG2
SEG1

SEG0
COM3
COM2
COM1
COM0

V3
V2/P33
V1/P32

P31
P30
P40

PWM/P41

INT1/PWC/P42

SI/P43

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

84838281807978

85
86
87
88
89
90
91
92
93

94959665666768

(Top View)

20212223242526272829303132

X0

X1

RST

SO/P44

Vss

MODA

SCK/P45

51
50
49
48

SEG38/P22

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

SEG37/P21

77
76
75
74
73
72
71
70
69

INT0/P46

SEG41/P25

SEG40/P24

SEG39/P23

SEG18
SEG19
SEG20/P00
SEG21/P01
SEG22/P02
SEG23/P03
SEG24/P04
SEG25/P05
SEG26/P06
SEG27/P07
SEG28/P10
SEG29/P11
SEG30/P12
SEG31/P13
SEG32/P14
SEG33/P15
SEG34/P16
SEG35/P17
SEG36/P20

Fig. 1.3 Pin Assignment of MB89PV950 (MQFP-64, pitch: 0.8 mm)

Pin assignment on package top (MB89PV950 only

)

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

65 N.C. 73 A2 81 N.C. 89 OE
66 Vpp 74 A1 82 O4 90 N.C.
67 A12 75 A0 83 O5 91 A11
68 A7 76 N.C. 84 O6 92 A9
69 A6 77 O1 85 O7 93 A8
70 A5 78 O2 86 O8 94 A13
71 A4 79 O3 87 CE

95 A14

72 A3 80 Vss 88 A10 96 Vcc

N.C.: Non connection pin. Keep open.

1– 7

GENERAL

1.5 Pin Description

Table 1–2 lists the pin functions and shows the Fig. 1.4 input/output circuits.

T able 1–2 Pin Description

Pin No

0.65 0.8

22 23
23 24
21 22

19 20

48 to 41 49 to

42

40 to 33 41 to

34

32 to 27 33 to

28

14 to 11 15 to

12

12 to 11 13 to

12

15 16

16 17

17 18

18 19

20 21

25 26

Pin Name Circuit Function

X0 A Clock oscillator pins
X1
MODA B Operation-mode select pins

RST

P00/SEG20
to
P07/SEG27

P10/SEG28
to
P17/SEG35

P20/SEG36
to
P25/SEG41

P30 to P31 F N-channel open-drain type general-purpose I/O ports

P32/V1 to
P33/V2

P40 E General-purpose I/O ports

P41/PWM E General-purpose I/O port

P42/PWC/
INT1

P43/SI E General-purpose I/O port

P44/SO E General-purpose I/O port

P45/SCK E General-purpose I/O port

C Reset I/O pin

D N-channel open-drain type general-purpose I/O ports

D N-channel open-drain type general-purpose I/O ports

D N-channel open-drain type general-purpose I/O ports

D N-channel open-drain type general-purpose I/O ports

E General-purpose I/O port

This pin is connected directly to V

This pin consists of an N-ch open-drain output with a pull-up resistor and
hysteresis input. A Low l evel is pu t out from this pin. A “LOW” vo ltage o n
this port generates a RESET condition.

Also serve as LCDC controller segment outputs.
Switching between port output and segment output is performed by the
mask option every 8 bits.

Also serve as LCDC controller segment outputs.
Switching between port output and segment output is performed by the
mask option.

Also serve as LCDC controller segment outputs.
Switching between port output and segment output is performed by the
mask option.

Also serve as LCDC controller power supply.

A pull-up resistor option is provided.

Serves as PWM timer toggle output (PWM).
A pull-up resistor option is provided.

Also serves as pul se-width coun t tim er input (PWC) a nd exter nal interr upt
input (INT1). The PWC and INT1 inputs are hysteresis type. A pull-up
resistor option is provided.

Also serves as serial I/O and UART data input (SI). The SI input is
hysteresis type.
A pull-up resistor option is provided.

Also serves as serial I/O and UART data output (SO).
A pull-up resistor option is provided.

Also serves as serial I/O and UART clock input/output (SCK). The SCK
input is hysteresis type.
A pull-up resistor option is provided.

SS

with pull down resistor.

1– 8

GENERAL

Pin No

0.65 0.8

26 27

5 to 1
64 to 57
55 to 49

9 to 6 7 to 10

10 11
56 57
24 25

6 to 1
64 to
58
56 to
50

Table 1–2 Pin Description

Pin Name Circuit Function

P46/INT0 E General-purpose input port

Also serves as external-interrupt input (INT0).
The input is hysteresis type.
A pull-up resistor option is provided.

SEG0 to

G For LCDC controller segment ouput

SEG19

COM0 TO
COM3

V3 - For LCD driver power supply
Vcc - Power Pin
Vss - Power (GND) Pin

G For LCDC controller common output

(Continued)

T able 1–3 Pin Description for External ROM

• External EPROM pins (for MB89PV950)

Pins No. Pin Name I/O Function

66 Vpp O For High-level output
67 A12
68 A7
69 A6
70 A5
71 A4
72 A3
73 A2
74 A1
75 A0
77 O1

79 O3
80 Vss O For power supply (GND)
82 04
83 O5
84 O6
85 O7
86 O8

87 CE
88 A10 O For address output
89 OE O
91 A11

93 A8
94 A13
95 A14
96 Vcc O For EPROM power supply

O For address output

I For data input78 O2

I For data input

O

O For address output92 A9

O For address output

For ROM out put enable
The High level is output in standby mode .

For ROM output enable.
The Low level is always output.

1– 9

GENERAL

Table 1–3 Pin Description for External ROM

(Continued)

• External EPROM pins (for MB89PV950)

Pins No. Pin Name I/O Function

65
76
81
90

N.C. —

For internal connection
Keep open.

Fig. 1.4 I/O Circuits

Classification Circuit Remarks

A • Crystal oscillator

X1

• Feedback resistor: About 1 M
5 V (1 to 5 MHz)

X0

Standby control signal

B • CMOS input

• Pull down resistor (N-ch)

Ω

/

R

C • Output pull-up resistor (P-ch):

Ω

• About 50 M

R

P-ch

N-ch

• Hysteresis input

(5 V)

D • N-ch open-drain output

• CMOS input

N-ch

• The segment output is optional.

1– 10

GENERAL

Fig. 1.4 I/O Circuits

(Continued)

Classification Circuit Remarks

E • CMOS output

• CMOS input

R

P-ch

P-ch

N-ch

• Hysteresis input
(peripheral input)

• The pull-up resistor is optional.

F • N-ch open-drain output

• CMOS input

N-ch

G • LCDC output

1– 11

1.6 Handling Devices

(1) Preventing latch-up

GENERAL

Latchup may occur on CMOS ICs if voltage higher than V

or lower than VSS is applied to input and output

CC

pins other than medium to high-voltage pins or if higher than the voltage which shows on Absolute Maximum
Ratings is applied between V

and VSS.

CC

When latch-up occurs, supply current increases rapidly and might thermally damage elements. When using,
take great care not to exceed the absolute maximum ratings.

(2) Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull­down resistor.

(3) Power Supply Voltage Fluctuations

Although V

power supply voltage is assured to operate within the rated, a rapid change to the IC is therefore

CC

cause malfunctions, ev en if it occurs within the rated range. Stabilizing voltage supplied of the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that V

(P-P. value) will be less that 10% of the standard V

value at the commercial frequency (50 to 60 Hz) and

CC

ripple fluctuations

CC

the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when
power is switched.

(4) Precaution When Using an External Clock

Even when an external clock is used, oscillation stabilization time is required for power-on reset (option
selection) and release from stop mode.

(5) Recommended Screening Conditions

The OTPROM product should be screened by high-temperature aging before mounting.

Verify program

High-temperature aging (150°C, 48H)

Read

Mount

The programming test cannot be performed for all bits of the preprogrammed OTPROM product due to its
characteristics. Consequently, 100% programming yielding cannot be ensured.

1– 12

2. HARDWARE CONFIGURATION

2.1 CPU ... ...................................................................................2-3

2.2 Peripherals .......................................................................... 2-18

HARDWARE CONFIGURATION

This chapter describes each block of the CPU hardware.

CPU

0000
0080

00C0

0100

0140

H
H

H

H

Register

H

MB89951

I/O

Reserved

RAM

2.1 CPU

This section describes the memory space and register composing CPU
hardware.

2.1.1 Memory Space

F2MC-8L CPU has a memory space of 64 Kilobytes. All I/O, data, and
program areas are located in this space. The I/O area is near the lowest
address and the data area is immediately above it. The data area can be
divided into register, stack, and direct-address areas according to the
applications. The program area is located near the highest address, and
the tables of interrupt and reset vectors and vector-call instructions are at
the highest address in this area. Fig.2.1 shows the structure of the
memory space for the MB89950 series of microcontrollers.

MB89PV950

H

H

H

Register

H

I/O

RAM

0000

0080

0100

0180

H

H

H

Register

H

MB89953

I/O

RAM

0000

0080

0100

0200

0280

H

H

H

Register

H

H

MB89P955

I/O

RAM

0000

0080

0100

0200

F000

0480

H

Vacant

E000

H

ROM

Vacant

C000

H

ROM

Vacant

8000

H

ROM

Vacant

H

ROM

Fig. 2.1 Memory Space of MB89950 Series Microcontrollers

2– 3

HARDWARE CONFIGURATION

CPU

(1) I/O area

This area is where various peripherals such as control and data registers
are located. The memory map for the I/O area is given in APPENDIX A.

(2) RAM area

This area is where the static RAM is located. Addresses from

017F

(

H

0100

H

to

013F

in MB89951,

H

0100

to

H

01FF0

in MB89P955 and

H

0100

H

to

MB89PV950) are also used as the general-purpose register area. One can
access these registers through register-related instructions or just treat
them as ordinary RAM.

(3) ROM area

This area is wh ere the in ternal ROM is locate d. Addres ses from

are also used for the table of interrupt, reset and vector-call

FFFF

H

FFC0

H

to

instructions. T able 2–1 shows the correspondence between each interrupt
number or reset and the table addresses to be referenced for the MB89950
series of microcontrollers.

Table 2–1 Table of Reset and Interrupt Vectors

CALLV #0
CALLV #1
CALLV #2
CALLV #3
CALLV #4
CALLV #5
CALLV #6
CALLV #7

Table address

Upper data Lower data

FFC0
FFC2
FFC4
FFC6
FFC8
FFCA
FFCC
FFCE

H

H

H

H

H

H

H

H

FFC1
FFC3
FFC5
FFC7
FFC9
FFCB
FFCD
FFCF

H

H

H

H

H

H

H

H

Interrupt #B
Interrupt #A

Interrupt #9
Interrupt #8
Interrupt #7
Interrupt #6
Interrupt #5
Interrupt #4
Interrupt #3
Interrupt #2
Interrupt #1
Interrupt #0

Reset mode

Reset vector

FFFC

Note:

FFFD

is already reserved . W hen using

H

in the reset mode, write

H

Table address

Upper data Lower data

00

FFE5
FFE7
FFE9
FFEB
FFED
FFEF
FFF1
FFF3
FFF5
FFF7
FFF9
FFFB

FFFF

.

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

FFE4

H

FFE6

H

FFE8

H

FFEA

H

FFEC

H

FFEE

H

FFF0

H

FFF2

H

FFF4

H

FFF6

H

FFF8

H

FFFA

H

----- FFFD
FFFE

H

2– 4

HARDWARE CONFIGURATION

CPU

Before execution

A

1234

2.1.2 Arrangement of 16-bit Data in Memory Space

When the MB89950 series of microcontrollers handle 16-bit data, the data
written at the lower address is treated as the upper 8-bit data and that written
at the next address is treated as the lower 8-bit data as shown in Fig. 2.2.

Memory

MOVW ABCDH , A

ABCF

H

ABCE

H

ABCD
ABCC

H
H
H

Fig. 2.2 Arrangement of 16 bit Data in Memory Space

This is the same when 16 bits are specified by the operand during execution
of an instruction. Bits closer to the OP code are treated as the upper byte
and those next to it are treated as the lower byte. This is also the same
when the memory address or 16-bit immediate data is specified by the
operand.

After execution

1234

A

Memory

ABCF

H

34

H

ABCE

H

12

H

ABCD
ABCC

H
H
H

[Example]

MOV A, 5678

MOV A, #1234

; Extended address

H

; 16-bit immediate data

H

Assemble

XXXXH XX XX

60 56 78

XXXX
XXXX
XXXX

H

H

H

E4 12 34
XX

; Extended address

; 16-bit immediate data

Fig. 2.3 Arrangement of 16 bit Data during Execution of Instruction

Data saved in the stack by an interrupt is also treated in the same manner.

2– 5

HARDWARE CONFIGURATION

CPU

2.1.3 Internal Registers in CPU

The MB89950 series of microcontrollers have dedicated registers in the
CPU and general-purpose registers in memory. The types of dedicated
registers are as follows.

•

Program counter (PC) 16-bit length register indicating the location

where instruction s ar e stored .

•

Accumulator (A) 16-bit length register storing results of

operations temporarily. The lower one byte
is used to execute 8-bit data processing
instructions.

•

Temporary accumulator (T) 16-bit length register where the operations

are performed between this register and the
accumulator. The lower one byte is used to
execute 8-bit data processing instructions.

•

Index register (IX) 16-bit length register for index modification.

•

Extra pointer (EP) 16-bit length register for indicating memory

address.

•

Stack pointer (SP) 16-bit length register indicating stack area.

•

Processor status (PS) 16-bit length register where register

pointers and condition codes are stored.

16 bits

P C

A

T

IX

EP

SP

PS

Program counter

Accumulator

Temporary accumulator

Index register

Extra pointer

Stack pointer

Processor status

2– 6

HARDWARE CONFIGURATION

CPU

for a register bank pointer (RP) and 8 lower bits for a condition code register

(CCR). (See Fig. 2.4.)

The 16 bits of the processor status (PS) can be divided into 8 upper bits

1514131211109876543210

PS

RP

Vacant Vacant Vacant

RP

HI NZVC

IL1, 0

CCR

Fig. 2.4 Structure of Processor Status

The RP indicates the address of the current register bank. The relationship
between the contents of the RP and the real addresses is as shown in
Figure 2.5.

Source address

R P

‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ R4 R3 R2 R1 R0 b2 b1 b0

↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Lower bits of OP code

Fig. 2.5 Rule for Translating Real Addresses at General-purpose Register Area

The CCR has bits indicating the results of operations and transfer data
contents, and bits controlling the CPU operation when an interrupt occurs.

- H-flag H-flag is set when a carry or a borrow out of bit 3 into bit 4
is generated as a result of operations; it is cleared in other
cases. This flag is used for decimal-correction instructions.

- I-flag An interrupt is enabled when this flag is 1 and is disabled
when it is 0. The I-flag is 0 at reset.

- IL1 and IL0 These bits indicate the level of the currently-enabled
interrupt. The CPU executes interrupt processing only when
an interrupt with a value smaller than the value indicated by
this bit is requested.

IL1 IL0 Interrupt level High and low

00

1

High

01
10 2
11 3

low = No interrupt

- N-flag The N-flag is set when the most significant bit is 1 as a result
of operations; it is cleared when the MSB is 0.

2– 7

HARDWARE CONFIGURATION

CPU

- Z-flag Z-flag is set when zero is the result of operations; it is
cleared in other cases.

- V-flag V -flag is set when a two’s complement overflow occurs as a
result of operations; it is reset when an overflow does not
occur.

- C-flag C-flag is set when a carry or a borrow out of bit 7 is generated
as a result of operations; it is cleared in other cases. When
the shift instruction is executed, the value of the C- flag is
shifted out.

•

General-purpose register..... 8-bit length register where data are stored.

8-bit general-purpose registers are provided in the register banks in the
memory for storing data. Eight registers are provided per bank for and up
to 16 banks can be used for MB89953 (8 banks are provided in MB89951,
32 banks are provided in MB89P955 and MB89PV950).
The register bank pointer (RP) indicates the currently-used bank.

Note: The register banks are as follows depend on RAM area.

MB89951
MB89953
MB89P955
MB89PV950

0100
0100
0100
0100

H
H
H
H

to
to
to
to

013F
017F
01FF
01FF

8 banks

H

16 banks

H

32 banks

H

32 banks

H

Address =

0100

+ 8*(RP)

H

Memory area

Fig. 2.6 Register Bank Configuration

R0
R1
R2
R3
R4
R5
R6
R7

16 banks

2– 8

HARDWARE CONFIGURATION

CPU

Clock

oscillator

2.1.4 Clock Control Block

This block controls the standby operation and software reset.

(1) Machine clock control block diagram

(a) Machine clock control section

STP SLP SPL

Pin state
Stop

CPU operation clock

Clock control

Peripheral operation clock

From time-base timer

Power-on reset

Watchdog timer reset

External reset

Software reset

HC1
HC3

Stop release signal

Selector

Option

(b) Reset control section

Reset control

(2) Register list

Address:

0008

H

8 bits

STBC

Internal reset signal

Standby control register

2– 9

HARDWARE CONFIGURATION

CPU

0008

(3) Description of registers

The detail of each register is described below.

STBCAddress:

H

(a) Standby control register (STBC)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Address:

0008

STPSLPSPLRST————

H

(W) (W) (R/W) (W )

(Initial value)

0001XXXX

[Bit 7] STP: Stop bit
This bit is used to specify switching CPU to the stop mode.

0
1

No operation
Stop mode

This bit is cleared at reset or stop cancellation.
0 is always read when this bit is read.
[Bit 6] SLP: Sleep bit

This bit is used to specify switching the CPU to the sleep mode.

0
1

No operation
Sleep mode

This bit is cleared at reset, sleep cancellation or stop cancellation.
0 is always read when this bit is read.
[Bit 5] SPL: Pin state specifying bit

This bit is used to specify the external pin state in the stop mode.

0
1

Holds pin state and level immediately before stop mode
High impedance

This bit is cleared at reset.
[Bit 4] RST: Software reset bit

This bit is used to specify the software reset.

0
1

Generates 4-cycle reset signal
No operation

1 is always read when this bit is read.

2– 10

HARDWARE CONFIGURATION

CPU

(4) Description of operation

(a) Low-power consumption mode
This chip has three operation modes shown in the table below. The sleep

mode and stop mode reduce the power consumption. The system clock
can be selected out of three according to the system condition to minimize
power consumption.

Table 2–2 Operating Mode of Low-power Consumption Modes

Each operating clock pulse

Oscillation

mode

RUN

SLEEP

STOP Stop Stops Stops External interrupt

Clock

pulse

Oscillates

CPU

2.5 MHz
Stops

(5 MHz clock)

Time-base

timer

2.5 MHz 2.5 MHz

peripheral

Each

Wake-up source

in each mode

Various interrupt

requests

• The SLEEP mode stops only the operating clock pulse of the CPU; other
operations are continued.

• The STOP mode stops the oscillation. Data can be held with the lowest
power consumption in this mode.

a. SLEEP mode

• Switching to Sleep mode

- Writing 1 at the SLP (bit 6) of the STBC register switches the mode to

SLEEP mode.

- The SLEEP mode is the mode to stop clock pulse operating the CPU;

only the CPU stops and the peripherals continue to operate.

- If an interrupt is requested when 1 is written at the SLP (bit 6),

instruction ex ecution continues without switching to the SLEEP mode.

- In the SLEEP mode, the contents of registers and RAM immediately

before entering the SLEEP mode are held.

• Canceling SLEEP mode

- The SLEEP mode is canceled by inputting the reset signal or

requesting an interrupt.

- When the reset signal is input during the SLEEP mode, the CPU is

switched to the reset state and the SLEEP mode is canceled.

- When an interrupt level higher than 11 is requested from a peripheral

during the SLEEP mode, the SLEEP mode is canceled.

- When the I flag and IL bit are enable after canceling, the CPU executes

the interrupt processing like an ordinary interrupt. When they are
disabled, the CPU starts processing the next instruction given before
entering the SLEEP mode.

2– 11

HARDWARE CONFIGURATION

CPU

b. STOP mode

• Switching to STOP mode

- Writing 1 at the STP (bit 7) of the STBC register switches the mode to

STOP mode.

- The STOP mode stops clock oscillation and the CPU and all

peripherals stop.

- The input/output pins and output pins in the STOP mode can be

controlled by the SPL (bit 5) of the STBC register so that they are held
in the state immediately before entering the STOP mode, or so that
they enter in the high-impedance state.

- If an interrupt is requested when 1 is written at the STP (bit 7),

instruction execution continues without switching to the STOP mode.

- In the STOP mode, the contents of registers and RAM immediately

before entering the STOP mode are held.

• Canceling STOP mode

- The STOP mode is canceled either by inputting the reset signal or by

requesting an interrupt.

- When the reset signal is input during the STOP mode, the CPU is

switched to the reset state and the STOP mode is canceled.

- When an interrupt higher than level 11 is requested from the external

interrupt circuit during the STOP mode, the STOP mode is canceled.

- When the I flag and IL bit are enabled after canceling, the CPU

executes the interrupt processing like an ordinary interrupt. When they
are disabled, the CPU starts processing the next instruction given
before entering the STOP mode.

- The oscillation stabilization time can be selected from the two types

in Table 2–3 as options.

- If the STOP mode is canceled by inputting the reset signal, the CPU

is switched to the oscillation stabilization state. Therefore, the reset
sequence is not executed unless the oscillation stabilization time is
elapsed. The oscillation stabilization time corresponds to the
optionally selected oscillation stabilization time of the main clock.
However, when Power-on reset unavailable is selected by the mask
option, the CPU is not switched to the oscillation stabilization state
even if the STOP mode is canceled by inputting the reset signal.

Table 2–3 Selection of Oscillation Stabilization Time

Oscillation

stabilization time

18

14

/f

CH

/f

CH

About 2
About 2

Oscillation stabilization

Remarks

time at 5 MHz

About 52.4 ms For crystal oscillator
About 3.28 ms For crystal oscillator

2– 12

HARDWARE CONFIGURATION

CPU

(b) State transition diagram

STOP

Clock stops.

(8)

(3)

Oscillation stabilization

waiting

(7)

SLEEP

Clock oscillates.

(5)

(4)

Clock oscillates.

(9)

RUN

(1) (2)

Power-on

(1) When power-on reset available selected
(2) When power-on reset unavailable selected

(3) After oscillation stabilizing
(4) Set STP bit to 1.

(5) Set SLP bit to 1.
(7) External reset when power-on reset unavailable selected

(8) External reset or interrupt when power-on reset available selected
(9) External reset or interrupt

2– 13

HARDWARE CONFIGURATION

CPU

(c) Reset
There are four types of reset depending on the source shown in Table 2–4.

Table 2–4 Sources of Reset

Reset name Description

External-pin reset
Software reset
Watchdog reset
Power-on reset

When the power-on reset or reset during the stop state is used, the
oscillation stabilization time is needed after the oscillator starts operating.
The time-base timer controls this stabilization time. Consequently, the
operation does not start immediately even after canceling the reset.

Howev er, if P ower-on reset is not selected by the mask option, no oscillation
stabilization time is required in any state after external pins have been
released from the reset.

When setting external-reset pin to Low
When writing 0 at RST (bit 4) of STBC
When watchdog timer overflows
When turning power on

Note: A longer time than the optionally-specified oscillation stabilization

time should be allowed for reset at power-on of P ower-on reset
unavailable products. In other cases, the time is based on theorist
timing given in the
characteristics.”

MB89950 SERIES DATA SHEET

“AC

2– 14

HARDWARE CONFIGURATION

CPU

Peripheral #1

F2MC-8L bus

Test

register

G L

2.1.5 Interrupt Controller

The interrupt controller for the F2MC-8L family is located between the CPU
and each peripheral. This controller receives interrupt requests from the
peripherals, assigns priority to them. When the interrupt controller transfers
the priority to the CPU, it also decides the priority of same-level interrupts.

(1) Block diagram

CPU

2

Address decoder

Level

G

Peripheral #2

•

•

Peripheral #n

G

•

•

•

G

L

•

•

•

L

Level

•

•

•

Level

•

•

•

Level

deciding

block

G

G

Same level
priority
deciding
block

Interrupt
vector
generation

•

block

•

•

(2) Register list

Interrupt controller consists of interrupt-level registers (ILR1, 2, and 3) and
interrupt-test register (ITR).

8 bits

Address:

Address:

Address:

Address:

007C

007D

007E

007F

H

H

H

H

ILR1

ILR2

ILR3

ITR

W Interrupt level register #1

W Interrupt level register #2

W Interrupt level register #3

— Interrupt test register

2– 15