Fujitsu MB89950-950A User Manual
FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
MB89950/950A Series
HARDWARE MANUAL
CM25-10146-1E
F2MC-8L
8-BIT MICROCONTROLLER
F2MC-8L
8-BIT MICROCONTROLLER
MB89950/950A Series
HARDWARE MANUAL
FUJITSU LIMITED
PREFACE
■ Objectives and Intended Reader
The MB89950/950A series has been developed as a general-purpose version of the F2MC-8L family
consisting of proprietary 8-bit, single-chip microcontrollers. The MB89950/950A series is applicable to a
wide range of applications from consumer products to industrial equipment, including portable devices.
This manual describes the functions and operation of the MB89950/950A series and is aimed at engineers
using the MB89950/950A series of microcontrollers to develop actual products. See the F
Series Programming Manual for details on the MB89950/950A instruction set.
■ Trademarks
F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
Other system and product names in this manual are trademarks of respective companies or organizations.
TM
The symbols
■ Structure of This Manual
This manual contains the following 12 chapters:
CHAPTER 1 "OVERVIEW"
and ® are sometimes omitted in this manual.
2
MC-8L MB89600
This chapter describes the main features and basic specifications of the MB89950/950A series.
CHAPTER 2 "HANDLING DEVICE"
This chapter describes points to note when using the general-purpose single-chip microcontroller.
CHAPTER 3 "CPU"
This chapter describes the functions and operation of the CPU.
CHAPTER 4 "I/O PORTS"
This chapter describes the functions and operation of the I/O ports.
CHAPTER 5 "TIMEBASE TIMER"
This chapter describes the functions and operation of the timebase timer.
CHAPTER 6 "WATCHDOG TIMER"
This chapter describes the functions and operation of the watchdog timer.
CHAPTER 7 "8-BIT PWM TIMER"
This chapter describes the functions and operation of the 8-bit PWM timer.
CHAPTER 8 "PULSE WIDTH COUNT TIMER (PWC)"
This chapter describes the functions and operation of the pulse width count timer (PWC).
CHAPTER 9 "8-BIT SERIAL I/O"
This chapter describes the functions and operation of the 8-bit serial I/O.
CHAPTER 10 "UART"
This chapter describes the functions and operation of the UART.
CHAPTER 11 "EXTERNAL INTERRUPT CIRCUIT (EDGE)"
This chapter describes the functions and operation of the external interrupt circuit.
i
CHAPTER 12 "LCD CONTROLLER/DRIVER"
This chapter describes the functions and operation of the LCD controller/driver.
APPENDIX
This appendix includes I/O maps, instruction lists, and other information.
• The contents of this document are subject to change without notice. Customers are advised to consult with
FUJITSU sales representatives before ordering.
• The information and circuit diagrams in this document are presented as examples of semiconductor device
applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume
responsibility for infringement of any patent rights or other rights of third parties arising from the use of this
information or circuit diagrams.
• The products described in this document are designed, developed and manufactured as contemplated for general
use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but
are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers
that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to
death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control
in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy,
fire protection, and prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on export
under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will
be required for export of those products from Japan.
©2002 FUJITSU LIMITED Printed in Japan
ii
READING THIS MANUAL
■ Notations of the Register Name and Pin Name
Example for description of register name and bit name
●
Notations of a double-purpose pin
●
P22/SCK pin
Some pins can be used by switching their functions using, for example, settings by a program. Each
double-purpose pin is represented by separating the name of each function using "/".
iii
■
Documents and Development Tools Required for Development
Items necessary for the development of this product are as follows.
To obtain the necessary documents and development tools, contact a company sales
representative.
Manuals required for development
●
[Check field]
2
MC-8L MB89950/950A series data sheet (provides a table of electrical characteristics and vari-
F
ous examples of this product)
2
MC-8L Programming Manual (manual including instructions for the F2MC-8L family)
F
*
2
MC Family Softune C Compiler Manual (required only if C language is used for develop-
FR/F
ment) (manual describing how to develop and activate programs in the C language)
*
2
FR/F
MC Family Softune Assembler Manual for V3 (manual describing program development
using the assembler language)
*
2
FR/F
MC Family Softune Linkage Kit Manual for V3 (manual describing functions and opera-
tions of the assembler, linker, and library manager
Manuals with the * mark are attached to each product.
Other manuals, such as those for development, are attached to respective products.
Software required for development
[Check field]
Softune V3 Workbench
Softune V3 for personal ICE (required only if the evaluation is performed for the personal-ICE)
Softune V3 for compact ICE (required only if the evaluation is performed for the compact-ICE)
The type of software product is dependent on the OS to be used.
For details, see the F
2
MC Development Tool Catalog or Product Guide.
iv
❍
What is needed for evaluation on the one-time PROM microcomputer (if the programming
operation is performed at your side)
[Check field]
Development tools
●
[Check field]
MB89P955
EPROM programmer
(Programmer available for the MBM27C1001)
Package conversion adapter
ROM-64QF2-28DP-8L3
MB89PV950 (piggyback/evaluation device)
Development tool
References
●
Main unit Pod Probe
MB2141A + MB2144-505 MB2144-203
To use a the other development environment, contact respective makers.
2
•"F
MC Development Tool Catalog"
• "Microcomputer Product Guide"
v
vi
CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 MB89950/950A Series Features ........................................................................................................... 2
1.2 MB89950/950A Series Product Range ................................................................................................. 4
1.3 Differences among Products ................................................................................................................ 6
1.4 Block Diagram of MB89950/950A Series ............................................................................................ 7
1.5 Pin Assignment ..................................................................................................................................... 8
1.6 Package Dimensions .......................................................................................................................... 10
1.7 I/O Pins and Pin Functions ................................................................................................................. 12
CHAPTER 2 HANDLING DEVICES ................................................................................ 17
2.1 Notes on Handling Devices ................................................................................................................ 18
CHAPTER 3 CPU ............................................................................................................ 21
3.1 Memory Space .................................................................................................................................... 22
3.1.1 Special Areas ................................................................................................................................. 24
3.1.2 Storing 16-bit Data in Memory ....................................................................................................... 26
3.2 Dedicated Registers ........................................................................................................................... 27
3.2.1 Condition Code Register (CCR) .................................................................................................... 29
3.2.2 Register Bank Pointer (RP) ........................................................................................................... 32
3.3 General-purpose Registers ................................................................................................................. 33
3.4 Interrupts ............................................................................................................................................. 35
3.4.1 Interrupt Level Setting Registers (ILR1, ILR2, ILR3) ..................................................................... 36
3.4.2 Interrupt Processing ....................................................................................................................... 37
3.4.3 Multiple Interrupts .......................................................................................................................... 39
3.4.4 Interrupt Processing Time .............................................................................................................. 40
3.4.5 Stack Operation during Interrupt Processing ................................................................................. 41
3.4.6 Stack Area for Interrupt Processing ............................................................................................... 42
3.5 Resets ................................................................................................................................................. 43
3.5.1 External Reset Pin ......................................................................................................................... 45
3.5.2 Reset Operation ............................................................................................................................. 46
3.5.3 Pin States during Reset ................................................................................................................. 48
3.6 Clocks ................................................................................................................................................. 49
3.6.1 Clock Generator ............................................................................................................................. 51
3.6.2 Clock Controller ............................................................................................................................. 53
3.6.3 Oscillation Stabilization Delay Time ............................................................................................... 55
3.7 Standby Mode (Low-power Consumption) ......................................................................................... 57
3.7.1 Operating States in Standby Mode ................................................................................................ 58
3.7.2 Sleep Mode ................................................................................................................................... 59
3.7.3 Stop Mode ..................................................................................................................................... 60
3.7.4 Standby Control Register (STBC) .................................................................................................. 61
3.7.5 State Transition Diagram ............................................................................................................... 63
3.7.6 Notes on Using Standby Mode ...................................................................................................... 65
3.8 Memory Access Mode ........................................................................................................................ 67
vii
CHAPTER 4 I/O PORTS .................................................................................................. 69
4.1 Overview of I/O Ports .......................................................................................................................... 70
4.2 Port 0 ................................................................................................................................................. 72
4.2.1 Port 0 Data Register (PDR0) ......................................................................................................... 74
4.2.2 Operation of Port 0 ........................................................................................................................ 75
4.3 Port 1 ................................................................................................................................................. 77
4.3.1 Port 1 Data Register (PDR1) ......................................................................................................... 79
4.3.2 Operation of Port 1 ........................................................................................................................ 80
4.4 Port 2 ................................................................................................................................................. 82
4.4.1 Port 2 Data Register (PDR2) ......................................................................................................... 84
4.4.2 Operation of Port 2 ........................................................................................................................ 85
4.5 Port 3 ................................................................................................................................................. 86
4.5.1 Port 3 Data Register (PDR3) ......................................................................................................... 89
4.5.2 Operation of Port 3 ........................................................................................................................ 90
4.6 Port 4 .................................................................................................................................................. 92
4.6.1 Port 4 Registers (PDR4, DDR4) .................................................................................................... 94
4.6.2 Operation of Port 4 ....................................................................................................................... 96
4.7 Program Example for I/O Ports ........................................................................................................... 98
CHAPTER 5 TIMEBASE TIMER ..................................................................................... 99
5.1 Overview of Timebase Timer ........................................................................................................... 100
5.2 Block Diagram of Timebase Timer ................................................................................................... 102
5.3 Timebase Timer Control Register (TBTC) ........................................................................................ 104
5.4 Timebase Timer Interrupt ................................................................................................................. 106
5.5 Operation of Timebase Timer ........................................................................................................... 107
5.6 Notes on Using Timebase Timer ...................................................................................................... 109
5.7 Program Example for Timebase Timer ............................................................................................. 110
CHAPTER 6 WATCHDOG TIMER ................................................................................ 111
6.1 Overview of Watchdog Timer ........................................................................................................... 112
6.2 Block Diagram of Watchdog Timer ................................................................................................... 113
6.3 Watchdog Timer Control Register (WDTC) ...................................................................................... 115
6.4 Operation of Watchdog Timer ........................................................................................................... 116
6.5 Notes on Using Watchdog Timer ...................................................................................................... 118
6.6 Program Example for Watchdog Timer ............................................................................................ 119
CHAPTER 7 8-BIT PWM TIMER ................................................................................... 121
7.1 Overview of 8-bit PWM Timer ........................................................................................................... 122
7.2 Block Diagram of 8-bit PWM Timer .................................................................................................. 124
7.3 Structure of 8-bit PWM Timer .......................................................................................................... 126
7.3.1 PWM Control Register (CNTR) .................................................................................................... 128
7.3.2 PWM Compare Register (COMR) ............................................................................................... 130
7.4 8-bit PWM Timer Interrupts ............................................................................................................... 131
7.5 Operation of Interval Timer Function ................................................................................................ 132
7.6 Operation of PWM Timer Function ................................................................................................... 134
7.7 States in Each Mode during 8-bit PWM Timer Operation ................................................................. 135
7.8 Notes on Using 8-bit PWM Timer ..................................................................................................... 137
viii
7.9 Program Example for 8-bit PWM Timer ............................................................................................ 138
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) ................................................... 141
8.1 Overview of Pulse Width Count Timer .............................................................................................. 142
8.2 Block Diagram of Pulse Width Count Timer ..................................................................................... 144
8.3 Structure of Pulse Width Count Timer .............................................................................................. 146
8.3.1 PWC Pulse Width Control Register 1 (PCR1) ............................................................................. 148
8.3.2 PWC Pulse Width Control Register 2 (PCR2) ............................................................................. 150
8.3.3 PWC Reload Buffer Register (RLBR) .......................................................................................... 152
8.3.4 PWC Noise Filter Control Register (NCCR) ................................................................................ 154
8.4 Pulse Width Count Timer Interrupts .................................................................................................. 155
8.5 Operation of Interval Timer Function ................................................................................................ 156
8.6 Operation of Pulse Width Measurement Function ............................................................................ 159
8.7 Operation of Noise Filter Circuit ........................................................................................................ 162
8.8 States in Each Mode during Pulse Width Count Timer Operation .................................................... 163
8.9 Notes on Using Pulse Width Count Timer ........................................................................................ 164
8.10 Program Example for Timer Function of Pulse Width Count Timer .................................................. 165
CHAPTER 9 8-BIT SERIAL I/O ..................................................................................... 169
9.1 Overview of 8-bit Serial I/O ............................................................................................................... 170
9.2 Block Diagram of 8-bit Serial I/O ...................................................................................................... 171
9.3 Structure of 8-bit Serial I/O ............................................................................................................... 173
9.3.1 Serial Mode Register (SMR) ........................................................................................................ 176
9.3.2 Serial Data Register (SDR) .......................................................................................................... 179
9.4 8-bit Serial I/O Interrupts ................................................................................................................... 180
9.5 Operation of Serial Output ............................................................................................................... 181
9.6 Operation of Serial Input ................................................................................................................... 183
9.7 States in Each Mode during 8-bit Serial I/O Operation ..................................................................... 185
9.8 Notes on Using 8-bit Serial I/O ......................................................................................................... 188
9.9 Connection Example for 8-bit Serial I/O ........................................................................................... 189
9.10 Program Example for 8-bit Serial I/O ................................................................................................ 190
CHAPTER 10 UART ........................................................................................................ 193
10.1 Overview of UART ............................................................................................................................ 194
10.2 Structure of UART ............................................................................................................................ 199
10.3 UART Pins ........................................................................................................................................ 202
10.4 UART Registers ................................................................................................................................ 204
10.4.1 Serial Mode Control Register 1 (SMC1) ...................................................................................... 205
10.4.2 Serial Rate Control Register (SRC) ............................................................................................. 207
10.4.3 Serial Status and Data Register (SSD) ........................................................................................ 209
10.4.4 Serial Input Data Register (SIDR) ................................................................................................ 211
10.4.5 Serial Output Data Register (SODR) ........................................................................................... 212
10.4.6 Serial Mode Control Register 2 (SMC2) ...................................................................................... 213
10.5 UART Interrupts ................................................................................................................................ 215
10.6 Operation of UART ........................................................................................................................... 216
10.7 Operation of Mode 0, 1, 3 ................................................................................................................ 217
10.8 Program Example for UART ............................................................................................................. 220
ix
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) ............................................ 223
11.1 Overview of the External Interrupt Circuit ........................................................................................ 224
11.2 Block Diagram of the External Interrupt Circuit ................................................................................. 225
11.3 Structure of the External Interrupt Circuit ......................................................................................... 226
11.3.1 External Interrupt Control Register (EIC) ..................................................................................... 228
11.4 External Interrupt Circuit Interrupts ................................................................................................... 230
11.5 Operation of the External Interrupt Circuit ........................................................................................ 231
11.6 Program Example for the External Interrupt Circuit .......................................................................... 232
CHAPTER 12 LCD CONTROLLER/DRIVER .................................................................. 233
12.1 Overview of LCD Controller/Driver .................................................................................................. 234
12.2 Block Diagram of LCD Controller/Driver .......................................................................................... 235
12.2.1 LCD Controller/Driver Internal Voltage Divider ............................................................................ 237
12.2.2 LCD Controller/Driver External Voltage Divider ........................................................................... 239
12.3 Structure of LCD Controller/Driver .................................................................................................... 241
12.3.1 LCD Control Register (LCDR) ..................................................................................................... 244
12.3.2 Segment Output Select Register (SEGR) .................................................................................... 246
12.3.3 Display RAM ................................................................................................................................ 248
12.4 Operation of LCD Controller/Driver .................................................................................................. 250
12.4.1 Output Waveforms during LCD Controller/Driver Operation (1/2 Duty Ratio) ............................. 251
12.4.2 Output Waveforms during LCD Controller/Driver Operation (1/3 Duty Ratio) ............................. 254
12.4.3 Output Waveforms during LCD Controller/Driver Operation (1/4 Duty Ratio) ............................. 257
12.5 Program Example for LCD Controller/Driver .................................................................................... 260
APPENDIX ......................................................................................................................... 263
APPENDIX A I/O Map ................................................................................................................................ 264
APPENDIX B Overview of Instructions ....................................................................................................... 266
B.1 Overview of F
B.2 Addressing ..................................................................................................................................... 269
B.3 Special Instructions ........................................................................................................................ 274
B.4 Bit Manipulation Instructions (SETB, CLRB) .................................................................................. 278
B.5 F
B.6 Instruction map ............................................................................................................................... 286
APPENDIX C Mask Options ....................................................................................................................... 287
APPENDIX D Programming Specifications for One-Time PROM And EPROM Microcontroller ................ 289
D.1 Programming Specifications for One-time PROM and EPROM Microcontrollers .......................... 290
D.2 Programming Yield and Erasure .................................................................................................... 293
D.3 Programming to the EPROM with Piggyback/Evaluation Device ................................................... 294
APPENDIX E MB89950/950A Series Pin States ........................................................................................ 295
2
MC-8L Instructions ..................................................................................................................... 279
2
MC-8L Instructions ................................................................................................. 267
INDEX................................................................................................................................... 297
x
CHAPTER 1
OVERVIEW
This chapter describes the main features and basic
specifications of the MB89950/950A series.
1.1 "MB89950/950A Series Features"
1.2 "MB89950/950A Series Product Range"
1.3 "Differences among Products"
1.4 "Block Diagram of MB89950/950A Series"
1.5 "Pin Assignment"
1.6 "Package Dimensions"
1.7 "I/O Pins and Pin Functions"
1
CHAPTER 1 OVERVIEW
1.1 MB89950/950A Series Features
The MB89950/950A series is a line of the general-purpose, single-chip microcontrollers.
In addition to a compact instruction set, the microcontrollers contain a variety of
peripheral functions such as an LCD controller/driver, UART, a serial I/O, PWC timer,
PWM timer and external interrupts.
■ MB89950/950A series features
Various package options
●
• QFP packages (0.65 mm lead pitch) for MB89951A/MB89953A/MB89P955 only
High speed processing at low voltage
●
Minimum execution time: 0.8 µs/5 MHz
F2MC-8L family CPU core
●
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Test and branch instructions
• Bit manipulation instructions, etc.
Single-clock control system
●
• Main clock: max. 5 MHz
Four types of timer
●
• 21-bit timebase timer
• Watchdog timer
• 8-bit PWM timer (also can be used as an interval timer)
• 8-bit PWC timer
Two types of serial interface
●
• UART
- 5, 7, 8 bits transfer data length
• Serial I/O
LCD controller/driver
●
• 42 segments x 4 commons (max. 168 pixels)
• Built-in LCD voltage divider
2
External interrupts (2 channels)
●
• Two channels are independent and capable of wake-up from low-power consumption mode (with an
edge detection function).
Standby mode (low-power mode)
●
• Stop mode (oscillation stops so as to minimize the current consumption).
• Sleep mode (CPU stops so as to reduce the current consumption to approx. 1/3 of normal).
I/O ports: max. 33 channels
●
• General-purpose I/O ports (N-ch open-drain): 22 (Also serve as segment pins)
• General-purpose I/O ports (N-ch open-drain): 4 (2 also serve as LCD bias pins)
• General-purpose I/O ports (CMOS): 7 (6 also serve as peripheral pins)
CHAPTER 1 OVERVIEW
3
CHAPTER 1 OVERVIEW
1.2 MB89950/950A Series Product Range
The MB89950/950A series contains 4 different models. Table 1.2-1 "MB89950/950A
series product line-up" lists the product range and Table 1.2-2 "Common specifications
for the MB89950/950A series" lists the common specifications.
■ MB89950/950A series product range
Table 1.2-1 MB89950/950A series product line-up
Part number
MB89951A MB89953A MB89P955
Classification Mask ROM OTP Piggy-back
ROM size 4K x 8 bits
(internal mask ROM)
RAM size 128 x 8 bits 256 x 8 bits 512 x 8 bits 1024 x 8 bits
Low-power consumption
(Standby mode)
Process CMOS
Operating voltage
*1: Varies with conditions such as operating frequencies.
*2: Use MBM27C256A as the external ROM
*1
2.7 V to 5.5 V 2.7 V to 6.0 V
8K x 8 bits
(internal mask ROM)
Sleep mode and stop mode
16K x 8 bits
(internal OTP)
MB89PV950
32K x 8 bits
(external ROM)
*2
4
Table 1.2-2 Common specifications for the MB89950/950A series
Parameter Specification
CPU functions Number of instructions: 136
Instruction bit length: 8 bits
Instruction length: 1 to 3 bytes
Data bit length: 1, 8, 16 bits
Minimum execution time: 0.80 µs to 12.8 µs at 5 MHz
Interrupt processing time: 7.26 µs to 115.2 µs at 5 MHz
CHAPTER 1 OVERVIEW
Peripheral
functions
Ports
20-bit timebase
timer
Watchdog timer Reset generate cycle: min. 419.4 ms at 5 MHz
8-bit PWM
timer
PWC timer 8-bit interval timer operation
UART Transfer data length: 5, 7, 8 bits
8-bit serial I/O 8 bits
General-purpose I/O ports (N-ch open-drain): 22 (also serve as LCD segment pins)
General-purpose I/O ports (N-ch open-drain): 4 (two also serve as LCD bias pins)
General-purpose I/O ports (CMOS): 7 (6 ports serve as peripherals)
Total: 33 (max.)
20 bits
Interrupt cycle: 6.55 ms, 26.21 ms, 104.86 ms, 419.43 ms at 5 MHz
8-bit reload timer operation (square wave output; operating frequency: 0.8 µs, 12.8 µs,
51.2 µs at 5 MHz)
8-bit resolution PWM operation (conversion frequency: 204.8 µs - 3.36 s)
Event count function
8-bit pulse width measurement (continuous measurement, High-width, Low-width measurement and
One-cycle measurement)
Operation clock (0.8 µs, 3.2 µs, 25.6 µs at 5 MHz)
Internal baud rate generator (Max. 78125 bps at 5 MHz)
LSB first/MSB first selectability
One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 1.6
µs, 6.4 µs, 25.6 µs at 5 MHz)
*1
LCD controller/
driver
External
interrupt
Note:
Unless otherwise specified, values given for clock cycle, conversion times, etc. are for 5 MHz operation.
*1: Segment pins can be selected by mask option.
Common output: 4 (max.)
Segment output: 42 (max.)
Operation mode: 1/2 bias and 1/2 duty, 1/3 bias and 1/3 duty, 1/3 bias and 1/4 duty
LCD display RAM size: 21 bytes (42 x 4 bits, max. 168 pixels)
Dividing voltage for LCD driving: built-in/external voltage divider selectable
2 independent channels (interrupt vector, request flag, request output enable)
Edge selectability (rising/falling)
5
CHAPTER 1 OVERVIEW
1.3 Differences among Products
This section describes the differences among the 4 products in the MB89950/950A
series and lists points to note in product selection.
■ Differences among products and points to note for product selection
Table 1.3-1 Package and corresponding products
Package Part number
MB89951A MB89953A MB89P955 MB89PV950
FPT-64P-M09
(LQFP-64, 0.65 mm pitch)
MQP-64C-P01
(MQFP-64, 1 mm pitch)
: Available
X: Not available
Current consumption
●
• In the case of the MB89PV950, add the current consumed by the EPROM, which is connected to the top
socket.
• When operated at low speed, the product with a one-time PROM (OTPROM) or an EPROM will
consume more current than the product with mask ROM. However the current consumption in sleep/
stop mode, is the same.
For more information about the package, see Section 1.6 "Package Dimensions".
• For more information about the current consumption, see the electrical characteristics in the Data Sheet.
Mask options
●
X
XXX
Functions that can be selected as options and how to designate these options vary from product to product.
Before using, check Appendix C, "Mask Options".
Take particular care on the following points:
• In the MB89951A and MB89953A, the number of common and segment outputs is specified by Data
Release Form.
• Options are fixed on the MB89PV950. (See Appendix C, "Mask Options")
6
CHAPTER 1 OVERVIEW
1.4 Block Diagram of MB89950/950A Series
Figure 1.4-1 "MB89950/950A series overall block diagram" shows the block diagram of
the MB89950/950A series.
■ MB89950/950A series block diagram
Figure 1.4-1 MB89950/950A series overall block diagram
X0
X1
RST
Other pins
MODA
V
, VSS
CC
Clock control circuit
(Watchdog timer)
Timebase timer
R A M
2
MC-8L
F
CPU
R O M
Main oscillator
circuit
Reset circuit
Internal bus
8-bit PWM timer
External interrupt
8-bit
pulse width
count timer
8-bit serial I/O
UART
CMOS I/O port
N-ch open-drain I/O port
LCD controller/driver
N-ch open-drain I/O port
Noise
filter
Port 4
Port 0/1/2
Port 3
P41/PWM
P40
P42/PWC/
INT1
P45/SCK
P44/SO
P43/SI
P46/INT0
8
P00/SEG20 to
P07/SEG27
8
P10/SEG28 to
P17/SEG35
6
P20/SEG36 to
P25/SEG41
20
SEG0 to
SEG19
4
COM0 to
COM3
V3
P33/V2
2
P32/V1
2
P30, P31
7
CHAPTER 1 OVERVIEW
1.5 Pin Assignment
Figure 1.5-1 "FPT-64P-M09 pin assignment" and Figure 1.5-2 "MQP-64C-P01 pin
assignment" show the pin assignment diagrams for the MB89950/950A series.
■ FPT-64P-M09 pin assignment
Figure 1.5-1 FPT-64P-M09 pin assignment
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
VCCSEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG4
SEG3
SEG2
SEG1
SEG0
COM3
COM2
COM1
COM0
V3
P33/V2
P32/V1
P31
P30
P40
P41/PWM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
646362616059585756555453525150
TOP VIEW
QFP-64
171819202122232425262728293031
X1
SS
V
P45/SCK
P46/INT0
P25/SEG41
P24/SEG40
P23/SEG39
P22/SEG38
P21/SEG37
MODA
P44/SO
X0
RST
P43/SI
P42/INT1/PWC
32
P20/SEG36
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P00/SEG20
P01/SEG21
P02/SEG22
P03/SEG23
P04/SEG24
P05/SEG25
P06/SEG26
P07/SEG27
P10/SEG28
P11/SEG29
P12/SEG30
P13/SEG31
P14/SEG32
P15/SEG33
P16/SEG34
P17/SEG35
8
■ MQP-64C-P01 pin assignment
Figure 1.5-2 MQP-64C-P01 pin assignment
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
Vcc
SEG13
SEG14
SEG15
SEG16
64636261605958575655545352
CHAPTER 1 OVERVIEW
SEG17
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM3
COM2
COM1
COM0
V3
V2/P33
V1/P32
P31
P30
P40
P41/PWM
P42/PWC/INT1
P43/SI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
84838281807978
85
86
87
88
89
90
91
92
93
94959665666768
(TOP VIEW)
20212223242526272829303132
X0
X1
RST
P44/SO
Vss
MODA
Pin assignment on package top (MB89PV950 only)
51
50
49
48
77
76
75
74
73
72
71
70
69
P45/SCK
P46/INT0
P25/SEG41
P24/SEG40
P23/SEG39
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P22/SEG38
P21/SEG37
SEG18
SEG19
P00/SEG20
P01/SEG21
P02/SEG22
P03/SEG23
P04/SEG24
P05/SEG25
P06/SEG26
P07/SEG27
P10/SEG28
P11/SEG29
P12/SEG30
P13/SEG31
P14/SEG32
P15/SEG33
P16/SEG34
P17/SEG35
P20/SEG36
Pin no. Pin name Pin no. Pin nam e Pi n no. Pin nam e Pin no. Pi n name
65 N.C. 73 A2 81 N.C. 89 OE
66 Vpp 74 A1 82 O4 90 N.C.
67 A127 5 A0 83 O5 91A 11
68 A7 76 N.C. 84 O6 92 A9
69 A6 77 O1 85 O7 93 A8
70 A5 78 O2 86 O8 94 A13
71 A4 79 O3 87 CE
95 A14
72 A3 80 Vss 88 A10 96 Vcc
N.C.: Internally connected. Do not use.
9
CHAPTER 1 OVERVIEW
1.6 Package Dimensions
Two types of packages are available for MB89950/950A series. Figure 1.6-1 "FPT-64PM09 package dimensions" and Figure 1.6-2 "MQP-64C-P01 package dimensions" show
the package dimensions.
■ FPT-64P-M09 package dimensions
Figure 1.6-1 FPT-64P-M09 package dimensions
64-pin plastic LQFP Lead pitch 0.65 mm
64-pin plastic LQFP
(FPT-64P-M09)
49
(FPT-64P-M09)
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
INDEX
Package width
package length
12
12 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.70 mm MAX
Note: Pins width and pins thickness include plating thickness.
0.145±0.055
3348
32
(.0057±.0022)
0.10(.004)
0.10(.004)
Details of "A" part
+0.20
1.50
+.008
.059
0.25(.010)
(Mounting height)
10
64
116
0.65(.026)
C
2001 FUJITSU LIMITED F64018S-c-2-4
0.32±0.05
(.013±.002)
17
0.13(.005)
0.50±0.20
"A"
M
(.020±.008)
0.60±0.15
(.024±.006)
Dimensions in mm (inches).
0.10±0.10
(.004±.004)
(Stand off)
■ MQP-64C-P01 package dimensions
Figure 1.6-2 MQP-64C-P01 package dimensions
64-pin ceramic MQFP Lead pitch 1.00 mm
CHAPTER 1 OVERVIEW
Lead shape Straight
(MQP-64C-P01)
64-pin ceramic MQFP
(MQP-64C-P01)
INDEX AREA
1.27±0.13
(.050±.005)
22.30±0.33
(.878±.013)
24.70(.972)
TYP
0.30(.012)
TYP
18.70(.736)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.02(.473)
10.16(.400)
TYP
Mounted package
18.12±0.20
(.713±.008)
TYP
14.22(.560)
TYP
Motherboard
material
material
+0.40
1.20
+.016
.047
12.00(.472)TYP
1.00±0.25
(.039±.010)
Ceramic
Plastic
18.00(.709)
1.00±0.25
(.039±.010)
TYP
1.27±0.13
(.050±.005)
0.50(.020)TYP
C
1994 FUJITSU LIMITED M64004SC-1-3
0.30(.012)TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
10.82(.426)
0.15±0.05
(.006±.002)
MAX
0.40±0.10
(.016±.004)
0.40±0.10
(.016±.004)
Dimensions in mm (inches).
1.20
.047
+0.40
+.016
11
CHAPTER 1 OVERVIEW
1.7 I/O Pins and Pin Functions
Table 1.7-1 "Pin description" and Table 1.7-2 "Pin description for external ROM (for
MB89PV950 only)" list the MB89950/950A series I/O pins and their functions. Table 1.7-3
"I/O circuit type" lists the I/O circuit types.
The letter in the "I/O circuit type" column in Table 1.7-1 "Pin description" refer to the
letter in the "Type" column Table 1.7-3 "I/O circuit type".
■ I/O pins and pin functions
Table 1.7-1 Pin description (1/2)
Pin no.
*1
LQFP
22 23 X0
23 24 X1
21 22 MODA B
19 20 RST C
48 to 41 49 to 42
40 to 33 41 to 34
MQFP
*2
Pin name
P00/SEG20
to
P07/SEG27
P10/SEG28
to
P17/SEG35
I/O
circuit
type
A Clock oscillator pins.
Operation mode selection pin.
This pin is connected directly to V
Reset I/O pin.
This pin consists of an N-ch open-drain output with a pull-up
resistor and hysteresis input. A "LOW" level is output from this
pin. A "LOW" voltage on this port generates a RESET condition.
N-channel open-drain type general-purpose I/O ports.
D
D
Also serve as LCD controller/driver segment outputs.
Switching between port output and segment driver output is
performed by the mask option.
N-channel open-drain type general-purpose I/O ports.
Also serve as LCD controller/driver segment outputs.
Switching between port output and segment driver output is
performed by the mask option.
Function
SS
with pull-down resistor.
P20/SEG36
32 to 27 33 to 28
14 to 13 15 to 14 P30 to P31 F N-channel open-drain type general-purpose I/O ports.
12 to 11 13 to 12
15 16 P40 E
12
to
P25/SEG41
P32/V1 to
P33/V2
D
H
N-channel open-drain type general-purpose I/O ports.
Also serve as LCD controller/driver segment outputs.
Switching between port output and segment driver output is
performed by the mask option.
N-channel open-drain type general-purpose I/O ports.
Also serve as LCD controller/driver power supply.
General-purpose I/O port.
A pull-up resistor option is provided.
Table 1.7-1 Pin description (2/2)
CHAPTER 1 OVERVIEW
Pin no.
Pin name
LQFP
*1
MQFP
*2
16 17 P41/PWM E
17 18 P42/PWC/INT1 E
18 19 P43/SI E
20 21 P44/SO E
25 26 P45/SCK E
I/O
circuit
type
Function
General-purpose I/O port.
Also serves as PWM timer toggle output (PWM).
A pull-up resistor option is provided.
General-purpose I/O port.
Also serves as pulse-width count timer input (PWC) and external
interrupt input (INT1).
The PWC and INT1 inputs are hysteresis type.
A pull-up resistor option is provided.
General-purpose I/O port.
Also serves as serial I/O and UART data input (SI).
The SI input is hysteresis type.
A pull-up resistor option is provided.
General-purpose I/O port.
Also serves as serial I/O and UART data output (SO).
A pull-up resistor option is provided.
General-purpose I/O port.
Also serves as serial I/O and UART clock input/output (SCK).
The SCK input is hysteresis type.
A pull-up resistor option is provided.
General-purpose input port.
26 27 P46/INT0 E
Also serves as external interrupt input (INT0).
The input is hysteresis type.
A pull-up resistor option is provided.
5 to 1
64 to 57
55 to 49
6 to 1
64 to 58
56 to 50
For LCD segment driver outputs.
SEG0 to SEG19 G
9 to 6 10 to 7 COM0 to COM3 G For LCD common driver outputs.
10 11 V3 - For LCD driver power supply.
56 57
24 25
V
CC
V
SS
Power pin.
-
Power (GND) pin.
-
*1: FPT-64P-M09
*2: MQP-64C-P01
13
CHAPTER 1 OVERVIEW
Table 1.7-2 Pin description for external ROM (for MB89PV950 only)
Pin no. Pin name I/O Function
66
67 A12
68 A7
69 A6
70 A5
71 A4
72 A3
73 A2
74 A1
75 A0
77 O1
79 O3
80
82 O4
83 O5
84 O6
85 O7
86 O8
87 CE O
88 A10 O For address output.
89 OE O
91 A11
93 A8
94 A13
95 A14
96
65
76
81
90
V
PP
V
SS
V
CC
N.C. --
O For high-level output.
O For address output.
I For data input.78 O2
O For power supply (GND).
I For data input.
For ROM chip enable.
The High level is output in standby mode.
For ROM output enable.
The Low level is always output.
O For address output.92 A9
O For address output.
O For EPROM power supply.
For internal connection.
Keep open.
14
Table 1.7-3 I/O circuit type (1/2)
Type Circuit Remarks
A • Crystal oscillator
X1
N-ch
X0
S
tandby control signal
P-ch
P-ch
N-ch
N-ch
• Feedback resistor: About 1 MΩ (5 V)
B • CMOS input
• Pull-down resistor (N-ch): About 50 kΩ (5 V)
R
CHAPTER 1 OVERVIEW
C • Output pull-up resistor (P-ch): About 50 kΩ (5 V)
• Hysteresis input
R
P-ch
N-ch
D • N-ch open-drain output
• CMOS input
P-ch
N-ch
P-ch
N-ch
N-ch
• The segment driver output is optional.
15
CHAPTER 1 OVERVIEW
Table 1.7-3 I/O circuit type (2/2)
Type Circuit Remarks
E • CMOS output
• CMOS input
R
P-ch
P-ch
N-ch
• Hysteresis input (peripheral input)
• The pull-up resistor is optional: About 50 kΩ (5 V)
F • N-ch open-drain output
• CMOS input
N-ch
G • LCD controller/driver common/segment driver
output
P-ch
N-ch
P-ch
N-ch
H • N-ch open-drain output
• CMOS input
P-ch
N-ch
N-ch
16
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