FUJITSU MB89643, MB89645, MB89646, MB89647, MB89P647 DATA SHEET

查询MB89643供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

8-bit Proprietary Microcontroller

CMOS

F2MC-8L MB89640 Series

MB89643/645/646/647/P647/PV640

DESCRIPTION

■

The MB89640 series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit, single-chip microcontrollers.

DS07-12505-3E

In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as
dual-clock control system, five operating speed control stages, timers, a PWM timer, serial interface, an A/D
converter, a D/A converter, an external interrupt, and a watch prescaler.

2

MC stands for FUJITSU Flexible Microcontroller.

*: F

FEATURES

■

•F2MC-8L family CPU core
Multiplication and division instructions

Instruction set optimized for controllers

PACKAGE

■

80-pin Plastic QFP

16-bit arithmetic operations
Test and branch instructions
Bit manipulation instructions, etc.

80-pin Plastic QFP

(Continued)

80-pin Ceramic MQFP

(FPT-80P-M11) (FPT-80P-M06) (MQP-80C-P01)

MB89640 Series

(Continued)

• Six types of timers

8-bit PWM timer: 2 channels (also usable reload timer)
8-bit pulse width counter (continuous measurement capable and applicable to remote control)
16-bit timer/counter
21-bit time-base counter
15-bit watch prescaler

• Two 8-bit serial I/O

Swichable transfer direction allows communication with various equipment.

• 8-bit A/D converter: 8 channels

Sense mode function enabling comparison at 12 instructions
Activation by external input capable

• External interrupt 1, external interrupt 2: 9 channels

• 8-bit D/A converter: 2 channels

8-bit R-2R type

• Low-power consumption modes (stop mode, sleep mode, watch mode, subclock mode)

• Bus interface functions

Including hold and ready functions

2

MB89640 Series

PRODUCT LINEUP

■

Part number

Parameter

Classification

ROM size 8 K × 8 bits

RAM size 256 × 8 bits 512 × 8 bits 768 × 8 bits 1 K × 8 bits
CPU functions Number of instructions: 136

MB89643 MB89645 MB89646 MB89647 MB89P647 MB89PV640

(internal mask
ROM)

Mass production products

(mask ROM products)

16 K × 8 bits
(internal mask
ROM)

24 K × 8 bits
(internal mask
ROM)

32 K × 8 bits
(internal mask
ROM)

One-time

PROM product

32 K × 8 bits
(internal PROM,
programming with
general-purpose
programmer)

Instruction bit length: 8 bits
Instruction length: 1 to 3 bytes
Data bit length: 1, 8, 16 bits
Minimum execution time: 0.4 µs/10 MHz to 6.4 µs/10 MHz,

or 61.0 µs/32.768 kHz

Interrupt processing time: 3.6 µs/10 MHz to 57.6 µs/10 MHz,

or 562.5 µs/32.768 kHz

Piggyback/
evaluation product
for evaluation and
development

32 K × 8 bits

(external ROM)

Ports Input ports (CMOS): 9 (All also serve as a external interrupt.)

Output ports (CMOS): 8 (All also serve as a bus control.)
I/O ports (CMOS): 24 (8 ports also serve as peripherals,

16 ports also serve as a bus control.)
I/O ports (N-ch open-drain): 8 (All also serve as peripherals.)
Output ports (N-ch open-drain): 16 (8 ports also serve as peripherals.)
Total: 65

Clock timer 21 bits × 1 (in main clock mode), 15 bits × 1 (at 32.768 kHz)
8-bit PWM

timer

8-bit reload timer operation × 2 channels

7/8-bit resolution PWM operation × 2 channels

8-bit PPG operation × 1 channel

8-bit pulse
width counter

8-bit timer operation (overflow output capable)

8-bit reload timer operation (toggled output capable)

8-bit pulse width measurement operation

(Continuous measurement capable, measurement of “H” width/“L” width/from ↑ to ↓/from ↓ to ↑ capable)

16-bit timer/
counter

16-bit timer operation

16-bit event counter operation

8-bit serial I/O 8 bits × 2 channels

LSB first/MSB first selectability

One clock selectable from four transfer clocks

(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)

8-bit A/D
converter

A/D conversion mode (conversion time: 44 instructions)

8-bit resolution × 8 channels

Sense mode (conversion time: 12 instructions)

Continuous activation by an external activation or an internal timer capable

Reference voltage input

(Continued)

3

MB89640 Series

(Continued)

Part number

Parameter

MB89643 MB89645 MB89646 MB89647 MB89P647 MB89PV640

8-bit D/A
converter

External interrupt 1,
External interrupt 2

Standby modes Watch mode, subclock mode, sleep mode, and stop mode
Process CMOS
Operating

voltage*
EPROM for use

*1: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

■

1

PACKAGE AND CORRESPONDING PRODUCTS

MB89643

Package

FPT-80P-M11 ×
FPT-80P-M06 ×

MQP-80C-P01 ×

MB89645
MB89646
MB89647

MB89P647

8-bit resolution × 2 channels, R-2R type

9 channels

2.2 V to 6.0 V 2.7 V to 6.0 V



MB89PV640

MBM27C256A

-20TV

: Available

Note: For more information about each package, see section “■ External Dimensions.”

× : Not available

4

MB89640 Series

DIFFERENCES AMONG PRODUCTS

■

1. Memory Size

Before e v aluating using the piggyback product, v erify its diff erences from the product that will actually be used.
Take particular care on the following points:

• On the MB89643 register banks 16 to 32 cannot be used.

• On the MB89P647, the program area starts from address 8007
from 8000H.

(On the MB89P647, addresses 8000
by reading these addresses. On the MB89PV640 and MB89647, addresses 8000
used as a program ROM. However, do not use these addresses in order to maintain compatibility of the
MB89P647.)

• The stack area, etc., is set at the upper limit of the RAM.

• The external areas are used.

H to 8006H comprise the option setting area, option settings can be read

H but on the MB89PV640 and MB89647 starts

H to 8006H could also be

2. Current Consumption

• In the case of the MB89PV640, add the current consumed by the EPROM which is connected to the top soc ket.

• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.

• However, the current consumption in sleep/stop modes is the same. (For more information, see sections
“■ Electrical Characteristics” and “■ Example Characteristics.”)

3. Mask Options

Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
Take particular care on the following points:

• A pull-up resistor cannot be set for P40 to P47 and P50 to P57 on the MB89P647.

• For all products, P60 to P67 are available for no pull-up resistor when an A/D converter is used.

• For all products, P50 to P57 are available for no pull-up resistor when a D/A converter is used.

• Options are fixed on the MB89PV640.

5

MB89640 Series

PIN ASSIGNMENT

■

P72/LI2

P73/LI3

P74/LI4

P60/AN0

P61/AN1

P62/AN2

(Top view)

P63/AN3

P64/AN4

P65/AN5

P66/AN6

SS

AVRL

P67/AN7

AV

AVRH

AVCCDAVC

P50/DA1

P51/DA2

P52/PWM

P53/PTO2

P71/LI1

P70/LI0
P83/INT3
P82/INT2
P81/INT1
P80/INT0

X0A

X1A
MOD0
MOD1

X0
X1

V

RST

P27/ALE

P26/RD

P25/WR

P24/CLK
P23/RDY
P22/HRQ

80797877767574737271706968676665646362

1
2
3
4
5
6
7
8
9
10
11
12
13

SS

14
15
16
17
18
19
20

21222324252627282930313233343536373839

P17/A15

P16/A14

P15/A13

P14/A12

P13/A11

P12/A10

P11/A09

P10/A08

P07/AD7

P06/AD6

P05/AD5

P04/AD4

P03/AD3

P21/HAK

P20/BUFC

P02/AD2

P01/AD1

P00/AD0

P37/PTO1

61

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

40

P36/WTO

P54/BZ
P55/SCK2
P56/SO2
P57/SI2

SS

V
P40
P41
V

CC

P42
P43
P44
P45
P46
P47
P30/ADST
P31/SCK1
P32/SO1
P33/SI1
P34/EC
P35/PWC

(FPT-80P-M11)

6

P74/LI4

P60/AN0

P61/AN1

(Top view)

P62/AN2

P63/AN3

P64/AN4

P65/AN5

P66/AN6

P67/AN7

SS

AV

AVRL

AVRH

AVCCDAVC

P50/DA1

MB89640 Series

P51/DA2

P73/LI3
P72/LI2
P71/LI1

P70/LI0
P83/INT3
P82/INT2
P81/INT1
P80/INT0

X0A

X1A
MOD0
MOD1

X0
X1

V

RST

P27/ALE

P26/RD

P25/WR

P24/CLK

P23/RDY

P22/HRQ

P21/HAK

P20/BUFC

807978777675747372717069686766

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

SS

16
17
18
19

Each pin inside the dashed line is for the

20
21
22
23
24

252627282930313233343536373839

100999897969594

101
102
103
104
105
106
107
108
109

110

111

MB89PV640 only.

818283

112

93
92
91
90
89
88
87
86
85

84

65

40

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

P52/PWM
P53/PTO2
P54/BZ
P55/SCK2
P56/SO2
P57/SI2

SS

V
P40
P41
V

CC

P42
P43
P44
P45
P46
P47
P30/ADST
P31/SCK1
P32/SO1
P33/SI1
P34/EC
P35/PWC
P36/WTO
P37/PTO1

P17/A15

P16/A14

P15/A13

P14/A12

P13/A11

P12/A10

P11/A09

P10/A08

P07/AD7

P06/AD6

P05/AD5

P04/AD4

P03/AD3

P02/AD2

P01/AD1

P00/AD0

(FPT-80P-M06)

(MQP-80C-P01)

• Pin assignment on package top (MB89PV640 only)
Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name

81 N.C. 89 A2 97 N.C. 105 OE
82 VPP 90 A1 98 O4 106 N.C.
83A1291A099O5107A11
84 A7 92 N.C. 100 O6 108 A9
85 A6 93 O1 101 O7 109 A8
86 A5 94 O2 102 O8 110 A13
87 A4 95 O3 103 CE
88 A3 96 V

SS 104 A10 112 VCC

111 A14

N.C.: Internally connected. Do not use.

7

MB89640 Series

PIN DESCRIPTION

■

Pin no.

Circuit

type

Function

QFP

*2

*1

QFP

MQFP

Pin name

*3

11 13 X0 A Main clock crystal oscillator pins (Max. 10 MHz)
12 14 X1

9 11 MOD0 C Operating mode selection pins

10 12 MOD1

Connect directly to V

CC or VSS.

14 16 RST D Reset I/O pin

This pin is an N-ch open-drain output type with pull-up
resistor, and a h ysteresis input type . “L” is output from this
pin by an internal reset source. The internal circuit is
initialized by the input of “L”.

38 to 31 40 to 33 P00/AD0 to

P07/AD7

E General-purpose I/O ports

Also serve as multiplex pins of lower address output and
data I/O.

30 to 23 32 to 25 P10/A08 to

P17/A15

22,
21,

18,

15

20,

19

17,

16

24,
23,
20,

17

22,

21

19,

18

P20/BUFC,
P21/HAK

,
P24/CLK,
P27/ALE

P22/HRQ,
P23/RDY

P25/WR

,

P26/RD

E General-purpose I/O ports

Also serve as an upper address output.

G General-purpose output-only ports

Also serve as a bus control signal output.

E General-purpose output-only ports

Also serve as a bus control signal input.

E General-purpose output-only ports

Also serve as a bus control signal output.

46 48 P30/ADST F General-purpose I/O port

45 47 P31/SCK1 F General-purpose I/O port

44,

43

42 44 P34/EC F General-purpose I/O port

*1: FPT-80P-M11
*2: FPT-80P-M06
*3: MQP-80C-P01

8

46,

45

P32/SO1,
P33/SI1

Also serves as an A/D converter external activation. This
port is a hysteresis input type.

Also serves as the clock I/O for the serial I/O 1. This port
is a hysteresis input type.

F General-purpose I/O ports

Also serve as the data output for the serial I/O 1. These
ports are a hysteresis input type.

Also serves as the external clock input for the 16-bit timer/
counter. This port is a hysteresis input type.

(Continued)

MB89640 Series

(Continued)

QFP

41 43 P35/PWC F General-purpose I/O port

40 42 P36/WTO F General-purpose I/O port

39 41 P37/PTO1 F General-purpose I/O port

55, 54,

52 to 47

64 66 P50/DA1 K N-ch open-drain I/O port

63 65 P51/DA2 K N-ch open-drain I/O port

62 64 P52/PWM H N-ch open-drain I/O port

Pin no.

*1

MQFP

54 to 49

*2

QFP

57, 56,

Pin name

*3

P40 to P47 L N-ch medium-voltage open-drain output-only ports

Circuit

type

Also serves as the measured pulse input for the 8-bit pulse
width counter. This port is a hysteresis input type.

Also serves as the toggle output for the 8-bit pulse width
counter. This port is a hysteresis input type.

Also serves as the toggle output for the 1-channel PWM
timer.

Also serves as a D/A channel 1 output. This port is a
hysteresis input type.

Also serves as a D/A channel 2 output. This port is a
hysteresis input type.

Also serves as the PWM output by the two PWM timers.
This port is a hysteresis input type.

Function

61 63 P53/PTO2 H N-ch open-drain I/O port

Also serves as the toggle output for the 2-channel PWM
timer. This port is a hysteresis input type.

60 62 P54/BZ H N-ch open-drain I/O port

Also serves as a buzzer output. This port is a hysteresis
input type.

59 61 P55/SCK2 H N-ch open-drain I/O port

Also serves as the clock I/O for the serial I/O 2. This port
is a hysteresis input type.

58 60 P56/SO2 H N-ch open-drain I/O port

Also serves as the data output for the serial I/O 2. This
port is a hysteresis input type.

57 59 P57/SI2 H N-ch open-drain I/O port

Also serves as the data input for the serial I/O 2. This port
is a hysteresis input type.

77 to 70 79 to 72 P60/AN0 to

P67/AN7

2, 1,

80 to 78

*1: FPT-80P-M11
*2: FPT-80P-M06
*3: MQP-80C-P01

4 to 1, 80 P70/LI0 to

P74/LI4

I N-ch open-drain output-only ports

Also serve as the analog input for the A/D converter.
These ports are a hysteresis input type.

J Input-only ports

Also serve as external interrupt 1 input. These ports are a
hysteresis input type.

9

MB89640 Series

(Continued)

Pin no.

Circuit

type

Function

QFP

*2

*1

QFP

MQFP

Pin name

*3

7 9 X0A B Subclock oscillator pins (32.768 kHz)
810X1A

53 55 V

13, 56 15, 58 V

66 68 AV

CC  Power supply pin
SS  Power supply (GND) pin

CC  A/D converter power supply pin

Use this pin at the same voltage as VCC.

67, 68 69, 70 AVRH, AVRL  A/D converter reference voltage input pins

65 67 DAVC  D/A converter power supply pin

Use this pin at the same voltage as V

69 71 AVSS  Analog circuit power supply pin

Use this pin at the same voltage as V

3 to 6 5 to 8 P83/INT3 to

P80/INT0

J Input-only ports

Also serve as an external interrupt 2 input. These ports
are a hysteresis input type.

*1: FPT-80P-M11
*2: FPT-80P-M06
*3: MQP-80C-P01

CC.

SS.

10

MB89640 Series

• External EPROM pins (MB89PV640 only)
Pin no. Pin name I/O Function

82 V
83

84
85
86
87
88
89
90
91

93
94
95

96 V
98

99
100
101
102

103 CE

PP O “H” level output pin

A12

O Address output pins
A7
A6
A5
A4
A3
A2
A1
A0

O1

I Data input pins
O2
O3

SS O Power supply (GND) pin

O4

I Data input pins
O5
O6
O7
O8

O ROM chip enable pin

Outputs “H” during standby.
104 A10 O Address output pin
105 OE

O ROM output enable pin

Outputs “L” at all times.
107

108
109

A11
A9

A8
110 A13 O
111 A14 O
112 V

81

CC O EPROM power supply pin

N.C. — Internally connected pins

92
97

106

O Address output pins

Be sure to leave them open.

11

MB89640 Series

I/O CIRCUIT TYPE

■

Type Circuit Remarks

A Main clock

X1

• At an oscillation feedback resistor of approximately

X0

Standby control signal

B Subclock

X1A

1 MΩ/5.0 V

• At an oscillation feedback resistor of approximately

X0A

Standby control signal

4.5 MΩ/5.0 V

C

D • At an output pull-up resistor (P-ch) of approximately

R

P-ch

50 kΩ/5.0 V

• Hysteresis input

N-ch

E • CMOS output

R
P-ch

P-ch

N-ch

• CMOS input

• Pull-up resistor optional

(Continued)

12

MB89640 Series

(Continued)

Type Circuit Remarks

F • CMOS output

R

• Hysteresis input

P-ch

P-ch

N-ch

• Pull-up resistor optional

G • CMOS output

R

P-ch

P-ch

N-ch

• Pull-up resistor optional

H • N-ch open-drain output

R

P-ch

N-ch

• Hysteresis input

• Pull-up resistor optional

I • N-ch open-drain output

R

P-ch

P-ch

N-ch

Analog input

• Analog input

• Pull-up resistor optional

J • Hysteresis input

R

• Pull-up resistor optional

(Continued)

13

MB89640 Series

(Continued)

Type Circuit Remarks

K • N-ch open-drain output

R

P-ch

P-ch

N-ch

Analog output

• Hysteresis input

• Analog output

Enable

• Pull-up resistor optional

L • N-ch open-drain output

R

P-ch

N-ch

• Medium voltage

• Pull-up resistor optional

14

MB89640 Series

HANDLING DEVICES

■

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lo wer than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between V

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.

CC and VSS.

Also, tak e care to prevent the analog po wer supply (A V
power supply (VCC) when the analog system power supply is turned on and off.

CC and A VRH) and analog input from exceeding the digital

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. The y should be connected to a pull-up or pull-do wn
resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AVCC = DAVC = VCC and AVSS = AVRH = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to oper ate within the rated range, a r apid fluctuation of the voltage
could cause malfunctions, ev en if it occurs within the rated range. Stabilizing voltage supplied to the IC is theref ore
important. As stabilization guidelines, it is recommended to control power so that V
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the tr ansient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.

CC ripple fluctuations (P-P

6. Precautions when Using an External Clock

Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.

15

MB89640 Series

PROGRAMMING TO THE EPROM ON THE MB89P647

■

The MB89P647 is an OTPROM version of the MB89640 series.

1. Features

• 32-Kbyte PROM on chip

• Options can be set using the EPROM programmer.

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below.

Single chipAddress EPROM mode

(Corresponding addresses on the EPROM programmer)

0000H

0080H

0180H

I/O

RAM

Not available
8000H

8007H 0007H

FFFFH

Not available

PROM

32 KB

0000H

Option area

EPROM

32 KB

7FFFH

• Precautions

(1) The program area of the MB89P647 is 7 bytes smaller than that of the MB89PV640 and MB89647 to provide

an option area. Note this point during program development.

(2) During normal operation, the option data is read when the option area is read from the CPU.

3. Programming to the EPROM

In EPROM mode, the MB89P647 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.

• Programming procedure

(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0007

while operating as internal ROM mode assign to 0007H to 7FFFH in EPROM mode).
Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each
corresponding option, see “7. Setting OTPROM Options.”)

(3) Program with the EPROM programmer.

16

H to 7FFFH (note that addresses 8007H to FFFFH

MB89640 Series

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure f or a product with a blanked
OTPROM microcomputer program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

5. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blank ed O TPR OM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.

6. EPROM Programmer Socket Adapter

Package Compatible socket adapter

FPT-80P-M06 R OM-80QF-28DP-8L2
FPT-80P-M11 R OM-80QF2-28DP-8L

Inquiry: Sun Hayato Co., Ltd.: TEL [phone]

Note: Depending on the EPR OM programmer , inserting a capacitor of about 0.1 µF between V

and VSS can stabilize programming operations.

PP and VSS or VCC

17

MB89640 Series

7. Setting OTPROM Options

The programming procedure is the same as that for the PROM. Options can be set by programming values at
the addresses shown on the memory map. The relationship between bits and options is shown on the f ollowing
bit map:

• OTPROM option bit map
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0000

Vacancy
Readable and

H

writable

Vacancy
Readable and

writable

Vacancy
Readable and

writable

Single/dual­clock system
1: Dual clock
2: Single clock

Reset pin
output
1: Yes
2: No

Power-on
reset
1: Yes
2: No

Oscillation stabilization time

00: 24/FCH
01: 217/FCH

10: 214/FCH
11: 218/FCH

0001

0002

0003

0004

0005

0006

P07
Pull-up

H

1: No
0: Yes

P17
Pull-up

H

1: No
0: Yes

P37
Pull-up

H

1: No
0: Yes

P67
Pull-up

H

1: No
0: Yes

Vacancy
Readable and

H

writable

Vacancy
Readable and

H

writable

P06
Pull-up
1: No
0: Yes

P16
Pull-up
1: No
0: Yes

P36
Pull-up
1: No
0: Yes

P66
Pull-up
1: No
0: Yes

Vacancy
Readable and

writable

Vacancy
Readable and

writable

P05
Pull-up
1: No
0: Yes

P15
Pull-up
1: No
0: Yes

P35
Pull-up
1: No
0: Yes

P65
Pull-up
1: No
0: Yes

Vacancy
Readable and

writable

Vacancy
Readable and

writable

P04
Pull-up
1: No
0: Yes

P14
Pull-up
1: No
0: Yes

P34
Pull-up
1: No
0: Yes

P64
Pull-up
1: No
0: Yes

P74
Pull-up
1: No
0: Yes

Vacancy
Readable and

writable

P03
Pull-up
1: No
0: Yes

P13
Pull-up
1: No
0: Yes

P33
Pull-up
1: No
0: Yes

P63
Pull-up
1: No
0: Yes

P73
Pull-up
1: No
0: Yes

P83
Pull-up
1: No
0: Yes

P02
Pull-up
1: No
0: Yes

P12
Pull-up
1: No
0: Yes

P32
Pull-up
1: No
0: Yes

P62
Pull-up
1: No
0: Yes

P72
Pull-up
1: No
0: Yes

P82
Pull-up
1: No
0: Yes

P01
Pull-up
1: No
0: Yes

P11
Pull-up
1: No
0: Yes

P31
Pull-up
1: No
0: Yes

P61
Pull-up
1: No
0: Yes

P71
Pull-up
1: No
0: Yes

P81
Pull-up
1: No
0: Yes

P00
Pull-up
1: No
0: Yes

P10
Pull-up
1: No
0: Yes

P30
Pull-up
1: No
0: Yes

P60
Pull-up
1: No
0: Yes

P70
Pull-up
1: No
0: Yes

P80
Pull-up
1: No
0: Yes

18

Notes:

• Set each bit to 1 to erase.

• Do not write 0 to the vacant bit.

The read value of the vacant bit is 1, unless 0 is written to it.

MB89640 Series

PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

■

1. EPROM for Use

MBM27C256A-20TV

2. Programming Socket Adapter

To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.

Package Adapter socket part number

LCC-32 (Rectangle) ROM-32LC-28DP-YG

Inquiry: Sun Hayato Co., Ltd.: TEL [phone]

3. Memory Space

Memory space in each mode, such as 32-Kbyte PROM is diagrammed below.

Address

0000H

0080H

0480H

8000H

8007H

FFFF

H

Single chip

I/O

RAM

Not available

Not available

PROM

32 KB

Corresponding addresses on the EPROM programmer

0000H

0007H

7FFF

H

4. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0007H to 7FFFH.

Not available

EPROM

32 KB

(3) Program to 0000

H to 7FFFH with the EPROM programmer.

19

MB89640 Series

BLOCK DIAGRAM

■

RST

P00/AD0
to P07/AD7

P10/A08
to P17/A15

MOD0
MOD1

P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
P20/BUFC

X0
X1

X0A
X1A

8

8

Main clock

oscillator

Clock controller

Subclock oscillator

(32.768 kHz)

Reset circuit

Time-base

timer

Watch prescaler

CMOS I/O ports

External bus

interface

Port 2 Port 0 and port 1

CMOS output port

ROM

2

F

MC-8L
CPU

RAM

8-bit pulse width

16-bit timer/counter

2-channel 8-bit

Internal bus

Buzzer output

2-channel 8-bit

D/A converter

N-ch open-drain output port

8-bit A/D converter

External interrupt 1

CMOS I/O port

counter

Serial I/O 1

PWM timer

Serial I/O 2

N-ch open-drain I/O port

Port 4

Medium-voltage N-ch

open-drain output port

8

CMOS input port

5

Port 3

Port 5

Port 6Port 7Port 8

P36/WTO
P35/PWC

P34/EC

P33/SI1
P32/SO1
P31/SCK1
P30/ADST
P37/PTO1
P52/PWM
P53/PTO2

P57/SI2
P56/SO2
P55/SCK2

P54/BZ

P51/DA2
P50/DA1

DAVC

P40 to P47

P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
AVRH
AVRL

CC

AV
AV SS

P74/LI4
P73/LI3
P72/LI2
P71/LI1
P70/LI0

20

Other pins

V

CC, V SS

External interrupt 2

CMOS input port

4

P83/INT3
P82/INT2
P81/INT1
P80/INT0

MB89640 Series

CPU CORE

■

1. Memory Space

The microcontrollers of the MB89640 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the low est address. The data area is pro vided immediately abov e the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89640 series is structured as illustrated below.

Memory Space

MB89P647

0000 H

0080 H

0100 H

0200 H

0480 H

MB89PV640

I/O

RAM
1 KB

Register

0000

0080 H

0100 H
0180 H

0280

MB89643

H

RAM

256 B

Not available

H

I/O

Register

0000

0080 H

0100 H

0200 H
0280 H

H

MB89645

I/O

RAM

512 B

Register

0000

0080 H

0100 H

0200 H

0380 H

H

MB89646

I/O

RAM

768 B

Register

0000

0080 H

0100 H

0200 H

0480 H

MB89647

H

I/O

RAM
1 KB

Register

External area

8000 H

Not available

8007 H

External ROM

32 KB

FFFF

H

Note: Since addresses 8000H to 8006H for the MB89P647 comprise an option area, do not use this area for the

MB89PV640 and MB89647.

C000 H

E000 H

FFFF H

External area

Not available

ROM

8 KB

C000 H

FFFF H

External area

ROM

16 KB

External area

A000 H

ROM

24 KB

FFFF H

External area

8000 H

Not available

8007 H

ROM

32 KB

FFFF H

21

MB89640 Series

2. Registers

The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:

Program counter (PC): A 16-bit register for indicating instruction storage positions
Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX): A 16-bit register for index modification
Extra pointer (EP): A 16-bit pointer for indicating a memory address
Stack pointer (SP): A 16-bit register for indicating a stack area
Program status (PS): A 16-bit register for storing a register pointer, a condition code

16 bits

PC

A

T

IX

EP

SP

PS

: Program counter

: Accumulator

: Temporary accumulator

: Index register

: Extra pointer

: Stack pointer

: Program status

Initial value

FFFD

H

Undefined

Undefined

Undefined

Undefined

Undefined

I-flag = 0, IL1, 0 = 11
Other bits are undefined.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)

Structure of the Program Status Register

109876 321015 14 13 12 11

54

22

RPPS

RP CCR

Vacancy

Vacancy Vacancy

H I IL1, 0 N Z VC

MB89640 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.

Rule for Conversion of Actual Addresses of the General-purpose Register Area

R1

A4

R0

↓

↓

A3

Lower OP codes

b2

b1

b0

↓

↓

↓

A2

A1

A0

Generated addresses

“0”

↓

A15

“0”

↓

A14

“0”

↓

A13

“0”

↓

A12

“0”

↓

A11

“0”

↓

A10

“0”

A9

RP

“1”

R4

R3

R2

↓

↓

↓

↓

↓

A8

A7

A6

A5

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.

H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0

when reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1 IL0 Interrupt level High-low

00

1

01
10 2

High

11 3

Low = no interrupt

N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag: Set if the complement on 2 overflo ws as a result of an arithmetic operation. Reset if the o verflow does

not occur.

C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.

Set to the shift-out value in the case of a shift instruction.

23

MB89640 Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers. Up to a total of 16 banks can be used on the MB89643 and a total of 32 banks can be used on
the MB89645/646/647/P647/PV640. The bank currently in use is indicated by the register bank pointer (RP).

Note: The number of register banks that can be used varies with the RAM size.

Register Bank Configuration

This address = 0100 H + 8 × (RP)

R0
R1
R2
R3
R4
R5
R6
R7

32 banks

Memory area

24

MB89640 Series

I/O MAP

■

Address Read/write Register name Register description

00

H (R/W) PDR0 Port 0 data register

01H (W) DDR0 Port 0 data direction register
02

H (R/W) PDR1 Port 1 data register

03

H (W) DDR1 Port 1 data direction register

04

H (R/W) PDR2 Port 2 data register

05H (W) BCTR External bus control register
06

H Vacancy

07

H (R/W) SYCC System clock control register

08H (R/W) STBC Standby control register
09

H (R/W) WDTC Watchdog timer control register

0A

H (R/W) TBCR Time-base timer control register

0BH (R/W) WPCR Watch prescaler control register
0C

H (R/W) PDR3 Port 3 data register

0D

H (W) DDR3 Port 3 data direction register

0EH (R/W) PDR4 Port 4 data register

0F

H (R/W) BUZR Buzzer register

10

H (R/W) PDR5 Port 5 data register

11

H (R/W) PDR6 Port 6 data register

12H (R) PDR7 Port 7 data register
13

H (R) PDR8 Port 8 data register

14

H Vacancy

15H Vacancy
16

H Vacancy

17

H Vacancy

18H (R/W) TMCR 16-bit timer control register
19

H (R/W) TCHR 16-bit timer count register (H)

1A

H (R/W) TCLR 16-bit timer count register (L)

1BH Vacancy
1C

H (R/W) SMR1 Serial 1 mode register

1D

H (R/W) SDR1 Serial 1 data register

1EH (R/W) SMR2 Serial 2 mode register

1F

H (R/W) SDR2 Serial 2 data register

(Continued)

25

MB89640 Series

(Continued)

Address Read/write Register name Register description

20

H (R/W) ADC1 A/D converter control register 1

21

H (R/W) ADC2 A/D converter control register 2

22

H (R/W) ADCD A/D converter data register

23H Vacancy
24

H (R/W) DACR D/A converter control register

25

H (W) DADR1 D/A converter data register 1

26H (W) DADR2 D/A converter data register 2
27

H Vacancy

28

H (R/W) CNTR1 PWM timer control register 1

29H (R/W) CNTR2 PWM timer control register 2

2A

H (R/W) CNTR3 PWM timer control register 3

2B

H (W) COMR1 PWM timer compare register 1

2CH (W) COMR2 PWM timer compare register 2
2D

H (R/W) PCR1 PWC pulse width control register 1

2E

H (R/W) PCR2 PWC pulse width control register 2

2FH (R/W) RLBR PWC reload buffer register
30

H Vacancy

31

H (R/W) EIC1 External interrupt 1 control register 1

32

H (R/W) EIC2 External interrupt 1 control register 2

33H (R/W) EIE2 External interr upt 2 enable register
34

H (R/W) EIF2 External interrupt 2 flag register

35

H to 7AH Vacancy

7BH Vacancy
7C

H (W) ILR1 Interrupt level setting register 1

7D

H (W) ILR2 Interrupt level setting register 2

7EH (W) ILR3 Interrupt level setting register 3

7F

H Vacancy

Note: Do not use vacancies.

26

ELECTRICAL CHARACTERISTICS

■

1. Absolute Maximum Ratings

Parameter

Power supply voltage

Symbol

V

CC

AVCC
DAVC

Value

Unit Remarks

Min. Max.

SS – 0.3 VSS + 7.0 V *

V

MB89640 Series

(AVSS = VSS = 0.0 V)

A/D converter reference input
voltage

Program voltage V

Input voltage

Output voltage

“L” level maximum output
current

“L” level average output current I
“L” level total average output

current

AVRH V
AVRL V

PP VSS – 0.3 13.0 V MOD1 pin on MB89P647

V

I VSS – 0.3 VCC + 0.3 V

V

I2 VSS – 0.3 VSS + 7.0 V

SS – 0.3 VSS + 7.0 V
SS – 0.3 VSS + 7.0 V AVRL must not exceed AVRH.

AVRH must not exceed AV

0.3 V.

P52 to P57 with a pull-up
resistor and other input ports

P52 to P57 without a pull-up
resistor

P40 to P47 and P52 to P57 with

O VSS – 0.3 VCC + 0.3 V

V

a pull-up resistor and other
output ports

O2 VSS – 0.3

V

O3 VSS – 0.3 VSS + 7.0 V

V

I

OL  20 mA

OLAV  4mA

∑I

OLAV  40 mA

VSS + 17.0

P40 to P47 without a pull-up

V

resistor
P52 to P57 without a pull-up

resistor

Average value (operating
current × operating rate)

Average value (operating
current × operating rate)

CC +

“L” level total maximum output
current

“H” level maximum output
current

“H” level average output current I
“H” level total average output

current
“H” level total maximum output

current
Power consumption P

OL  100 mA

∑I

OH  –20 mA

I

OHAV  –4 mA

OHAV  –20 mA

∑I

∑I

OH  –50 mA

D  500 mW

Average value (operating
current × operating rate)

Average value (operating
current × operating rate)

(Continued)

27

MB89640 Series

(Continued)

Parameter

Symbol

(AVSS = VSS = 0.0 V)

Value

Unit Remarks

Min. Max.

Operating temperature T

A –40 +85 °C

Storage temperature Tstg –55 +150 °C

* :Use DAVC and AVCC and VCC set at the same voltage.

Take care so that DAVC and AV

CC does not exceed VCC, such as when power is turned on.

Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.

Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

Parameter

Power supply voltage

A/D converter reference input
voltage

Symbol

V

CC

AVCC
DAVC

AVRH 3.0 AV
AVRL 0.0 2.0 V

Value

Unit Remarks

Min. Max.

2.2* 6.0* V

2.7* 6.0* V

Normal operation assurance range*
(MB89643/645/646/647)

Normal operation assurance range*
(MB89P647/PV640)

1.5 6.0 V Retains the RAM state in stop mode

CC V

Operating temperature T

A –40 +85 °C

* :These values vary with the operating frequency and analog assurance range. See Figure 1, “5. A/D Converter

Electrical Characteristics,” and “6. D/A Converter Electrical Characteristics.”

28

MB89640 Series

6

5

4

3

Operating voltage (V)

2

1

1.0 10.0

Main clock operating frequency (at an instruction cycle of 4/F

4.0 0.40.82.0

Minimum execution time (instruction cycle) (µs)

Note: The shaded area is assured only for the MB89643/645/646/647.

Operation assurance range

5.0

1.0 0.5

Analog accuracy assured in the
VCC = AVCC = DAVC = 3.5 V to 6.0 V range.

CH) (MHz)

Figure 1 Operating Voltage vs. Main Clock Operating Frequency

Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/F

CH.

Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the
operating speed is switched using a gear.

29

MB89640 Series

3. DC Characteristics

(AVCC = DAVC = VCC = +5.0 V, AVSS = VSS = 0.0 V, FCH = 10 MHz, FCL = 32.768 kHz, TA = –40°C to +85°C)

Parameter

“H” level input
voltage

*1

“L” level input
voltage

*1

Open-drain output
pin application
voltage

“H” level output
voltage

“L” level output
voltage

Input leakage
current (Hi-z output
leakage current)

Symbol

VIH

V

P00 to P07, P10 to
P17, P22, P23

RST, P30 to P37,
P50, P51, P70 to P74,
P80 to P83

IHS

P52 to P57

IHS2 P52 to P57 0.8 VCC 

V

VIL

P00 to P07, P10 to
P17, P22, P23

RST, P30 to P37,
P50 to P57, P70 to

ILS

V

P74, P80 to P83

D P40 to P47

V

VD2 P52 to P57

P60 to P67

D3

V

P40 to P47, P52 to
P57

V

V

V

I

P00 to P07, P10 to P17,

OH

P20 to P27, P30 to P37
P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

OL

P40 to P47, P50 to P57,
P60 to P67

OL2 RST IOL = +4.0 mA 0.4 V

P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P50 to P57, P70 to P74,

LI1

P80 to P83, MOD0,
MOD1

Pin Condition



IOH = –2.0 mA 2.4 V

IOL = +1.8 mA 0.4 V

0.45 V < VI < VCC

Value

Min. Typ. Max.

CC 

0.7 V

0.8 VCC 

SS

V

− 0.3

SS

V

− 0.3

SS

V

− 0.3

SS

V

− 0.3

SS

V

− 0.3

VCC + 0.3

VCC + 0.3

VSS + 6.0

 0.3 VCC V

 0.2 VCC V

SS

V







+ 15.0

VSS + 6.0

VCC + 0.3

±5 µA

Unit Remarks

V

V

With pull-up
resistor

Without pull-

V

up resistor

Without pull-

V

up resistor
Without pull-

V

up resistor

V

With pull-up
resistor

Without pull­up resistor

(Continued)

30

(AV

Parameter

Pull-up resistance R

Power supply
current

Power supply
current

Input capacitance C

MB89640 Series

CC = DAVC = VCC = +5.0 V, AVSS = VSS = 0.0 V, FCH = 10 MHz, FCL = 32.768 kHz, TA = –40°C to +85°C)

Symbol

P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P50 to P57, P60 to P64,

PULL

P70 to P74, P80 to P83,
RST

I

CC1

CC2

I

I

CS1

VCC

I

CS2

I

CS3

ICCH

CSB

I

I

CCT VCC

I

A AVCC

Other than AVCC,

IN

AV

Pin Condition

VI = 0.0 V 25 50 100 kΩ

VCC = +5.0 V

• Main clock

• High speed
VCC = +3.0 V

• Main clock

• Low speed

CC

V

• Main clock sleep

• High speed

CC

V

• Main clock sleep

• Low speed

CC

V
Subclock sleep

TA = +25°C

Subclock stop

CC

V
Subclock operation

(32.768 kHz)

VCC = +3.0 V
Watch mode
(32.768 kHz)

• Main clock

• High speed

SS, VCC, and VSS

f = 1 MHz — 10  pF

operation

operation

= +5.0 V

= +3.0 V

= +3.0 V

= +3.0 V

operation

Min. Typ. Max.

—1020mA

*2

—1123mA
—1.5 2mA

*3

*2

*3

—2.5 5mA

—3 7mA

—11.5mA

—2550µA

——10µA
—50100µA
—1 3mA

——15µA

—1 3mA

*2

Value

Unit Remarks

Without pull­up resistor

MB89P647
only

MB89P647
only

MB89P647
only

*1: Connect MOD0 and MOD1 to VCC or VSS.
*2: High-speed operation is the operation when the system clock is set to the maxim um speed by the system cloc k

select bit at 10-MHz clock.

*3: Low-speed operation is the operation when the system cloc k is set to the maximu m speed by the system cloc k

select bit at 10-MHz clock.

31

MB89640 Series

4. AC Characteristics

(1) Reset Timing

Parameter

RST

“L” pulse width tZLZH —48 tXCYL —ns

* :tXCYL is the oscillation cycle (1/FCH) to input to the X0 pin.

Symbol Condition

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Unit Remarks

Min. Max.

tZLZH

RST

0.2 V CC 0.2 V CC

(2) Power-on Reset

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol Condition

Unit Remarks

Min. Max.

Power supply rising time t

R

—50ms

—

Power supply cut-off time t

OFF 1 — ms Due to repeated operation

Note: Make sure that power supply rises within the selected oscillation stabilization time.

For example, when the main clock is operating at 10 MHz (F
option has been set to 2

14

/FCH, the oscillation stabilization delay time is 1.6 ms and accordingly the maximum

CH) and the oscillation stabilization time select

value of power supply rising time is about 1.6 ms.
Keep in mind that abrupt changes in power supply voltage may cause a power-on reset. If power supply

voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.

VCC

t

2.0 V

0.2 V

R

0.2 V

tOFF

0.2 V

32

(3) Clock Timing

Parameter

Symbol Pin Condition

MB89640 Series

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Unit Remarks

Min. Typ. Max.

CH X0, X1

F

Clock frequency

FCL X0A, X1A — 32.768 — kHz

XCYL X0, X1 100 — 1000 ns

t

Clock cycle time

t

LXCYL X0A, X1A — 30.5 — µs

P

WH

PWL

Input clock pulse width

WHL

P
PWLL

Input clock rising/falling time

tCR
tCF

X0 and X1 Timing and Conditions

X0

1—10MHz

X0 20 — — ns External clock

—

X0A — 30.5 — µs

X0 — — 10 ns External clock

tCR tCF

0.8 VCC

0.2 VCC

0.8 VCC

tXCYL

0.2 VCC

PWLPWH

0.2 VCC

Main Clock Conditions

When a crystal

ceramic resonator is used.

X0 X1 X0 X1

or

When an external clock is used.

Open

33

MB89640 Series

X0A and X1A Timing and Conditions

tLXCYL

PWHL PWLL

tCR tCF

X0A

Subclock Conditions

ceramic resonator is used.

X0A X1A X0A X1A

(4) Instruction Cycle

Parameter

0.8 VCC

0.2 VCC

When a crystal

or

0.8 VCC

0.2 VCC

0.2 VCC

When an external clock is used.

Open

Symbol Value (typical) Unit Remarks

Instruction cycle
(minimum execution time)

34

inst = 0.4 µs when operating at FCH =

4/FCH system clock selection 11

8/FCH system clock selection 10

t

inst

16/FCH system clock selection 01

64/FCH system clock selection 00

t

µs

10 MHz

inst = 0.8 µs when operating at FCH =

t

µs

10 MHz
t

inst = 1.6 µs when operating at FCH =

µs

10 MHz
t

inst = 6.4 µs when operating at FCH =

µs

10 MHz

(5) Recommended Resonator Manufacturers

Sample Application of Piezoelectric Resonator (FAR series)

X0 X1

FAR*

* : Fujitsu Acoustic Resonator

C1 C2

C1 = C2 = 20 pF±8 pF (built-in FAR)

MB89640 Series

FAR part number

(built-in capacitor type)

Frequency

Initial deviation of

FAR frequency

A

= +25°C)

(T

Temperature characteristic of

FAR frequency

(TA = –20°C to +60°C)

FAR-C4CB-08000-M02 8.00 MHz ±0.5% ±0.5%
FAR-C4CB-10000-M02 10.00 MHz ±0.5% ±0.5%

Inquiry: FUJITSU LIMITED

35

MB89640 Series

Sample Application of Ceramic Resonator

X0

X1

*

C1 C2

Resonator manufacturer* Resonator Frequency C1 (pF) C2 (pF) R (kΩ)

KBR-7.68MWS 7.68 MHz 33 33 

Kyocera Corporation

KBR-8.0MWS 8.0 MHz 33 33 

Murata Mfg. Co., Ltd. CSA8.00MTZ 8.0 MHz 30 30 

Inquiry: Kyocera Corporation

• AVX Corporation
North American Sales Headquarters: TEL [phone]

• AVX Limited
European Sales Headquarters: TEL [phone]

• AVX/Kyocera H.K. Ltd.
Asian Sales Headquarters: TEL [phone]

Murata Mfg. Co., Ltd.

• Murata Electronics North America, Inc.: TEL [phone]

• Murata Europe Management GmbH: TEL [phone]

• Murata Electronics Singapore (Pte.) Ltd.: TEL [phone]

(6) Clock Output Timing

Parameter Symbol Pin Condition

Cycle time t

CLK ↑→ CLK ↓ t

36

CLK

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Unit Remarks

Min. Max.

CYC CLK

200 — ns

—

CHCL CLK 30 100 ns

tCYC

tCHCL

2.4 V

0.8 V

2.4 V

t

XCYL × 2 at 10 MHz

oscillation
Approx. t

CYL/2 at

10 MHz oscillation

MB89640 Series

(7) Bus Read Timing

(VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Parameter Symbol Pin Condition

Valid address → RD

pulse width tRLRH RD

RD
Valid address → read data

time

↓ → read data time tRLDV RD, AD7 to 0

RD

↓ time tAVRL

AVDV

t

RD ↑ → data hold time tRHDX AD7 to 0, RD 0—ns
RD

↑ → ALE ↑ time tRHLH RD, ALE

RD ↑ → address invalid time tRHAX

RD, A15 to
08, AD7 to 0

AD7 to 0,
A15 to 08

—

RD , A15 to 08 1/4 tinst* – 40 ns

RD ↓ → CLK ↑ time tRLCH RD, CLK
CLK ↓ → RD

↑ time tCLRH RD, CLK 0 — ns

1/4 tinst* – 64 ns

1/2 tinst* – 20 ns

1/2 tinst* – 80 ns

1/4 tinst* – 40 ns

1/4 tinst* – 40 ns

RD ↓ → BUFC ↓ time tRLBL RD, BUFC –5 — ns
BUFC ↑→ Valid address time t

BHAV

A15 to 08,
AD7 to 0, BUFC

Value

Unit Remarks

Min. Max.

—ns
—ns

1/2 t

inst* 200 ns No wait

120 ns No wait

—ns
—ns
—ns

5—ns

* :For information on tinst, see “(4) Instruction Cycle.”

CLK

ALE

AD

A

RD

2.4 V

0.8 V

2.4 V

0.8 V

tAVRL

tAVDV

tRLCH

0.8 V

tRLBL

tRLDV

tRLRH

2.4 V

0.7 VCC

0.3 VCC

0.8 V

2.4 V

tRHLH

0.7 V

0.3 VCC

t

RHDX

2.4 V

0.8 V

tCLRH

tRHAX

0.8 V

CC

2.4 V

0.8 V

2.4 V

0.8 V

tBHAV

BUFC

2.4 V

0.8 V

37

MB89640 Series

(8) Bus Write Timing

(VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Parameter Symbol Pin Condition

Valid address → ALE ↓ time t

ALE ↓ → address invalid time t
Valid address → WR

↓ time tAVWL WR, ALE

AVLL

LLAX

AD7 to 0, ALE,
A15 to 08

AD7 to 0, ALE,
A15 to 08

WR pulse width tWLWH WR
Write data → WR ↑ time tDVWH
WR

↑ → address invalid time tWHAX

WR ↑ → data hold time tWHDX

AD7 to 0, WR
WR, A15 to 08
AD7 to 0, WR

WR ↑ → ALE ↑ time tWHLH WR, ALE
WR

↓ → CLK ↑ time tWLCH WR, CLK

—

1/4 t

1/4 t
1/2 t
1/2 t
1/4 t
1/4 t
1/4 t
1/4 t

CLK ↓ → WR ↑ time tCLWH WR, CLK 0 — ns
ALE pulse width tLHLL ALE
ALE ↓ → CLK ↑ time t

LLCH ALE, CLK

1/4 t
1/4 t

Value

Min. Max.

*1

inst

– 64 ns

*2

—ns

5—ns*2

*1

inst

inst

inst

inst

inst

inst

inst

*1

inst

*1

inst

– 60 ns

*1

– 20 ns

*1

– 60 ns

*1

– 40 ns

*1

– 40 ns

*1

– 40 ns

*1

– 40 ns

– 35 ns
– 30 ns

—ns
—ns
—ns
—ns
—ns
—ns
—ns

*2

—ns

*2

—ns

Unit Remarks

*1: For information on tinst, see “(4) Instruction Cycle.”
*2: These characteristics are also applicable to the bus read timing.

CLK

ALE

AD

A

WR

2.4 V

tAVLL

2.4 V

0.8 V

2.4 V

0.8 V

t

AVWL

2.4 V

0.8 V

tLLCHtLHLL

0.8 V

tLLAX

2.4 V

0.8 V

tWLCH

0.8 V

2.4 V

tDVWH

tWLWH

0.8 V

2.4 V

tWHLH

2.4 V

0.8 V

tWHDX

2.4 V

0.8 V

tCLWH
tWHAX

0.8 V

38

(9) Ready Input Timing

(VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Parameter Symbol Pin Condition

RDY valid → CLK ↑ time t
CLK ↑ → RDY invalid time t

YVCH RDY, CLK
CHYX RDY, CLK 0 — ns *

* :These characteristics are also applicable to the read cycle.

MB89640 Series

Value

Unit Remarks

Min. Max.

60 — ns *

—

CLK

ALE

AD

A

WR

RDY

Address

2.4 V 2.4 V

Data

tYVCH tCHYX

Note: The bus cycle is also extended in the read cycle in the same manner.

tYVCH tCHYX

39

MB89640 Series

(10) Serial I/O Timing

Parameter

(VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Symbol Pin Condition

Value

Unit Remarks

Min. Max.

Serial clock cycle time t
SCK1 ↓ → SO1 time

SCK2 ↓ → SO2 time
Valid SI1 → SCK1 ↑

Valid SI2 → SCK2 ↑
SCK1 ↑ → valid SI1 hold time

SCK2 ↑ → valid SI2 hold time
Serial clock “H” pulse width t
Serial clock “L” pulse width t
SCK1 ↓ → SO1 time

SCK2 ↓ → SO2 time
Valid SI1 → SCK1 ↑

Valid SI2 → SCK2 ↑
SCK1 ↑ → valid SI1 hold time

SCK2 ↑ → valid SI2 hold time

SCYC SCK1, SCK2

SLOV

t

IVSH

t

SHIX

t

SHSL SCK1, SCK2
SLSH SCK1, SCK2 1 tinst*—µs

t

SLOV

t

IVSH

t

SHIX

SCK1, SO1
SCK2, SO2

SI1, SCK1
SI2, SCK2

SCK1, SI1
SCK2, SI2

SCK1, SO1
SCK2, SO2

SI1, SCK1
SI2, SCK2

SCK1, SI1
SCK2, SI2

* :For information on tinst, see “(4) Instruction Cycle.”

Internal shift
clock mode

External shift
clock mode

2 tinst*—µs

–200 200 ns

1/2 t

inst*— µs

1/2 t

inst*— µs

1 tinst*—µs

0 200 ns

inst*— µs

1/2 t

1/2 t

inst*— µs

40

Internal Shift Clock Mode

SCYC

t

MB89640 Series

SCK1
SCK2

SO1
SO2

SI1
SI2

External Shift Clock Mode

SCK1
SCK2

0.8 V

0.2 VCC

tSLOV

2.4 V

0.8 V

tSLSH

tIVSH

0.8 VCC

0.2 VCC

0.2 VCC

2.4 V

tSHIX

0.8 VCC

0.8 V

0.8 VCC

0.2 VCC

tSHSL

0.8 VCC

SO1
SO2

SI1
SI2

tSLOV

2.4 V

0.8 V

tIVSH

0.8 VCC

0.2 VCC

tSHIX

0.8 VCC

0.2 VCC

41

MB89640 Series

(11) Peripheral Input Timing

Parameter

(VCC = +5.0 V±10%, FCH = 10 MHz, A VSS = VSS = 0.0 V, TA = –40°C to +85°C)

Symbol Pin Condition

Value

Unit Remarks

Min. Max.

Peripheral input pulse “H”
width 1

Peripheral input pulse “L”
width 1

Peripheral input pulse “H”
width 2

Peripheral input pulse “L”
width 2

Peripheral input pulse “H”
width 2

Peripheral input pulse “L”
width 2

t

ILIH1

t

IHIL1

ILIH2 ADST

t

t

IHIL2 ADST 32 tinst*— µs

ILIH2 ADST

t

IHIL2 ADST 8 tinst*—µs

t

PWC, EC,
INT0 to INT3

PWC, EC,
INT0 to INT3

* :For information on tinst, see “(4) Instruction Cycle.”

tIHIL1

PWC
EC
INT0 to 3

0.2 VCC

—

A/D mode

Sense mode

0.8 VCC

0.2 VCC

2 t

inst*—µs

2 t

inst*—µs

32 tinst*— µs

8 tinst*—µs

tILIH1

0.8 VCC

42

ADST

0.2 VCC

tIHIL2

0.8 VCC

0.2 VCC

tILIH2

0.8 VCC

5. A/D Converter Electrical Characteristics

(AVCC = VCC = +3.5 V to +6.0 V, FCH = 10 MHz, AVSS = VSS = AVRL = 0.0 V, TA = –40°C to +85°C)

Parameter

Symbol

Pin Condition

MB89640 Series

Value

Unit Remarks

Min. Typ. Max.

Resolution
Total error
Linearity error — — ±1.0 LSB

—

Differential linearity
error

Zero transition voltage V
Full-scale transition

voltage

OT –1.0 +0.5 +2.0 LSB

—

V

FST

Interchannel disparity
A/D mode conversion

time

—

Sense mode
conversion time

Analog port input
current

AIN

I

AN0 to

——— 8bit

——±3.0 LSB

——±0.9 LSB

AVRH = AV

CC

AVRH – 4.5 AVRH – 1.5 AVRH + 1.5

LSB
——0.5LSB
—44—t

—12—t

inst*

inst*

—

——10µA

AN7

Analog input voltage — 0 — AVRH V
Reference voltage —

I

R

Reference voltage
supply current

I

RH

AVRH

When A/D
conversion is
activated
AVRH = 5.0 V

When A/D
conversion is
stopped
AVRH = 5.0 V

0—AV

—100µA

—— 1µA

CC V

* : For information on tinst, see “(4) Instruction Cycle.”

43

MB89640 Series

(1) A/D Glossary

• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 8, analog voltage can be divided into 2

• Linearity error (unit: LSB)
The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the
full-scale transition point (“1111 1111” ↔

“1111 1110”) from actual conversion characteristics

• Differential linearity error (unit: LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit: LSB)
The difference between theoretical and actual conversion values

Digital output

8

= 256.

1111
1111

0000
0000
0000

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

1111
1110

0010
0001
0000

Theoretical conversion value

Actual conversion value

(1 LSB × N + V

VOT VNT V(N + 1)T VFST

OT)

Linearity error

Differential linearity error =

Analog input

1 LSB =

Linearity error =

AVRH – AVRL

Total error =

256

NT – (1 LSB × N + VOT)

V

V( N + 1 ) T – VNT

VNT – (1 LSB × N + 1 LSB)

1 LSB

1 LSB

– 1

1 LSB

(2) Precautions

• Input impedance of the analog input pins

The A/D converter used for the MB89640 series contains a sample hold circuit as illustrated below to fetch
analog input voltage into the sample hold capacitor for eight instruction cycles after activ ating A/D conv ersion.

For this reason, if the output impedance of the e xternal circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low (below 10 kΩ).

Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about

0.1 µF for the analog input pin.

44

MB89640 Series

Analog Input Equivalent Circuit

Sample hold circuit

Analog input pin

If the analog input
impedance is higher
than 10 kΩ, it is
recommended to
contact an external
capacitor of about

0.1 µF.
Analog channel selector

•Error

The smaller the | AVRH – AVRL |, the greater the error would become relatively.

.

C = 33 pF

.

.

R = 6 kΩ

.

Close for 8 instruction cycles after activating
A/D conversion.

Comparator

6. D/A Converter Electrical Characteristics

(DAVC = VCC = +3.5 V to +6.0 V, FCH=10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Parameter Symbol

Min. Typ. Max.

Resolution

—— 8bit

Linearity error — — ±1.0 LSB

—

Differential linearity error — — ±0.9 LSB
Output impedance — 20 — kΩ

I

D/A analog power supply

DINA —0.1 mA

current (for one channel)

I

DINS —0.1—µA During power down

Value

Unit Remarks

DAVC = V

CC = 5.0 V

At no load and
conversion cycle of
5 µs

45

MB89640 Series

EXAMPLES CHARACTERISTICS

■

(1) “L” Level Output Voltage (P00 to P07, P10

to P17, P20 to P27, P30 to P37, P50 to P57,
P60 to P67)

OL (V)

V

0.6

0.5

0.4

0.3

0.2

0.1

0.0
010123456789

VOL vs. IOL

TA = +25°C

V

V

V
V

V

I

OL (mA)

CC = 2.5 V

CC = 3.0 V

CC = 4.0 V
CC = 5.0 V

CC = 6.0 V

(2) “H” Level Output Voltage (P00 to P07, P10 to

P17, P20 to P27, P30 to P37)

CC–VOH (V)

V

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.0

VCC–VOH vs. IOH

–0.5 –1.0 –1.5 –2.0 –2.5 –3.0

TA = +25°C

V

V
V

V
VCC = 6.0 V

I

OH (mA)

CC = 2.5 V

CC = 3.0 V
CC = 4.0 V

CC = 5.0 V

(3) “L” Level Output Voltage (P40 to P47)

OL (mV)

V
1500
1400
1300
1200
1100
1000

900
800
700
600
500
400
300
200
100

0

010123456789

VOL vs. IOL

TA = +25°C

11 12 13 14 15

I

OL (mA)

CC = 5 V

V

(4) “H” Level Input V oltage/“L” Le vel Input V oltage

(CMOS Input)

IN (V)

V

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0
0123456

VIN vs. VCC

TA = +25°C

V

CC (V)

7

46

(5) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input)

MB89640 Series

IN (V)

V

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0
0123 456

VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level

(6) Power Supply Current (External Clock)

VIN vs. VCC

TA = +25°C

V

IHS

VILS

V

7

CC (V)

Main clock operation mode (4/FCH instruction)

ICC vs. VCC

CC (mA)

I

15
14

13
12
11

10

9
8

7
6
5
4
3

2
1
0

23456

TA = +25°C

V

CC (V)

XTAL
10 MHz

8 MHz

6 MHz

4 MHz

2 MHz
1 MHz

I

CC vs. VCC

Main clock operation mode (64/FCH instruction)

CC (mA)

I

3

TA = +25°C

2

1

0

23456

V

CC (V)

XTAL

10 MHz
8 MHz

6 MHz
4 MHz

2 MHz
1 MHz

(Continued)

47

MB89640 Series

(Continued)

ICS1 vs. VCC

Main clock sleep mode (4/FCH instruction)

ICS1 (mA)

4

3

2

1

0

23456

TA = +25°C

V

CC (V)

XTAL
10 MHz

8 MHz

6 MHz

4 MHz

2 MHz
1 MHz

ICS3 vs. VCC

ICS3 (µA)

120

100

80

60

40

Subclock mode

T

A = +25°C

Operation

Sleep

CS2 vs. VCC

I

Main clock sleep mode (64/FCH instruction)

CS2 (µA)

I

1,500

1,000

500

0

23456

TA = +25°C

V

XTAL
10 MHz

8 MHz

6 MHz

4 MHz

2 MHz
1 MHz

CC (V)

20

0

23456

V

CC (V)

Watch

(7) Pull-up Resistance

PULL (kΩ)

R

1000

100

10

1

2345 6

RPULL vs. VCC

TA = +25°C

V

CC (V)

48

INSTRUCTIONS

■

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

•Others

Table 1 lists symbols used for notation of instructions.

MB89640 Series

Table 1 Instruction Symbols

Symbol Meaning

dir Direct address (8 bits)
off Offset (8 bits)

ext Extended address (16 bits)
#vct Vector table number (3 bits)
#d8 Immediate data (8 bits)

#d16 Immediate data (16 bits)
dir: b Bit direct address (8:3 bits)

rel Branch relative address (8 bits)
@ Register indirect (Example: @A, @IX, @EP)

A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

AH Upper 8 bits of accumulator A (8 bits)

AL Lower 8 bits of accumulator A (8 bits)

T

TH Upper 8 bits of temporary accumulator T (8 bits)

TL Lower 8 bits of temporary accumulator T (8 bits)

IX Index register IX (16 bits)

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)

(Continued)

49

MB89640 Series

(Continued)

Symbol Meaning

EP Extra pointer EP (16 bits)
PC Program counter PC (16 bits)
SP Stack pointer SP (16 bits)
PS Program status PS (16 bits)

dr Accumulator A or index register IX (16 bits)

CCR Condition code register CCR (8 bits)

RP Register bank pointer RP (5 bits)

Ri General-purpose register Ri (8 bits, i = 0 to 7)

×

( × )

(( × ))

Columns indicate the following:
Mnemonic: Assembler notation of an instruction
~: Number of instructions
#: Number of bytes
Operation: Operation of an instruction
TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in

Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)

Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)

The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)

the column indicate the following:

“–” indicates no change.

•

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH immediately bef ore the instruction
is executed.

• 00 becomes 00.

50

N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

OP code: Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.

MB89640 Series

–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

–
–

–
AH
AH
AH

AH
AH
AH

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–
AH

–

–

–

–

–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

–
–

–
dH
dH
dH

dH
dH
dH
dH

–

–
dH

–
dH

–

–

–
dH

–

–
AL

–

–

–
dH
dH
dH
dH
dH

– – – –
– – – –
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –

– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –

+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –

– – – –
+ + + +
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –

Table 2 Transfer Instructions (48 instructions)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A

MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off

MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC

(dir) ← (A)

2

3

( (IX) +off ) ← (A)

2

4

(ext) ← (A)

3

4

( (EP) ) ← (A)

1

3

(Ri) ← (A)

1

3

(A) ← d8

2

2

(A) ← (dir)

2

3

(A) ← ( (IX) +off)

2

4

(A) ← (ext)

3

4

(A) ← ( (A) )

1

3

(A) ← ( (EP) )

1

3

(A) ← (Ri)

1

3

(dir) ← d8

3

4

( (IX) +off ) ← d8

3

5

( (EP) ) ← d8

2

4

(Ri) ← d8

2

4

(dir) ← (AH),(dir + 1) ← (AL)

2

4

( (IX) +off) ← (AH),

2

5

( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)

3

5

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

1

4

(EP) ← (A)

1

2

(A) ← d16

3

3

(AH) ← (dir), (AL) ← (dir + 1)

2

4

(AH) ← ( (IX) +off),

2

5

(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)

3

5

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

1

4

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)

1

4

(A) ← (EP)

1

2

(EP) ← d16

3

3

(IX) ← (A)

1

2

(A) ← (IX)

1

2

(SP) ← (A)

1

2

(A) ← (SP)

1

2

( (A) ) ← (T)

1

3

( (A) ) ← (TH),( (A) + 1) ← (TL)

1

4

(IX) ← d16

3

3

(A) ← (PS)

1

2

(PS) ← (A)

1

2

(SP) ← d16

3

3

(AH) ↔ (AL)

1

2

(dir): b ← 1

2

4

(dir): b ← 0

2

4

(AL) ↔ (TL)

1

2

(A) ↔ (T)

1

3

(A) ↔ (EP)

1

3

(A) ↔ (IX)

1

3

(A) ↔ (SP)

1

3

(A) ← (PC)

1

2

–
–
–
–

–
AL
AL
AL
AL
AL
AL
AL

–

–

–

–

–

–

–

–

–
AL
AL
AL

AL
AL
AL

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–
AL
AL

–

–

–

–

45
46
61
47

48 to 4F

04
05
06
60
92
07

08 to 0F

85
86
87

88 to 8F

D5
D6

D4
D7
E3
E4
C5
C6

C4

93

C7

F3
E7
E2

F2
E1

F1

82

83
E6

70

71
E5

10

A8 to AF
A0 to A7

42

43

F7

F6

F5

F0

Notes:

• During byte transfer to A, T

• Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F

←

A is restricted to low bytes.

2

MC-8 family)

51

MB89640 Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

1

19
21

3

2

2

2

3

2

4

1

3

1

3

1

2

1

3

2

2

2

3

2

4

1

3

1

3

1

2

1

4

1

3

1

3

1

3

1

4

1

3

1

3

1

3

1
1
1

3

1

3

1

3

1

2

1

3

1

2

ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A

(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)

(TL) − (AL)
(T) − (A)

→→

A

C

–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

dL

–
–
–
–
–
–

00

+ + + +

–

–

+ + + +

–

–

+ + + +

–

–

+ + + +

–

–

+ + + +

–

–

+ + + +

dH

–

+ + + +

–

–

+ + + +

–

–

+ + + +

–

–

+ + + +

–

–

+ + + +

–

–

+ + + +

–

–

+ + + +

dH

–

+ + + +

–

–

+ + + –

–

–

– – – –

–

–

– – – –

–

–

+ + – –

dH

–

+ + + –

–

–

– – – –

–

–

– – – –

–

–

+ + – –

dH

–

– – – –

dH

–

– – – –

00

+ + R –

dH

–

+ + R –

dH

–

+ + R –

dH

–

+ + + +

–

–

+ + + +

–

–

+ + – +

–

–

28 to 2F

24

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3
C2
C0

D8 to DF

D3
D2
D0

01

11

63

73

53

12

13

03

ROLC A
CMP A,#d8

CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir

52

←

←

AC

1

2

2

2

2

3

1

3

2

4

1

3
2
2
2
2
3
3
4
3
2
2
3

Decimal adjust for addition

1

Decimal adjust for subtraction

1

(A) ← (AL) ∀ (TL)

1

(A) ← (AL) ∀ d8

2

(A) ← (AL) ∀ (dir)

2

(A) ← (AL) ∀ ( (EP) )

1

(A) ← (AL) ∀ ( (IX) +off)

2

(A) ← (AL) ∀ (Ri)

1

(A) ← (AL) ∧ (TL)

1

(A) ← (AL) ∧ d8

2

(A) ← (AL) ∧ (dir)

2

(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

+ + – +

–

+ + + +

–

+ + + +

–

+ + + +

–

+ + + +

–

+ + + +

–

+ + + +

–

+ + + +

–

+ + R –

–

+ + R –

–

+ + R –

–

+ + R –

–

+ + R –

–

+ + R –

–

+ + R –

–

+ + R –

–

+ + R –

–

02

14

15

17

16

18 to 1F

84

94

52

54

55

57

56

58 to 5F

62

64

65

(Continued)

MB89640 Series

(Continued)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP

Mnemonic ~ # Operation TL TH AH N Z V C OP code

3

1

(A) ← (AL) ∧ ( (EP) )

4

2

(A) ← (AL) ∧ ( (IX) +off)

3

1

(A) ← (AL) ∧ (Ri)

2

1

(A) ← (AL) ∨ (TL)

2

2

(A) ← (AL) ∨ d8

3

2

(A) ← (AL) ∨ (dir)

3

1

(A) ← (AL) ∨ ( (EP) )

4

2

(A) ← (AL) ∨ ( (IX) +off)

3

1

(A) ← (AL) ∨ (Ri)

5

3

4

2

5

3

4

2

3

1

(SP) ← (SP) + 1

3

1

(SP) ← (SP) – 1

Table 4 Branch Instructions (17 instructions)

(dir) – d8
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8

–

–

–

+ + R –

–

–

–

+ + R –

–

–

–

+ + R –

–

–

–

+ + R –

–

–

–

+ + R –

–

–

–

+ + R –

–

–

–

+ + R –

–

–

–

+ + R –

–

–

–

+ + R –

–

–

–

+ + + +

–

–

–

+ + + +

–

–

–

+ + + +

–

–

–

+ + + +

–

–

–

– – – –

–

–

–

– – – –

67

66

68 to 6F

72

74

75

77

76

78 to 7F

95

97

96

98 to 9F

C1
D1

BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI

Mnemonic ~ # Operation TL TH AH N Z V C OP code

PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI

3

2

If Z = 1 then PC ← PC + rel

3

2

If Z = 0 then PC ← PC + rel

3

2

If C = 1 then PC ← PC + rel

3

2

If C = 0 then PC ← PC + rel

3

2

If N = 1 then PC ← PC + rel

3

2

If N = 0 then PC ← PC + rel

3

2

If V ∀ N = 1 then PC ← PC + rel

3

2

If V ∀ N = 0 then PC ← PC + reI

5

3

If (dir: b) = 0 then PC ← PC + rel

5

3

If (dir: b) = 1 then PC ← PC + rel

2

1

(PC) ← (A)

3

3

(PC) ← ext

6

1

Vector call

6

3

Subroutine call

3

1

(PC) ← (A),(A) ← (PC) + 1

4

1

Return from subrountine

6

1

Return form interrupt

Table 5 Other Instructions (9 instructions)

4

1

4

1

4

1

4

1

1

1

1

1

1

1

1

1

1

1

–

–

–

– – – –

–

–

–

– – – –

–

–

–

– – – –

–

–

–

– – – –

–

–

–

– – – –

–

–

–

– – – –

–

–

–

– – – –

–

–

–

– – – –

–

–

–

– + – –

–

–

–

– + – –

–

–

–

– – – –

–

–

–

– – – –

–

–

–

– – – –

–

–

–

– – – –

–

–

dH

– – – –

–

–

–

– – – –

–

–

–

Restore

–

–

–

– – – –

–

–

dH

– – – –

–

–

–

– – – –

–

–

–

– – – –

–

–

–

– – – –

–

–

–

– – – R

–

–

–

– – – S

–

–

–

– – – –

–

–

–

– – – –

FD
FC

F9

F8
FB
FA
FF
FE

B0 to B7
B8 to BF

E0

21

E8 to EF

31

F4

20

30

40
50
41
51
00
81
91
80
90

53

MB89640 Series

INSTRUCTION MAP

■

rel

rel

BC

#1

CALLV

R1

DEC

R1

INC

dir: 1,rel

BBS

dir: 1

SETB

R1,#d8

CMP

R1,#d8

MOV

A,R1

OR

A,R1

AND

A,R1

XOR

R1,A

MOV

A,R1

SUBC

A,R1

ADDC

A,R1

CMP

A,R1

9 MOV

MOVW

JMP

DECW

INCW

BBC

CLRI SETI CLRB

MOVW

MOV

POPW

PUSHW

0123456789ABCDEF

H

0 NOP SWAP RET RETI

A,PC

@A

A

A

dir: 0,rel

dir: 0

A,PS

A,ext

A

A

A,SP

MOVW

SP,A

MOVW

SP

DECW

SP

INCW

BBC

dir: 1,rel

dir: 1

CLRC SETC CLRB

PS,A

MOVW

ext,A

MOV

IX

POPW

IX

PUSHW

addr16

CALL

addr16

JMP

A

DIVU

A

1 MULU

A,IX

MOVW

IX,A

MOVW

IX

DECW

IX

INCW

BBC

dir: 2,rel

dir: 2

CLRB

A,@A

MOV

@A,T

MOV

A

OR

A

AND

A

XOR

A, T

XCH

A

SUBC

A

ADDC

A

CMP

A

2 ROLC

A,EP

MOVW

EP,A

MOVW

EP

DECW

EP

INCW

BBC

dir: 3,rel

dir: 3

CLRB

A,@A

MOVW

@A,T

MOVW

A

ORW

A

ANDW

A

XORW

A, T

XCHW

A

SUBCW

A

ADDCW

A

CMPW

A

3 RORC

A,PC

XCHW

A,#d16

MOVW

ext,A

MOVW

A,ext

MOVW

dir: 4,rel

BBC

dir: 4

DAA DAS CLRB

A,#d8

OR

A,#d8

AND

A,#d8

XOR

A,#d8

SUBC

A,#d8

ADDC

A,#d8

CMP

A,#d8

4 MOV

A,SP

XCHW

SP,#d16

MOVW

dir,A

MOVW

A,dir

MOVW

dir: 5,rel

BBC

dir: 5

CLRB

dir,#d8

CMP

dir,#d8

MOV

A,dir

OR

A,dir

AND

A,dir

XOR

dir,A

MOV

A,dir

SUBC

A,dir

ADDC

A,dir

CMP

A,dir

5 MOV

A,IX

XCHW

IX,#d16

MOVW

@IX +d,A

MOVW

A,@IX +d

MOVW

dir: 6,rel

BBC

dir: 6

CLRB

@IX +d,#d8

CMP

@IX +d,#d8

MOV

OR

A,@IX +d

AND

A,@IX +d

A,@IX +d

XOR

MOV @IX

+d,A

SUBC

A,@IX +d

ADDC

A,@IX +d

CMP

A,@IX +d

MOV

A,@IX +d

6

A,EP

XCHW

EP,#d16

MOVW

@EP,A

MOVW

A,@EP

MOVW

dir: 7,rel

BBC

dir: 7

CLRB

CMP

@EP,#d8

MOV

@EP,#d8

A,@EP

OR

A,@EP

AND

A,@EP

XOR

@EP,A

MOV

A,@EP

SUBC

A,@EP

ADDC

A,@EP

CMP

A,@EP

7 MOV

rel

BNC

#0

CALLV

R0

DEC

R0

INC

dir: 0,rel

BBS

dir: 0

SETB

R0,#d8

CMP

R0,#d8

MOV

A,R0

OR

A,R0

AND

A,R0

XOR

R0,A

MOV

A,R0

SUBC

A,R0

ADDC

A,R0

CMP

A,R0

8 MOV

L

54

rel

BP

#2

CALLV

R2

DEC

R2

INC

dir: 2,rel

BBS

dir: 2

SETB

R2,#d8

CMP

R2,#d8

MOV

A,R2

OR

A,R2

AND

A,R2

XOR

R2,A

MOV

A,R2

SUBC

A,R2

ADDC

A,R2

CMP

A,R2

A MOV

BN

#3

CALLV

R3

DEC

R3

INC

dir: 3,rel

BBS

dir: 3

SETB

R3,#d8

CMP

R3,#d8

MOV

A,R3

OR

A,R3

AND

A,R3

XOR

R3,A

MOV

A,R3

SUBC

A,R3

ADDC

A,R3

CMP

A,R3

B MOV

rel

BNZ

#4

CALLV

R4

DEC

R4

INC

dir: 4,rel

BBS

dir: 4

SETB

R4,#d8

CMP

R4,#d8

MOV

A,R4

OR

A,R4

AND

A,R4

XOR

R4,A

MOV

A,R4

SUBC

A,R4

ADDC

A,R4

CMP

A,R4

C MOV

rel

BZ

#5

CALLV

R5

DEC

R5

INC

dir: 5,rel

BBS

dir: 5

SETB

R5,#d8

CMP

R5,#d8

MOV

A,R5

OR

A,R5

AND

A,R5

XOR

R5,A

MOV

A,R5

SUBC

A,R5

ADDC

A,R5

CMP

A,R5

D MOV

rel

BGE

#6

CALLV

R6

DEC

R6

INC

dir: 6,rel

BBS

dir: 6

SETB

R6,#d8

CMP

R6,#d8

MOV

A,R6

OR

A,R6

AND

A,R6

XOR

R6,A

MOV

A,R6

SUBC

A,R6

ADDC

A,R6

CMP

A,R6

E MOV

rel

BLT

#7

CALLV

R7

DEC

R7

INC

dir: 7,rel

BBS

dir: 7

SETB

R7,#d8

CMP

R7,#d8

MOV

A,R7

OR

A,R7

AND

A,R7

XOR

R7,A

MOV

A,R7

SUBC

A,R7

ADDC

A,R7

CMP

A,R7

F MOV

MASK OPTIONS

■

No.

Specifying procedure

Pull-up resistors

P00 to P07, P10 to P17,
P30 to P37, P40 to P47,

1

P50 to P57, P60 to P67,
P70 to P74, P80 to P83

Power-on reset

2

With power-on reset
Without power-on reset

Main clock oscillation stabilization time
selection (when operating at 10 MHz)

Approx. 2

3

Approx. 2
Approx. 2
Approx. 2

F

CH: Main clock frequency

Reset pin output

4

With reset output
Without reset output

Selection either single- or dual-clock
system

5

Single clock
Dual clock

Part number

18

/FCH (Approx. 26.2 ms)

17

/FCH (Approx. 13.1 ms)

14

/FCH (Approx. 1.6 ms)

4

/FCH (Approx. 0 ms)

MB89640 Series

MB89643
MB89645
MB89646
MB89647

Specify when

ordering
masking

Selectable per pin
(P60 to P67 must be set to
without a pull-up resistor
when an A/D converter is
used. P51 and P50 are
must be set to without a
pull-up resistor when a D/A
converter is used.)

Selectable Setting possible

Selectable Setting possible

Selectable Setting possible

Selectable Setting possible

MB89P647 MB89PV640

Set with EPROM

programmer

Can be set per pin
(Only P40 to P47
and P50 to P57
are without a pull­up resistor.)

Setting not

possible

Fixed to without
pull-up resistor

Fixed to with
power-on reset

Fixed to appro x.

18

2

/FCH (Approx.

26.2 ms)

Fixed to with
reset output

Fixed to dual­clock system

ORDERING INFORMATION

■

Part number Package Remarks

MB89647PFM
MB89646PFM
MB89645PFM
MB89643PFM
MB89P647PFM

MB89647PF
MB89646PF
MB89645PF
MB89643PF
MB89P647PF

MB89PV640CF

80-pin Plastic QFP

(FPT-80P-M11)

80-pin Plastic QFP

(FPT-80P-M06)

80-pin Ceramic MQFP

(MQP-80C-P01)

55

MB89640 Series

PACKAGE DIMENSIONS

■

80-pin Plastic QFP

(FPT-80P-M11)

16.00±0.20(.630±.008)SQ

60 41

14.00±0.10(.551±.004)SQ

1.50
.059

+0.20
–0.10

+.008
–.004

61

1 PIN INDEX

80

LEAD No.

C

1994 FUJITSU LIMITED F80016S-1C-2

1

0.65(.0256)TYP

0.30±0.10

(.012±.004)

0.13(.005)

0.10(.004)

40

15.00

12.35
(.591)

(.486)

NOM

REF

21

"A"

20

M

0.127
.005

+0.05
–0.02

+.002
–.001

Details of "A" part

0.10±0.10

(.004±.004)

0.50±0.20

0 10°

(.020±.008)

(STAND OFF)

Dimensions in mm (inches)

56

80-pin Plastic QFP

(FPT-80P-M06)

MB89640 Series

23.90±0.40(.941±.016)

64 41

65

80

LEAD No.

C

1994 FUJITSU LIMITED F80010S-3C-2

20.00±0.20(.787±.008)

INDEX

0.80(.0315)TYP

18.40(.724)REF

22.30±0.40(.878±.016)

(.014±.004)

0.10(.004)

0.35±0.10

"A"

241

0.16(.006)

40

14.00±0.20

25

M

"B"

17.90±0.40
(.705±.016)(.551±.008)

Details of "A" part

0.18(.007)MAX

0.58(.023)MAX

0.25(.010)

0.30(.012)

3.35(.132)MAX

0.05(.002)MIN
(STAND OFF)

12.00(.472)
REF

0.15±0.05(.006±.002)

Details of "B" part

16.30±0.40
(.642±.016)

0 10°

0.80±0.20

(.031±.008)

Dimensions in mm (inches)

57

MB89640 Series

80-pin Ceramic MQFP

(MQP-80C-P01)

18.70(.736)TYP

16.30±0.33

INDEX AREA

1.27±0.13

(.050±.005)

22.30±0.33
(.878±.013)

24.70(.972)
TYP

C

1994 FUJITSU LIMITED M80001SC-4-2

0.30(.012)
TYP

INDEX

1.27±0.13

(.050±.005)

(.642±.013)

15.58±0.20

(.613±.008)

0.30(.012)TYP

7.62(.300)TYP

9.48(.373)TYP

11.68(.460)TYP

4.50(.177)
TYP

12.02(.473)

10.16(.400)
TYP

6.00(.236)
TYP

0.15±0.05

(.006±.002)

TYP

14.22(.560)

8.70(.343)
MAX

18.12±0.20
(.713±.008)

TYP

1.50(.059)TYP

1.00(.040)TYP

0.40±0.10

(.016±.004)

1.50(.059)
TYP

1.00(.040)

1.20
.047

TYP

+0.40
–0.20

+.016
–.008

12.00(.472)TYP

0.80±0.25

INDEX AREA

0.40±0.10

(.016±.004)

(.0315±.010)

0.80±0.25

(.0315±.010)

18.40(.724)
REF

+0.40

1.20

–0.20
+.016

.047

–.008

Dimensions in mm (inches)

58

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka,
Nakahara-ku, Kawasaki-shi,
Kanagawa 211-8588, Japan
Tel: [phone]
Fax: [phone]

http://www.fujitsu.co.jp/

North and South America

FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: [phone]
Fax: [phone]

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: [phone]
Fax: [phone]

http://www.fujitsumicro.com/

Europe

FUJITSU MICROELECTRONICS EUR OPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: [phone]
Fax: [phone]

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD .
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: [phone]
Fax: [phone]

http://www.fmap.com.sg/

Korea

FUJITSU MICROELECTRONICS K OREA LTD .
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: [phone]
Fax: [phone]

MB89640 Series

All Rights Reserved.

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.

The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.

FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.

Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.

F0005
 FUJITSU LIMITED Printed in Japan

59