Freescale MCF5249 DATA SHEET

Freescale Semiconductor, Inc.
MCF5249
ColdFire® Integrated Microprocessor
User’s Manual
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MCF5249UM/D
Rev. 4.0, 10/2003
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Document Revision History

Document Revision History
Rev.
No.
1.0 10/2002 Chapter 21, Electrical Specifications
2.0 05/2003 Chapter 21, Electrical Specifications
3.0 08/2003 Chapter 4, QSPISEL bit
4.0 10/29/03 Chapter 21, Electrical Specifications
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2 MCF5249UM MOTOROLA
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TABLE OF CONTENTS

Paragraph Page Number Number
SECTION 1
INTRODUCTION 1
1.1 MCF5249 Overview .............................................................................................................1-1
1.2 MCF5249 Feature Introduction ............................................................................................1-1
1.3 MCF5249 Block Diagram .....................................................................................................1-2
1.4 MCF5249 Feature Details ....................................................................................................1-3
1.5 160 MAPBGA Ball Assignments ..........................................................................................1-5
1.6 MCF5249 Functional Overview ...........................................................................................1-6
1.6.1 ColdFire V2 Core ............................................................................................................1-6
1.6.2 DMA Controller ...............................................................................................................1-6
1.6.3 Enhanced Multiply and Accumulate Module (EMAC) .....................................................1-6
1.6.4 Instruction Cache ............................................................................................................1-6
1.6.5 Internal 96-KByte SRAM ................................................................................................1-6
1.6.6 DRAM Controller ............................................................................................................1-7
1.6.7 System Interface .............................................................................................................1-7
1.6.8 External Bus Interface ....................................................................................................1-7
1.6.9 Serial Audio Interfaces ...................................................................................................1-7
1.6.10 IEC958 Digital Audio Interfaces ......................................................................................1-7
1.6.11 Audio Bus .......................................................................................................................1-7
1.6.12 CD-ROM Encoder/Decoder ............................................................................................1-8
1.6.13 Dual UART Module .........................................................................................................1-8
1.6.14 Queued Serial Peripheral Interface QSPI .......................................................................1-8
1.6.15 Timer Module ..................................................................................................................1-8
1.6.16 IDE and SmartMedia Interfaces .....................................................................................1-9
1.6.17 Analog/Digital Converter (ADC) ......................................................................................1-9
1.6.18 Flash Memory Card Interface .........................................................................................1-9
1.6.19 I
1.6.20 Chip-Selects ...................................................................................................................1-9
1.6.21 GPIO Interface ................................................................................................................1-9
1.6.22 Interrupt Controller ..........................................................................................................1-9
1.6.23 JTAG ............................................................................................................................1-10
1.6.24 System Debug Interface ...............................................................................................1-10
1.6.25 Crystal and On-chip PLL ..............................................................................................1-10
2.1 Introduction ..........................................................................................................................2-1
2.2 GPIO ....................................................................................................................................2-4
2.3 MCF5249 BUS SIGNALS ....................................................................................................2-4
2.3.1 ADDRESS BUS ..............................................................................................................2-4
2.3.2 READ-WRITE CONTROL ..............................................................................................2-4
2.3.3 OUTPUT ENABLE ..........................................................................................................2-5
2.3.4 Data Bus .........................................................................................................................2-5
2.3.5 Transfer Acknowledge ....................................................................................................2-5
2.4 SDRAM Controller Signals ..................................................................................................2-5
2.5 CHIP SELECTS ...................................................................................................................2-5
2.6 ISA bus ................................................................................................................................2-6
2.7 bus buffer signals .................................................................................................................2-6
2
C Module ......................................................................................................................1-9
SECTION 2
SIGNAL DESCRIPTION
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2.8 I2C Module Signals ..............................................................................................................2-6
2.9 Serial Module Signals ..........................................................................................................2-6
2.10 Timer Module Signals ..........................................................................................................2-7
2.11 Serial Audio Interface Signals ..............................................................................................2-7
2.12 Digital Audio Interface Signals .............................................................................................2-9
2.13 Subcode interface ................................................................................................................2-9
2.14 Analog to Digital Converter (ADC) .......................................................................................2-9
2.15 Secure Digital/ MemoryStick card Interface .......................................................................2-10
2.16 Queued Serial Peripheral Interface (QSPI) .......................................................................2-10
2.17 Crystal Trim .......................................................................................................................2-11
2.18 Clock Out ...........................................................................................................................2-11
2.19 Debug and Test Signals ....................................................................................................2-11
2.19.1 Test Mode .....................................................................................................................2-11
2.19.2 High Impedance ...........................................................................................................2-11
2.19.3 Processor Clock Output ................................................................................................2-11
2.19.4 Debug Data ..................................................................................................................2-11
2.19.5 Processor Status ..........................................................................................................2-11
2.20 BDM/JTAG Signals ............................................................................................................2-12
2.20.1 Test Clock .....................................................................................................................2-12
2.20.2 Test Reset/Development Serial Clock ..........................................................................2-12
2.20.3 Test Mode Select/Break Point ......................................................................................2-13
2.20.4 Test Data Input/Development Serial Input ....................................................................2-13
2.20.5 Test Data Output/Development Serial Output ..............................................................2-13
2.21 Clock and Reset signals ....................................................................................................2-14
2.21.1 Reset In ........................................................................................................................2-14
2.21.2 System Bus input ..........................................................................................................2-14
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SECTION 3
COLDFIRE CORE
3.1 Processor Pipelines .............................................................................................................3-1
3.2 Processor Register Description ...........................................................................................3-2
3.2.1 User Programming Model ...............................................................................................3-2
3.2.1.1 Data Registers (D0–D7) ............................................................................................3-2
3.2.1.2 Address Registers (A0–A6) .......................................................................................3-2
3.2.1.3 Stack Pointer (A7,SP) ................................................................................................3-2
3.2.1.4 Program Counter (PC) ...............................................................................................3-3
3.2.1.5 Condition Code Register (CCR) ................................................................................3-3
3.2.2 Enhanced Multiply Accumulate Module (EMAC) User Programming Model ..................3-4
3.2.2.1 EMAC Instruction Set Summary ................................................................................3-4
3.2.3 Supervisor Programming Model .....................................................................................3-5
3.2.3.1 Status Register (SR) ..................................................................................................3-6
3.2.3.2 Vector Base Register (VBR) ......................................................................................3-6
3.3 Exception Processing Overview ..........................................................................................3-7
3.4 Exception Stack Frame Definition ........................................................................................3-8
3.5 Processor Exceptions ........................................................................................................3-10
3.5.1 Access Error Exception ................................................................................................3-10
3.5.2 Address Error Exception ...............................................................................................3-10
3.5.3 Illegal Instruction Exception ..........................................................................................3-10
3.5.4 Divide By Zero ..............................................................................................................3-10
3.5.5 Privilege Violation .........................................................................................................3-11
3.5.6 Trace Exception ............................................................................................................3-11
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3.5.7 Debug Interrupt .............................................................................................................3-11
3.5.8 RTE and Format Error Exceptions ................................................................................3-11
3.5.9 TRAP Instruction Exceptions ........................................................................................3-12
3.5.10 Interrupt Exception .......................................................................................................3-12
3.5.11 Fault-on-Fault Halt ........................................................................................................3-12
3.5.12 Reset Exception ...........................................................................................................3-12
3.6 Instruction Execution Timing ..............................................................................................3-12
3.6.1 Timing Assumptions .....................................................................................................3-13
3.6.2 MOVE Instruction Execution Times ..............................................................................3-13
3.7 Standard One Operand Instruction Execution Times ........................................................3-15
3.8 Standard Two Operand Instruction Execution Times ........................................................3-16
3.9 Miscellaneous Instruction Execution Times .......................................................................3-18
3.10 Branch Instruction Execution Times ..................................................................................3-19
Table of Contents
SECTION 4
PHASE-LOCKED LOOP AND CLOCK DIVIDERS
4.1 PLL Features .......................................................................................................................4-1
4.2 PLL Programming ................................................................................................................4-2
4.2.1 PLL Operation ................................................................................................................4-4
4.2.2 PLL Lock-in Time ............................................................................................................4-4
4..2.3 PLL Electrical Limits .......................................................................................................4-4
4.3 Audio Clock Generation .......................................................................................................4-5
4.4 Reduced Power Mode .........................................................................................................4-6
4.5 Recommended Settings ......................................................................................................4-6
SECTION 5
INSTRUCTION CACHE
5.1 Instruction Cache Features ..................................................................................................5-1
5.2 Instruction Cache Physical Organization .............................................................................5-1
5.3 Instruction Cache Operation ................................................................................................5-2
5.3.1 Interaction with Other Modules .......................................................................................5-2
5.3.2 Memory Reference Attributes .........................................................................................5-3
5.3.3 Cache Coherency and Invalidation .................................................................................5-3
5.3.4 Reset ..............................................................................................................................5-3
5.3.5 Cache Miss Fetch Algorithm/Line Fills ............................................................................5-3
5.4 Instruction Cache Programming Model ...............................................................................5-5
5.4.1 Instruction Cache Registers Memory Map ......................................................................5-5
5.4.2 Instruction Cache Register .............................................................................................5-6
5.4.2.1 Cache Control Register .............................................................................................5-6
5.4.2.2 Access Control Registers ..........................................................................................5-8
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SECTION 6
STATIC RAM (SRAM)
6.1 SRAM Features ...................................................................................................................6-1
6.2 SRAM Operation ..................................................................................................................6-1
6.3 SRAM Programming Model .................................................................................................6-1
6.3.1 SRAM Base Address Register .......................................................................................6-1
6.3.2 SRAM Initialization .........................................................................................................6-4
6.3.3 SRAM Initialization Code ................................................................................................6-4
6.3.4 Power Management .......................................................................................................6-4
SECTION 7
SYNCHRONOUS DRAM CONTROLLER MODULE
7.1 DRAM Features ...................................................................................................................7-1
7.1.1 Definitions .......................................................................................................................7-1
7.1.2 Block Diagram and Major Components ..........................................................................7-1
7.2 DRAM Controller Operation .................................................................................................7-2
7.2.1 DRAM Controller Registers ............................................................................................7-2
7.3 Synchronous Operation .......................................................................................................7-3
7.3.1 DRAM Controller Signals in Synchronous Mode ............................................................7-4
7.3.2 Synchronous Register Set ..............................................................................................7-5
7.3.2.1 DRAM Control Register (DCR) (Synchronous Mode) ...............................................7-5
7.3.2.2 DRAM Address and Control (DACR0/DACR1) (Synchronous Mode) .......................7-7
7.3.2.3 DRAM Controller Mask Registers (DMR0/DMR1) .....................................................7-9
7.3.3 General Synchronous Operation Guidelines ................................................................7-10
7.3.3.1 Address Multiplexing ...............................................................................................7-10
7.3.3.2 Interfacing Example .................................................................................................7-11
7.3.3.3 Burst Page Mode .....................................................................................................7-11
7.3.3.4 Continuous Page Mode ...........................................................................................7-13
7.3.3.5 Auto-Refresh Operation ...........................................................................................7-15
7.3.3.6 Self-Refresh Operation ............................................................................................7-16
7.3.4 Initialization Sequence ..................................................................................................7-17
7.3.4.1 Mode Register Settings ...........................................................................................7-17
7.4 SDRAM Example ...............................................................................................................7-18
7.4.1 SDRAM Interface Configuration ...................................................................................7-18
7.4.2 DCR Initialization ..........................................................................................................7-19
7.4.3 DACR Initialization ........................................................................................................7-19
7.4.4 DMR Initialization ..........................................................................................................7-21
7.4.5 Mode Register Initialization ..........................................................................................7-22
7.4.6 Initialization Code .........................................................................................................7-23
SECTION 8
BUS OPERATION
8.1 Bus Features .......................................................................................................................8-1
8.2 Bus And Control Signals ......................................................................................................8-1
8.2.1 Address Bus ...................................................................................................................8-1
8.2.2 Read/Write control ..........................................................................................................8-2
8.2.3 Transfer Acknowledge (TA) ............................................................................................8-2
8.2.4 Data Bus .........................................................................................................................8-2
8.2.5 Chip Selects ...................................................................................................................8-3
8.2.6 Output Enable .................................................................................................................8-3
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8.3 Clock and Reset Signals ......................................................................................................8-3
8.3.1 Reset In ..........................................................................................................................8-4
8.3.2 System Bus Clock Output ...............................................................................................8-4
8.4 Bus Characteristics ..............................................................................................................8-4
8.5 Data Transfer Operation ......................................................................................................8-5
8.5.1 Bus Cycle Execution .......................................................................................................8-6
8.5.2 Read Cycle .....................................................................................................................8-7
8.5.3 Write Cycle .....................................................................................................................8-8
8.5.4 Back-to-Back Bus Cycles .............................................................................................8-10
8.5.5 Burst Cycles .................................................................................................................8-11
8.5.5.1 Line Transfers ..........................................................................................................8-11
8.5.5.2 Line Read Bus Cycles .............................................................................................8-11
8.5.5.3 Line Write Bus Cycles .............................................................................................8-12
8.6 Misaligned Operands .........................................................................................................8-14
8.7 Reset Operation .................................................................................................................8-15
8.7.1 Software Watchdog Reset ............................................................................................8-16
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Table of Contents
SECTION 9
SYSTEM INTEGRATION MODULE
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9.1 SIM Introduction ...................................................................................................................9-1
9.1.1 SIM Features ..................................................................................................................9-1
9.2 Programming Model ............................................................................................................9-1
9.2.1 SIM Register Memory Map .............................................................................................9-1
9.3 SIM Programming and Configuration ..................................................................................9-3
9.3.1 Module Base Address Registers ....................................................................................9-3
9.3.2 Device ID ........................................................................................................................9-5
9.3.3 Interrupt Controller ..........................................................................................................9-6
9.4 Interrupt Interface ................................................................................................................9-6
9.4.1 Primary controller Interrupt Registers .............................................................................9-6
9.4.1.1 Interrupt Mask Register .............................................................................................9-9
9.4.1.2 Interrupt Pending Register .......................................................................................9-10
9.4.2 Secondary Interrupt Controller Registers .....................................................................9-11
9.4.2.1 Interrupt Level Selection ..........................................................................................9-11
9.4.2.2 Interrupt Vector Generation .....................................................................................9-12
9.4.2.3 Spurious Vector Register .........................................................................................9-12
9.4.2.4 Secondary Interrupt Sources ...................................................................................9-12
9.4.3 Software interrupts .......................................................................................................9-15
9.5 System Protection And Reset Status .................................................................................9-15
9.5.1 Reset Status Register ...................................................................................................9-15
9.5.2 Software Watchdog Timer ............................................................................................9-16
9.5.2.1 System Protection Control Register ........................................................................9-18
9.5.2.2 Software Watchdog Interrupt Vector Register .........................................................9-19
9.5.2.3 Software Watchdog Service Register ......................................................................9-20
9.6 CPU STOP Instruction .......................................................................................................9-20
9.7 MCF5249 Bus Arbitration Control ......................................................................................9-20
9.7.1 Default Bus Master Park Register ................................................................................9-20
9.7.1.1 Internal Arbitration Operation ..................................................................................9-20
9.7.1.2 PARK Register Bit Configuration .............................................................................9-21
9.8 General Purpose I/Os ........................................................................................................9-23
9.8.1 General Purpose Inputs ................................................................................................9-23
9.8.1.1 General Purpose Input Interrupts ............................................................................9-25
9.8.2 General Purpose Outputs .............................................................................................9-26
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SECTION 10
CHIP-SELECT MODULE
10.1 Introduction ........................................................................................................................10-1
10.1.1 Chip Select Features ....................................................................................................10-1
10.2 Chip-Select Signals ...........................................................................................................10-1
10.2.1 Chip Selects .................................................................................................................10-1
10.2.1.1 CS0 .........................................................................................................................10-1
10.2.1.2 CS1/GPIO1 .............................................................................................................10-1
10.2.1.3 CS2/IDE-DIOR/GPIO13 and IDE-DIOW/GPIO14 ...................................................10-1
10.2.1.4 CS3/SRE/GPIO11 and SWE/GPIO12 .....................................................................10-2
10.2.2 Output Enable OE/gpio9 ...............................................................................................10-2
10.2.3 buffer enable signals - bufenb1 and bufenb2 ...............................................................10-2
10.2.4 IORDY - bus termination signal ....................................................................................10-2
10.3 MCF5249Chip-Select Operation ........................................................................................10-2
10.3.1 Chip-Select Module ......................................................................................................10-2
10.3.1.1 General Chip Select Operation ................................................................................10-3
10.3.1.1.1 Port Sizing ..........................................................................................................10-4
10.3.2 Global Chip-Select Operation .......................................................................................10-4
10.4 Programming Model ..........................................................................................................10-4
10.4.1 Chip-Select Registers Memory Map .............................................................................10-4
10.4.2 Chip Select Module Registers ......................................................................................10-6
10.4.2.1 Chip Select Address Register ..................................................................................10-6
10.4.2.2 Chip Select Mask Register ......................................................................................10-6
10.4.2.3 Chip Select Control Register ...................................................................................10-8
10.4.2.4 Code example .......................................................................................................10-10
SECTION 11
TIMER MODULE
11.1 Timer Module Overview .....................................................................................................11-1
11.2 Timer Features ..................................................................................................................11-1
11.3 Timer Signals .....................................................................................................................11-1
11.3.1 Timer Inputs ..................................................................................................................11-1
11.3.2 Timer Outputs ...............................................................................................................11-1
11.4 General-Purpose Timer Units ............................................................................................11-2
11.4.1 Selecting the Prescaler .................................................................................................11-3
11.4.2 Capture Mode ...............................................................................................................11-3
11.4.3 Configuring the Timer for Reference Compare .............................................................11-3
11.4.4 Configuring the Timer for Output Mode ........................................................................11-3
11.5 General-Purpose Timer Registers .....................................................................................11-3
11.5.1 Timer Mode Registers (TMR0, TMR1) .........................................................................11-4
11.5.2 Timer Reference Registers (TRR0, TRR1) ...................................................................11-5
11.5.3 Timer Capture Registers (TCR0, TCR1) ......................................................................11-5
11.5.4 Timer Counters (TCN0, TCN1) .....................................................................................11-6
11.5.5 Timer Event Registers (TER0, TER1) ..........................................................................11-6
11.5.6 Timer Initialization Example Code ................................................................................11-7
11.5.6.1 Timer 0 (Timer Mode Register) ...............................................................................11-7
11.5.6.2 Timer 0 (Timer Reference Register 0) .....................................................................11-8
11.5.6.3 Timer 1 (Timer Mode Register 1) ............................................................................11-8
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Table of Contents
SECTION 12
ANALOG TO DIGITAL CONVERTER (ADC)
12.1 ADC Overview ...................................................................................................................12-1
12.2 ADC Functionality ..............................................................................................................12-2
SECTION 13
IDE AND FLASHMEDIA INTERFACE
13.1 IDE and SmartMedia Overview .........................................................................................13-1
13.1.1 Buffer enables bufenb1, bufenB2, and associated logic. .............................................13-2
13.1.2 Generation of IDE-DIOR, IDE-DIOW, SRE, SWE ........................................................13-4
13.1.3 Cycle termination on CS2, CS3 (DIOR, DIOW, SRE, SWE) ........................................13-5
13.2 SmartMedia Interface Setup ..............................................................................................13-6
13.2.1 SmartMedia timing ........................................................................................................13-7
13.3 Setting Up The IDE Interface .............................................................................................13-8
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13.3.1 IDE timing diagram .......................................................................................................13-8
13.4 FlashMedia Interface .......................................................................................................13-10
13.4.1 FlashMedia Interface Registers ..................................................................................13-10
13.4.1.1 FlashMedia Clock Generation and Configuration ..................................................13-11
13.4.2 FlashMedia Interface Operation .................................................................................13-12
13.4.2.1 FlashMedia Command Registers in MemoryStick Mode .......................................13-13
13.4.2.2 FlashMedia Command Register 1 in Secure Digital Mode ....................................13-13
13.4.2.3 FLASHMEDIA COMMAND REGISTER 2 in Secure Digital Mode ........................13-14
13.4.3 FlashMedia Data Register ..........................................................................................13-15
13.4.3.1 FlashMedia Status Register ..................................................................................13-15
13.4.4 FlashMedia Interrupt Interface ....................................................................................13-15
13.4.5 FlashMedia Interface Operation in MemoryStick Mode ..............................................13-16
13.4.5.1 Reading Data From the MemoryStick ...................................................................13-17
13.4.5.2 Writing Data to the MemoryStick ...........................................................................13-18
13.4.5.3 Interrupt From MemoryStick ..................................................................................13-19
13.4.6 FlashMedia interface Operation in Secure Digital (SD) mode ....................................13-20
13.4.6.1 Sent Command To Card ........................................................................................13-20
13.4.6.2 Write Data To Card ................................................................................................13-21
13.4.7 Commonly used commands in SD mode ...................................................................13-23
13.4.7.1 Send Command To Card (No Data) ......................................................................13-23
13.4.7.2 Send Command To Card (Receive Multiple Data Blocks and Status) ..................13-24
13.4.7.3 Send Command To Card (Write Multiple Data Blocks) .........................................13-25
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SECTION 14
DMA CONTROLLER MODULE
14.1 DMA Features ....................................................................................................................14-2
14.2 DMA Signal Description .....................................................................................................14-2
14.2.1 DMA Request ...............................................................................................................14-2
14.3 DMA Module Overview ......................................................................................................14-2
14.4 DMA Programming Model .................................................................................................14-3
14.4.1 REQUEST source selection .........................................................................................14-5
14.4.2 Source Address Register ..............................................................................................14-8
14.4.3 FLASHmEDIA DATA RegisterS ...................................................................................14-9
14.4.4 Byte Count Register .....................................................................................................14-9
14.4.5 DMA Control Register .................................................................................................14-10
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14.4.6 DMA Status Register ..................................................................................................14-13
14.4.7 DMA Interrupt Vector Register ...................................................................................14-15
14.5 Transfer Request Generation ..........................................................................................14-15
14.5.1 Cycle-Steal Mode .......................................................................................................14-15
14.5.2 Continuous Mode .......................................................................................................14-15
14.6 Data Transfer Modes .......................................................................................................14-16
14.6.1 Dual-Address Transaction ..........................................................................................14-16
14.6.1.1 Dual-Address Read ...............................................................................................14-16
14.6.1.2 Dual-Address Write ...............................................................................................14-16
14.7 DMA Transfer Functional Description .............................................................................14-16
14.7.1 Channel Initialization and Startup ...............................................................................14-17
14.7.1.1 Channel Prioritization ............................................................................................14-17
14.7.1.2 Programming the DMA ..........................................................................................14-17
14.7.2 Data Transfer ..............................................................................................................14-18
14.7.2.1 Periphery Request Operation ................................................................................14-18
14.7.2.2 Auto Alignment ......................................................................................................14-18
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14.7.2.3 Bandwidth Control .................................................................................................14-19
14.7.3 Channel Termination ..................................................................................................14-19
14.7.3.1 Error Conditions .....................................................................................................14-19
14.7.3.2 Interrupts ...............................................................................................................14-19
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SECTION 15
UART MODULES
15.1 Module Overview ...............................................................................................................15-1
15.1.1 Serial Communication Channel ....................................................................................15-2
15.1.2 Baud-Rate Generator/Timer .........................................................................................15-2
15.1.3 Interrupt Control Logic ..................................................................................................15-2
15.2 UART Module Signal Definitions .......................................................................................15-3
15.2.1 Transmitter Serial Data Output .....................................................................................15-3
15.2.2 Receiver Serial Data Input ............................................................................................15-3
15.2.3 Request-To-Send .........................................................................................................15-4
15.2.4 Clear-To-Send ..............................................................................................................15-4
15.3 Operation ...........................................................................................................................15-4
15.3.1 Baud-Rate Generator/Timer .........................................................................................15-4
15.3.2 Transmitter and Receiver Operating Modes .................................................................15-5
15.3.2.1 Transmitter ..............................................................................................................15-5
15.3.2.2 Receiver ..................................................................................................................15-7
15.3.2.3 Receiver FIFO .........................................................................................................15-8
15.3.3 Looping Modes .............................................................................................................15-9
15.3.3.1 Automatic Echo Mode .............................................................................................15-9
15.3.3.2 Local Loopback Mode .............................................................................................15-9
15.3.3.3 Remote Loopback Mode .......................................................................................15-10
15.3.4 Multidrop Mode ...........................................................................................................15-10
15.3.5 Bus Operation .............................................................................................................15-12
15.3.5.1 Read Cycles ..........................................................................................................15-12
15.3.5.2 Write Cycles ..........................................................................................................15-12
15.3.5.3 Interrupt Acknowledge Cycles ...............................................................................15-12
15.4 Register Description and Programming ...........................................................................15-12
15.4.1 Register Description ...................................................................................................15-12
15.4.1.1 Mode Register 1 (UMR1n) .....................................................................................15-13
15.4.1.2 Mode Register 2 (UMR2n) .....................................................................................15-15
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15.4.1.3 Status Registers (USRn) .......................................................................................15-18
15.4.1.4 Clock-Select Registers (USCRn) ...........................................................................15-19
15.4.1.5 Command Registers (UCRn) .................................................................................15-20
15.4.1.6 Miscellaneous Commands ....................................................................................15-20
15.4.1.6.1 Reset Mode Register Pointer ...........................................................................15-21
15.4.1.6.2 Reset Receiver .................................................................................................15-21
15.4.1.6.3 Reset Transmitter .............................................................................................15-21
15.4.1.6.4 Reset Error Status ............................................................................................15-21
15.4.1.6.5 Reset Break-Change Interrupt .........................................................................15-21
15.4.1.6.6 Start Break .......................................................................................................15-21
15.4.1.6.7 Stop Break ........................................................................................................15-21
15.4.1.7 Transmitter Commands .........................................................................................15-21
15.4.1.7.1 No Action Taken ...............................................................................................15-22
15.4.1.7.2 Transmitter Enable ...........................................................................................15-22
15.4.1.7.3 Transmitter Disable ..........................................................................................15-22
15.4.1.7.4 Do Not Use .......................................................................................................15-22
15.4.1.8 Receiver Commands .............................................................................................15-22
15.4.1.8.1 No Action Taken ...............................................................................................15-22
15.4.1.8.2 Receiver Enable ...............................................................................................15-22
15.4.1.8.3 Receiver Disable ..............................................................................................15-23
15.4.1.8.4 Do Not Use .......................................................................................................15-23
15.4.1.9 Receiver Buffer Registers (UBRn) .........................................................................15-23
15.4.1.10 Transmitter Buffer Registers (UTBn) .....................................................................15-23
15.4.1.11 Input Port Change Registers UIPCRn) ..................................................................15-24
15.4.1.12 Auxiliary Control Registers (UACRn) .....................................................................15-24
15.4.1.13 Interrupt Status Registers (UISRn) ........................................................................15-25
15.4.1.14 Interrupt Mask Registers UIMRn) ..........................................................................15-26
15.4.1.15 Timer Upper Preload Register (UBG1n) ................................................................15-27
15.4.1.16 Timer Upper Preload Register 2 (UBG2n) .............................................................15-27
15.4.1.17 Interrupt Vector Registers (UIVRn) ........................................................................15-27
15.4.1.18 Input Port Registers (UIPn) ...................................................................................15-28
15.4.1.19 Output Port Data Registers (UOP1n) ....................................................................15-28
15.4.2 Programming ..............................................................................................................15-29
15.4.2.1 UART Module Initialization ....................................................................................15-29
15.4.2.2 I/O Driver Example ................................................................................................15-29
15.4.1.3 Interrupt Handling ..................................................................................................15-29
15.5 UART Module Initialization Sequence .............................................................................15-30
Table of Contents
SECTION 16
QUEUED SERIAL PERIPHERAL INTERFACE (QSPI) MODULE
16.1 Overview ............................................................................................................................16-1
16.2 Features .............................................................................................................................16-1
16.3 Module Description ............................................................................................................16-1
16.3.1 Interface and Pins .........................................................................................................16-1
16.3.2 Internal Bus Interface ...................................................................................................16-2
16.4 Operation ...........................................................................................................................16-3
16.4.1 QSPI RAM ....................................................................................................................16-3
16.4.1.1 Transmit RAM ..........................................................................................................16-5
16.4.1.2 Receive RAM ...........................................................................................................16-5
16.4.1.3 Command RAM .......................................................................................................16-5
16.4.2 Baud Rate Selection .....................................................................................................16-6
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16.4.3 Transfer Delays ............................................................................................................16-6
16.4.4 Transfer Length ............................................................................................................16-7
16.4.5 Data Transfer ................................................................................................................16-7
16.5 Programming Model ..........................................................................................................16-8
16.5.1 QSPI Mode Register (QMR) .........................................................................................16-8
16.5.2 QSPI Delay Register (QDLYR) ...................................................................................16-10
16.5.3 QSPI Wrap Register (QWR) .......................................................................................16-10
16.5.4 QSPI Interrupt Register (QIR) ....................................................................................16-11
16.5.5 QSPI Address Register (QAR) ...................................................................................16-12
16.5.6 QSPI Data Register (QDR) .........................................................................................16-13
16.5.7 Command RAM Registers (QCR0–QCR15) ...............................................................16-13
16.5.8 Programming Example ...............................................................................................16-15
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SECTION 17
AUDIO FUNCTIONS
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17.1 Audio Interface Overview ...................................................................................................17-1
17.1.1 Audio Interface Structure ..............................................................................................17-2
17.1.1.1 Audio Interrupt Mask and Interrupt Status Registers ...............................................17-3
17.2 Serial Audio Interface (IIS/EIAJ) ........................................................................................17-5
17.2.1 IIS/EIAJ Transmitter Descriptions .................................................................................17-9
17.2.2 IIS/EIAJ Transmitter Interrupts .....................................................................................17-9
17.2.3 IIS/EIAJ Receiver Descriptions .....................................................................................17-9
17.3 Digital Audio Interface (EBU) ...........................................................................................17-10
17.3.1 IEC958 Receive Interface ...........................................................................................17-13
17.3.1.1 Audio Data Reception ............................................................................................17-13
17.3.1.2 Control Channel Reception ...................................................................................17-13
17.3.1.3 Control Channel Interrupt (IEC958 “C” Channel New Frame) ...............................17-13
17.3.1.4 Validity Flag Reception ..........................................................................................17-13
17.3.1.5 IEC958 Exception Definition ..................................................................................17-14
17.3.1.6 EBU Extracted Clock .............................................................................................17-14
17.3.1.7 Reception of User Channel and CD-subcode Over IEC958 Receiver ..................17-14
17.3.1.8 U and Q Receive Register Interrupts .....................................................................17-16
17.3.1.9 Behavior of User Channel Receive Interface (CD Data) .......................................17-16
17.3.1.10 Behavior of User Channel Receive Interface (non-CD data) .................................17-18
17.3.2 IEC958 Transmit Interface ..........................................................................................17-18
17.3.2.1 Transmit “C” Channel ............................................................................................17-18
17.3.2.2 IEC958 Transmitter Exception Conditions .............................................................17-19
17.3.2.3 IEC958-3 Ed2 and Tech 3250-E Standards Compliance ......................................17-19
17.3.2.4 Transmission of U-Channel and CD Subcode Data ..............................................17-20
17.3.3 CD Subcode Interrupts ...............................................................................................17-21
17.3.3.1 Free Running Counter Synchronization ................................................................17-22
17.3.3.2 Controlling the SFSY Sync Position ......................................................................17-22
17.3.4 Inserting CD User Channel Data Into IEC958 Transmit Data .....................................17-22
17.4 Processor Interface Overview ..........................................................................................17-23
17.4.1 Data Exchange Register Descriptions ........................................................................17-23
17.4.2 Data Exchange Register Overview .............................................................................17-24
17.4.2.1 Data In Selection ...................................................................................................17-25
17.4.3 PDIR and PDOR Field Formatting ..............................................................................17-27
17.4.4 Overrun and Underrun with PDIR and PDOR Registers ............................................17-27
17.4.5 Automatic Resynchronization of FIFOs ......................................................................17-28
17.4.6 Audio Interrupts ..........................................................................................................17-30
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17.4.6.1 AudioTick Interrupts ...............................................................................................17-30
17.4.6.2 PDIR1, PDIR2, and PDIR3, Exceptions ................................................................17-30
17.4.6.3 PDOR1, PDOR2, and PDOR3 Exceptions ............................................................17-30
17.4.6.4 Audio Interrupt Routines and Timing .....................................................................17-32
17.4.7 CD-ROM Block Encoder and Decoder .......................................................................17-33
17.4.7.1 CD-ROM Decoder Interrupts .................................................................................17-35
17.4.7.2 CD-ROM Encoder Interrupts .................................................................................17-36
17.5 DMA Channel Interaction .................................................................................................17-36
17.6 Phase/Frequency Determination and Xtrim Function ......................................................17-37
17.6.1 Incoming Source Frequency Measurement ................................................................17-37
17.6.1.1 Filtering for the Discrete Time Oscillator ...............................................................17-40
17.6.2 XTRIM Option - Locking Xtal Clock to Incoming Signal ..............................................17-40
17.6.3 XTRIM Internal Logic ..................................................................................................17-40
17.7 Audio Interface Memory Map ...........................................................................................17-41
Table of Contents
SECTION 18
I2C MODULES
18.1 I2C Overview ......................................................................................................................18-1
18.2 I
18.3 I
18.4 I
18.4.1 START Signal ...............................................................................................................18-3
18.4.2 Slave Address Transmission ........................................................................................18-3
18.4.3 Data Transfer ................................................................................................................18-4
18.4.4 Repeated START Signal ..............................................................................................18-4
18.4.5 STOP Signal .................................................................................................................18-4
18.4.6 Arbitration Procedure ....................................................................................................18-4
18.4.7 Clock Synchronization ..................................................................................................18-4
18.4.8 Handshaking .................................................................................................................18-5
18.4.9 Clock Stretching ...........................................................................................................18-5
18.5 Programming Model ..........................................................................................................18-5
18.5.1 I
18.5.2 I
18.5.3 I
18.5.4 I
18.5.5 I
18.6 I
18.6.1 Initialization Sequence ................................................................................................18-12
18.6.2 Generation of START .................................................................................................18-12
18.6.3 Post-Transfer Software Response .............................................................................18-13
18.6.4 Slave Mode .................................................................................................................18-14
18.6.5 Arbitration Lost ...........................................................................................................18-15
2
C Interface Features .......................................................................................................18-1
2
C System Configuration ..................................................................................................18-2
2
C Protocol .......................................................................................................................18-3
2
C Address Registers (MADR) ....................................................................................18-6
2
C Frequency Divider Registers (MFDR) ....................................................................18-6
2
C Control Registers (MBCR) ......................................................................................18-8
2
C Status Registers (MBSR) .....................................................................................18-10
2
C Data I/O Registers (MBDR) ..................................................................................18-11
2
C Programming Examples ............................................................................................18-12
SECTION 19
DEBUG SUPPORT
19.1 Breakpoint (BKPT) .............................................................................................................19-1
19.1.1 Debug Support Signals ................................................................................................19-1
19.1.2 Debug Data (DDATA[3:0]) ............................................................................................19-1
19.1.3 Development Serial Clock (DSCLK) .............................................................................19-2
19.1.4 Development Serial Input (DSI) ....................................................................................19-2
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19.1.5 Development Serial Output (DSO) ...............................................................................19-2
19.1.6 Processor Status (PST[3:0]) .........................................................................................19-2
19.1.7 Processor Status Clock (PSTCLK) ...............................................................................19-3
19.2 Real-Time Trace Support ..................................................................................................19-4
19.2.1 Processor Status Signal Encoding ...............................................................................19-4
19.2.1.1 Continue Execution (PST = $0) ...............................................................................19-4
19.2.1.2 Begin Execution of an Instruction (PST = $1) .........................................................19-4
19.2.1.3 Entry into User Mode (PST = $3) ............................................................................19-4
19.2.1.4 Begin Execution of PULSE or WDDATA instructions (PST = $4) ...........................19-4
19.2.1.5 Begin Execution of Taken Branch (PST = $5) .........................................................19-5
19.2.1.6 Begin Execution of RTE Instruction (PST = $7) ......................................................19-6
19.2.1.7 Begin Data Transfer (PST = $8–$B) .......................................................................19-6
19.2.1.8 Exception Processing (PST = $C) ...........................................................................19-6
19.2.1.9 Emulator Mode Exception Processing (PST = $D) .................................................19-6
19.2.1.10 Processor Stopped (PST = $E) ...............................................................................19-6
19.2.1.11 Processor Halted (PST = $F) ..................................................................................19-6
19.3 Background-Debug Mode (BDM) ......................................................................................19-6
19.3.1 CPU Halt .......................................................................................................................19-7
19.3.2 BDM Serial Interface ....................................................................................................19-7
19.3.2.1 Receive Packet Format ...........................................................................................19-8
19.3.2.2 Transmit Packet Format ..........................................................................................19-9
19.3.3 BDM Command Set ......................................................................................................19-9
19.3.3.1 BDM Command Set Summary ................................................................................19-9
19.3.3.2 ColdFire BDM Commands .......................................................................................19-9
19.3.3.3 Command Sequence Diagram ..............................................................................19-11
19.3.3.4 Command Set Descriptions ...................................................................................19-13
19.3.3.4.1 Read Address/Data Register (RAREG/RDREG) .............................................19-13
19.3.3.4.2 Write Address/Data Register (WAREG and WDREG) .....................................19-13
19.3.3.4.3 Read Memory Location (READ) .......................................................................19-14
19.3.3.4.4 Write Memory Location (WRITE) .....................................................................19-16
19.3.3.4.5 Dump Memory Block (DUMP) ..........................................................................19-17
19.3.3.4.6 Fill Memory Block (FILL) ..................................................................................19-18
19.3.3.4.7 Resume Execution (GO) ..................................................................................19-20
19.3.3.4.8 No Operation (NOP) .........................................................................................19-20
19.3.3.4.9 Read Control Register (RCREG) .....................................................................19-21
19.3.3.4.10 Write Control Register (WCREG) .....................................................................19-22
19.3.3.4.11 Read Debug Module Register (RDMREG) .......................................................19-22
19.3.3.4.12 Write Debug Module Register (WDMREG) ......................................................19-23
19.3.3.4.13 Unassigned Opcodes .......................................................................................19-24
19.3.3.5 BDM Accesses of the EMAC Registers .................................................................19-24
19.4 Real-Time Debug Support ...............................................................................................19-25
19.4.1 Theory of Operation ....................................................................................................19-26
19.4.1.1 Emulator Mode ......................................................................................................19-27
19.4.1.2 Debug Module Hardware .......................................................................................19-27
19.4.1.2.1 Reuse of Debug Module Hardware (Rev. A) ....................................................19-27
19.4.2 Programming Model ...................................................................................................19-28
19.4.2.1 Address Breakpoint Registers ...............................................................................19-28
19.4.2.2 Address Attribute Trigger Register ........................................................................19-29
19.4.2.3 Program Counter Breakpoint Register (PBR, PBMR) ...........................................19-31
19.4.2.4 Data Breakpoint Registers (DBR, DBMR) .............................................................19-32
19.4.2.5 Trigger Definition Register (TDR) ..........................................................................19-34
19.4.2.6 Configuration/Status Register (CSR) .....................................................................19-36
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19.4.2.7 BDM Address Attribute (BAAR) .............................................................................19-39
19.4.3 Concurrent BDM and Processor Operation ................................................................19-40
19.4.4 Motorola-Recommended BDM Pinout ........................................................................19-41
Table of Contents
SECTION 20
IEEE 1149.1 TEST ACCESS PORT (JTAG)
20.1 JTAG Overview ..................................................................................................................20-1
20.2 JTAG Signal Descriptions .................................................................................................20-2
20.2.1 Test Clock - (TCK) ........................................................................................................20-3
20.2.2 Test Reset/Development Serial Clock - (TRST/DSCLK) ..............................................20-3
20.2.3 Test Mode Select/ Breakpoint (TMS/BKPT) .................................................................20-3
20.2.4 Test Data Input/Development Serial Input - (TDI/DSI) .................................................20-4
20.2.5 Test Data Output/Development Serial Output - (TDO/DSO) ........................................20-4
20.3 TAP Controller ...................................................................................................................20-4
20.4 JTAG Registers .................................................................................................................20-6
20.4.1 JTAG Instruction Shift Register ...................................................................................20-6
20.4.1.1 EXTEST Instruction .................................................................................................20-6
20.4.1.2 IDCODE ...................................................................................................................20-6
20.4.1.3 SAMPLE/PRELOAD Instruction ..............................................................................20-7
20.4.1.4 CLAMP Instruction ...................................................................................................20-7
20.4.1.5 HIGHZ Instruction ....................................................................................................20-7
20.4.1.6 BYPASS Instruction .................................................................................................20-7
20.4.2 IDcode Register ............................................................................................................20-8
20.4.3 JTAG Boundary Scan Register ....................................................................................20-8
20.4.4 JTAG Bypass Register .................................................................................................20-9
20.5 Restrictions ........................................................................................................................20-9
20.6 Disabling IEEE 1149.1A Standard Operation ....................................................................20-9
20.7 MCF5249 BSDL File ........................................................................................................20-10
20.8 Obtaining the IEEE 1149.1A Standard ............................................................................20-22
SECTION 21
ELECTRICAL SPECIFICATIONS
21.1 Supply Voltage Sequencing and Separation Cautions ......................................................21-3
21.2 JTAG Timing Definition IIS Module AC Timing Specifications .........................................21-18
SECTION 22
MECHANICAL DATA
22.1 Package .............................................................................................................................22-1
22.2 Pin Assignment ..................................................................................................................22-1
APPENDIX A
REGISTER MEMORY MAP
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LIST OF FIGURES

Page
Number
Figure 1-1 MCF5249 Block Diagram .................................................................................. 1-2
Figure 3-1 V2 ColdFire Processor Core Pipelines ............................................................. 2-1
Figure 3-2 User Programming Model ................................................................................. 2-3
Figure 3-3 Supervisor Programming Model ....................................................................... 2-5
Figure 3-4 Vector Base Register (VBR) ............................................................................. 2-6
Figure 3-5 Exception Stack Frame Form ........................................................................... 2-9
Figure 4-1 Phase-Locked Loop Module Block Diagram ..................................................... 4-1
Figure 5-1 Instruction Cache Block Diagram ...................................................................... 5-2
Figure 7-1 Synchronous DRAM Controller Block Diagram ................................................ 7-2
Figure 7-2 MCF5249 SDRAM Interface ............................................................................. 7-5
Figure 7-3 DRAM Control Register (DCR) (Synchronous Mode) ....................................... 7-5
Figure 7-4 DACR0 and DACR1 (Synchronous Mode) ....................................................... 7-7
Figure 7-5 DRAM Controller Mask Registers (DMR0 and DMR1) ..................................... 7-9
Figure 7-6 Burst Read SDRAM Access ........................................................................... 7-12
Figure 7-7 Burst Write SDRAM Access ............................................................................ 7-13
Figure 7-8 Synchronous, Continuous Page-Mode Access—Consecutive Reads ............ 7-14
Figure 7-9 Synchronous, Continuous Page-Mode Access—Read after Write ................. 7-15
Figure 7-10 Auto-Refresh Operation .................................................................................. 7-16
Figure 7-11 Self-Refresh Operation ................................................................................... 7-16
Figure 7-12 Mode Register Set (mrs) Command ............................................................... 7-18
Figure 7-13 Initialization Values for DCR ........................................................................... 7-19
Figure 7-14 SDRAM Configuration ..................................................................................... 7-20
Figure 7-15 DACR Register Configuration ......................................................................... 7-20
Figure 7-16 DMR0 Register ............................................................................................... 7-21
Figure 7-17 Mode Register Mapping to MCF5249 A[31:0] ................................................. 7-22
Figure 8-1 Connections for External Memory Port Sizes ................................................... 8-3
Figure 8-2 Signal Relationship to BCLK for Non-DRAM Access ........................................ 8-5
Figure 8-3 Read Cycle Flowchart ....................................................................................... 8-7
Figure 8-4 Basic Read Bus Cycle ...................................................................................... 8-7
Figure 8-5 Write Cycle Flowchart ....................................................................................... 8-9
Figure 8-6 Basic Write Bus Cycle ....................................................................................... 8-9
Figure 8-7 Back-to-Back Bus Cycles ................................................................................ 8-10
Figure 8-8 Line Read Burst (one wait cycle) .................................................................... 8-12
Figure 8-9 Line Read Burst (no wait cycles) .................................................................... 8-12
Figure 8-10 Line Write Burst (no wait cycles) ..................................................................... 8-13
Figure 8-11 Line Read Burst-Inhibited ............................................................................... 8-13
Figure 8-12 Line Write Burst with One Wait State .............................................................. 8-14
Figure 8-13 Line Write Burst-Inhibited ................................................................................ 8-14
Figure 8-14 Misaligned Longword Transfer ........................................................................ 8-15
Figure 8-15 Misaligned Word Transfer ............................................................................... 8-15
Figure 8-16 Master Reset Timing ....................................................................................... 8-16
Figure 8-17 Software Watchdog Reset Timing .................................................................. 8-17
Figure 9-1 MCF5249 Unterminated Access Recovery ..................................................... 9-17
Figure 9-2 General-Purpose Pin Logic for Pin ddata3/gpio34 .......................................... 9-27
Figure 11-1 Timer Block Diagram Module Operation ......................................................... 11-2
Figure 12-1 ADC with On-chip and External Parts ............................................................. 12-2
Figure 13-1 Bus Setup with IDE and SmartMedia Interface ............................................... 13-1
Figure 13-2 Buffer Enables (BUFENB1 and BUFENB2) .................................................... 13-2
Figure 13-3 DIOR and SRE Timing Diagram ..................................................................... 13-5
Figure 13-4 Non-IORDY Controlled IDE/SmartMedia TA Timing ....................................... 13-6
Figure 13-5 CS2 (DIOR, DIOW) and CS3 (SRE, SWE) Cycle Timing ............................... 13-6
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List of Figures
Figure 13-6 SmartMedia Timing ..........................................................................................13-7
Figure 13-7 IDE Timing .......................................................................................................13-8
Figure 13-8 FlashMedia Block Diagram ............................................................................13-10
Figure 13-9 One Interface Shift Register ..........................................................................13-12
Figure 13-10 Reading Data From MemoryStick ..................................................................13-17
Figure 13-11 Reading Data From MemoryStick Timing ......................................................13-17
Figure 13-12 Writing Data To MemoryStick ........................................................................13-18
Figure 13-13 Writing Data to MemoryStick Timing .............................................................13-18
Figure 13-14 Interrupt From MemoryStick ..........................................................................13-19
Figure 13-15 Interrupt From MemoryStick ..........................................................................13-19
Figure 13-16 Sent Command To Card ................................................................................13-20
Figure 13-17 Write Data To Card With Busy .......................................................................13-21
Figure 13-18 Write Data To Card Without Busy ..................................................................13-22
Figure 13-19 Read Data From Card ...................................................................................13-23
Figure 14-1 DMA Signal Diagram .......................................................................................14-1
Figure 14-2 Dual Address Transfer .....................................................................................14-3
Figure 15-1 UART Block Diagram .......................................................................................15-1
Figure 15-2 External and Internal Interface Signals ............................................................15-3
Figure 15-3 Baud-Rate Timer Generator Diagram ..............................................................15-4
Figure 15-4 Transmitter and Receiver Functional Diagram ................................................15-5
Figure 15-5 Transmitter Timing Diagram ............................................................................15-6
Figure 15-6 Receiver Timing Diagram ................................................................................15-7
Figure 15-7 Looping Modes Functional Diagram ..............................................................15-10
Figure 15-8 Multidrop Mode Timing Diagram ....................................................................15-11
Figure 15-9 UART Software Flowchart (1 of 5) .................................................................15-31
Figure 15-10 UART Software Flowchart (2 of 5) .................................................................15-32
Figure 15-11 UART Software Flowchart (3 of 5) .................................................................15-33
Figure 15-12 UART Software Flowchart (4 of 5) .................................................................15-34
Figure 15-13 UART Software Flowchart (5 of 5) .................................................................15-35
Figure 16-1 QSPI Block Diagram ........................................................................................16-2
Figure 16-2 QSPI RAM Model ............................................................................................16-4
Figure 16-3 QSPI Mode Register (QSPIMR) ......................................................................16-8
Figure 16-4 QSPI Clocking and Data Transfer Example ....................................................16-9
Figure 16-5 QSPI Delay Register (QDLYR) ......................................................................16-10
Figure 16-6 QSPI Wrap Register (QWR) ..........................................................................16-10
Figure 16-7 QSPI Interrupt Register (QIR) ........................................................................16-11
Figure 16-8 QSPI Address Register (QAR) ......................................................................16-13
Figure 16-9 QSPI Data Register (QDR) ............................................................................16-13
Figure 16-10 Command RAM Registers (QCR0–QCR15) ..................................................16-14
Figure 16-11 QSPI Timing ..................................................................................................16-15
Figure 17-1 Audio Interface Block Diagram ........................................................................17-2
Figure 17-2 IIS/EIAJ Timing Diagram (16 SCLK edges per word) ......................................17-9
Figure 17-3 IIS/EIAJ timing diagram (24 or 32 SCLK edges per word) ............................17-10
Figure 17-4 CD-Subcode Interface ...................................................................................17-20
Figure 17-5 Data Format on CD-Subcode Interface Out ..................................................17-21
Figure 17-6 Processor/Audio Module Interface .................................................................17-23
Figure 17-7 Automatic Resynchronization FSM of left-right FIFOs ...................................17-28
Figure 17-8 Audio Transmit / Receive FIFOs ....................................................................17-33
Figure 17-9 Block Decoder ...............................................................................................17-35
Figure 17-10 Block Encoder ................................................................................................17-36
Figure 17-11 Frequency Measurement Circuit ....................................................................17-38
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Figure 17-12 XTRIM External Circuit .................................................................................. 17-40
Figure 17-13 PDM Modulator Used on Xtrim Output .......................................................... 17-41
Figure 18-1 I2C Module Block Diagram ............................................................................. 18-2
Figure 18-2 I2C Standard Communication Protocol ........................................................... 18-3
Figure 18-3 Synchronized Clock SCL ................................................................................ 18-5
Figure 18-4 Flow-Chart of Typical I
Figure 19-1 Processor/Debug Module Interface ................................................................. 19-1
Figure 19-2 Example PST/DDATA Diagram ...................................................................... 19-5
Figure 19-3 1BDM Serial Transfer ...................................................................................... 19-8
Figure 19-4 Command Sequence Diagram ...................................................................... 19-12
Figure 19-5 Command/Result Formats ............................................................................ 19-13
Figure 19-6 Read A/D Register Command Sequence ..................................................... 19-13
Figure 19-7 Write A/D Register Command Sequence ...................................................... 19-14
Figure 19-8 WAREG/WDREG Command Format ............................................................ 19-14
Figure 19-9 READ Command/Result Format ................................................................... 19-15
Figure 19-10 Read Memory Location Command Sequence .............................................. 19-15
Figure 19-11 Write Memory Location Command Sequence .............................................. 19-16
Figure 19-12 DUMP Command/Result Format .................................................................. 19-17
Figure 19-13 DUMP Memory Block Command Sequence ................................................. 19-18
Figure 19-14 Fill Memory Block Command Sequence ....................................................... 19-19
Figure 19-15 Resume Execution ........................................................................................ 19-20
Figure 19-16 No Operation Command Sequence .............................................................. 19-20
Figure 19-17 RCREG Command/Result Formats .............................................................. 19-21
Figure 19-18 WCREG Command Sequence ...................................................................... 19-22
Figure 19-19 Write Control Register Command Sequence ................................................ 19-22
Figure 19-20 RDMREG Command/Result Formats ........................................................... 19-23
Figure 19-21 Read Debug Module Register Command Sequence .................................... 19-23
Figure 19-22 WDMREG BDM Command Format .............................................................. 19-23
Figure 19-23 Write Debug Module Register Command Sequence .................................... 19-24
Figure 19-24 Read Control Register Command Sequence ................................................ 19-25
Figure 19-25 Debug Programming Mode ........................................................................... 19-28
Figure 19-26 Recommended BDM Connector ................................................................... 19-41
Figure 20-1 JTAG Test Logic Block Diagram ..................................................................... 20-2
Figure 20-2 JTAG TAP Controller State Machine .............................................................. 20-5
Figure 20-3 Disabling JTAG in JTAG Mode ....................................................................... 20-9
Figure 20-4 Disabling JTAG in Debug Mode .................................................................... 20-10
Figure 21-1 Supply Voltage Sequencing and Separation Cautions ................................... 21-3
Figure 21-2 Example Circuit to Control Supply Sequencing .............................................. 21-4
Figure 21-3 MCF5249 Power Supply ................................................................................. 21-4
Figure 21-4 Clock Timing Definition ................................................................................... 21-6
Figure 21-5 Input/Output Timing Definition-I ...................................................................... 21-8
Figure 21-6 Input/Output Timing Definition-III .................................................................... 21-9
Figure 21-7 Debug Timing Definition ................................................................................ 21-10
Figure 21-8 Timer Module Timing Definition .................................................................... 21-11
Figure 21-9 UART Timing Definition ................................................................................. 21-12
Figure 21-10 I2C Timing Definition ..................................................................................... 21-14
Figure 21-11 I2C and System Clock Timing Relationship .................................................. 21-15
Figure 21-12 General-Purpose Parallel Port Timing Definition .......................................... 21-15
Figure 21-13 ...................................................................................................................... 21-17
Figure 21-14 SCLK Input, SDATA Output Timing .............................................................. 21-18
Figure 21-15 SCLK Output, SDATAO Output Timing Diagram .......................................... 21-18
List of Figures
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2
C Interrupt Routine .................................................. 18-16
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Figure 21-16 SCLK Input/Output, SDATAI Input Timing Diagram ......................................21-19
Figure 22-1 144 QFP Package (1 of 3) .............................................................................22-12
Figure 22-2 144 QFP Package (2 of 3) .............................................................................22-13
Figure 22-3 144 QFP Package (3 of 3) .............................................................................22-14
Figure 22-4 160 BGA Mechanical Package (1 of 2) ..........................................................22-15
Figure 22-5 160 BGA Mechanical Package (2 of 2) ..........................................................22-16
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LIST OF TABLES

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Number
Table 1-1 160 MAPBGA Ball Assignments ..............................................................................1-5
Table 2-1 MCF5249 Signal Index .............................................................................................2-1
Table 2-2 SDRAM Controller Signals .......................................................................................2-5
Table 2-3 I2C Module Signals ..................................................................................................2-6
Table 2-4 Timer Module Signals ..............................................................................................2-7
Table 2-5 Serial Module Signals ..............................................................................................2-7
Table 2-6 Serial Audio Interface Signals ..................................................................................2-8
Table 2-7 Digital Audio Interface Signals .................................................................................2-9
Table 2-8 Subcode Interface Signal .........................................................................................2-9
Table 2-9 Flash Memory Card Signals ...................................................................................2-10
Table 2-10 Queued Serial Peripheral Interface (QSPI) Signals ...............................................2-10
Table 2-11 Processor Status Signal Encodings .......................................................................2-12
Table 3-1 Condition Code Register (Bits 0-4) ..........................................................................3-3
Table 3-2 CCR Functionality ....................................................................................................3-4
Table 3-3 EMAC Instruction Summary .....................................................................................3-4
Table 3-4 Status Register .........................................................................................................3-6
Table 3-5 Status Bit Descriptions .............................................................................................3-6
Table 3-6 Exception Vector Assignments ................................................................................3-8
Table 3-7 Format Field Encoding .............................................................................................3-9
Table 3-8 Fault Status Encoding ..............................................................................................3-9
Table 3-9 Misaligned Operand References ............................................................................3-13
Table 3-10 Move Byte and Word Execution times ...................................................................3-14
Table 3-11 Move Long Execution Times ..................................................................................3-14
Table 3-12 One Operand Instruction Execution Times ............................................................3-15
Table 3-13 Two Operand Instruction Execution Times - (MACS) ............................................3-16
Table 3-14 Miscellaneous Instruction Execution Times ...........................................................3-18
Table 3-15 General Branch Instruction Execution Times .........................................................3-19
Table 3-16 BRA, Bcc Instruction Execution Times ...................................................................3-19
Table 4-1 PLLCR Register .......................................................................................................4-2
Table 4-2 PLLCR Bit Descriptions ............................................................................................4-2
Table 4-3 PLL Electrical Limits .................................................................................................4-4
Table 4-4 PLLCR Bit Fields ......................................................................................................4-5
Table 4-5 Recommended PLL Settings ...................................................................................4-6
Table 5-1 Initial Fetch Offset vs. CLNF Bits .............................................................................5-4
Table 5-2 Instruction Cache Operation as Defined by CACR[31,10] .......................................5-5
Table 5-3 Memory Map of I-Cache Registers ..........................................................................5-6
Table 5-4 Cache Control Register (CACR) ..............................................................................5-6
Table 5-5 Cache Control Bit Descriptions ................................................................................5-7
Table 5-6 External Fetch Size Based on Miss Address and CLNF ..........................................5-8
Table 5-7 Access Control Registers (ACRo, ACR1) ................................................................5-8
Table 5-8 Access Control Bit Descriptions ...............................................................................5-9
Table 6-1 SRAM Base Address Register (RAMBAR0) ............................................................6-2
Table 6-2 SRAM1 Base Address Register (RAMBAR1) ..........................................................6-2
Table 6-3 Cache Control Bit Descriptions ................................................................................6-3
Table 6-4 Typical RAMBAR Setting Examples ........................................................................6-4
Table 7-1 DRAM Controller Registers ......................................................................................7-3
Table 7-2 SDRAM Commands .................................................................................................7-3
Table 7-3 Synchronous DRAM Signal Connections .................................................................7-4
Table 7-4 DCR Field Descriptions (Synchronous Mode) .........................................................7-6
Table 7-5 DACR0/DACR1 Field Descriptions (Synchronous Mode) ........................................7-7
Table 7-6 DMR0/DMR1 Field Descriptions ..............................................................................7-9
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Table 7-7 SDRAM Interface (8-Bit Port,10-Column Address Lines) ......................................7-10
Table 7-8 SDRAM Interface (16-Bit Port,11-Column Address Lines) ....................................7-10
Table 7-9 SDRAM Interface (16-Bit Port,12-Column Address Lines) ....................................7-10
Table 7-10 SDRAM Interface (16-Bit Port, 8-Column Address Lines) .....................................7-11
Table 7-11 SDRAM Interface (16-Bit Port, 9-Column Address Lines) .....................................7-11
Table 7-12 SDRAM Interface (16-Bit Port, 10-Column Address Lines) ...................................7-11
Table 7-13 SDRAM Interface (16-Bit Port, 11-Column Address Lines) ...................................7-11
Table 7-14 SDRAM Hardware Connections .............................................................................7-11
Table 7-15 SDRAM Example Specifications ............................................................................7-18
Table 7-16 SDRAM Hardware Connections .............................................................................7-19
Table 7-17 DCR Initialization Values ........................................................................................7-19
Table 7-18 DACR Initialization Values .....................................................................................7-20
Table 7-19 DMR0 Initialization Values .....................................................................................7-21
Table 7-20 Mode Register Initialization ....................................................................................7-22
Table 8-1 MCF5249 Bus Signal Summary ...............................................................................8-1
Table 8-2 Reset Port Settings ..................................................................................................8-2
Table 8-3 CF-Bus Signal Summary ..........................................................................................8-4
Table 8-4 Accesses by Matches ..............................................................................................8-6
Table 8-5 Read Cycle States ...................................................................................................8-8
Table 8-6 Write Cycle States ....................................................................................................8-9
Table 8-7 Allowable Line Access Patterns .............................................................................8-11
Table 8-8 Power-on Reset Configuration for CS0 ..................................................................8-16
Table 9-1 MBAR Register Addresses ......................................................................................9-2
Table 9-2 SIM Memory Map .....................................................................................................9-2
Table 9-3 Module Base Address Register (MBAR) ..................................................................9-4
Table 9-4 Module Base Address Bit Descriptions ....................................................................9-4
Table 9-5 Second Module Base Address Register (MBAR2) ...................................................9-5
Table 9-6 Second Module Base Address Bit Descriptions .......................................................9-5
Table 9-7 DeviceID Register (DeviceID) ..................................................................................9-6
Table 9-8 Primary Interrupt Control Register Memory Map .....................................................9-7
Table 9-9 Interrupt Control Register (ICR) ...............................................................................9-7
Table 9-10 Interrupt Control Bit Descriptions .............................................................................9-7
Table 9-11 Interrupt Priority Scheme .........................................................................................9-8
Table 9-12 Interrupt Priority Assignment ....................................................................................9-8
Table 9-13 Interrupt Mask Register (IMR) ..................................................................................9-9
Table 9-14 Interrupt Mask Bit Descriptions ..............................................................................9-10
Table 9-15 Interrupt Pending Register (IPR) ............................................................................9-10
Table 9-16 Interrupt Pending Bit Descriptions ..........................................................................9-10
Table 9-17 Secondary Interrupt Controller Registers Memory Map .........................................9-11
Table 9-18 Secondary Interrupt Level Programming Bit Assignment ......................................9-11
Table 9-19 intBase Register Description ..................................................................................9-12
Table 9-20 intBase Bit Descriptions .........................................................................................9-12
Table 9-21 spurvec Register Description .................................................................................9-12
Table 9-22 Secondary Interrupt Sources .................................................................................9-12
Table 9-23 FlashMedia Interrupt Interface ...............................................................................9-14
Table 9-24 Extraint Register Descriptions ................................................................................9-15
Table 9-25 Reset Status Register (RSR) .................................................................................9-16
Table 9-26 Reset Status Bit Descriptions .................................................................................9-16
Table 9-27 System Protection Control Register (SYPCR) .......................................................9-18
Table 9-28 System Protection Control Bit Descriptions ...........................................................9-18
Table 9-29 SWT Timeout Period ..............................................................................................9-18
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Table 9-30 SWP and SWT Bit Descriptions .............................................................................9-19
Table 9-31 Software Watchdog Interrupt Vector Register (SWIVR) ........................................9-19
Table 9-32 Software Watchdog Service Register (SWSR) ......................................................9-20
Table 9-33 Default Bus Master Register (MPARK) ..................................................................9-20
Table 9-34 Default Bus Master Selected with PARK[1:0] ........................................................9-21
Table 9-35 Round Robin (PARK[1:0] = 00) ..............................................................................9-21
Table 9-36 Park on Master Core Priority (PARK[1:0] = 01) ......................................................9-22
Table 9-37 Park on Current Master Priority (PARK[1:0] = 11) .................................................9-22
Table 9-38 Park Bit Descriptions ..............................................................................................9-22
Table 9-39 GPIO Registers ......................................................................................................9-23
Table 9-40 General Purpose Input to Pin Mapping ..................................................................9-24
Table 9-41 GPIO-INT-STAT, GPIO-INT-CLEAR and GPIO-INT-EN Interrupts .......................9-25
Table 9-42 General-Purpose Output Register Bits to Pins Mapping ........................................9-27
Table 10-1 Accesses by Matches in CS Control Registers ......................................................10-3
Table 10-2 Memory Map of Chip-Select Registers ..................................................................10-5
Table 10-3 Chip Select Address Register (CSAR) ...................................................................10-6
Table 10-4 Chip Select Bit Descriptions ...................................................................................10-6
Table 10-5 Chip Select Mask Register (CSMR) .......................................................................10-7
Table 10-6 Chip Select Mask Bit Descriptions .........................................................................10-7
Table 10-7 Chip Select Control Register 0 ...............................................................................10-8
Table 10-8 Chip Select Control Register 1 to 3 ........................................................................10-9
Table 10-9 Chip Select Bit Descriptions ...................................................................................10-9
Table 11-1 Programming Model for Timers ..............................................................................11-3
Table 11-2 Timer Mode Register (TMRn) ...............................................................................11-4
Table 11-3 Timer Mode Bit Descriptions ..................................................................................11-4
Table 11-4 Timer Reference Register (TRRn) ........................................................................11-5
Table 11-5 Timer Capture Register (TCR) ...............................................................................11-6
Table 11-6 Timer Counter (TCN) .............................................................................................11-6
Table 11-7 Timer Event Register (TERn) .................................................................................11-6
Table 11-8 Timer Event Bit Descriptions ..................................................................................11-7
Table 12-1 ADC Registers .......................................................................................................12-2
Table 12-2 ADconfig (ADconfig) Register ................................................................................12-3
Table 12-3 ADconfig Register Bit Descriptions ........................................................................12-3
Table 12-4 ADvalue Register ...................................................................................................12-4
Table 12-5 ADvalue Register Bit Descriptions .........................................................................12-4
Table 13-1 ideconfig1 Register ................................................................................................13-3
Table 13-2 IDECONFIG1 Bits ..................................................................................................13-3
Table 13-3 IDEConfig Register ................................................................................................13-5
Table 13-4 IDEConfig Bit Description .......................................................................................13-5
Table 13-5 DIOR, DIOW, and IORDY Timing Parameters .......................................................13-6
Table 13-6 SmartMedia Timing Values ....................................................................................13-7
Table 13-7 IDE Timing Values .................................................................................................13-9
Table 13-8 FlashMedia Registers ..........................................................................................13-11
Table 13-9 FLASHMEDIACONFIG Register Configuration ...................................................13-11
Table 13-10 FLASHMEDIA COMMAND REGISTERS (MemoryStick Mode) ..........................13-13
Table 13-11 FLASHMEDIA COMMAND REGISTER 1 (Secure Digital Mode) ........................13-13
Table 13-12 FLASHMEDIA COMMAND REGISTER 2 (Secure Digital Mode) ........................13-14
Table 13-13 FLASHMEDIA DATA REGISTERS ......................................................................13-15
Table 13-14 FLASHMEDIA STATUS REGISTER ....................................................................13-15
Table 13-15 FLASHMEDIA INTERRUPTS ..............................................................................13-16
Table 14-1 DMA Signals ..........................................................................................................14-2
List of Tables
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Table 14-2 Memory Map DMA Channel 0 ................................................................................14-4
Table 14-3 Memory Map DMA Channel 1 ................................................................................14-4
Table 14-4 Memory Map DMA Channel 2 ................................................................................14-4
Table 14-5 Memory Map DMA Channel 3 ................................................................................14-4
Table 14-6 Memory Map (DMA Controller Registers —BCR24BIT = 1) ..................................14-5
Table 14-7 DMAroute Register .................................................................................................14-5
Table 14-8 DMAroute Register Fields ......................................................................................14-5
Table 14-9 DMA3REQ Field Definition .....................................................................................14-6
Table 14-10 DMA2REQ Field Definition .....................................................................................14-6
Table 14-11 DMA1REQ Field Definition .....................................................................................14-7
Table 14-12 DMA0REQ Field Definition .....................................................................................14-8
Table 14-13 Source Address Register (SAR) ............................................................................14-8
Table 14-14 Destination Address Register (DAR) ......................................................................14-9
Table 14-15 Byte Count Register (BCR)—BCR24BIT = 1 .......................................................14-10
Table 14-16 Byte Count Register (BCR)—BCR24BIT = 0 .......................................................14-10
Table 14-17 DMA Control Register (DCR)—BCR24BIT = 0 ....................................................14-10
Table 14-18 DMA Control Bit Descriptions ...............................................................................14-11
Table 14-19 BWC Encoding .....................................................................................................14-12
Table 14-20 SSIZE Encoding ...................................................................................................14-13
Table 14-21 DSIZE Encoding ...................................................................................................14-13
Table 14-22 DMA Status Register (DSR) .................................................................................14-14
Table 14-23 DMA Status Bit Descriptions ................................................................................14-14
Table 14-24 DMA Interrupt Vector Register (DIVR) .................................................................14-15
Table 15-1 UART Module Programming Model .....................................................................15-13
Table 15-2 Mode Register 1 ...................................................................................................15-13
Table 15-3 PMx and PT Control Bits ......................................................................................15-14
Table 15-4 Mode Register 1 Bit Descriptions .........................................................................15-14
Table 15-5 B/Cx Control Bits ..................................................................................................15-15
Table 15-6 Mode Register 2 ...................................................................................................15-15
Table 15-7 Mode Register 2 Bit Descriptions .........................................................................15-16
Table 15-8 Status Registers (USR0 and USR1) ....................................................................15-18
Table 15-9 Status Bit Descriptions .........................................................................................15-18
Table 15-10 Clock Select Register (UCSRn) ...........................................................................15-19
Table 15-11 Clock Select Bit Descriptions ...............................................................................15-20
Table 15-12 Command Register (UCRn) .................................................................................15-20
Table 15-13 MISCx Control Bits ...............................................................................................15-20
Table 15-14 RCx Control Bits ...................................................................................................15-22
Table 15-15 TCx Control Bits ...................................................................................................15-22
Table 15-16 Receiver Buffer (URBn) .......................................................................................15-23
Table 15-17 Receiver Buffer Bit Descriptions ..........................................................................15-23
Table 15-18 Transmitter Buffer (UTBn) ....................................................................................15-23
Table 15-19 Transmitter Buffer Bit Descriptions ......................................................................15-24
Table 15-20 Input Port Change Register (UIPCRn) .................................................................15-24
Table 15-21 Input Port Change Bit Descriptions ......................................................................15-24
Table 15-22 Auxiliary Control Register (UACRn) .....................................................................15-25
Table 15-23 Auxiliary Control Bit Descriptions .........................................................................15-25
Table 15-24 Interrupt Status Register (UISRn) ........................................................................15-25
Table 15-25 Interrupt Status Bit Descriptions ...........................................................................15-26
Table 15-26 Interrupt Mask Register (UIMRn) .........................................................................15-26
Table 15-27 Interrupt Mask Bit Descriptions ............................................................................15-27
Table 15-28 Interrupt Vector Register (UIVRn) ........................................................................15-27
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Table 15-29 Interrupt Vector Bit Descriptions ..........................................................................15-28
Table 15-30 Input Port Register (UIPn) ....................................................................................15-28
Table 15-31 Interrupt Vector Bit Descriptions ..........................................................................15-28
Table 15-32 Output Port Data Registers (UOP1n) ...................................................................15-28
Table 15-33 Output Port Data Bit Descriptions ........................................................................15-29
Table 15-34 Output Port Data Registers (UOP0n) ...................................................................15-29
Table 16-1 QSPI Input and Output Signals and Functions ......................................................16-2
Table 16-2 QSPI_CLK Frequency as Function of CPU Clock and Baud Rate ........................16-6
Table 16-3 QSPIMR Field Descriptions ...................................................................................16-8
Table 16-4 QDLYR Field Descriptions ...................................................................................16-10
Table 16-5 QWR Field Descriptions .......................................................................................16-11
Table 16-6 QIR Field Descriptions .........................................................................................16-12
Table 16-7 QCR0–QCR15 Field Descriptions ........................................................................16-14
Table 17-1 Interrupt Register Addresses .................................................................................17-4
Table 17-2 Interrupt Register Description ................................................................................17-4
Table 17-3 InterruptEn3 InterruptClear3, InterruptStat3 Register Description .........................17-5
Table 17-4 IIS1 Configuration Registers (0x10) .......................................................................17-6
Table 17-5 IIS2 Configuration Registers (0x14) .......................................................................17-6
Table 17-6 IIS3,4 Configuration Registers (0x18, 0x1C) ..........................................................17-6
Table 17-7 IIS Configuration Bit Descriptions ..........................................................................17-7
Table 17-8 EBU1Config Register ...........................................................................................17-10
Table 17-9 EBU1Config Register Bit Descriptions .................................................................17-11
Table 17-10 EBU2Config Register ...........................................................................................17-12
Table 17-11 EBU2Config Register Bit Descriptions .................................................................17-12
Table 17-12 EBURcvCChannel Register .................................................................................17-13
Table 17-13 UChannel Receive and QChannel Receive Registers .........................................17-15
Table 17-14 U Channel Receive and Q Channel Receive Bit Descriptions .............................17-15
Table 17-15 CDTEXTCONTROL .............................................................................................17-15
Table 17-16 CD-Subcode Register Bit Descriptions ................................................................17-15
Table 17-17 Correlation Between Zero Bits and Sync Symbols ..............................................17-17
Table 17-18 EBU1TxCChannel Registers Addresses ..............................................................17-19
Table 17-19 Formatting of EBUOUT1 (Consumer “C” channel) ..............................................17-19
Table 17-20 Formatting of EBUOUT2 - Professional “C” Channel ...........................................17-19
Table 17-21 UChannel Transmit Register ................................................................................17-20
Table 17-22 CD-Subcode Register ..........................................................................................17-20
Table 17-23 Data Exchange Register Descriptions .................................................................17-23
Table 17-24 DataInControl Register .........................................................................................17-25
Table 17-25 DataInControl Bit Descriptions .............................................................................17-25
Table 17-26 PDIR1-L, PDIR3-L, PDOR1-L, PDOR2-L Formatting ..........................................17-27
Table 17-27 PDIR1-R, PDIR3-R, PDOR1-R, PDOR2-R Formatting ........................................17-27
Table 17-28 PDIR2, PDOR3 Formatting ..................................................................................17-27
Table 17-29 audioGlob Register ..............................................................................................17-28
Table 17-30 audioGlob Register Fields (0xCE) ........................................................................17-29
Table 17-31 Interrupt Register Description (0x94, 0x98) .........................................................17-31
Table 17-32 blockControl Register ...........................................................................................17-33
Table 17-33 blockControl Bit Descriptions ...............................................................................17-34
Table 17-34 Swap Control in CD-ROM Encoder/Decoder .......................................................17-35
Table 17-35 DMA Config Register Address .............................................................................17-37
Table 17-36 DMA Config Bit Descriptions ................................................................................17-37
Table 17-37 PhaseConfig and Frequency Measure Register Addresses ................................17-38
Table 17-38 PhaseConfig Register ..........................................................................................17-39
List of Tables
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Table 17-39 PhaseConfig Bit Descriptions ...............................................................................17-39
Table 17-40 PhaseConfig Register Description (0xA0) ............................................................17-39
Table 17-41 XTrim Register Address and Description .............................................................17-40
Table 17-42 Audio Interface Memory Map ...............................................................................17-41
Table 18-1 I2C Interfaces Programmer’s Model ......................................................................18-5
Table 18-2 MADR Register ......................................................................................................18-6
Table 18-3 MADR Bit Descriptions ...........................................................................................18-6
Table 18-4 MFDR Register ......................................................................................................18-7
Table 18-5 MFDR Bit Descriptions ...........................................................................................18-7
Table 18-6 I2C Prescaler Values .............................................................................................18-7
Table 18-7 MBCR Register ......................................................................................................18-8
Table 18-8 MBCR Bit Descriptions ...........................................................................................18-9
Table 18-9 MBSR Register ....................................................................................................18-10
Table 18-10 MBSR Bit Descriptions .........................................................................................18-10
Table 18-11 MBDR Register ....................................................................................................18-11
Table 19-1 Processor Status Encoding ....................................................................................19-3
Table 19-2 Receive BDM Packet .............................................................................................19-8
Table 19-3 CPU-Generated Command Responses .................................................................19-8
Table 19-4 Receive BDM Bit Descriptions ...............................................................................19-9
Table 19-5 Transmit BDM Packet ............................................................................................19-9
Table 19-6 Transmit Bit Descriptions .......................................................................................19-9
Table 19-7 BDM Command Summary ...................................................................................19-10
Table 19-8 BDM Command Format .......................................................................................19-11
Table 19-9 BDM Bit Descriptions ...........................................................................................19-11
Table 19-10 BDM Size Field Encoding ....................................................................................19-11
Table 19-11 WAREG/WDREG Command ...............................................................................19-14
Table 19-12 Byte FILL Command ............................................................................................19-19
Table 19-13 Word FILL Command ...........................................................................................19-19
Table 19-14 Long FILL Command ...........................................................................................19-19
Table 19-15 GO Command ......................................................................................................19-20
Table 19-16 NOP Command ....................................................................................................19-20
Table 19-17 RC Encoding ........................................................................................................19-21
Table 19-18 Definition of DRc Encoding--Read .......................................................................19-23
Table 19-19 Definition of DRc Encoding--Write .......................................................................19-24
Table 19-20 DDATA[3:0], CSR[31:28] Breakpoint Response ..................................................19-26
Table 19-21 Shared BDM/Breakpoint Hardware ......................................................................19-28
Table 19-22 Address Breakpoint Low Register (ABLR) ...........................................................19-29
Table 19-23 Address Breakpoint High Register (ABHR) ..........................................................19-29
Table 19-24 Address Attribute Trigger Register (AATR) ..........................................................19-30
Table 19-25 Address Attribute Trigger Bit Descriptions ...........................................................19-30
Table 19-26 Program Counter Breakpoint Register (PBR) ......................................................19-32
Table 19-27 Program Counter Breakpoint Mask Register (PBMR) ..........................................19-32
Table 19-28 Data Breakpoint Register (DBR) ..........................................................................19-33
Table 19-29 Data Breakpoint Mask Register (DBMR) .............................................................19-33
Table 19-30 Access and Operand Data Location ....................................................................19-34
Table 19-31 Trigger Definition Register (TDR) .........................................................................19-35
Table 19-32 Trigger Definition Bit Descriptions ........................................................................19-35
Table 19-33 Configuration/Status Register (CSR) ...................................................................19-37
Table 19-34 Configuration/Status Bit Descriptions ...................................................................19-37
Table 19-35 BDM Address Attribute Register (BAAR) .............................................................19-39
Table 19-36 BDM Address Attribute (BAAR) Bit Descriptions .................................................19-40
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Table 20-1 JTAG Pin Descriptions ...........................................................................................20-3
Table 20-2 JTAG Instructions ...................................................................................................20-6
Table 20-3 ID Code Register Command ..................................................................................20-8
Table 20-4 ID Code Bit Descriptions ........................................................................................20-8
Table 21-1 Maximum Ratings .................................................................................................21-1
Table 21-2 Operating Temperature ..........................................................................................21-1
Table 21-3 DC Electrical Specifications (Vcc = 3.3 Vdc + 0.3 Vdc) .........................................21-2
Table 21-4 160 MAPBGA Ball Assignments ............................................................................21-5
Table 21-5 Clock Timing Specification .....................................................................................21-6
Table 21-6 Input AC Timing Specification ................................................................................21-7
Table 21-7 Output AC Timing Specification .............................................................................21-7
Table 21-8 Debug AC Timing Specification ...........................................................................21-10
Table 21-9 Timer Module AC Timing Specification ................................................................21-11
Table 21-10 UART Module AC Timing Specifications ..............................................................21-12
Table 21-11 I2C-Bus Input Timing Specifications Between SCL and SDA .............................21-13
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Table 21-12 I2C-Bus Output Timing Specifications Between SCL and SDA ..........................21-13
Table 21-13 .............................................................................................................................21-14
Table 21-14 General-Purpose I/O Port AC Timing Specifications ...........................................21-15
Table 21-15 IEEE 1149.1 (JTAG) AC Timing Specifications ...................................................21-16
Table 21-16 SCLK INPUT, SDATAO OUTPUT Timing Specifications ....................................21-18
Table 21-17 SCLK OUTPUT, SDATA0 OUTPUT Timing Specifications .................................21-18
Table 21-18 SCLK INPUT, SDATAI INPUT Timing Specifications ..........................................21-19
Table 22-1 144 QFP Pin Assignments .....................................................................................22-2
Table 22-2 160 MAPBGA Pins .................................................................................................22-6
Table 22-3 160 MAPBGA Pin Assignments .............................................................................22-7
Table A-1 CPU Memory Map ................................................................................................... A-1
Table A-2 MBAR Address Space Memory Map ...................................................................... A-1
Table A-3 Audio Interface Memory Map .................................................................................. A-4
Table A-4 GPIO and Interrupt Status Memory Map ................................................................. A-6
A/D, MBUS2 and Memory Stick Memory Map ........................................................ A-7
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LOT-8 MCF5249UM MOTOROLA
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Section 1 Introduction

1.1 MCF5249 OVERVIEW

This document provides an overview of the MCF5249 ColdFire® processor and general descriptions of the MCF5249 features and modules.
The MCF5249 was designed as a system controller/decoder for MP3 music players, especially portable MP3 CD players. The 32-bit ColdFire core with Enhanced Multiply Accumulate (EMAC) unit provides optimum performance and code density for the combination of control code and signal processing required for MP3 decode, file management, and system control.
Low power features include a hardwired CD ROM decoder, advanced 0.18um CMOS process technology,
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1.8V core power supply, and on-chip 96KByte SRAM. MP3 decode requires less than 20MHz CPU bandwidth and runs in on-chip SRAM with external access only for data input and output.
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The MCF5249 is also an excellent general purpose system controller with over 125 Dhrystone 2.1 MIPS @ 140MHz performance at a very competitive price. The integrated peripherals and EMAC allow the MCF5249 to replace both the microcontroller and the DSP in certain applications. Most peripheral pins can also be remapped as General Purpose I/O pins.

1.2 MCF5249 FEATURE INTRODUCTION

The MCF5249 integrated microprocessor combines a Version 2 ColdFire® processor core operating at 140MHz with the following modules.
• DMA controller with 4 DMA channels
• Integrated Enhanced Multiply-accumulate Unit (EMAC)
• 8-KByte Direct Mapped Instruction Cache
• 96-KByte SRAM (A 64K and a 32K bank)
• Operates from external crystal oscillator
• Supports 16-bit wide SDRAM memories
• Serial Audio Interface which supports IIS and EIAJ audio protocols
• Digital audio transmitter and two receivers compliant with IEC958 audio protocol
• CD-ROM and CD-ROM XA block decoding and encoding function
•Two UARTS
• Queued Serial Peripheral Interface (QSPI) (Master Only)
• Two timers
• IDE and SmartMedia interfaces
• Analog/Digital Converter
• Flash Memory Card Interface
•Two I
• System debug support
• General Purpose I/O pins shared with other functions
2
C modules
1
1. I2C is a proprietary Philips bus.
MOTOROLA Introduction 1-1
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MCF5249 Block Diagram
• 1.8V core, 3.3V I/O
• 160 pin MAPBGA package (qualified at 140 MHz) and 144 pin QFP package (qualified at 120 MHz)

1.3 MCF5249 BLOCK DIAGRAM

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Instruction
Cache
64K
SRAM1
32K
SRAM0
ColdFire V2 Core
(160 BGA
140 Mhz)
(144 QFP
120 Mhz)
Clock
Multiplied
PLL
Debug
Module w/
JTAG
Standard ColdFire Peripheral Blocks
Timer
I2C
Dual
DMA
5x08
Arbiter
Translator
UART
5x08
Interrupt
S/DRAM Interface
External
Bus
IDE
SmartMedia
Interrupt
Controller
QSPI
Interface
Audio
Interfaces
ADC
Flash Memory/
Card
Interface
Timer Support
I2C Interface
UART Interface
MUX
(S)DRAM SRAM
IDE
BUFEN1_B
BufEn_b1
BUFEN2_B
BufEn_b2 IDE-DIOR IDE-DIOW
IDE-IORDY SWE
SRE
QSPI_DIN
QSPI_Din
QSPI_DOUT
QSPI_Dout QSPI_CS[3:0]
QSPI_CLK Serial Audio Interface
ebuin3_adin0_gpi38
EBUIN3/ADIN0_GP138
ebuin4_adin1_gpi39
EBUIN4/ADIN1_GP139
rxd2_adin2_gpi28
RXD2/ADIN2/GP128 CTS2/ADIN3/GP131
cts2_adin3_gpi31
TOUT1/ADOUT/GP135
tout1_adout_gpi35
MemoryStick/ SecureDigital Interface
Figure 1-1 MCF5249 Block Diagram
1-2 MCF5249UM MOTOROLA
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