Freescale MCF5235EC DATA SHEET

Freescale Semiconductor

Document Number: MCF5235EC

Hardware Specification

MCF523x Integrated
Microprocessor
Hardware Specification

by: Microcontroller Division

Rev. 2, 08/2006

The MCF523x is a family of highly-integrated 32-bit
microcontrollers based on the V2 ColdFire
microarchitecture. Featuring a 16 or 32 channel eTPU,
64 Kbytes of internal SRAM, a 2-bank SDRAM
controller, four 32-bit timers with dedicated DMA, a 4
channel DMA controller, up to 2 CAN modules, 3
UARTs and a queued SPI, the MCF523x family has been
designed for general purpose industrial control
applications. It is also a high-performance upgrade for
users of the MC68332. This document provides an
overview of the MCF523x microcontroller family, as
well as detailed descriptions of the mechanical and
electrical characteristics of the devices.

The MCF523x family is based on the Version 2 ColdFire
reduced instruction set computing (RISC)
microarchitecture operating at a core frequency of up to
150 MHz and bus frequency up to 75 MHz.

Contents

1 MCF523x Family Configurations . . . . . . . . . . . . . . . . . . . 2

2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . 9

6 Mechanicals/Pinouts and Part Numbers . . . . . . . . . . . . 14

7 Preliminary Electrical Characteristics . . . . . . . . . . . . . . 23

8 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9 Document Revision History . . . . . . . . . . . . . . . . . . . . . . 44

© Freescale Semiconductor, Inc., 2006. All rights reserved.

MCF523x Family Configurations

1 MCF523x Family Configurations

Table 1. MCF523x Family Configurations

Module MCF5232 MCF5233 MCF5234 MCF5235

ColdFire V2 Core with EMAC
(Enhanced Multiply-Accumulate
Unit)

Enhanced Time Processor Unit
with memory (eTPU)

System Clock up to 150 MHz

Performance (Dhrystone/2.1 MIPS) up to 144

Instruction/Data Cache 8 Kbytes

Static RAM (SRAM) 64 Kbytes

Interrupt Controllers (INTC) 2 2 2 2

Edge Port Module (EPORT) x x x x

External Interface Module (EIM) x x x x

4-channel Direct-Memory Access
(DMA)

SDRAM Controller x x x x

Fast Ethernet Controller (FEC) — — x x

Cryptography - Security module for
data packets processing

Watchdog Timer (WDT) x x x x

xxxx

16-ch

6K

xxxx

——— x

32-ch

6K

16-ch

6K

32-ch

6K

Four Periodic Interrupt Timers (PIT) x x x x

32-bit DMA Timers 4 4 4 4

QSPI xxxx

UART(s) 3333

2

Cxxxx

I

FlexCAN 2.0B - Controller-Area
Network communication module

General Purpose I/O Module
(GPIO)

JTAG - IEEE 1149.1 Test Access
Por t

Package 160 QFP

1212

xxxx

xxxx

196

MAPBGA

256

MAPBGA

256

MAPBGA

256

MAPBGA

2 Block Diagram

The superset device in the MCF523x family comes in a 256 mold array process ball grid array (MAPBGA)
package. Figure shows a top-level block diagram of the MCF5235, the superset device.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor2

(To/From PADI)

(To/From PADI)

(To/From

PAD I)

MUX

JTAG

TAP

(To/From PADI)

DREQ[2:0]

JTAG_EN

FAST

ETHERNET

CONTROLLER

(FEC)

4 CH DMA

DACK[2:0]

NEXUS

eTPU

(To/From SRAM backdoor)

Arbiter

UART

UART

0

1

DTIM

DTIM

0

V2 ColdFire CPU

BDM

64 Kbytes

SRAM

(8Kx16)x4

UART

1

DIV

INTC0

2

DTIM

2

INTC1

2

C

I

DTIM

EMAC

8 Kbytes

CACHE

(1Kx32)x2

QSPI

3

EIM

CHIP

SELECTS

EBI

SDRAMC

PORTS

(GPIO)

Features

SDRAMC

QSPI

I2C_SDA

I2C_SCL

UnTXD

UnRXD

DTnOUT

DTnIN

FEC

CANTX

PADI – Pin Muxing

CIM

UnRTS

nCTS

U

CANRX

eTPU

D[31:0]

A[23:0]

R/

W

CS[3:0]

TA

TSIZ[1:0]

TEA

BS[3:0]

Watchdog

Timer

SKHA

FlexCAN

(x2)

RNGA

MDHA

(To/From Arbiter backdoor)

PLL

CLKGEN

(To/From INTC)

Edge

Port

PIT0

PIT1 PIT2 PIT3

Cryptography

MCF5235 Block Diagram

Modules

3Features

For a detailed feature list see the MCF5235 Reference Manual (MCF5235RM).

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 3

Signal Descriptions

4 Signal Descriptions

This section describes signals that connect off chip, including a table of signal properties. For a more
detailed discussion of the MCF523x signals, consult the MCF5235 Reference Manual (MCF5235RM).

4.1 Signal Properties

Table 2 lists all of the signals grouped by function. The “Dir” column is the direction for the primary

function of the pin. Refer to Section 6, “Mechanicals/Pinouts and Part Numbers,” for package diagrams.

NOTE

In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., A24), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.

NOTE

The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO will default to their GPIO functionality.

Table 2. MCF523x Signal Information and Muxing

MCF5232

Signal Name GPIO Alternate 1 Alternate 2 Dir.

RESET — — — I 83 N13 T15 T15 T15

RSTOUT — — — O 82 P13 T14 T14 T14

EXTAL — — — I 86 M14 P16 P16 P16

XTAL — — — O 85 N14 R16 R16 R16

CLKOUT — — — O 89 K14 M16 M16 M16

CLKMOD[1:0] — — — I 19,20 G5, H5 J3, J2 J3, J2 J3, J2

RCON — — — I 79 K10 P13 P13 P13

External Memory Interface and Ports

A[23:21] PADDR[7:5] CS

[6:4] — O 126, 125,

1

160

QFP

Reset

Clock

Mode Selection

124

MCF5232

196

MAPBGA

B11, C11,

D11

MCF5233

256

MAPBGA

B14, C14,

A15

MCF5234

256

MAPBGA

B14, C14,

A15

MCF5235

256

MAPBGA

B14, C14,

A15

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor4

Table 2. MCF523x Signal Information and Muxing (continued)

Signal Descriptions

MCF5232

Signal Name GPIO Alternate 1 Alternate 2 Dir.

1

A[20:0] — — — O 123:115,

112:106,

160

QFP

102:98

MCF5232

MAPBGA

A12, B12,
C12, A13,
B13, B14,
C13, C14,
D12, D13,
D14, E11,
E12, E13,
E14, F12,
F13, F14,

G11, G12,

G13

D[31:16] — — — O 21:24, 26:30,

33:39

G1, G2, H1,

H2, H3, H4,

J1, J2, J3,

J4, K1, K2,

K3, K4, L1,

D[15:8] PDATAH[7:0] — — O 42:49, M1, N1, M2,

N2, P2, L3,

M3, N3,

D[7:0] PDATAL[7:0] — — O 50:52, 56:60 P3, M4, N4,

P4, L5, M5,

N5, P5

196

L2

MCF5233

256

MAPBGA

B15, B16,
C15, C16,
D16, D15,
D14, E16,

E15, E14,

E13, F15,

F14, F13,
G15, G14,
G13, H16,
H15, H14,

H13

K4, K3, K2,

K1, L4, L3,

L2, L1, M3,

M2, M1,

N2, N1, P2,

P1, R1

R2, T2, N3,
P3, R3, T3,

N4, P4,

R4, T4, P5,
R5, N6, P6,

R6, N7

MCF5234

256

MAPBGA

B15, B16,
C15, C16,
D16, D15,
D14, E16,
E15, E14,
E13, F15,

F14, F13,
G15, G14,
G13, H16,
H15, H14,

H13

K4, K3, K2,

K1, L4, L3,

L2, L1, M3,

M2, M1,

N2, N1, P2,

P1, R1

R2, T2, N3,
P3, R3, T3,

N4, P4,

R4, T4, P5,
R5, N6, P6,

R6, N7

MCF5235

256

MAPBGA

B15, B16,
C15, C16,
D16, D15,
D14, E16,
E15, E14,
E13, F15,

F14, F13,
G15, G14,
G13, H16,
H15, H14,

H13

K4, K3, K2,

K1, L4, L3,

L2, L1, M3,

M2, M1,

N2, N1, P2,

P1, R1

R2, T2, N3,
P3, R3, T3,

N4, P4,

R4, T4, P5,
R5, N6, P6,

R6, N7

BS

[3:0] PBS[7:4] CAS[3:0] — O 143:140 B6, C6, D7, C7C9, B9, A9,

A10

OE

PBUSCTL7 — — O 63 N6 T7 T7 T7

C9, B9, A9,

A10

C9, B9, A9,

A10

TA PBUSCTL6 — — I 97 H11 K14 K14 K14

TEA

R/W

PBUSCTL5 DREQ1 —I — J14 K13 K13 K13

PBUSCTL4 — — O 96 J13 L16 L16 L16

TSIZ1 PBUSCTL3 DACK1 — O —P6N8N8N8

TSIZ0 PBUSCTL2 DACK0 — O —P7P8P8P8

TS PBUSCTL1 DACK2 — O — H13 K16 K16 K16

TIP PBUSCTL0 DREQ0 — O — H12 K15 K15 K15

Chip Selects

CS

[7:4] PCS[7:4] — — O —B9, A10,

C10, A11

CS

[3:2] PCS[3:2] SD_CS[1:0] — O 134,133 A9, C9 B12, D12 B12, D12 B12, D12

CS1

CS0

PCS1 — — O 130 B10 B13 B13 B13

— — — O 129 D10 D13 D13 D13

C12, A13,

C13, A14

C12, A13,

C13, A14

C12, A13,

C13, A14

SDRAM Controller

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 5

Signal Descriptions

Table 2. MCF523x Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2 Dir.

SD_WE

SD_SCAS

SD_SRAS

PSDRAM5 — — O 93 K13 L13 L13 L13

PSDRAM4 — — O 92 K12 M15 M15 M15

PSDRAM3 — — O 91 K11 M14 M14 M14

1

MCF5232

160

QFP

MCF5232

196

MAPBGA

MCF5233

256

MAPBGA

MCF5234

256

MAPBGA

MCF5235

256

MAPBGA

SD_CKE PSDRAM2 — — O — E8 C10 C10 C10

SD_CS

[1:0] PSDRAM[1:0] — — O — L12, L13 N15, M13 N15, M13 N15, M13

External Interrupts Port

IRQ[7:3] PIRQ[7:3] — — I IRQ7=64

IRQ4=65

N7, M7, L7,

P8, N8

R8, T8, N9,

P9, R9

R8, T8, N9,

P9, R9

R8, T8, N9,

P9, R9

IRQ2 PIRQ2 DREQ2 — I —M8T9T9T9

IRQ1 PIRQ1 — — I 66 L8 N10 N10 N10

eTPU

TPUCH31 — ECOL — — —F3—F3

TPUCH30 — ECRS — — —F4—F4

TPUCH29 — ERXCLK — — —E3—E3

TPUCH28 — ERXDV — — —E4—E4

TPUCH[27:24] — ERXD[3:0] — — — D3, D4, C3,

C4

— D3, D4, C3,

C4

TPUCH23 — ERXER — — —D5—D5

TPUCH22 — ETXCLK — — —C5—C5

TPUCH21 — ETXEN — — —D6—D6

TPUCH20 — ETXER — — —C6—C6

TPUCH[19:16] — ETXD[3:0] — — — B6,B5, A5,

B7

TPUCH[15:0] — — — 11, 10, 7:2,

159:154,
152, 151

E2, E1, D1
D2, D3, C1,
C2, B1, B2,
A2, C3, B3,
A3, A4, C4,

BR

F2, E1, E2,
D1, D2, C1,
C2, B1, B2,
A2, B3, A3,
B4, A4, A6,

A7

— B6,B5, A5,

F2, E1, E2,
D1, D2, C1,
C2, B1, B2,
A2, B3, A3,
B4, A4, A6,

F2, E1, E2,
D1, D2, C1,
C2, B1, B2,
A2, B3, A3,
B4, A4, A6,

A7

B7

A7

TCRCLK PETPU2 — — 12 E3 F1 F1 F1

UTPUODIS PETPU1 — — — H10 J13 J13 J13

LTPUODIS PETPU0 — — — G10 J14 J14 J14

FEC

EMDIO PFECI2C2 I2C_SDA U2RXD I/O — — —C7C7

EMDC PFECI2C3 I2C_SCL U2TXD O — — —D7D7

ECOL — — — I — — —F3F3

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor6

Table 2. MCF523x Signal Information and Muxing (continued)

Signal Descriptions

Signal Name GPIO Alternate 1 Alternate 2 Dir.

1

MCF5232

160

QFP

MCF5232

196

MAPBGA

MCF5233

256

MAPBGA

MCF5234

256

MAPBGA

MCF5235

256

MAPBGA

ECRS — — — I — — —F4F4

ERXCLK — — — I — — —E3E3

ERXDV — — — I — — —E4E4

ERXD[3:0] — — — I — — —D3, D4, C3, C4D3, D4, C3,

C4

ERXER — — — I — — —D5D5

ETXCLK — — — I — — —C5C5

ETXEN — — — O — — —D6D6

ETXER — — — O — — —C6C6

ETXD[3:0] — — — O — — — B6, B5, A5, B7B6, B5, A5,

B7

Feature Control

eTPU/EthENB — — — I ————M4

I2C

I2C_SDA PFECI2C1 CAN0RX — I/O — J12 L15 L15 L15

I2C_SCL PFECI2C0 CAN0TX — I/O — J11 L14 L14 L14

DMA

DACK[2:0] and DREQ[2:0] do not have a dedicated bond pads.

— — — — —

Please refer to the following pins for muxing:

TS and DT2OUT for DACK2, TSIZ1and DT1OUT for DACK1,

TSIZ0 and DT0OUT for DACK0, IRQ2

and DT2IN for DREQ2,

TEA and DT1IN for DREQ1, and TIP and DT0IN for DREQ0.

QSPI

QSPI_CS1 PQSPI4 SD_CKE — O 139 B7 B10 B10 B10

QSPI_CS0 PQSPI3 — — O 147 A6 D9 D9 D9

QSPI_CLK PQSPI2 I2C_SCL — O 148 C5 B8 B8 B8

QSPI_DIN PQSPI1 I2C_SDA — I 149 B5 C8 C8 C8

QSPI_DOUT PQSPI0 — — O 150 A5 D8 D8 D8

UARTs

U2TXD PUARTH1 CAN1TX — O —A8D11D11D11

U2RXD PUARTH0 CAN1RX — I —A7D10D10D10

U1CTS PUARTL7 U2CTS — I —B8C11C11C11

U1RTS PUARTL6 U2RTS — O —C8B11B11B11

U1TXD PUARTL5 CAN0TX — O 135 D9 A12 A12 A12

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 7

Signal Descriptions

Table 2. MCF523x Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2 Dir.

1

MCF5232

160

QFP

MCF5232

196

MAPBGA

MCF5233

256

MAPBGA

MCF5234

256

MAPBGA

MCF5235

256

MAPBGA

U1RXD PUARTL4 CAN0RX — I 136 D8 A11 A11 A11

U0CTS PUARTL3 — — I — F3 G1G1G1

U0RTS PUARTL2 — — O —G3H3H3H3

U0TXD PUARTL1 — — O 14 F1 H2 H2 H2

U0RXD PUARTL0 — — I 13 F2 G2 G2 G2

DMA Timers

DT3IN PTIMER7 U2CTS QSPI_CS2 I — H14 J15 J15 J15

DT3OUT PTIMER6 U2RTS QSPI_CS3 O — G14 J16 J16 J16

DT2IN PTIMER5 DREQ2 DT2OUT I —M9P10P10P10

DT2OUT PTIMER4 DACK2 — O —L9R10R10R10

DT1IN PTIMER3 DREQ1 DT1OUT I —L6P7P7P7

DT1OUT PTIMER2 DACK1 — O —M6R7R7R7

DT0IN PTIMER1 DREQ0 — I — E4 G4G4G4

DT0OUT PTIMER0 DACK0 — O — F4 G3G3G3

BDM/JTAG

2

DSCLK — TRST — I 70 N9 N11 N11 N11

PSTCLK — TCLK — O 68 P9 T10 T10 T10

BKPT — TMS — I 71 P10 P11 P11 P11

DSI — TDI — I 73 M10 T11 T11 T11

DSO — TDO — O 72 N10 R11 R11 R11

JTAG_EN — — — I 78 K9 N13 N13 N13

DDATA[3:0] — — — O —M12, N12,

P12, L11

PST[3:0] — — — O 77:74 M11, N11,

P11, L10

N14, P14,

T13, R13

T12, R12,

P12, N12

N14, P14,

T13, R13

T12, R12,

P12, N12

N14, P14,

T13, R13

T12, R12,

P12, N12

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor8

Table 2. MCF523x Signal Information and Muxing (continued)

Design Recommendations

MCF5232

Signal Name GPIO Alternate 1 Alternate 2 Dir.

TEST — — — I 18 F5 J4 J4 J4

PLL_TEST — — — I —R14R14R14

VDDPLL — — — I 87 M13 P15

VSSPLL — — — I 84 L14 R15

OVDD — — — I 1, 9, 17, 32,

VSS — — — I 8, 16, 25, 31,

1

160

QFP

Test

Power Supplies

41, 55, 62,
69, 81, 90,

95, 105, 114,

128, 132,

138, 146

40, 54, 61,
67, 80, 88,

94, 104, 113,

127, 131,
137, 145,

153, 160

MCF5232

196

MAPBGA

E5, E7,
E10, F7, F9,
G6, G8, H7,

H8, H9, J6,

J8, J10, K5,

K6, K8

A1, A14,

E6, E9, F6,

F8, F10,

G7, G9, H6,

J5, J7, J9,

K7, P1, P14

MCF5233

256

MAPBGA

E6:11, F5, F7:10, F12, G5, G6, G11,

G12, H5, H6, H11, H12, J5, J6, J11,

J12, K5, K6, K11, K12, L5, L7:10,

A1, A16, E5, E12, F6, F11, F16,

G7:10, H7: 10, J1, J7:10, K7:10, L6,

L11, M5, M12, N16, T1, T6, T16

MCF5234

256

MAPBGA

L12, M6:M11

MCF5235

256

MAPBGA

VDD — — — I 15, 53, 103,

144

1

Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception
of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM.

2

If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning
these pins.

D6, F11,

G4, L4

A8, G16, H1, T5

5 Design Recommendations

5.1 Layout

• Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power
and ground planes for the MCF523x.

• See application note AN1259, System Design and Layout Techniques for Noise Reduction in
Processor-Based Systems.

• Match the PC layout trace width and routing to match trace length to operating frequency and board
impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the
PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk
analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace
and separation. Clocks get extra separation and more precise balancing.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 9

Design Recommendations

5.2 Power Supply

•33µF, 0.1 µF, and 0.01 µF across each power supply

5.2.1 Supply Voltage Sequencing and Separation Cautions

Figure 1 shows situations in sequencing the I/O VDD (OVDD), PLL VDD (PLLVDD), and Core VDD (VDD).

OVDD is specified relative to VDD.

OV

3.3V
Supplies Stable

2.5V

DD

1.5V

DC Power Supply Voltage

0

Notes:

1.

2.

3.

4.

Figure 1. Supply Voltage Sequencing and Separation Cautions

1

2

VDD should not exceed OVDD or PLLVDD by more than 0.4 V
at any time, including power-up.
Recommended that VDD/PLLVDD should track OVDD up to

0.9 V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (OVDD,
VDD, or PLLVDD) by more than 0.5 V at any time, including during power-up.
Use 1 ms or slower rise time for all supplies.

VDD, PLLV

DD

Time

5.2.1.1 Power Up Sequence

If OVDD are powered up with VDD at 0 V, then the sense circuits in the I/O pads will cause all pad output
drivers connected to the OV
powers up before V

must powered up. VDD should not lead the OVDD or PLLVDD by more than 0.4 V

DD

during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times
on the power supplies should be slower than 1 µs to avoid turning on the internal ESD protection clamp
diodes.

to be in a high impedance state. There is no limit on how long after OVDD

DD

The recommended power up sequence is as follows:

1. Use 1 µs or slower rise time for all supplies.

2. V

/PLLVDD and OVDD should track up to 0.9 V, then separate for the completion of ramps with

DD

OV

going to the higher external voltages. One way to accomplish this is to use a low drop-out

DD

voltage regulator.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor10

Design Recommendations

5.2.1.2 Power Down Sequence

If VDD/PLLVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to
be in a high impedance state. There is no limit on how long after VDD and PLLVDD power down before
OV
power down or there will be undesired high current in the ESD protection diodes. There are no
requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

must power down. VDD should not lag OVDD or PLLVDD going low by more than 0.4 V during

DD

1. Drop V

/PLLVDD to 0 V.

DD

2. Drop OVDD supplies.

5.3 Decoupling

• Place the decoupling caps as close to the pins as possible, but they can be outside the footprint of
the package.

• 0.1 µF and 0.01 µF at each supply input

5.4 Buffering

• Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses
when excessive loading is expected. See Section 7, “Preliminary Electrical Characteristics.”

5.5 Pull-up Recommendations

• Use external pull-up resistors on unused inputs. See pin table.

5.6 Clocking Recommendations

• Use a multi-layer board with a separate ground plane.

• Place the crystal and all other associated components as close to the EXTAL and XTAL (oscillator
pins) as possible.

• Do not run a high frequency trace around crystal circuit.

• Ensure that the ground for the bypass capacitors is connected to a solid ground trace.

• Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop currents
in the vicinity of the crystal.

• Tie the ground pin to the most solid ground in the system.

• Do not connect the trace that connects the oscillator and the ground plane to any other circuit
element. This tends to make the oscillator unstable.

• Tie XTAL to ground when an external oscillator is clocking the device.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 11

Design Recommendations

5.7 Interface Recommendations

5.7.1 SDRAM Controller

5.7.1.1 SDRAM Controller Signals in Synchronous Mode

Table 3 shows the behavior of SDRAM signals in synchronous mode.

Table 3. Synchronous DRAM Signal Connections

Signal Description

SD_SRAS

SD_SCAS

DRAMW

SD_CS

SD_CKE Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of

BS

CLKOUT Bus clock output. Connects to the CLK input of SDRAMs.

Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be

latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM
SD_SRAS
be interfaced to the SDRAM SD_SRAS signals.

Synchronous column address strobe. Indicates a valid column address is present and can be

latched by the SDRAM. SD_SCAS
SD_SCAS on the SDRAM.

DRAM read/write. Asserted for write operations and negated for read operations.

[1:0] Row address strobe. Select each memory block of SDRAMs connected to the MCF523x. One

SD_CS signal selects one SDRAM block and connects to the corresponding CS signals.

SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can
enter a power-down mode where operations are suspended or they can enter self-refresh mode.
SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing,
setting COC allows SD_CKE to provide command-bit functionality.

[3:0] Column address strobe. For synchronous operation, BS[3:0] function as byte enables to the

SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs.

. Do not confuse SD_SRAS with the DRAM controller’s SD_CS[1:0], which should not

should be connected to the corresponding signal labeled

5.7.1.2 Address Multiplexing

See the SDRAM controller module chapter in the MCF5235 Reference Manual for details on address
multiplexing.

5.7.2 Ethernet PHY Transceiver Connection

The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10
Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3
standard defines and the FEC module supports 18 signals. These are shown in Table 4.

Table 4. MII Mode

Signal Description MCF523x Pin

Transmit clock ETXCLK

Transmit enable ETXEN

Transmit data ETXD[3:0]

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor12

Design Recommendations

Table 4. MII Mode (continued)

Signal Description MCF523x Pin

Transmit error ETXER

Collision ECOL

Carrier sense ECRS

Receive clock ERXCLK

Receive enable ERXDV

Receive data ERXD[3:0]

Receive error ERXER

Management channel clock EMDC

Management channel serial data EMDIO

The serial mode interface operates in what is generally referred to as AMD mode. The MCF523x
configuration for seven-wire serial mode connections to the external transceiver are shown in Table 5.

Table 5. Seven-Wire Mode Configuration

Signal Description MCF523x Pin

Transmit clock ETXCLK

Transmit enable ETXEN

Transmit data ETXD[0]

Collision ECOL

Receive clock ERXCLK

Receive enable ERXDV

Receive data ERXD[0]

Unused, configure as PB14 ERXER

Unused input, tie to ground ECRS

Unused, configure as PB[13:11] ERXD[3:1]

Unused output, ignore ETXER

Unused, configure as PB[10:8] ETXD[3:1]

Unused, configure as PB15 EMDC

Input after reset, connect to ground EMDIO

Refer to the M523xEVB evaluation board user’s manual for an example of how to connect an external
PHY. Schematics for this board are accessible at the MCF5235 site by navigating to:

http://www.freescale.com/coldfire.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 13

Mechanicals/Pinouts and Part Numbers

5.7.3 FlexCAN

The FlexCAN module interface to the CAN bus is composed of 2 pins: CANTX and CANRX, which are
the serial transmitted data and the serial received data. The use of an external CAN transceiver to interface
to the CAN bus is generally required. The transceiver is capable of driving the large current needed for the
CAN bus and has current protection, against a defective CAN bus or defective stations.

5.7.4 BDM

Use the BDM interface as shown in the M523xEVB evaluation board user’s manual. The schematics for
this board are accessible at the Freescale website at: http://www.freescale.com/coldfire.

6 Mechanicals/Pinouts and Part Numbers

This section contains drawings showing the pinout and the packaging and mechanical characteristics of
the MCF523x devices. See Table 2 for a list the signal names and pin locations for each device.

6.1 Pinout—196 MAPBGA

The following figure shows a pinout of the MCF5232CVMxxx package.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor14

Mechanicals/Pinouts and Part Numbers

1234567891011121314

A

VSS TPUCH6 TPUCH3 TPUCH2

B TPUCH8 TPUCH7 TPUCH4 TPUCH0

C TPUCH10 TPUCH9 TPUCH5 TPUCH1 QSPI_CLK BS2

D TPUCH13 TPUCH12 TPUCH11

E TPUCH14 TPUCH15 TCRCLK DT0IN

F U0TXD U0RXD U0CTS

G D31 D30 U0RTS

H D29 D28 D27 D26 CLKMOD0

NC NC VDD BS1

DT0OUT TEST VSS OVDD VSS OVDD VSS VDD A5 A4 A3 F

VDD C LKMOD1 OVDD VSS OVDD VSS

QSPI_
DOUT

QSPI_

OVDD VSS OVDD SD_CKE VSS OVDD A9 A8 A7 A6 E

QSPI_CS0 U2RXD U2TXD CS3

DIN

BS3

VSS OVDD OVDD OVDD

CS6 CS4 A20 A17 VSS A

QSPI_CS1 U1CTS CS7 CS1 A23 A19 A16 A15 B

BS0 U1RTS CS2 CS5 A22 A18 A14 A13 C

U1RXD/

CAN0RX

U1TXD/

CAN0TX

CS0

LTP U
ODIS

UTPU

ODIS

A21 A12 A11 A10 D

A2 A1 A0 DT3OUT G

TA

TIP TS DT3IN H

J D25 D24 D23 D22

K D21 D20 D19 D18

L D17 D16 D10

M D15 D13 D9 D6 D2 DT1OUT IRQ6

N D14 D12 D8 D5 D1 OE

VSS D11 D7 D4 D0 TSIZ1 TSIZ0 IRQ4

P

1234567891011121314

VDD D3 DT1IN IRQ5 IRQ1 DT2OUT PST0 DDATA0 SD_CS1 SD_CS0 VSSPLL L

VSS OVDD VSS OVDD VSS OVDD I2C_SCL I2C_SDA R/W TEA J

OVDD OVDD VSS OVDD JTAG_EN RCON SD_SRAS SD_SCAS SD_WE CLKOUT K

IRQ2 DT2IN TDI/DSI PST3 DDATA3 VDDPLL EXTAL M

IRQ7 IRQ3

TRST/

DSCLK

TCLK/

PSTCLK

TDO/DSO PST2 DDATA2 RESET

TMS/

BKPT

PST1 DDATA1 RSTOUT VSS P

Figure 2. MCF5232CVMxxx Pinout (196 MAPBGA)

6.2 Package Dimensions—196 MAPBGA

Figure 3 shows MCF5232CVMxxx package dimensions.

XTAL N

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 15

Mechanicals/Pinouts and Part Numbers

X

Y

Laser mark for pin 1
identification in
this area

D

M

K

NOTES:

1. Dimensions are in millimeters.

2. Interpret dimensions and tolerances
per ASME Y14.5M, 1994.

3. Dimension b is measured at the
maximum solder ball diameter,
parallel to datum plane Z.

4. Datum Z (seating plane) is defined
by the spherical crowns of the solder
balls.

5. Parallelism measurement shall
exclude any effect of mark on top
surface of package.

E

Millimeters

DIM

Min Max

1.25 1.60

A

0.27 0.47

A1

A2

M

TOL

e13X

S

14 13 12 11 5 4 3 2

S

e13X

3

Metalized mark for
pin 1 identification

1610 9

in this area

A

B

C

D

E

F

G

H

J

K

L

M

N

P

A2

A

A1

b

D

E

e

S

Z

Detail K

Rotated 90° Clockwise

1.16 REF

0.45 0.55

15.00 BSC

15.00 BSC

1.00 BSC

0.50 BSC

4

5

0.20 Z

0.10 Z

196X

b196X

X0.15 YZ

View M-M

0.08 Z

Figure 3. 196 MAPBGA Package Dimensions (Case No. 1128A-01)

6.2.1 Pinout—256 MAPBGA

Figure 4 through Figure 6 show pinouts of the MCF5233CVMxxx, MCF5234CVMxxx, and

MCF5235CVMxxx packages.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor16

Mechanicals/Pinouts and Part Numbers

1 2 3 4 5 6 7 8 9 1011121314 15 16

A

VSS TPUCH6 TPUCH4 TPUCH2 TPUCH17 TPUCH1 TPUCH0 VDD BS1 BS0

U1RXD/

CAN0RX

U1TXD/

CAN0TX

CS6

CS4 A21 VSS A

B

TPUCH8 TPUCH7 TPUCH5 TPUCH3 TPUCH18 TPUCH19 TPUCH16

C

TPUCH10 TPUCH9 TPUCH25 TPUCH24 TPUCH22 TPUCH20

D

TPUCH12 TPUCH11 TPUCH27 TPUCH26 TPUCH23 TPUCH21

E

TPUCH14 TPUCH13 TPUCH29 TPUCH28 VSS OVDD OVDD OVDD OVDD OVDD OVDD VSS A10 A11 A12 A13 E

F

TCRCLK TPUCH15 TPUCH31 TPUCH30 OVDD VSS OVDD OVDD OVDD OVDD VSS OVDD A7 A8 A9 VSS F

G

U0CTS

H

VDD U0TXD U0RTS NC OVDD OVDD VSS VSS VSS VSS OVDD OVDD A0 A1 A2 A3 H

J

VSS

K

D28 D29 D30 D31

U0RXD DT0OUT DT0IN OVDD OVDD VSS VSS VSS VSS OVDD OVDD A4 A5 A6 VDD G

CLK

MOD0

CLK

MOD1

TEST

OVDD OVDD VSS VSS VSS VSS OVDD OVDD

OVDD OVDD VSS VSS VSS VSS OVDD OVDD TEA TA TIP TS K

I2C_SDA/

U2RXD

I2C_SCL/

U2TXD

QSPI_

CLK

QSPI_

DIN

QSPI_

DOUT

QSPI_

BS2

BS3

SD_CKE U1CTS CS7 CS5 A22 A18 A17 C

QSPI_

U2RXD/

CS0

CAN1RX

CS1

U1RTS

U2TXD/

CAN1TX

CS3 CS1 A23 A20 A19 B

CS2

CS0 A14 A15 A16 D

UTPU

ODIS

LTP U
ODIS

DT3IN DT3OUT J

L

D24 D25 D26 D27

M

D21 D22 D23

N

D19 D20 D13 D9

P

D17 D18 D12 D8 D5 D2 DT1IN TSIZ0 IRQ4

R

D16 D15 D11 D7 D4 D1 DT1OUT IRQ7

T

VSS D14 D10 D6 VDD VSS OE IRQ6 IRQ2

1 2 3 4 5 6 7 8 9 1011121314 15 16

NC VSS OVDD OVDD OVDD OVDD OVDD OVDD VSS

OVDD VSS OVDD OVDD OVDD OVDD VSS OVDD SD_WE

NC D3 D0 TSIZ1 IRQ5 IRQ1

DT2IN

IRQ3 DT2OUT

TCLK/

PSTCLK

TRST/

DSCLK

TMS/
BKPT

TDO/

TDI/DSI PST3 DDATA1 RSTOUT

PST0

PST1 RCON DDATA2 VDDPLL EXTAL P

PST2 DDATA0

DSO

SD_
CS0

JTAG_

EN

I2C_SCL/

CAN0TX

DDATA3 SD_CS1

I2C_SDA/

CAN0RX

SD_

SRAS

PLL_

VSSPLL XTAL R

TEST

RESET VSS T

SD_

SCAS

Figure 4. MCF5233CVMxxx Pinout (256 MAPBGA)

R/W

CLKOUT M

VSS N

L

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 17

Mechanicals/Pinouts and Part Numbers

1 2 3 4 5 6 7 8 9 10111213 14 15 16

VSS TPUCH6 TPUCH4 TPUCH2 ETXD1 TPUCH1 TPUCH0 VDD BS1 BS0

A

TPUCH8 TPUCH7 TPUCH5 TPUCH3 ETXD2 ETXD3 ETXD0

B

TPUCH10 TPUCH9 ERXD1 ERXD0 ETXCLK ETXER EMDIO

C

TPUCH12 TPUCH11 ERXD3 ERXD2 ERXER ETXEN EMDC

D

TPUCH14 TPUCH13 ERXCLK ERXDV VSS OVDD OVDD OVDD OVDD OVDD OVDD VSS A10 A11 A12 A13 E

E

TCRCLK TPUCH15 ECOL ECRS OVDD VSS OVDD OVDD OVDD OVDD VSS OVDD A7 A8 A9 VSS F

F

G U0CTS

VDD U0TXD U0RTS NC OVDD OVDD VSS VSS VSS VSS OVDD OVDD A0 A1 A2 A3 H

H

VSS

J

U0RXD DT0OUT DT0IN OVDD OVDD VSS VSS VSS VSS OVDD OVDD A4 A5 A6 VDD G

CLK

MOD0

CLK

MOD1

TEST

OVDD OVDD VSS VSS VSS VSS OVDD OVDD

QSPI_

CLK

QSPI_

DIN

QSPI_
DOUT

BS2

BS3

SD_CKE U1CTS CS7 CS5 A22 A18 A17 C

QSPI_

CS0

U1RXD/

CAN0RX

QSPI_

CS1

U2RXD U2TXD CS2

U1RTS

U1TXD/

CAN0TX

CS3 CS1 A23 A20 A19 B

CS6

CS0 A14 A15 A16 D

UTPU

ODIS

CS4 A21 VSS A

LTP U
ODIS

DT3IN DT3OUT J

K D28 D29 D30 D31

L D24 D25 D26 D27

M D21 D22 D23

N D19 D20 D13 D9

P D17 D18 D12 D8 D5 D2 DT1IN TSIZ0 IRQ4

R D16 D15 D11 D7 D4 D1 DT1OUT IRQ7

T

VSS D14 D10 D6 VDD VSS OE IRQ6 IRQ2

1 2 3 4 5 6 7 8 9 10111213 14 15 16

NC VSS OVDD OVDD OVDD OVDD OVDD OVDD VSS SD_CS0

OVDD OVDD VSS VSS VSS VSS OVDD OVDD TEA TA TIP TS K

OVDD VSS OVDD OVDD OVDD OVDD VSS OVDD SD_WE

NC D3 D0 TSIZ1 IRQ5 IRQ1

DT2IN

IRQ3 DT2OUT

TCLK/

PSTCLK

TRST/

DSCLK

TMS/
BKPT

TDO/

DSO

TDI/DSI PST3 DDATA1

JTAG_

PST0

PST1 RCON DDATA2 VDDPLL EXTAL P

PST2 DDATA0

EN

I2C_SCL/

CAN0TX

DDATA3 SD_CS1

SD_

SRAS

PLL_

TEST

RST
OUT

I2C_SDA/

CAN0RX

SD_

SCAS

VSSPLL XTAL R

RESET VSS T

Figure 5. MCF5234CVMxxx Pinout (256 MAPBGA)

R/W

CLKOUT M

VSS N

L

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor18

Mechanicals/Pinouts and Part Numbers

12345678910111213141516

TEST

TPUCH17/

ETXD1

TPUCH18/

ETXD2

TPUCH22/

ETXCLK

TPUCH23/

ERXER

OVDD VSS OVDD OVDD OVDD OVDD VSS OVDD A7 A8 A9 VSS F

OVDD OVDD VSS VSS VSS VSS OVDD OVDD

TPUCH1 TPUCH0 VDD BS1 BS0

TPUCH19/

ETXD3

TPUCH20/

ETXER

TPUCH21/

ETXEN

VSS OVDD OVDD OVDD OVDD OVDD OVDD VSS A10 A11 A12 A13 E

TPUCH16/

ETXD0

I2C_SDA/

U2RXD/

EMDIO

I2C_SCL/

U2TXD/

EMDC

QSPI_

CLK

QSPI_

DIN

QSPI_
DOUT

BS2

BS3

SD_CKE U1CTS CS7 CS5 A22 A18 A17 C

QSPI_

U2RXD/

CS0

CAN1RX

VSS TPUCH6 TPUCH4 TPUCH2

A

TPUCH8 TPUCH7 TPUCH5 TPUCH3

B

C

TPUCH10 TPUCH9

TPUCH12 TPUCH11

D

E

TPUCH14 TPUCH13

TCRCLK TPUCH15

F

G U0CTS

VDD U0TXD U0RTS NC OVDD OVDD VSS VSS VSS VSS OVDD OVDD A0 A1 A2 A3 H

H

J

U0RXD DT0OUT DT0IN OVDD OVDD VSS VSS VSS VSS OVDD OVDD A4 A5 A6 VDD G

VSS

TPUCH25/

ERXD1

TPUCH27/

ERXD3

TPUCH29/

ERXCLK

TPUCH31/

CLK

MOD0

ECOL

CLK

MOD1

TPUCH24/

ERXD0

TPUCH26/

ERXD2

TPUCH2/

ERXDV

TPUCH30/

ECRS

QSPI_

CS1

U1RXD/

CAN0RX

U1RTS

U2TXD/

CAN1TX

U1TXD/

CAN0TX

CS3 CS1 A23 A20 A19 B

CS2

CS6

CS0 A14 A15 A16 D

UTPU

ODIS

CS4 A21 VSS A

LTP U
ODIS

DT3IN DT3OUT J

K D28 D29 D30 D31

L D24 D25 D26 D27

M D21 D22 D23

N D19 D20 D13 D9

P D17 D18 D12 D8 D5 D2 DT1IN TSIZ0 IRQ4

R D16 D15 D11 D7 D4 D1 DT1OUT IRQ7

T

VSS D14 D10 D6 VDD VSS OE IRQ6 IRQ2

12345678910111213141516

eTPU/

EthENB

OVDD OVDD VSS VSS VSS VSS OVDD OVDD TEA TA TIP TS K

OVDD VSS OVDD OVDD OVDD OVDD VSS OVDD SD_WE

VSS OVDD OVDD OVDD OVDD OVDD OVDD VSS SD_CS0

NC D3 D0 TSIZ1 IRQ5 IRQ1

DT2IN

IRQ3 DT2OUT

TCLK/

PSTCLK

TRST/

DSCLK

TMS/
BKPT

TDO/

DSO

TDI/DSI PST3 DDATA1 RSTOUT

JTAG_

PST0

PST1 RCON DDATA2 VDDPLL EXTAL P

PST2 DDATA0

EN

I2C_SCL/

CAN0TX

DDATA3 SD_CS1

I2C_SDA/

CAN0RX

SD_

SRAS

PLL_

VSSPLL XTAL R

TEST

RESET VSS T

SD_

SCAS

Figure 6. MCF5235CVMxxx Pinout (256 MAPBGA)

R/W

CLKOUT M

VSS N

L

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 19

Mechanicals/Pinouts and Part Numbers

6.2.2 Package Dimensions—256 MAPBGA

Figure 7 shows MCF5235CVMxxx, MCF5234CVMxxx, and MCF5233CVMxx package dimensions.

X

Y

D

LASER MARK FOR PIN A1
IDENTIFICATION IN
THIS AREA

M

K

A2

A

5

Z0.30

A1

4

E

M

0.20

S

e15X

e15X

S

METALIZED MARK FOR
PIN A1 IDENTIFICATION
IN THIS AREA

123456710111213141516

A
B
C
D

E

F
G
H

J
K

L
M
N

P
R

T

3

b256X

M

0.25 YZ

M

0.10XZ

Z

ROTATED 90 CLOCKWISE

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTE RPRET DIMENSIONS AND

3. DIMENSION b IS MEASURED AT THE

4. DATUM Z (SEATING PLANE) IS DEFINED BY

5. PAR ALLELISM MEASUREMENT SHALL

VIEW M-M

256X

Z

0.15

DETAIL K

°

TOLERANCES PER ASME Y14.5M, 1994.

MAXIMUM SOLDER BALL DIAMETER,
PARALLEL TO DATUM PLANE Z.

THE SPHERICAL CROWNS OF THE SOLDER
BALLS.

EXCLUDE ANY EFFECT OF MARK ON TOP
SURFACE OF PACKAGE.

MILLIMETERS

DIM MIN MAX

A 1.25 1.60

A1

0.27 0.47

1.16 REF

A2

0.40 0.60

b

17.00 BSC

D

17.00 BSC

E
e 1.00 BSC

0.50 BSC

S

Figure 7. 256 MAPBGA Package Outline

6.3 Pinout—160 QFP

Figure 8 shows a pinout of the MCF5232CABxxx package.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor20

OVDD
TPUCH8
TPUCH9

TPUCH10
TPUCH11
TPUCH12
TPUCH13

VSS

OVDD

TPUCH14
TPUCH15

TCRCLK

U0RXD

U0TXD

VDD

VSS

OVDD

TEST
CLKMOD1
CLKMOD0

D31
D30
D29
D28
VSS
D27
D26
D25
D24
D23
VSS

OVDD

D22
D21
D20
D19
D18
D17
D16
VSS

Mechanicals/Pinouts and Part Numbers

VSS

TPUCH7

TPUCH6

TPUCH5

TPUCH4

TPUCH3

TPUCH2

VSS

TPUCH1

TPUCH0

QSPI_DOUT

QSPI_DIN

QSPI_CLK

QSPI_CS0

OVDD

VSS\OVSS

VDD

BS3

BS2

BS1

BS0

SD_CKE\QSPI_CS1

OVDD

VSS

U1RXD\CAN0RX

U1TXD\CAN0TX

CS3

CS2

OVDD

VSS

CS1

CS0

OVDD

VSS

A23

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

414243444546474849505152535455565758596061626364656667686970717273747576777879

MCF5232

126

A22

A21

A20

A19

A18

125

124

123

122

121
120

A17

119

A16

118

A15

117

A14

116

A13

115

A12

114

OVDD

113

VSS

112

A11

111

A10

110

A9

109

A8

108

A7

107

A6

106

A5

105

OVDD

104

VSS/OVSS

103

VDD

102

A4

101

A3

100

A2

99

A1

98

A0

97

TA

96

R/W

95

OVDD

94

VSS

93

SD_WE

92

SD_SCAS

91

SD_SRAS

90

OVDD

89

CLKOUT

88

VSS

87

VDDPLL

86

EXTAL

85

XTAL

84

VSSPLL

83

RESET

82

RSTOUT/PLL_TEST

81

OVDD

80

D15

OVDD

D9D8D7D6D5

D11

D14

D13

D12

D10

VDD

D4D3D2D1D0

OVDD

VSS\OVSS

VSS

OE

OVDD

IRQ7

IRQ4

IRQ1

VSS

OVDD

TCLK\PSTCLK

TMS\BKPT

TRST\DSCLK

TDO/DSO

PST0

PST1

TDI/DSI

VSS

PST2

PST3

RCON

JTAG_EN

Figure 8. MCF5232CABxxx Pinout (160 QFP)

6.4 Package Dimensions—160 QFP

Figure 9 shows MCF5232CAB80 package dimensions.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 21

Mechanicals/Pinouts and Part Numbers

LY

Z

–C–

A-B

V

0.20 (0.008)

S

D

S

A-B

H

M

0.20 (0.008)

–A–, –B–, –D–

B

B

P

G

S

D

S

–A–

–B–

L

DETAIL A

A-B

H

M

B

0.20 (0.008)

DETAIL A

A

0.20 (0.008) A-B DCM

0.20 (0.008)

A-B

S

S

0.20 (0.008)

M

S

A-B DC

S

N

S

DETAIL C

BASE
METAL

F

J

D

–H–

0.13 (0.005)

M

A-B DC

S

S

SECTION B–B

MILLIMETERS

×

M

TOP &

BOTTOM

×

U

E

C

–H–

W

H

0.110 (0.004)

K

X

DETAIL C

NOTES

1. DIMENSIONING AND TOLERINCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER

T

3. DATUM PLAN -H- IS LOCATED AT BOTTOM OF

R

Q

LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.

×

4. DATUMS -A-, -B-, AND -D- TO BE DETERMINED AT

DATUM PLANE -H-.

5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -C-.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE -H-.

7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.

DIM MIN MAX MIN MAX

A

27.90 28.10 1.098 1.106

27.90 28.10 1.098 1.106

B

3.35 3.85

3.35 3.85 0.132 1.106

C
D
E
F

0.65 BSC 0.026 REF

G

H
J
K

25.35 BSC 0.998 REF

L

°16°5°16°

M

5

N

0.325 BSC 0.013 REF

P

°7°

Q

0

R
S

31.00 31.40 1.220 1.236

T

°

U

0

V

31.00 31.40 1.220 1.236

W

1.60 REF 0.063 REF

X
Y

1.33 REF 0.052 REF

1.33 REF 0.052 REF

Z

INCHES

0.009 0.0150.22 0.38

0.126 0.1383.20 3.50

0.009 0.0130.22 0.33

0.010 0.0140.25 0.35

0.004 0.0090.11 0.23

0.028 0.0350.70 0.90

0.004 0.0070.11 0.19

0°7

0.005 0.0120.13 0.30

0.005 —0.13 —

—0°—

0.016 —0.4 —

°

Case 864A-03

Figure 9. 160 QFP Package Dimensions

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor22

6.5 Ordering Information

Table 6. Orderable Part Numbers

Preliminary Electrical Characteristics

Freescale Part

Number

MCF5232CAB80 MCF5232 RISC Microprocessor, 160 QFP 80MHz –40

MCF5232CVM100 MCF5232 RISC Microprocessor, 196 MAPBGA 100MHz –40

MCF5232CVM150 MCF5232 RISC Microprocessor, 196 MAPBGA 150MHz –40

MCF5233CVM100 MCF5233 RISC Microprocessor, 256 MAPBGA 100MHz –40

MCF5233CVM150 MCF5233 RISC Microprocessor, 256 MAPBGA 150MHz –40

MCF5234CVM100 MCF5234 RISC Microprocessor, 256 MAPBGA 100MHz –40

MCF5234CVM150 MCF5234 RISC Microprocessor, 256 MAPBGA 150MHz –40

MCF5235CVM100 MCF5235 RISC Microprocessor, 256 MAPBGA 100MHz –40

MCF5235CVM150 MCF5235 RISC Microprocessor, 256 MAPBGA 150MHz –40

Description Speed Temperature

° to +85° C

° to +85° C

° to +85° C

° to +85° C

° to +85° C

° to +85° C

° to +85° C

° to +85° C

° to +85° C

7 Preliminary Electrical Characteristics

This chapter contains electrical specification tables and reference timing diagrams for the MCF5235
microcontroller unit. This section contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications of MCF5235.

The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however
for production silicon these specifications will be met. Finalized specifications will be published after
complete characterization and device qualifications have been completed.

NOTE

The parameters specified in this processor document supersede any values
found in the module specifications.

7.1 Maximum Ratings

Table 7. Absolute Maximum Ratings

Rating Symbol Value Unit

Core Supply Voltage V

Pad Supply Voltage OV

Clock Synthesizer Supply Voltage V

Digital Input Voltage

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 23

3

DD

DD

DDPLL

V

IN

1, 2

– 0.5 to +2.0 V

– 0.3 to +4.0 V

– 0.3 to +4.0 V

– 0.3 to + 4.0 V

Preliminary Electrical Characteristics

Table 7. Absolute Maximum Ratings

1, 2

(continued)

Rating Symbol Value Unit

Instantaneous Maximum Current
Single pin limit (applies to all pins)

3,4,5

Operating Temperature Range (Packaged) T

I

D

A

25 mA

– 40 to 85 °C

(TL - TH)

Storage Temperature Range T

1

Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum

stg

– 65 to 150 °C

Ratings are stress ratings only, and functional operation at the maxima is not guaranteed.
Continued operation at these levels may affect device reliability or cause permanent damage
to the device.

2

This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid application of
any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.,
either V

3

Input must be current limited to the value specified. To determine the value of the required

or OVDD).

SS

current-limiting resistor, calculate resistance values for positive and negative clamp voltages,
then use the larger of the two values.

4

All functional non-supply pins are internally clamped to VSS and OVDD.

5

Power supply must maintain regulation within operating OVDD range during instantaneous
and operating maximum current conditions. If positive injection current (V
than IDD, the injection current may flow out of OV

and could result in external power supply

DD

> OVDD) is greater

in

going out of regulation. Insure external OVDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the processor is not consuming power
(ex; no clock).Power supply must maintain regulation within operating OV

range during

DD

instantaneous and operating maximum current conditions.

7.2 Thermal Characteristics

The below table lists thermal resistance values.

Characteristic Symbol

Junction to ambient, natural convection Four layer board (2s2p) θ

Junction to ambient (@200 ft/min) Four layer board (2s2p) θ

Junction to board θ

Junction to case θ

Junction to top of package Ψ

Maximum operating junction temperature T

1

θ

and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale

JMA

recommends the use of θ

and power dissipation specifications in the system design to prevent device junction

JmA

temperatures from exceeding the rated specification. System designers should be aware that device junction
temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device
junction temperature specification can be verified by physical measurement in the customer’s system using the Ψ
parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.

2

Per JEDEC JESD51-6 with the board horizontal.

Table 8. Thermal Characteristics

JMA

JMA

JB

JC

jt

j

256

MAPBGA

1,2

26

1,2

23

3

15

4

10

1,5

2

196

MAPBGA

1,2

32

1,2

29

3

20

4

10

1,5

2

102 104 105

160

QFP

1,2

40

1,2

36

3

25

4

10

1,5

2

6o

°C / W

°C / W

°C / W

°C / W

°C / W

jt

Unit

C

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor24

Preliminary Electrical Characteristics

3

Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.

4

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).

5

Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written in conformance with Psi-JT.

6

At 100MHz.

The average chip-junction temperature (TJ) in °C can be obtained from:

JTAPDΘJMA

×()+=

(1)

Where:

TA= Ambient Temperature, °C

Θ

= Package Thermal Resistance, Junction-to-Ambient, °C/W

JMA

PD= P

P

INT

P

I/O

For most applications P
and TJ (if P

+ P

INT

I/O

= IDD × VDD, Watts - Chip Internal Power

= Power Dissipation on Input and Output Pins — User Determined

I/O

is neglected) is:

I/O

< P

and can be ignored. An approximate relationship between PD

INT

PDKTJ273° C+()÷=

(2)

Solving equations 1 and 2 for K gives:

2

K = PD × (TA + 273 °C) + Θ

JMA

× P

(3)

D

where K is a constant pertaining to the particular part. K can be determined from equation (3)
by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and
TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.

7.3 DC Electrical Specifications

Characteristic Symbol Min Typical Max Unit

Core Supply Voltage V

Pad Supply Voltage OV

Input High Voltage V

Input Low Voltage V

Input Hysteresis V

Input Leakage Current

V

= VDD or VSS, Input-only pins

in

High Impedance (Off-State) Leakage Current

= VDD or VSS, All input/output and output pins

V

in

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 25

Table 9. DC Electrical Specifications

DD

DD

0.7 × OV

0.06 × OV

HYS

I

in

I

OZ

IH

IL

1

1.4 — 1.6 V

3—3.6V

DD

V

– 0.3 — 0.35 × OV

SS

DD

–1.0 — 1.0 µA

–1.0 — 1.0 µA

—3.65V

V

DD

——mV

Preliminary Electrical Characteristics

Table 9. DC Electrical Specifications1 (continued)

Characteristic Symbol Min Typical Max Unit

Output High Voltage (All input/output and all output pins)

= –5.0 mA

I

OH

Output Low Voltage (All input/output and all output pins)
I

= 5.0mA

OL

Weak Internal Pull Up Device Current, tested at V

Input Capacitance

3

Max.

IL

2

All input-only pins
All input/output (three-state) pins

Load Capacitance

4

Low drive strength
High drive strength

Core Operating Supply Current

5

Master Mode

Pad Operating Supply Current

Master Mode
Low Power Modes

DC Injection Current

V

NEGCLAMP

3, 6, 7, 8

=VSS– 0.3 V, V

POSCLAMP

= VDD + 0.3
Single Pin Limit
Total processor Limit, Includes sum of all stressed pins

1

Refer to Table 10 for additional PLL specifications.

2

Refer to the MCF5235 signals section for pins having weak internal pull-up devices.

3

This parameter is characterized before qualification rather than 100% tested.

4

pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces require

V

V

I

APU

C

I

OI

C

DD

I

OH

OL

DD

IC

OV

- 0.5 — — V

DD

——0.5V

–10 — – 130 µA

in

—
—

L

—

—
—

7
7

25
50

— 135 150 mA

—
—

–1.0

–10

100

TBD

—
—

1.0
10

transmission line analysis to determine proper drive strength and termination. See High Speed Signal Propagation:
Advanced Black Magic by Howard W. Johnson for design guidelines.

5

Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load.

6

All functional non-supply pins are internally clamped to VSS and their respective VDD.

7

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.

8

Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (V

> VDD) is greater than IDD, the injection current may flow out of V

in

and could

DD

result in external power supply going out of regulation. Insure external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the processor is not consuming power. Examples are: if no system
clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, system clock
is not present during the power-up sequence until the PLL has attained lock.

pF

pF
pF

mA

µA

mA
mA

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor26

Preliminary Electrical Characteristics

7.4 Oscillator and PLLMRFM Electrical Characteristics

Table 10. HiP7 PLLMRFM Electrical Specifications

1

Num Characteristic Symbol

1 PLL Reference Frequency Range

Crystal reference
External reference
1:1 mode (NOTE: f

2 Core frequency

CLKOUT Frequency

External reference

sys/2

2

= 2 × f

ref_1:1

)

f

ref_crystal

f

ref_ext

f

ref_1:1

f

sys

f

sys/2

On-Chip PLL Frequency

5

5, 6,8

5

3, 5

4, 5

9

f

LOR

f

SCM

—10ms

t

cst

t

lpll

t

lplk

t

skew

tdc 40 60 %

3 Loss of Reference Frequency

4 Self Clocked Mode Frequency

5 Crystal Start-up Time

5, 6

6 XTAL Load Capacitance

7 PLL Lock Time

5, 7,13

8 Power-up To Lock Time

With Crystal Reference (includes 5 time)
Without Crystal Reference

9 1:1 Mode Clock Skew (between CLKOUT

and EXTAL)

10

10 Duty Cycle of reference

Min.

Val ue

Max.

Val ue

Unit

MHz
8
8

24

0

f

ref

÷ 32

25
25
75

150

75
75

MHz

MHz

MHz

100 1000 kHz

10.25 15.25 MHz

530pF

—750µs

—
—

11

750

ms

µs

–1 1 ns

11 Frequency un-LOCK Range f

12 Frequency LOCK Range f

13 CLKOUT Period Jitter,

Measured at f

sys/2

5, 6, 8,11, 12

Max

Peak-to-peak Jitter (Clock edge to clock

–3.8 4.1 % f

UL

–1.7 2.0 % f

LCK

C

jitter

—
—

5.0
.01

% f

edge)

Long Term Jitter (Averaged over 2 ms

interval)

14 Frequency Modulation Range Limit

(f

Max must not be exceeded)

sys/2

15 ICO Frequency. f

1

All values given are initial design targets and subject to change.

2

All internal registers retain data at 0 Hz.

3

“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL
into self clocked mode.

4

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls
below f

5

This parameter is guaranteed by characterization before qualification rather than 100% tested.

6

Proper PC board layout procedures must be followed to achieve specifications.

with default MFD/RFD settings.

LOR

ico

= f

ref

× 2 × (MFD+2)

13,14

15

C

0.8 2.2 %f

mod

f

48 150 MHz

ico

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

sys/2

sys/2

sys/2

sys/2

Freescale Semiconductor 27

Preliminary Electrical Characteristics

7

This specification applies to the period required for the PLL to relock after changing the MFD frequency
control bits in the synthesizer control register (SYNCR).

8

Assuming a reference is available at power up, lock time is measured from the time VDD and V
valid to RSTOUT
crystal start up time must be added to the PLL lock time to determine the total start-up time.

9

t

= (64 * 4 * 5 + 5 × τ) × T

lpll

τ = 1.57x10

10

PLL is operating in 1:1 PLL mode.

11

Jitter is the average deviation from the programmed frequency measured over the specified interval at
maximum f
stable external clock signal. Noise injected into the PLL circuitry via V
crystal oscillator frequency increase the Cjitter percentage for a given interval.

12

Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of
Cjitter+Cmod.

13

Modulation percentage applies over an interval of 10µs, or equivalently the modulation rate is 100KHz.

14

Modulation rate selected must not result in f
Modulation range determined by hardware design.

15

f

= f

sys/2

ico

negating. If the crystal oscillator is being used as the reference for the PLL, then the

, where T

-6

× 2(MFD + 2).

. Measurements are made with the device powered by filtered supplies and clocked by a

sys/2

RFD

/ (2 * 2

ref

)

ref

= 1/F

sys/2

ref_crystal

= 1/F

value greater than the f

ref_ext

= 1/F

DDSYN

7.5 External Interface Timing Characteristics

Table 11 lists processor bus input timings.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.

, and

ref_1:1

and V

maximum specified value.

sys/2

and variation in

SSSYN

DDSYN

are

All other timing relationships can be derived from these values.

Table 11. Processor Bus Input Timing Specifications

Name Characteristic

1

freq System bus frequency f

B0 CLKOUT period t

Control Inputs

B1a Control input valid to CLKOUT high

B1b BKPT

B2a

B2b

valid to CLKOUT high

CLKOUT high to control inputs invalid

CLKOUT high to asynchronous control input BKPT invalid

2

3

2

3

Data Inputs

B4

Data input (D[31:0]) valid to CLKOUT high t

B5

CLKOUT high to data input (D[31:0]) invalid t

1

Timing specifications are tested using full drive strength pad configurations in a 50ohm transmission line
environment..

2

TEA and TA pins are being referred to as control inputs.

3

Refer to figure A-19.

Symbol Min Max Unit

sys/2

cyc

t

CVCH

t

BKVCH

t

CHCII

t

BKNCH

DIVCH

CHDII

50 75 MHz

—1/75ns

9—ns

9—ns

0—ns

0—ns

4—ns

0—ns

Timings listed in Table 11 are shown in Figure 10 & Figure A-3.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor28

* The timings are also valid for inputs sampled on the negative clock edge.

Preliminary Electrical Characteristics

CLKOUT

Inputs

CLKOUT(75MHz)

Input Setup And Hold

Input Rise Time

Input Fall Time

B4

1.5V

T

SETUP

Invalid Invalid

Vh = V

IH

Vl = V

IL

Vh = V

IH

Vl = V

IL

T

HOLD

1.5V1.5V Valid

trise

tfall

B5

Figure 10. General Input Timing Requirements

7.6 Processor Bus Output Timing Specifications

Table 12 lists processor bus output timings.

Table 12. External Bus Output Timing Specifications

Name Characteristic Symbol Min Max Unit

Control Outputs

B6a CLKOUT high to chip selects valid

B6b CLKOUT high to byte enables (BS

B6c CLKOUT high to output enable (OE

B7 CLKOUT high to control output (BS

B7a CLKOUT high to chip selects invalid t

B8 CLKOUT high to address (A[23:0]) and control (TS

TSIZ[1:0], TIP, R/W) valid

1

[3:0]) valid

) valid

2

3

[3:0], OE) invalid t

t

CHCV

t

CHBV

t

CHOV

CHCOI

CHCI

Address and Attribute Outputs

,

t

CHAV

—0.5t

—0.5t

—0.5t

0.5t

0.5t

+1.5 — ns

CYC

+1.5 — ns

CYC

—9ns

+5 ns

CYC

+5 ns

CYC

+5 ns

CYC

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 29

Preliminary Electrical Characteristics

Table 12. External Bus Output Timing Specifications (continued)

Name Characteristic Symbol Min Max Unit

B9 CLKOUT high to address (A[23:0]) and control (TS,

[1:0], TIP, R/W) invalid

TSIZ

t

CHAI

1.5 — ns

Data Outputs

B11 CLKOUT high to data output (D[31:0]) valid t

B12 CLKOUT high to data output (D[31:0]) invalid t

B13 CLKOUT high to data output (D[31:0]) high impedance t

1

CS transitions after the falling edge of CLKOUT.

2

BS transitions after the falling edge of CLKOUT.

3

OE transitions after the falling edge of CLKOUT.

CHDOV

CHDOI

CHDOZ

—9ns

1.5 — ns

—9ns

Read/write bus timings listed in Table 12 are shown in Figure 11, Figure 12, and Figure 13.

CLKOUT

CSn

A[23:0]

TSIZ[1:0]

TS

TIP

S0

B6a

B8

B8

B9

B8

S2 S3S1 S4 S5 S0 S1 S2 S3 S4 S5

B7a

B7a

B6a

B8

B9

B8

B9

B9

R/W

BS[3:0]

D[31:0]

TA

TEA

OE

(H)

(H)

(H)

B6c

B0

B7

B8

B6b

B6b

B7

B7

B4

B11

B5

Figure 11. Read/Write (Internally Terminated) SRAM Bus Timing

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

B9

B12

B13

Freescale Semiconductor30

Preliminary Electrical Characteristics

Figure 12 shows a bus cycle terminated by TA showing timings listed in Ta b l e 1 2 .

S0 S2 S3S1 S4 S5 S0 S1

CLKOUT

CS

A[23:0]

TSIZ[1:0]

TS

TIP

OE

R/W

BS[3:0]

D[31:0]

n

(H)

B6a

B8

B8

B8

B6c

B6b

B7a

B9

B9

B9

B7

B7

B5

B4

B2a

TA

B1a

TEA

(H)

Figure 12. SRAM Read Bus Cycle Terminated by TA

Figure 13 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 12.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 31

Preliminary Electrical Characteristics

CLKOUT

CS

A[23:0]

TSIZ[1:0]

TS

TIP

OE

R/W

BS[3:0]

n

(H)

B6a

B8

B8

B8

B6c

B6b

S0

B9

S1

S2

B7a

B7

B7

S3

S4

S5 S0 S1

B9

B9

D[31:0]

TA

(H)

TEA

Figure 13. SRAM Read Bus Cycle Terminated by TEA

Figure 14 shows an SDRAM read cycle.

B1a

B2a

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor32

SD_CKE

Preliminary Electrical Characteristics

0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A[23:0]

D2

SD_SRAS

SD_CAS

SDWE

D[31:0]

RAS[1:0]

CAS[3:0]

1

DACR[CASL] = 2

D1

D3

Row

D4

D2

1

D4

D2

D2

ACTV NOP PALLNOP

READ

NOP

Column

D4

D2

D6

D5

D4

Figure 14. SDRAM Read Cycle

Table 13. SDRAM Timing

NUM Characteristic Symbol Min Max Unit

D1 CLKOUT high to SDRAM address valid t

D2 CLKOUT high to SDRAM control valid t

D3 CLKOUT high to SDRAM address invalid t

D4 CLKOUT high to SDRAM control invalid t

D5 SDRAM data valid to CLKOUT high t

D6 CLKOUT high to SDRAM data invalid t

1

D7

CLKOUT high to SDRAM data valid t

2

CLKOUT high to SDRAM data invalid t

D8

1

D7 and D8 are for write cycles only.

CHDAV

CHDCV

CHDAI

CHDCI

DDVCH

CHDDI

CHDDVW

CHDDIW

—9ns

—9ns

1.5 — ns

1.5 — ns

4—ns

1.5 — ns

—9ns

1.5 — ns

Figure 15 shows an SDRAM write cycle.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 33

Preliminary Electrical Characteristics

0 1 2 3 4 5 6 7 8 9 10 11 12

SD_CKE

A[23:0]

SD_SRAS

SD_SCAS

SD_WE

D[31:0]

RAS[1:0]

CAS[3:0]

D1

D2

1

D2

D2

ACTV PALLNOP

1

DACR[CASL] = 2

D7

Row

D2

D2

D3

D4

WRITE

Column

D4

D8

D4

NOP

Figure 15. SDRAM Write Cycle

7.7 General Purpose I/O Timing

Table 14. GPIO Timing1

NUM Characteristic Symbol Min Max Unit

G1G2CLKOUT High to GPIO Output Valid t

CLKOUT High to GPIO Output Invalid t

G3G4GPIO Input Valid to CLKOUT High t

CLKOUT High to GPIO Input Invalid t

1

GPIO pins include: INT, ETPU, UART, FlexCAN and Timer pins.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

CHPOV

CHPOI

PVCH

CHPI

—10ns

1.5 — ns

9—ns

1.5 — ns

Freescale Semiconductor34

CLKOUT

Preliminary Electrical Characteristics

G1

GPIO Outputs

G4G3

GPIO Inputs

G2

Figure 16. GPIO Timing

7.8 Reset and Configuration Override Timing

Table 15. Reset and Configuration Override Timing

(V

= 2.7 to 3.6 V, V

DD

NUM Characteristic Symbol Min Max Unit

R1 RESET Input valid to CLKOUT High t

R2 CLKOUT High to RESET

R3 RESET

Input valid Time

Input invalid t

2

R4 CLKOUT High to RSTOUT Valid t

R5 RSTOUT

valid to Config. Overrides valid t

R6 Configuration Override Setup Time to RSTOUT

R7 Configuration Override Hold Time after RSTOUT invalid t

R8 RSTOUT

1

All AC timing is shown with respect to 50% VDD levels unless otherwise noted.

2

During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously

invalid to Configuration Override High Impedance t

to the system. Thus, RESET must be held a minimum of 100 ns.

SS

= 0 V, T

= T

L

A

invalid t

to TH)

RVCH

CHRI

t

RIVT

CHROV

ROVCV

COS

COH

ROICZ

1

9—ns

1.5 — ns

5—t

—10ns

0—ns

20 — t

0—ns

—1t

CYC

CYC

CYC

CLKOUT

RESET

RSTOUT

Configuration Overrides*:

(RCON, Override pins])

R1

R3

R2

R4

R4

R8

R7R6R5

Figure 17. RESET and Configuration Override Timing

Refer to the chip configuration module (CCM) chapter in the device’s reference manual for more
information.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 35

Preliminary Electrical Characteristics

7.9 I2C Input/Output Timing Specifications

Table 16 lists specifications for the I2C input timing parameters shown in Figure 18.

Table 16. I2C Input Timing Specifications between I2C_SCL and I2C_SDA

Num Characteristic Min Max Units

I1 Start condition hold time 2 — t

I2 Clock low period 8 — t

I3 I2C_SCL/I2C_SDA rise time (VIL= 0.5 V to VIH= 2.4 V) — 1 ms

I4 Data hold time 0 — ns

I5 I2C_SCL/I2C_SDA fall time (VIH= 2.4 V to VIL= 0.5 V) — 1 ms

I6 Clock high time 4 — t

I7 Data setup time 0 — ns

I8 Start condition setup time (for repeated start condition only) 2 — t

I9 Stop condition setup time 2 — t

Table 17 lists specifications for the I2C output timing parameters shown in Figure 18.

1

2

3

Tabl e 17. I2C Output Timing Specifications between I2C_SCL and I2C_SDA

Num Characteristic Min Max Units

1

I1

I2 1Clock low period 10 — t

I3

I4

I5

I6

I7 1Data setup time 2 — t

I8 1Start condition setup time (for repeated start condition only) 20 — t

I9 1Stop condition setup time 10 — t

Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with
the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Ta b l e 1 7 . The
I
I2C_SCL low period. The actual position is affected by the prescale and division values programmed
into the IFDR; however, the numbers given in Ta bl e 1 7 are minimum values.

Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only
actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external
signal capacitance and pull-up resistor values.

Specified at a nominal 50-pF load.

Start condition hold time 6 — t

2

I2C_SCL/I2C_SDA rise time (V

1

Data hold time 7 — t

3

I2C_SCL/I2C_SDA fall time (V

1

Clock high time 10 — t

2

C interface is designed to scale the actual data transition time to move it to the middle of the

= 0.5 V to VIH= 2.4 V) — — µs

IL

= 2.4 V to VIL= 0.5 V) — 3 ns

IH

cyc

cyc

cyc

cyc

cyc

cyc

cyc

cyc

cyc

cyc

cyc

cyc

Figure 18 shows timing for the values in Table 16 and Table 17.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor36

Preliminary Electrical Characteristics

I2C_SCL

I2C_SDA

I2 I6

I1 I4

I7

I8 I9

I5

I3

Figure 18. I2C Input/Output Timings

7.10 Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

7.10.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK)

The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. The processor
clock frequency must exceed twice the ERXCLK frequency.

Table 18 lists MII receive channel timings.

Table 18. MII Receive Signal Timing

Num Characteristic Min Max Unit

M1 ERXD[3:0], ERXDV, ERXER to ERXCLK setup 5 — ns

M2 ERXCLK to ERXD[3:0], ERXDV, ERXER hold 5 — ns

M3 ERXCLK pulse width high 35% 65% ERXCLK period

M4 ERXCLK pulse width low 35% 65% ERXCLK period

Figure 19 shows MII receive signal timings listed in Table 18.

M3

ERXCLK (input)

ERXD[3:0] (inputs)

ERXDV

ERXER

M1 M2

Figure 19. MII Receive Signal Timing Diagram

M4

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 37

Preliminary Electrical Characteristics

7.10.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK)

Table 19 lists MII transmit channel timings.

The transmitter functions correctly up to a ETXCLK maximum frequency of 25 MHz +1%. The processor
clock frequency must exceed twice the ETXCLK frequency.

Table 19. MII Transmit Signal Timing

Num Characteristic Min Max Unit

M5 ETXCLK to ETXD[3:0], ETXEN, ETXER invalid 5 — ns

M6 ETXCLK to ETXD[3:0], ETXEN, ETXER valid — 25 ns

M7 ETXCLK pulse width high 35% 65% ETXCLK period

M8 ETXCLK pulse width low 35% 65% ETXCLK period

Figure 20 shows MII transmit signal timings listed in Table 19.

M7

ETXCLK (input)

M5

ETXD[3:0] (outputs)

ETXEN
ETXER

M6

M8

Figure 20. MII Transmit Signal Timing Diagram

7.10.3 MII Async Inputs Signal Timing (ECRS and ECOL)

Table 20 lists MII asynchronous inputs signal timing.

Table 20. MII Async Inputs Signal Timing

Num Characteristic Min Max Unit

M9 ECRS, ECOL minimum pulse width 1.5 — ETXCLK period

Figure 21 shows MII asynchronous input timings listed in Table 20.

ECRS, ECOL

M9

Figure 21. MII Async Inputs Timing Diagram

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor38

Preliminary Electrical Characteristics

7.10.4 MII Serial Management Channel Timing (EMDIO and EMDC)

Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum

MDC frequency of 2.5 MHz.

Table 21. MII Serial Management Channel Timing

Num Characteristic Min Max Unit

M10 EMDC falling edge to EMDIO output invalid (minimum propagation delay) 0 — ns

M11 EMDC falling edge to EMDIO output valid (max prop delay) — 25 ns

M12 EMDIO (input) to EMDC rising edge setup 10 — ns

M13 EMDIO (input) to EMDC rising edge hold 0 — ns

M14 EMDC pulse width high 40% 60% MDC period

M15 EMDC pulse width low 40% 60% MDC period

Figure 22 shows MII serial management channel timings listed in Table 21.

M14

EMDC (output)

EMDIO (output)

EMDIO (input)

M12

M13

M15

M10

M11

Figure 22. MII Serial Management Channel Timing Diagram

7.11 32-Bit Timer Module AC Timing Specifications

Table 22 lists timer module AC timings.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 39

Preliminary Electrical Characteristics

Table 22. Timer Module AC Timing Specifications

Name Characteristic

0–66 MHz

Unit

Min Max

T1 DT0IN / DT1IN / DT2IN / DT3IN cycle time 3 — t

T2 DT0IN / DT1IN / DT2IN / DT3IN pulse width 1 — t

7.12 QSPI Electrical Specifications

Table 23 lists QSPI timings.

Table 23. QSPI Modules AC Timing Specifications

Name Characteristic Min Max Unit

QS1 QSPI_CS[1:0] to QSPI_CLK 1 510 tcyc

QS2 QSPI_CLK high to QSPI_DOUT valid. — 10 ns

QS3 QSPI_CLK high to QSPI_DOUT invalid. (Output hold) 2 — ns

QS4 QSPI_DIN to QSPI_CLK (Input setup) 9 — ns

QS5 QSPI_DIN to QSPI_CLK (Input hold) 9 — ns

The values in Table 23 correspond to Figure 23.

QS1

QSPI_CS[1:0]

CYC

CYC

QSPI_CLK

QSPI_DOUT

QSPI_DIN

QS2

QS3

QS4

Figure 23. QSPI Timing

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

QS5

Freescale Semiconductor40

7.13 JTAG and Boundary Scan Timing

Table 24. JTAG and Boundary Scan Timing

Preliminary Electrical Characteristics

Num Characteristics

1

J1 TCLK Frequency of Operation f

J2 TCLK Cycle Period t

J3 TCLK Clock Pulse Width t

J4 TCLK Rise and Fall Times t

J5 Boundary Scan Input Data Setup Time to TCLK Rise t

J6 Boundary Scan Input Data Hold Time after TCLK Rise t

J7 TCLK Low to Boundary Scan Output Data Valid t

J8 TCLK Low to Boundary Scan Output High Z t

J9 TMS, TDI Input Data Setup Time to TCLK Rise t

J10 TMS, TDI Input Data Hold Time after TCLK Rise t

J11 TCLK Low to TDO Data Valid t

J12 TCLK Low to TDO High Z t

J13 TRST

J14 TRST

1

JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.

Assert Time t

Setup Time (Negation) to TCLK High t

Symbol Min Max Unit

JCYC

JCYC

JCW

JCRF

BSDST

BSDHT

BSDV

BSDZ

TAPBST

TAPBHT

TDODV

TDODZ

TRSTAT

TRSTST

DC 1/4 f

4—t

sys/2

CYC

26 — ns

03ns

4—ns

26 — ns

033ns

033ns

4—ns

10 — ns

026ns

08ns

100 — ns

10 — ns

TCLK
(input)

J2

J3 J3

V

IH

V

J4 J4

IL

Figure 24. Test Clock Input Timing

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 41

Preliminary Electrical Characteristics

TCLK

Data Inputs

Data Outputs

Data Outputs

Data Outputs

TCLK

TDI

TMS

V

IL

J5 J6

Input Data Valid

J7

J8

J7

V

IH

Output Data Valid

Output Data Valid

Figure 25. Boundary Scan (JTAG) Timing

V

IL

J9 J10

Input Data Valid

J11

V

IH

TDO

J12

Output Data Valid

TDO

J11

TDO

Output Data Valid

Figure 26. Test Access Port Timing

TCLK

J14

TRST

J13

Figure 27. TRST

Timing

7.14 Debug AC Timing Specifications

Table 25 lists specifications for the debug AC timing parameters shown in Figure 29.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor42

Table 25. Debug AC Timing Specification

Num Characteristic

Preliminary Electrical Characteristics

150 MHz

Units

Min Max

DE0 PSTCLK cycle time — 0.5 t

DE1 PST valid to PSTCLK high 4 — ns

DE2 PSTCLK high to PST invalid 1.5 — ns

DE3 DSCLK cycle time 5 — t

DE4 DSI valid to DSCLK high 1 — t

1

DE5

DSCLK high to DSO invalid 4 — t

DE6 BKPT input data setup time to CLKOUT rise 4 — ns

DE7 CLKOUT high to BKPT

1

DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK

high Z 0 10 ns

input relative to the rising edge of CLKOUT.

Figure 28 shows real-time trace timing for the values in Table 25.

PSTCLK

DE0

cyc

cyc

cyc

cyc

DE2DE1

PST[3:0]

DDATA[3:0]

Figure 28. Real-Time Trace AC Timing

Figure 29 shows BDM serial port AC timing for the values in Table 25.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 43

Documentation

CLKOUT

BKPT

DSCLK

DE6

DE7

DE5

DE3

DSI

DSO

Current Next

DE4

Past Current

Figure 29. BDM Serial Port AC Timing

8 Documentation

Documentation regarding the MCF523x and their development support tools is available from a local
Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center,
or through the Freescale web address at http://www.freescale.com/coldfire.

9 Document Revision History

The below table provides a revision history for this document.

Table 26. Document Revision History

Rev. No. Substantive Change(s)

0 Preliminary release.

1 • Updated Signal List table

1.1 • Removed duplicate information in the module description sections. The information is all in the
Signals Description Table.

1.2 • Corrected Figure 8 pin 81. VDD instead of VSS

• Changed instances of Motorola to Freescale

1.3 • Removed detailed signal description section. This information can be found in the
MCF5235RM Chapter 2.

• Removed detailed feature list. This information can be found in the MCF5235RM Chapter 1.

• Corrected Figure 2 pin F10. VSS instead of VDD. Change made in Ta b le 2 as well.

• Corrected Figure 8 pin 81. OVDD instead of VDD. Change made in Ta bl e 2 as well.

• Cleaned up many inconsistencies within the pinout figure signal names

• Corrected document IDs in Documentation Table

1.4 • Added values for ‘Maximum operating junction temperature’ in Ta b le 8 .

• Added typical values for ‘Core operating supply current (master mode)’ in Ta b le 9 .

• Added typical values for ‘Pad operating supply current (master mode)’ in Ta bl e 9 .

• Removed unnecessary PLL specifications, #6-9, in Ta bl e 1 0 .

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor44

Document Revision History

Table 26. Document Revision History (continued)

Rev. No. Substantive Change(s)

1.5 • Removed Overview, Features, Modes of Operation, and Address Multiplexing sections. This
information can be found in the MCF5235 Reference Manual.

• Removed list of documentation table in Section 8, “Documentation.”. An up-to-date list is
always available on our web site.

1.6 • Ta bl e 9 : Changed core supply voltage (V

1.7 • Ta bl e 1 0: Changed max f

frequency from “75 MHz” to “150 MHz”.

ICO

) from 1.35-1.65 to 1.4-1.6.

DD

1.8 • Added Section 5.2.1, “Supply Voltage Sequencing and Separation Cautions.”

• Updated 196MAPBGA package dimensions, Figure 3.

2 •Ta b le 2 : Changed SD_CKE pin location from 139 to “—” for the 160QFP device. Changed

QSPI_CS1 pin location from “—” to 139 for the 160QFP device.

• Figure 8: Changed pin 139 label from “SD_CKE/QSPI_CS1” to “QSPI_CS1/SD_CKE”.

• Removed second sentence from Section 7.10.1, “MII Receive Signal Timing (ERXD[3:0],

ERXDV, ERXER, and ERXCLK),” and Section 7.10.2, “MII Transmit Signal Timing (ETXD[3:0],
ETXEN, ETXER, ETXCLK),” regarding no minimum frequency requirement for TXCLK.

• Removed third and fourth paragraphs from Section 7.10.2, “MII Transmit Signal Timing

(ETXD[3:0], ETXEN, ETXER, ETXCLK),” as this feature is not supported on this device.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 45

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Document Number: MCF5235EC

Rev. 2
08/2006