Freescale MCF5235EC DATA SHEET

Freescale Semiconductor

Document Number: MCF5235EC

Hardware Specification

MCF523x Integrated
Microprocessor
Hardware Specification

by: Microcontroller Division

Rev. 2, 08/2006

The MCF523x is a family of highly-integrated 32-bit
microcontrollers based on the V2 ColdFire
microarchitecture. Featuring a 16 or 32 channel eTPU,
64 Kbytes of internal SRAM, a 2-bank SDRAM
controller, four 32-bit timers with dedicated DMA, a 4
channel DMA controller, up to 2 CAN modules, 3
UARTs and a queued SPI, the MCF523x family has been
designed for general purpose industrial control
applications. It is also a high-performance upgrade for
users of the MC68332. This document provides an
overview of the MCF523x microcontroller family, as
well as detailed descriptions of the mechanical and
electrical characteristics of the devices.

The MCF523x family is based on the Version 2 ColdFire
reduced instruction set computing (RISC)
microarchitecture operating at a core frequency of up to
150 MHz and bus frequency up to 75 MHz.

Contents

1 MCF523x Family Configurations . . . . . . . . . . . . . . . . . . . 2

2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . 9

6 Mechanicals/Pinouts and Part Numbers . . . . . . . . . . . . 14

7 Preliminary Electrical Characteristics . . . . . . . . . . . . . . 23

8 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9 Document Revision History . . . . . . . . . . . . . . . . . . . . . . 44

© Freescale Semiconductor, Inc., 2006. All rights reserved.

MCF523x Family Configurations

1 MCF523x Family Configurations

Table 1. MCF523x Family Configurations

Module MCF5232 MCF5233 MCF5234 MCF5235

ColdFire V2 Core with EMAC
(Enhanced Multiply-Accumulate
Unit)

Enhanced Time Processor Unit
with memory (eTPU)

System Clock up to 150 MHz

Performance (Dhrystone/2.1 MIPS) up to 144

Instruction/Data Cache 8 Kbytes

Static RAM (SRAM) 64 Kbytes

Interrupt Controllers (INTC) 2 2 2 2

Edge Port Module (EPORT) x x x x

External Interface Module (EIM) x x x x

4-channel Direct-Memory Access
(DMA)

SDRAM Controller x x x x

Fast Ethernet Controller (FEC) — — x x

Cryptography - Security module for
data packets processing

Watchdog Timer (WDT) x x x x

xxxx

16-ch

6K

xxxx

——— x

32-ch

6K

16-ch

6K

32-ch

6K

Four Periodic Interrupt Timers (PIT) x x x x

32-bit DMA Timers 4 4 4 4

QSPI xxxx

UART(s) 3333

2

Cxxxx

I

FlexCAN 2.0B - Controller-Area
Network communication module

General Purpose I/O Module
(GPIO)

JTAG - IEEE 1149.1 Test Access
Por t

Package 160 QFP

1212

xxxx

xxxx

196

MAPBGA

256

MAPBGA

256

MAPBGA

256

MAPBGA

2 Block Diagram

The superset device in the MCF523x family comes in a 256 mold array process ball grid array (MAPBGA)
package. Figure shows a top-level block diagram of the MCF5235, the superset device.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor2

(To/From PADI)

(To/From PADI)

(To/From

PAD I)

MUX

JTAG

TAP

(To/From PADI)

DREQ[2:0]

JTAG_EN

FAST

ETHERNET

CONTROLLER

(FEC)

4 CH DMA

DACK[2:0]

NEXUS

eTPU

(To/From SRAM backdoor)

Arbiter

UART

UART

0

1

DTIM

DTIM

0

V2 ColdFire CPU

BDM

64 Kbytes

SRAM

(8Kx16)x4

UART

1

DIV

INTC0

2

DTIM

2

INTC1

2

C

I

DTIM

EMAC

8 Kbytes

CACHE

(1Kx32)x2

QSPI

3

EIM

CHIP

SELECTS

EBI

SDRAMC

PORTS

(GPIO)

Features

SDRAMC

QSPI

I2C_SDA

I2C_SCL

UnTXD

UnRXD

DTnOUT

DTnIN

FEC

CANTX

PADI – Pin Muxing

CIM

UnRTS

nCTS

U

CANRX

eTPU

D[31:0]

A[23:0]

R/

W

CS[3:0]

TA

TSIZ[1:0]

TEA

BS[3:0]

Watchdog

Timer

SKHA

FlexCAN

(x2)

RNGA

MDHA

(To/From Arbiter backdoor)

PLL

CLKGEN

(To/From INTC)

Edge

Port

PIT0

PIT1 PIT2 PIT3

Cryptography

MCF5235 Block Diagram

Modules

3Features

For a detailed feature list see the MCF5235 Reference Manual (MCF5235RM).

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 3

Signal Descriptions

4 Signal Descriptions

This section describes signals that connect off chip, including a table of signal properties. For a more
detailed discussion of the MCF523x signals, consult the MCF5235 Reference Manual (MCF5235RM).

4.1 Signal Properties

Table 2 lists all of the signals grouped by function. The “Dir” column is the direction for the primary

function of the pin. Refer to Section 6, “Mechanicals/Pinouts and Part Numbers,” for package diagrams.

NOTE

In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., A24), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.

NOTE

The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO will default to their GPIO functionality.

Table 2. MCF523x Signal Information and Muxing

MCF5232

Signal Name GPIO Alternate 1 Alternate 2 Dir.

RESET — — — I 83 N13 T15 T15 T15

RSTOUT — — — O 82 P13 T14 T14 T14

EXTAL — — — I 86 M14 P16 P16 P16

XTAL — — — O 85 N14 R16 R16 R16

CLKOUT — — — O 89 K14 M16 M16 M16

CLKMOD[1:0] — — — I 19,20 G5, H5 J3, J2 J3, J2 J3, J2

RCON — — — I 79 K10 P13 P13 P13

External Memory Interface and Ports

A[23:21] PADDR[7:5] CS

[6:4] — O 126, 125,

1

160

QFP

Reset

Clock

Mode Selection

124

MCF5232

196

MAPBGA

B11, C11,

D11

MCF5233

256

MAPBGA

B14, C14,

A15

MCF5234

256

MAPBGA

B14, C14,

A15

MCF5235

256

MAPBGA

B14, C14,

A15

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor4

Table 2. MCF523x Signal Information and Muxing (continued)

Signal Descriptions

MCF5232

Signal Name GPIO Alternate 1 Alternate 2 Dir.

1

A[20:0] — — — O 123:115,

112:106,

160

QFP

102:98

MCF5232

MAPBGA

A12, B12,
C12, A13,
B13, B14,
C13, C14,
D12, D13,
D14, E11,
E12, E13,
E14, F12,
F13, F14,

G11, G12,

G13

D[31:16] — — — O 21:24, 26:30,

33:39

G1, G2, H1,

H2, H3, H4,

J1, J2, J3,

J4, K1, K2,

K3, K4, L1,

D[15:8] PDATAH[7:0] — — O 42:49, M1, N1, M2,

N2, P2, L3,

M3, N3,

D[7:0] PDATAL[7:0] — — O 50:52, 56:60 P3, M4, N4,

P4, L5, M5,

N5, P5

196

L2

MCF5233

256

MAPBGA

B15, B16,
C15, C16,
D16, D15,
D14, E16,

E15, E14,

E13, F15,

F14, F13,
G15, G14,
G13, H16,
H15, H14,

H13

K4, K3, K2,

K1, L4, L3,

L2, L1, M3,

M2, M1,

N2, N1, P2,

P1, R1

R2, T2, N3,
P3, R3, T3,

N4, P4,

R4, T4, P5,
R5, N6, P6,

R6, N7

MCF5234

256

MAPBGA

B15, B16,
C15, C16,
D16, D15,
D14, E16,
E15, E14,
E13, F15,

F14, F13,
G15, G14,
G13, H16,
H15, H14,

H13

K4, K3, K2,

K1, L4, L3,

L2, L1, M3,

M2, M1,

N2, N1, P2,

P1, R1

R2, T2, N3,
P3, R3, T3,

N4, P4,

R4, T4, P5,
R5, N6, P6,

R6, N7

MCF5235

256

MAPBGA

B15, B16,
C15, C16,
D16, D15,
D14, E16,
E15, E14,
E13, F15,

F14, F13,
G15, G14,
G13, H16,
H15, H14,

H13

K4, K3, K2,

K1, L4, L3,

L2, L1, M3,

M2, M1,

N2, N1, P2,

P1, R1

R2, T2, N3,
P3, R3, T3,

N4, P4,

R4, T4, P5,
R5, N6, P6,

R6, N7

BS

[3:0] PBS[7:4] CAS[3:0] — O 143:140 B6, C6, D7, C7C9, B9, A9,

A10

OE

PBUSCTL7 — — O 63 N6 T7 T7 T7

C9, B9, A9,

A10

C9, B9, A9,

A10

TA PBUSCTL6 — — I 97 H11 K14 K14 K14

TEA

R/W

PBUSCTL5 DREQ1 —I — J14 K13 K13 K13

PBUSCTL4 — — O 96 J13 L16 L16 L16

TSIZ1 PBUSCTL3 DACK1 — O —P6N8N8N8

TSIZ0 PBUSCTL2 DACK0 — O —P7P8P8P8

TS PBUSCTL1 DACK2 — O — H13 K16 K16 K16

TIP PBUSCTL0 DREQ0 — O — H12 K15 K15 K15

Chip Selects

CS

[7:4] PCS[7:4] — — O —B9, A10,

C10, A11

CS

[3:2] PCS[3:2] SD_CS[1:0] — O 134,133 A9, C9 B12, D12 B12, D12 B12, D12

CS1

CS0

PCS1 — — O 130 B10 B13 B13 B13

— — — O 129 D10 D13 D13 D13

C12, A13,

C13, A14

C12, A13,

C13, A14

C12, A13,

C13, A14

SDRAM Controller

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 5

Signal Descriptions

Table 2. MCF523x Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2 Dir.

SD_WE

SD_SCAS

SD_SRAS

PSDRAM5 — — O 93 K13 L13 L13 L13

PSDRAM4 — — O 92 K12 M15 M15 M15

PSDRAM3 — — O 91 K11 M14 M14 M14

1

MCF5232

160

QFP

MCF5232

196

MAPBGA

MCF5233

256

MAPBGA

MCF5234

256

MAPBGA

MCF5235

256

MAPBGA

SD_CKE PSDRAM2 — — O — E8 C10 C10 C10

SD_CS

[1:0] PSDRAM[1:0] — — O — L12, L13 N15, M13 N15, M13 N15, M13

External Interrupts Port

IRQ[7:3] PIRQ[7:3] — — I IRQ7=64

IRQ4=65

N7, M7, L7,

P8, N8

R8, T8, N9,

P9, R9

R8, T8, N9,

P9, R9

R8, T8, N9,

P9, R9

IRQ2 PIRQ2 DREQ2 — I —M8T9T9T9

IRQ1 PIRQ1 — — I 66 L8 N10 N10 N10

eTPU

TPUCH31 — ECOL — — —F3—F3

TPUCH30 — ECRS — — —F4—F4

TPUCH29 — ERXCLK — — —E3—E3

TPUCH28 — ERXDV — — —E4—E4

TPUCH[27:24] — ERXD[3:0] — — — D3, D4, C3,

C4

— D3, D4, C3,

C4

TPUCH23 — ERXER — — —D5—D5

TPUCH22 — ETXCLK — — —C5—C5

TPUCH21 — ETXEN — — —D6—D6

TPUCH20 — ETXER — — —C6—C6

TPUCH[19:16] — ETXD[3:0] — — — B6,B5, A5,

B7

TPUCH[15:0] — — — 11, 10, 7:2,

159:154,
152, 151

E2, E1, D1
D2, D3, C1,
C2, B1, B2,
A2, C3, B3,
A3, A4, C4,

BR

F2, E1, E2,
D1, D2, C1,
C2, B1, B2,
A2, B3, A3,
B4, A4, A6,

A7

— B6,B5, A5,

F2, E1, E2,
D1, D2, C1,
C2, B1, B2,
A2, B3, A3,
B4, A4, A6,

F2, E1, E2,
D1, D2, C1,
C2, B1, B2,
A2, B3, A3,
B4, A4, A6,

A7

B7

A7

TCRCLK PETPU2 — — 12 E3 F1 F1 F1

UTPUODIS PETPU1 — — — H10 J13 J13 J13

LTPUODIS PETPU0 — — — G10 J14 J14 J14

FEC

EMDIO PFECI2C2 I2C_SDA U2RXD I/O — — —C7C7

EMDC PFECI2C3 I2C_SCL U2TXD O — — —D7D7

ECOL — — — I — — —F3F3

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor6

Table 2. MCF523x Signal Information and Muxing (continued)

Signal Descriptions

Signal Name GPIO Alternate 1 Alternate 2 Dir.

1

MCF5232

160

QFP

MCF5232

196

MAPBGA

MCF5233

256

MAPBGA

MCF5234

256

MAPBGA

MCF5235

256

MAPBGA

ECRS — — — I — — —F4F4

ERXCLK — — — I — — —E3E3

ERXDV — — — I — — —E4E4

ERXD[3:0] — — — I — — —D3, D4, C3, C4D3, D4, C3,

C4

ERXER — — — I — — —D5D5

ETXCLK — — — I — — —C5C5

ETXEN — — — O — — —D6D6

ETXER — — — O — — —C6C6

ETXD[3:0] — — — O — — — B6, B5, A5, B7B6, B5, A5,

B7

Feature Control

eTPU/EthENB — — — I ————M4

I2C

I2C_SDA PFECI2C1 CAN0RX — I/O — J12 L15 L15 L15

I2C_SCL PFECI2C0 CAN0TX — I/O — J11 L14 L14 L14

DMA

DACK[2:0] and DREQ[2:0] do not have a dedicated bond pads.

— — — — —

Please refer to the following pins for muxing:

TS and DT2OUT for DACK2, TSIZ1and DT1OUT for DACK1,

TSIZ0 and DT0OUT for DACK0, IRQ2

and DT2IN for DREQ2,

TEA and DT1IN for DREQ1, and TIP and DT0IN for DREQ0.

QSPI

QSPI_CS1 PQSPI4 SD_CKE — O 139 B7 B10 B10 B10

QSPI_CS0 PQSPI3 — — O 147 A6 D9 D9 D9

QSPI_CLK PQSPI2 I2C_SCL — O 148 C5 B8 B8 B8

QSPI_DIN PQSPI1 I2C_SDA — I 149 B5 C8 C8 C8

QSPI_DOUT PQSPI0 — — O 150 A5 D8 D8 D8

UARTs

U2TXD PUARTH1 CAN1TX — O —A8D11D11D11

U2RXD PUARTH0 CAN1RX — I —A7D10D10D10

U1CTS PUARTL7 U2CTS — I —B8C11C11C11

U1RTS PUARTL6 U2RTS — O —C8B11B11B11

U1TXD PUARTL5 CAN0TX — O 135 D9 A12 A12 A12

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 7

Signal Descriptions

Table 2. MCF523x Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2 Dir.

1

MCF5232

160

QFP

MCF5232

196

MAPBGA

MCF5233

256

MAPBGA

MCF5234

256

MAPBGA

MCF5235

256

MAPBGA

U1RXD PUARTL4 CAN0RX — I 136 D8 A11 A11 A11

U0CTS PUARTL3 — — I — F3 G1G1G1

U0RTS PUARTL2 — — O —G3H3H3H3

U0TXD PUARTL1 — — O 14 F1 H2 H2 H2

U0RXD PUARTL0 — — I 13 F2 G2 G2 G2

DMA Timers

DT3IN PTIMER7 U2CTS QSPI_CS2 I — H14 J15 J15 J15

DT3OUT PTIMER6 U2RTS QSPI_CS3 O — G14 J16 J16 J16

DT2IN PTIMER5 DREQ2 DT2OUT I —M9P10P10P10

DT2OUT PTIMER4 DACK2 — O —L9R10R10R10

DT1IN PTIMER3 DREQ1 DT1OUT I —L6P7P7P7

DT1OUT PTIMER2 DACK1 — O —M6R7R7R7

DT0IN PTIMER1 DREQ0 — I — E4 G4G4G4

DT0OUT PTIMER0 DACK0 — O — F4 G3G3G3

BDM/JTAG

2

DSCLK — TRST — I 70 N9 N11 N11 N11

PSTCLK — TCLK — O 68 P9 T10 T10 T10

BKPT — TMS — I 71 P10 P11 P11 P11

DSI — TDI — I 73 M10 T11 T11 T11

DSO — TDO — O 72 N10 R11 R11 R11

JTAG_EN — — — I 78 K9 N13 N13 N13

DDATA[3:0] — — — O —M12, N12,

P12, L11

PST[3:0] — — — O 77:74 M11, N11,

P11, L10

N14, P14,

T13, R13

T12, R12,

P12, N12

N14, P14,

T13, R13

T12, R12,

P12, N12

N14, P14,

T13, R13

T12, R12,

P12, N12

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor8

Table 2. MCF523x Signal Information and Muxing (continued)

Design Recommendations

MCF5232

Signal Name GPIO Alternate 1 Alternate 2 Dir.

TEST — — — I 18 F5 J4 J4 J4

PLL_TEST — — — I —R14R14R14

VDDPLL — — — I 87 M13 P15

VSSPLL — — — I 84 L14 R15

OVDD — — — I 1, 9, 17, 32,

VSS — — — I 8, 16, 25, 31,

1

160

QFP

Test

Power Supplies

41, 55, 62,
69, 81, 90,

95, 105, 114,

128, 132,

138, 146

40, 54, 61,
67, 80, 88,

94, 104, 113,

127, 131,
137, 145,

153, 160

MCF5232

196

MAPBGA

E5, E7,
E10, F7, F9,
G6, G8, H7,

H8, H9, J6,

J8, J10, K5,

K6, K8

A1, A14,

E6, E9, F6,

F8, F10,

G7, G9, H6,

J5, J7, J9,

K7, P1, P14

MCF5233

256

MAPBGA

E6:11, F5, F7:10, F12, G5, G6, G11,

G12, H5, H6, H11, H12, J5, J6, J11,

J12, K5, K6, K11, K12, L5, L7:10,

A1, A16, E5, E12, F6, F11, F16,

G7:10, H7: 10, J1, J7:10, K7:10, L6,

L11, M5, M12, N16, T1, T6, T16

MCF5234

256

MAPBGA

L12, M6:M11

MCF5235

256

MAPBGA

VDD — — — I 15, 53, 103,

144

1

Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception
of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM.

2

If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning
these pins.

D6, F11,

G4, L4

A8, G16, H1, T5

5 Design Recommendations

5.1 Layout

• Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power
and ground planes for the MCF523x.

• See application note AN1259, System Design and Layout Techniques for Noise Reduction in
Processor-Based Systems.

• Match the PC layout trace width and routing to match trace length to operating frequency and board
impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the
PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk
analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace
and separation. Clocks get extra separation and more precise balancing.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor 9

Design Recommendations

5.2 Power Supply

•33µF, 0.1 µF, and 0.01 µF across each power supply

5.2.1 Supply Voltage Sequencing and Separation Cautions

Figure 1 shows situations in sequencing the I/O VDD (OVDD), PLL VDD (PLLVDD), and Core VDD (VDD).

OVDD is specified relative to VDD.

OV

3.3V
Supplies Stable

2.5V

DD

1.5V

DC Power Supply Voltage

0

Notes:

1.

2.

3.

4.

Figure 1. Supply Voltage Sequencing and Separation Cautions

1

2

VDD should not exceed OVDD or PLLVDD by more than 0.4 V
at any time, including power-up.
Recommended that VDD/PLLVDD should track OVDD up to

0.9 V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (OVDD,
VDD, or PLLVDD) by more than 0.5 V at any time, including during power-up.
Use 1 ms or slower rise time for all supplies.

VDD, PLLV

DD

Time

5.2.1.1 Power Up Sequence

If OVDD are powered up with VDD at 0 V, then the sense circuits in the I/O pads will cause all pad output
drivers connected to the OV
powers up before V

must powered up. VDD should not lead the OVDD or PLLVDD by more than 0.4 V

DD

during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times
on the power supplies should be slower than 1 µs to avoid turning on the internal ESD protection clamp
diodes.

to be in a high impedance state. There is no limit on how long after OVDD

DD

The recommended power up sequence is as follows:

1. Use 1 µs or slower rise time for all supplies.

2. V

/PLLVDD and OVDD should track up to 0.9 V, then separate for the completion of ramps with

DD

OV

going to the higher external voltages. One way to accomplish this is to use a low drop-out

DD

voltage regulator.

MCF523x Integrated Microprocessor Hardware Specification, Rev. 2

Freescale Semiconductor10

Design Recommendations

5.2.1.2 Power Down Sequence

If VDD/PLLVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to
be in a high impedance state. There is no limit on how long after VDD and PLLVDD power down before
OV
power down or there will be undesired high current in the ESD protection diodes. There are no
requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

must power down. VDD should not lag OVDD or PLLVDD going low by more than 0.4 V during

DD

1. Drop V

/PLLVDD to 0 V.

DD

2. Drop OVDD supplies.

5.3 Decoupling

• Place the decoupling caps as close to the pins as possible, but they can be outside the footprint of
the package.

• 0.1 µF and 0.01 µF at each supply input

5.4 Buffering

• Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses
when excessive loading is expected. See Section 7, “Preliminary Electrical Characteristics.”

5.5 Pull-up Recommendations

• Use external pull-up resistors on unused inputs. See pin table.

5.6 Clocking Recommendations

• Use a multi-layer board with a separate ground plane.

• Place the crystal and all other associated components as close to the EXTAL and XTAL (oscillator
pins) as possible.

• Do not run a high frequency trace around crystal circuit.

• Ensure that the ground for the bypass capacitors is connected to a solid ground trace.

• Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop currents
in the vicinity of the crystal.

• Tie the ground pin to the most solid ground in the system.

• Do not connect the trace that connects the oscillator and the ground plane to any other circuit
element. This tends to make the oscillator unstable.

• Tie XTAL to ground when an external oscillator is clocking the device.

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Design Recommendations

5.7 Interface Recommendations

5.7.1 SDRAM Controller

5.7.1.1 SDRAM Controller Signals in Synchronous Mode

Table 3 shows the behavior of SDRAM signals in synchronous mode.

Table 3. Synchronous DRAM Signal Connections

Signal Description

SD_SRAS

SD_SCAS

DRAMW

SD_CS

SD_CKE Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of

BS

CLKOUT Bus clock output. Connects to the CLK input of SDRAMs.

Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be

latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM
SD_SRAS
be interfaced to the SDRAM SD_SRAS signals.

Synchronous column address strobe. Indicates a valid column address is present and can be

latched by the SDRAM. SD_SCAS
SD_SCAS on the SDRAM.

DRAM read/write. Asserted for write operations and negated for read operations.

[1:0] Row address strobe. Select each memory block of SDRAMs connected to the MCF523x. One

SD_CS signal selects one SDRAM block and connects to the corresponding CS signals.

SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can
enter a power-down mode where operations are suspended or they can enter self-refresh mode.
SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing,
setting COC allows SD_CKE to provide command-bit functionality.

[3:0] Column address strobe. For synchronous operation, BS[3:0] function as byte enables to the

SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs.

. Do not confuse SD_SRAS with the DRAM controller’s SD_CS[1:0], which should not

should be connected to the corresponding signal labeled

5.7.1.2 Address Multiplexing

See the SDRAM controller module chapter in the MCF5235 Reference Manual for details on address
multiplexing.

5.7.2 Ethernet PHY Transceiver Connection

The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10
Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3
standard defines and the FEC module supports 18 signals. These are shown in Table 4.

Table 4. MII Mode

Signal Description MCF523x Pin

Transmit clock ETXCLK

Transmit enable ETXEN

Transmit data ETXD[3:0]

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Design Recommendations

Table 4. MII Mode (continued)

Signal Description MCF523x Pin

Transmit error ETXER

Collision ECOL

Carrier sense ECRS

Receive clock ERXCLK

Receive enable ERXDV

Receive data ERXD[3:0]

Receive error ERXER

Management channel clock EMDC

Management channel serial data EMDIO

The serial mode interface operates in what is generally referred to as AMD mode. The MCF523x
configuration for seven-wire serial mode connections to the external transceiver are shown in Table 5.

Table 5. Seven-Wire Mode Configuration

Signal Description MCF523x Pin

Transmit clock ETXCLK

Transmit enable ETXEN

Transmit data ETXD[0]

Collision ECOL

Receive clock ERXCLK

Receive enable ERXDV

Receive data ERXD[0]

Unused, configure as PB14 ERXER

Unused input, tie to ground ECRS

Unused, configure as PB[13:11] ERXD[3:1]

Unused output, ignore ETXER

Unused, configure as PB[10:8] ETXD[3:1]

Unused, configure as PB15 EMDC

Input after reset, connect to ground EMDIO

Refer to the M523xEVB evaluation board user’s manual for an example of how to connect an external
PHY. Schematics for this board are accessible at the MCF5235 site by navigating to:

http://www.freescale.com/coldfire.

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Mechanicals/Pinouts and Part Numbers

5.7.3 FlexCAN

The FlexCAN module interface to the CAN bus is composed of 2 pins: CANTX and CANRX, which are
the serial transmitted data and the serial received data. The use of an external CAN transceiver to interface
to the CAN bus is generally required. The transceiver is capable of driving the large current needed for the
CAN bus and has current protection, against a defective CAN bus or defective stations.

5.7.4 BDM

Use the BDM interface as shown in the M523xEVB evaluation board user’s manual. The schematics for
this board are accessible at the Freescale website at: http://www.freescale.com/coldfire.

6 Mechanicals/Pinouts and Part Numbers

This section contains drawings showing the pinout and the packaging and mechanical characteristics of
the MCF523x devices. See Table 2 for a list the signal names and pin locations for each device.

6.1 Pinout—196 MAPBGA

The following figure shows a pinout of the MCF5232CVMxxx package.

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