Freescale MCF5216 DATA SHEET

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MCF5216 ColdFire

Freescale Semiconductor, Inc.

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MCF5216UM/D

Rev. 0

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Microcontroller User’s Manu

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MCF521

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Overview

Freescale Semiconductor, Inc.

ColdFire Core

Enhanced Multiply-Accumulate Unit (EMAC)

Cache

Static RAM (SRAM)

ColdFire Flash Module (CFM)

Power Management

System Control Module (SCM)

Clock Module Interrupt Controller Modules Edge Port Module (EPORT)

Chip Select Module

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External Interface Module (EIM)

Signal Descriptions

Synchronous DRAM Controller Module

3 4 5

6 7 8

9 10 11 12 13 14 15

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DMA Controller Module

Watchdog Timer Module

Programmable Interrupt Timer (PIT) Modules

General Purpose Timer (GPT) Modules

DMA Timers

Queued Serial Peripheral Interface Module (QSPI)

UART Modules

C Module

FlexCAN Module

General Purpose I/O Module

Chip Configuration Module (CCM)

Queued Analog-to-Digital Converter (QADC)

Reset Controller Module

Debug Support

16 17 18 19 20 21 22 23 24 25 26 27 28 29

IEEE 1149.1 Test Access Port (JTAG)

Mechanical Data

Electrical Characteristics

Appendix A: List of Memory Maps

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Index

30 31 32

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Overview

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3 4 5

6 7 8

9 10 11 12

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13 14 15

ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache S tatic RAM (SRAM) ColdFire Flash Module (CFM) Power Management System Control Module (SCM) Clock Module Interrupt Controller Modules Edge Port Module (EPORT) Chip Select Module External Interface Module (EIM) Signal Descriptions Synchronous DRAM Controller Module

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16 17 18 19 20 21 22 23 24 25 26 27 28 29

DMA Controller Module Watchdog Timer Module

Programmable Interrupt Timer (PIT) Modules General Purpose Ti mer (GPT) Modules DMA Timers Queued Serial Peripheral Interface Module (QSPI) UART Modules

C Module

FlexCAN Module General Purpose I/O Module Chip Configuration Module (CCM) Queued Analog-to-Digital Converter (QADC) Reset Controller Module Debug Support

30 31 32

IND

IEEE 1149.1 Test Access Port (JTAG) Mechanical Data Electrical Characteristics Appendix A: List of Memory Maps Index

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CONTENTS

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Paragraph Number

Title

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Chapter 1

Overview

1.1 MCF5216 Key Features...................................................................................... 1-1

1.1.1 Version 2 ColdFire Core................................................................................. 1-8

1.1.2 System Control Module................................................................................ 1-10

1.1.3 External Interface Module (EIM) ................................................................. 1-10

1.1.4 Chip Select.................................................................................................... 1-11

1.1.5 Power Management ...................................................................................... 1-11

1.1.6 General Input/Output Ports........................................................................... 1-11

1.1.7 Interrupt Controllers (INTC0/INTC1).......................................................... 1-11

1.1.8 SDRAM Controller....................................................................................... 1-11

1.1.9 Test Access Port............................................................................................ 1-12

1.1.10 UART Modules............................................................................................. 1-12

1.1.11 DMA Timers (DTIM0-DTIM3) ................................................................... 1-13

1.1.12 General-Purpose Timers (GPTA/GPTB)...................................................... 1-13

1.1.13 Periodic Interrupt Timers (PIT0-PIT3)......................................................... 1-13

1.1.14 Software Watchdog Timer............................................................................ 1-14

1.1.15 Phase Locked Loop (PLL)............................................................................ 1-14

1.1.16 DMA Controller............................................................................................ 1-14

1.1.17 Reset.............................................................................................................. 1-14

1.2 MCF5216-Specific Features............................................................................. 1-15

1.2.1 FlexCAN....................................................................................................... 1-15

1.2.2 I2C Bus.......................................................................................................... 1-15

1.2.3 Queued Serial Peripheral Interface (QSPI)................................................... 1-15

1.2.4 Queued Analog-to-Digital Converter (QADC) ............................................ 1-15

Chapter 2

ColdFire Core

2.1 Processor Pipelines ............................................................................................. 2-1

2.2 Processor Register Description........................................................................... 2-2

2.2.1 User Programming Model .............................................................................. 2-2

2.2.2 Programming Model ..................................................................................... 2-5

2.2.3 Supervisor Programming Model..................................................................... 2-5

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2.3 Programming Model........................................................................................... 2-8

2.4 Additions to the Instruction Set Architecture ..................................................... 2-9

2.5 Exception Processing Overview....................................................................... 2-10

2.6 Exception Stack Frame Definition.................................................................... 2-12

2.7 Processor Exceptions........................................................................................ 2-13

2.7.1 Access Error Exception ................................................................................ 2-13

2.7.2 Address Error Exception............................................................................... 2-14

2.7.3 Illegal Instruction Exception......................................................................... 2-14

2.7.4 Divide-By-Zero............................................................................................. 2-14

2.7.5 Privilege Violation........................................................................................ 2-14

2.7.6 Trace Exception............................................................................................ 2-14

2.7.7 Unimplemented Line-A Opcode................................................................... 2-15

2.7.8 Unimplemented Line-F Opcode ................................................................... 2-15

2.7.9 Debug Interrupt............................................................................................. 2-15

2.7.10 RTE and Format Error Exception................................................................. 2-16

2.7.11 TRAP Instruction Exception......................................................................... 2-16

2.7.12 Interrupt Exception....................................................................................... 2-16

2.7.13 Fault-on-Fault Halt ....................................................................................... 2-16

2.7.14 Reset Exception ............................................................................................ 2-16

2.8 Instruction Execution Timing........................................................................... 2-20

2.8.1 Timing Assumptions..................................................................................... 2-21

2.8.2 MOVE Instruction Execution Times............................................................ 2-22

2.9 Standard One Operand Instruction Execution Times ....................................... 2-23

2.10 Standard Two Operand Instruction Execution Times....................................... 2-24

2.11 Miscellaneous Instruction Execution Times..................................................... 2-25

2.12 EMAC Instruction Execution Times ................................................................ 2-26

2.13 Branch Instruction Execution Times ................................................................ 2-28

2.14 ColdFire Instruction Set Architecture Enhancements ...................................... 2-28

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Chapter 3

Enhanced Multiply-Accumulate Unit (EMAC)

3.1 Multiply-Accumulate Unit.................................................................................. 3-1

3.2 Introduction to the MAC..................................................................................... 3-2

3.3 General Operation............................................................................................... 3-3

3.4 Memory Map/Register Set.................................................................................. 3-4

3.4.1 MAC Status Register (MACSR) .................................................................... 3-4

3.4.2 Mask Register (MASK).................................................................................. 3-8

3.5 MAC Instruction Set Summary .......................................................................... 3-9

3.5.1 MAC Instruction Execution Times................................................................. 3-9

3.5.2 Data Representation........................................................................................ 3-9

3.5.3 MAC Opcodes .............................................................................................. 3-10

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Chapter 4

Cache

4.1 Cache Features.................................................................................................... 4-1

4.2 Cache Physical Organization.............................................................................. 4-1

4.3 Cache Operation ................................................................................................. 4-3

4.3.1 Interaction with Other Modules...................................................................... 4-3

4.3.2 Memory Reference Attributes ........................................................................ 4-4

4.3.3 Cache Coherency and Invalidation................................................................. 4-4

4.3.4 Reset................................................................................................................ 4-5

4.3.5 Cache Miss Fetch Algorithm/Line Fills ......................................................... 4-5

4.4 Cache Programming Model................................................................................ 4-7

4.4.1 Cache Registers Memory Map ....................................................................... 4-7

4.4.2 Cache Registers............................................................................................... 4-7

Chapter 5

Static RAM (SRAM)

5.1 SRAM Features................................................................................................... 5-1

5.2 SRAM Operation................................................................................................ 5-1

5.3 SRAM Programming Model............................................................................... 5-1

5.3.1 SRAM Base Address Register (RAMBAR)................................................... 5-2

5.3.2 SRAM Initialization........................................................................................ 5-3

5.3.3 SRAM Initialization Code.............................................................................. 5-4

5.3.4 Power Management ........................................................................................ 5-4

Chapter 6

ColdFire Flash Module (CFM)

6.1 Features............................................................................................................... 6-1

6.2 Block Diagram.................................................................................................... 6-2

6.3 Memory Map ...................................................................................................... 6-4

6.3.1 CFM Configuration Field ............................................................................... 6-5

6.3.2 Flash Base Address Register (FLASHBAR).................................................. 6-5

6.3.3 CFM Registers................................................................................................ 6-8

6.3.4 Register Descriptions...................................................................................... 6-9

6.4 CFM Operation................................................................................................. 6-17

6.4.1 Read Operations............................................................................................ 6-17

6.4.2 Write Operations........................................................................................... 6-17

6.4.3 Program and Erase Operations ..................................................................... 6-17

6.4.4 Stop Mode..................................................................................................... 6-22

6.4.5 Master Mode................................................................................................. 6-23

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6.5 Flash Security Operation .................................................................................. 6-23

6.5.1 Back Door Access......................................................................................... 6-24

6.5.2 Erase Verify Check....................................................................................... 6-24

6.6 Reset.................................................................................................................. 6-24

6.7 Interrupts........................................................................................................... 6-25

Title

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Chapter 7

Power Management

7.1 Features............................................................................................................... 7-1

7.2 Memory Map and Registers................................................................................ 7-1

7.2.1 Programming Model....................................................................................... 7-1

7.2.2 Memory Map .................................................................................................. 7-2

7.2.3 Register Descriptions...................................................................................... 7-2

7.3 Functional Description........................................................................................ 7-5

7.3.1 Low-Power Modes.......................................................................................... 7-5

7.3.2 Peripheral Behavior in Low-Power Modes .................................................... 7-7

7.3.3 Summary of Peripheral State During Low-Power Modes............................ 7-16

Chapter 8

System Control Module (SCM)

8.1 Overview............................................................................................................. 8-1

8.2 Features............................................................................................................... 8-1

8.3 Memory Map and Register Definition................................................................ 8-2

8.4 Register Descriptions.......................................................................................... 8-3

8.4.1 Internal Peripheral System Base Address Register (IPSBAR)....................... 8-3

8.4.2 Memory Base Address Register (RAMBAR) ................................................ 8-4

8.4.3 Core Reset Status Register (CRSR)................................................................ 8-6

8.4.4 Core Watchdog Control Register (CWCR).................................................... 8-6

8.4.5 Core Watchdog Service Register (CWSR)..................................................... 8-9

8.5 Internal Bus Arbitration...................................................................................... 8-9

8.5.1 Overview....................................................................................................... 8-10

8.5.2 Arbitration Algorithms ................................................................................. 8-11

8.5.3 Bus Master Park Register (MPARK)............................................................ 8-12

8.6 System Access Control Unit (SACU)............................................................... 8-13

8.6.1 Overview....................................................................................................... 8-13

8.6.2 Features......................................................................................................... 8-14

8.6.3 Memory Map/Register Definition ................................................................ 8-15

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Chapter 9

Clock Module

9.1 Features............................................................................................................... 9-1

9.2 Modes of Operation ............................................................................................ 9-1

9.2.1 Normal PLL Mode.......................................................................................... 9-1

9.2.2 1:1 PLL Mode................................................................................................. 9-2

9.2.3 External Clock Mode...................................................................................... 9-2

9.3 Low-power Mode Operation .............................................................................. 9-2

9.4 Block Diagram.................................................................................................... 9-3

9.5 Signal Descriptions............................................................................................. 9-4

9.5.1 EXTAL ........................................................................................................... 9-4

9.5.2 XTAL.............................................................................................................. 9-5

9.5.3 CLKOUT........................................................................................................ 9-5

9.5.4 CLKMOD[1:0] ............................................................................................... 9-5

9.5.5 RSTOUT

9.6 Memory Map and Registers................................................................................ 9-5

9.6.1 Module Memory Map..................................................................................... 9-5

9.6.2 Register Descriptions...................................................................................... 9-6

9.7 Functional Description...................................................................................... 9-10

9.7.1 System Clock Modes.................................................................................... 9-10

9.7.2 Clock Operation During Reset...................................................................... 9-11

9.7.3 System Clock Generation ............................................................................. 9-11

9.7.4 PLL Operation .............................................................................................. 9-12

......................................................................................................... 9-5

Chapter 10

Interrupt Controller Modules

10.1 68K/ColdFire Interrupt Architecture Overview ............................................... 10-1

10.1.1 Interrupt Controller Theory of Operation..................................................... 10-3

10.2 Memory Map .................................................................................................... 10-5

10.3 Register Descriptions........................................................................................ 10-6

10.3.1 Interrupt Pending Registers (IPRHn, IPRLn)............................................... 10-6

10.3.2 Interrupt Mask Register (IMRHn, IMRLn).................................................. 10-8

10.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)................................... 10-9

10.3.4 Interrupt Request Level Register (IRLRn) ................................................. 10-10

10.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn)............ 10-11

10.3.6 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63)).................................. 10-11

10.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK). 10-15

10.4 Prioritization Between Interrupt Controllers .................................................. 10-16

10.5 Low-Power Wakeup Operation ...................................................................... 10-17

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Chapter 11

Edge Port Module (EPORT)

11.1 Introduction....................................................................................................... 11-1

11.2 Low-Power Mode Operation ............................................................................ 11-1

11.3 Interrupt/General-Purpose I/O Pin Descriptions............................................... 11-2

11.4 Memory Map and Registers.............................................................................. 11-3

11.4.1 Memory Map ................................................................................................ 11-3

11.4.2 Registers........................................................................................................ 11-3

Chapter 12

Chip Select Module

12.1 Overview........................................................................................................... 12-1

12.2 Chip Select Module Signals.............................................................................. 12-1

12.3 Chip Select Operation....................................................................................... 12-3

12.3.1 General Chip Select Operation..................................................................... 12-3

12.4 Chip Select Registers........................................................................................ 12-5

12.4.1 Chip Select Module Registers....................................................................... 12-6

Chapter 13

External Interface Module (EIM)

13.1 Features............................................................................................................. 13-1

13.2 Bus and Control Signals ................................................................................... 13-1

13.3 Bus Characteristics ........................................................................................... 13-2

13.4 Data Transfer Operation ................................................................................... 13-2

13.4.1 Bus Cycle Execution..................................................................................... 13-3

13.4.2 Data Transfer Cycle States ........................................................................... 13-5

13.4.3 Read Cycle.................................................................................................... 13-6

13.4.4 Write Cycle................................................................................................... 13-8

13.4.5 Fast Termination Cycles............................................................................... 13-9

13.4.6 Back-to-Back Bus Cycles........................................................................... 13-10

13.4.7 Burst Cycles................................................................................................ 13-10

13.5 Misaligned Operands...................................................................................... 13-14

Chapter 14

Signal Descriptions

14.1 Overview........................................................................................................... 14-1

14.1.1 Single-Chip Mode....................................................................................... 14-15

14.1.2 External Boot Mode.................................................................................... 14-15

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14.2 MCF5216 External Signals............................................................................. 14-16

14.2.1 External Interface Module (EIM) Signals .................................................. 14-16

14.2.2 SDRAM Controller Signals........................................................................ 14-19

14.2.3 Clock and Reset Signals ............................................................................. 14-20

14.2.4 Chip Configuration Signals ........................................................................ 14-20

14.2.5 External Interrupt Signals........................................................................... 14-21

14.2.6 Queued Serial Peripheral Interface (QSPI) Signals.................................... 14-21

14.2.7 FlexCAN Signals........................................................................................ 14-21

14.2.8 I2C Signals.................................................................................................. 14-22

14.2.9 UART Module Signals ............................................................................... 14-22

14.2.10 General Purpose Timer Signals .................................................................. 14-23

14.2.11 DMA Timer Signals.................................................................................... 14-23

14.2.12 Analog-to-Digital Converter Signals.......................................................... 14-25

14.2.13 Debug Support Signals ............................................................................... 14-26

14.2.14 Test Signals................................................................................................. 14-28

14.2.15 Power and Reference Signals ..................................................................... 14-28

Title

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Chapter 15

Synchronous DRAM Controller Module

15.1 Overview........................................................................................................... 15-1

15.1.1 Definitions .................................................................................................... 15-1

15.1.2 Block Diagram and Major Components....................................................... 15-2

15.2 SDRAM Controller Operation.......................................................................... 15-3

15.2.1 DRAM Controller Signals............................................................................ 15-4

15.2.2 Memory Map for SDRAMC Registers......................................................... 15-4

15.2.3 General Synchronous Operation Guidelines................................................. 15-9

15.2.4 Initialization Sequence................................................................................ 15-17

15.3 SDRAM Example........................................................................................... 15-19

15.3.1 SDRAM Interface Configuration................................................................ 15-20

15.3.2 DCR Initialization....................................................................................... 15-20

15.3.3 DACR Initialization.................................................................................... 15-21

15.3.4 DMR Initialization...................................................................................... 15-22

15.3.5 Mode Register Initialization ....................................................................... 15-23

15.3.6 Initialization Code....................................................................................... 15-24

Chapter 16

DMA Controller Module

16.1 Overview........................................................................................................... 16-1

16.1.1 DMA Module Features................................................................................. 16-2

16.2 DMA Request Control (DMAREQC) .............................................................. 16-3

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16.3 DMA Transfer Overview.................................................................................. 16-4

16.4 DMA Controller Module Programming Model................................................ 16-5

16.4.1 Source Address Registers (SAR0–SAR3).................................................... 16-6

16.4.2 Destination Address Registers (DAR0–DAR3) ........................................... 16-6

16.4.3 Byte Count Registers (BCR0–BCR3) .......................................................... 16-7

16.4.4 DMA Control Registers (DCR0–DCR3)...................................................... 16-8

16.4.5 DMA Status Registers (DSR0–DSR3)....................................................... 16-10

16.5 DMA Controller Module Functional Description .......................................... 16-11

16.5.1 Transfer Requests (Cycle-Steal and Continuous Modes) 16-11

16.5.2 Data Transfer Modes .................................................................................. 16-12

16.5.3 Channel Initialization and Startup.............................................................. 16-13

16.5.4 Data Transfer .............................................................................................. 16-14

16.5.5 Termination................................................................................................. 16-15

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Chapter 17

Watchdog Timer Module

17.1 Introduction....................................................................................................... 17-1

17.2 Low-Power Mode Operation ............................................................................ 17-1

17.3 Block Diagram.................................................................................................. 17-2

17.4 Signals............................................................................................................... 17-2

17.5 Memory Map and Registers.............................................................................. 17-2

17.5.1 Memory Map ................................................................................................ 17-2

17.5.2 Registers........................................................................................................ 17-3

Chapter 18

Programmable Interrupt Timer Modules (PIT0–PIT3)

18.1 Overview........................................................................................................... 18-1

18.2 Block Diagram.................................................................................................. 18-1

18.3 Low-Power Mode Operation ............................................................................ 18-2

18.4 Signals............................................................................................................... 18-2

18.5 Memory Map and Registers.............................................................................. 18-3

18.5.1 Memory Map ................................................................................................ 18-3

18.5.2 Registers........................................................................................................ 18-3

18.6 Functional Description...................................................................................... 18-6

18.6.1 Set-and-Forget Timer Operation................................................................... 18-6

18.6.2 Free-Running Timer Operation .................................................................... 18-7

18.6.3 Timeout Specifications................................................................................. 18-7

18.7 Interrupt Operation ........................................................................................... 18-8

xii MCF5216 User’s Manual MOTOROLA

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Chapter 19

General Purpose Timer Modules

(GPTA and GPTB)

19.1 Features............................................................................................................. 19-1

19.2 Block Diagram.................................................................................................. 19-2

19.3 Low-Power Mode Operation ............................................................................ 19-3

19.4 Signal Description............................................................................................. 19-3

19.4.1 GPTn[2:0]..................................................................................................... 19-3

19.4.2 GPTn3........................................................................................................... 19-4

19.4.3 SYNCn.......................................................................................................... 19-4

19.5 Memory Map and Registers.............................................................................. 19-4

19.5.1 GPT Input Capture/Output Compare Select Register (GPTIOS)................. 19-5

19.5.2 GPT Compare Force Register (GPCFORC)................................................. 19-6

19.5.3 GPT Output Compare 3 Mask Register (GPTOC3M).................................. 19-6

19.5.4 GPT Output Compare 3 Data Register (GPTOC3D).................................... 19-7

19.5.5 GPT Counter Register (GPTCNT) ............................................................... 19-7

19.5.6 GPT System Control Register 1 (GPTSCR1)............................................... 19-8

19.5.7 GPT Toggle-On-Overflow Register (GPTTOV).......................................... 19-9

19.5.8 GPT Control Register 1 (GPTCTL1)............................................................ 19-9

19.5.9 GPT Control Register 2 (GPTCTL2).......................................................... 19-10

19.5.10 GPT Interrupt Enable Register (GPTIE) .................................................... 19-10

19.5.11 GPT System Control Register 2 (GPTSCR2)............................................. 19-11

19.5.12 GPT Flag Register 1 (GPTFLG1)............................................................... 19-12

19.5.13 GPT Flag Register 2 (GPTFLG2)............................................................... 19-12

19.5.14 GPT Channel Registers (GPTCn)............................................................... 19-13

19.5.15 Pulse Accumulator Control Register (GPTPACTL) .................................. 19-13

19.5.16 Pulse Accumulator Flag Register (GPTPAFLG)........................................ 19-14

19.5.17 Pulse Accumulator Counter Register (GPTPACNT) ................................. 19-15

19.5.18 GPT Port Data Register (GPTPORT)......................................................... 19-16

19.5.19 GPT Port Data Direction Register (GPTDDR)........................................... 19-16

19.6 Functional Description.................................................................................... 19-17

19.6.1 Prescaler...................................................................................................... 19-17

19.6.2 Input Capture .............................................................................................. 19-17

19.6.3 Output Compare.......................................................................................... 19-17

19.6.4 Pulse Accumulator...................................................................................... 19-18

19.6.5 Event Counter Mode................................................................................... 19-18

19.6.6 Gated Time Accumulation Mode ............................................................... 19-19

19.6.7 General-Purpose I/O Ports.......................................................................... 19-19

19.7 Reset................................................................................................................ 19-21

19.8 Interrupts......................................................................................................... 19-21

19.8.1 GPT Channel Interrupts (CnF) ................................................................... 19-22

19.8.2 Pulse Accumulator Overflow (PAOVF)..................................................... 19-22

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19.8.3 Pulse Accumulator Input (PAIF)................................................................ 19-22

19.8.4 Timer Overflow (TOF)............................................................................... 19-22

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Chapter 20

DMA Timers (DTIM0–DTIM3)

20.1 Overview........................................................................................................... 20-1

20.1.1 Key Features................................................................................................. 20-2

20.2 DMA Timer Programming Model.................................................................... 20-2

20.2.1 Prescaler........................................................................................................ 20-2

20.2.2 Capture Mode ............................................................................................... 20-3

20.2.3 Reference Compare....................................................................................... 20-3

20.2.4 Output Mode................................................................................................. 20-3

20.2.5 Memory Map ................................................................................................ 20-3

20.2.6 DMA Timer Mode Registers (DTMRn)....................................................... 20-4

20.2.7 DMA Timer Extended Mode Registers (DTXMRn).................................... 20-5

20.2.8 DMA Timer Event Registers (DTERn)........................................................ 20-6

20.2.9 DMA Timer Reference Registers (DTRRn)................................................. 20-7

20.2.10 DMA Timer Capture Registers (DTCRn) .................................................... 20-7

20.2.11 DMA Timer Counters (DTCNn) .................................................................. 20-8

20.3 Using the DMA Timer Modules....................................................................... 20-8

20.3.1 Code Example............................................................................................... 20-9

20.3.2 Calculating Time-Out Values..................................................................... 20-10

Chapter 21

Queued Serial Peripheral Interface

(QSPI) Module

21.1 Overview........................................................................................................... 21-1

21.2 Features............................................................................................................. 21-1

21.3 Module Description .......................................................................................... 21-1

21.3.1 Interface and Signals..................................................................................... 21-2

21.3.2 Internal Bus Interface.................................................................................... 21-3

21.4 Operation .......................................................................................................... 21-3

21.4.1 QSPI RAM.................................................................................................... 21-4

21.4.2 Baud Rate Selection...................................................................................... 21-6

21.4.3 Transfer Delays............................................................................................. 21-7

21.4.4 Transfer Length............................................................................................. 21-8

21.4.5 Data Transfer ................................................................................................ 21-8

21.5 Programming Model......................................................................................... 21-9

21.5.1 QSPI Mode Register (QMR) ...................................................................... 21-10

21.5.2 QSPI Delay Register (QDLYR) ................................................................. 21-11

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21.5.3 QSPI Wrap Register (QWR)....................................................................... 21-12

21.5.4 QSPI Interrupt Register (QIR).................................................................... 21-13

21.5.5 QSPI Address Register (QAR)................................................................... 21-14

21.5.6 QSPI Data Register (QDR)......................................................................... 21-14

21.5.7 Command RAM Registers (QCR0–QCR15).............................................. 21-15

21.5.8 Programming Example............................................................................... 21-16

Title

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Chapter 22

UART Modules

22.1 Overview........................................................................................................... 22-1

22.2 Serial Module Overview................................................................................... 22-2

22.3 Register Descriptions........................................................................................ 22-3

22.3.1 UART Mode Registers 1 (UMR1n).............................................................. 22-4

22.3.2 UART Mode Register 2 (UMR2n)............................................................... 22-6

22.3.3 UART Status Registers (USRn) ................................................................... 22-7

22.3.4 UART Clock Select Registers (UCSRn)...................................................... 22-8

22.3.5 UART Command Registers (UCRn)............................................................ 22-9

22.3.6 UART Receive Buffers (URBn)................................................................. 22-11

22.3.7 UART Transmit Buffers (UTBn) ............................................................... 22-11

22.3.8 UART Input Port Change Registers (UIPCRn).......................................... 22-12

22.3.9 UART Auxiliary Control Register (UACRn)............................................. 22-13

22.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)......................... 22-13

22.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)......................... 22-14

22.3.12 UART Input Port Register (UIPn).............................................................. 22-15

22.3.13 UART Output Port Command Registers (UOP1n/UOP0n) ....................... 22-15

22.4 UART Module Signal Definitions.................................................................. 22-16

22.5 Operation ........................................................................................................ 22-17

22.5.1 Transmitter/Receiver Clock Source............................................................ 22-17

22.5.2 Transmitter and Receiver Operating Modes............................................... 22-19

22.5.3 Looping Modes........................................................................................... 22-24

22.5.4 Multidrop Mode.......................................................................................... 22-26

22.5.5 Bus Operation............................................................................................. 22-28

22.5.6 Programming .............................................................................................. 22-28

Chapter 23

C Interface

23.1 Overview........................................................................................................... 23-1

23.2 Interface Features.............................................................................................. 23-1

23.3 I2C System Configuration................................................................................. 23-3

23.4 I2C Protocol ...................................................................................................... 23-3

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23.4.1 Arbitration Procedure ................................................................................... 23-4

23.4.2 Clock Synchronization.................................................................................. 23-5

23.4.3 Handshaking ................................................................................................. 23-5

23.4.4 Clock Stretching ........................................................................................... 23-5

23.5 Programming Model......................................................................................... 23-6

23.5.1 I

23.5.2 I2C Frequency Divider Register (I2FDR)..................................................... 23-7

23.5.3 I

23.5.4 I

23.5.5 I2C Data I/O Register (I2DR)..................................................................... 23-10

23.6 I

23.6.1 Initialization Sequence................................................................................ 23-10

23.6.2 Generation of START................................................................................. 23-11

23.6.3 Post-Transfer Software Response............................................................... 23-11

23.6.4 Generation of STOP.................................................................................... 23-12

23.6.5 Generation of Repeated START................................................................. 23-13

23.6.6 Slave Mode................................................................................................. 23-13

23.6.7 Arbitration Lost........................................................................................... 23-14

C Address Register (I2ADR)..................................................................... 23-6

C Control Register (I2CR)......................................................................... 23-8

C Status Register (I2SR)............................................................................ 23-9

C Programming Examples........................................................................... 23-10

Title

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Chapter 24

FlexCAN

24.1 Features............................................................................................................. 24-1

24.1.1 FlexCAN Memory Map................................................................................ 24-3

24.1.2 External Signals............................................................................................ 24-3

24.2 The CAN System.............................................................................................. 24-4

24.3 Message Buffers ............................................................................................... 24-4

24.3.1 Message Buffer Structure ............................................................................. 24-4

24.3.2 Message Buffer Memory Map...................................................................... 24-7

24.4 Functional Overview......................................................................................... 24-8

24.4.1 Transmit Process........................................................................................... 24-9

24.4.2 Receive Process ............................................................................................ 24-9

24.4.3 Message Buffer Handling........................................................................... 24-10

24.4.4 Remote Frames........................................................................................... 24-12

24.4.5 Overload Frames......................................................................................... 24-13

24.4.6 Time Stamp................................................................................................. 24-13

24.4.7 Listen-Only Mode....................................................................................... 24-13

24.4.8 Bit Timing................................................................................................... 24-14

24.4.9 FlexCAN Error Counters............................................................................ 24-15

24.4.10 FlexCAN Initialization Sequence............................................................... 24-16

24.4.11 Special Operating Modes............................................................................ 24-17

24.4.12 Interrupts..................................................................................................... 24-19

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24.5 Programmer’s Model...................................................................................... 24-20

24.5.1 CAN Module Configuration Register (CANMCR).................................... 24-20

24.5.2 FlexCAN Control Register 0 (CANCTRL0).............................................. 24-22

24.5.3 FlexCAN Control Register 1 (CANCTRL1).............................................. 24-23

24.5.4 Prescaler Divide Register (PRESDIV)....................................................... 24-24

24.5.5 FlexCAN Control Register 2 (CANCTRL2).............................................. 24-25

24.5.6 Free Running Timer (TIMER).................................................................... 24-26

24.5.7 Rx Mask Registers...................................................................................... 24-26

24.5.8 FlexCAN Error and Status Register (ESTAT) ........................................... 24-28

24.5.9 Interrupt Mask Register (IMASK).............................................................. 24-30

24.5.10 Interrupt Flag Register (IFLAG)................................................................. 24-31

nc...

24.5.11 FlexCAN Receive Error Counter (RXECTR)............................................ 24-32

24.5.12 FlexCAN Transmit Error Counter (TXECTR)........................................... 24-32

Title

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Chapter 25

General Purpose I/O Module

25.1 Introduction....................................................................................................... 25-1

25.1.1 Overview....................................................................................................... 25-3

25.1.2 Features......................................................................................................... 25-3

25.1.3 Modes of Operation...................................................................................... 25-3

25.2 External Signal Description.............................................................................. 25-4

25.3 Memory Map/Register Definition .................................................................... 25-6

25.3.1 Register Overview ........................................................................................ 25-6

25.3.2 Register Descriptions.................................................................................... 25-8

25.4 Functional Description.................................................................................... 25-25

cale Semiconductor,

25.4.1 Overview..................................................................................................... 25-25

25.4.2 Port Digital I/O Timing .............................................................................. 25-25

25.5 Initialization/Application Information............................................................ 25-26

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Chapter 26

Queued Analog-to-Digital Converter (QADC)

26.1 Features............................................................................................................. 26-1

26.2 Block Diagram.................................................................................................. 26-2

26.3 Modes of Operation .......................................................................................... 26-3

26.3.1 Debug Mode ................................................................................................. 26-3

26.3.2 Stop Mode..................................................................................................... 26-3

26.4 Signals............................................................................................................... 26-4

26.4.1 Port QA Signal Functions............................................................................. 26-4

26.4.2 Port QB Signal Functions............................................................................. 26-5

26.4.3 External Trigger Input Signals...................................................................... 26-6

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26.4.4 Multiplexed Address Output Signals............................................................ 26-6

26.4.5 Multiplexed Analog Input Signals................................................................ 26-6

26.4.6 Voltage Reference Signals............................................................................ 26-7

26.4.7 Dedicated Analog Supply Signals ................................................................ 26-7

26.4.8 Dedicated Digital I/O Port Supply Signal..................................................... 26-7

26.5 Memory Map .................................................................................................... 26-7

26.6 Register Descriptions........................................................................................ 26-8

26.6.1 QADC Module Configuration Register (QADCMCR)................................ 26-8

26.6.2 QADC Test Register (QADCTEST) ............................................................ 26-9

26.6.3 Port Data Registers (PORTQA and PORTQB)............................................ 26-9

26.6.4 Port QA and QB Data Direction Register (DDRQA and DDRQB)........... 26-10

26.6.5 Control Registers ........................................................................................ 26-11

26.6.6 Status Registers........................................................................................... 26-19

26.6.7 Conversion Command Word Table (CCW) ............................................... 26-26

26.6.8 Result Registers .......................................................................................... 26-29

26.7 Functional Description.................................................................................... 26-31

26.7.1 Result Coherency........................................................................................ 26-31

26.7.2 External Multiplexing................................................................................. 26-31

26.7.3 Analog Subsystem ...................................................................................... 26-34

26.8 Digital Control Subsystem.............................................................................. 26-37

26.8.1 Queue Priority Timing Examples............................................................... 26-38

26.8.2 Boundary Conditions.................................................................................. 26-49

26.8.3 Scan Modes................................................................................................. 26-50

26.8.4 Disabled Mode............................................................................................ 26-50

26.8.5 Reserved Mode........................................................................................... 26-50

26.8.6 Single-Scan Modes..................................................................................... 26-50

26.8.7 Continuous-Scan Modes............................................................................. 26-54

26.8.8 QADC Clock (QCLK) Generation............................................................. 26-57

26.8.9 Periodic/Interval Timer............................................................................... 26-58

26.8.10 Conversion Command Word Table............................................................ 26-59

26.8.11 Result Word Table...................................................................................... 26-62

26.9 Signal Connection Considerations.................................................................. 26-62

26.9.1 Analog Reference Signals........................................................................... 26-63

26.9.2 Analog Power Signals................................................................................. 26-63

26.9.3 Conversion Timing Schemes...................................................................... 26-64

26.9.4 Analog Supply Filtering and Grounding .................................................... 26-67

26.9.5 Accommodating Positive/Negative Stress Conditions............................... 26-69

26.9.6 Analog Input Considerations...................................................................... 26-71

26.9.7 Analog Input Pins ....................................................................................... 26-73

26.10 Interrupts......................................................................................................... 26-75

26.10.1 Interrupt Operation ..................................................................................... 26-75

26.10.2 Interrupt Sources......................................................................................... 26-76

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Chapter 27

Reset Controller Module

27.1 Features............................................................................................................. 27-1

27.2 Block Diagram.................................................................................................. 27-2

27.3 Signals............................................................................................................... 27-2

27.3.1 RSTI............................................................................................................. 27-2

27.3.2 RSTO

27.4 Memory Map and Registers.............................................................................. 27-3

27.4.1 Reset Control Register (RCR) ...................................................................... 27-3

27.4.2 Reset Status Register (RSR)......................................................................... 27-4

27.5 Functional Description...................................................................................... 27-6

27.5.1 Reset Sources................................................................................................ 27-6

27.5.2 Reset Control Flow....................................................................................... 27-8

27.5.3 Concurrent Resets....................................................................................... 27-10

........................................................................................................... 27-2

Chapter 28

Debug Support

28.1 Overview........................................................................................................... 28-1

28.2 Signal Description............................................................................................. 28-2

28.3 Real-Time Trace Support.................................................................................. 28-3

28.3.1 Begin Execution of Taken Branch (PST = 0x5)........................................... 28-4

28.4 Programming Model......................................................................................... 28-5

28.4.1 Revision A Shared Debug Resources........................................................... 28-7

28.4.2 Address Attribute Trigger Register (AATR)................................................ 28-8

28.4.3 Address Breakpoint Registers (ABLR, ABHR)........................................... 28-9

28.4.4 Configuration/Status Register (CSR) ......................................................... 28-10

28.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)....................................... 28-12

28.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR).................... 28-13

28.4.7 Trigger Definition Register (TDR)............................................................. 28-14

28.5 Background Debug Mode (BDM).................................................................. 28-16

28.5.1 CPU Halt..................................................................................................... 28-16

28.5.2 BDM Serial Interface.................................................................................. 28-18

28.5.3 BDM Command Set ................................................................................... 28-20

28.6 Real-Time Debug Support.............................................................................. 28-37

28.6.1 Theory of Operation.................................................................................... 28-37

28.6.2 Concurrent BDM and Processor Operation................................................ 28-39

28.7 Processor Status, DDATA Definition............................................................. 28-40

28.7.1 User Instruction Set .................................................................................... 28-40

28.7.2 Supervisor Instruction Set........................................................................... 28-44

28.8 Motorola-Recommended BDM Pinout........................................................... 28-46

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Chapter 29

Chip Configuration Module (CCM)

29.1 Features............................................................................................................. 29-1

29.2 Modes of Operation .......................................................................................... 29-1

29.2.1 Master Mode................................................................................................. 29-2

29.2.2 Single-Chip Mode......................................................................................... 29-2

29.3 Block Diagram.................................................................................................. 29-2

29.4 Signal Descriptions........................................................................................... 29-3

29.4.1 RCON ........................................................................................................... 29-3

29.4.2 CLKMOD[1:0] ............................................................................................. 29-3

29.4.3 D[26:24, 21, 19:16] (Reset Configuration Override) ................................... 29-3

29.5 Memory Map and Registers.............................................................................. 29-3

29.5.1 Programming Model..................................................................................... 29-3

29.5.2 Memory Map ................................................................................................ 29-4

29.5.3 Register Descriptions.................................................................................... 29-5

29.6 Functional Description...................................................................................... 29-8

29.6.1 Reset Configuration...................................................................................... 29-8

29.6.2 Chip Mode Selection .................................................................................. 29-10

29.6.3 Boot Device Selection ................................................................................ 29-11

29.6.4 Output Pad Strength Configuration ............................................................ 29-11

29.6.5 Clock Mode Selection................................................................................. 29-11

29.6.6 Chip Select Configuration .......................................................................... 29-12

29.7 Reset................................................................................................................ 29-12

29.8 Interrupts......................................................................................................... 29-12

Chapter 30

IEEE 1149.1 Test Access Port (JTAG)

30.1 Features............................................................................................................. 30-2

30.2 Modes of Operation .......................................................................................... 30-3

30.3 External Signal Description.............................................................................. 30-3

30.3.1 Detailed Signal Description.......................................................................... 30-3

30.4 Memory Map/Register Definition .................................................................... 30-5

30.4.1 Memory Map ................................................................................................ 30-5

30.4.2 Register Descriptions.................................................................................... 30-5

30.5 Functional Description...................................................................................... 30-7

30.5.1 JTAG Module............................................................................................... 30-7

30.5.2 TAP Controller ............................................................................................. 30-7

30.5.3 JTAG Instructions......................................................................................... 30-8

30.6 Initialization/Application Information............................................................ 30-11

30.6.1 Restrictions ................................................................................................. 30-11

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30.6.2 Nonscan Chain Operation........................................................................... 30-12

Title

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Chapter 31

Mechanical Data

31.1 Pinout................................................................................................................ 31-2

31.2 Ordering Information........................................................................................ 31-7

Chapter 32

Electrical Characteristics

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cale Semiconductor,

32.1 Maximum Ratings............................................................................................. 32-1

32.2 Thermal Characteristics.................................................................................... 32-3

32.3 DC Electrical Specifications............................................................................. 32-4

32.4 Phase Lock Loop Electrical Specifications ...................................................... 32-5

32.5 QADC Electrical Characteristics...................................................................... 32-7

32.6 Flash Memory Characteristics .......................................................................... 32-9

32.7 External Interface Timing Characteristics........................................................ 32-9

32.8 Processor Bus Output Timing Specifications................................................. 32-11

32.9 General Purpose I/O Timing........................................................................... 32-17

32.10 Reset and Configuration Override Timing ..................................................... 32-18

32.11 I2C Input/Output Timing Specifications......................................................... 32-19

32.12 DMA Timer Module AC Timing Specifications............................................ 32-21

32.13 QSPI Electrical Specifications........................................................................ 32-21

32.14 JTAG and Boundary Scan Timing.................................................................. 32-22

32.15 Debug AC Timing Specifications................................................................... 32-24

Appendix A

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Figure Number

1-1 MCF5216 Block Diagram ............................................................................................ 1-7

2-1 ColdFire Processor Core Pipelines............................................................................... 2-1

2-2 User Programming Model ............................................................................................ 2-4

2-3 Condition Code Register (CCR)...................................................................................2-4

2-4 MAC Register Set......................................................................................................... 2-5

2-5 Supervisor Programming Model................................................................................... 2-6

2-6 Status Register ..............................................................................................................2-6

2-7 Exception Stack Frame Form ..................................................................................... 2-12

2-8 D0 Hardware Configuration Info................................................................................ 2-17

2-9 D1 Hardware Configuration Info................................................................................ 2-19

3-1 Multiply-Accumulate Functionality Diagram .............................................................. 3-2

3-2 Infinite Impulse Response (IIR) Filter.......................................................................... 3-3

3-3 Four-Tap FIR Filter ...................................................................................................... 3-3

3-4 MAC Register Set......................................................................................................... 3-4

3-5 MAC Status Register (MACSR)................................................................................... 3-4

3-6 Two’s Complement, Signed Fractional Equation......................................................... 3-9

4-1 Cache Block Diagram................................................................................................... 4-3

4-2 Cache Control Register (CACR) .................................................................................. 4-8

4-3 Access Control Registers (ACR0, ACR1).................................................................. 4-11

5-1 SRAM Base Address Register (RAMBAR)................................................................. 5-2

6-1 CFM Block Diagram .................................................................................................... 6-3

6-2 CFM Array Memory Map............................................................................................. 6-4

6-3 Flash Base Address Register (FLASHBAR)................................................................ 6-7

6-4 CFM Module Configuration Register (CFMCR) ......................................................... 6-9

6-5 CFM Clock Divider Register (CFMCLKD)............................................................... 6-10

6-6 CFM Security Register (CFMSEC)............................................................................ 6-11

6-7 CFM Protection Register (CFMPROT)...................................................................... 6-12

6-8 CFMPROT Protection Diagram ................................................................................. 6-13

6-9 CFM Supervisor Access Register (CFMSACC) ........................................................ 6-13

6-10 CFM Data Access Register (CFMDACC).................................................................. 6-14

6-11 CFM User Status Register (CFMUSTAT) ................................................................. 6-15

6-12 CFM Command Register (CFMCMD)....................................................................... 6-16

6-13 Example Program Algorithm...................................................................................... 6-21

7-1 Low-Power Interrupt Control Register (LPICR).........................................................7-3

7-2 Low-Power Control Register (LPCR) ......................................................................... 7-4

8-1 IPS Base Address Register (IPSBAR)..........................................................................8-4

Title

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Figure Number

8-2 Memory Base Address Register (RAMBAR) .............................................................. 8-5

8-3 Core Reset Status Register (CRSR)............................................................................. 8-6

8-4 Core Watchdog Control Register (CWCR) ................................................................. 8-8

8-5 Core Watchdog Service Register (CWSR)..................................................................8-9

8-6 Arbiter Module Functions .......................................................................................... 8-10

8-7 Default Bus Master Park Register (MPARK)............................................................. 8-12

8-8 Master Privilege Register (MPR) .............................................................................. 8-16

8-9 Peripheral Access Control Register (PACRn)............................................................8-16

8-10 GPACR Register......................................................................................................... 8-18

9-1 Clock Module Block Diagram...................................................................................... 9-3

9-2 PLL Block Diagram...................................................................................................... 9-4

9-3 Synthesizer Control Register (SYNCR) ....................................................................... 9-6

9-4 Synthesizer Status Register (SYNSR).......................................................................... 9-8

9-5 Crystal Oscillator Example......................................................................................... 9-12

9-6 Lock Detect Sequence ................................................................................................9-15

10-1 Interrupt Pending Register High (IPRHn) .................................................................. 10-7

10-2 Interrupt Pending Register Low (IPRLn) ................................................................... 10-7

10-3 Interrupt Mask Register High (IMRHn)..................................................................... 10-8

10-4 Interrupt Mask Register Low (IMRLn) ...................................................................... 10-8

10-5 Interrupt Force Register High (INTFRCHn) .............................................................. 10-9

10-6 Interrupt Force Register Low (INTFRCLn) ............................................................. 10-10

10-7 Interrupt Request Level Register (IRLRn) ............................................................... 10-10

10-8 IACK Level and Priority Register (IACKLPRn) ..................................................... 10-11

10-9 Interrupt Control Register (ICRnx)........................................................................... 10-12

10-10 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)...............10-16

11-1 EPORT Block Diagram .............................................................................................. 11-1

11-2 EPORT Pin Assignment Register (EPPAR)............................................................... 11-4

11-3 EPORT Data Direction Register (EPDDR)................................................................11-4

11-4 EPORT Port Interrupt Enable Register (EPIER)........................................................ 11-5

11-5 EPORT Port Data Register (EPDR) ........................................................................... 11-5

11-6 EPORT Port Pin Data Register (EPPDR)................................................................... 11-6

11-7 EPORT Port Flag Register (EPFR) ............................................................................ 11-6

12-1 Connections for External Memory Port Sizes ............................................................ 12-4

12-2 Chip Select Address Registers (CSARn)................................................................... 12-6

12-3 Chip Select Mask Registers (CSMRn) ...................................................................... 12-7

12-4 Chip Select Control Registers (CSCRn)..................................................................... 12-8

13-1 Signal Relationship to CLKOUT for Non-DRAM Access ........................................ 13-2

13-2 Connections for External Memory Port Sizes ............................................................ 13-3

13-3 Chip-Select Module Output Timing Diagram............................................................ 13-3

13-4 Data Transfer State Transition Diagram.....................................................................13-5

13-5 Read Cycle Flowchart................................................................................................. 13-7

13-6 Basic Read Bus Cycle................................................................................................. 13-7

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Figure Number

13-7 Write Cycle Flowchart................................................................................................ 13-8

13-8 Basic Write Bus Cycle................................................................................................ 13-8

13-9 Read Cycle with Fast Termination ............................................................................. 13-9

13-10 Write Cycle with Fast Termination ............................................................................ 13-9

13-11 Back-to-Back Bus Cycles......................................................................................... 13-10

13-12 Line Read Burst (2-1-1-1), External Termination .................................................... 13-11

13-13 Line Read Burst (2-1-1-1), Internal Termination ..................................................... 13-12

13-14 Line Read Burst (3-2-2-2), External Termination .................................................... 13-12

13-15 Line Read Burst-Inhibited, Fast Termination, External Termination....................... 13-13

13-16 Line Write Burst (2-1-1-1), Internal/External Termination...................................... 13-13

13-17 Line Write Burst (3-2-2-2) with One Wait State...................................................... 13-14

13-18 Line Write Burst-Inhibited........................................................................................ 13-14

13-19 Example of a Misaligned Longword Transfer (32-Bit Port) .................................... 13-15

13-20 Example of a Misaligned Word Transfer (32-Bit Port)............................................ 13-15

14-1 MCF5216 Block Diagram with Signal Interfaces ...................................................... 14-1

15-1 Synchronous DRAM Controller Block Diagram........................................................ 15-2

15-2 DRAM Control Register (DCR).................................................................................15-5

15-3 DRAM Address and Control Register (DACRn)....................................................... 15-6

15-4 DRAM Controller Mask Registers (DMRn) .............................................................. 15-8

15-5 Connections for External Memory Port Sizes .......................................................... 15-13

15-6 Burst Read SDRAM Access.....................................................................................15-14

15-7 Burst Write SDRAM Access.................................................................................... 15-15

15-8 Auto-Refresh Operation............................................................................................15-16

15-9 Self-Refresh Operation ............................................................................................. 15-17

15-10 Mode Register Set (mrs) Command ......................................................................... 15-19

15-11 Initialization Values for DCR...................................................................................15-20

15-12 SDRAM Configuration............................................................................................. 15-21

15-13 DACR Register Configuration.................................................................................. 15-21

15-14 DMR0 Register.........................................................................................................15-22

16-1 DMA Signal Diagram................................................................................................. 16-2

16-2 DMA Request Control Register (DMAREQC).......................................................... 16-3

16-3 Dual-Address Transfer................................................................................................ 16-4

16-4 Source Address Registers (SARn).............................................................................. 16-6

16-5 Destination Address Registers (DARn)...................................................................... 16-6

16-6 Byte Count Registers (BCRn)—BCR24BIT = 1........................................................ 16-7

16-7 Byte Count Registers (BCRn)—BCR24BIT = 0........................................................ 16-7

16-8 DMA Control Registers (DCRn)................................................................................ 16-8

16-9 DMA Status Registers (DSRn)................................................................................16-10

17-1 Watchdog Timer Block Diagram................................................................................17-2

17-2 Watchdog Control Register (WCR)............................................................................ 17-3

17-3 Watchdog Modulus Register (WMR)......................................................................... 17-4

17-4 Watchdog Count Register (WCNTR)......................................................................... 17-5

17-5 Watchdog Service Register (WSR) ............................................................................ 17-6

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18-1 PIT Block Diagram..................................................................................................... 18-1

18-2 PIT Control and Status Register (PCSR).................................................................... 18-4

18-3 PIT Modulus Register (PMR)..................................................................................... 18-6

18-4 PIT Count Register (PCNTR)..................................................................................... 18-6

18-5 Counter Reloading from the Modulus Latch.............................................................. 18-7

18-6 Counter in Free-Running Mode.................................................................................. 18-7

19-1 GPT Block Diagram ................................................................................................... 19-2

19-2 GPT Input Capture/Output Compare Select Register (GPTIOS)............................... 19-5

19-3 GPT Input Compare Force Register (GPCFORC) ..................................................... 19-6

19-4 GPT Output Compare 3 Mask Register (GPTOC3M)................................................ 19-6

19-5 GPT Output Compare 3 Data Register (GPTOC3D).................................................. 19-7

19-6 GPT Counter Register (GPTCNT) ............................................................................. 19-7

19-7 GPT System Control Register 1 (GPTSCR1)............................................................. 19-8

19-8 Fast Clear Flag Logic.................................................................................................. 19-9

19-9 GPT Toggle-On-Overflow Register (GPTTOV)........................................................19-9

19-10 GPT Control Register 1 (GPTCTL1).......................................................................... 19-9

19-11 GPT Control Register 2 (GPTCTL2)........................................................................ 19-10

19-12 GPT Interrupt Enable Register (GPTIE) ..................................................................19-10

19-13 GPT System Control Register 2 (GPTSCR2)........................................................... 19-11

19-14 GPT Flag Register 1 (GPTFLG1)............................................................................. 19-12

19-15 GPT Flag Register 2 (GPTFLG2)............................................................................. 19-12

19-16 GPT Channel[0:3] Register (GPTCn)....................................................................... 19-13

19-17 Pulse Accumulator Control Register (GPTPACTL) ................................................ 19-13

19-18 Pulse Accumulator Flag Register (GPTPAFLG)...................................................... 19-14

19-19 Pulse Accumulator Counter Register (GPTPACNT) ............................................... 19-15

19-20 GPT Port Data Register (GPTPORT)....................................................................... 19-16

19-21 GPT Port Data Direction Register (GPTDDR)......................................................... 19-16

19-22 Channel 3 Output Compare/Pulse Accumulator Logic ............................................ 19-19

20-1 DMA Timer Block Diagram....................................................................................... 20-2

20-2 DTMRn Bit Definitions..............................................................................................20-4

20-3 DTXMRn Bit Definitions........................................................................................... 20-5

20-4 DTERn Bit Definitions............................................................................................... 20-6

20-5 DTRRn Bit Definitions............................................................................................... 20-7

20-6 DTCRn Bit Definitions............................................................................................... 20-8

20-7 DTCNn Bit Definitions............................................................................................... 20-8

21-1 QSPI Block Diagram .................................................................................................. 21-2

21-2 QSPI RAM Model ...................................................................................................... 21-5

21-3 QSPI Mode Register (QMR) .................................................................................... 21-10

21-4 QSPI Clocking and Data Transfer Example............................................................. 21-11

21-5 QSPI Delay Register (QDLYR) ............................................................................... 21-11

21-6 QSPI Wrap Register (QWR)..................................................................................... 21-12

21-7 QSPI Interrupt Register (QIR).................................................................................. 21-13

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21-8 QSPI Address Register ............................................................................................. 21-14

21-9 QSPI Data Register (QDR)....................................................................................... 21-14

21-10 Command RAM Registers (QCR0–QCR15)............................................................ 21-15

21-11 QSPI Timing.............................................................................................................21-16

22-1 Simplified Block Diagram..........................................................................................22-1

22-2 UART Mode Registers 1 (UMR1n)............................................................................ 22-4

22-3 UART Mode Register 2 (UMR2n)............................................................................. 22-6

22-4 UART Status Register (USRn)...................................................................................22-7

22-5 UART Clock Select Register (UCSRn)...................................................................... 22-8

22-6 UART Command Register (UCRn)............................................................................ 22-9

22-7 UART Receive Buffer (URBn) ................................................................................ 22-11

22-8 UART Transmit Buffer (UTBn)...............................................................................22-12

22-9 UART Input Port Change Register (UIPCRn) ......................................................... 22-12

22-10 UART Auxiliary Control Register (UACRn)........................................................... 22-13

22-11 UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 22-13

22-12 UART Baud Rate Generator Register (UBG1n) ...................................................... 22-14

22-13 UART Baud Rate Generator Register (UBG2n) ...................................................... 22-14

22-14 UART Input Port Register (UIPn)............................................................................22-15

22-15 UART Output Port Command Registers (UOP1n/UOP0n) ..................................... 22-15

22-16 UART Block Diagram Showing External and Internal Interface Signals................ 22-16

22-17 UART/RS-232 Interface........................................................................................... 22-17

22-18 Clocking Source Diagram.........................................................................................22-18

22-19 Transmitter and Receiver Functional Diagram......................................................... 22-20

22-20 Transmitter Timing Diagram................................................................................... 22-21

22-21 Receiver Timing ....................................................................................................... 22-23

22-22 Automatic Echo ........................................................................................................ 22-25

22-23 Local Loop-Back ...................................................................................................... 22-25

22-24 Remote Loop-Back...................................................................................................22-26

22-25 Multidrop Mode Timing Diagram............................................................................ 22-27

22-26 UART Mode Programming Flowchart..................................................................... 22-31

23-1 I

23-2 I2C Standard Communication Protocol...................................................................... 23-3

23-3 Repeated START........................................................................................................ 23-4

23-4 Synchronized Clock SCL............................................................................................ 23-5

23-5 I2C Address Register (I2ADR)................................................................................... 23-6

23-6 I2C Frequency Divider Register (I2FDR) ................................................................. 23-7

23-7 I2C Control Register (I2CR)....................................................................................... 23-8

23-8 I2CR Status Register (I2SR)...................................................................................... 23-9

23-9 I2C Data I/O Register (I2DR).................................................................................. 23-10

23-10 Flow-Chart of Typical I2C Interrupt Routine........................................................... 23-15

24-1 FlexCAN Block Diagram and Pinout........................................................................ 24-2

24-2 Typical CAN system................................................................................................... 24-4

24-3 Extended ID Message Buffer Structure...................................................................... 24-5

C Module Block Diagram ....................................................................................... 23-2

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24-4 Standard ID Message Buffer Structure.......................................................................24-5

24-5 FlexCAN Memory Map.............................................................................................. 24-8

24-6 CAN Module Configuration Register (CANMCR).................................................. 24-20

24-7 FlexCAN Control Register 0 (CANCTRL0)............................................................ 24-22

24-8 FlexCAN Control Register 1 (CANCTRL1)............................................................ 24-23

24-9 Prescaler Divide Register (PRESDIV) ..................................................................... 24-24

24-10 FlexCAN Control Register 2 (CANCTRL2)............................................................ 24-25

24-11 Free Running Timer (TIMER)..................................................................................24-26

24-12 Rx Mask Registers (RXGMASK, RX14MASK, and RX15MASK) ....................... 24-27

24-13 FlexCAN Error and Status Register (ESTAT) ......................................................... 24-28

24-14 Interrupt Mask Register (IMASK)............................................................................24-30

24-15 Interrupt Flag Register (IFLAG)............................................................................... 24-31

24-16 FlexCAN Receive Error Counter (RXECTR) .......................................................... 24-32

24-17 FlexCAN Transmit Error Counter (TXECTR)......................................................... 24-32

25-1 MCF5216 Ports Module Block Diagram.................................................................... 25-2

25-2 Port Output Data Registers (8-bit)..............................................................................25-8

25-3 Port Output Data Register (7-bit)................................................................................ 25-8

25-4 Port Output Data Registers (6-bit)..............................................................................25-8

25-5 Port Output Data Registers (4-bit)..............................................................................25-9

25-6 Port Data Direction Registers (8-bit)..........................................................................25-9

25-7 Port Data Direction Register (7-bit).......................................................................... 25-10

25-8 Port Data Direction Registers (6-bit)........................................................................25-10

25-9 Port Data Direction Registers (4-bit)........................................................................25-10

25-10 Port Pin Data/Set Data Registers (8-bit)..................................................................25-11

25-11 Port Pin Data/Set Data Register (7-bit)..................................................................... 25-11

25-12 Port Pin Data/Set Data Registers (6-bit)...................................................................25-11

25-13 Port Pin Data/Set Data Registers (4-bit)...................................................................25-12

25-14 Port Clear Output Data Registers (8-bit) .................................................................. 25-12

25-15 Port Clear Output Data Register (7-bit).................................................................... 25-13

25-16 Port Clear Output Data Registers (6-bit) .................................................................. 25-13

25-17 Port Clear Output Data Registers (4-bit) .................................................................. 25-13

25-18 Port B/C/D Pin Assignment Register (PBCDPAR).................................................. 25-14

25-19 Port E Pin Assignment Register (PEPAR) ............................................................... 25-15

25-20 Port F Pin Assignment Register (PFPAR)................................................................ 25-17

25-21 Port J Pin Assignment Register (PJPAR)................................................................ 25-18

25-22 Port SD Pin Assignment Register (PSDPAR)..........................................................25-19

25-23 Port AS Pin Assignment Register (PASPAR)..........................................................25-19

25-24 Port EL Pin Assignment Register (PELPAR).......................................................... 25-20

25-25 Port QS Pin Assignment Register (PQSPAR)..........................................................25-21

25-26 Port TC Pin Assignment Register (PTCPAR).........................................................25-22

25-27 Port TD Pin Assignment Register (PTDPAR)......................................................... 25-23

25-28 Port UA Pin Assignment Register (PUAPAR)........................................................ 25-24

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25-29 Digital Input Timing.................................................................................................25-25

25-30 Digital Output Timing .............................................................................................. 25-26

26-1 QADC Block Diagram................................................................................................ 26-2

26-2 QADC Input and Output Signals................................................................................26-5

26-3 QADC Module Configuration Register (QADCMCR)..............................................26-9

26-4 QADC Port QA Data Register (PORTQA).............................................................. 26-10

26-5 QADC Port QB Data Register (PORTQB)............................................................... 26-10

26-6 QADC Port QA Data Direction Register (DDRQA)................................................ 26-11

26-7 Port QB Data Direction Register (DDRQB)............................................................. 26-11

26-8 QADC Control Register 0 (QACR0)........................................................................ 26-12

26-9 QADC Control Register 1 (QACR1)........................................................................ 26-14

26-10 QADC Control Register 2 (QACR2)........................................................................ 26-17

26-11 QADC Status Register 0 (QASR0)........................................................................... 26-22

26-12 Queue Status Transition............................................................................................ 26-25

26-13 QADC Status Register 1 (QASR1)........................................................................... 26-26

26-14 Conversion Command Word Table (CCW) ............................................................. 26-27

26-15 Right-Justified Unsigned Result Register (RJURR)................................................. 26-29

26-16 Left-Justified Signed Result Register (LJSRR)........................................................26-30

26-17 Left-Justified Unsigned Result Register (LJURR)................................................... 26-31

26-18 External Multiplexing Configuration........................................................................ 26-33

26-19 QADC Analog Subsystem Block Diagram .............................................................. 26-35

26-20 Conversion Timing................................................................................................... 26-36

26-21 Bypass Mode Conversion Timing ............................................................................ 26-36

26-22 QADC Queue Operation with Pause ........................................................................ 26-39

26-23 CCW Priority Situation 1.......................................................................................... 26-41

26-24 CCW Priority Situation 2.......................................................................................... 26-42

26-25 CCW Priority Situation 3.......................................................................................... 26-42

26-26 CCW Priority Situation 4.......................................................................................... 26-43

26-27 CCW Priority Situation 5.......................................................................................... 26-43

26-28 CCW Priority Situation 6.......................................................................................... 26-44

26-29 CCW Priority Situation 7.......................................................................................... 26-44

26-30 CCW Priority Situation 8.......................................................................................... 26-45

26-31 CCW Priority Situation 9.......................................................................................... 26-45

26-32 CCW Priority Situation 10........................................................................................ 26-46

26-33 CCW Priority Situation 11........................................................................................ 26-46

26-34 CCW Freeze Situation 12 ......................................................................................... 26-47

26-35 CCW Freeze Situation 13 ......................................................................................... 26-47

26-36 CCW Freeze Situation 14 ......................................................................................... 26-47

26-37 . CCW Freeze Situation 15 ....................................................................................... 26-47

26-38 CCW Freeze Situation 16 ......................................................................................... 26-48

26-39 CCW Freeze Situation 17 ......................................................................................... 26-48

26-40 CCW Freeze Situation 18 ......................................................................................... 26-48

26-41 CCW Freeze Situation 19 ......................................................................................... 26-48

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26-42 QADC Clock Subsystem Functions ......................................................................... 26-58

26-43 QADC Conversion Queue Operation ....................................................................... 26-60

26-44 Equivalent Analog Input Circuitry ........................................................................... 26-63

26-45 Errors Resulting from Clipping ................................................................................ 26-64

26-46 External Positive Edge Trigger Mode Timing with Pause....................................... 26-65

26-47 Gated Mode, Single Scan Timing............................................................................. 26-66

26-48 Gated Mode, Continuous Scan Timing..................................................................... 26-67

26-49 Star-Ground at the Point of Power Supply Origin.................................................... 26-68

26-50 Input Signal Subjected to Negative Stress................................................................ 26-69

26-51 Input Signal Subjected to Positive Stress ................................................................. 26-70

26-52 External Multiplexing of Analog Signal Sources..................................................... 26-72

26-53 Electrical Model of an A/D Input Signal..................................................................26-73

27-1 Reset Controller Block Diagram................................................................................. 27-2

27-2 Reset Control Register (RCR) .................................................................................... 27-3

27-3 Reset Status Register (RSR)....................................................................................... 27-4

27-4 Reset Control Flow..................................................................................................... 27-9

28-1 Processor/Debug Module Interface ............................................................................ 28-1

28-2 CLKOUT Timing ....................................................................................................... 28-2

28-3 Example JMP Instruction Output on PST/DDATA ................................................... 28-5

28-4 Debug Programming Model ....................................................................................... 28-6

28-5 Address Attribute Trigger Register (AATR)..............................................................28-8

28-6 Address Breakpoint Registers (ABLR, ABHR)......................................................... 28-9

28-7 Configuration/Status Register (CSR)........................................................................ 28-10

28-8 Data Breakpoint/Mask Registers (DBR/DBMR) ..................................................... 28-12

28-9 Program Counter Breakpoint Register (PBR) .......................................................... 28-14

28-10 Program Counter Breakpoint Mask Register (PBMR).............................................28-14

28-11 Trigger Definition Register (TDR)...........................................................................28-15

28-12 BDM Serial Interface Timing...................................................................................28-18

28-13 Receive BDM Packet................................................................................................ 28-19

28-14 Transmit BDM Packet.............................................................................................. 28-19

28-15 BDM Command Format........................................................................................... 28-21

28-16 Command Sequence Diagram .................................................................................. 28-22

28-17 RAREG/RDREG Command Format ............................................................................. 28-23

28-18 RAREG/RDREG Command Sequence.......................................................................... 28-23

28-19 WAREG/WDREG Command Format............................................................................ 28-24

28-20 WAREG/WDREG Command Sequence........................................................................ 28-24

28-21 READ Command/Result Formats............................................................................... 28-25

28-22 READ Command Sequence........................................................................................ 28-25

28-23 WRITE Command Format .......................................................................................... 28-26

28-24 WRITE Command Sequence ...................................................................................... 28-27

28-25 DUMP Command/Result Formats.............................................................................28-28

28-26 DUMP Command Sequence....................................................................................... 28-29

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28-27 FILL Command Format ............................................................................................ 28-30

28-28 28-29

28-30 GO Command Sequence............................................................................................ 28-31

28-31 28-32

28-33 RCREG Command/Result Formats............................................................................. 28-32

28-34 28-35

28-36 WCREG Command Sequence.....................................................................................28-35

28-37

28-38 RDMREG Command Sequence................................................................................... 28-36

28-39 WDMREG BDM Command Format............................................................................ 28-36

28-40 WDMREG Command Sequence..................................................................................28-36

28-41 Recommended BDM Connector...............................................................................28-46

29-1 Chip Configuration Module Block Diagram.............................................................. 29-2

29-2 Chip Configuration Register (CCR)........................................................................... 29-5

29-3 Reset Configuration Register (RCON).......................................................................29-6

29-4 Chip Identification Register (CIR) ............................................................................. 29-8

30-1 JTAG Block Diagram................................................................................................. 30-2

30-2 IDCODE Register.......................................................................................................30-5

30-3 TAP Controller State Machine Flow .......................................................................... 30-8

31-1 MCF5216 Pinout (256 MAPBGA)............................................................................. 31-2

31-2 256 MAPBGA Package Dimensions.......................................................................... 31-7

32-1 General Input Timing Requirements ........................................................................ 32-11

32-2 Read/Write (Internally Terminated) Timing............................................................. 32-13

32-3 Read Bus Cycle Terminated by TA.......................................................................... 32-14

32-4 Read Bus Cycle Terminated by TEA ....................................................................... 32-15

32-5 SDRAM Read Cycle................................................................................................. 32-16

32-6 SDRAM Write Cycle................................................................................................ 32-17

32-7 GPIO Timing ............................................................................................................ 32-18

32-8 RSTI and Configuration Override Timing................................................................ 32-19

32-9 I2C Input/Output Timings......................................................................................... 32-20

32-10 QSPI Timing.............................................................................................................32-21

32-11 Test Clock Input Timing........................................................................................... 32-22

32-12 Boundary Scan (JTAG) Timing................................................................................32-23

32-13 Test Access Port Timing........................................................................................... 32-23

32-14 TRST Timing............................................................................................................ 32-23

32-15 BKPT Timing ........................................................................................................... 32-24

32-16 Real-Time Trace AC Timing.................................................................................... 32-25

32-17 BDM Serial Port AC Timing....................................................................................32-25

FILL Command Sequence.......................................................................................... 28-30

GO Command Format................................................................................................ 28-31

NOP Command Format.............................................................................................. 28-31

NOP Command Sequence..........................................................................................28-31

RCREG Command Sequence...................................................................................... 28-33

WCREG Command/Result Formats............................................................................ 28-34

RDMREG Command/Result Formats......................................................................... 28-35

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Table Number

1-1 Cache Configuration.....................................................................................................1-8

2-1 CCR Field Descriptions................................................................................................2-4

2-2 SR Field Descriptions................................................................................................... 2-6

2-3 ColdFire CPU Registers................................................................................................ 2-8

2-4 ISA Revision A+ New Instructions ............................................................................ 2-10

2-5 Exception Vector Assignments................................................................................... 2-11

2-6 Format Field Encodings.............................................................................................. 2-12

2-7 Fault Status Encodings................................................................................................ 2-13

2-8 D0 Hardware Configuration Info Field Description................................................... 2-18

2-9 D1 Local Memory Hardware Configuration Information Field Description ............. 2-19

2-10 Misaligned Operand References.................................................................................2-22

2-11 Move Byte and Word Execution Times .....................................................................2-22

2-12 Move Long Execution Times .................................................................................... 2-23

2-13 One Operand Instruction Execution Times ................................................................ 2-23

2-14 Two Operand Instruction Execution Times................................................................ 2-24

2-15 Miscellaneous Instruction Execution Times............................................................... 2-25

2-16 EMAC Instruction Execution Times .......................................................................... 2-26

2-17 General Branch Instruction Execution Times............................................................. 2-28

2-18 BRA, Bcc Instruction Execution Times ..................................................................... 2-28

3-1 MACSR Field Descriptions..........................................................................................3-5

3-2 Summary of S/U, F/I, and R/T Control Bits.................................................................3-6

3-3 MAC Instruction Summary .......................................................................................... 3-9

4-1 Initial Fetch Offset vs. CLNF Bits................................................................................ 4-5

4-2 Instruction Cache Operation as Defined by CACR[31, 10] ......................................... 4-6

4-3 Memory Map of Cache Registers................................................................................. 4-7

4-4 CACR Field Descriptions............................................................................................. 4-8

4-5 Cache Configuration as Defined by CACR[31, 23, 22] ............................................. 4-10

4-6 Cache Invalidate All as Defined by CACR[23, 22, 21, 20]........................................ 4-10

4-7 External Fetch Size Based on Miss Address and CLNF ............................................ 4-11

4-8 ACR Field Descriptions.............................................................................................. 4-11

5-1 SRAM Base Address Register...................................................................................... 5-2

5-2 Typical RAMBAR Setting Examples........................................................................... 5-4

6-1 CFM Configuration Field ............................................................................................ 6-5

6-2 FLASHBAR Field Descriptions................................................................................... 6-7

6-3 CFM Register Address Map......................................................................................... 6-8

6-4 CFMCR Field Descriptions.......................................................................................... 6-9

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6-5 CFMCLKD Field Descriptions................................................................................... 6-10

6-6 CFMSEC Field Descriptions...................................................................................... 6-11

6-7 CFMPROT Field Descriptions ................................................................................... 6-12

6-8 CFMSACC Field Descriptions................................................................................... 6-14

6-9 CFMDACC Field Descriptions .................................................................................. 6-14

6-10 CFMUSTAT Field Descriptions................................................................................. 6-15

6-11 CFMCMD Field Descriptions .................................................................................... 6-16

6-12 CFMCMD User Mode Commands............................................................................. 6-16

6-13 Flash User Commands................................................................................................6-20

6-14 CFM Interrupt Sources ............................................................................................... 6-25

7-1 Chip Configuration Module Memory Map................................................................... 7-2

7-2 LPICR Field Description .............................................................................................. 7-3

7-3 XLPM_IPL Settings ..................................................................................................... 7-4

7-4 LPCR Field Descriptions..............................................................................................7-4

7-5 Low-Power Modes........................................................................................................ 7-5

7-6 PLL/CLKOUT Stop Mode Operation .......................................................................... 7-5

7-7 CPU and Peripherals in Low-Power Modes...............................................................7-16

8-1 SCM Register Map ....................................................................................................... 8-2

8-2 IPSBAR Field Description............................................................................................ 8-4

8-3 RAMBAR Field Description........................................................................................ 8-5

8-4 CRSR Field Descriptions..............................................................................................8-6

8-5 CWCR Field Description.............................................................................................. 8-8

8-6 Core Watchdog Timer Delay........................................................................................8-8

8-7 MPARK Field Description ......................................................................................... 8-12

8-8 SACU Register Memory Map .................................................................................... 8-15

8-9 MPR[n] Field Descriptions......................................................................................... 8-16

8-10 PACR Field Descriptions............................................................................................ 8-16

8-11 PACR ACCESSCTRL Bit Encodings........................................................................ 8-17

8-12 Peripheral Access Control Registers (PACRs)........................................................... 8-17

8-13 Grouped PeripheralAccess Control Register (GPACR) Field Descriptions............... 8-18

8-14 GPACR ACCESS_CTRL Bit Encodings................................................................... 8-19

8-15 GPACR Address Space .............................................................................................. 8-19

9-1 Clock Module Operation in Low-power Modes........................................................... 9-2

9-2 Signal Properties..........................................................................................................9-4

9-3 Clock Module Memory Map ........................................................................................ 9-5

9-4 SYNCR Field Descriptions........................................................................................... 9-6

9-5 SYNSR Field Descriptions........................................................................................... 9-9

9-6 System Clock Modes ................................................................................................. 9-10

9-7 Clock Out and Clock In Relationships ....................................................................... 9-11

9-8 Charge Pump Current and MFD in Normal Mode Operation .................................... 9-13

9-9 Loss of Clock Summary ............................................................................................. 9-16

9-10 Stop Mode Operation.................................................................................................. 9-17

10-1 Interrupt Priority Within a Level ................................................................................ 10-3

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10-2 Interrupt Controller Base Addresses........................................................................... 10-5

10-3 Interrupt Controller Memory Map.............................................................................. 10-5

10-4 IPRHn Field Descriptions........................................................................................... 10-7

10-5 IPRLn Field Descriptions ........................................................................................... 10-7

10-6 IMRHn Field Descriptions.......................................................................................... 10-8

10-8 INTFRCHn Field Descriptions................................................................................... 10-9

10-7 IMRLn Field Descriptions..........................................................................................10-9

10-9 INTFRCLn Field Descriptions ................................................................................. 10-10

10-10 IRQn Field Descriptions........................................................................................... 10-10

10-11 IACKLPRn Field Descriptions................................................................................. 10-11

10-12 ICRnx Field Descriptions ......................................................................................... 10-12

10-13 Interrupt Source Assignment for INTC0 .................................................................. 10-12

10-14 Interrupt Source Assignment for INTC1 .................................................................. 10-15

10-15 SWIACK and L1IACK-L7IACK Field Descriptions............................................... 10-16

11-1 Edge Port Module Operation in Low-power Modes .................................................. 11-2

11-2 Edge Port Module Memory Map................................................................................11-3

11-3 EPPAR Field Descriptions.......................................................................................... 11-4

11-4 EPDD Field Descriptions............................................................................................ 11-5

11-5 EPIER Field Descriptions........................................................................................... 11-5

11-6 EPDR Field Descriptions............................................................................................ 11-6

11-7 EPPDR Field Descriptions.......................................................................................... 11-6

11-8 EPFR Field Descriptions ............................................................................................ 11-7

12-1 Chip Select Module Signals........................................................................................ 12-1

12-2 Byte Enables/Byte Write Enable Signal Settings....................................................... 12-2

12-3 Accesses by Matches in CSARs and DACRs............................................................. 12-4

12-4 D[19:18] External Boot Chip Select Configuration ................................................... 12-5

12-5 Chip Select Registers..................................................................................................12-5

12-6 CSARn Field Description........................................................................................... 12-7

12-7 CSMRn Field Descriptions......................................................................................... 12-7

12-8 CSCRn Field Descriptions..........................................................................................12-9

13-1 ColdFire Bus Signal Summary.................................................................................. 13-1

13-2 Accesses by Matches in CSCRs and DACRs............................................................. 13-4

13-3 Bus Cycle States ........................................................................................................ 13-5

13-4 Allowable Line Access Patterns ...............................................................................13-11

14-1 MCF5216 Signal Description.................................................................................... 14-1

14-2 MCF5216 Alphabetical Signal Index ......................................................................... 14-6

14-3 MCF5216 Signals and Pin Numbers Sorted by Function........................................... 14-8

14-4 Pin Reset States at Reset (Single-Chip Mode).......................................................... 14-15

14-5 Default Signal Functions After System Reset (External Boot Mode)......................14-15

14-6 Transfer Size Encoding.............................................................................................14-18

14-7 Processor Status Encoding........................................................................................ 14-28

15-1 SDRAM Commands...................................................................................................15-3

15-2 Synchronous DRAM Signal Connections .................................................................. 15-4

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15-3 DRAM Controller Registers....................................................................................... 15-4

15-4 DCR Field Descriptions.............................................................................................. 15-5

15-5 DACRn Field Descriptions......................................................................................... 15-6

15-6 DMRn Field Descriptions........................................................................................... 15-8

15-7 Generic Address Multiplexing Scheme...................................................................... 15-9

15-8 MCF5216 to SDRAM Interface (8-Bit Port, 9-Column Address Lines).................. 15-10

15-9 MCF5216 to SDRAM Interface (8-Bit Port,10-Column Address Lines)................. 15-10

15-10 MCF5216 to SDRAM Interface (8-Bit Port,11-Column Address Lines)................ 15-10

15-11 MCF5216 to SDRAM Interface (8-Bit Port,12-Column Address Lines)................ 15-10

15-12 MCF5216 to SDRAM Interface (8-Bit Port,13-Column Address Lines)................. 15-10

15-13 MCF5216 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)................ 15-11

15-14 MCF5216 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)............... 15-11

15-15 MCF5216 to SDRAM Interface (16-Bit Port, 10-Column Address Lines)............. 15-11

15-16 MCF5216 to SDRAM Interface (16-Bit Port, 11-Column Address Lines).............. 15-11

15-17 MCF5216 to SDRAM Interface (16-Bit Port, 12-Column Address Lines).............. 15-11

15-18 MCF5216 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines) ............ 15-12

15-19 MCF5216 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)................ 15-12

15-20 MCF5216 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)................ 15-12

15-21 MCF5216 to SDRAM Interface (32-Bit Port, 10-Column Address Lines).............. 15-12

15-22 MCF5216 to SDRAM Interface (32-Bit Port, 11-Column Address Lines).............. 15-12

15-23 MCF5216 to SDRAM Interface (32-Bit Port, 12-Column Address Lines).............. 15-13

15-24 SDRAM Hardware Connections .............................................................................15-13

15-25 SDRAM Example Specifications ............................................................................ 15-19

15-26 SDRAM Hardware Connections .............................................................................15-20

15-27 DCR Initialization Values......................................................................................... 15-20

15-28 DACR Initialization Values...................................................................................... 15-21

15-29 DMR0 Initialization Values...................................................................................... 15-22

15-30 Mode Register Initialization .................................................................................... 15-23

15-31 Mode Register Mapping to MCF5216 A[31:0]........................................................ 15-24

16-1 DMAREQC Field Description.................................................................................... 16-3

16-2 Memory Map for DMA Controller Module Registers................................................ 16-5

16-3 DCRn Field Descriptions............................................................................................ 16-8

16-4 DSRn Field Descriptions ......................................................................................... 16-10

17-1 Watchdog Module Operation in Low-power Modes.................................................. 17-1

17-2 Watchdog Timer Module Memory Map.....................................................................17-3

17-3 WCR Field Descriptions............................................................................................. 17-4

17-4 WMR Field Descriptions............................................................................................17-5

17-5 WCNTR Field Descriptions........................................................................................ 17-5

18-1 PIT Module Operation in Low-power Modes ............................................................ 18-2

18-2 Programmable Interrupt Timer Modules Memory Map............................................. 18-3

18-3 PCSR Field Descriptions............................................................................................ 18-4

18-4 PIT Interrupt Requests................................................................................................18-8

19-1 Watchdog Module Operation in Low-power Modes.................................................. 19-3

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19-2 Signal Properties.........................................................................................................19-3

19-3 GPT Modules Memory Map....................................................................................... 19-4

19-4 GPTIOS Field Descriptions........................................................................................19-6

19-5 GPTCFORC Field Descriptions ................................................................................. 19-6

19-6 GPTOC3M Field Descriptions ................................................................................... 19-7

19-7 GPTOC3D Field Descriptions....................................................................................19-7

19-8 GPTCNT Field Descriptions ...................................................................................... 19-8

19-9 GPTSCR1 Field Descriptions..................................................................................... 19-8

19-10 GPTTOV Field Description........................................................................................ 19-9

19-11 GPTCL1 Field Descriptions ..................................................................................... 19-10

19-12 GPTLCTL2 Field Descriptions ................................................................................ 19-10

19-13 GPTIE Field Descriptions......................................................................................... 19-11

19-14 GPTSCR2 Field Descriptions................................................................................... 19-11

19-15 GPTFLG1 Field Descriptions................................................................................... 19-12

19-16 GPTFLG2 Field Descriptions................................................................................... 19-12

19-17 GPTCn Field Descriptions........................................................................................ 19-13

19-18 GPTPACTL Field Descriptions................................................................................ 19-13

19-19 GPTPAFLG Field Descriptions................................................................................ 19-15

19-20 GPTPACR Field Descriptions..................................................................................19-15

19-21 GPTPORT Field Descriptions .................................................................................. 19-16

19-22 GPTDDR Field Descriptions....................................................................................19-16

19-23 GPT Settings and Pin Functions............................................................................... 19-20

19-24 GPT Interrupt Requests ............................................................................................ 19-21

20-1 DMA Timer Module Memory Map........................................................................... 20-3

20-2 DTMRn Field Descriptions ........................................................................................ 20-5

20-3 DTXMRn Field Descriptions...................................................................................... 20-6

20-4 DTERn Field Descriptions.......................................................................................... 20-7

21-1 QSPI Input and Output Signals and Functions........................................................... 21-2

21-2 QSPI_CLK Frequency as Function of System Clock and Baud Rate........................ 21-7

21-3 QSPI Registers............................................................................................................ 21-9

21-4 QMR Field Descriptions........................................................................................... 21-10

21-5 QDLYR Field Descriptions ...................................................................................... 21-12

21-6 QWR Field Descriptions........................................................................................... 21-12

21-7 QIR Field Descriptions............................................................................................. 21-13

21-8 QCR0–QCR15 Field Descriptions............................................................................ 21-15

22-1 UART Module Memory Map.....................................................................................22-3

22-2 UMR1n Field Descriptions......................................................................................... 22-5

22-3 UMR2n Field Descriptions......................................................................................... 22-6

22-4 USRn Field Descriptions............................................................................................ 22-7

22-5 UCSRn Field Descriptions.......................................................................................... 22-9

22-6 UCRn Field Descriptions.......................................................................................... 22-10

22-7 UIPCRn Field Descriptions ...................................................................................... 22-12

22-8 UACRn Field Descriptions....................................................................................... 22-13

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22-9 UISRn/UIMRn Field Descriptions ........................................................................... 22-14

22-10 UIPn Field Descriptions............................................................................................ 22-15

22-11 UOP1/UOP0 Field Descriptions............................................................................... 22-16

22-12 UART Module Signals ............................................................................................. 22-17

22-13 UART Interrupts.......................................................................................................22-29

22-14 UART DMA Requests.............................................................................................. 22-30

22-15 UART Module Initialization Sequence .................................................................... 22-30

23-1 I2C Interface Memory Map....................................................................................... 23-6

23-2 I2ADR Field Descriptions .......................................................................................... 23-6

23-3 I2FDR Field Descriptions........................................................................................... 23-7

23-4 I2CR Field Descriptions ............................................................................................. 23-8

23-5 I2SR Field Descriptions.............................................................................................. 23-9

24-1 FlexCAN Memory Map.............................................................................................. 24-3

24-2 Common Extended/Standard Format Frames............................................................. 24-6

24-3 Message Buffer Codes for Receive Buffers ............................................................... 24-6

24-4 Message Buffer Codes for Transmit Buffers.............................................................. 24-6

24-5 Extended Format Frames............................................................................................24-7

24-6 Standard Format Frames............................................................................................. 24-7

24-7 Examples of System Clock/CAN Bit-Rate/S-Clock................................................. 24-14

24-8 CANMCR Field Descriptions................................................................................... 24-21

24-9 CANCTRL0 Field Descriptions ............................................................................... 24-23

24-10 Transmit Pin Configuration...................................................................................... 24-23

24-11 CANCTRL1 Field Descriptions ............................................................................... 24-24

24-12 PRESDIV Field Descriptions ................................................................................... 24-25

24-13 CANCTRL2 Field Descriptions ............................................................................... 24-25

24-14 TIMER Field Descriptions........................................................................................ 24-26

24-15 Mask examples for Normal/Extended Messages...................................................... 24-26

24-16 RXGMASK, RX14MASK, and RX15MASK Field Descriptions...........................24-28

24-17 ESTAT Field Descriptions........................................................................................ 24-29

24-18 IMASK Field Descriptions....................................................................................... 24-31

24-19 IFLAG Field Descriptions ........................................................................................ 24-31

24-20 RXECTR Field Descriptions .................................................................................... 24-32

24-21 TXECTR Field Descriptions .................................................................................... 24-32

25-1 MCF5216 Ports External Signals ............................................................................... 25-4

25-2 MCF5216 Ports Module Memory Map ...................................................................... 25-6

25-3 PORTn (8-bit, 7-bit, 6-bit, and 4-bit) Field Descriptions........................................... 25-9

25-4 DDRn (8-bit, 6-bit, and 4-bit) Field Descriptions .................................................... 25-10

25-5 PORTnP/SETn (8-bit, 6-bit, and 4-bit) Field Descriptions...................................... 25-12

25-6 CLRn (8-bit,7-bit, 6-bit, and 4-bit) Field Descriptions............................................. 25-13

25-7 PBCDPAR Field Descriptions.................................................................................. 25-14

25-8 Reset Values for PBCDPAR Bits............................................................................. 25-14

25-9 PEPAR Field Descriptions........................................................................................ 25-15

25-10 Reset Values for PEPAR Bits and Fields ................................................................. 25-16

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25-11 PFPAR Field Descriptions........................................................................................ 25-17

25-12 PJPAR Field Descriptions ........................................................................................ 25-18

25-13 PSDPAR Field Descriptions..................................................................................... 25-19

25-14 PASPAR Field Descriptions..................................................................................... 25-20

25-15 PELPAR Field Descriptions..................................................................................... 25-21

25-16 PQSPAR Field Description ...................................................................................... 25-21

25-17 PTCPAR Field Descriptions..................................................................................... 25-22

25-18 PTDPAR Field Descriptions..................................................................................... 25-23

25-19 PUAPAR Field Descriptions .................................................................................... 25-24

26-1 Multiplexed Analog Input Channels........................................................................... 26-7

26-2 QADC Memory Map..................................................................................................26-8

26-3 QADCMCR Field Descriptions.................................................................................. 26-9

26-4 QACR0 Field Descriptions....................................................................................... 26-12

26-5 Prescaler fSYS Divide-by Values............................................................................. 26-13

26-6 QACR1 Field Descriptions....................................................................................... 26-14

26-7 Queue 1 Operating Modes........................................................................................ 26-15

26-8 QACR2 Field Descriptions....................................................................................... 26-18

26-9 Queue 2 Operating Modes........................................................................................ 26-18

26-10 QASR0 Field Descriptions ....................................................................................... 26-23

26-11 CCW Pause Bit Response......................................................................................... 26-24

26-12 Queue Status ............................................................................................................. 26-24

26-13 QASR1 Field Descriptions ....................................................................................... 26-26

26-14 CCW Field Descriptions........................................................................................... 26-27

26-15 Input Sample Times..................................................................................................26-28

26-16 Non-Multiplexed Channel Assignments and Signal Designations........................... 26-28

26-17 Multiplexed Channel Assignments and Signal Designations...................................26-29

26-18 RJURR Field Descriptions........................................................................................ 26-30

26-19 LJSRR Field Descriptions ........................................................................................ 26-30

26-20 LJURR Field Descriptions........................................................................................ 26-31

26-21 Analog Input Channels ............................................................................................. 26-34

26-22 Trigger Events........................................................................................................... 26-40

26-23 Status Bits................................................................................................................. 26-40

26-24 External Circuit Settling Time to 1/2 LSB ............................................................... 26-74

26-25 Error Resulting from Input Leakage (I

26-26 QADC Status Flags and Interrupt Sources ............................................................... 26-76

27-1 Reset Controller Signal Properties............................................................................. 27-2

27-2 Reset Controller Memory Map...................................................................................27-3

27-3 RCR Field Descriptions..............................................................................................27-3

27-4 RSR Field Descriptions .............................................................................................. 27-5

27-5 Reset Source Summary............................................................................................... 27-6

28-1 Debug Module Signals................................................................................................ 28-2

28-2 Processor Status Encoding.......................................................................................... 28-3

28-3 BDM/Breakpoint Registers......................................................................................... 28-7

Title

) ...............................................................26-75

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28-4 Rev. A Shared BDM/Breakpoint Hardware ...............................................................28-7

28-5 AATR Field Descriptions........................................................................................... 28-8

28-6 ABLR Field Description........................................................................................... 28-10

28-7 ABHR Field Description .......................................................................................... 28-10

28-8 CSR Field Descriptions ............................................................................................ 28-11

28-9 DBR Field Descriptions............................................................................................ 28-13

28-10 DBMR Field Descriptions ........................................................................................ 28-13

28-11 Access Size and Operand Data Location..................................................................28-13

28-12 PBR Field Descriptions ............................................................................................ 28-14

28-13 PBMR Field Descriptions......................................................................................... 28-14

28-14 TDR Field Descriptions............................................................................................28-15

28-15 Receive BDM Packet Field Description................................................................... 28-19

28-16 Transmit BDM Packet Field Description ................................................................. 28-19

28-17 BDM Command Summary....................................................................................... 28-20

28-18 BDM Field Descriptions........................................................................................... 28-21

28-19 Control Register Map................................................................................................ 28-32

28-20 Definition of DRc Encoding—Read......................................................................... 28-36

28-21 DDATA[3:0]/CSR[BSTAT] Breakpoint Response.................................................. 28-37

28-22 PST/DDATA Specification for User-Mode Instructions.......................................... 28-40

28-23 PST/DDATA Specification for MAC Instructions................................................... 28-43

28-24 PST/DDATA Specification for Supervisor-Mode Instructions................................ 28-44

29-1 Signal Properties........................................................................................................29-3

29-2 Write-Once Bits Read/Write Accessibility.................................................................29-4

29-3 Chip Configuration Module Memory Map................................................................. 29-4

29-4 CCR Field Descriptions..............................................................................................29-5

29-5 RCON Field Descriptions........................................................................................... 29-6

29-6 RCSC Chip Select Configuration............................................................................... 29-7

29-7 BOOTPS Port Size Configuration.............................................................................. 29-7

29-8 CIR Field Description................................................................................................. 29-8

29-9 Reset Configuration Pin States During Reset.............................................................29-9

29-10 Configuration During Reset....................................................................................... 29-9

29-11 Chip Configuration Mode Selection.........................................................................29-11

29-12 Output Pad Driver Strength Selection ...................................................................... 29-11

29-13 Clock Mode Selection............................................................................................... 29-12

30-1 Signal Properties.........................................................................................................30-3

30-2 Pin Function Selected ................................................................................................. 30-3

30-3 Signal State to the Disable Module............................................................................. 30-4

30-4 IDCODE Register Field Descriptions......................................................................... 30-6

30-5 JTAG Instructions....................................................................................................... 30-8

31-1 MCF5216 Signal Description by Pin Number............................................................ 31-3

31-2 Orderable Part Numbers ............................................................................................. 31-7

32-1 Absolute Maximum Ratings, ..................................................................................... 32-1

32-2 Thermal Characteristics.............................................................................................. 32-3

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32-3 DC Electrical Specifications....................................................................................... 32-4

32-4 PLL Electrical Specifications ..................................................................................... 32-5

32-5 QADC Absolute Maximum Ratings........................................................................... 32-7

32-6 QADC Electrical Specifications (Operating) ............................................................ 32-7

32-7 QADC Conversion Specifications (Operating) .......................................................... 32-8

32-8 SGFM Flash Program and Erase Characteristics........................................................ 32-9

32-9 SGFM Flash Module Life Characteristics..................................................................32-9

32-10 Processor Bus Input Timing Specifications................................................................ 32-9

32-11 External Bus Output Timing Specifications............................................................. 32-11

32-12 SDRAM Timing ....................................................................................................... 32-16

32-13 GPIO Timing, ...........................................................................................................32-17

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32-13 (V

32-14 Reset and Configuration Override Timing ............................................................... 32-18

32-15 I2C Input Timing Specifications between SCL and SDA......................................... 32-19

32-16 I2C Output Timing Specifications between SCL and SDA..................................... 32-20

32-17 Timer Module AC Timing Specifications ................................................................ 32-21

32-18 QSPI Modules AC Timing Specifications................................................................ 32-21

32-19 JTAG and Boundary Scan Timing............................................................................ 32-22

32-20 Debug AC Timing Specification .............................................................................. 32-24

A-1 CPU Space Register Memory Map.............................................................................. A-1

A-2 Module Memory Map Overview................................................................................. A-2

A-3 Register Memory Map................................................................................................. A-3

= 2.7 to 3.6 V, VSS = 0 V, V

Title

= 5 V) ........................................................ 32-17

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xlii MCF5216 User’s Manual MOTOROLA

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About This Book

The primary objective of this user ’s manual is to define the functionality of the MCF5216 processor for use by software and hardware developers.

The information in this book, except for changes to the Flash functionality, also applies to the MCF5214.

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The information in this book is subject to change without notice, as described in the disclaimers on the title page. As with any technical documentation, it is the reader’s responsibility to be sure he is using the most recent version of the documentation.

To locate any published errata or updates for this document, refer to the world-wide web at http://www.motorola.com/coldfire.

Audience

This manual is intended for system software and hardware developers and applications programmers who want to develop products with the MCF5216. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the ColdFire

architecture.

Organization

Following is a summary and brief description of the major sections of this manual:

• Chapter 1, “Overview,” includes general descriptions of the modules and features incorporated in the MCF5216, focussing in particular on new features.

• Chapter 2, “ColdFire Core,” provides an overview of the microprocessor core of the MCF5216. The chapter describes the organization of the Version 2 (V2) ColdFire processor core and an overview of the program-visible registers (the programming model) as they are implemented on the MCF5216.

• Chapter 3, “Enhanced Multiply-Accumulate Unit (EMAC),” describes the MCF5216 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The EMAC is integrated into the operand execution pipeline (OEP).

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• Chapter 4, “Cache,” describes the MCF5216 cache implementation, including organization, configuration, and coherency. It describes cache operations and how the cache interacts with other memory structures.

• Chapter 5, “Static RAM (SRAM),” describes the MCF5216 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization. It also provides information and examples of how to minimize power consumption when using the SRAM.

• Chapter 6, “ColdFire Flash Module (CFM)” describe the functionality of the MCF5216 Flash memory.

• Chapter 7, “Power Management,” describes the low power operation of the MCF5216 and peripheral behavior in low power modes.

• Chapter 8, “System Control Module (SCM),” describes the functionality of the SCM, which provides the programming model for the System Access Control Unit

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(SACU), the system bus arbiter, a 32-bit Core Watchdog Timer (CWT), and the system control registers and logic.

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• Chapter 9, “Clock Module,” describes the MCF5216’s different clocking methods. It also describes clock module operation in low power modes.

• Chapter 10, “Interrupt Controller Modules,” describes operation of the interrupt controller portion of the SCM. Includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme.

• Chapter 11, “Edge Port Module (EPOR T),” describes EPORT module functionality , including operation in low power mode.

• Chapter 12, “Chip Select Module,” describes the MCF5216 chip-select implementation, including the operation and programming model, which includes the chip-select address, mask, and control registers.

• Chapter 13, “External Interface Module (EIM),” describes data-transfer operations, error conditions, bus arbitration, and reset operations.

• Chapter 14, “Signal Descriptions,” describes MCF5216 signals. It includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state at reset, and identifies whether a pull-up resistor should be used.

• Chapter 15, “Synchronous DRAM Controller Module,” describes the configuration and operation of the SDRAM controller. It begins with a general description and brief glossary , and includes a description of signals involved in DRAM operations. The remainder of the chapter describes the programming model and signal timing, as well as the command set required for synchronous operations.

• Chapter 16, “DMA Controller Module,” describes the MCF5216 Direct Memory Access (DMA) controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail.

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Organization

• Chapter 17, “Watchdog Timer Module,” describes Watchdog timer functionality, including operation in low power mode.

• Chapter 18, “Programmable Interrupt Timer Modules (PIT0–PIT3),” describes the functionality of the four PIT timers, including operation in low power mode.

• Chapter 19, “General Purpose Timer Modules (GPTA and GPTB),” describes the functionality of the two general purpose timers, including operation in low power mode.

• Chapter 20, “DMA Timers (DTIM0–DTIM3),” describes the configuration and operation of the four DMA timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers provide input capture and reference compare capabilities with optional signaling of events using interrupts or triggers. This chapter also provides programming examples.

• Chapter 21, “Queued Serial Peripheral Interface (QSPI) Module,” provides a

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feature-set overview and a description of operation, including details of the QSPI’s internal storage organization. The chapter concludes with the programming model and a timing diagram.

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• Chapter 22, “UART Modules,” describes the use of the universal asynchronous receiver/transmitters (UARTs) implemented on the MCF5216 and includes programming examples.

• Chapter 23, “I protocol, clock synchronization, and I

C Interface,” describes the MCF5216 I2C module, including I2C

C programming model registers. It also

provides extensive programming examples.

• Chapter 24, “FlexCAN,” describes the MCF5216 implementation of the controller area network (CAN) protocol. This chapter describes FlexCAN module operation and provides a programming model.

• Chapter 25, “General Purpose I/O Module,” describes the operation and programming model of the general purpose I/O (GPIO) ports on the MCF5216.

• Chapter 29, “Chip Configuration Module (CCM),” describes CCM functionality, detailing the two modes of chip operation: master mode and single-chip mode. This chapter provides a description of signals used by the CCM and a programming model.

• Chapter 26, “Queued Analog-to-Digital Converter (QADC),” describes the use of the QADC module implemented on the MCF5216.

• Chapter 27, “Reset Controller Module,” describes the operation of the reset controller module, detailing the different types of reset that can occur.

• Chapter 28, “Debug Support” describes the Revision A enhanced hardware debug support in the MCF5216.

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Conventions

— ColdFire MCF5206E User’s Manual (MCF5206EUM/AD) — ColdFire MCF5307 User’s Manual (MCF5307UM/AD) — ColdFire MCF5407 User’s Manual (MCF5407UM/AD) — ColdFire MCF5282 User’s Manual (MCF5282UM/AD)

Additional literature on ColdFire implementations is being released as new processors become available. For a current list of ColdFire docum entation, refer to the World Wide Web at http://www.motorola.com/ColdFire/.

Conventions

This document uses the following notational conventions: MNEMONICS In text, instruction mnemonics are shown in uppercase.

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mnemonics In code and tables, instruction mnemonics are shown in lowercase.

italics Italics indicate variable command parameters.

Book titles in text are set in italics.

0x0 Prefix to denote hexadecimal number 0b0 Prefix to denote binary number REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits,

fields, or ranges appear in brackets. For example, RAMBAR[BA]

identifies the base address field in the RAM base address register. nibble A 4-bit data unit byte An 8-bit data unit word A 16-bit data unit

longword A 32-bit data unit x In some contexts, such as signal encodings, x indicates a don’t care.

n Used to express an undefined numerical value ~ NOT logical operator

& AND logical operator | OR logical operator

Acronyms and Abbreviations

Table i lists acronyms and abbreviations used in this document.

The only exceptions to this appear in the discussion of serial communication modules that support variable-le ngth da ta t ran smi ssi o n uni ts . T o simp li f y the di scussion these units are referred to as words regardless of length.

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Acronyms and Abbreviations

Table i. Acronyms and Abbreviated Terms

Term Meaning

ADC Analog-to-digital conve rsion

ALU Arithmetic logic unit BDM Background debug mode BIST Built-in self test

BSDL Boundary-scan description language

CODEC Code/decode

DAC Digital-to-analog conversion DMA Direct memory access DSP Digital signal processing

EA Effective address

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FIFO First-in, first-out

GPIO General-purpose I/O

C Inter-integrated circuit

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IEEE Institute for Electrical and Electronics Engineers

IFP Instruction fetch pipeline IPL Interrupt priority level

JEDEC Joint Electron Device Engineering Council

JTAG Joint Test Action Group

LIFO Last-in, first-out LRU Least recently used

LSB Least-significant byte

lsb Least-significant bit

MAC Multiply accumulate unit, also Media access controller

MBAR Memory base address register

MSB Most-significant byte

msb Most-significant bit

Mux Multiplex NOP No operation OEP Operand executio n pipeline

PC Program counter

PCLK Processor clock

PLIC Physical layer interface controller

PLL Phase-locked loop

POR Power-on reset

PQFP Plastic quad flat pack

PWM Pulse width modulation

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Terminology Conventions

Table i. Acronyms and Abbreviated Terms (Continued)

Term Meaning

QSPI Queued serial peripheral interface RISC Reduced instruction set computing

Rx Receive

SIM System integration module

SOF Start of frame

TAP Test access port

TTL Transistor tran sis to r logic

Tx Transmit

UART Universal asynchronous/synchronous receiver transmitter

USB Universal serial bus

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Terminology Conventions

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Table ii shows terminology conventions used throughout this document.

Table ii. Notational Conventions

Instruction Operand Syntax

Opcode Wildcard

cc Logical condition (example: NE for not equal)

An Any address register n (example: A3 is address register 3)

Ay,Ax Source and destination address registers, respectively

Dn Any data register n (example: D5 is data register 5)

Dy,Dx Source and destination data registers, respectively

Rc Any control register (example VBR is the vector base register)

Rm MAC registers (ACC, MAC, MASK)

Rn Any address or data register Rw Destination register w (used for MAC instructions only)

Ry,Rx Any source and destination registers, respectively

Xi Index register i (can be an address or data register: Ai, Di)

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Table ii. Notational Conventions (Continued)

Instruction Operand Syntax

ACC MAC accumulator register CCR Condition code register (lower byte of SR)

MACSR MAC status register

MASK MAC mask register

PC Program counter SR Status register

Port Name

DDATA Debug data port

PST Processor status port

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#<data> Immediate data following the 16-bit operation word of the instruction

Miscellaneous Oper and s

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<ea> Effective add res s

<ea>y,<ea>x Source and destination effective addresses, respectively

<label> Assembly language program label

<list> List of registers for MOVEM instruction (example: D3–D0) <shift> Shift operation: shift left (<<), shift right (>>) <size> Operand data size: byte (B), word (W), longword (L)

bc Both instruction and data caches dc Data cache

ic Instruction cache

# <vector> Identifies the 4-bit vector number for trap instructions

<> identifies an indirect data address referencing memory

<xxx> identifies an absolute address referencing memory

dn Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)

SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)

Operations

+ Arithmetic addition or postincrement indicator – Arithmetic s ubtraction or predecrement indicator x Arithmetic multiplicat ion

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Terminology Conventions

Table ii. Notational Conventions (Continued)

Instruction Operand Syntax

/ Arithmetic division ~ Invert; operand is logically complemented & Logical AND

| Logical OR ^ Logical exclusive OR

<< Shift left (example: D0 << 3 is shift D0 left 3 bits) >> Shift right (example: D0 >> 3 is shift D0 right 3 bits)

→ Source operand is moved to destination operand

←→ Two operands are exchanged

sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion

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If <condition>

then

else

{} Optional operation () Identifies an indirect address

Address Calculated effective address (pointer)

Bit Bit selection (example: Bit 3 of D0)

lsb Least significant bit (example: lsb of D0)

LSB Least significant byte

LSW Le ast significant word

msb Most significant bit

MSB Most significant byte

MSW Most significant word

C Carry

Test the co ndition. If true, the ope rations aft er ‘then’ are performed. If the condi tion is false and the optional ‘else’ clause is present, the operations after ‘else’ are performed. If the condition is false and else is omitted, the instruction perfo r ms no operation. Refer to the Bcc in struction descript ion as an exampl e.

Subfields and Qualifiers

Displacement value, n-bits wide (example: d16 is a 16-bit displacement)

Condition Code Register Bit Names

N Negative

VOverflow X Extend Z Zero

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Revision History

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Revision History

Table iii provides a revision history for this document.

Table iii. Revision History

Revision

Number

0 3/2004 Initial release.

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Date of

Release

Substant ive Changes Section /Page

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Chapter 1 Overview

This chapter provides an overview of the MCF5216 microprocessor features, including the major functional components.

1.1 MCF5216 Key Features

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A block diagram of the MCF5216 is shown in Figure 1-1. The main features are as follows:

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• Static Version 2 ColdFire variable-length RISC processor — Static operation — On-chip 32-bit address and data path — Processor core and bus frequency up to 80 MHz — Sixteen general-purpose 32-bit data and address registers — ColdFire ISA_A with extensions to support the user stack pointer register, and

four new instructions for improved bit processing

— Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to

support 32-bit signal processing algorithms

— Illegal instruction decode that allows for 68K emulation support

• System debug support — Real-time trace for determining dynamic execution path — Background debug mode (BDM) for in-circuit debugging — Real time debug support, with one user-visible hardware breakpoint register (PC

and address with optional data) that can be configured into a 1- or 2-level trigger

• On-chip memories — 2-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache — 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and

non-core bus masters (e.g., DMA) with standby power supply support

— 512 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses

(256 Kbytes on the MCF5214) – This product incorporates SuperFlash® technology licensed from SST.

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• Power management — Fully-static operation with processor sleep and whole chip stop modes — Very rapid response to interrupts from the low-power sleep mode (wake-up

feature)

— Clock enable/disable for each peripheral when not used

• FlexCAN 2.0B Module — Includes all existing features of the Motorola TouCAN module — Full implementation of the CAN protocol specification version 2.0B

– Standard data and remote frames (up to 109 bits long) – Extended data and remote frames (up to 127 bits long) – 0–8 bytes data length

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– Programmable bit rate up to 1 Mbit/sec

— Up to 16 message buffers (MBs)

– Configurable as receive (Rx) or transmit (Tx)

– Support standard and extended messages — Unused message buffer (MB) space can be used as general-purpose RAM space — Listen-only mode capability — Content-related addressing — No read/write semaphores — Three programmable mask registers

– Global (for MBs 0-13)

– Special for MB14

– Special for MB15 — Programmable transmit-first scheme: lowest ID or lowest buffer number — “Time stamp” based on 16-bit free-running timer — Global network time, synchronized by a specific message — Programmable I/O modes — Maskable interrupts

• Three universal asynchronous/synchronous receiver transmitters (UARTs) — 16-bit divider for clock generation — Interrupt control logic — Maskable interrupts — DMA support — Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity — Up to 2 stop bits in 1/16 increments

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— Error-detection capabilities

MCF5216 Key Features

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— Modem support includes request-to-send (URTS

) and clear-to-send (UCTS)

lines for two UARTs

— Transmit and receive FIFO buffers

C module

•I — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and

keypads

— Fully compatible with industry-standard I

C bus — Master or slave modes support multiple masters — Automatic interrupt generation with programmable level

• Queued serial peripheral interface (QSPI) — Full-duplex, three-wire synchronous transfers — Up to four chip selects available — Master mode operation only — Programmable master bit rates — Up to 16 pre-programmed transfers

• Queued analog-to-digital converter (QADC) — 8 direct, or up to 18 multiplexed, analog input channels — 10-bit resolution +/- 2 counts accuracy — Minimum 7 µS conversion time — Internal sample and hold — Programmable input sample time for various source impedances — Two conversion command queues with a total of 64 entries — Sub-queues possible using pause mechanism — Queue complete and pause software interrupts available on both queues — Queue pointers indicate current location for each queue

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— Automated queue modes initiated by:

– External edge trigger and gated trigger – Periodic/interval timer, within QADC module [Queue 1 and 2]

– Software command — Single-scan or continuous-scan of queues — Output data readable in three formats:

– Right-justified unsigned

– Left-justified signed

– Left-justified unsigned — Unused analog channels can be used as digital I/O — Low pin-count configuration implemented

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• Four 32-bit DMA timers — 15-ns resolution at 66 MHz — Programmable sources for clock input, including an external clock option — Programmable prescaler — Input-capture capability with programmable trigger edge on input pin — Output-compare with programmable mode for the output pin — Free run and restart modes — Maskable interrupts on input capture or reference-compare — DMA trigger capability on input capture or reference-compare

• Two 4-channel general purpose timers — Four 16-bit input capture/output compare channels per timer — 16-bit architecture — Programmable prescaler — Pulse widths variable from microseconds to seconds — Single 16-bit pulse accumulator — Toggle-on-overflow feature for pulse-width modulator (PWM) generation — One dual-mode pulse accumulation channel per timer

• Four periodic interrupt timers (PITs) — 16-bit counter — Selectable as free running or count down

• Software watchdog timer — 16-bit counter — Low-power mode support

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MCF5216 Key Features

• Phase locked loop (PLL) — Crystal or external oscillator reference — 2- to 10-MHz reference frequency for normal PLL mode — 33- to MHz oscillator reference frequency for 1:1 mode — Low-power modes supported — Separate clock output pin

• Two interrupt controllers — Support for up to 63 interrupt sources per interrupt controller (a total of 126),

organized as follows: – 56 fully-programmable interrupt sources – 7 fixed-level interrupt sources

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— Seven external interrupt signals — Unique vector number for each interrupt source — Ability to mask any individual interrupt source or all interrupt sources (global

mask-all) — Support for hardware and software interrupt acknowledge (IACK) cycles — Combinatorial path to provide wake-up from low-power modes

• DMA controller — Four fully programmable channels — Dual-address transfer support with 8-, 16- and 32-bit data capability along with

support for 16-byte (4 x 32-bit) burst transfers — Source/destination address pointers that can increment or remain constant — 24-bit byte transfer counter per channel — Auto-alignment transfers supported for efficient block movement — Bursting and cycle steal support — Software-programmable connections between the 11 DMA requesters in the

UARTs (3), 32-bit timers (4) plus external logic (4) and the four DMA channels

• External bus interface — Glueless connections to external memory devices (e.g., SRAM, Flash, ROM,

etc.) — SDRAM controller supports 8-, 16-, and 32-bit wide memory devices — Glueless interface to SRAM devices with or without byte strobe inputs — Programmable wait state generator — 32-bit bidirectional data bus — 24-bit address bus

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MCF5216 Key Features

— Up to seven chip selects available — Byte/write enables (byte strobes) — Ability to boot from internal Flash memory or external memories that are 8, 16,

or 32 bits wide

• Reset — Separate reset in and reset out signals — Seven sources of reset:

– Power-on reset (POR) – External – Software – Watchdog

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– Loss of clock – Loss of lock – Low-voltage detection (LVD)

— Status flag indication of source of last reset

• Chip integration module (CIM) — System configuration during reset — Support for single chip, master, and test modes — Selects one of four clock modes — Sets boot device and its data port width — Configures output pad drive strength — Unique part identification number and part revision number

• General purpose I/O interface — Up to 134 bits of general purpose I/O — Coherent 32-bit control — Bit manipulation supported via set/clear functions — Unused peripheral pins may be used as extra GPIO

• JTAG support for system-level board testing

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Chip

Configuration

Reset

Controller

External Interface

Module

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Power

Management

Ports

Module

JTAG

Port

Debug Module

ColdFire V2 Core

Flash

Module

MCF5216 Key Features

64K

SRAM

Test

Controller

2-Kbyte

EMAC

Module

I2C

Internal Bus

Arbiter

Watchdog

Timer

DMA

Controller

DIV

D-Cache/I-Cache

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Chip

Selects

Edgeport

DRAM

Controller

Clock Module

(PLL)

Interrupt

Controller 0

Interrupt

Controller 1

UART0

Serial

I/O

UART1

Serial

I/O

UART2

Serial

I/O

System

Control

Module (SCM)

DMA Timer

Modules

(DTIM0–

DTIM3)

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General Purpose

Timer A

General Purpose Timer B

QSPI FlexCANQADC

PIT Timers (PIT0–

PIT3)

Figure 1-1. MCF5216 Block Diagram

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1.1.1 Version 2 ColdFire Core

The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaitin g execut ion in the operand execution pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed.

The V2 core implements the ColdFire instruction set architecture revision A with added support for a separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the MCF5216 core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing capabilities. The EMAC implements a 4-stage execution pipeline, optimized for 32 x 32 bit operations, with support for four 48-bit

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accumulators. Supported operands include 16- and 32-bit signed and unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The EMAC provides superb support for execution of DSP operations within the context of a single processor at a minimal hardware cost.

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1.1.1.1 Cache

The 2-Kbyte cache can be configured into one of three possible organizations: a 2-Kbyte instruction cache, a 2-Kbyte data cache or a split 1-Kbyte instruction/1-Kbyte data cache. The configuration is software-programmable by control bits w ithin the privileged cache configuration register (CACR). In all configurations, the cache is a direct-mapped single-cycle memory, organized as 128 lines, each containing 16 bytes of data. The memories consist of a 128-entry tag array (containing addresses and control bits) and a 2-Kbyte data array, organized as 512 x 32 bits. The tag and data arrays are accessed in parallel using the following address bits:

Table 1-1. Cache Configuration

Configuration Tag Address Data Array Address

2 Kbyte I-Cache [10:4] [10:2] 2 Kbyte D-Cache [10:4] [10:2] Split I-/D-Cache 0

Instruction Fetches Operand Accesses

If the desired address is mapped into the cache memory, the output of the data array is driven onto the ColdFire core’s local data bus, completing the access in a single cycle. If the data is not mapped into the tag memory, a cache miss occurs and the processor core initiates a 16-byte line-sized fetch. The cache module includes a 16-byte line fill buffer used

0, [9:4] 1, [9:4]

0, [9:2] 1, [9:2]

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MCF5216 Key Features

as temporary storage during miss processing. For all data cache configurations, the memory operates in write-through mode and all operand writes generate an external bus cycle.

1.1.1.2 SRAM

The SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 64-Kbyte boundary within the 4-Gbyte address space. The memory is ideal for storing critical code or data structures, or for use as the system stack. Because the SRAM mo dule is physically connected to the processor’s high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module.

The SRAM module is also accessible by non-core bus masters, for example the DMA. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions

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of the SRAM to maximize system performance.

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1.1.1.3 Flash

This product incorporates SuperFlash® technology licensed from SST . The ColdFire Flash Module (CFM) is a non-volatile memory (NVM) module for integration with the processor core. The CFM is constructed with eight banks of 32K x 16-bit Flash arrays to generate 512 Kbytes of 32-bit Flash memory

NOTE

The CFM on the MCF5214 is constructed with four bank s of 32K x 16-bit Flash arrays to generate 256 Kbytes of 32-bit Flash memory.

These arrays serve as electrically erasable and program mable, non-volatile program and data memory. The Flash memory is ideal for program and data storage for single-chip applications allowing for field reprogramming without requiring an external programming voltage source. The CFM interfaces to the V2 ColdFire core through an optimized read-only memory controller which supports interleaved accesses from the 2-cycle F lash arrays. A “backdoor” mapping of the Flash memory is used for all program, erase, and verify operations. It also provides a read datapath for non-core masters (for example, DMA).

1.1.1.4 Debug Module

The ColdFire processor core debug interface is provided to support system debuggi ng in conjunction with low-cost debug and emulator development tools. Through a standard debug interface, users can access real-time trace and debug information. This allows the processor and system to be debugged at full speed without the need for costly in-circuit

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emulators. The debug interface is a superset of the BDM interface provided on Motorola’s 683xx family of parts.

The on-chip breakpoint resources include a total of 6 programmable registers—a set of address registers (with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask register), and one 32-bit PC register plus a 32-bit PC mask register . These registers can be accessed through the dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.

T o support program trace, the Version 2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the CLKOUT output provide execution status, captured operand data, and branch target addresses defining the dynamic

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execution path of the processor at the CPU’s clock rate.

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1.1.2 System Control Module

This section details the functionality of the System Control Module (SCM) which provides the programming model for the System Access Control Unit (SACU), the system bus arbiter, a 32-bit Core Watchdog Timer (CWT), and the system control regis ters and logic. Specifically, the system control includes the internal peripheral system base address register (IPSBAR), the processor’s dual-port RAM base address register (RAMBAR), and system control registers that include low-power and core watchdog timer control.

1.1.3 External Interface Module (EIM)

The external interface module handles the transfer of information between the internal core and memory, peripherals, or other processing elements in the external address space.

Programmable chip-select outputs provide signals to enable external memory and peripheral circuits, providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing.

Base memory address and block size are programmable, with some restrictions. For example, the starting address must be on a boundary that is a m ultiple of the block size. Each chip select can be configured to provide read and write enable signals suitable for use with most popular static RAMs and peripherals. Data bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and further decoding is available for protection from user mode access or read-only access.

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MCF5216 Key Features

1.1.4 Chip Select

Programmable chip select outputs provide a glueless connection to external memory and peripheral circuits, providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing.

1.1.5 Power Management

The MCF5216 incorporates several low-power modes of operation which are entered under program control and exited by several external trigger events. An integrated Power-On Reset (POR) circuit monitors the input supply and forces an MCU reset as the supply voltage rises. The Low Voltage Dete ct (LVD) sectio n monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the LVD trip point. The RAM standby switch provides power to RAM when the supply voltage is higher th an the

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standby voltage. If the supply voltage to chip falls below the standby battery voltage, the RAM is switched over to the standby supply.

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1.1.6 General Input/Output Ports

All of the pins associated with the external bus interface may be used fo r several different functions. Their primary function is to provide an external memory interface to access off-chip resources. When not used for this function, all of the pins may be used as general-purpose digital I/O pins. In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported.

The digital I/O pins on the MCF5 216 are grouped int o 8-bit ports. Som e ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pins.

1.1.7 Interrupt Controllers (INTC0/INTC1)

There are two interrupt controllers on the MCF5216, each of which can support up to 63 interrupt sources for a total of 126. Each interrupt controller is organized as 7 levels with 9 interrupt sources per level. Each interrupt source has a unique interrupt vector, and 56 of the 63 sources of a given controller provide a programmable level [1-7] and priority within the level.

1.1.8 SDRAM Controller

The SDRAM controller provides all required signals for glueless interfacing to a variety of JEDEC-compliant SDRAM devices. SRAS/SCAS address multiplexing is software configurable for different page sizes. To maintain refresh capability without conflicting with concurrent accesses on the address and data buses, SRAS SDRAM_CS

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1.1.9 Test Access Port

The MCF5216 supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit boundary-scan register , and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic.

The MCF5216 implementation supports the following:

• Perform boundary-scan operations to test circuit board electrical continuity

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• Sample

MCF5216 system pins during operation and transparently shift out the result

in the boundary scan register

• Bypass the MCF5216 for a given circuit board test by effectively reducing the boundary-scan register to a single bit

• Disable the output drive to pins during circuit-board testing

• Drive output pins to stable levels

1.1.10 UART Modules

The MCF5216 contains three full-duplex UARTs that function independently. The three UARTs can be clocked by the system clock, eliminating the need for an external crystal.

Each UART has the following features:

• Each can be clocked by the system clock, eliminating a need for an external UART clock

• Full-duplex asynchronous/synchronous receiver/transmitter channel

• Quadruple-buffered receiver

• Double-buffered transmitter

• Independently programmable receiver and transmitter clock sources

• Programmable data format: — 5–8 data bits plus parity — Odd, even, no parity, or force parity — One, one-and-a-half, or two stop bits

• Each channel programmable to normal (full-duplex), automatic echo, local loop-back, or remote loop-back mode

• Automatic wake-up mode for multidrop applications

• Four maskable interrupt conditions

• All three UARTs have DMA request capability

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MCF5216 Key Features

• Parity, framing, and overrun error detection

• False-start bit detection

• Line-break detection and generation

• Detection of breaks originating in the middle of a character

• Start/end break interrupt/status

1.1.11 DMA Timers (DTIM0-DTIM3)

There are four independent, DMA-transfer-generating 32-bit timers (DTIM0, DTIM1, DTIM2, DTIM3) on the MCF5216. Each timer module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clock source using one of the DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The selected clock is further

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divided by a user-programmable 8-bit prescaler which clocks the actual timer counter register (TCRn). Each of these timers can be configured for input capture or reference compare mode. By configuring the internal registers, each timer may be configured to assert an external signal, generate an interrupt on a particular event, or cause a DMA transfer.

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1.1.12 General-Purpose Timers (GPTA/GPTB)

The two general-purpose timers (GPTA and GPTB) are 4-channel timer modules. Each timer consists of a 16-bit programmable counter driven by a 7-stage programmable prescaler. Each of the four channels for each timer can be configured for input capture or output compare. Additionally, one of the channels, channel 3, can be configured as a pulse accumulator.

A timer overflow function allows soft ware to extend the timing capability of t he system beyond the 16-bit range of the counter. The input capture and output compare functions allow simultaneous input waveform measurements and output waveform generation. The input capture function can capture the time of a selected transition edge. The output compare function can generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.

1.1.13 Periodic Interrupt Timers (PIT0-PIT3)

The four periodic interrupt timers (PIT0, PIT1, PIT2 , PIT3) are 16-bi t timers that pro vide precise interrupts at regular intervals with minimal processor interventio n. Each tim er can either count down from the value written in its PIT modulus register, or it can be a free-running down-counter.

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1.1.14 Software Watchdog Timer

The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.

1.1.15 Phase Locked Loop (PLL)

The clock module contains a crystal oscillator (OSC), phase-locked loop (PLL), reduced frequency divider (RFD), status/control registers, and control logic. To improve noise immunity , the PLL and OSC have their own power supply inputs, VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS.

1.1.16 DMA Controller

The Direct Memory Access (DMA) controller module provides an efficient way to move blocks of data with minimal processor interaction. The DMA module provides four channels (DMA0–DMA3) that allow byte, word, longword or 16-byte burst line transfers. These transfers are triggered by software, explicitly setting a DCRn[START] bit or the occurrence of a hardware event from one of the on-chip peripheral devices, such as a capture event or an output reference event in a DMA timer (DTIMn) for each channel. The DMA controller supports dual-address mode to on-chip devices.

1.1.17 Reset

The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and keep track of what caused the last reset. The power management registers for the internal low-voltage detect (LVD) circuit are implemented in the reset module. There are seven sources of reset:

• External

• Power-on reset (POR)

• Watchdog timer

• Phase-locked loop (PLL) loss of lock

• PLL loss of clock

• Software

• Low-voltage detection (LVD) reset

External reset on the RSTO

pin is software-assertable independent of chip reset state. There are also software-readable status flags indicating the cause of the last reset, and LVD control and status bits for setup and use of LVD reset or interrupt.

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MCF5216-Specific Features

1.2 MCF5216-Specific Features

1.2.1 FlexCAN

The FlexCAN module is a communication controller implementing the CAN protocol. The CAN protocol can be used as an industrial control serial data bus, meeting the specific requirements of real-time processing, reliable operation in a harsh EMI environment, cost-effectiveness, and required bandwidth. FlexCAN contains 16 message buffers.

1.2.2 I2C Bus

The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many

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1.2.3 Queued Serial Peripheral Interface (QSPI)

The queued serial peripheral interface module provides a synchronous serial peripheral interface with queued transfer capability. It allows up to 16 transfers to be queued at once, eliminating CPU intervention between transfers.

1.2.4 Queued Analog-to-Digital Converter (QADC)

The QADC is a 10-bit, unipolar, successive approximation converter. A maximum of 8 analog input channels can be supported using internal multiplexing. A maximum of 18 input channels can be supported in the internal/external multiplexed mode.

The QADC consists of an analog front-end and a digital control subsystem. The analog section includes input pins, an analog multiplexer, and sample and hold analog circuits. The analog conversion is performed by the digital-to-analog converter (DAC) resistor-capacitor array and a high-gain comparator.

The digital control section contains queue control logic to sequence the conversion process and interrupt generation logic. Also included are the periodic/interval timer, control and status registers, the 64-entry conversion command word (CCW) table, and the 64-entry result table.

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MCF5216-Specific Features

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I F P

]

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Chapter 2 ColdFire Core

This section describes the organization of the Version 2 (V2) ColdFire® processor core and an overview of the program-visible registers. For detailed information on instructions, see the ColdFire Family Programmer’s Reference Manual.

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2.1 Processor Pipelines

Figure 2-1 is a block diagram showing the processor pipelines of a V2 ColdFire core.

Instruction

IAG

nstruction

etch ipeline

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perand xecution ipeline

DSOC

AGEX

Address

Generation

Instruction

Fetch Cycle

FIFO

Instruction Buffer

Decode & Select,

Operand Fetch

Address

Generation,

Execute

Address [31:0]

read_data[31:0]

write_data[31:0

Figure 2-1. ColdFire Processor Core Pipelines

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Processor Register Description

The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer.

The Instruction Fetch Pipeline (IFP) is a two-stage p ipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage Operand Execution Pipeline (OEP), which decodes the instruction, fetches the required operands and then executes the required function. Since the IFP and OEP pipelines are decoupled by an instruction buffer which serves as a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for instructions.

The Instruction Fetch Pipeline consists of two stages with an instruction buffer stage:

• Instruction Address Generation (IAG Cycle)

• Instruction Fetch Cycle (IC Cycle)

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• Instruction Buffer (IB Cycle)

When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into the Operand Execution Pipeline. If the buffer is not empty, the IFP stores the contents of the fetch cycle in the FIFO queue until it is required by the OEP. In the Version 2 implementation, the instruction buffer contains three 32-bit longwords of storage.

The Operand Execution Pipeline is implemented in a two-stage pipeline featuring a traditional RISC datapath with a dual-read-ported register file (RGF) feeding an arithmetic/logic unit. In this design, the pipeline stages have multiple functions:

• Decode & Select/Operand Cycle (DSOC Cycle)

• Address Generation/Execute Cycle (AGEX Cycle)

2.2 Processor Register Description

The following paragraphs describe the processor registers in the user and supervisor programming models. The appropriate programming model is selected based on the privilege level (user mode or supervis or mode) o f the proces sor as defin ed by the S bit of the status register (SR).

2.2.1 User Programming Model

Figure 2-2 illustrates the user programming model . The model is the same as th e M6 8000 family microprocessors, consisting of the following registers:

• 16 general-purpose 32-bit registers (D0–D7, A0–A7)

• 32-bit program counter (PC)

• 8-bit condition code register (CCR)

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Processor Register Description

2.2.1.1 Data Register s (D0–D7)

Registers D0–D7 are used as data registers for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they can also be used as index registers.

2.2.1.2 Address Registers (A0–A6)

These registers can be used as software stack pointers, index registers, or base address registers; they can also be used for word and longword operations.

2.2.1.3 Stack Pointer (A7)

Certain ColdFire implementations, including the MCF5216, support two unique stack pointer (A7) registers—the supervisor stack pointer (SSP) and the user stack pointer (USP). This support provides the required isolation between operating modes of the processor. The

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SSP is described in Section 2.2.3.2, “Supervisor/User Stack Pointers (A7 and OTHER_A7).”

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A subroutine call saves the PC on the stack and the return res tores it from the stack. B oth the PC and the SR are saved on the supervisor stack during the processing of exceptions and interrupts. The return from exception (RTE) instruction restores the SR and PC values from the supervisor stack.

2.2.1.4 Program Counter (PC)

The PC contains the address of the currently executing instruction. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC, as appropriate. For some addressing modes, the PC is used as a base address for PC-relative operand addressing.

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Processor Register Description

15 031

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15 7 0

D1 D2 D3 D4 D5 D6 D7

A0 A1 A2 A3 A4 A5 A6

CCR

DATA REGISTERS

ADDRESS REGISTERS

USERSTACK POINTER

PROGRAM COUNTER

CONDITION CODE REGISTER

Figure 2-2. User Programming Model

2.2.1.5 Condition Code Register (CCR)

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The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results generated by processor operations. Bit 4, the extend bit (X bit), is also used as an input operand during multiprecision arithmetic computations.

43210

XNZVC

Figure 2-3. Condition Code Register (CCR)

Table 2-1. CCR Field Descript ions

Bits Name Description

4 X Extend condition code bit. 3 N Negative condition code bit. Set if the most significant bit of the result is set;

otherwise cleared. 2 Z Zero condition code bit. Set if the result equals zero; otherwise cleared. 1 V Overflo w conditio n code bi t. Set if an arithmeti c overflow occurs i mplying tha t the

result cannot be represented in the operand size; otherwise cleared. 0 C Carry condition code bit. Set if a carry out of the operand msb occurs for an

addition, or if a borrow occurs in a subtraction; otherwise cleared

Set to the value of the C bit for arithmetic operations; otherwise not affected.

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Processor Register Description

2.2.2 Programming Model

The registers in the portion of the user programming model, are described in Chapter 3, “Enhanced Multiply-Accumulate Unit (EMAC),” and include the following registers:

These registers are shown in Figure 2-4.

31 0

MACSR MAC status register ACC MAC accumulator MASK MAC mask register

Figure 2-4. MAC Register Set

2.2.3 Supervisor Programming Model

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Only system control software is intended to use the supervisor programming model to implement restricted operating system functions, I/O control, and memory management. All accesses that affect the control features of ColdFire processors are in the supervisor programming model, which consists of registers available in user mode as well as the following control registers:

• 16-bit status register (SR)

• 32-bit supervisor stack pointer (SSP)

• 32-bit vector base register (VBR)

• 32-bit cache control register (CACR)

• Two 32-bit access control registers (ACR0, ACR1)

• Two 32-bit memory base address registers (RAMBAR, FLASHBAR)

15 7 0

(CCR)

OTHER_A7

VBR

CACR

ACR0

ACR1

FLASHBAR

RAMBAR

STATUS REGISTER SUPERVISOR A7

STACK POINTER VECTOR BASE

Figure 2-5. Supervisor Programming Model

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Processor Register Description

The following paragraphs describe the supervisor programming model registers.

2.2.3.1 Status Register (SR)

The SR stores the processor status and includes the CCR, the interrupt priority mas k, and other control bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits are accessible (CCR). The control bits indicate the following states for the processor: trace mode (T bit), supervisor or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access when in supervisor mode.

System Byte Condition Code Register (CCR)

151413121110 876543210

T0SM0 I 000XNZVC

Figure 2-6. Status Register

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Table 2-2. SR Field Descriptions

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Bits Name Description

15 T Trace enable. When set, the processo r performs a trace ex ception after

every instruction. 14 — Reserved, should be cleared. 13 S Supervisor/user state. Denotes whet her the proces sor is in superv isor

mode (S = 1) or user mode (S = 0). 12 M Master/interrupt state. This b it is cleared by an interrupt exce ption, and

can be set by software during execution of the RTE or move to SR

instructions.

11 — Reserved, should be cleared.

10–8 I Interrupt level mask. Defines the current interrupt level. Interrupt

requests are inhibited for all priority levels less than or equal to the

current level, except the edge-sensitive level 7 request, which cannot

be masked.

7–5 — Reserved, should be cleared. 4–0 CCR Refer to Table 2-1.

2.2.3.2 Supervisor/User Stack Pointers (A7 and OTHER_A7)

The MCF5216 architecture supports two independent stack pointer (A7) registers—the supervisor stack pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two programmable-visible 32-bit registers does not identify one as the SSP and the other as the USP . Instead, the hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus, the register contents are a function of the processor operation mode, as shown in the following:

if SR[S] = 1

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then A7 = Supervisor Stack Pointer

OTHER_A7 = User Stack Pointer

else A7 = User Stack Pointer

OTHER_A7 = Supervisor Stack Pointer

Processor Register Description

The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It is the responsibility of the external development system to determine, based on the setting of SR[S], the mapping of A7 and OTHER_A7 to the two program-visible definitions (SSP and USP). This functionality is enabled by setting the enable user stack pointer bit, CACR[EUSP]. If this bit is cleared, only the stack pointer (A7), defined for previous ColdFire versions, is available. EUSP is zero at reset.

If EUSP is set, the appropriate stack pointer register (SSP or USP) is accessed as a function of the processor’s operating mode. To support dual stack pointers, the following two

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privileged M68000 instructions are added to the ColdFire instruction set architec ture to load/store the USP :

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move.l Ay, USP; move to USP

move.l USP, Ax; move from USP

These instructions are described in the ColdFire Family Programmer’s Reference Manual.

2.2.3.3 Vector Base Register (VBR)

The VBR contains the base address of the exception vector table in memory. To access the vector table, the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are not implemented by ColdFire processors; they are assumed to be zero, forcing the table to be aligned on a 1 MByte boundary.

2.2.3.4 Cache Control Register (CACR)

The CACR controls operation of the instruction/data cach e memories. It includes bits for enabling, freezing, and invalidating cache contents. It also includes bits for defining the default cache mode and write-protect fields. The CACR is de scribed in Section 4.4.2.1, “Cache Control Register (CACR).”

2.2.3.5 Access Control Registers (ACR0, ACR1)

The access control registers, ACR0 and ACR1, define attributes for two user-defined memory regions. These attributes include the definition of cache mode, wri te protect, and buffer write enables. The ACRs are described in Section 4.4.2.2, “Access Control Registers (ACR0, ACR1).”

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2.2.3.6 Memory Base Address Registers (RAMBAR, FLASHBAR)

Memory base address registers are used to specify the base addres s of the internal SR AM and Flash modules and indicate the types of references mapped to each. Each base address register includes a base address, write-protect bit, address space mask bits, and an enable bit. For theMCF5216, FLASHBAR determines the base address of the on-chip Flash, and RAMBAR determines the base address of the on-chip RAM. For more information, refer to Section 5.3.1, “SRAM Base Address Register (RAMBAR)” and Section 6.3.2, “ Flash Base Address Register (FLASHBAR).”

2.3 Programming Model

Table 2-3 lists register names, the CPU space location, and whether the register is written from the processor using the MOVEC instruction.

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Table 2-3. ColdFire CPU Registers

Name CPU Space (Rc)

Memory Management Control Registers

CACR 0x002 Yes Cache control register ACR0, ACR1 0x004-0x005 Yes Access control registers 0 and 1

Processor General-Purpose Registers

D0-D7 0x(0,1)80-0x(0,1)87 No Data registers 0-7 (0 = load, 1 = store) A0-A7 0x(0,1)88-0x(0,1)8F No Address registers 0-7 (0 = load, 1 = store)

Processor Miscellaneous Regi sters

OTHER_A7 0x800 No Other stack pointer VBR 0x801 Yes Vector base register MACSR 0x804 No MAC status register MASK 0x805 No MAC address mask register ACC0-ACC3 0x806, 0x809,

0x80A, 0x80B

Written with

MOVEC

A7 is user stack pointer

No MAC accumulators 0-3

ACCext01 0x807 No MAC accumulator 0, 1 extension bytes ACCext23 0x808 No MAC accumulator 2, 3 extension bytes SR 0x80E No Status register PC 0x80F Yes Program counter

Local Memory Registers

FLASHBAR 0xC04 Yes Flash base address register RAMBAR 0xC05 Yes SRAM base address register

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Additions to the Instruction Set Architecture

2.4 Additions to the Instruction Set Architecture

The original ColdFire instruction set architecture (ISA) was derived from the M68000-family opcodes based on extensive analysis of embedded application code. After the initial ColdFire compilers were created, developers identified ISA additions that would enhance both code density and overall performance. Additionally, as users implemented ColdFire-based designs into a wide range of embedded systems, they identified frequently used instruction sequences that could be improved by the creation of new instructions. This observation was especially prevalent in development environments that made use of substantial amounts of assembly language code.

T able 2-4 summarizes the new instructions added to Revision A+ ISA. For more details see Section 2.14, “ColdFire Instruction Set Architecture Enhancements.”

Table 2-4. ISA Revision A+ New Instructions

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Instruction Description

BITREV The contents of the destinati on data register are bit-reverse d; that

is, new Dx[31] = old Dx[0], new Dx[30] = old Dx[1], ... , new Dx[0] = old Dx[31].

BYTEREV The contents of the destination data register are byte-reversed;

that is, new Dx[31:24] = old Dx[7:0], ..., new Dx[7:0] = old Dx[31:24].

FF1 The data register, Dx, is scanned, beginning from the

most-significant bit (Dx[3 1]) and endin g with the least-s igni ficant bit (Dx[0]), searching for the first set bit. The dat a register is then loaded with the offset count from bit 31 where the first set bit appears.

STLDSR Pushes the contents of the Status Register onto the stack and

then reloads the Status Register with the immediate data value.

2.5 Exception Processing Overview

Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors differ from the M68000 family in that they include:

• A simplified exception vector table

• Reduced relocation capabilities using the vector base register

• A single exception stack frame format

• Use of a single self-aligning system stack

All ColdFire processors use an instruction restart exception model, but certain microarchitectures (V2 and V3) require more software support to recover from certain access errors. See Section 2.7.1, “Access Error Exception” for details.

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Exception Processing Overview

Exception processing includes all actions from the detection of the faul t condition to the initiation of fetch for the first handler instruction. Exception processing is comprised of four major steps

First, the processor makes an internal copy of the SR a nd then enters supervisor mode by asserting the S bit and disabling trace mode by negating the T bit. The occurrence of an interrupt exception also forces the M bit to be cleared and the interrupt priority mask to be set to the level of the current interrupt request.

Second, the processor determines the exception vector number. For all faults except interrupts, the processor performs this calculation based on the exception type. For interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the interrupt controller. The IACK cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address.

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Third, the processor saves the current co ntext b y creati ng an exceptio n stack frame on the supervisor system stack. As a result, the exception stack frame is created at a 0-modulo-4 address on the top of the current system stack. Additionally, the processor uses a simplified fixed-length stack frame for all exceptions. The exception type determines whether the program counter placed in the exception stack frame defines the location of the faulting instruction (fault) or the address of the next instruction to be executed (next).

Fourth, the processor calculates the address of the first instruction of the exception handler . By definition, the exception vector table is aligned on a 1 Mbyte boundary . This instruction address is generated by fetching an exception vector from the tab le located at the ad dress defined in the vector base register. The index into the exception table is calculated as (4 x vector number). Once the exception vector has been fetched, the contents of the vector determine the address of the first instruction of the desired handler. After the instruction fetch for the first opcode of the handler has been initiated, exception processing terminates and normal instruction processing continues in the handler.

All ColdFire processors support a 1024-b yte vector tabl e aligned on any 1 M byte address boundary (see T able 2-5). The table contains 256 exception vectors; the first 64 are defined by Motorola and the remaining 192 are user-defined interrupt vectors.

Table 2-5. Exception Vector Assignments

Vector

Number(S)

0 0x000 — Initial stack pointer 1 0x004 — Initial program counter 2 0x008 Fault Access error 3 0x00C Fault Address error 4 0x010 Fault Illegal instruction 5 0x014 Fault Divide by zero

6–7 0x018–0x01C — Reserved

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Program

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Assignment

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Exception Stack Frame Definition

Table 2-5. Exception Vector Assignments (Continued)

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Vector

Number(S)

8 0x020 Fault Privilege violation

9 0x024 Next Trace 10 0x028 Fault Unimplemented line-a opcod e 11 0x02C Fault Unimplemented line-f opcode 12 0x030 Next Debug interrupt 13 0x034 — Reserved 14 0x038 Fault Format error

15–23 0x03C–0x05C — Reserved

24 0x060 Next Spurious interrupt

25–31 0x064-0x07C — Reserved 32–47 0x080–0x0BC Next Trap # 0-15 instructions 48–63 0x0C0–0x0FC — Reserved

64–255 0x100–0x3FC Next User-defined interrupts

“Fault” refers to the PC of the instructio n that cause d the exception; “N ext” refers to the PC

of the next instruction that follows the instruction that caused the fault.

Vector

Offset (Hex)

Stacked

Program

Counter

Assignment

All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers. This allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level contained in the status register. In addition, the V2 core includes a new instruction (STLDSR) that stores the current interrupt mask level and loads a value into the SR. This instru ction is sp ecifically intended for use as the first instru ction of an interrupt service routine which services multiple interrupt requests with different interrupt levels. For more details see Section 2.14, “ColdFire Instruction Set Architecture Enhancements.”

2.6 Exception Stack Frame Definition

The exception stack frame is shown in Figure 2-7. The first longword of the exception stack frame contains the 16-bit format/vector word (F/V) and the 16-bit status register, and the second longword contains the 32-bit program counter address.

SSP

FORMAT FS[3:2] VECTOR[7:0] FS[1:0] STATUS REGISTER

+ 0X4

PROGRAM COUNTER[31:0]

Figure 2-7. Exception Stack Frame Form

The 16-bit format/vector word contains 3 unique fields:

• A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by the processor indicating a two-longword frame format. See T able 2-6.

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Table 2-6. Format Field Encodings

Original SSP @ Time

of Exception, Bits 1:0

00 Original SSP - 8 4 01 Original SSP - 9 5 10 Original SSP - 10 6 11 Original SSP - 11 7

SSP @ 1st Instruction

of Handler

Format Field

• There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for access and address errors only and written as zeros for all other types of exceptions. See Table 2-7.

Table 2-7. Fault Status Encodings

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• The 8-bit vector number, vector[7:0], defines the exception type and is calculated by

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the processor for all internal faults and represents the value supplied by the interrupt controller in the case of an interrupt. Refer to Table 2-5.

FS[3:0] Definition

00xx Reserved 0100 Error on instruction fetch 0101 Reserved 011x Reserved 1000 Error on operand write 1001 Attempted write to write-protected space 101x Reserved 1100 Error on operand read 1101 Reserved 111x Reserved

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2.7 Processor Exceptions

2.7.1 Access Error Exception

The exact processor response to an access error depends on the type of memory reference being performed. For an instruction fetch, the processor postpones the error reporting until the faulted reference is needed by an instruction for execution. Therefore, faults that occur during instruction prefetches that are then followed by a change of instruction flow do not generate an exception. When the processor attempts to execute an instruction with a faulted opword and/or extension words, the access error is signaled and the instruction aborted. For

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Processor Exceptions

this type of exception, the programming model has not been altered by the instruction generating the access error.

If the access error occurs on an operand read, the processor immediately aborts the current instruction’s execution and initiates exception processing. In this situation, any address register updates attributable to the auto-addressing modes, (for example, (An)+,-(An)), have already been performed, so the programming model contains the updated An value. In addition, if an access error occurs during the execution of a MOVEM instruction loading from memory, any registers already updated before the fault occurs contain the operands from memory.

The V2 ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes. Because the actual write cycle may be decoupled from the processor ’s issuing of the operation, the signaling of an access error appears to be decou pled from the instruction that generated the write. Accor dingly, the PC contained in the exception stack

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frame merely represents the location in the program when the access error was signaled. All programming model updates associated with the write instruction are completed. The NOP instruction can collect access errors for writes. This instruction delays its execution until all previous operations, including all pending write operations, are complete. If any previous write terminates with an access error, it is guaranteed to be reported on the NOP instruction.

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2.7.2 Address Error Exception

Any attempted execution transferring control to an odd instruction address (that is, if bit 0 of the target address is set) results in an address error exception.

Any attempted use of a word-sized index register (Xn.w) or a scale factor of 8 on an indexed effective addressing mode generates an address error as does an attempted execution of a full-format indexed addressing mode.

2.7.3 Illegal Instruction Exception

Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an illegal instruction exception (vector 4). Additionally, any attempted execution of any non-MAC line-A and most line-F opcode generates their unique exception types, vector numbers 10 and 11, respectively. The V2 core does not provide illegal instruction detection on the extension words on any instruction, including MOVEC.

2.7.4 Divide-By-Zero

Attempting to divide by zero causes an exception (vector 5, offset = 0x014).

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2.7.5 Privilege Violation

The attempted execution of a supervisor mode instruction while in user mode gen erates a privilege violation exception. See the ColdFire Programmer’s Reference Manual for lists of supervisor- and user-mode instructions.

2.7.6 Trace Exception

To aid in program development, all ColdFire processors provide an instruction-by-instruction tracing capability. While in trace mode, indicated by the assertion of the T-bit in the status register (SR[15] = 1), the completion of an instruction execution (for all but the STOP instruction) signals a trace exception. This functionality allows a debugger to monitor program execution.

The STOP instruction has the following effects:

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1. The instruction before the STOP executes and then generates a trace exception. In the exception stack frame, the PC points to the STOP opcode.

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2. When the trace handler is exited, the STOP instruction is executed, loading the SR with the immediate operand from the instruction.

3. The processor then generates a trace exception. The PC in the exception stack frame points to the instruction after the STOP, and the SR reflects the value loaded in the previous step.

If the processor is not in trace mode and executes a STOP instruction where the immediate operand sets SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after the STOP , and the SR reflects the value loaded in step 2.

Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other exception types. As an example, consider the execution of a TRAP instruction while in trace mode. The processor will initiate the TRAP exception and then pass control to the corresponding handler. If the system requires that a trace exception be processed, it is the responsibility of the TRAP exception handler to check for this condition (SR[15] in the exception stack frame asserted) and pass control to the trace handler before returning from the original exception.

2.7.7 Unimplemented Line-A Opcode

A line-A opcode is defined when bits 15-1 2 of the opword are 0b1010. This exception is generated by the attempted execution of an undefined line-A opcode.

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Processor Exceptions

2.7.8 Unimplemented Line-F Opcode

A line-F opcode is defined when bits 15-1 2 of the opword are 0b1111. This exception is generated by attempted execution of an undefined line-F opcode.

2.7.9 Debug Interrupt

This special type of program interrupt is discussed in detail in Chapter 28, “Debug Support.” This exception is generated in response to a hardware breakpoint register trigger . The processor does not generate an IACK cycle but rather calculates the vector nu mber internally (vector number 12).

2.7.10 RTE and Format Error Exception

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When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the frame type. For a ColdFire core, any attempted RTE execution where the format is not equal to {4,5,6,7} generates a format error. The exception stack frame for the format error is created without disturbing the original RTE frame and the stacked PC pointing to the RTE instruction.

The selection of the format value prov ides some limited debug support for porting code from M68000 applications. On M68000 family processors, the SR was located at the top of the stack. On those processors, bit 30 of the longword addressed by the system stack pointer is typically zero. Thus, if an R TE is attempted using this “old” format, it generates a format error on a ColdFire processor.

If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the second longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the second longword operand within the stack frame.

2.7.11 TRAP Instruction Exception

The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing system calls.

2.7.12 Interrupt Exception

Interrupt exception processing includes interrupt recognition and the fetch of the appropriate vector from the interrupt controller using an IACK cycle. See Chapter 10, “Interrupt Controller Modules” for details on the interrupt controller.

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2.7.13 Fault-on-Fault Halt

If a ColdFire processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic “fault-on-fault” condition. A reset is required to force the processor to exit this halted state.

2.7.14 Reset Exception

Asserting the reset input signal to the processor causes a reset exception. The reset exception has the highest priority of any exception; it provides for system initialization and recovery from catastrophic failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot be recovered.

The reset exception places the processor in the supervisor mode by setting the S-bit and disables tracing by clearing the T bit in the SR. This exception also clears the M-bit and sets

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the processor’s interrupt priority mask in the SR to the highe st level (level 7). Next, the VBR is initialized to zero (0x00000000). The control registers sp ecifying th e operation of any memories (e.g., cache and/or RAM modules) connected directly to the processor are disabled.

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NOTE

Other implementation-specific supervisor registers are also affected. Refer to each of the modules in this user’ s manual for details on these registers.

Once the processor is granted the bus, it then performs two longword read bus cycles. The first longword at address 0 is loaded into the stack pointer and the second longword at address 4 is loaded into the program counter. After the initial instruction is fetched from memory, program execution begins at the address in the PC. If an access error or address error occurs before the first instruction is executed, the processor enters the fault-on -fault halted state.

ColdFire processors load hardware configuration information into the D0 and D1 general-purpose registers after system reset. The hardware configuration information is loaded immediately after the reset-in signal is negated. This allows an emulator to read out the contents of these registers via BDM to determine the hardware configuration.

Information loaded into D0 defines the processor hardware configuration as shown in Figure 2-8.

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31 24 23 20 19 16

Field PF VER REV

Reset 1100_1111_0010_0000

R/W R

15 14 13 12 11 10 8 7 4 3 0

Field MAC DIV EMAC FPU MMU — ISA DEBUG

Reset 0110_0000_1000_0000

R/W R

Processor Exceptions

Figure 2-8. D0 Hardware Configuration Info

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Table 2-8. D0 Hardware Configuration Info Field Description

Bits Name Description

31–24 PF Processor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is present. 23–20 VER ColdFire core version number . This fie ld is fixed to a hex val ue of 0x2 in dicating a Version 2 ColdFire

core.

19–16 REV Processor revision number.

15 MAC MAC execute engine status. Indicates if optional MAC unit is present.

0 MAC execute engine not present in core. (This is the value used for MCF5216.) 1 MAC execute engine is present in core.

14 DIV Divide execute engine status. Indicates if optional hardware divide unit is present.

0 Divide execute engine not present in core. 1 Divide execute engine is present in core. (This is the value used for MCF5216.)

13 EMAC EMAC execute engine status. Indicates if optional enhanced MAC unit is present.

0 EMAC execute engine not present in core.

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12 FPU FPU execute engine status. Indicates if optional FPU unit is present.

1 EMAC execute engine is present in core. (This is the value used for MCF5216.)

0 FPU execute engine not present in core. (This is the value used for MCF5216) 1 FPU execute engine is present in core.

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11 MMU Virtual memory management unit status. Indicates if optional MMU unit is present.

0 MMU execute engine not present in core. (This is the value used for MCF5216) 1 MMU execute engine is present in core.

10–8 — Reserved.

7–4 ISA Instruction set architecture (ISA) revision number.

0000 ISA_A 0001 ISA_B 0010 ISA_C 1000 ISA_A+ (ISA_A with the addition of the BYTEREV, BITREV, FF1, and STLDSR instructions.

This is the value used for MCF5216.)

0x3-0xF Reserved.

3–0 DEBUG Debug module revision number.

0000 DEBUG_A (This is the value used for MCF5216) 0001 DEBUG_B 0010 DEBUG_C 0011 DEBUG_D 0100 DEBUG_E 0x5-0xF Reserved.

Information loaded into D1 defines the local memory hardware configuration as sho wn in Figure 2-9.

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31 30 29 28 27 24 23 20 19 16

Field CL ICA ICSIZ RAM0SIZ ROM0SIZ

R/W R

15 14 13 12 11 8 7 4 3 0

Field BUSW DCA DCSIZ RAM1SIZ ROM1SIZ

R/W R

Processor Exceptions

Figure 2-9. D1 Hardware Configuration Info

Table 2-9. D1 Local Memory Hardware Configuration

Information Field Description

Bits Name Description

31–30 CL Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size.

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29–28 ICA Instruction cache associativity.

00 Four-way. 01 Direct mapped. (This is the value used for MCF5216)

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27–24 ICSIZ Instruction cache size.

0000 No instruction cache. 0001 512B instruction cache. 0010 1KB instruction cache. 0011 2KB instruction cache. (This is the value used for MCF5216) 0100 4KB instruction cache. 0101 8KB instruction cache. 0110 16KB instruction cache. 0111 32KB instruction cache. 1000 64KB instruction cache. 0x9–0xF Reserved.

23–20 RAM0SIZ RAM bank 0 size. The first RAM bank can be used for either SRAM or Flash. The first encodings

shown are used to indicate the size of a RAM bank, and the second set of encodings indicate the size for a Flash bank. On the MCF5216, RAM0 is associated with the on-chip Flash, so these bits use the Flash encodings. Note: The encoding for the Flash size does not change with the MCF5214.

RAM size encodings: 0x0–0x3 No RAM. 0100 4KB RAM. 0101 8KB RAM. 0110 16KB RAM. 0111 32KB RAM. 1000 64KB RAM. 1001 128KB RAM. 0xA–0xF Reserved. Flash size encodings: 0x0–0x7 No Flash. 1000 64KB Flash. 1001 128KB Flash. 1010 256KB Flash. 1011 512KB Flash. (This is the value used for MCF5216) 0xC–0xF Reserved.

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Instruction Execution Timing

Table 2-9. D1 Local Memory Hardware Configuration

Information Field Description (Continued)

Bits Name Description

19–16 R OM0SIZ ROM bank 0 size.

0x0–0x3 No ROM. (This is the value used for MCF5216) 0100 4KB ROM. 0101 8KB ROM. 0110 16KB ROM. 0111 32KB ROM. 1000 64KB ROM. 1001 128KB ROM. 0xA–0xF Reserved.

15–14 BUSW Encoded bus data width.

00 32-bit data bus (only configuration currently in use).

13–12 DCA Data cache associativity.

00 Four-way. 01 Direct mapped. (This is the value used for MCF5216)

11–8 DCSIZ Data cache size.

0000 No data cache. (This is the value used for MCF5216) 0001 512B data cache. 0010 1KB data cache. 0011 2KB data cache. 0100 4KB data cache. 0101 8KB data cache. 0110 16KB data cache. 01 11 32KB data cache. 1000 64KB data cache. 0x9–0xF Reserved.

7–4 RAM1SIZ RAM bank 1size.

0x0–0x3 No RAM. 0100 4KB RAM. 0101 8KB RAM. 0110 16KB RAM. 0111 32KB RAM. 1000 64KB RAM. (This is the value used for MCF5216) 1001 128KB RAM. 0xA–0xF Reserved.

3–0 ROM1SIZ ROM bank 1size.

0x0–0x3 No ROM. (This is the value used for MCF5216) 0100 4KB ROM. 0101 8KB ROM. 0110 16KB ROM. 0111 32KB ROM. 1000 64KB ROM. 1001 128KB ROM. 0xA–0xF Reserved.

2.8 Instruction Execution Timing

This section presents V2 processor instruction execution times in terms of processor core clock cycles. The number of operand references for each instruction is enclosed in

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Instruction Execution Timing

parentheses following the number of processor clock cycles. Each timing entry is presented as C(R/W) where:

•C is the number of processor clock cycles, including all applicable operand fetches and writes, and all internal core cycles required to complete the instruction execution.

• R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation performing a read-modify-write function is denoted as (1/1).

This section includes the assumptions concerning the timing values and the execution time details.

2.8.1 Timing Assumptions

For the timing data presented in this section, the following assumptions apply:

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1. The operand execution pipeline (OEP) is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP does not wait for the instruction fetch pipeline (IFP) to supply opwords and/or extension words.

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2. The OEP does not experience any sequence-related pipeline stalls. For V2 ColdFire processors, the most common example of this type of stall involves consecutive store operations, excluding the MOVEM instruction. For all STORE operations (except MOVEM), certain hardware resources within the processor are marked as “busy” for two processor clock cycles after the final DSOC cycle of the store instruction. If a subsequent STORE instruction is encountered within this 2-cycle window, it will be stalled until the resource again becomes available. Thus, the maximum pipeline stall involving consecutive STORE operations is 2 cycles. The MOVEM instruction uses a different set of resources and this stall does not apply.

3. The OEP completes all memory accesses without any stall conditions caused by the memory itself. Thus, the timing details provided in this section assume that an infinite zero-wait state memory is attached to the processor core.

4. All operand data accesses are aligned on the same byte boundary as the operand size: that is, 16 bit operands aligned on 0-modulo-2 addresses and 32 bit operands aligned on 0-modulo-4 addresses.

If the operand alignment fails these guidelines, it is misaligned. The processor core decomposes the misaligned operand reference into a series of aligned accesses as shown in Table 2-10.

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Instruction Execution Timing

Table 2-10. Misaligned Operand References

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Address[1:0] Size

X1 Word Byte, Byte 2(1/0) if read

X1 Long Byte, Word, Byte 3(2/0) if read

10 Long Word, Word 2(1/0) if read

Kbus

Operations

Additional

C(R/W)

1(0/1) if write

2(0/2) if write

1(0/1) if write

2.8.2 MOVE Instruction Execution Times

The execution times for the MOVE.{B,W} instructions are shown in Table 2-11, while Table 2-12 provides the timing for MOVE.L.

For all tables in this section, the execution time of any instruction using the PC-rel ative effective addressing modes is the same for the comparable An-relative mode.

The nomenclature “xxx.wl” refers to both forms of absolute addressing, xxx.w and xxx.l.

Source

Dn 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) An 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

(An) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1)

(An)+ 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1)

-(An) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) ,An) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —

,An,Xi) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —

(xxx).w 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

(xxx).l 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

Table 2-11. Move Byte and Word Execution Times

Destination

Rx (Ax) (Ax)+ -(Ax) (d

,Ax) (d8,Ax,Xi) (xxx).wl

(d16,PC) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — —

(d8,PC,Xi) 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — —

#<xxx> 1(0/0) 3(0/1) 3(0/1) 3(0/1) — — —

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Standard One Operand Instruction Execution Times

Table 2-12. Move Long Execution Times

Destination

Source

Rx (Ax) (Ax)+ -(Ax) (d

Dn 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) An 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)

(An) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)

(An)+ 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1)

-(An) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) ,An) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —

(d8,An,Xi) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

(xxx).w 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — —

,Ax) (d8,Ax,Xi) (xxx).wl

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(xxx).l 2(1/0) 2(1/1) 2(1/1) 2(1/1) — — —

,PC) 2(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) — —

(d8,PC,Xi) 3(1/0) 3(1/1) 3(1/1) 3(1/1) — — —

#<xxx> 1(0/0) 2(0/1) 2(0/1) 2(0/1) — — —

2.9 Standard One Operand Instruction Execution Times

Table 2-13. One Operand Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx

bitrevDx1(0/0)———— — ——

byterevDx1(0/0)———— — ——

clr.b <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

clr.w <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

clr.l <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) —

ext.wDx1(0/0)———— — ——

ext.lDx1(0/0)———— — ——

extb.lDx1(0/0)———— — ——

ff1Dx1(0/0)———— — ——

neg.lDx1(0/0)———— — ——

negx.lDx1(0/0)———— — ——

not.lDx1(0/0)———— — ——

sccDx1(0/0)———— — ——

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Standard Two Operand Instruction Execution Times

Table 2-13. One Operand Instruction Execution Times (Continued)

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx

stldsr#imm————— — —5(0/1) swapDx1(0/0)———— — ——

tst.b <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

tst.w <ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

tst.l <ea> 1(0/0) 2(1/0) 2(1/0) 2(1/0) 2(1/0) 3(1/0) 2(1/0) 1(0/0)

2.10 Standard Two Operand Instruction Execution Times

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Table 2-14. Two Operand Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An)

add.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) add.l Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

addi.l #imm,Dx 1(0/0) — — — — — — — addq.l #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — addx.l Dy,Dx 1(0/0) — — — — — — —

and.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) and.l Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

andi.l #imm,Dx 1(0/0) — — — — — — —

asl.l <ea>,Dx 1(0/0) — — — — — — 1(0/0)

asr.l <ea>,Dx 1(0/0) — — — — — — 1(0/0) bchg Dy,<ea> 2 (0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — bchg #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —

bclr Dy,<ea> 2 (0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) —

bclr #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — — bset Dy,<ea> 2(0/0) 4(1/1) 41/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — bset #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — —

btst Dy,<ea> 2(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

btst #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) — — 1(0/0)

cmp.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

cmpi.l #imm,Dx 1(0/0) — — — — — — —

divs.w divu.w

<ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0) 24(1/0) 23(1/0) 20(0/0)

(d16,An) (d16,PC)

(d8,An,Xn*SF) (d8,PC,Xn*SF)

xxx.wl #xxx

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Miscellaneous Instruction Execution Times

Table 2-14. Two Operand Instruction Execution Times (Continued)

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An)

divs.l divu.l

eor.l Dy,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

eori.l #imm,Dx 1(0/0) — — — — — — —

lea <ea>,Ax — 1(0/0) — — 1(0/0) 2(0/0) 1(0/0) — lsl.l <ea>,Dx 1(0/0) — — — — — — 1(0/0) lsr.l <ea>,Dx 1(0/0) — — — — — — 1(0/0)

moveq #imm,Dx — — — — — — — 1(0/0) muls.w <ea>y, Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 7(1/0) 6(1/0) 4(1/0) mulu.w <ea>y, Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 7(1/0) 6(1/0) 4(1/0)

muls.l <ea>y, Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) — — —

mulu.l <ea>y, Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) — — —

or.l <ea>,Rx 1 (0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0)

or.l Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) — ori.l #imm,Dx 1(0/0) — — — — — — —

rems.l remu.l

sub.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) sub.l Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

subi.l #imm,Dx 1(0/0) — — — — — — —

subq.l #imm,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —

subx.l Dy,Dx 1(0/0) — — — — — — —

For divide and remain der instru ction s the times li st ed repre sent the wors t-case timi ng. Depe nd ing on the o perand values, the actual execution time may be less.

<ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) — — —

(d16,An) (d16,PC)

(d8,An,Xn*SF) (d8,PC,Xn*SF)

xxx.wl #xxx

2.11 Miscellaneous Instruction Execution Times

Table 2-15. Miscell aneous Instruction Execution Times

Opcode <EA>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx

link.wAy,#imm2(0/1)———— — —— move.w CCR,Dx 1(0/0) ———— — —— move.w<ea>,CCR1(0/0)———— — —1(0/0) move.wSR,Dx1(0/0)———— — —— move.w<ea>,SR7(0/0)———— — —7(0/0)

MOTOROLA Chapter 2. ColdFire Core 2- 25

Effective Address

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EMAC Instruction Execution Times

Table 2-15. Miscellaneous Instruction Execution Times (Continued)

nc...

cale Semiconductor,

Frees

Opcode <EA>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx

movecRy,Rc9(0/1)———— — —— movem.l <ea>,&list — 1+n(n/0) — — 1+n(n/0) — — — movem.l &list,<ea> — 1+n(0/n) — — 1+n(0/n) — — —

nop 3(0/0)———— — —— pea <ea> — 2(0/1) — — 2(0/1)

pulse 1(0/0)———— — ——

stop#imm————— — —3(0/0)

trap#imm————— — —15(1/2)

trapf 1(0/0)———— — ——

trapf.w 1(0/0)———— — ——

trapf.l 1(0/0)———— — ——

unlkAx2(1/0)———— — ——

wddata <ea> — 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 3(1/0)

wdebug <ea> — 5(2/0) — — 5(2/0) — — —

n is the number of registers moved by the MOVEM opcode.

If a MOVE.W #imm,SR instruction is executed and imm[13] = 1, the execution time is 1(0/0).

The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.

PEA execution times are the same for (d16,PC).

PEA execution times are the same for (d8,PC,Xn*SF).

Effective Address

3(0/1)

2(0/1) —

2.12 EMAC Instruction Execution Times

Table 2-16. EMAC Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An) (d16,An)

muls.w <ea>y, Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 7(1/0) 6(1/0) 4(1/0)

mulu.w <ea>y, Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 7(1/0) 6(1/0) 4(1/0)

(d8,An,X

n*SF)

xxx.wl #xxx

muls.l <ea>y, Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) — — —

mulu.l <ea>y, Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) — — —

mac.wRy, Rx, Raccx1(0/0)———————

mac.lRy, Rx, Raccx1(0/0)———————

msac.wRy, Rx, Raccx1(0/0)———————

msac.lRy, Rx, Raccx1(0/0)——————— mac.w Ry, Rx, <ea>, Rw,

Raccx

2-26 MCF5216 User’s Manual MOTOROLA

— 2(1/0) 2(1/0) 2(1/0) 2(1/0)

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EMAC Instruction Execution Times

Table 2-16. EMAC Instruction Execution Times (Continued)

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An) (d16,An)

mac.l Ry, Rx, <ea>, Rw,

Raccx

msac.w Ry, Rx, <ea>, Rw — 2(1/0) 2(1/0) 2(1/0) 2(1/0)

msac.l Ry, Rx, <ea>, Rw ,

Raccx mov.l<ea>y, Raccx1(0/0)——————1(0/0) mov.lRaccy,Raccx1(0/0)——————— mov.l<ea>y, MACSR5(0/0)——————5(0/0)

— 2(1/0) 2(1/0) 2(1/0) 2(1/0)

(d8,An,X

n*SF)

———

——— ———

xxx.wl #xxx

nc...

cale Semiconductor,

Frees

mov.l<ea>y, Rmask4(0/0)——————4(0/0) mov.l<ea>y,Raccext011(0/0)——————1(0/0) mov.l<ea>y,Raccext231(0/0)——————1(0/0) mov.l Raccx,<ea>x 1(0/0) mov.lMACSR,<ea>x1(0/0)——————— mov.lRmask, <ea>x1(0/0)——————— mov.lRaccext01,<ea.x1(0/0)——————— mov.lRaccext23,<ea>x1(0/0)———————

Effective address of (d16,PC) not supported

Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional rounding is performed (MACSR[7:4] = 1---, -11-, --11)

———————

NOTE

The execution times for moving the contents of the Racc,

Raccext[01,23], MACSR, or Rmask into a destination location

<ea>x shown in this table represent the best-case scenario

when the store instruction is executed and there are no load or

M{S}AC instructions in the EMAC execution pipeline. In

general, these store operations require only a single cycle for

execution, but if preceded immediately by a load, MAC, or

MSAC instruction, the depth of the EMAC pipeline is exposed

and the execution time is four cycles.

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Branch Instruction Execution Times

2.13 Branch Instruction Exe cution Times

Table 2-17. General Branch Instruction Execution Times

Effective Address

Opcode <EA>

Rn (An) (An)+ -(An)

bsr ————3(0/1)— ——

jmp <ea> — 3(0/0) — — 3(0/0) 4(0/0) 3(0/0) —

jsr <ea> — 3(0/1) — — 3(0/1) 4(0/1) 3(0/1) — rte — — 10(2/0) — — — — — rts — — 5(1/0) — — — — —

Table 2-18. BRA, Bcc Instruction Execution Times

nc...

Opcode

Forward

Taken

Forward

Not Ta ken

(d16,An) (d16,PC)

Backward

Taken

(d8,An,Xi*SF)

(d8,PC,Xi*SF)

Backward Not Ta ken

xxx.wl #xxx

cale Semiconductor,

Frees

bra 2(0/0) — 2(0/0) — bcc 3(0/0) 1(0/0) 2(0/0) 3(0/0)

2.14 ColdFire Instruction Set Architecture Enhancements

This section describes the new opcodes implemented as part of the Revision A+ enhancements to the basic ColdFire ISA.

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ColdFire Instruction Set Architecture Enhancements

BITREV Bit Reverse Register BITREV

(Supported Starting with ISA A+)

Operation: Bit Reversed Dx → Dx Assembler Syntax: BITREV.L Dx Attributes: Size = longword

Instruction Format:

The contents of the destination data register are bit-reversed; that is, new Dx[31] = old Dx[0], new Dx[30] = old Dx[1], ..., new Dx[0] = old Dx[31].

nc...

Condition Codes: Not affected Instruction Field:

• Register field—Specifies the destination data register, Dx.

cale Semiconductor,

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000011000 Register, Dx

Frees

BITREV V2, V3 Core (ISA_A) V4 Core (ISA_B) V2 Core (ISA_A+)

Opcode present No No Yes

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ColdFire Instruction Set Architecture Enhancements

BYTEREV Byte Reverse Register BYTEREV

(Supported Starting with ISA A+)

Operation: Byte Reversed Dx → Dx Assembler Syntax: BYTEREV.L Dx Attributes: Size = longword

Instruction Format:

The contents of the destination data register are byte-reversed as defined below:

nc...

Condition Codes: Not affected Instruction Field:

• Register field—Specifies the destination data register, Dx.

cale Semiconductor,

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000001011000 Register, Dx

new Dx[31:24] = old Dx[7:0] new Dx[23:16] = old Dx[15:8] new Dx[15:8] = old Dx[23:16] new Dx[7:0] = old Dx[31:24]

Frees

BYTEREV V2, V3 Core (ISA_A) V4 Core (ISA_B) V2 Core (ISA_A+)

Opcode present No No Yes

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ColdFire Instruction Set Architecture Enhancements

FF1 Find First One in Register FF1

(Supported Starting with ISA A+)

Operation: Bit Offset of the First Logical One in Register → Destination Assembler Syntax: FF1.L Dx Attributes: Size = longword

Instruction Format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000010011000 Destination

The data register, Dx, is scanned, beginning from the most-significant bit (Dx[31]) and

nc...

ending with the least -significan t bit (D x[0]), sea rching for the first set bit. Th e data register is then loaded with the offset count from bit 31 where the first set bit appears, as shown below. If the source data is zero, then an offset of 32 is returned.

Old Dx[31:0] New Dx[31:0]

0b1---- . . . ---- 0x0000 0000

0b01--- . . . ---- 0x0000 0001

0b001-- . . . ---- 0x0000 0002

... ...

0b00000 . . . 0010 0x0000 001E 0b00000 . . . 0001 0x0000 001F 0b00000 . . . 0000 0x0000 0020

Condition Codes:

cale Semiconductor,

X N Z V C X Not affected

— ∗∗00

N Set if the msb of the source operand is set; cleared

otherwise Z Set if the source operand is zero; cleared otherwise V Always cleared C Always cleared

Frees

Instruction Field:

• Destination Register field—Specifies the destination data register, Dx.

FF1 V2, V3 Core (ISA_A) V4 Core (ISA_B) V2 Core (ISA_A+)

Opcode present No No Yes

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ColdFire Instruction Set Architecture Enhancements

STRLDSR Store/Load Status Register STRLDSR

(Supported Starting with ISA A+)

Operation: If Supervisor State

Then SP - 4 → SP; zero-filled SR → (SP); immediate data → SR Else TRAP

Assembler Syntax:STRLDSR #<data> Attributes: Size = word

Instruction Format:

nc...

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0100000011100111 0100011011111100

Immediate Data

Description: Pushes the conten ts of the Statu s Register on to the stack an d then reloa ds the Status Register with the immediate data val ue . Thi s in str ucti o n is i nte nd ed for use as the first instruction of an interrupt service routine shared across multiple interrupt request levels. It allows the level of the just-taken interrupt request to be stored in memory (using the SR[IML] field), and then masks interrupts by loading the SR[IML] field with 0x7 (if desired). If execution is attempted with bit 13 of the immediate data cleared (attempting to place the processor in user mode), a privilege violation exception is generated. The opcode for STRLDSR is 0x40E7 46FC.

Condition Codes:

X N Z V C X Set to the value of bit 4 of the immediate operand

∗∗∗∗∗

N Set to the value of bit 3 of the immediate operand Z Set to the value of bit 2 of the immediate operand V Set to the value of bit 1 of the immediate operand C Set to the value of bit 0 of the immediate operand

cale Semiconductor,

Frees

STRLDSR V2, V3 Core (ISA_A) V4 Core (ISA_B) V2 Core (ISA_A+)

Opcode present No No Yes

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Freescale MCF5216 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

About This Book

Audience

Organization

Suggested Reading

General Information

ColdFire Documentation

Conventions

Acronyms and Abbreviations

Terminology Conventions

Revision History

Chapter 1 Overview

1.1 MCF5216 Key Features

Figure 1-1. MCF5216 Block Diagram

1.1.1 Version 2 ColdFire Core

1.1.1.1 Cache

Table 1-1. Cache Configuration

1.1.1.2 SRAM

1.1.1.3 Flash

1.1.1.4 Debug Module

1.1.2 System Control Module

1.1.3 External Interface Module (EIM)

1.1.4 Chip Select

1.1.5 Power Management

1.1.6 General Input/Output Ports

1.1.7 Interrupt Controllers (INTC0/INTC1)

1.1.8 SDRAM Controller

1.1.9 Test Access Port

1.1.10 UART Modules

1.1.11 DMA Timers (DTIM0-DTIM3)

1.1.12 General-Purpose Timers (GPTA/GPTB)

1.1.13 Periodic Interrupt Timers (PIT0-PIT3)

1.1.14 Software Watchdog Timer

1.1.15 Phase Locked Loop (PLL)

1.1.16 DMA Controller

1.1.17 Reset

1.2 MCF5216-Specific Features

1.2.1 FlexCAN

1.2.2 I2C Bus

1.2.3 Queued Serial Peripheral Interface (QSPI)

1.2.4 Queued Analog-to-Digital Converter (QADC)

Chapter 2 ColdFire Core

2.1 Processor Pipelines

Figure 2-1. ColdFire Processor Core Pipelines

2.2 Processor Register Description

2.2.1 User Programming Model

2.2.1.3 Stack Pointer (A7)

2.2.1.4 Program Counter (PC)

Figure 2-2. User Programming Model

2.2.1.5 Condition Code Register (CCR)

Figure 2-3. Condition Code Register (CCR)

Table 2-1. CCR Field Descript ions

2.2.2 Programming Model

Figure 2-4. MAC Register Set

2.2.3 Supervisor Programming Model

Figure 2-5. Supervisor Programming Model

2.2.3.1 Status Register (SR)

Figure 2-6. Status Register

Table 2-2. SR Field Descriptions

2.2.3.2 Supervisor/User Stack Pointers (A7 and OTHER_A7)

2.2.3.3 Vector Base Register (VBR)

2.2.3.4 Cache Control Register (CACR)

2.2.3.5 Access Control Registers (ACR0, ACR1)

2.2.3.6 Memory Base Address Registers (RAMBAR, FLASHBAR)

2.3 Programming Model

Table 2-3. ColdFire CPU Registers

2.4 Additions to the Instruction Set Architecture

Table 2-4. ISA Revision A+ New Instructions

2.5 Exception Processing Overview

2.6 Exception Stack Frame Definition

Figure 2-7. Exception Stack Frame Form

Table 2-6. Format Field Encodings

Table 2-7. Fault Status Encodings

2.7 Processor Exceptions

2.7.1 Access Error Exception

2.7.2 Address Error Exception

2.7.3 Illegal Instruction Exception