Freescale MCF5216 DATA SHEET
MCF5216 ColdFire
®
al
d:
4
Freescale Semiconductor, Inc.
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MCF5216UM/D
Rev. 0
3/2004
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Microcontroller User’s Manu
Devices Supporte
MCF521
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© Motorola, Inc. 2004
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Overview
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1
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
ColdFire Flash Module (CFM)
Power Management
System Control Module (SCM)
Clock Module
Interrupt Controller Modules
Edge Port Module (EPORT)
Chip Select Module
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External Interface Module (EIM)
Signal Descriptions
Synchronous DRAM Controller Module
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3
4
5
6
7
8
9
10
11
12
13
14
15
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DMA Controller Module
Watchdog Timer Module
Programmable Interrupt Timer (PIT) Modules
General Purpose Timer (GPT) Modules
DMA Timers
Queued Serial Peripheral Interface Module (QSPI)
UART Modules
2
I
C Module
FlexCAN Module
General Purpose I/O Module
Chip Configuration Module (CCM)
Queued Analog-to-Digital Converter (QADC)
Reset Controller Module
Debug Support
16
17
18
19
20
21
22
23
24
25
26
27
28
29
IEEE 1149.1 Test Access Port (JTAG)
Mechanical Data
Electrical Characteristics
Appendix A: List of Memory Maps
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Index
30
31
32
A
IND
Overview
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ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
S tatic RAM (SRAM)
ColdFire Flash Module (CFM)
Power Management
System Control Module (SCM)
Clock Module
Interrupt Controller Modules
Edge Port Module (EPORT)
Chip Select Module
External Interface Module (EIM)
Signal Descriptions
Synchronous DRAM Controller Module
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17
18
19
20
21
22
23
24
25
26
27
28
29
DMA Controller Module
Watchdog Timer Module
Programmable Interrupt Timer (PIT) Modules
General Purpose Ti mer (GPT) Modules
DMA Timers
Queued Serial Peripheral Interface Module (QSPI)
UART Modules
2
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C Module
FlexCAN Module
General Purpose I/O Module
Chip Configuration Module (CCM)
Queued Analog-to-Digital Converter (QADC)
Reset Controller Module
Debug Support
30
31
32
A
IND
IEEE 1149.1 Test Access Port (JTAG)
Mechanical Data
Electrical Characteristics
Appendix A: List of Memory Maps
Index
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CONTENTS
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Title
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Chapter 1
Overview
1.1 MCF5216 Key Features...................................................................................... 1-1
1.1.1 Version 2 ColdFire Core................................................................................. 1-8
1.1.2 System Control Module................................................................................ 1-10
1.1.3 External Interface Module (EIM) ................................................................. 1-10
1.1.4 Chip Select.................................................................................................... 1-11
1.1.5 Power Management ...................................................................................... 1-11
1.1.6 General Input/Output Ports........................................................................... 1-11
1.1.7 Interrupt Controllers (INTC0/INTC1).......................................................... 1-11
1.1.8 SDRAM Controller....................................................................................... 1-11
1.1.9 Test Access Port............................................................................................ 1-12
1.1.10 UART Modules............................................................................................. 1-12
1.1.11 DMA Timers (DTIM0-DTIM3) ................................................................... 1-13
1.1.12 General-Purpose Timers (GPTA/GPTB)...................................................... 1-13
1.1.13 Periodic Interrupt Timers (PIT0-PIT3)......................................................... 1-13
1.1.14 Software Watchdog Timer............................................................................ 1-14
1.1.15 Phase Locked Loop (PLL)............................................................................ 1-14
1.1.16 DMA Controller............................................................................................ 1-14
1.1.17 Reset.............................................................................................................. 1-14
1.2 MCF5216-Specific Features............................................................................. 1-15
1.2.1 FlexCAN....................................................................................................... 1-15
1.2.2 I2C Bus.......................................................................................................... 1-15
1.2.3 Queued Serial Peripheral Interface (QSPI)................................................... 1-15
1.2.4 Queued Analog-to-Digital Converter (QADC) ............................................ 1-15
Chapter 2
ColdFire Core
2.1 Processor Pipelines ............................................................................................. 2-1
2.2 Processor Register Description........................................................................... 2-2
2.2.1 User Programming Model .............................................................................. 2-2
2.2.2 Programming Model ..................................................................................... 2-5
2.2.3 Supervisor Programming Model..................................................................... 2-5
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2.3 Programming Model........................................................................................... 2-8
2.4 Additions to the Instruction Set Architecture ..................................................... 2-9
2.5 Exception Processing Overview....................................................................... 2-10
2.6 Exception Stack Frame Definition.................................................................... 2-12
2.7 Processor Exceptions........................................................................................ 2-13
2.7.1 Access Error Exception ................................................................................ 2-13
2.7.2 Address Error Exception............................................................................... 2-14
2.7.3 Illegal Instruction Exception......................................................................... 2-14
2.7.4 Divide-By-Zero............................................................................................. 2-14
2.7.5 Privilege Violation........................................................................................ 2-14
2.7.6 Trace Exception............................................................................................ 2-14
2.7.7 Unimplemented Line-A Opcode................................................................... 2-15
2.7.8 Unimplemented Line-F Opcode ................................................................... 2-15
2.7.9 Debug Interrupt............................................................................................. 2-15
2.7.10 RTE and Format Error Exception................................................................. 2-16
2.7.11 TRAP Instruction Exception......................................................................... 2-16
2.7.12 Interrupt Exception....................................................................................... 2-16
2.7.13 Fault-on-Fault Halt ....................................................................................... 2-16
2.7.14 Reset Exception ............................................................................................ 2-16
2.8 Instruction Execution Timing........................................................................... 2-20
2.8.1 Timing Assumptions..................................................................................... 2-21
2.8.2 MOVE Instruction Execution Times............................................................ 2-22
2.9 Standard One Operand Instruction Execution Times ....................................... 2-23
2.10 Standard Two Operand Instruction Execution Times....................................... 2-24
2.11 Miscellaneous Instruction Execution Times..................................................... 2-25
2.12 EMAC Instruction Execution Times ................................................................ 2-26
2.13 Branch Instruction Execution Times ................................................................ 2-28
2.14 ColdFire Instruction Set Architecture Enhancements ...................................... 2-28
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Chapter 3
Enhanced Multiply-Accumulate Unit (EMAC)
3.1 Multiply-Accumulate Unit.................................................................................. 3-1
3.2 Introduction to the MAC..................................................................................... 3-2
3.3 General Operation............................................................................................... 3-3
3.4 Memory Map/Register Set.................................................................................. 3-4
3.4.1 MAC Status Register (MACSR) .................................................................... 3-4
3.4.2 Mask Register (MASK).................................................................................. 3-8
3.5 MAC Instruction Set Summary .......................................................................... 3-9
3.5.1 MAC Instruction Execution Times................................................................. 3-9
3.5.2 Data Representation........................................................................................ 3-9
3.5.3 MAC Opcodes .............................................................................................. 3-10
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Chapter 4
Cache
4.1 Cache Features.................................................................................................... 4-1
4.2 Cache Physical Organization.............................................................................. 4-1
4.3 Cache Operation ................................................................................................. 4-3
4.3.1 Interaction with Other Modules...................................................................... 4-3
4.3.2 Memory Reference Attributes ........................................................................ 4-4
4.3.3 Cache Coherency and Invalidation................................................................. 4-4
4.3.4 Reset................................................................................................................ 4-5
4.3.5 Cache Miss Fetch Algorithm/Line Fills ......................................................... 4-5
4.4 Cache Programming Model................................................................................ 4-7
4.4.1 Cache Registers Memory Map ....................................................................... 4-7
4.4.2 Cache Registers............................................................................................... 4-7
Chapter 5
Static RAM (SRAM)
5.1 SRAM Features................................................................................................... 5-1
5.2 SRAM Operation................................................................................................ 5-1
5.3 SRAM Programming Model............................................................................... 5-1
5.3.1 SRAM Base Address Register (RAMBAR)................................................... 5-2
5.3.2 SRAM Initialization........................................................................................ 5-3
5.3.3 SRAM Initialization Code.............................................................................. 5-4
5.3.4 Power Management ........................................................................................ 5-4
Chapter 6
ColdFire Flash Module (CFM)
6.1 Features............................................................................................................... 6-1
6.2 Block Diagram.................................................................................................... 6-2
6.3 Memory Map ...................................................................................................... 6-4
6.3.1 CFM Configuration Field ............................................................................... 6-5
6.3.2 Flash Base Address Register (FLASHBAR).................................................. 6-5
6.3.3 CFM Registers................................................................................................ 6-8
6.3.4 Register Descriptions...................................................................................... 6-9
6.4 CFM Operation................................................................................................. 6-17
6.4.1 Read Operations............................................................................................ 6-17
6.4.2 Write Operations........................................................................................... 6-17
6.4.3 Program and Erase Operations ..................................................................... 6-17
6.4.4 Stop Mode..................................................................................................... 6-22
6.4.5 Master Mode................................................................................................. 6-23
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6.5 Flash Security Operation .................................................................................. 6-23
6.5.1 Back Door Access......................................................................................... 6-24
6.5.2 Erase Verify Check....................................................................................... 6-24
6.6 Reset.................................................................................................................. 6-24
6.7 Interrupts........................................................................................................... 6-25
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Chapter 7
Power Management
7.1 Features............................................................................................................... 7-1
7.2 Memory Map and Registers................................................................................ 7-1
7.2.1 Programming Model....................................................................................... 7-1
7.2.2 Memory Map .................................................................................................. 7-2
7.2.3 Register Descriptions...................................................................................... 7-2
7.3 Functional Description........................................................................................ 7-5
7.3.1 Low-Power Modes.......................................................................................... 7-5
7.3.2 Peripheral Behavior in Low-Power Modes .................................................... 7-7
7.3.3 Summary of Peripheral State During Low-Power Modes............................ 7-16
Chapter 8
System Control Module (SCM)
8.1 Overview............................................................................................................. 8-1
8.2 Features............................................................................................................... 8-1
8.3 Memory Map and Register Definition................................................................ 8-2
8.4 Register Descriptions.......................................................................................... 8-3
8.4.1 Internal Peripheral System Base Address Register (IPSBAR)....................... 8-3
8.4.2 Memory Base Address Register (RAMBAR) ................................................ 8-4
8.4.3 Core Reset Status Register (CRSR)................................................................ 8-6
8.4.4 Core Watchdog Control Register (CWCR).................................................... 8-6
8.4.5 Core Watchdog Service Register (CWSR)..................................................... 8-9
8.5 Internal Bus Arbitration...................................................................................... 8-9
8.5.1 Overview....................................................................................................... 8-10
8.5.2 Arbitration Algorithms ................................................................................. 8-11
8.5.3 Bus Master Park Register (MPARK)............................................................ 8-12
8.6 System Access Control Unit (SACU)............................................................... 8-13
8.6.1 Overview....................................................................................................... 8-13
8.6.2 Features......................................................................................................... 8-14
8.6.3 Memory Map/Register Definition ................................................................ 8-15
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Chapter 9
Clock Module
9.1 Features............................................................................................................... 9-1
9.2 Modes of Operation ............................................................................................ 9-1
9.2.1 Normal PLL Mode.......................................................................................... 9-1
9.2.2 1:1 PLL Mode................................................................................................. 9-2
9.2.3 External Clock Mode...................................................................................... 9-2
9.3 Low-power Mode Operation .............................................................................. 9-2
9.4 Block Diagram.................................................................................................... 9-3
9.5 Signal Descriptions............................................................................................. 9-4
9.5.1 EXTAL ........................................................................................................... 9-4
9.5.2 XTAL.............................................................................................................. 9-5
9.5.3 CLKOUT........................................................................................................ 9-5
9.5.4 CLKMOD[1:0] ............................................................................................... 9-5
9.5.5 RSTOUT
9.6 Memory Map and Registers................................................................................ 9-5
9.6.1 Module Memory Map..................................................................................... 9-5
9.6.2 Register Descriptions...................................................................................... 9-6
9.7 Functional Description...................................................................................... 9-10
9.7.1 System Clock Modes.................................................................................... 9-10
9.7.2 Clock Operation During Reset...................................................................... 9-11
9.7.3 System Clock Generation ............................................................................. 9-11
9.7.4 PLL Operation .............................................................................................. 9-12
......................................................................................................... 9-5
Chapter 10
Interrupt Controller Modules
10.1 68K/ColdFire Interrupt Architecture Overview ............................................... 10-1
10.1.1 Interrupt Controller Theory of Operation..................................................... 10-3
10.2 Memory Map .................................................................................................... 10-5
10.3 Register Descriptions........................................................................................ 10-6
10.3.1 Interrupt Pending Registers (IPRHn, IPRLn)............................................... 10-6
10.3.2 Interrupt Mask Register (IMRHn, IMRLn).................................................. 10-8
10.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)................................... 10-9
10.3.4 Interrupt Request Level Register (IRLRn) ................................................. 10-10
10.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn)............ 10-11
10.3.6 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63)).................................. 10-11
10.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK). 10-15
10.4 Prioritization Between Interrupt Controllers .................................................. 10-16
10.5 Low-Power Wakeup Operation ...................................................................... 10-17
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Chapter 11
Edge Port Module (EPORT)
11.1 Introduction....................................................................................................... 11-1
11.2 Low-Power Mode Operation ............................................................................ 11-1
11.3 Interrupt/General-Purpose I/O Pin Descriptions............................................... 11-2
11.4 Memory Map and Registers.............................................................................. 11-3
11.4.1 Memory Map ................................................................................................ 11-3
11.4.2 Registers........................................................................................................ 11-3
Chapter 12
Chip Select Module
12.1 Overview........................................................................................................... 12-1
12.2 Chip Select Module Signals.............................................................................. 12-1
12.3 Chip Select Operation....................................................................................... 12-3
12.3.1 General Chip Select Operation..................................................................... 12-3
12.4 Chip Select Registers........................................................................................ 12-5
12.4.1 Chip Select Module Registers....................................................................... 12-6
Chapter 13
External Interface Module (EIM)
13.1 Features............................................................................................................. 13-1
13.2 Bus and Control Signals ................................................................................... 13-1
13.3 Bus Characteristics ........................................................................................... 13-2
13.4 Data Transfer Operation ................................................................................... 13-2
13.4.1 Bus Cycle Execution..................................................................................... 13-3
13.4.2 Data Transfer Cycle States ........................................................................... 13-5
13.4.3 Read Cycle.................................................................................................... 13-6
13.4.4 Write Cycle................................................................................................... 13-8
13.4.5 Fast Termination Cycles............................................................................... 13-9
13.4.6 Back-to-Back Bus Cycles........................................................................... 13-10
13.4.7 Burst Cycles................................................................................................ 13-10
13.5 Misaligned Operands...................................................................................... 13-14
Chapter 14
Signal Descriptions
14.1 Overview........................................................................................................... 14-1
14.1.1 Single-Chip Mode....................................................................................... 14-15
14.1.2 External Boot Mode.................................................................................... 14-15
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14.2 MCF5216 External Signals............................................................................. 14-16
14.2.1 External Interface Module (EIM) Signals .................................................. 14-16
14.2.2 SDRAM Controller Signals........................................................................ 14-19
14.2.3 Clock and Reset Signals ............................................................................. 14-20
14.2.4 Chip Configuration Signals ........................................................................ 14-20
14.2.5 External Interrupt Signals........................................................................... 14-21
14.2.6 Queued Serial Peripheral Interface (QSPI) Signals.................................... 14-21
14.2.7 FlexCAN Signals........................................................................................ 14-21
14.2.8 I2C Signals.................................................................................................. 14-22
14.2.9 UART Module Signals ............................................................................... 14-22
14.2.10 General Purpose Timer Signals .................................................................. 14-23
14.2.11 DMA Timer Signals.................................................................................... 14-23
14.2.12 Analog-to-Digital Converter Signals.......................................................... 14-25
14.2.13 Debug Support Signals ............................................................................... 14-26
14.2.14 Test Signals................................................................................................. 14-28
14.2.15 Power and Reference Signals ..................................................................... 14-28
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Chapter 15
Synchronous DRAM Controller Module
15.1 Overview........................................................................................................... 15-1
15.1.1 Definitions .................................................................................................... 15-1
15.1.2 Block Diagram and Major Components....................................................... 15-2
15.2 SDRAM Controller Operation.......................................................................... 15-3
15.2.1 DRAM Controller Signals............................................................................ 15-4
15.2.2 Memory Map for SDRAMC Registers......................................................... 15-4
15.2.3 General Synchronous Operation Guidelines................................................. 15-9
15.2.4 Initialization Sequence................................................................................ 15-17
15.3 SDRAM Example........................................................................................... 15-19
15.3.1 SDRAM Interface Configuration................................................................ 15-20
15.3.2 DCR Initialization....................................................................................... 15-20
15.3.3 DACR Initialization.................................................................................... 15-21
15.3.4 DMR Initialization...................................................................................... 15-22
15.3.5 Mode Register Initialization ....................................................................... 15-23
15.3.6 Initialization Code....................................................................................... 15-24
Chapter 16
DMA Controller Module
16.1 Overview........................................................................................................... 16-1
16.1.1 DMA Module Features................................................................................. 16-2
16.2 DMA Request Control (DMAREQC) .............................................................. 16-3
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16.3 DMA Transfer Overview.................................................................................. 16-4
16.4 DMA Controller Module Programming Model................................................ 16-5
16.4.1 Source Address Registers (SAR0–SAR3).................................................... 16-6
16.4.2 Destination Address Registers (DAR0–DAR3) ........................................... 16-6
16.4.3 Byte Count Registers (BCR0–BCR3) .......................................................... 16-7
16.4.4 DMA Control Registers (DCR0–DCR3)...................................................... 16-8
16.4.5 DMA Status Registers (DSR0–DSR3)....................................................... 16-10
16.5 DMA Controller Module Functional Description .......................................... 16-11
16.5.1 Transfer Requests (Cycle-Steal and
Continuous Modes) 16-11
16.5.2 Data Transfer Modes .................................................................................. 16-12
16.5.3 Channel Initialization and Startup.............................................................. 16-13
16.5.4 Data Transfer .............................................................................................. 16-14
16.5.5 Termination................................................................................................. 16-15
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Chapter 17
Watchdog Timer Module
17.1 Introduction....................................................................................................... 17-1
17.2 Low-Power Mode Operation ............................................................................ 17-1
17.3 Block Diagram.................................................................................................. 17-2
17.4 Signals............................................................................................................... 17-2
17.5 Memory Map and Registers.............................................................................. 17-2
17.5.1 Memory Map ................................................................................................ 17-2
17.5.2 Registers........................................................................................................ 17-3
Chapter 18
Programmable Interrupt Timer Modules (PIT0–PIT3)
18.1 Overview........................................................................................................... 18-1
18.2 Block Diagram.................................................................................................. 18-1
18.3 Low-Power Mode Operation ............................................................................ 18-2
18.4 Signals............................................................................................................... 18-2
18.5 Memory Map and Registers.............................................................................. 18-3
18.5.1 Memory Map ................................................................................................ 18-3
18.5.2 Registers........................................................................................................ 18-3
18.6 Functional Description...................................................................................... 18-6
18.6.1 Set-and-Forget Timer Operation................................................................... 18-6
18.6.2 Free-Running Timer Operation .................................................................... 18-7
18.6.3 Timeout Specifications................................................................................. 18-7
18.7 Interrupt Operation ........................................................................................... 18-8
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Chapter 19
General Purpose Timer Modules
(GPTA and GPTB)
19.1 Features............................................................................................................. 19-1
19.2 Block Diagram.................................................................................................. 19-2
19.3 Low-Power Mode Operation ............................................................................ 19-3
19.4 Signal Description............................................................................................. 19-3
19.4.1 GPTn[2:0]..................................................................................................... 19-3
19.4.2 GPTn3........................................................................................................... 19-4
19.4.3 SYNCn.......................................................................................................... 19-4
19.5 Memory Map and Registers.............................................................................. 19-4
19.5.1 GPT Input Capture/Output Compare Select Register (GPTIOS)................. 19-5
19.5.2 GPT Compare Force Register (GPCFORC)................................................. 19-6
19.5.3 GPT Output Compare 3 Mask Register (GPTOC3M).................................. 19-6
19.5.4 GPT Output Compare 3 Data Register (GPTOC3D).................................... 19-7
19.5.5 GPT Counter Register (GPTCNT) ............................................................... 19-7
19.5.6 GPT System Control Register 1 (GPTSCR1)............................................... 19-8
19.5.7 GPT Toggle-On-Overflow Register (GPTTOV).......................................... 19-9
19.5.8 GPT Control Register 1 (GPTCTL1)............................................................ 19-9
19.5.9 GPT Control Register 2 (GPTCTL2).......................................................... 19-10
19.5.10 GPT Interrupt Enable Register (GPTIE) .................................................... 19-10
19.5.11 GPT System Control Register 2 (GPTSCR2)............................................. 19-11
19.5.12 GPT Flag Register 1 (GPTFLG1)............................................................... 19-12
19.5.13 GPT Flag Register 2 (GPTFLG2)............................................................... 19-12
19.5.14 GPT Channel Registers (GPTCn)............................................................... 19-13
19.5.15 Pulse Accumulator Control Register (GPTPACTL) .................................. 19-13
19.5.16 Pulse Accumulator Flag Register (GPTPAFLG)........................................ 19-14
19.5.17 Pulse Accumulator Counter Register (GPTPACNT) ................................. 19-15
19.5.18 GPT Port Data Register (GPTPORT)......................................................... 19-16
19.5.19 GPT Port Data Direction Register (GPTDDR)........................................... 19-16
19.6 Functional Description.................................................................................... 19-17
19.6.1 Prescaler...................................................................................................... 19-17
19.6.2 Input Capture .............................................................................................. 19-17
19.6.3 Output Compare.......................................................................................... 19-17
19.6.4 Pulse Accumulator...................................................................................... 19-18
19.6.5 Event Counter Mode................................................................................... 19-18
19.6.6 Gated Time Accumulation Mode ............................................................... 19-19
19.6.7 General-Purpose I/O Ports.......................................................................... 19-19
19.7 Reset................................................................................................................ 19-21
19.8 Interrupts......................................................................................................... 19-21
19.8.1 GPT Channel Interrupts (CnF) ................................................................... 19-22
19.8.2 Pulse Accumulator Overflow (PAOVF)..................................................... 19-22
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19.8.3 Pulse Accumulator Input (PAIF)................................................................ 19-22
19.8.4 Timer Overflow (TOF)............................................................................... 19-22
Title
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Chapter 20
DMA Timers (DTIM0–DTIM3)
20.1 Overview........................................................................................................... 20-1
20.1.1 Key Features................................................................................................. 20-2
20.2 DMA Timer Programming Model.................................................................... 20-2
20.2.1 Prescaler........................................................................................................ 20-2
20.2.2 Capture Mode ............................................................................................... 20-3
20.2.3 Reference Compare....................................................................................... 20-3
20.2.4 Output Mode................................................................................................. 20-3
20.2.5 Memory Map ................................................................................................ 20-3
20.2.6 DMA Timer Mode Registers (DTMRn)....................................................... 20-4
20.2.7 DMA Timer Extended Mode Registers (DTXMRn).................................... 20-5
20.2.8 DMA Timer Event Registers (DTERn)........................................................ 20-6
20.2.9 DMA Timer Reference Registers (DTRRn)................................................. 20-7
20.2.10 DMA Timer Capture Registers (DTCRn) .................................................... 20-7
20.2.11 DMA Timer Counters (DTCNn) .................................................................. 20-8
20.3 Using the DMA Timer Modules....................................................................... 20-8
20.3.1 Code Example............................................................................................... 20-9
20.3.2 Calculating Time-Out Values..................................................................... 20-10
Chapter 21
Queued Serial Peripheral Interface
(QSPI) Module
21.1 Overview........................................................................................................... 21-1
21.2 Features............................................................................................................. 21-1
21.3 Module Description .......................................................................................... 21-1
21.3.1 Interface and Signals..................................................................................... 21-2
21.3.2 Internal Bus Interface.................................................................................... 21-3
21.4 Operation .......................................................................................................... 21-3
21.4.1 QSPI RAM.................................................................................................... 21-4
21.4.2 Baud Rate Selection...................................................................................... 21-6
21.4.3 Transfer Delays............................................................................................. 21-7
21.4.4 Transfer Length............................................................................................. 21-8
21.4.5 Data Transfer ................................................................................................ 21-8
21.5 Programming Model......................................................................................... 21-9
21.5.1 QSPI Mode Register (QMR) ...................................................................... 21-10
21.5.2 QSPI Delay Register (QDLYR) ................................................................. 21-11
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21.5.3 QSPI Wrap Register (QWR)....................................................................... 21-12
21.5.4 QSPI Interrupt Register (QIR).................................................................... 21-13
21.5.5 QSPI Address Register (QAR)................................................................... 21-14
21.5.6 QSPI Data Register (QDR)......................................................................... 21-14
21.5.7 Command RAM Registers (QCR0–QCR15).............................................. 21-15
21.5.8 Programming Example............................................................................... 21-16
Title
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Chapter 22
UART Modules
22.1 Overview........................................................................................................... 22-1
22.2 Serial Module Overview................................................................................... 22-2
22.3 Register Descriptions........................................................................................ 22-3
22.3.1 UART Mode Registers 1 (UMR1n).............................................................. 22-4
22.3.2 UART Mode Register 2 (UMR2n)............................................................... 22-6
22.3.3 UART Status Registers (USRn) ................................................................... 22-7
22.3.4 UART Clock Select Registers (UCSRn)...................................................... 22-8
22.3.5 UART Command Registers (UCRn)............................................................ 22-9
22.3.6 UART Receive Buffers (URBn)................................................................. 22-11
22.3.7 UART Transmit Buffers (UTBn) ............................................................... 22-11
22.3.8 UART Input Port Change Registers (UIPCRn).......................................... 22-12
22.3.9 UART Auxiliary Control Register (UACRn)............................................. 22-13
22.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)......................... 22-13
22.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)......................... 22-14
22.3.12 UART Input Port Register (UIPn).............................................................. 22-15
22.3.13 UART Output Port Command Registers (UOP1n/UOP0n) ....................... 22-15
22.4 UART Module Signal Definitions.................................................................. 22-16
22.5 Operation ........................................................................................................ 22-17
22.5.1 Transmitter/Receiver Clock Source............................................................ 22-17
22.5.2 Transmitter and Receiver Operating Modes............................................... 22-19
22.5.3 Looping Modes........................................................................................... 22-24
22.5.4 Multidrop Mode.......................................................................................... 22-26
22.5.5 Bus Operation............................................................................................. 22-28
22.5.6 Programming .............................................................................................. 22-28
Chapter 23
2
I
C Interface
23.1 Overview........................................................................................................... 23-1
23.2 Interface Features.............................................................................................. 23-1
23.3 I2C System Configuration................................................................................. 23-3
23.4 I2C Protocol ...................................................................................................... 23-3
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23.4.1 Arbitration Procedure ................................................................................... 23-4
23.4.2 Clock Synchronization.................................................................................. 23-5
23.4.3 Handshaking ................................................................................................. 23-5
23.4.4 Clock Stretching ........................................................................................... 23-5
23.5 Programming Model......................................................................................... 23-6
23.5.1 I
23.5.2 I2C Frequency Divider Register (I2FDR)..................................................... 23-7
23.5.3 I
23.5.4 I
23.5.5 I2C Data I/O Register (I2DR)..................................................................... 23-10
23.6 I
23.6.1 Initialization Sequence................................................................................ 23-10
23.6.2 Generation of START................................................................................. 23-11
23.6.3 Post-Transfer Software Response............................................................... 23-11
23.6.4 Generation of STOP.................................................................................... 23-12
23.6.5 Generation of Repeated START................................................................. 23-13
23.6.6 Slave Mode................................................................................................. 23-13
23.6.7 Arbitration Lost........................................................................................... 23-14
2
C Address Register (I2ADR)..................................................................... 23-6
2
C Control Register (I2CR)......................................................................... 23-8
2
C Status Register (I2SR)............................................................................ 23-9
2
C Programming Examples........................................................................... 23-10
Title
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Chapter 24
FlexCAN
24.1 Features............................................................................................................. 24-1
24.1.1 FlexCAN Memory Map................................................................................ 24-3
24.1.2 External Signals............................................................................................ 24-3
24.2 The CAN System.............................................................................................. 24-4
24.3 Message Buffers ............................................................................................... 24-4
24.3.1 Message Buffer Structure ............................................................................. 24-4
24.3.2 Message Buffer Memory Map...................................................................... 24-7
24.4 Functional Overview......................................................................................... 24-8
24.4.1 Transmit Process........................................................................................... 24-9
24.4.2 Receive Process ............................................................................................ 24-9
24.4.3 Message Buffer Handling........................................................................... 24-10
24.4.4 Remote Frames........................................................................................... 24-12
24.4.5 Overload Frames......................................................................................... 24-13
24.4.6 Time Stamp................................................................................................. 24-13
24.4.7 Listen-Only Mode....................................................................................... 24-13
24.4.8 Bit Timing................................................................................................... 24-14
24.4.9 FlexCAN Error Counters............................................................................ 24-15
24.4.10 FlexCAN Initialization Sequence............................................................... 24-16
24.4.11 Special Operating Modes............................................................................ 24-17
24.4.12 Interrupts..................................................................................................... 24-19
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24.5 Programmer’s Model...................................................................................... 24-20
24.5.1 CAN Module Configuration Register (CANMCR).................................... 24-20
24.5.2 FlexCAN Control Register 0 (CANCTRL0).............................................. 24-22
24.5.3 FlexCAN Control Register 1 (CANCTRL1).............................................. 24-23
24.5.4 Prescaler Divide Register (PRESDIV)....................................................... 24-24
24.5.5 FlexCAN Control Register 2 (CANCTRL2).............................................. 24-25
24.5.6 Free Running Timer (TIMER).................................................................... 24-26
24.5.7 Rx Mask Registers...................................................................................... 24-26
24.5.8 FlexCAN Error and Status Register (ESTAT) ........................................... 24-28
24.5.9 Interrupt Mask Register (IMASK).............................................................. 24-30
24.5.10 Interrupt Flag Register (IFLAG)................................................................. 24-31
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24.5.11 FlexCAN Receive Error Counter (RXECTR)............................................ 24-32
24.5.12 FlexCAN Transmit Error Counter (TXECTR)........................................... 24-32
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Chapter 25
General Purpose I/O Module
25.1 Introduction....................................................................................................... 25-1
25.1.1 Overview....................................................................................................... 25-3
25.1.2 Features......................................................................................................... 25-3
25.1.3 Modes of Operation...................................................................................... 25-3
25.2 External Signal Description.............................................................................. 25-4
25.3 Memory Map/Register Definition .................................................................... 25-6
25.3.1 Register Overview ........................................................................................ 25-6
25.3.2 Register Descriptions.................................................................................... 25-8
25.4 Functional Description.................................................................................... 25-25
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25.4.1 Overview..................................................................................................... 25-25
25.4.2 Port Digital I/O Timing .............................................................................. 25-25
25.5 Initialization/Application Information............................................................ 25-26
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Chapter 26
Queued Analog-to-Digital Converter (QADC)
26.1 Features............................................................................................................. 26-1
26.2 Block Diagram.................................................................................................. 26-2
26.3 Modes of Operation .......................................................................................... 26-3
26.3.1 Debug Mode ................................................................................................. 26-3
26.3.2 Stop Mode..................................................................................................... 26-3
26.4 Signals............................................................................................................... 26-4
26.4.1 Port QA Signal Functions............................................................................. 26-4
26.4.2 Port QB Signal Functions............................................................................. 26-5
26.4.3 External Trigger Input Signals...................................................................... 26-6
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26.4.4 Multiplexed Address Output Signals............................................................ 26-6
26.4.5 Multiplexed Analog Input Signals................................................................ 26-6
26.4.6 Voltage Reference Signals............................................................................ 26-7
26.4.7 Dedicated Analog Supply Signals ................................................................ 26-7
26.4.8 Dedicated Digital I/O Port Supply Signal..................................................... 26-7
26.5 Memory Map .................................................................................................... 26-7
26.6 Register Descriptions........................................................................................ 26-8
26.6.1 QADC Module Configuration Register (QADCMCR)................................ 26-8
26.6.2 QADC Test Register (QADCTEST) ............................................................ 26-9
26.6.3 Port Data Registers (PORTQA and PORTQB)............................................ 26-9
26.6.4 Port QA and QB Data Direction Register (DDRQA and DDRQB)........... 26-10
26.6.5 Control Registers ........................................................................................ 26-11
26.6.6 Status Registers........................................................................................... 26-19
26.6.7 Conversion Command Word Table (CCW) ............................................... 26-26
26.6.8 Result Registers .......................................................................................... 26-29
26.7 Functional Description.................................................................................... 26-31
26.7.1 Result Coherency........................................................................................ 26-31
26.7.2 External Multiplexing................................................................................. 26-31
26.7.3 Analog Subsystem ...................................................................................... 26-34
26.8 Digital Control Subsystem.............................................................................. 26-37
26.8.1 Queue Priority Timing Examples............................................................... 26-38
26.8.2 Boundary Conditions.................................................................................. 26-49
26.8.3 Scan Modes................................................................................................. 26-50
26.8.4 Disabled Mode............................................................................................ 26-50
26.8.5 Reserved Mode........................................................................................... 26-50
26.8.6 Single-Scan Modes..................................................................................... 26-50
26.8.7 Continuous-Scan Modes............................................................................. 26-54
26.8.8 QADC Clock (QCLK) Generation............................................................. 26-57
26.8.9 Periodic/Interval Timer............................................................................... 26-58
26.8.10 Conversion Command Word Table............................................................ 26-59
26.8.11 Result Word Table...................................................................................... 26-62
26.9 Signal Connection Considerations.................................................................. 26-62
26.9.1 Analog Reference Signals........................................................................... 26-63
26.9.2 Analog Power Signals................................................................................. 26-63
26.9.3 Conversion Timing Schemes...................................................................... 26-64
26.9.4 Analog Supply Filtering and Grounding .................................................... 26-67
26.9.5 Accommodating Positive/Negative Stress Conditions............................... 26-69
26.9.6 Analog Input Considerations...................................................................... 26-71
26.9.7 Analog Input Pins ....................................................................................... 26-73
26.10 Interrupts......................................................................................................... 26-75
26.10.1 Interrupt Operation ..................................................................................... 26-75
26.10.2 Interrupt Sources......................................................................................... 26-76
Title
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Chapter 27
Reset Controller Module
27.1 Features............................................................................................................. 27-1
27.2 Block Diagram.................................................................................................. 27-2
27.3 Signals............................................................................................................... 27-2
27.3.1 RSTI............................................................................................................. 27-2
27.3.2 RSTO
27.4 Memory Map and Registers.............................................................................. 27-3
27.4.1 Reset Control Register (RCR) ...................................................................... 27-3
27.4.2 Reset Status Register (RSR)......................................................................... 27-4
27.5 Functional Description...................................................................................... 27-6
27.5.1 Reset Sources................................................................................................ 27-6
27.5.2 Reset Control Flow....................................................................................... 27-8
27.5.3 Concurrent Resets....................................................................................... 27-10
........................................................................................................... 27-2
Chapter 28
Debug Support
28.1 Overview........................................................................................................... 28-1
28.2 Signal Description............................................................................................. 28-2
28.3 Real-Time Trace Support.................................................................................. 28-3
28.3.1 Begin Execution of Taken Branch (PST = 0x5)........................................... 28-4
28.4 Programming Model......................................................................................... 28-5
28.4.1 Revision A Shared Debug Resources........................................................... 28-7
28.4.2 Address Attribute Trigger Register (AATR)................................................ 28-8
28.4.3 Address Breakpoint Registers (ABLR, ABHR)........................................... 28-9
28.4.4 Configuration/Status Register (CSR) ......................................................... 28-10
28.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)....................................... 28-12
28.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR).................... 28-13
28.4.7 Trigger Definition Register (TDR)............................................................. 28-14
28.5 Background Debug Mode (BDM).................................................................. 28-16
28.5.1 CPU Halt..................................................................................................... 28-16
28.5.2 BDM Serial Interface.................................................................................. 28-18
28.5.3 BDM Command Set ................................................................................... 28-20
28.6 Real-Time Debug Support.............................................................................. 28-37
28.6.1 Theory of Operation.................................................................................... 28-37
28.6.2 Concurrent BDM and Processor Operation................................................ 28-39
28.7 Processor Status, DDATA Definition............................................................. 28-40
28.7.1 User Instruction Set .................................................................................... 28-40
28.7.2 Supervisor Instruction Set........................................................................... 28-44
28.8 Motorola-Recommended BDM Pinout........................................................... 28-46
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Chapter 29
Chip Configuration Module (CCM)
29.1 Features............................................................................................................. 29-1
29.2 Modes of Operation .......................................................................................... 29-1
29.2.1 Master Mode................................................................................................. 29-2
29.2.2 Single-Chip Mode......................................................................................... 29-2
29.3 Block Diagram.................................................................................................. 29-2
29.4 Signal Descriptions........................................................................................... 29-3
29.4.1 RCON ........................................................................................................... 29-3
29.4.2 CLKMOD[1:0] ............................................................................................. 29-3
29.4.3 D[26:24, 21, 19:16] (Reset Configuration Override) ................................... 29-3
29.5 Memory Map and Registers.............................................................................. 29-3
29.5.1 Programming Model..................................................................................... 29-3
29.5.2 Memory Map ................................................................................................ 29-4
29.5.3 Register Descriptions.................................................................................... 29-5
29.6 Functional Description...................................................................................... 29-8
29.6.1 Reset Configuration...................................................................................... 29-8
29.6.2 Chip Mode Selection .................................................................................. 29-10
29.6.3 Boot Device Selection ................................................................................ 29-11
29.6.4 Output Pad Strength Configuration ............................................................ 29-11
29.6.5 Clock Mode Selection................................................................................. 29-11
29.6.6 Chip Select Configuration .......................................................................... 29-12
29.7 Reset................................................................................................................ 29-12
29.8 Interrupts......................................................................................................... 29-12
Chapter 30
IEEE 1149.1 Test Access Port (JTAG)
30.1 Features............................................................................................................. 30-2
30.2 Modes of Operation .......................................................................................... 30-3
30.3 External Signal Description.............................................................................. 30-3
30.3.1 Detailed Signal Description.......................................................................... 30-3
30.4 Memory Map/Register Definition .................................................................... 30-5
30.4.1 Memory Map ................................................................................................ 30-5
30.4.2 Register Descriptions.................................................................................... 30-5
30.5 Functional Description...................................................................................... 30-7
30.5.1 JTAG Module............................................................................................... 30-7
30.5.2 TAP Controller ............................................................................................. 30-7
30.5.3 JTAG Instructions......................................................................................... 30-8
30.6 Initialization/Application Information............................................................ 30-11
30.6.1 Restrictions ................................................................................................. 30-11
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30.6.2 Nonscan Chain Operation........................................................................... 30-12
Title
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Chapter 31
Mechanical Data
31.1 Pinout................................................................................................................ 31-2
31.2 Ordering Information........................................................................................ 31-7
Chapter 32
Electrical Characteristics
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32.1 Maximum Ratings............................................................................................. 32-1
32.2 Thermal Characteristics.................................................................................... 32-3
32.3 DC Electrical Specifications............................................................................. 32-4
32.4 Phase Lock Loop Electrical Specifications ...................................................... 32-5
32.5 QADC Electrical Characteristics...................................................................... 32-7
32.6 Flash Memory Characteristics .......................................................................... 32-9
32.7 External Interface Timing Characteristics........................................................ 32-9
32.8 Processor Bus Output Timing Specifications................................................. 32-11
32.9 General Purpose I/O Timing........................................................................... 32-17
32.10 Reset and Configuration Override Timing ..................................................... 32-18
32.11 I2C Input/Output Timing Specifications......................................................... 32-19
32.12 DMA Timer Module AC Timing Specifications............................................ 32-21
32.13 QSPI Electrical Specifications........................................................................ 32-21
32.14 JTAG and Boundary Scan Timing.................................................................. 32-22
32.15 Debug AC Timing Specifications................................................................... 32-24
Appendix A
Register Memory Map
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Figure
Number
1-1 MCF5216 Block Diagram ............................................................................................ 1-7
2-1 ColdFire Processor Core Pipelines............................................................................... 2-1
2-2 User Programming Model ............................................................................................ 2-4
2-3 Condition Code Register (CCR)...................................................................................2-4
2-4 MAC Register Set......................................................................................................... 2-5
2-5 Supervisor Programming Model................................................................................... 2-6
2-6 Status Register ..............................................................................................................2-6
2-7 Exception Stack Frame Form ..................................................................................... 2-12
2-8 D0 Hardware Configuration Info................................................................................ 2-17
2-9 D1 Hardware Configuration Info................................................................................ 2-19
3-1 Multiply-Accumulate Functionality Diagram .............................................................. 3-2
3-2 Infinite Impulse Response (IIR) Filter.......................................................................... 3-3
3-3 Four-Tap FIR Filter ...................................................................................................... 3-3
3-4 MAC Register Set......................................................................................................... 3-4
3-5 MAC Status Register (MACSR)................................................................................... 3-4
3-6 Two’s Complement, Signed Fractional Equation......................................................... 3-9
4-1 Cache Block Diagram................................................................................................... 4-3
4-2 Cache Control Register (CACR) .................................................................................. 4-8
4-3 Access Control Registers (ACR0, ACR1).................................................................. 4-11
5-1 SRAM Base Address Register (RAMBAR)................................................................. 5-2
6-1 CFM Block Diagram .................................................................................................... 6-3
6-2 CFM Array Memory Map............................................................................................. 6-4
6-3 Flash Base Address Register (FLASHBAR)................................................................ 6-7
6-4 CFM Module Configuration Register (CFMCR) ......................................................... 6-9
6-5 CFM Clock Divider Register (CFMCLKD)............................................................... 6-10
6-6 CFM Security Register (CFMSEC)............................................................................ 6-11
6-7 CFM Protection Register (CFMPROT)...................................................................... 6-12
6-8 CFMPROT Protection Diagram ................................................................................. 6-13
6-9 CFM Supervisor Access Register (CFMSACC) ........................................................ 6-13
6-10 CFM Data Access Register (CFMDACC).................................................................. 6-14
6-11 CFM User Status Register (CFMUSTAT) ................................................................. 6-15
6-12 CFM Command Register (CFMCMD)....................................................................... 6-16
6-13 Example Program Algorithm...................................................................................... 6-21
7-1 Low-Power Interrupt Control Register (LPICR).........................................................7-3
7-2 Low-Power Control Register (LPCR) ......................................................................... 7-4
8-1 IPS Base Address Register (IPSBAR)..........................................................................8-4
Title
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Figure
Number
8-2 Memory Base Address Register (RAMBAR) .............................................................. 8-5
8-3 Core Reset Status Register (CRSR)............................................................................. 8-6
8-4 Core Watchdog Control Register (CWCR) ................................................................. 8-8
8-5 Core Watchdog Service Register (CWSR)..................................................................8-9
8-6 Arbiter Module Functions .......................................................................................... 8-10
8-7 Default Bus Master Park Register (MPARK)............................................................. 8-12
8-8 Master Privilege Register (MPR) .............................................................................. 8-16
8-9 Peripheral Access Control Register (PACRn)............................................................8-16
8-10 GPACR Register......................................................................................................... 8-18
9-1 Clock Module Block Diagram...................................................................................... 9-3
9-2 PLL Block Diagram...................................................................................................... 9-4
9-3 Synthesizer Control Register (SYNCR) ....................................................................... 9-6
9-4 Synthesizer Status Register (SYNSR).......................................................................... 9-8
9-5 Crystal Oscillator Example......................................................................................... 9-12
9-6 Lock Detect Sequence ................................................................................................9-15
10-1 Interrupt Pending Register High (IPRHn) .................................................................. 10-7
10-2 Interrupt Pending Register Low (IPRLn) ................................................................... 10-7
10-3 Interrupt Mask Register High (IMRHn)..................................................................... 10-8
10-4 Interrupt Mask Register Low (IMRLn) ...................................................................... 10-8
10-5 Interrupt Force Register High (INTFRCHn) .............................................................. 10-9
10-6 Interrupt Force Register Low (INTFRCLn) ............................................................. 10-10
10-7 Interrupt Request Level Register (IRLRn) ............................................................... 10-10
10-8 IACK Level and Priority Register (IACKLPRn) ..................................................... 10-11
10-9 Interrupt Control Register (ICRnx)........................................................................... 10-12
10-10 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)...............10-16
11-1 EPORT Block Diagram .............................................................................................. 11-1
11-2 EPORT Pin Assignment Register (EPPAR)............................................................... 11-4
11-3 EPORT Data Direction Register (EPDDR)................................................................11-4
11-4 EPORT Port Interrupt Enable Register (EPIER)........................................................ 11-5
11-5 EPORT Port Data Register (EPDR) ........................................................................... 11-5
11-6 EPORT Port Pin Data Register (EPPDR)................................................................... 11-6
11-7 EPORT Port Flag Register (EPFR) ............................................................................ 11-6
12-1 Connections for External Memory Port Sizes ............................................................ 12-4
12-2 Chip Select Address Registers (CSARn)................................................................... 12-6
12-3 Chip Select Mask Registers (CSMRn) ...................................................................... 12-7
12-4 Chip Select Control Registers (CSCRn)..................................................................... 12-8
13-1 Signal Relationship to CLKOUT for Non-DRAM Access ........................................ 13-2
13-2 Connections for External Memory Port Sizes ............................................................ 13-3
13-3 Chip-Select Module Output Timing Diagram............................................................ 13-3
13-4 Data Transfer State Transition Diagram.....................................................................13-5
13-5 Read Cycle Flowchart................................................................................................. 13-7
13-6 Basic Read Bus Cycle................................................................................................. 13-7
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Figure
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13-7 Write Cycle Flowchart................................................................................................ 13-8
13-8 Basic Write Bus Cycle................................................................................................ 13-8
13-9 Read Cycle with Fast Termination ............................................................................. 13-9
13-10 Write Cycle with Fast Termination ............................................................................ 13-9
13-11 Back-to-Back Bus Cycles......................................................................................... 13-10
13-12 Line Read Burst (2-1-1-1), External Termination .................................................... 13-11
13-13 Line Read Burst (2-1-1-1), Internal Termination ..................................................... 13-12
13-14 Line Read Burst (3-2-2-2), External Termination .................................................... 13-12
13-15 Line Read Burst-Inhibited, Fast Termination, External Termination....................... 13-13
13-16 Line Write Burst (2-1-1-1), Internal/External Termination...................................... 13-13
13-17 Line Write Burst (3-2-2-2) with One Wait State...................................................... 13-14
13-18 Line Write Burst-Inhibited........................................................................................ 13-14
13-19 Example of a Misaligned Longword Transfer (32-Bit Port) .................................... 13-15
13-20 Example of a Misaligned Word Transfer (32-Bit Port)............................................ 13-15
14-1 MCF5216 Block Diagram with Signal Interfaces ...................................................... 14-1
15-1 Synchronous DRAM Controller Block Diagram........................................................ 15-2
15-2 DRAM Control Register (DCR).................................................................................15-5
15-3 DRAM Address and Control Register (DACRn)....................................................... 15-6
15-4 DRAM Controller Mask Registers (DMRn) .............................................................. 15-8
15-5 Connections for External Memory Port Sizes .......................................................... 15-13
15-6 Burst Read SDRAM Access.....................................................................................15-14
15-7 Burst Write SDRAM Access.................................................................................... 15-15
15-8 Auto-Refresh Operation............................................................................................15-16
15-9 Self-Refresh Operation ............................................................................................. 15-17
15-10 Mode Register Set (mrs) Command ......................................................................... 15-19
15-11 Initialization Values for DCR...................................................................................15-20
15-12 SDRAM Configuration............................................................................................. 15-21
15-13 DACR Register Configuration.................................................................................. 15-21
15-14 DMR0 Register.........................................................................................................15-22
16-1 DMA Signal Diagram................................................................................................. 16-2
16-2 DMA Request Control Register (DMAREQC).......................................................... 16-3
16-3 Dual-Address Transfer................................................................................................ 16-4
16-4 Source Address Registers (SARn).............................................................................. 16-6
16-5 Destination Address Registers (DARn)...................................................................... 16-6
16-6 Byte Count Registers (BCRn)—BCR24BIT = 1........................................................ 16-7
16-7 Byte Count Registers (BCRn)—BCR24BIT = 0........................................................ 16-7
16-8 DMA Control Registers (DCRn)................................................................................ 16-8
16-9 DMA Status Registers (DSRn)................................................................................16-10
17-1 Watchdog Timer Block Diagram................................................................................17-2
17-2 Watchdog Control Register (WCR)............................................................................ 17-3
17-3 Watchdog Modulus Register (WMR)......................................................................... 17-4
17-4 Watchdog Count Register (WCNTR)......................................................................... 17-5
17-5 Watchdog Service Register (WSR) ............................................................................ 17-6
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MOTOROLA Illustrations xxv
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18-1 PIT Block Diagram..................................................................................................... 18-1
18-2 PIT Control and Status Register (PCSR).................................................................... 18-4
18-3 PIT Modulus Register (PMR)..................................................................................... 18-6
18-4 PIT Count Register (PCNTR)..................................................................................... 18-6
18-5 Counter Reloading from the Modulus Latch.............................................................. 18-7
18-6 Counter in Free-Running Mode.................................................................................. 18-7
19-1 GPT Block Diagram ................................................................................................... 19-2
19-2 GPT Input Capture/Output Compare Select Register (GPTIOS)............................... 19-5
19-3 GPT Input Compare Force Register (GPCFORC) ..................................................... 19-6
19-4 GPT Output Compare 3 Mask Register (GPTOC3M)................................................ 19-6
19-5 GPT Output Compare 3 Data Register (GPTOC3D).................................................. 19-7
19-6 GPT Counter Register (GPTCNT) ............................................................................. 19-7
19-7 GPT System Control Register 1 (GPTSCR1)............................................................. 19-8
19-8 Fast Clear Flag Logic.................................................................................................. 19-9
19-9 GPT Toggle-On-Overflow Register (GPTTOV)........................................................19-9
19-10 GPT Control Register 1 (GPTCTL1).......................................................................... 19-9
19-11 GPT Control Register 2 (GPTCTL2)........................................................................ 19-10
19-12 GPT Interrupt Enable Register (GPTIE) ..................................................................19-10
19-13 GPT System Control Register 2 (GPTSCR2)........................................................... 19-11
19-14 GPT Flag Register 1 (GPTFLG1)............................................................................. 19-12
19-15 GPT Flag Register 2 (GPTFLG2)............................................................................. 19-12
19-16 GPT Channel[0:3] Register (GPTCn)....................................................................... 19-13
19-17 Pulse Accumulator Control Register (GPTPACTL) ................................................ 19-13
19-18 Pulse Accumulator Flag Register (GPTPAFLG)...................................................... 19-14
19-19 Pulse Accumulator Counter Register (GPTPACNT) ............................................... 19-15
19-20 GPT Port Data Register (GPTPORT)....................................................................... 19-16
19-21 GPT Port Data Direction Register (GPTDDR)......................................................... 19-16
19-22 Channel 3 Output Compare/Pulse Accumulator Logic ............................................ 19-19
20-1 DMA Timer Block Diagram....................................................................................... 20-2
20-2 DTMRn Bit Definitions..............................................................................................20-4
20-3 DTXMRn Bit Definitions........................................................................................... 20-5
20-4 DTERn Bit Definitions............................................................................................... 20-6
20-5 DTRRn Bit Definitions............................................................................................... 20-7
20-6 DTCRn Bit Definitions............................................................................................... 20-8
20-7 DTCNn Bit Definitions............................................................................................... 20-8
21-1 QSPI Block Diagram .................................................................................................. 21-2
21-2 QSPI RAM Model ...................................................................................................... 21-5
21-3 QSPI Mode Register (QMR) .................................................................................... 21-10
21-4 QSPI Clocking and Data Transfer Example............................................................. 21-11
21-5 QSPI Delay Register (QDLYR) ............................................................................... 21-11
21-6 QSPI Wrap Register (QWR)..................................................................................... 21-12
21-7 QSPI Interrupt Register (QIR).................................................................................. 21-13
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xxvi MCF5216 User’s Manual MOTOROLA
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21-8 QSPI Address Register ............................................................................................. 21-14
21-9 QSPI Data Register (QDR)....................................................................................... 21-14
21-10 Command RAM Registers (QCR0–QCR15)............................................................ 21-15
21-11 QSPI Timing.............................................................................................................21-16
22-1 Simplified Block Diagram..........................................................................................22-1
22-2 UART Mode Registers 1 (UMR1n)............................................................................ 22-4
22-3 UART Mode Register 2 (UMR2n)............................................................................. 22-6
22-4 UART Status Register (USRn)...................................................................................22-7
22-5 UART Clock Select Register (UCSRn)...................................................................... 22-8
22-6 UART Command Register (UCRn)............................................................................ 22-9
22-7 UART Receive Buffer (URBn) ................................................................................ 22-11
22-8 UART Transmit Buffer (UTBn)...............................................................................22-12
22-9 UART Input Port Change Register (UIPCRn) ......................................................... 22-12
22-10 UART Auxiliary Control Register (UACRn)........................................................... 22-13
22-11 UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 22-13
22-12 UART Baud Rate Generator Register (UBG1n) ...................................................... 22-14
22-13 UART Baud Rate Generator Register (UBG2n) ...................................................... 22-14
22-14 UART Input Port Register (UIPn)............................................................................22-15
22-15 UART Output Port Command Registers (UOP1n/UOP0n) ..................................... 22-15
22-16 UART Block Diagram Showing External and Internal Interface Signals................ 22-16
22-17 UART/RS-232 Interface........................................................................................... 22-17
22-18 Clocking Source Diagram.........................................................................................22-18
22-19 Transmitter and Receiver Functional Diagram......................................................... 22-20
22-20 Transmitter Timing Diagram................................................................................... 22-21
22-21 Receiver Timing ....................................................................................................... 22-23
22-22 Automatic Echo ........................................................................................................ 22-25
22-23 Local Loop-Back ...................................................................................................... 22-25
22-24 Remote Loop-Back...................................................................................................22-26
22-25 Multidrop Mode Timing Diagram............................................................................ 22-27
22-26 UART Mode Programming Flowchart..................................................................... 22-31
23-1 I
23-2 I2C Standard Communication Protocol...................................................................... 23-3
23-3 Repeated START........................................................................................................ 23-4
23-4 Synchronized Clock SCL............................................................................................ 23-5
23-5 I2C Address Register (I2ADR)................................................................................... 23-6
23-6 I2C Frequency Divider Register (I2FDR) ................................................................. 23-7
23-7 I2C Control Register (I2CR)....................................................................................... 23-8
23-8 I2CR Status Register (I2SR)...................................................................................... 23-9
23-9 I2C Data I/O Register (I2DR).................................................................................. 23-10
23-10 Flow-Chart of Typical I2C Interrupt Routine........................................................... 23-15
24-1 FlexCAN Block Diagram and Pinout........................................................................ 24-2
24-2 Typical CAN system................................................................................................... 24-4
24-3 Extended ID Message Buffer Structure...................................................................... 24-5
2
C Module Block Diagram ....................................................................................... 23-2
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MOTOROLA Illustrations xxvii
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24-4 Standard ID Message Buffer Structure.......................................................................24-5
24-5 FlexCAN Memory Map.............................................................................................. 24-8
24-6 CAN Module Configuration Register (CANMCR).................................................. 24-20
24-7 FlexCAN Control Register 0 (CANCTRL0)............................................................ 24-22
24-8 FlexCAN Control Register 1 (CANCTRL1)............................................................ 24-23
24-9 Prescaler Divide Register (PRESDIV) ..................................................................... 24-24
24-10 FlexCAN Control Register 2 (CANCTRL2)............................................................ 24-25
24-11 Free Running Timer (TIMER)..................................................................................24-26
24-12 Rx Mask Registers (RXGMASK, RX14MASK, and RX15MASK) ....................... 24-27
24-13 FlexCAN Error and Status Register (ESTAT) ......................................................... 24-28
24-14 Interrupt Mask Register (IMASK)............................................................................24-30
24-15 Interrupt Flag Register (IFLAG)............................................................................... 24-31
24-16 FlexCAN Receive Error Counter (RXECTR) .......................................................... 24-32
24-17 FlexCAN Transmit Error Counter (TXECTR)......................................................... 24-32
25-1 MCF5216 Ports Module Block Diagram.................................................................... 25-2
25-2 Port Output Data Registers (8-bit)..............................................................................25-8
25-3 Port Output Data Register (7-bit)................................................................................ 25-8
25-4 Port Output Data Registers (6-bit)..............................................................................25-8
25-5 Port Output Data Registers (4-bit)..............................................................................25-9
25-6 Port Data Direction Registers (8-bit)..........................................................................25-9
25-7 Port Data Direction Register (7-bit).......................................................................... 25-10
25-8 Port Data Direction Registers (6-bit)........................................................................25-10
25-9 Port Data Direction Registers (4-bit)........................................................................25-10
25-10 Port Pin Data/Set Data Registers (8-bit)..................................................................25-11
25-11 Port Pin Data/Set Data Register (7-bit)..................................................................... 25-11
25-12 Port Pin Data/Set Data Registers (6-bit)...................................................................25-11
25-13 Port Pin Data/Set Data Registers (4-bit)...................................................................25-12
25-14 Port Clear Output Data Registers (8-bit) .................................................................. 25-12
25-15 Port Clear Output Data Register (7-bit).................................................................... 25-13
25-16 Port Clear Output Data Registers (6-bit) .................................................................. 25-13
25-17 Port Clear Output Data Registers (4-bit) .................................................................. 25-13
25-18 Port B/C/D Pin Assignment Register (PBCDPAR).................................................. 25-14
25-19 Port E Pin Assignment Register (PEPAR) ............................................................... 25-15
25-20 Port F Pin Assignment Register (PFPAR)................................................................ 25-17
25-21 Port J Pin Assignment Register (PJPAR)................................................................ 25-18
25-22 Port SD Pin Assignment Register (PSDPAR)..........................................................25-19
25-23 Port AS Pin Assignment Register (PASPAR)..........................................................25-19
25-24 Port EL Pin Assignment Register (PELPAR).......................................................... 25-20
25-25 Port QS Pin Assignment Register (PQSPAR)..........................................................25-21
25-26 Port TC Pin Assignment Register (PTCPAR).........................................................25-22
25-27 Port TD Pin Assignment Register (PTDPAR)......................................................... 25-23
25-28 Port UA Pin Assignment Register (PUAPAR)........................................................ 25-24
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xxviii MCF5216 User’s Manual MOTOROLA
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25-29 Digital Input Timing.................................................................................................25-25
25-30 Digital Output Timing .............................................................................................. 25-26
26-1 QADC Block Diagram................................................................................................ 26-2
26-2 QADC Input and Output Signals................................................................................26-5
26-3 QADC Module Configuration Register (QADCMCR)..............................................26-9
26-4 QADC Port QA Data Register (PORTQA).............................................................. 26-10
26-5 QADC Port QB Data Register (PORTQB)............................................................... 26-10
26-6 QADC Port QA Data Direction Register (DDRQA)................................................ 26-11
26-7 Port QB Data Direction Register (DDRQB)............................................................. 26-11
26-8 QADC Control Register 0 (QACR0)........................................................................ 26-12
26-9 QADC Control Register 1 (QACR1)........................................................................ 26-14
26-10 QADC Control Register 2 (QACR2)........................................................................ 26-17
26-11 QADC Status Register 0 (QASR0)........................................................................... 26-22
26-12 Queue Status Transition............................................................................................ 26-25
26-13 QADC Status Register 1 (QASR1)........................................................................... 26-26
26-14 Conversion Command Word Table (CCW) ............................................................. 26-27
26-15 Right-Justified Unsigned Result Register (RJURR)................................................. 26-29
26-16 Left-Justified Signed Result Register (LJSRR)........................................................26-30
26-17 Left-Justified Unsigned Result Register (LJURR)................................................... 26-31
26-18 External Multiplexing Configuration........................................................................ 26-33
26-19 QADC Analog Subsystem Block Diagram .............................................................. 26-35
26-20 Conversion Timing................................................................................................... 26-36
26-21 Bypass Mode Conversion Timing ............................................................................ 26-36
26-22 QADC Queue Operation with Pause ........................................................................ 26-39
26-23 CCW Priority Situation 1.......................................................................................... 26-41
26-24 CCW Priority Situation 2.......................................................................................... 26-42
26-25 CCW Priority Situation 3.......................................................................................... 26-42
26-26 CCW Priority Situation 4.......................................................................................... 26-43
26-27 CCW Priority Situation 5.......................................................................................... 26-43
26-28 CCW Priority Situation 6.......................................................................................... 26-44
26-29 CCW Priority Situation 7.......................................................................................... 26-44
26-30 CCW Priority Situation 8.......................................................................................... 26-45
26-31 CCW Priority Situation 9.......................................................................................... 26-45
26-32 CCW Priority Situation 10........................................................................................ 26-46
26-33 CCW Priority Situation 11........................................................................................ 26-46
26-34 CCW Freeze Situation 12 ......................................................................................... 26-47
26-35 CCW Freeze Situation 13 ......................................................................................... 26-47
26-36 CCW Freeze Situation 14 ......................................................................................... 26-47
26-37 . CCW Freeze Situation 15 ....................................................................................... 26-47
26-38 CCW Freeze Situation 16 ......................................................................................... 26-48
26-39 CCW Freeze Situation 17 ......................................................................................... 26-48
26-40 CCW Freeze Situation 18 ......................................................................................... 26-48
26-41 CCW Freeze Situation 19 ......................................................................................... 26-48
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MOTOROLA Illustrations xxix
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26-42 QADC Clock Subsystem Functions ......................................................................... 26-58
26-43 QADC Conversion Queue Operation ....................................................................... 26-60
26-44 Equivalent Analog Input Circuitry ........................................................................... 26-63
26-45 Errors Resulting from Clipping ................................................................................ 26-64
26-46 External Positive Edge Trigger Mode Timing with Pause....................................... 26-65
26-47 Gated Mode, Single Scan Timing............................................................................. 26-66
26-48 Gated Mode, Continuous Scan Timing..................................................................... 26-67
26-49 Star-Ground at the Point of Power Supply Origin.................................................... 26-68
26-50 Input Signal Subjected to Negative Stress................................................................ 26-69
26-51 Input Signal Subjected to Positive Stress ................................................................. 26-70
26-52 External Multiplexing of Analog Signal Sources..................................................... 26-72
26-53 Electrical Model of an A/D Input Signal..................................................................26-73
27-1 Reset Controller Block Diagram................................................................................. 27-2
27-2 Reset Control Register (RCR) .................................................................................... 27-3
27-3 Reset Status Register (RSR)....................................................................................... 27-4
27-4 Reset Control Flow..................................................................................................... 27-9
28-1 Processor/Debug Module Interface ............................................................................ 28-1
28-2 CLKOUT Timing ....................................................................................................... 28-2
28-3 Example JMP Instruction Output on PST/DDATA ................................................... 28-5
28-4 Debug Programming Model ....................................................................................... 28-6
28-5 Address Attribute Trigger Register (AATR)..............................................................28-8
28-6 Address Breakpoint Registers (ABLR, ABHR)......................................................... 28-9
28-7 Configuration/Status Register (CSR)........................................................................ 28-10
28-8 Data Breakpoint/Mask Registers (DBR/DBMR) ..................................................... 28-12
28-9 Program Counter Breakpoint Register (PBR) .......................................................... 28-14
28-10 Program Counter Breakpoint Mask Register (PBMR).............................................28-14
28-11 Trigger Definition Register (TDR)...........................................................................28-15
28-12 BDM Serial Interface Timing...................................................................................28-18
28-13 Receive BDM Packet................................................................................................ 28-19
28-14 Transmit BDM Packet.............................................................................................. 28-19
28-15 BDM Command Format........................................................................................... 28-21
28-16 Command Sequence Diagram .................................................................................. 28-22
28-17 RAREG/RDREG Command Format ............................................................................. 28-23
28-18 RAREG/RDREG Command Sequence.......................................................................... 28-23
28-19 WAREG/WDREG Command Format............................................................................ 28-24
28-20 WAREG/WDREG Command Sequence........................................................................ 28-24
28-21 READ Command/Result Formats............................................................................... 28-25
28-22 READ Command Sequence........................................................................................ 28-25
28-23 WRITE Command Format .......................................................................................... 28-26
28-24 WRITE Command Sequence ...................................................................................... 28-27
28-25 DUMP Command/Result Formats.............................................................................28-28
28-26 DUMP Command Sequence....................................................................................... 28-29
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xxx MCF5216 User’s Manual MOTOROLA
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