Freescale MCF51QE128, MCF51QE64, MCF51QE32 DATA SHEET

Freescale Semiconductor

80-LQFP
Case 917A
14 mm

2

64-LQFP

Case 840F

10 mm

2

Data Sheet: Advance Information

Document Number: MCF51QE128

Rev. 4, 09/2007

MCF51QE128 Series

Covers: MCF51QE128, MCF51QE64, MCF51QE32

• 32-Bit Version 1 ColdFire® Central Processor Unit (CPU)
– Up to 50.33-MHz ColdFire CPU from 3.6V to 2.1V, and

20-MHz CPU at 2.1V to 1.8V across temperature range
of -40°C to 85°C

– Provides 0.94 Dhrystone 2.1 MIPS per MHz

performance when running from internal RAM

(0.76 DMIPS/MHz from flash)
– Implements Instruction Set Revision C (ISA_C)
– Support for up to 30 peripheral interrupt requests and

seven software interrupts

•On-Chip Memory
– Flash read/program/erase over full operating voltage

and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to

RAM and flash contents

• Power-Saving Modes
– Two low power stop modes; reduced power wait mode
– Peripheral clock enable register can disable clocks to

unused modules, reducing currents; allows clocks to
remain enabled to specific peripherals in stop3 mode

– Very low power external oscillator can be used in stop3

mode to provide accurate clock to active peripherals

– Very low power real time counter for use in run, wait,

and stop modes with internal and external clock sources

–6 μs typical wake up time from stop modes

• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator;

Crystal or ceramic resonator range of 31.25 kHz to

38.4 kHz or 1 MHz to 16 MHz

– Internal Clock Source (ICS) — FLL controlled by

internal or external reference; precision trimming of
internal reference allows 0.2% resolution and 2%
deviation; supports CPU freq. from 2 to 50.33 MHz

• System Protection
– Watchdog computer operating properly (COP) reset

with option to run from dedicated 1-kHz internal clock
source or bus clock

– Low-voltage detection with reset or interrupt; selectable

trip points

– Illegal opcode and illegal address detection with

programmable reset or exception response

– Flash block protection

MCF51QE128

• Development Support
– Single-wire background debug interface
– 4 PC plus 2 address (optional data) breakpoint registers

with programmable 1- or 2-level trigger response

– 64-entry processor status and debug data trace buffer

with programmable start/stop conditions

• ADC — 24-channel, 12-bit resolution; 2.5 μs conversion
time; automatic compare function; 1.7 mV/°C temperature
sensor; internal bandgap reference channel; operation in
stop3; fully functional from 3.6V to 1.8V

• ACMPx — Two analog comparators with selectable
interrupt on rising, falling, or either edge of comparator
output; compare option to fixed internal bandgap reference
voltage; outputs can be optionally routed to TPM module;
operation in stop3

• SCIx — Two SCIs with full duplex non-return to zero
(NRZ); LIN master extended break generation; LIN slave
extended break detection; wake up on active edge

• SPIx— Two serial peripheral interfaces with Full-duplex or
single-wire bidirectional; Double-buffered transmit and
receive; MSB-first or LSB-first shifting

• IICx — Two IICs with; Up to 100 kbps with maximum bus
loading; Multi-master operation; Programmable slave
address; Interrupt driven byte-by-byte data transfer;
supports broadcast mode and 10 bit addressing

• TPMx — One 6-channel and two 3-channel; Selectable
input capture, output compare, or buffered edge- or
center-aligned PWMs on each channel

• RTC — 8-bit modulus counter with binary or decimal
based prescaler; External clock source for precise time
base, time-of-day, calendar or task scheduling functions;
Free running on-chip low power oscillator (1 kHz) for
cyclic wake-up without external components

• Input/Output
– 70 GPIOs and 1 input-only and 1 output-only pin
– 16 KBI interrupts with selectable polarity
– Hysteresis and configurable pull-up device on all input

pins; Configurable slew rate and drive strength on all

output pins.
– SET/CLR registers on 16 pins (PTC and PTE)
– 16 bits of Rapid GPIO connected to the CPU’s

high-speed local bus with set, clear, and toggle

functionality

This document contains information on a new product. Specifications and information herein
are subject to change without notice.

© Freescale Semiconductor, Inc., 2007. All rights reserved.

Table of Contents

1 MCF51QE128 Series Comparison . . . . . . . . . . . . . . . . . . . . . .4

2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .9

3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .9

3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .10

3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .11

3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15

3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .18

3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .19

3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.10.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . . 23

3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.10.4 Analog Comparator (ACMP) Electricals . . . . . . 27

3.10.5 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . 27

3.10.6 Flash Specifications . . . . . . . . . . . . . . . . . . . . . 30

3.11 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.11.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . 31

3.11.2 Conducted Transient Susceptibility . . . . . . . . . 31

4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 32

6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor2

TPM2CH2-0

TPM1CH2-0

ANALOG COMPARATOR

(ACMP1)

ACMP1O

ACMP1-

ACMP1+

V

SS

V

DD

IIC MODULE (IIC1)

SERIAL PERIPHERAL

INTERFACE MODULE (SPI1)

USER FLASH

USER RAM

128K / 64K

V1 ColdFire CORE

CPU

BDC / Debug

6-CHANNEL TIMER/PWM

MODULE (TPM3)

SYSTEM CONTROL

RESETS AND INTERRUPTS

MODES OF OPERATION

POWER MANAGEMENT

VOLTAGE

REGULATOR

COP

-

LVD

OSCILLATOR (XOSC)

RESET

V

REFL

V

REFH

8K / 6K / 4K

BKGD/MS

INTERFACE (SCI1)

SERIAL COMMUNICATIONS

MISO1

SS1

SPSCK1

3-CHANNEL TIMER/PWM

MODULE (TPM2)

REAL TIME COUNTER (RTC)

Rapid GPIO

IRQ

PTA3/KBI1P3/SCL1/ADP3

PTA4/ACMP1O/BKGD/MS

PTA5/IRQ/TPM1CLK/RESET

PTA2/KBI1P2/SDA1/ADP2

PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-

PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+

PORT A

PTA6/TPM1CH2/ADP8

PTA7/TPM2CH2/ADP9

MOSI1

PTB3/KBI1P7/MOSI1/ADP7

PTB4/TPM2CH1/MISO1

PTB5/TPM1CH1/SS1

PTB2/KBI1P6/SPSCK1/ADP6

PTB1/KBI1P5/TxD1/ADP5

PTB0/KBI1P4/RxD1/ADP4

PORT B

PTB6/SDA1/XTAL

PTB7/SCL1/EXTAL

PTC3/RGPIO11/TPM3CH3

PTC4/RGPIO12/TPM3CH4/RSTO

PTC5/RGPIO13/TPM3CH5/ACMP2O

PTC2/RGPIO10/TPM3CH2

PTC1/RGPIO9/TPM3CH1

PTC0/RGPIO8/TPM3CH0

PORT C

PTC6/RGPIO14/RxD2/ACMP2+

PTC7/RGPIO15/TxD2/ACMP2-

PTD3/KBI2P3/SS2

PTD4/KBI2P4

PTD5/KBI2P5

PTD2/KBI2P2/MISO2

PTD1/KBI2P1/MOSI2

PTD0/KBI2P0/SPSCK2

PORT D

PTD6/KBI2P6

PTD7/KBI2P7

PTE3/RGPIO3/SS1

PTE4/RGPIO4

PTE5/RGPIO5

PTE2/RGPIO2/MISO1

PTE1/RGPIO1/MOSI1

TPM2CLK

PORT E

PTE6/RGPIO6

PTE0/RGPIO0/TPM2CLK/SPSCK1

PTF3/ADP13

PTF4/ADP14

PTF5/ADP15

PTF2/ADP12

PTF1/ADP11

PTF0/ADP10

PORT F

PTF6/ADP16

PTF7/ADP17

PTG1

PTG2/ADP18

PTG3/ADP19

PORT G

PTG4/ADP20

PTG5/ADP21

PTG0

V

SS

V

DD

V

SSA

V

DDA

IP Bus Bridge

INTC

ANALOG COMPARATOR

(ACMP2)

INTERFACE (SCI2)

SERIAL COMMUNICATIONS

TPM3CH5-0

PTG6/ADP22

PTG7/ADP23

SOURCE (ICS)

INTERNAL CLOCK

PORT J

PORT H

PTJ1

PTJ2

PTJ3

PTJ4

PTJ5

PTJ0

PTJ6

PTJ7

PTH1

PTH2

PTH3

PTH4

PTH5

PTH0

PTH6/SCL2

PTH7/SDA2

IIC MODULE (IIC2)

ANALOG-TO-DIGITAL

CONVERTER (ADC)

24-CHANNEL,12-BIT

3-CHANNEL TIMER/PWM

MODULE (TPM1)

SDA2
SCL2

SERIAL PERIPHERAL

INTERFACE MODULE (SPI2)

MISO2

SS2

SPSCK2

MOSI2

EXTAL

XTAL

16

SDA1

SCL1

ACMP2-

ACMP2+

ACMP2O

RxD1

TxD1

RxD2

TxD2

TPM3CLK

3

TPM1CLK

PTE7/RGPIO7/TPM3CLK

Figure 1. MCF51QE128 Series Block Diagram

Freescale Semiconductor 3

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

MCF51QE128 Series Comparison

1 MCF51QE128 Series Comparison

The following table compares the various device derivatives available within the MCF51QE128 series.

Table 1. MCF51QE128 Series Features by MCU and Package

Feature MCF51QE128 MCF51QE64 MCF51QE32

Flash size (bytes) 131072 65536 32768

RAM size (bytes) 8192 8192 8192

Pin quantity 80 64 64 64

Version 1 ColdFire core yes yes

ACMP1 yes yes

ACMP2 yes yes

ADC channels 24 20 20 20

DBG yes

ICS yes

IIC1 yes

IIC2 yes

KBI 16

Port I/O

Rapid GPIO yes

RTC yes

SCI1 yes

SCI2 yes

SPI1 yes

SPI2 yes

External IRQ yes

TPM1 channels 3

TPM2 channels 3

TPM3 channels 6

XOSC yes

1

2

1, 2

Port I/O count does not include the input-only PTA5/IRQ/TPM1CLK/RESET or the
output-only PTA4/ACMP1O/BKGD/MS.

16 bits associated with Ports C and E are shadowed with ColdFire Rapid GPIO
module.

70 54 54 54

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor4

Pin Assignments

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

80797877767574737271706968676665646362

61

21222324252627282930313233343536373839

40

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

V

REFH

V

SSAD

V

DD

V

REFL

V

DDAD

V

SS

PTB7/SCL1/EXTAL

PTH7/SDA2

PTD0/KBI2P0/SPSCK2

PTD1/KBI2P1/MOSI2

PTE6/RGPIO6

PTB6/SDA1/XTAL

PTH6/SCL2

PTE7/RGPIO7/TPM3CLK

PTH1
PTH0

PTH3
PTH2

PTH5
PTH4

PTC2/RGPIO10/TPM3CH2

PTB4/TPM2CH1/MISO1

PTB5/TPM1CH1/SS1

PTC3/RGPIO11/TPM3CH3

PTD7/KBI2P7

PTC0/RGPIO8/TPM3CH0

PTC1/RGPIO9/TPM3CH1

PTD6/KBI2P6

PTD5/KBI2P5

PTB3/KBI1P7/MOSI1/ADP7

PTB2/KBI1P6/SPSCK1/ADP6

PTE5/RGPIO5

PTF7/ADP17

PTF6/ADP16

PTF5/ADP15

PTF4/ADP14

PTD4/KBI2P4

V

DD

V

SS

PTA7/TPM2CH2/ADP9

PTB1/KBI1P5/TxD1/ADP5

PTB0/KBI1P4/RxD1/ADP4

PTA2/KBI1P2/SDA1/ADP2
PTA3/KBI1P3/SCL1/ADP3

PTA6/TPM1CH2/ADP8

PTD3/KBI2P3/SS2

PTD2/KBI2P2/MISO2

PTE4/RGPIO4

PTF0/ADP10
PTF1/ADP11

PTF2/ADP12
PTF3/ADP13

PTE2/RGPIO2/MISO1

PTA5/IRQ/TPM1CLK/RESET

PTA4/ACMP1O/BKGD/MS

PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+

PTC7/RGPIO15 /TxD2/ACMP2-

PTC5/RGPIO13/TPM3CH5/ACMP2O

PTC4/RGPIO12/TPM3CH4/RSTO

PTC6/RGPIO14/RxD2/ACMP2+

PTE0/RGPIO0/TPM2CLK/SPSCK1

PTE1/RGPIO1/MOSI1

PTE3/RGPIO3/SS1

PTG3/ADP19

PTG2/ADP18

PTG1

PTG0

PTG7/ADP23

PTG6/ADP22

PTG5/ADP21

PTG4/ADP20

PTJ4

PTJ5

PTJ6

PTJ7

PTJ1

PTJ0

PTJ3

PTJ2

PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-

Pins in bold are added from the next smaller package.

2 Pin Assignments

This section describes the pin assignments for the available packages. See Tab le 1 for pin availability by package pin-count.

Freescale Semiconductor 5

Figure 2. Pin Assignments in 80-Pin LQFP

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Pin Assignments

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

171819202122232425262728293031

32

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

646362616059585756555453525150

49

V

REFH

V

SSAD

V

DD

V

REFL

V

DDAD

V

SS

PTB7/SCL1/EXTAL

PTH7/SDA2

PTD0/KBI2P0/SPSCK2

PTD1/KBI2P1/MOSI2

PTE6/RGPIO6

PTB6/SDA1/XTAL

PTC2/RGPIO10/TPM3CH2

PTB4/TPM2CH1/MISO1

PTB5/TPM1CH1/SS1

PTC3/RGPIO11/TPM3CH3

PTD7/KBI2P7

PTC0/RGPIO8/TPM3CH0

PTC1/RGPIO9/TPM3CH1

PTD6/KBI2P6

PTD5/KBI2P5

PTB3/KBI1P7/MOSI1/ADP7

PTB2/KBI1P6/SPSCK1/ADP6

PTE5/RGPIO5

PTD4/KBI2P4

V

DD

V

SS

PTA7/TPM2CH2/ADP9

PTB1/KBI1P5/TxD1/ADP5

PTB0/KBI1P4/RxD1/ADP4

PTA2/KBI1P2/SDA11/ADP2
PTA3/KBI1P3/SCL1/ADP3

PTA6/TPM1CH2/ADP8

PTD3/KBI2P3/SS2

PTD2/KBI2P2/MISO2

PTE4/RGPIO4

PTE2/RGPIO2/MISO1

PTA5/IRQ/TPM1CLK/RESET

PTA4/ACMP1O/BKGD/MS

PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+

PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-

PTC7/RGPIO15/TxD2/ACMP2-

PTC5/RGPIO13/TPM3CH5/ACMP2O

PTC4/RGPIO12/TPM3CH4/RSTO

PTC6/RGPIO14/RxD2/ACMP2+

PTE0/RGPIO0/TPM2CLK/SPSCK1

PTE1/RGPIO1/MOSI1

PTE3/RGPIO3/SS1

PTF0/ADP10
PTF1/ADP11

PTF7/ADP17

PTF6/ADP16

PTF5/ADP15

PTF4/ADP14

PTF2/ADP12
PTF3/ADP13

PTG3/ADP19

PTG2/ADP18

PTG1

PTG0

PTH6/SCL2

PTE7/RGPIO7/TPM3CLK

PTH1
PTH0

Figure 3. Pin Assignments in 64-Pin LQFP Package

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor6

Pin Assignments

Table 2. MCF51QE128 Series Pin Assignment by Package and Pin Sharing Priority

Pin

Number

Lowest ←⎯ Priority ⎯→ Highest

80 64 Port Pin Alt 1 Alt 2 Alt 3 Alt 4

1 1 PTD1 KBI2P1 MOSI2

2 2 PTD0 KBI2P0 SPSCK2

3 3 PTH7 SDA2

44 PTH6 SCL2

5— PTH5

6— PTH4

7 5 PTE7 RGPIO7 TPM3CLK

86 V

97 V

10 8 V

11 9 V

12 10 V

13 11 V

DD

DDAD

REFH

REFL

SSAD

SS

14 12 PTB7 SCL1 EXTAL

15 13 PTB6 SDA1 XTAL

16 — PTH3

17 — PTH2

18 14 PTH1

19 15 PTH0

20 16 PTE6 RGPIO6

21 17 PTE5 RGPIO5

22 18 PTB5 TPM1CH1 SS1

23 19 PTB4 TPM2CH1 MISO1

24 20 PTC3 RGPIO11 TPM3CH3

25 21 PTC2 RGPIO10 TPM3CH2

26 22 PTD7 KBI2P7

27 23 PTD6 KBI2P6

28 24 PTD5 KBI2P5

29 — PTJ7

30 — PTJ6

31 — PTJ5

32 — PTJ4

33 25 PTC1 RGPIO9 TPM3CH1

34 26 PTC0 RGPIO8 TPM3CH0

35 27 PTF7 ADP17

36 28 PTF6 ADP16

37 29 PTF5 ADP15

38 30 PTF4 ADP14

39 31 PTB3 KBI1P7 MOSI1

1

ADP7

40 32 PTB2 KBI1P6 SPSCK1 ADP6

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor 7

Pin Assignments

Table 2. MCF51QE128 Series Pin Assignment by Package and Pin Sharing Priority (continued)

Pin

Number

Lowest ←⎯ Priority ⎯→ Highest

80 64 Port Pin Alt 1 Alt 2 Alt 3 Alt 4

41 33 PTB1 KBI1P5 TxD1 ADP5

42 34 PTB0 KBI1P4 RxD1 ADP4

43 — PTJ3

44 — PTJ2

45 35 PTF3 ADP13

46 36 PTF2 ADP12

47 37 PTA7 TPM2CH2 ADP9

48 38 PTA6 TPM1CH2 ADP8

49 39 PTE4 RGPIO4

50 40 V

51 41 V

DD

SS

52 42 PTF1 ADP11

53 43 PTF0 ADP10

54 — PTJ1

55 — PTJ0

56 44 PTD4 KBI2P4

57 45 PTD3 KBI2P3 SS2

58 46 PTD2 KBI2P2 MISO2

59 47 PTA3 KBI1P3 SCL1

2

ADP3

60 48 PTA2 KBI1P2 SDA1 ADP2

61 49 PTA1 KBI1P1 TPM2CH0 ADP1 ACMP1-

62 50 PTA0 KBI1P0 TPM1CH0 ADP0 ACMP1+

63 51 PTC7 RGPIO15 TxD2 ACMP2-

64 52 PTC6 RGPIO14 RxD2 ACMP2+

65 — PTG7 ADP23

66 — PTG6 ADP22

67 — PTG5 ADP21

68 — PTG4 ADP20

69 53 PTE3 RGPIO3 SS1

70 54 PTE2 RGPIO2 MISO1

71 55 PTG3 ADP19

72 56 PTG2 ADP18

73 57 PTG1

74 58 PTG0

75 59 PTE1 RGPIO1 MOSI1

76 60 PTE0 RGPIO0 TPM2CLK SPSCK1

77 61 PTC5 RGPIO13 TPM3CH5 ACMP2O

78 62 PTC4 RGPIO12 TPM3CH4 RSTO

79 63 PTA5 IRQ TPM1CLK RESET

80 64 PTA4

3

ACMP1O BKGD MS

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor8

Electrical Characteristics

1

SPI1 pins (SS1, MISO1, MOSI1, and SPSCK2) can be repositioned using SPI1PS
in SOPT2. Default locations are PTB5, PTB4, PTB3, and PTB2.

2

IIC1 pins (SCL1 and SDA1) can be repositioned using IIC1PS in SOPT2. Default
locations are PTA3 and PTA2, respectively.

3

The PTA4/ACMP1O/BKGD/MS is limited to output only for the port I/O function.

3 Electrical Characteristics

3.1 Introduction

This section contains electrical and timing specifications for the MCF51QE128 series of microcontrollers available at the time
of publication.

3.2 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:

Table 3. Parameter Classifications

Those parameters are guaranteed during production testing on each individual device.

P

Those parameters are achieved by the design characterization by measuring a statistically relevant sample

C

size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this

T

category.

Those parameters are derived mainly from simulations.

D

NOTE

The classification is shown in the column labeled “C” in the parameter tables where
appropriate.

3.3 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V

or VDD) or the programmable pull-up resistor associated with the pin is enabled.

SS

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor 9

Electrical Characteristics

Table 4. Absolute Maximum Ratings

Rating Symbol Value Unit

Supply voltage V

Maximum current into V

DD

Digital input voltage V

Instantaneous maximum current

Single pin limit (applies to all port pins)

1, 2, 3

Storage temperature range T

1

Input must be current limited to the value specified. To determine the value of the required

DD

I

DD

In

I

D

stg

–0.3 to +3.8 V

120 mA

–0.3 to VDD+0.3 V

± 25 mA

–55 to 150 °C

current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.

2

All functional non-supply pins are internally clamped to VSS and VDD.

3

Power supply must maintain regulation within operating V

range during instantaneous and

DD

operating maximum current conditions. If positive injection current (VIn > VDD) is greater than

, the injection current may flow out of VDD and could result in external power supply going

I

DD

out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).

3.4 Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take P
the difference between actual pin voltage and V

or VDD and multiply by the pin current for each I/O pin. Except in cases of

SS

unusually high pin current (heavy loads), the difference between pin voltage and V

Table 5. Thermal Characteristics

into account in power calculations, determine

I/O

or VDD will be very small.

SS

Rating Symbol Value Unit

Operating temperature range
(packaged)

Maximum junction temperature T

Thermal resistance

Single-layer board

64-pin LQFP

80-pin LQFP 60

Thermal resistance

Four-layer board

64-pin LQFP

80-pin LQFP 47

1

Depending on packaging.

The average chip-junction temperature (T

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

T

A

JM

θ

JA

θ

JA

) in °C can be obtained from:

J

TL to T

H

(–40 to 85 or 0 to 70)

95 °C

69

50

°C

1

°C/W

°C/W

Freescale Semiconductor10

where:

= Ambient temperature, °C

T

A

θ

= Package thermal resistance, junction-to-ambient, °C/W

JA

P

= P

D

P

int

P

I/O

For most applications, P

+ P

int

I/O

= IDD × VDD, Watts — chip internal power

= Power dissipation on input and output pins — user determined

<< P

I/O

and can be neglected. An approximate relationship between PD and TJ (if P

int

is:

Solving Equation 1 and Equation 2 for K gives:

Electrical Characteristics

TJ = TA + (PD × θJA) Eqn. 1

is neglected)

I/O

P

= K ÷ (TJ + 273°C) Eqn. 2

D

K = P

× (TA + 273°C) + θJA × (PD)

D

where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P
for a known T
for any value of T

. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively

A

.

A

2

(at equilibrium)

D

Eqn. 3

3.5 ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.

All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.

Table 6. ESD and Latch-up Test Conditions

Model Description Symbol Value Unit

Series resistance R1 1500 Ω

Human

Body

Storage capacitance C 100 pF

Number of pulses per pin — 3

Series resistance R1 0 Ω

Machine

Latch-up

Freescale Semiconductor 11

Storage capacitance C 200 pF

Number of pulses per pin — 3

Minimum input voltage limit – 2.5 V

Maximum input voltage limit 7.5 V

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Electrical Characteristics

Table 7. ESD and Latch-Up Protection Characteristics

No. Rating

1 Human body model (HBM) V

2 Machine model (MM) V

3 Charge device model (CDM) V

4 Latch-up current at T

1

Parameter is achieved by design characterization on a small sample size from typical devices

1

= 85°CI

A

Symbol Min Max Unit

HBM

MM

CDM

LAT

± 2000 — V

± 200 — V

± 500 — V

± 100 — mA

under typical conditions unless otherwise noted.

3.6 DC Characteristics

This section includes information about power supply requirements and I/O pin characteristics.

Table 8. DC Characteristics

Num C Characteristic Symbol Condition Min Typ

1 Operating Voltage 1.8 3.6 V

Output high

C

voltage

P All I/O pins,

2

T 2.3 V, I

C1.8V, I

3D

4

Output high
current

Output low

C

voltage

P All I/O pins,

T 2.3 V, I

C 1.8 V, I

Output low

D

current

All I/O pins,

low-drive strength

high-drive strength

Max total I

OH

for all

ports

All I/O pins,

low-drive strength

high-drive strength

Max total I

OL

for all

ports

V

I

OHT

V

I

OLT

OH

OL

1.8 V, I

2.7 V, I

1.8 V, I

2.7 V, I

= –2 mA VDD – 0.5 — —

Load

= –10 mA VDD – 0.5 — —

Load

= –6 mA VDD – 0.5 — —

Load

= –3 mA VDD – 0.5 — —

Load

——100mA

= 2 mA — — 0.5

Load

= 10 mA — — 0.5

Load

= 6 mA — — 0.5

Load

= 3 mA — — 0.5

Load

——100mA5

1

Max Unit

V

V

P Input high

6

voltage

CV

P Input low voltage all digital inputs

7

CV

8 C Input hysteresis all digital inputs V

9P

10 P

Input leakage
current

Hi-Z (off-state)
leakage current

all digital inputs

all input only pins

(Per pin)

all input/output

(per pin)

V

IH

> 1.8 V 0.85 x V

DD

VDD > 2.7 V — — 0.35 x V

V

VDD > 2.7 V 0.70 x V

IL

hys

|I

In|

|I

OZ|

VIn = VDD or V

>1.8 V — — 0.30 x V

DD

0.06 x V

SS

V

= V

or V

In

DD

SS

—0.1 1μA

—0.1 1μA

——

DD

——

DD

DD

DD

——mV

DD

Pull-up resistors all digital inputs, when

11 P

enabled

R

PU

17.5 — 52.5 kΩ

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor12

V

Table 8. DC Characteristics (continued)

PULL-UP RESISTOR TYPICALS

V

DD

(V)

PULL-UP RESISTOR (kΩ)

20

25

30

35

40

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

25°C

85°C

–40°C

PULL-DOWN RESISTOR TYPICALS

V

DD

(V)

PULL-DOWN RESISTANCE (k

Ω

)

20

25

30

35

40

1.8 2.3 2.8 3.3

25°C

85°C

–40°C

3.6

Electrical Characteristics

2.1

2.19

1.82

1.90

2.46

2.46

2.1

2.19

1

Max Unit

2.2

2.27

1.91

1.99

2.56

2.56

2.2

2.27

Num C Characteristic Symbol Condition Min Typ

Single pin limit

I

V

IC

< VSS, V

IN

IN

> V

12 D

DC injection

2, 3, 4

current

Total MCU limit, includes

sum of all stressed pins

13 C Input Capacitance, all pins C

14 C RAM retention voltage V

15 C POR re-arm voltage

5

16 D POR re-arm time t

Low-voltage detection threshold —

P

17

18 P

19 P

20 P

high range

Low-voltage detection threshold —
low range

Low-voltage warning threshold —
high range

Low-voltage warning threshold —
low range

21 P Low-voltage inhibit reset/recover hysteresis V

22 P Bandgap Voltage Reference

1

Typical values are measured at 25°C. Characterized, not tested

2

All functional non-supply pins are internally clamped to VSS and VDD.

3

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate

6

V

V

V

V

V

V

In

RAM

POR

POR

LVD H

LVD L

LVW H

LVW L

hys

BG

VDD falling

VDD rising

VDD falling

rising

V

DD

VDD falling

VDD rising

VDD falling

VDD rising

–0.2 — 0.2 mA

DD

–5 — 5 mA

—— 8pF

—0.61.0V

0.9 1.4 2.0 V

10 — — μs

2.08

2.16

1.80

1.88

2.36

2.36

2.08

2.16

—80—mV

1.19 1.20 1.21 V

resistance values for positive and negative clamp voltages, then use the larger of the two values.

4

Power supply must maintain regulation within operating V

range during instantaneous and operating maximum current

DD

conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if
clock rate is very low (which would reduce overall power consumption).

5

Maximum is highest voltage that POR is guaranteed.

6

Factory trimmed at VDD = 3.0 V, Temp = 25°C

V

V

V

V

Figure 4. Pull-up and Pull-down Typical Resistor Values

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor 13

Electrical Characteristics

TYPICAL VOL VS IOL AT V

DD

= 3.0 V

I

OL

(mA)

V

OL

(V)

0

0.2

0.4

0.6

0.8

1

1.2

0 5 10 15 20

TYPICAL VOL VS V

DD

VDD (V)

V

OL

(V)

0

0.05

0.1

0.15

0.2

1234

25°C

85°C

–40°C

25°C,

I

OL

= 2 mA

85°C,

I

OL

= 2 mA

–40°C,

I

OL

= 2 mA

TYPICAL VOL VS IOL AT V

DD

= 3.0 V

I

OL

(mA)

V

OL

(V)

0

0.2

0.4

0.6

0.8

1

0102030

TYPICAL VOL VS V

DD

VDD (V)

V

OL

(V)

0

0.1

0.2

0.3

0.4

1234

IOL = 6 mA

I

OL

= 3 mA

I

OL

= 10 mA

25°C

85°C

–40°C

25°C

85°C

–40°C

TYPICAL V

DD

– VOH VS IOH AT V

DD

= 3.0 V

I

OH

(mA))

0

0.2

0.4

0.6

0.8

1

1.2

–20–15–10–50

TYPICAL V

DD

– VOH VS VDD AT SPEC I

OH

VDD (V)

V

DD

– V

OH

(V)

0

0.05

0.1

0.15

0.2

0.25

1234

V

DD

– V

OH

(V)

25°C

85°C

–40°C

25°C,

I

OH

= 2 mA

85°C,

I

OH

= 2 mA

–40°C,

I

OH

= 2 mA

Figure 5. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)

Figure 6. Typical Low-Side Driver (Sink) Characteristics

Figure 7. Typical High-Side (Source) Characteristics

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

— High Drive (PTxDSn = 1)

— Low Drive (PTxDSn = 0)

Freescale Semiconductor14

Figure 8. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)

TYPICAL V

DD

– VOH VS IOH AT V

DD

= 3.0 V

I

OH

(mA)

0

0.2

0.4

0.6

0.8

–30–25–20–15–10–50

TYPICAL VDD – VOH VS V

DD

AT SPEC I

OH

VDD (V)

V

DD

– V

OH

(V)

0

0.1

0.2

0.3

0.4

1234

I

OH

= –10 mA

I

OH

= –6 mA

I

OH

= –3 mA

V

DD

– V

OH

(V)

25°C

85°C

–40°C

25°C

85°C

–40°C

3.7 Supply Current Characteristics

This section includes information about power supply current in various operating modes.

Table 9. Supply Current Characteristics

Electrical Characteristics

Num C Parameter Symbol

P Run supply current

FEI mode, all modules on

T 20 MHz 28.0 TBD

1

T 8 MHz 13.2 TBD

RI

DD

Bus

Freq

25.165 MHz

V

DD

(V)

3

Typ

1

33.4 TBD

Max Unit

mA –40 to 85°C

Tem p

(°C)

T1 MHz2.4TBD

C Run supply current

FEI mode, all modules off

T 20 MHz 22.9 TBD

2

RI

T8 MHz11.3TBD

DD

25.165 MHz

3

27.4 TBD

mA –40 to 85°C

T1 MHz2.0TBD

Run supply current

T

3

LPS=0, all modules off

RI

DD

T

Run supply current

4T

LPS=1, all modules off, running from

RI

DD

Flash

C Wait mode supply current

FEI mode, all modules off

T 20 MHz 4570 TBD

5

T8 MHz2000TBD

WI

DD

16 kHz

FBILP

16 kHz

FBELP

16 kHz

FBELP

25.165 MHz

203 TBD

3

154 TBD

350

5740 TBD

3

μA –40 to 85°C

TBD

0 to 70°C

μA

TBD –40 to 85°C

μA –-40 to 85°C

T 1 MHz 730 TBD

6

P TBD –40 to 85°C

Stop3 mode supply current

7

No clocks active

P TBD –40 to 85°C

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor 15

S2I

DD

S3I

DD

n/a 3 350

n/a 3 520

Stop2 mode supply current

TBD

TBD

nA

nA

0 to 70°C

0 to 70°C

Electrical Characteristics

Table 9. Supply Current Characteristics (continued)

Num C Parameter Symbol

8T

EREFSTEN=1 32 kHz

Bus

Freq

V

DD

(V)

9 T IREFSTEN=1 32 kHz 70

10 T TPM PWM 100 Hz 12

11 T SCI, SPI, or IIC 300 bps 15

Low power

mode adders:

3

12 T RTC using LPO 1 kHz 200

13 T

RTC using

ICSERCLK

32 kHz 1

14 T LVD n/a 100

15 T ACMP n/a 20

1

Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.

Typ

500

1

Max Unit

TBD

nA

TBD –40 to 85°C

TBD

μA

TBD –40 to 85°C

TBD

μA

TBD –40 to 85°C

TBD

μA

TBD –40 to 85°C

TBD

nA

TBD –40 to 85°C

TBD

μA

TBD –40 to 85°C

TBD

μA

TBD –40 to 85°C

TBD

μA

TBD –40 to 85°C

Tem p

(°C)

0 to 70°C

0 to 70°C

0 to 70°C

0 to 70°C

0 to 70°C

0 to 70°C

0 to 70°C

0 to 70°C

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor16

Electrical Characteristics

TBD

Figure 9. Typical Run IDD for FBE and FEI, IDD vs. VDD

(ACMP and ADC off, All Other Modules Enabled)

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor 17

Electrical Characteristics

3.8 External Oscillator (XOSC) Characteristics

Reference Figure 10 and Figure 11 for crystal or resonator circuits.

Table 10. XOSC and ICS Specifications (Temperature Range = –40 to 85°C Ambient)

Num C Characteristic Symbol Min Typ

1

Max Unit

Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)

1C

Load capacitors

2D

Feedback resistor

3D

Series resistor —

4D

Crystal start-up time

5C

Low range (RANGE = 0)
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)

Low range (RANGE=0), low power (HGO=0)
Other oscillator settings

Low range, low power (RANGE=0, HGO=0)

2

Low range, High Gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)

Low range, low power (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)

≥ 8 MHz
4 MHz
1 MHz

4

Low range, low power
Low range, high power
High range, low power
High range, high power

lo

f

hi

f

hi

C

1,C2

R

F

2

R

S

t

CSTL

t

CSTH

32

1
1

—
—
—

—
—
—

—
—
—

—
—
—
—

—
—
—

See Note

See Note3

—
10

1

—

0

100

0
0
0

200
400

5

15

38.4
16

8

2

—
—
—

—
—
—

0
10
20

—
—
—
—

f

Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)

6D

FEE mode

f

FBE or FBELP mode

1

Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.

2

Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0.

3

See crystal or resonator manufacturer’s recommendation.

4

Proper PC board layout procedures must be followed to achieve specifications.

extal

0.031250—
—

50.33

50.33

kHz
MHz
MHz

MΩ

kΩ

ms

MHz
MHz

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor18

Electrical Characteristics

XOSC

EXTAL XTAL

Crystal or Resonator

R

S

C

2

R

F

C

1

XOSC

EXTAL XTAL

Crystal or Resonator

Figure 10. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain

Figure 11. Typical Crystal or Resonator Circuit: Low Range/Low Gain

3.9 Internal Clock Source (ICS) Characteristics

Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)

Num C Characteristic Symbol Min Typ

1P

2P

3T

4

5

6C

7C

Average internal reference frequency — factory trimmed

at V

= 3.6 V and temperature = 25°C

DD

Internal reference frequency — user trimmed f

Internal reference start-up time t

P

DCO output frequency range —

trimmed

2

P High range (DRS=10) 48 — 60

P

DCO output frequency

Reference = 32768 Hz

P Mid range (DRS=01) — 39.85 —

P

and

DMX32 = 1

Resolution of trimmed DCO output frequency at fixed voltage and
temperature (using FTRIM)

Resolution of trimmed DCO output frequency at fixed voltage and
temperature (not using FTRIM)

1

Max Unit

f

int_ft

int_ut

IRST

Low range (DRS=00)

f

dco_u

2

Low range (DRS=00)

f

dco_DMX32

High range (DRS=10)

Δf

dco_res_t

Δf

dco_res_t

— 32.768 — kHz

31.25 — 39.06 kHz

—60100μs

16 — 20

MHzC Mid range (DRS=01) 32 — 40

— 19.92 —

MHz

59.77

—

— ± 0.1 ± 0.2

— ± 0.2 ± 0.4

—

%f

%f

dco

dco

Freescale Semiconductor 19

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Electrical Characteristics

TBD

Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)

+ 0.5

-1.0

1

Max Unit

± 2

%f

%f

%f

Num C Characteristic Symbol Min Typ

8C

9C

10 C

11 C

1

Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.

2

The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.

3

This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing

Total deviation of trimmed DCO output frequency over voltage
and temperature

Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0

FLL acquisition time

3

°C to 70 °C

Long term jitter of DCO output clock (averaged over 2-ms

interval)

4

Δf

dco_t

Δf

dco_t

t

Acquire

C

Jitter

—

— ± 0.5 ± 1

—— 1ms

— 0.02 0.2

from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.

4

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

Bus

.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V

and VSS and variation in crystal oscillator frequency increase the C

DD

percentage for a

Jitter

given interval.

dco

dco

dco

Figure 12. Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 3.0 V)

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor20

Electrical Characteristics

TBD

Figure 13. Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 25°C)

3.10 AC Characteristics

This section describes timing characteristics for each peripheral system.

3.10.1 Control Timing

Table 12. Control Timing

Num C Rating Symbol Min Typ

Bus frequency (t

1D

2 D Internal low power oscillator period t

3 D External reset pulse width

4 D Reset low drive t

5D

6D

≤ 2.1V

V

DD

> 2.1V

V

DD

BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes

BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes

cyc

= 1/f

Bus

)

2

f

Bus

LPO

t

extrst

rstdrv

t

MSSU

3

t

MSH

dc
dc

700 — 1300 μs

100 — — ns

34 x t

cyc

500 — — ns

100 — — μs

1

—
—

——ns

Max Unit

10

25.165

MHz

IRQ pulse width

7D

Freescale Semiconductor 21

Asynchronous path
Synchronous path

2

4

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

t

ILIH, tIHIL

100

2 x t

cyc

—
—

—
—

ns

Electrical Characteristics

t

extrst

RESET PIN

t

IHIL

KBIPx

t

ILIH

IRQ/KBIPx

Table 12. Control Timing (continued)

—
—

TBD
TBD

1

Max Unit

—
—

—
—

Num C Rating Symbol Min Typ

Keyboard interrupt pulse width

8D

Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)

Asynchronous path
Synchronous path

2

4

5

t

ILIH, tIHIL

, t

t

Rise

Fall

100

2 x t

cyc

—
—

9C

Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)

Slew rate control disabled (PTxSE = 0)

Slew rate control enabled (PTxSE = 1)

10 C

1

Typical values are based on characterization data at V

2

This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not

Stop3 recovery time, from interrupt event to vector fetch t

= 3.0V, 25°C unless otherwise stated.

DD

, t

t

Rise

STPREC

Fall

—
—

TBD
TBD

—
—

—610μs

guaranteed to override reset requests from internal sources.

3

To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
rises above V

4

This is the minimum assertion time in which the interrupt may be recognized. The correct protocol is to assert the interrupt

LVD

.

MSH

after VDD

request until it is explicitly negated by the interrupt service routine.

5

Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.

ns

ns

ns

Figure 14. Reset Timing

Figure 15. IRQ

/KBIPx Timing

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor22

Electrical Characteristics

t

TCLK

t

clkh

t

clkl

TCLK

t

ICPW

TPMCHn

t

ICPW

TPMCHn

3.10.2 TPM Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.

Table 13. TPM Input Timing

No. C Function Symbol Min Max Unit

1 D External clock frequency f

2 D External clock period t

3 D External clock high time t

4 D External clock low time t

5 D Input capture pulse width t

Figure 16. Timer External Clock

TCLK

TCLK

clkh

clkl

ICPW

0f

4—t

1.5 — t

1.5 — t

1.5 — t

/4 Hz

Bus

cyc

cyc

cyc

cyc

Figure 17. Timer Input Capture Pulse

Freescale Semiconductor 23

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Electrical Characteristics

3.10.3 SPI Timing

Table 14 and Figure 18 through Figure 21 describe the timing requirements for the SPI system.

Table 14. SPI Timi n g

No. C Function Symbol Min Max Unit

Operating frequency

—D

Master
Slave

SPSCK period

1D

Master
Slave

Enable lead time

2D

Master
Slave

Enable lag time

3D

Master
Slave

Clock (SPSCK) high or low time

4D

Master

t

Slave

Data setup time (inputs)

5D

Master
Slave

Data hold time (inputs)

6D

Master
Slave

7 D Slave access time t

8 D Slave MISO disable time t

Data valid (after SPSCK edge)

9D

Master
Slave

Data hold time (outputs)

10 D

Master
Slave

Rise time

11 D

Input
Output

Fall time

12 D

Input
Output

f

op

t

SPSCK

t

Lead

t

Lag

WSPSCK

t

SU

t

HI

a

dis

t

v

t

HO

t

RI

t

RO

t

FI

t

FO

f

/2048

Bus

0

2
4

1/2

1

1/2

1

t

– 30

cyc

t

– 30

cyc

15
15

0

25

—1t

—1t

—
—

0
0

—
—

—
—

f

Bus

f

Bus

2048

—

—
—

—
—

1024 t

—

—
—

—
—

25
25

—
—

t

– 25

cyc

25

t

– 25

cyc

25

/2
/4

cyc

Hz
Hz

t

cyc

t

cyc

t

SPSCK

t

cyc

t

SPSCK

t

cyc

ns
ns

ns
ns

ns
ns

cyc

cyc

ns
ns

ns
ns

ns
ns

ns
ns

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor24

Electrical Characteristics

SPSCK

(OUTPUT)

SPSCK

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

SS

1

(OUTPUT)

MSB IN

2

BIT 6 . . . 1

LSB IN

MSB OUT

2

LSB OUT

BIT 6 . . . 1

(CPOL = 0)

(CPOL = 1)

NOTES:

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

1. SS

output mode (DDS7 = 1, SSOE = 1).

1

2

3

4

5

6

9

10

11

12

4

9

SPSCK

(OUTPUT)

SPSCK

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MSB IN

(2)

BIT 6 . . . 1

LSB IN

MASTER MSB OUT

(2)

MASTER LSB OUT

BIT 6 . . . 1

PORT DATA

(CPOL = 0)

(CPOL = 1)

PORT DATA

SS

(1)

(OUTPUT)

1. SS output mode (DDS7 = 1, SSOE = 1).

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

NOTES:

2

1

12

11

3

4 4

11

12

5

6

9 10

Figure 18. SPI Master Timing (CPHA = 0)

Figure 19. SPI Master Timing (CPHA =1)

Freescale Semiconductor 25

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Electrical Characteristics

SPSCK

(INPUT)

SPSCK

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

SS

(INPUT)

MSB IN

BIT 6 . . . 1

LSB IN

MSB OUT

SLAVE LSB OUT

BIT 6 . . . 1

(CPOL = 0)

(CPOL = 1)

NOTE:

SLAVE

SEE

NOTE

1. Not defined but normally MSB of character just received

1

2

3

4

5

6

7

8

9

10

11

12

4

11

12

10

SPSCK

(INPUT)

SPSCK

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

MSB IN

BIT 6 . . . 1

LSB IN

MSB OUT

SLAVE LSB OUT

BIT 6 . . . 1

SEE

(CPOL = 0)

(CPOL = 1)

SS

(INPUT)

NOTE:

SLAVE

NOTE

1. Not defined but normally LSB of character just received

1

2

3

4

5

6

7

8

9 10

11

12

4

11

12

Figure 20. SPI Slave Timing (CPHA = 0)

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Figure 21. SPI Slave Timing (CPHA = 1)

Freescale Semiconductor26

Electrical Characteristics

3.10.4 Analog Comparator (ACMP) Electricals

C Characteristic Symbol Min Typical Max Unit

Table 15. Analog Comparator Electrical Specifications

D Supply voltage V

P Supply current (active) I

D Analog input voltage V

P Analog input offset voltage V

C Analog comparator hysteresis V

P Analog input leakage current I

C Analog comparator initialization delay t

DD

DDAC

AIN

AIO

H

ALKG

AINIT

VSS – 0.3 — V

3.10.5 ADC Characteristics

C Characteristic Conditions Symb Min Typ

Supply voltage Absolute V

D

Delta to V

D Ground voltage Delta to V

D Ref Voltage High V

D Ref Voltage Low V

D Input Voltage V

Input

C

Capacitance

C Input Resistance R

Analog Source

12 bit mode

Resistance

C

10 bit mode

8 bit mode (all valid f

ADC Conversion

D

Clock Freq.

1

Typical values assume V

High Speed (ADLPC=0) f

Low Power (ADLPC=1) 0.4 — 4.0

DDAD

only and are not tested in production.

2

DC potential difference.

Table 16. 12-bit ADC Operating Conditions

1.8 — 3.6 V

-100 0 +100 mV

-100 0 +100 mV

1.8 V

V

SSAD

V

REFL

—4.55.5

—5 7kΩ

—
—

—
—

0.4 — 8.0

DD

f

ADCK

f

ADCK

f

ADCK

f

ADCK

(VDD-V

(VSS-V

SS

> 4MHz
< 4MHz

> 4MHz
< 4MHz

2

)

DDAD

)2ΔV

SSAD

)——10

ADCK

= 3.0V, Temp = 25°C, f

DDAD

ΔV

DDAD

SSAD

REFH

REFL

ADIN

C

ADIN

ADIN

R

AS

ADCK

=1.0MHz unless otherwise stated. Typical values are for reference

ADCK

1.80 — 3.6 V

—2035μA

DD

20 40 mV

3.0 9.0 15.0 mV

——1.0μA

——1.0μs

1

Max Unit Comment

DDAD

V

SSAD

—V

V

DDAD

V

SSAD

REFH

V

V

V

pF

External to MCU
—
—

2
5

kΩ
—
—

5

10

MHz

V

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor 27

Electrical Characteristics

+

–

+

–

V

AS

R

AS

C

AS

V

ADIN

Z

AS

Pad
leakage
due to
input
protection

Z

ADIN

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

R

ADIN

ADC SAR

ENGINE

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

INPUT PIN

R

ADIN

C

ADIN

INPUT PIN

R

ADIN

INPUT PIN

R

ADIN

Figure 22. ADC Input Impedance Equivalency Diagram

Characteristic Conditions C Symb Min Typ

Supply Current
ADLPC=1
ADLSMP=1
ADCO=1

Supply Current
ADLPC=1
ADLSMP=0
ADCO=1

Supply Current
ADLPC=0
ADLSMP=1
ADCO=1

Supply Current
ADLPC=0
ADLSMP=0
ADCO=1

Supply Current Stop, Reset, Module Off I

ADC
Asynchronous
Clock Source

Table 17. 12-bit ADC Characteristics (V

TI

DDAD

TI

DDAD

TI

DDAD

High Speed (ADLPC=0) P f

Low Power (ADLPC=1) C 1.25 2 3.3

PI

DDAD

DDAD

ADACK

= V

REFH

DDAD

1

— 120 —

— 202 —

— 288 —

—0.532 1

— 0.007 0.8 μA

23.35

, V

REFL

= V

SSAD

)

Max Unit Comment

μA

μA

μA

mA

t

ADACK

MHz

= 1/f

ADACK

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor28

Electrical Characteristics

Table 17. 12-bit ADC Characteristics (V

REFH

= V

DDAD

Characteristic Conditions C Symb Min Typ

Conversion Time
(Including
sample time)

Short Sample (ADLSMP=0) P t

Long Sample (ADLSMP=1) C — 40 —

Sample Time Short Sample (ADLSMP=0) P t

ADC

ADS

— 20 — ADCK

— 3.5 — ADCK

Long Sample (ADLSMP=1) C — 23.5 —

Total Unadjusted
Error

12 bit mode T E

TUE

10 bit mode P — ±1 ±2.5

— ±3.0 — LSB

8 bit mode T — ±0.5 ±1.0

Differential
Non-Linearity

Integral
Non-Linearity

12 bit mode T DNL — ±1.75 — LSB

10 bit mode

8 bit mode

3

3

P—±0.5 ±1.0

T—±0.3 ±0.5

12 bit mode T INL — ±1.5 — LSB

10 bit mode P — ±0.5 ±1.0

8 bit mode T — ±0.3 ±0.5

Zero-Scale Error 12 bit mode T E

ZS

— ±1.5 — LSB

10 bit mode P — ±0.5 ±1.5

, V

= V

REFL

1

Max Unit Comment

) (continued)

SSAD

cycles

cycles

2

2

2

2

See the ADC

chapter in the

MCF51QE128

Reference Manual

for conversion time

variances

Includes

Quantization

V

= V

ADIN

SSAD

8 bit mode T — ±0.5 ±0.5

Full-Scale Error 12 bit mode T E

FS

— ±1.0 — LSB

10 bit mode P — ±0.5 ±1

8 bit mode T — ±0.5 ±0.5

Quantization
Error

12 bit mode D E

Q

—-1 to 0—LSB

10 bit mode — — ±0.5

8 bit mode — — ±0.5

Input Leakage
Error

12 bit mode D E

IL

10 bit mode — ±0.2 ±4

— ±2—LSB2Pad leakage4 * R

8 bit mode — ±0.1 ±1.2

Temp Sensor
Slope

Temp Sensor

-40°C to 25°C D m — 1.646 — mV/°C

25°C to 85°C — 1.769 —

25°CDV

TEMP25

—701.2— mV

Vol tage

1

Typical values assume V

= 3.0V, Temp = 25°C, f

DDAD

=1.0MHz unless otherwise stated. Typical values are for reference

ADCK

only and are not tested in production.

2

1 LSB = (V

3

Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes

4

Based on input pad leakage current. Refer to pad electricals.

REFH

- V

REFL

)/2

N

2

V

= V

ADIN

2

DDAD

AS

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor 29

Electrical Characteristics

3.10.6 Flash Specifications

This section provides details about program/erase times and program-erase endurance for the flash memory.

Program and erase operations do not require any special power sources other than the normal V
information about program/erase operations, see the Memory section of the MCF51QE128 Reference Manual.

Table 18. Flash Characteristics

C Characteristic Symbol Min Typical Max Unit

Supply voltage for program/erase

D

-40°C to 85°CV

D Supply voltage for read operation V

D Internal FCLK frequency

1

D Internal FCLK period (1/FCLK) t

P Longword program time (random location)

P Longword program time (burst mode)

P Page erase time

P Mass erase time

Longword program current

Page erase current

Program/erase endurance

C

TL to TH = –40°C to + 85°C

2

(2)

3

3

4

(2)

(2)

prog/erase

Read

f

FCLK

Fcyc

t

prog

t

Burst

t

Page

t

Mass

R

IDDBP

R

IDDPE

T = 25°C

C Data retention

1

The frequency of this clock is controlled by a software setting.

2

These values are hardware state machine controlled. User code does not need to count cycles. This information supplied

5

t

D_ret

for calculating approximate time to program and erase.

3

The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.0 V, bus frequency = 4.0 MHz.

4

Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on
how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.

5

Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.

1.8 3.6 V

1.8 3.6 V

150 200 kHz

56.67μs

9t

4t

4000 t

20,000 t

—9.7—mA

—7.6—mA

10,000

—

—

100,000

15 100 — years

supply. For more detailed

DD

—
—

Fcyc

Fcyc

Fcyc

Fcyc

cycles

3.11 EMC Performance

Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor30

Electrical Characteristics

3.11.1 Radiated Emissions

Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East).

The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported
emissions levels.

Table 19. Radiated Emissions, Electric Field

1

Parameter Symbol Conditions Frequency f

OSC/fBUS

Level

(Max)

Unit

Radiated emissions,
electric field

1

Data based on qualification test results.

V

RE_TEM

VDD = TBD

= +25oC

T

A

package type

TBD

0.15 – 50 MHz

50 – 150 MHz TBD

150 – 500 MHz TBD

500 – 1000 MHz TBD

IEC Level TBD —

SAE Level TBD —

TBD crystal

TBD bus

TBD

dBμV

3.11.2 Conducted Transient Susceptibility

Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The
measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC
test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient
susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC
61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is
greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 20.

Table 20. Conducted Susceptibility, EFT/B

Parameter Symbol Conditions

VDD = TBD
Conducted susceptibility, electrical
fast transient/burst (EFT/B)

1

Data based on qualification test results. Not tested in production.

V

CS_EFT

T

A

package type

= +25oC

TBD

f

OSC/fBUS

TBD crystal

TBD bus

Result

A TBD

B TBD

C TBD

D TBD

Amplitude

(Min)

1

Unit

kV

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor 31

Ordering Information

The susceptibility performance classification is described in Table 21.

Table 21. Susceptibility Performance Classification

Result Performance Criteria

A No failure The MCU performs as designed during and after exposure.

B

C Soft failure

D Hard failure

E Damage

Self-recovering

failure

The MCU does not perform as designed during exposure. The MCU returns
automatically to normal operation after exposure is removed.

The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the RESET pin is asserted.

The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the power to the MCU is cycled.

The MCU does not perform as designed during and after exposure. The MCU cannot
be returned to proper operation due to physical damage or other permanent
performance degradation.

4 Ordering Information

This section contains ordering information for MCF51QE128 and MCF51QE64 devices.

Freescale Part Number

MCF51QE128CLK 128K 8K -40 to +85 80 LQFP

MCF51QE128CLH 128K 8K -40 to +85 64 LQFP

MCF51QE64CLH 64K 8K -40 to +85 64 LQFP

MCF51QE32CLH 32K 8K -40 to +85 64 LQFP

MCF51QE32LH 32K 8K 0 to +70 64 LQFP

1

See the reference manual, MCF51QE128RM, for a complete description of modules included on each device.

2

See Table 23 for package information.

1

Table 22. Ordering Information

Memory

Temperature range (°C) Package

Flash RAM

2

5 Package Information

The below table details the various packages available.

Table 23. Package Descriptions

Pin Count Package Type Abbreviation Designator Case No. Document No.

80 Low Quad Flat Package LQFP LK 917A 98ASS23237W

64 Low Quad Flat Package LQFP LH 840F 98ASS23234W

5.1 Mechanical Drawings

The following pages are mechanical drawings for the packages described in Table 23. For the latest available drawings please
visit our web site (http://www.freescale.com) and enter the package’s document number into the keyword search box.

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor32

Package Information

1

20

21

40

41

60

6180

VIEW AA

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.

4. DATUMS –L–, –M– AND –N– TO BE DETERMINED
AT DATUM PLANE –H–.

5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –T–.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.

7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.460
(0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 (0.003).

AB

VIEW Y

(K)

(Z)

(W)

VIEW AA

DIMAMIN MAX MIN MAX

INCHES

14.00 BSC 0.551 BSC

MILLIMETERS

A1 7.00 BSC 0.276 BSC

B 14.00 BSC 0.551 BSC

B1 7.00 BSC 0.276 BSC

C ––– 1.60 ––– 0.063
C1 0.04 0.24 0.002 0.009
C2 1.30 1.50 0.051 0.059

D 0.22 0.38 0.009 0.015

E 0.40 0.75 0.016 0.030

F 0.17 0.33 0.007 0.013

G 0.65 BSC 0.026 BSC

J 0.09 0.27 0.004 0.011

K 0.50 REF 0.020 REF

P 0.325 BSC 0.013 REF
R1 0.10 0.20 0.004 0.008

S 16.00 BSC 0.630 BSC
S1 8.00 BSC 0.315 BSC

U 0.09 0.16 0.004 0.006

V 16.00 BSC 0.630 BSC
V1 8.00 BSC 0.315 BSC

W 0.20 REF 0.008 REF

Z 1.00 REF 0.039 REF

0
01 ––– –––
02

C2

C1

C

L

0 10
0
9 14

0 10
0
9 14

L–M0.20 (0.008) H N

4X

3X

VIEW Y

–L–

L–M0.20 (0.008) T N

–M–

B

V

V1

B1

–N–

S1

A1

S

A

4X 20 TIPS

SEATING

0.10 (0.004) T

–H–

PLANE

–T–

8X

C

2

GAGE

0.25 (0.010)

PLANE

2X R

R1

E

1

S

0.05 (0.002)

AB

–X–

X= L, M, N

P

G

PLATING

BASE

METAL

J

U

F

D

SECTION AB–AB

S

L–M

M

0.13 (0.005) N

S

T

ROTATED 90 CLOCKWISE

CASE 917A-02

ISSUE C

DATE 09/21/95

Figure 23. 80-pin LQFP Package Drawing (Case 917A, Doc #98ASS23237W)

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor 33

Package Information

Figure 24. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 1 of 3

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor34

Package Information

Figure 25. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 2 of 3

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor 35

Package Information

Figure 26. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 3 of 3

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor36

Product Documentation

6 Product Documentation

Find the most current versions of all documents at: http://www.freescale.com

Reference Manual (MCF51QE128RM)

Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.

7 Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your
printed copy may be an earlier revision. To verify you have the latest information available, refer to:

http://www.freescale.com

The following revision history table summarizes changes contained in this document.

Table 24. Revision History

Revision Date Description of Changes

2 22 May 2007 Initial Advance Information release.

3 25 Jun 2007

4 17 Sep 2007

Ta bl e 8 : Changed Condition entires in specs #6 (V

> 2.7V and VDD≤ 1.8V to VDD>1.8V.

V

DD

Ta bl e 8 : Changed VDD rising and VDD falling min/typ/max specs in row #19 (Low-voltage

warning threshold—high range) from 2.35, 2.40, and 2.50 to 2.36, 2.46, and 2.56
respectively.

Added information about the MCF51QE32 device.

Changed the SRAM size for the MCF51QE64 device (was 4 Kbytes, is 8 Kbytes).
Corrected the number of ADC channels for the MCF51QE64 device (was 22, is 20).
Corrected the number of ADC channels for the 64-pin package of the MCF51QE64 device (was

22, is 20).

) and #7 (VIL) from VDD≥ 1.8V to

IH

MCF51QE128 Series Advance Information Data Sheet, Rev. 4

Freescale Semiconductor 37

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

[e-mail]

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Freescale Semiconductor
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1300 N. Alma School Road
Chandler, Arizona 85224
[phone] or [phone]
[e-mail]

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Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
[phone] (English)
[phone] (English)
[phone] (German)
[phone] (French)
[e-mail]

Japan:

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Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
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Japan
0120 191014 or [phone]
[e-mail]

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Document Number: MCF51QE128

Rev. 4
09/2007