Freescale MCF51QE128, MCF51QE64, MCF51QE32 DATA SHEET
Freescale Semiconductor
80-LQFP
Case 917A
14 mm
2
64-LQFP
Case 840F
10 mm
2
Data Sheet: Advance Information
Document Number: MCF51QE128
Rev. 4, 09/2007
MCF51QE128 Series
Covers: MCF51QE128, MCF51QE64, MCF51QE32
• 32-Bit Version 1 ColdFire® Central Processor Unit (CPU)
– Up to 50.33-MHz ColdFire CPU from 3.6V to 2.1V, and
20-MHz CPU at 2.1V to 1.8V across temperature range
of -40°C to 85°C
– Provides 0.94 Dhrystone 2.1 MIPS per MHz
performance when running from internal RAM
(0.76 DMIPS/MHz from flash)
– Implements Instruction Set Revision C (ISA_C)
– Support for up to 30 peripheral interrupt requests and
seven software interrupts
•On-Chip Memory
– Flash read/program/erase over full operating voltage
and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to
RAM and flash contents
• Power-Saving Modes
– Two low power stop modes; reduced power wait mode
– Peripheral clock enable register can disable clocks to
unused modules, reducing currents; allows clocks to
remain enabled to specific peripherals in stop3 mode
– Very low power external oscillator can be used in stop3
mode to provide accurate clock to active peripherals
– Very low power real time counter for use in run, wait,
and stop modes with internal and external clock sources
–6 μs typical wake up time from stop modes
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator;
Crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 16 MHz
– Internal Clock Source (ICS) — FLL controlled by
internal or external reference; precision trimming of
internal reference allows 0.2% resolution and 2%
deviation; supports CPU freq. from 2 to 50.33 MHz
• System Protection
– Watchdog computer operating properly (COP) reset
with option to run from dedicated 1-kHz internal clock
source or bus clock
– Low-voltage detection with reset or interrupt; selectable
trip points
– Illegal opcode and illegal address detection with
programmable reset or exception response
– Flash block protection
MCF51QE128
• Development Support
– Single-wire background debug interface
– 4 PC plus 2 address (optional data) breakpoint registers
with programmable 1- or 2-level trigger response
– 64-entry processor status and debug data trace buffer
with programmable start/stop conditions
• ADC — 24-channel, 12-bit resolution; 2.5 μs conversion
time; automatic compare function; 1.7 mV/°C temperature
sensor; internal bandgap reference channel; operation in
stop3; fully functional from 3.6V to 1.8V
• ACMPx — Two analog comparators with selectable
interrupt on rising, falling, or either edge of comparator
output; compare option to fixed internal bandgap reference
voltage; outputs can be optionally routed to TPM module;
operation in stop3
• SCIx — Two SCIs with full duplex non-return to zero
(NRZ); LIN master extended break generation; LIN slave
extended break detection; wake up on active edge
• SPIx— Two serial peripheral interfaces with Full-duplex or
single-wire bidirectional; Double-buffered transmit and
receive; MSB-first or LSB-first shifting
• IICx — Two IICs with; Up to 100 kbps with maximum bus
loading; Multi-master operation; Programmable slave
address; Interrupt driven byte-by-byte data transfer;
supports broadcast mode and 10 bit addressing
• TPMx — One 6-channel and two 3-channel; Selectable
input capture, output compare, or buffered edge- or
center-aligned PWMs on each channel
• RTC — 8-bit modulus counter with binary or decimal
based prescaler; External clock source for precise time
base, time-of-day, calendar or task scheduling functions;
Free running on-chip low power oscillator (1 kHz) for
cyclic wake-up without external components
• Input/Output
– 70 GPIOs and 1 input-only and 1 output-only pin
– 16 KBI interrupts with selectable polarity
– Hysteresis and configurable pull-up device on all input
pins; Configurable slew rate and drive strength on all
output pins.
– SET/CLR registers on 16 pins (PTC and PTE)
– 16 bits of Rapid GPIO connected to the CPU’s
high-speed local bus with set, clear, and toggle
functionality
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Table of Contents
1 MCF51QE128 Series Comparison . . . . . . . . . . . . . . . . . . . . . .4
2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .9
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .9
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .10
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .11
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15
3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .18
3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .19
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.10.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . . 23
3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10.4 Analog Comparator (ACMP) Electricals . . . . . . 27
3.10.5 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . 27
3.10.6 Flash Specifications . . . . . . . . . . . . . . . . . . . . . 30
3.11 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.11.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . 31
3.11.2 Conducted Transient Susceptibility . . . . . . . . . 31
4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 32
6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
MCF51QE128 Series Advance Information Data Sheet, Rev. 4
Freescale Semiconductor2
TPM2CH2-0
TPM1CH2-0
ANALOG COMPARATOR
(ACMP1)
ACMP1O
ACMP1-
ACMP1+
V
SS
V
DD
IIC MODULE (IIC1)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
USER FLASH
USER RAM
128K / 64K
V1 ColdFire CORE
CPU
BDC / Debug
6-CHANNEL TIMER/PWM
MODULE (TPM3)
SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
VOLTAGE
REGULATOR
COP
-
LVD
OSCILLATOR (XOSC)
RESET
V
REFL
V
REFH
8K / 6K / 4K
BKGD/MS
INTERFACE (SCI1)
SERIAL COMMUNICATIONS
MISO1
SS1
SPSCK1
3-CHANNEL TIMER/PWM
MODULE (TPM2)
REAL TIME COUNTER (RTC)
Rapid GPIO
IRQ
PTA3/KBI1P3/SCL1/ADP3
PTA4/ACMP1O/BKGD/MS
PTA5/IRQ/TPM1CLK/RESET
PTA2/KBI1P2/SDA1/ADP2
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PORT A
PTA6/TPM1CH2/ADP8
PTA7/TPM2CH2/ADP9
MOSI1
PTB3/KBI1P7/MOSI1/ADP7
PTB4/TPM2CH1/MISO1
PTB5/TPM1CH1/SS1
PTB2/KBI1P6/SPSCK1/ADP6
PTB1/KBI1P5/TxD1/ADP5
PTB0/KBI1P4/RxD1/ADP4
PORT B
PTB6/SDA1/XTAL
PTB7/SCL1/EXTAL
PTC3/RGPIO11/TPM3CH3
PTC4/RGPIO12/TPM3CH4/RSTO
PTC5/RGPIO13/TPM3CH5/ACMP2O
PTC2/RGPIO10/TPM3CH2
PTC1/RGPIO9/TPM3CH1
PTC0/RGPIO8/TPM3CH0
PORT C
PTC6/RGPIO14/RxD2/ACMP2+
PTC7/RGPIO15/TxD2/ACMP2-
PTD3/KBI2P3/SS2
PTD4/KBI2P4
PTD5/KBI2P5
PTD2/KBI2P2/MISO2
PTD1/KBI2P1/MOSI2
PTD0/KBI2P0/SPSCK2
PORT D
PTD6/KBI2P6
PTD7/KBI2P7
PTE3/RGPIO3/SS1
PTE4/RGPIO4
PTE5/RGPIO5
PTE2/RGPIO2/MISO1
PTE1/RGPIO1/MOSI1
TPM2CLK
PORT E
PTE6/RGPIO6
PTE0/RGPIO0/TPM2CLK/SPSCK1
PTF3/ADP13
PTF4/ADP14
PTF5/ADP15
PTF2/ADP12
PTF1/ADP11
PTF0/ADP10
PORT F
PTF6/ADP16
PTF7/ADP17
PTG1
PTG2/ADP18
PTG3/ADP19
PORT G
PTG4/ADP20
PTG5/ADP21
PTG0
V
SS
V
DD
V
SSA
V
DDA
IP Bus Bridge
INTC
ANALOG COMPARATOR
(ACMP2)
INTERFACE (SCI2)
SERIAL COMMUNICATIONS
TPM3CH5-0
PTG6/ADP22
PTG7/ADP23
SOURCE (ICS)
INTERNAL CLOCK
PORT J
PORT H
PTJ1
PTJ2
PTJ3
PTJ4
PTJ5
PTJ0
PTJ6
PTJ7
PTH1
PTH2
PTH3
PTH4
PTH5
PTH0
PTH6/SCL2
PTH7/SDA2
IIC MODULE (IIC2)
ANALOG-TO-DIGITAL
CONVERTER (ADC)
24-CHANNEL,12-BIT
3-CHANNEL TIMER/PWM
MODULE (TPM1)
SDA2
SCL2
SERIAL PERIPHERAL
INTERFACE MODULE (SPI2)
MISO2
SS2
SPSCK2
MOSI2
EXTAL
XTAL
16
SDA1
SCL1
ACMP2-
ACMP2+
ACMP2O
RxD1
TxD1
RxD2
TxD2
TPM3CLK
3
TPM1CLK
PTE7/RGPIO7/TPM3CLK
Figure 1. MCF51QE128 Series Block Diagram
Freescale Semiconductor 3
MCF51QE128 Series Advance Information Data Sheet, Rev. 4
MCF51QE128 Series Comparison
1 MCF51QE128 Series Comparison
The following table compares the various device derivatives available within the MCF51QE128 series.
Table 1. MCF51QE128 Series Features by MCU and Package
Feature MCF51QE128 MCF51QE64 MCF51QE32
Flash size (bytes) 131072 65536 32768
RAM size (bytes) 8192 8192 8192
Pin quantity 80 64 64 64
Version 1 ColdFire core yes yes
ACMP1 yes yes
ACMP2 yes yes
ADC channels 24 20 20 20
DBG yes
ICS yes
IIC1 yes
IIC2 yes
KBI 16
Port I/O
Rapid GPIO yes
RTC yes
SCI1 yes
SCI2 yes
SPI1 yes
SPI2 yes
External IRQ yes
TPM1 channels 3
TPM2 channels 3
TPM3 channels 6
XOSC yes
1
2
1, 2
Port I/O count does not include the input-only PTA5/IRQ/TPM1CLK/RESET or the
output-only PTA4/ACMP1O/BKGD/MS.
16 bits associated with Ports C and E are shadowed with ColdFire Rapid GPIO
module.
70 54 54 54
MCF51QE128 Series Advance Information Data Sheet, Rev. 4
Freescale Semiconductor4
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80797877767574737271706968676665646362
61
21222324252627282930313233343536373839
40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
V
REFH
V
SSAD
V
DD
V
REFL
V
DDAD
V
SS
PTB7/SCL1/EXTAL
PTH7/SDA2
PTD0/KBI2P0/SPSCK2
PTD1/KBI2P1/MOSI2
PTE6/RGPIO6
PTB6/SDA1/XTAL
PTH6/SCL2
PTE7/RGPIO7/TPM3CLK
PTH1
PTH0
PTH3
PTH2
PTH5
PTH4
PTC2/RGPIO10/TPM3CH2
PTB4/TPM2CH1/MISO1
PTB5/TPM1CH1/SS1
PTC3/RGPIO11/TPM3CH3
PTD7/KBI2P7
PTC0/RGPIO8/TPM3CH0
PTC1/RGPIO9/TPM3CH1
PTD6/KBI2P6
PTD5/KBI2P5
PTB3/KBI1P7/MOSI1/ADP7
PTB2/KBI1P6/SPSCK1/ADP6
PTE5/RGPIO5
PTF7/ADP17
PTF6/ADP16
PTF5/ADP15
PTF4/ADP14
PTD4/KBI2P4
V
DD
V
SS
PTA7/TPM2CH2/ADP9
PTB1/KBI1P5/TxD1/ADP5
PTB0/KBI1P4/RxD1/ADP4
PTA2/KBI1P2/SDA1/ADP2
PTA3/KBI1P3/SCL1/ADP3
PTA6/TPM1CH2/ADP8
PTD3/KBI2P3/SS2
PTD2/KBI2P2/MISO2
PTE4/RGPIO4
PTF0/ADP10
PTF1/ADP11
PTF2/ADP12
PTF3/ADP13
PTE2/RGPIO2/MISO1
PTA5/IRQ/TPM1CLK/RESET
PTA4/ACMP1O/BKGD/MS
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PTC7/RGPIO15 /TxD2/ACMP2-
PTC5/RGPIO13/TPM3CH5/ACMP2O
PTC4/RGPIO12/TPM3CH4/RSTO
PTC6/RGPIO14/RxD2/ACMP2+
PTE0/RGPIO0/TPM2CLK/SPSCK1
PTE1/RGPIO1/MOSI1
PTE3/RGPIO3/SS1
PTG3/ADP19
PTG2/ADP18
PTG1
PTG0
PTG7/ADP23
PTG6/ADP22
PTG5/ADP21
PTG4/ADP20
PTJ4
PTJ5
PTJ6
PTJ7
PTJ1
PTJ0
PTJ3
PTJ2
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
Pins in bold are added from the next smaller package.
2 Pin Assignments
This section describes the pin assignments for the available packages. See Tab le 1 for pin availability by package pin-count.
Freescale Semiconductor 5
Figure 2. Pin Assignments in 80-Pin LQFP
MCF51QE128 Series Advance Information Data Sheet, Rev. 4
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
171819202122232425262728293031
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
646362616059585756555453525150
49
V
REFH
V
SSAD
V
DD
V
REFL
V
DDAD
V
SS
PTB7/SCL1/EXTAL
PTH7/SDA2
PTD0/KBI2P0/SPSCK2
PTD1/KBI2P1/MOSI2
PTE6/RGPIO6
PTB6/SDA1/XTAL
PTC2/RGPIO10/TPM3CH2
PTB4/TPM2CH1/MISO1
PTB5/TPM1CH1/SS1
PTC3/RGPIO11/TPM3CH3
PTD7/KBI2P7
PTC0/RGPIO8/TPM3CH0
PTC1/RGPIO9/TPM3CH1
PTD6/KBI2P6
PTD5/KBI2P5
PTB3/KBI1P7/MOSI1/ADP7
PTB2/KBI1P6/SPSCK1/ADP6
PTE5/RGPIO5
PTD4/KBI2P4
V
DD
V
SS
PTA7/TPM2CH2/ADP9
PTB1/KBI1P5/TxD1/ADP5
PTB0/KBI1P4/RxD1/ADP4
PTA2/KBI1P2/SDA11/ADP2
PTA3/KBI1P3/SCL1/ADP3
PTA6/TPM1CH2/ADP8
PTD3/KBI2P3/SS2
PTD2/KBI2P2/MISO2
PTE4/RGPIO4
PTE2/RGPIO2/MISO1
PTA5/IRQ/TPM1CLK/RESET
PTA4/ACMP1O/BKGD/MS
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
PTC7/RGPIO15/TxD2/ACMP2-
PTC5/RGPIO13/TPM3CH5/ACMP2O
PTC4/RGPIO12/TPM3CH4/RSTO
PTC6/RGPIO14/RxD2/ACMP2+
PTE0/RGPIO0/TPM2CLK/SPSCK1
PTE1/RGPIO1/MOSI1
PTE3/RGPIO3/SS1
PTF0/ADP10
PTF1/ADP11
PTF7/ADP17
PTF6/ADP16
PTF5/ADP15
PTF4/ADP14
PTF2/ADP12
PTF3/ADP13
PTG3/ADP19
PTG2/ADP18
PTG1
PTG0
PTH6/SCL2
PTE7/RGPIO7/TPM3CLK
PTH1
PTH0
Figure 3. Pin Assignments in 64-Pin LQFP Package
MCF51QE128 Series Advance Information Data Sheet, Rev. 4
Freescale Semiconductor6
Pin Assignments
Table 2. MCF51QE128 Series Pin Assignment by Package and Pin Sharing Priority
Pin
Number
Lowest ←⎯ Priority ⎯→ Highest
80 64 Port Pin Alt 1 Alt 2 Alt 3 Alt 4
1 1 PTD1 KBI2P1 MOSI2
2 2 PTD0 KBI2P0 SPSCK2
3 3 PTH7 SDA2
44 PTH6 SCL2
5— PTH5
6— PTH4
7 5 PTE7 RGPIO7 TPM3CLK
86 V
97 V
10 8 V
11 9 V
12 10 V
13 11 V
DD
DDAD
REFH
REFL
SSAD
SS
14 12 PTB7 SCL1 EXTAL
15 13 PTB6 SDA1 XTAL
16 — PTH3
17 — PTH2
18 14 PTH1
19 15 PTH0
20 16 PTE6 RGPIO6
21 17 PTE5 RGPIO5
22 18 PTB5 TPM1CH1 SS1
23 19 PTB4 TPM2CH1 MISO1
24 20 PTC3 RGPIO11 TPM3CH3
25 21 PTC2 RGPIO10 TPM3CH2
26 22 PTD7 KBI2P7
27 23 PTD6 KBI2P6
28 24 PTD5 KBI2P5
29 — PTJ7
30 — PTJ6
31 — PTJ5
32 — PTJ4
33 25 PTC1 RGPIO9 TPM3CH1
34 26 PTC0 RGPIO8 TPM3CH0
35 27 PTF7 ADP17
36 28 PTF6 ADP16
37 29 PTF5 ADP15
38 30 PTF4 ADP14
39 31 PTB3 KBI1P7 MOSI1
1
ADP7
40 32 PTB2 KBI1P6 SPSCK1 ADP6
MCF51QE128 Series Advance Information Data Sheet, Rev. 4
Freescale Semiconductor 7
Pin Assignments
Table 2. MCF51QE128 Series Pin Assignment by Package and Pin Sharing Priority (continued)
Pin
Number
Lowest ←⎯ Priority ⎯→ Highest
80 64 Port Pin Alt 1 Alt 2 Alt 3 Alt 4
41 33 PTB1 KBI1P5 TxD1 ADP5
42 34 PTB0 KBI1P4 RxD1 ADP4
43 — PTJ3
44 — PTJ2
45 35 PTF3 ADP13
46 36 PTF2 ADP12
47 37 PTA7 TPM2CH2 ADP9
48 38 PTA6 TPM1CH2 ADP8
49 39 PTE4 RGPIO4
50 40 V
51 41 V
DD
SS
52 42 PTF1 ADP11
53 43 PTF0 ADP10
54 — PTJ1
55 — PTJ0
56 44 PTD4 KBI2P4
57 45 PTD3 KBI2P3 SS2
58 46 PTD2 KBI2P2 MISO2
59 47 PTA3 KBI1P3 SCL1
2
ADP3
60 48 PTA2 KBI1P2 SDA1 ADP2
61 49 PTA1 KBI1P1 TPM2CH0 ADP1 ACMP1-
62 50 PTA0 KBI1P0 TPM1CH0 ADP0 ACMP1+
63 51 PTC7 RGPIO15 TxD2 ACMP2-
64 52 PTC6 RGPIO14 RxD2 ACMP2+
65 — PTG7 ADP23
66 — PTG6 ADP22
67 — PTG5 ADP21
68 — PTG4 ADP20
69 53 PTE3 RGPIO3 SS1
70 54 PTE2 RGPIO2 MISO1
71 55 PTG3 ADP19
72 56 PTG2 ADP18
73 57 PTG1
74 58 PTG0
75 59 PTE1 RGPIO1 MOSI1
76 60 PTE0 RGPIO0 TPM2CLK SPSCK1
77 61 PTC5 RGPIO13 TPM3CH5 ACMP2O
78 62 PTC4 RGPIO12 TPM3CH4 RSTO
79 63 PTA5 IRQ TPM1CLK RESET
80 64 PTA4
3
ACMP1O BKGD MS
MCF51QE128 Series Advance Information Data Sheet, Rev. 4
Freescale Semiconductor8
Electrical Characteristics
1
SPI1 pins (SS1, MISO1, MOSI1, and SPSCK2) can be repositioned using SPI1PS
in SOPT2. Default locations are PTB5, PTB4, PTB3, and PTB2.
2
IIC1 pins (SCL1 and SDA1) can be repositioned using IIC1PS in SOPT2. Default
locations are PTA3 and PTA2, respectively.
3
The PTA4/ACMP1O/BKGD/MS is limited to output only for the port I/O function.
3 Electrical Characteristics
3.1 Introduction
This section contains electrical and timing specifications for the MCF51QE128 series of microcontrollers available at the time
of publication.
3.2 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 3. Parameter Classifications
Those parameters are guaranteed during production testing on each individual device.
P
Those parameters are achieved by the design characterization by measuring a statistically relevant sample
C
size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
T
category.
Those parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.3 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V
or VDD) or the programmable pull-up resistor associated with the pin is enabled.
SS
MCF51QE128 Series Advance Information Data Sheet, Rev. 4
Freescale Semiconductor 9
Electrical Characteristics
Table 4. Absolute Maximum Ratings
Rating Symbol Value Unit
Supply voltage V
Maximum current into V
DD
Digital input voltage V
Instantaneous maximum current
Single pin limit (applies to all port pins)
1, 2, 3
Storage temperature range T
1
Input must be current limited to the value specified. To determine the value of the required
DD
I
DD
In
I
D
stg
–0.3 to +3.8 V
120 mA
–0.3 to VDD+0.3 V
± 25 mA
–55 to 150 °C
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins are internally clamped to VSS and VDD.
3
Power supply must maintain regulation within operating V
range during instantaneous and
DD
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
, the injection current may flow out of VDD and could result in external power supply going
I
DD
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.4 Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take P
the difference between actual pin voltage and V
or VDD and multiply by the pin current for each I/O pin. Except in cases of
SS
unusually high pin current (heavy loads), the difference between pin voltage and V
Table 5. Thermal Characteristics
into account in power calculations, determine
I/O
or VDD will be very small.
SS
Rating Symbol Value Unit
Operating temperature range
(packaged)
Maximum junction temperature T
Thermal resistance
Single-layer board
64-pin LQFP
80-pin LQFP 60
Thermal resistance
Four-layer board
64-pin LQFP
80-pin LQFP 47
1
Depending on packaging.
The average chip-junction temperature (T
MCF51QE128 Series Advance Information Data Sheet, Rev. 4
T
A
JM
θ
JA
θ
JA
) in °C can be obtained from:
J
TL to T
H
(–40 to 85 or 0 to 70)
95 °C
69
50
°C
1
°C/W
°C/W
Freescale Semiconductor10
where:
= Ambient temperature, °C
T
A
θ
= Package thermal resistance, junction-to-ambient, °C/W
JA
P
= P
D
P
int
P
I/O
For most applications, P
+ P
int
I/O
= IDD × VDD, Watts — chip internal power
= Power dissipation on input and output pins — user determined
<< P
I/O
and can be neglected. An approximate relationship between PD and TJ (if P
int
is:
Solving Equation 1 and Equation 2 for K gives:
Electrical Characteristics
TJ = TA + (PD × θJA) Eqn. 1
is neglected)
I/O
P
= K ÷ (TJ + 273°C) Eqn. 2
D
K = P
× (TA + 273°C) + θJA × (PD)
D
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P
for a known T
for any value of T
. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
A
.
A
2
(at equilibrium)
D
Eqn. 3
3.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 6. ESD and Latch-up Test Conditions
Model Description Symbol Value Unit
Series resistance R1 1500 Ω
Human
Body
Storage capacitance C 100 pF
Number of pulses per pin — 3
Series resistance R1 0 Ω
Machine
Latch-up
Freescale Semiconductor 11
Storage capacitance C 200 pF
Number of pulses per pin — 3
Minimum input voltage limit – 2.5 V
Maximum input voltage limit 7.5 V
MCF51QE128 Series Advance Information Data Sheet, Rev. 4
Electrical Characteristics
Table 7. ESD and Latch-Up Protection Characteristics
No. Rating
1 Human body model (HBM) V
2 Machine model (MM) V
3 Charge device model (CDM) V
4 Latch-up current at T
1
Parameter is achieved by design characterization on a small sample size from typical devices
1
= 85°CI
A
Symbol Min Max Unit
HBM
MM
CDM
LAT
± 2000 — V
± 200 — V
± 500 — V
± 100 — mA
under typical conditions unless otherwise noted.
3.6 DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 8. DC Characteristics
Num C Characteristic Symbol Condition Min Typ
1 Operating Voltage 1.8 3.6 V
Output high
C
voltage
P All I/O pins,
2
T 2.3 V, I
C1.8V, I
3D
4
Output high
current
Output low
C
voltage
P All I/O pins,
T 2.3 V, I
C 1.8 V, I
Output low
D
current
All I/O pins,
low-drive strength
high-drive strength
Max total I
OH
for all
ports
All I/O pins,
low-drive strength
high-drive strength
Max total I
OL
for all
ports
V
I
OHT
V
I
OLT
OH
OL
1.8 V, I
2.7 V, I
1.8 V, I
2.7 V, I
= –2 mA VDD – 0.5 — —
Load
= –10 mA VDD – 0.5 — —
Load
= –6 mA VDD – 0.5 — —
Load
= –3 mA VDD – 0.5 — —
Load
——100mA
= 2 mA — — 0.5
Load
= 10 mA — — 0.5
Load
= 6 mA — — 0.5
Load
= 3 mA — — 0.5
Load
——100mA5
1
Max Unit
V
V
P Input high
6
voltage
CV
P Input low voltage all digital inputs
7
CV
8 C Input hysteresis all digital inputs V
9P
10 P
Input leakage
current
Hi-Z (off-state)
leakage current
all digital inputs
all input only pins
(Per pin)
all input/output
(per pin)
V
IH
> 1.8 V 0.85 x V
DD
VDD > 2.7 V — — 0.35 x V
V
VDD > 2.7 V 0.70 x V
IL
hys
|I
In|
|I
OZ|
VIn = VDD or V
>1.8 V — — 0.30 x V
DD
0.06 x V
SS
V
= V
or V
In
DD
SS
—0.1 1μA
—0.1 1μA
——
DD
——
DD
DD
DD
——mV
DD
Pull-up resistors all digital inputs, when
11 P
enabled
R
PU
17.5 — 52.5 kΩ
MCF51QE128 Series Advance Information Data Sheet, Rev. 4
Freescale Semiconductor12
V
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