Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
Cover Sheet
Block Diagram
Clock Distribution
Power Delivery Map 4
Power on sequence
Reset / Power good
D D
CPU 1-6
PCIE X16 X1 19
CLOCK Gen 20
PCH 1 - 8 SPI ,PCIRST 21-28
PCI SLOT 1,2 29
Audio/ALC887/ALC662 30-31
LAN RTL8111 / USB 32-33
FP-USB1,USB2,USB3 34
KB/MS 35
USB3.0
TPM/LPT
C C
PCIE to PCI (IT8893E/BX )
SIO IT8728
ATX/FP/BUZ/RSMRST
POWER
FOX2
XDP 47
FAN
VGA / HDMI / DVI
8-13
14-18DDR3 CHA - B
41-46
49-50
36
37
38
39
40
42
48
4
3
2
1
1
2
3
5
6
Q77M01
CPU:
Intel Ivy Bridge processors in LGA1155 Package
Fab 1.0
System Chipset:
PCH: Panther_Point
Main Memory:
Dual Channel / DDR-III * 4 (Max 16GB)
On Board Device:
LAN:Intel WG82579LM
LAN1:RealTek RTL8111F-CG
HDA Codec:ALC662-GR
BIOS:SPI Flash ROM 4M/8M
Expansion Slots:
PCI EXPRESS 16X SLOT *1
PCI EXPRESS 1X SLOT * 1
PCI SLOT * 2
Changelist 51
Fab.B
B B
A A
5
4
3
SKUVersion Function BOM
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Cover Sheet
Cover Sheet
Cover Sheet
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
FOXCONN PCEG
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
1
150Thursday, April 26, 2012
150Thursday, April 26, 2012
150Thursday, April 26, 2012
1.0C
1.0C
1.0C
of
of
of
Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
D D
4
3
2
1
BLOCK DIAGRAM
POWER
SUPPLY
CONNECTOR
VREG
VRD12
INTEL PROCESSOR
Ivy Bridge
LGA1155
C C
B B
PCIE (GEN 3)
PCIE X1
DVI
HDMI
DP
PCI1
PCI2 ALC662
PCIE GEN3 x16
PCI EXPRESS
SATA 3.0 (2 PORTS)
DMIFDI
XDP
INTEL
PCH
SATA 2.0 (4 PORTS) FOX2
CHANNEL A DDR3 SDRAM (800/1066/1333)
CHANNEL B DDR3 SDRAM (800/1066/1333)
PCIE
LAN:Intel WG82579LM
LAN1:RealTek RTL8111F-CG
USB3.0
BP*4
USB2.0
BP*4 / FP*8
AUDIOCODEC
DDR3 SDRAM CONN 1
DDR3 SDRAM CONN 1
A A
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
1
250Thursday, April 26, 2012
250Thursday, April 26, 2012
250Thursday, April 26, 2012
1.0C
1.0C
1.0C
of
of
of
5
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
4
3
2
1
CLOCK DISTRIBUTION
D D
PCH_CLK_DMI
CLKIN_SATA
CLKIN_DOT_96
(FOR USB)
CLKIN_BCLK
REFCLK14IN
CLKOUT_BCLK
BCLK
C C
CLKOUT_DMI
CPU
CLKIN
PE_100M_MCP
SIO
PCICLKIN
PCICLK1
PCICLK0
33M
33M
PCICLK
Debug Card(TPM)
PCICLK2
PCH
B B
25MHZ
X'TAL
Buffer Through Mode
FCI Mode
CLKOUT_PEG_A
PCIE X16
CLKOUT_PCIE3
PCIE X1 slot
CLKOUT_PCIE0
PCIE GLAN
CLKOUT_PCIE1
UPD720200(USB3.0)
A A
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
350Thursday, April 26, 2012
350Thursday, April 26, 2012
350Thursday, April 26, 2012
1
1.0A3
1.0A3
1.0A3
5
Title
Title
Title
Clock Distribution
Clock Distribution
Clock Distribution
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
POWER DELIVERY MAP
4
3
2
1
+12V_VIN(4PIN)
LYN/HVN(95W)
D D
DDR3(2 DIMM)
+V_1.5_SM=1.5V
+V_SM_VTT=0.75V
SWITCHING
Icc=20A
Max=25A
+V_1.5_SM(1.5V) to
+V_SM_VTT (0.75V)
Icc=0.75A Max=1A
SWITCHING
Icc=90A
Max=100A
SWITCHING
Icc=16A
Max=20A
SWITCHING
Icc=30A
Max=35A
+VCORE (CPU Vcore)
Voltage=1.1V
Icc(Max)=90A Max=100A
4-Phases Swithing
+V_1.1_AXG(Havendale only)
Voltage=1.1V
Icc=16A Max=20A
+V_1.5_SM(DDR III)
Voltage=1.5V
+V_1.1_VTT(1.1/1.05V)
ACPI
Controller
+3VDUAL
Icc=1.25A
VCCPLL(1.8V)
RTL8111DL GbE Lan
+3VDUAL
600mW
C C
DVDD12/EVDD12
289mA
+5VSB
+12V
HDA Codec
+5VA
Voltage=5V
Icc=200mA
VCC
Voltage=3.3V
Icc=40mA
12V TO +5VA
Icc=200mA
+3V
+V_1.5_SM to
+V_1.05_PCH
Icc=6.5A
Max=8A
SWITCHING
Icc=2A
Max=2.5A
+3V
+3V TO
+V_1.8_SFR
Icc=1.5A
IBEX PEAK(5.5W)
VCCCORE(+V_1.05_PCH)
Voltage=1.05V
Icc(Max)=6.5A
VCCME(+V_1.05_ME)
Voltage=1.05V
Icc(Max)=2.4072A
VCCDMI 0.0655A
V_CPU_IO 33uA
VCCPNAND=1.8V 0.01559A
+3VDUAL 0.168A
3.3V 0.3572A
VCCME(V_3P3_EPW)
Super I/O
+5V
B B
Icc=60mA
+5V
RTC
Battery
0.0862A
VCCRTC 0.0022A
+3V+5VSB
12V
PCI Express X16
+12V=5.5A
+3VDUAL
Icc(Max)=0.375A(wake)
Icc(Max)=0.02A(no wake)
+3V=3A
PCI Express X4
+12V=0.5A
+3VDUAL
Icc(Max)=0.375A(wake)
Icc(Max)=0.02A(no wake)
+3V=3A
PCI Slot
+5V
-12V
Icc(Max)=0.1A
+5V
Icc(Max)=5A
+3V
Icc(Max)=7.6A
+12V
Icc(Max)=0.5A
+3VDUAL
Icc(Max)=0.375A(wake)
Icc(Max)=0.02A(no wake)
CK505
+3V (Core)
Voltage=3.3V
Ivdd=250mA
-12V
PS2
+5V_DUAL=500mA(S0, S1)
+5V_DUAL=2mA(S3)
USB2.0 12 Ports
+5V_DUAL_USB=6A(S0, S1)
+5V_DUAL_USB=?A(S3)
A A
5
ACPI
Controller
+5V_DUAL
ACPI
Controller
+5V_DUAL_USB
4
+5V
+5VSB
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Power Delivery Map
Power Delivery Map
Power Delivery Map
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
3
2
Date: Sheet
FOXCONN PCEG
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
1
450Thursday, April 26, 2012
450Thursday, April 26, 2012
450Thursday, April 26, 2012
1.0C
1.0C
1.0C
of
of
of
Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
POWER ON SEQUENCE
D D
4
3
2
1
DSW Entry
VccDSW3_3
DPWROK
SUSWARN#
SUS_PWR_ACK
SLP_SUS#
RSMRST#
+5VDUAL
+5V_S5/+3V_S5
1.05V
VccDSW3_3
DPWROK
C C
B B
A A
SLP_SUS#
RSMRST#
+5V_S5/+3V_S5
SUSWARN#
SUS_PWR_ACK
+5VDUAL
DSW Exit
5
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Power On Sequence
Power On Sequence
Power On Sequence
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
FOXCONN PCEG
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
1
1.0Custom
1.0Custom
1.0Custom
550Thursday, April 26, 2012
550Thursday, April 26, 2012
550Thursday, April 26, 2012
of
of
of
Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
4
3
2
1
RESET / Power Good MAP
Sequence Signal Name:
O_PWRBTN#IN
D D
C C
(1)
S_SLP_S4# S_SLP_S3#
(2)
O_PSON#
(3)
B_ATX_PWROK
(4)
PCH_MEPWRGD
(5)
S_PCH_SYSPWROK P_VR_READY
(6)
PWRGD_3V
(7)
H_DRAMPWRGD
(8)
H_PWRGD
(9)
S_PLTRST#
(10)
X_PLTRST_PCIE_SLOT# K_PCIRST#_SLOT
(11)
A_Z_RST#
(12)
PCH_MEPWRGD
+1P05V_ME
D3_RESET#
H_RESET#_R S_PLTRST#_R
> 1ms
S_SLP_M#
ME POWER-GOOD
CIRCUIT
PCH_MEPWRGD
Power On Botton
RESET BUTTON
FP_RST#
(1) (1)
(5)
APWROK
PWRBTN#
SYS_RESET#
PCH
UNCOREPWRGOOD
(9)
DRAMPWROK
PROCPWRGD
SLP_S4# SLP_S4_S5#
PLTRST# LRESET#
CPU-Ivy Bridge
SM_DRAMPWROK
(1)
(8)
(2)
(2)
(10)
PWRBTN#
SLP_S3#SLP_S3#
RESET*
(10)
Buffer (UH2)
SIO-8728
SM_DRAMRST*
PCI_RST_SYS#
(11)
(8)
(9)
(1)
(1)
DDRIII Slots
D3_RESET#
CPU-XDP
PCH-XDP
F_TP_XDP_RST
Mini-PCIe
PERST#
PCI-E 1x Slot2
PERST#O_PWRBTN#IN
PCI-E 4x Slot4
PWRGD
(7)
RSMRST#
PWR_GOOD_3V
PWR_GOOD_3V
PWRGD_PS
PS_ON#
PWRGD_PS
100~120ms
2
(4)
PCI-E 16x Slot1
PWRGD
ATX Power
(3)
PSON
PWROK
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Reset/power good
Reset/power good
Reset/power good
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
1
650Thursday, April 26, 2012
650Thursday, April 26, 2012
650Thursday, April 26, 2012
1.0C
1.0C
1.0C
of
of
of
Front Panel
O_PWRBTN#IN
VRD 12
B B
A A
5
VR_RDY
HD Audio
RESET#
PCI Slot3
RESET#
LAN
PE_RST_N
TPM/TCM
LRESET#
(12)
(11)
(10)
(10)
(6)
SYS_PWROK
HDA_RST#
4
AND
PCIRST#
RSMRST#
PWROK
SLP_A# IO_SMI#
PROCPWRGD
PWROK
(2)
> 1ms
3
Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
4
3
2
1
IRQ Routing Table
INTA# INTB# INTC# INTD# IDSEL REQn# GNTn#
Slot1 A B C D 17 0 0
D D
INTA# INTB# INTC# INTD# IDSEL REQn# GNTn#
Slot2 ABC D 192 2
STRAPPING Table
CPU side
C C
CFG[17:0] Description
[2]
[6:5]
PCI Express static x16
lane numbering reversal
PCI Express Bifurcation
1: normal
0: lane numbers reversed
00: 1x8, 2x4 PCI Express
01: reserved
10: 2x8 PCI Express
11: 1x16 PCI Express
Default
Default
B B
A A
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
1
750Thursday, April 26, 2012
750Thursday, April 26, 2012
750Thursday, April 26, 2012
1.0C
1.0C
1.0C
of
of
of
5
Title
Title
Title
STRAP
STRAP
STRAP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
D D
U1C
U1C
B11
X_1X16_RXP019
X_1X16_RXN019
X_1X16_RXP119
H_DMI_RX_DP021
H_DMI_RX_DN021
H_DMI_RX_DP121
H_DMI_RX_DN121
H_DMI_RX_DP221
H_DMI_RX_DN221
H_DMI_RX_DP321
H_DMI_RX_DN321
R194 24.9+/-1%*R194 24.9+/-1%
X_1X16_RXN119
X_1X16_RXP219
X_1X16_RXN219
X_1X16_RXP319
X_1X16_RXN319
X_1X16_RXP419
X_1X16_RXN419
X_1X16_RXP519
X_1X16_RXN519
X_1X16_RXP619
X_1X16_RXN619
X_1X16_RXP719
X_1X16_RXN719
X_1X16_RXP819
X_1X16_RXN819
X_1X16_RXP919
X_1X16_RXN919
X_1X16_RXP1019
X_1X16_RXN1019
X_1X16_RXP1119
X_1X16_RXN1119
X_1X16_RXP1219
X_1X16_RXN1219
X_1X16_RXP1319
X_1X16_RXN1319
X_1X16_RXP1419
X_1X16_RXN1419
X_1X16_RXP1519
X_1X16_RXN1519
C C
V_1D05V_CPU
B B
Short B4 & C4 together, route as a single 4 mil trace to R2
Route B5 to R2 as a aeperate 10 mil trace
X_1X16_RXP0
X_1X16_RXN0
X_1X16_RXP1
X_1X16_RXN1
X_1X16_RXP2
X_1X16_RXN2
X_1X16_RXP3
X_1X16_RXN3
X_1X16_RXP4
X_1X16_RXN4
X_1X16_RXP5
X_1X16_RXN5
X_1X16_RXP6
X_1X16_RXN6
X_1X16_RXP7
X_1X16_RXN7
X_1X16_RXP8
X_1X16_RXN8
X_1X16_RXP9
X_1X16_RXN9
X_1X16_RXP10
X_1X16_RXN10
X_1X16_RXP11
X_1X16_RXN11
X_1X16_RXP12
X_1X16_RXN12
X_1X16_RXP13
X_1X16_RXN13
X_1X16_RXP14
X_1X16_RXN14
X_1X16_RXP15
X_1X16_RXN15
*
GRCOM
B12
D12
D11
C10
C9
E10
E9
B8
B7
C6
C5
A5
A6
E2
E1
F4
F3
G2
G1
H3
H4
J1
J2
K3
K4
L1
L2
M3
M4
N1
N2
W5
W4
V3
V4
Y3
Y4
AA4
AA5
P3
P4
R2
R1
T4
T3
U2
U1
B5
C4
B4
V_1D8V_SFR
PEG_RX[0]
PEG_RX#[0]
PEG_RX[1]
PEG_RX#[1]
PEG_RX[2]
PEG_RX#[2]
PEG_RX[3]
PEG_RX#[3]
PEG_RX[4]
PEG_RX#[4]
PEG_RX[5]
PEG_RX#[5]
PEG_RX[6]
PEG_RX#[6]
PEG_RX[7]
PEG_RX#[7]
PEG_RX[8]
PEG_RX#[8]
PEG_RX[9]
PEG_RX#[9]
PEG_RX[10]
PEG_RX#[10]
PEG_RX[11]
PEG_RX#[11]
PEG_RX[12]
PEG_RX#[12]
PEG_RX[13]
PEG_RX#[13]
PEG_RX[14]
PEG_RX#[14]
PEG_RX[15]
PEG_RX#[15]
DMI_RX[0]
DMI_RX#[0]
DMI_RX[1]
DMI_RX#[1]
DMI_RX[2]
DMI_RX#[2]
DMI_RX_3
DMI_RX#[3]
PE_RX[0]
PE_RX#[0]
PE_RX[1]
PE_RX#[1]
PE_RX[2]
PE_RX#[2]
PE_RX[3]
PE_RX#[3]
PEG_ICOMPO
PEG_RCOMPO
PEG_ICOMPI
CPU_SKT_H2
CPU_SKT_H2
4
?
?
SKT_H2
SKT_H2
REV = 4
REV = 4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
C434 0.1uF 16V, X7R, +/-10%
C434 0.1uF 16V, X7R, +/-10%
PEG_TX[0]
PEG_TX#[0]
PEG_TX[1]
PEG_TX#[1]
PEG_TX[2]
PEG_TX#[2]
PEG_TX[3]
PEG_TX#[3]
PEG_TX[4]
PEG_TX#[4]
PEG_TX[5]
PEG_TX#[5]
PEG_TX[6]
PEG_TX#[6]
PEG_TX[7]
PEG_TX#[7]
PEG_TX[8]
PEG_TX#[8]
PEG_TX[9]
PEG_TX#[9]
PEG_TX[10]
PEG_TX#[10]
PEG_TX[11]
PEG_TX#[11]
PEG_TX[12]
PEG_TX#[12]
PEG_TX[13]
PEG_TX#[13]
PEG_TX[14]
PEG_TX#[14]
PEG_TX[15]
PEG_TX#[15]
DMI_TX[0]
DMI_TX#[0]
DMI_TX[1]
DMI_TX#[1]
DMI_TX[2]
DMI_TX#[2]
DMIGEN PEG
DMIGEN PEG
DMI_TX[3]
DMI_TX#[3]
PE_TX[0]
PE_TX#[0]
PE_TX[1]
PE_TX#[1]
PE_TX[2]
PE_TX#[2]
PE_TX[3]
PE_TX#[3]
3 OF 11
3 OF 11
*
*
3
C13
X_1X16_TXP0
C14
E14
E13
G14
G13
F12
F11
J14
J13
D8
D7
D3
C3
E6
E5
F8
F7
G10
G9
G5
G6
K7
K8
J5
J6
M8
M7
L6
L5
N5
N6
V7
V6
W7
W8
Y6
Y7
AA7
AA8
P8
P7
T7
T8
R6
R5
U5
U6
?
?
X_1X16_TXP0 19
X_1X16_TXN0
X_1X16_TXN0 19
X_1X16_TXP1
X_1X16_TXP1 19
X_1X16_TXN1
X_1X16_TXN1 19
X_1X16_TXP2
X_1X16_TXP2 19
X_1X16_TXN2
X_1X16_TXN2 19
X_1X16_TXP3
X_1X16_TXP3 19
X_1X16_TXN3
X_1X16_TXN3 19
X_1X16_TXP4
X_1X16_TXP4 19
X_1X16_TXN4
X_1X16_TXN4 19
X_1X16_TXP5
X_1X16_TXP5 19
X_1X16_TXN5
X_1X16_TXN5 19
X_1X16_TXP6
X_1X16_TXP6 19
X_1X16_TXN6
X_1X16_TXN6 19
X_1X16_TXP7
X_1X16_TXP7 19
X_1X16_TXN7
X_1X16_TXN7 19
X_1X16_TXP8
X_1X16_TXP8 19
X_1X16_TXN8
X_1X16_TXN8 19
X_1X16_TXP9
X_1X16_TXP9 19
X_1X16_TXN9
X_1X16_TXN9 19
X_1X16_TXP10
X_1X16_TXP10 19
X_1X16_TXN10
X_1X16_TXN10 19
X_1X16_TXP11
X_1X16_TXP11 19
X_1X16_TXN11
X_1X16_TXN11 19
X_1X16_TXP12
X_1X16_TXP12 19
X_1X16_TXN12
X_1X16_TXN12 19
X_1X16_TXP13
X_1X16_TXP13 19
X_1X16_TXN13
X_1X16_TXN13 19
X_1X16_TXP14
X_1X16_TXP14 19
X_1X16_TXN14
X_1X16_TXN14 19
X_1X16_TXP15
X_1X16_TXP15 19
X_1X16_TXN15
X_1X16_TXN15 19
H_DMI_TX_DP0 21
H_DMI_TX_DN0 21
H_DMI_TX_DP1 21
H_DMI_TX_DN1 21
H_DMI_TX_DP2 21
H_DMI_TX_DN2 21
H_DMI_TX_DP3 21
H_DMI_TX_DN3 21
DESIGN NOTE:
N/T: PCIE X4 LANES ARE NOT SUPPORTED ON DESKTOP CPU SKUS
V_1D05V_CPU
C428 0.1uF 16V, X7R, +/-10%
C428 0.1uF 16V, X7R, +/-10%
C410 0.1uF 16V, X7R, +/-10%
C410 0.1uF 16V, X7R, +/-10%
C443 0.1uF 16V, X7R, +/-10%
C443 0.1uF 16V, X7R, +/-10%
V_1D05V_CPU
*
*
*
*
*
*
H_FDI_FSYNC0_124
H_FDI_LSYNC0_124
H_FDI_FSYNC1_124
H_FDI_LSYNC1_124
R374 24.9+/-1%*R374 24.9+/-1%
2
?
?
SKT_H2
SKT_H2
U1D
U1D
AC5
FDI_FSYNC_0
AC4
FDI_LSYNC_0
AE5
FDI_LSYNC_1
AE4
FDI_FSYNC_1
H_FDI_INT_124
*
AG3
AE2
AE1
V_1D05V_CPU
FDI_INT
FDI_COMPIO
FDI_ICOMPO
CPU_SKT_H2
CPU_SKT_H2
REV = 4
REV = 4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
4 OF 11
4 OF 11
C286 0.1uF 16V, X7R, +/-10%
C286 0.1uF 16V, X7R, +/-10%
*
*
C302 0.1uF 16V, X7R, +/-10%
C302 0.1uF 16V, X7R, +/-10%
*
*
C299 0.1uF 16V, X7R, +/-10%
C299 0.1uF 16V, X7R, +/-10%
*
*
C287 0.1uF 16V, X7R, +/-10%
C287 0.1uF 16V, X7R, +/-10%
*
*
C313 0.1uF 16V, X7R, +/-10%
C313 0.1uF 16V, X7R, +/-10%
*
*
C320 0.1uF 16V, X7R, +/-10%
C320 0.1uF 16V, X7R, +/-10%
*
*
C285 0.1uF 16V, X7R, +/-10%
C285 0.1uF 16V, X7R, +/-10%
*
*
C343 0.1uF 16V, X7R, +/-10%
C343 0.1uF 16V, X7R, +/-10%
*
*
C281 0.1uF 16V, X7R, +/-10%
C281 0.1uF 16V, X7R, +/-10%
*
*
C293 0.1uF 16V, X7R, +/-10%
C293 0.1uF 16V, X7R, +/-10%
*
*
C332 0.1uF 16V, X7R, +/-10%
C332 0.1uF 16V, X7R, +/-10%
*
*
C323 0.1uF 16V, X7R, +/-10%
C323 0.1uF 16V, X7R, +/-10%
*
*
C283 0.1uF 16V, X7R, +/-10%
C283 0.1uF 16V, X7R, +/-10%
*
*
FDI_TX[0]
FDI_TX[0]
FDI_TX[0]
FDI_TX#[0]
FDI_TX[1]
FDI_TX#[1]
FDI_TX[2]
FDI_TX#[2]
FDI_TX[3]
FDI_TX#[3]
FDI_TX[4]
FDI_TX#[4]
FDI_TX[5]
FDI_TX#[5]
FDI_TX[6]
FDI_TX#[6]
FDI_TX[7]
FDI_TX#[7]
FDI
FDI
LINK
LINK
AC8
AC7
AC2
AC3
AD2
AD1
AD4
AD3
AD7
AD6
AE7
AE8
AF3
AF2
AG2
AG1
?
?
1
H_FDI_TX_DP0 24
H_FDI_TX_DN0 24
H_FDI_TX_DP1 24
H_FDI_TX_DN1 24
H_FDI_TX_DP2 24
H_FDI_TX_DN2 24
H_FDI_TX_DP3 24
H_FDI_TX_DN3 24
H_FDI_TX_DP4 24
H_FDI_TX_DN4 24
H_FDI_TX_DP5 24
H_FDI_TX_DN5 24
H_FDI_TX_DP6 24
H_FDI_TX_DN6 24
H_FDI_TX_DP7 24
H_FDI_TX_DN7 24
Stiching CAP for FDI
A A
5
4
3
Stiching CAP for PEGStiching CAP for DMI
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
CPU1-PEG/DMI/FDI
CPU1-PEG/DMI/FDI
CPU1-PEG/DMI/FDI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
FOXCONN PCEG
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
1
850Thursday, April 26, 2012
850Thursday, April 26, 2012
850Thursday, April 26, 2012
1.0C
1.0C
1.0C
of
of
of
Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
4
3
2
1
D D
C C
B B
D3_DATA_A[63..0]14,15
?
?
SKT_H2
SKT_H2
REV = 4
REV = 4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
1 OF 11
1 OF 11
AU35
AW37
AU39
AU36
AW35
AY36
AU38
AU37
AR40
AR37
AN38
AN37
AR39
AR38
AN39
AN40
AG40
AG37
AE38
AE37
AG39
AG38
AE39
AE40
AV37
AP38
AK38
AF38
AV36
AP39
AK39
AF39
AW3
AW5
AW7
AW9
AL40
AL37
AJ38
AJ37
AL39
AL38
AJ39
AJ40
AW4
AW8
AJ3
AJ4
AL3
AL4
AJ2
AJ1
AL2
AL1
AN1
AN4
AR3
AR4
AN2
AN3
AR2
AR1
AV2
AV5
AU2
AU3
AU5
AY5
AY7
AU7
AV9
AU9
AV7
AY9
AK3
AP3
AV8
AK2
AP2
AV4
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
?
?
D3_DATA_A0
D3_DATA_A1
D3_DATA_A2
D3_DATA_A3
D3_DATA_A4
D3_DATA_A5
D3_DATA_A6
D3_DATA_A7
D3_DATA_A8
D3_DATA_A9
D3_DATA_A10
D3_DATA_A11
D3_DATA_A12
D3_DATA_A13
D3_DATA_A14
D3_DATA_A15
D3_DATA_A16
D3_DATA_A17
D3_DATA_A18
D3_DATA_A19
D3_DATA_A20
D3_DATA_A21
D3_DATA_A22
D3_DATA_A23
D3_DATA_A24
D3_DATA_A25
D3_DATA_A26
D3_DATA_A27
D3_DATA_A28
D3_DATA_A29
D3_DATA_A30
D3_DATA_A31
D3_DATA_A32
D3_DATA_A33
D3_DATA_A34
D3_DATA_A35
D3_DATA_A36
D3_DATA_A37
D3_DATA_A38
D3_DATA_A39
D3_DATA_A40
D3_DATA_A41
D3_DATA_A42
D3_DATA_A43
D3_DATA_A44
D3_DATA_A45
D3_DATA_A46
D3_DATA_A47
D3_DATA_A48
D3_DATA_A49
D3_DATA_A50
D3_DATA_A51
D3_DATA_A52
D3_DATA_A53
D3_DATA_A54D3_DATA_A54
D3_DATA_A55D3_DATA_A55
D3_DATA_A56D3_DATA_A56
D3_DATA_A57D3_DATA_A57
D3_DATA_A58D3_DATA_A58
D3_DATA_A59D3_DATA_A59
D3_DATA_A60D3_DATA_A60
D3_DATA_A61D3_DATA_A61
D3_DATA_A62D3_DATA_A62
D3_DATA_A63D3_DATA_A63
D3_DQS_A_DP014,15
D3_DQS_A_DP114,15
D3_DQS_A_DP214,15
D3_DQS_A_DP314,15
D3_DQS_A_DP414,15
D3_DQS_A_DP514,15
D3_DQS_A_DP614,15
D3_DQS_A_DP714,15
D3_DQS_A_DN014,15
D3_DQS_A_DN114,15
D3_DQS_A_DN214,15
D3_DQS_A_DN314,15
D3_DQS_A_DN414,15
D3_DQS_A_DN514,15
D3_DQS_A_DN614,15
D3_DQS_A_DN714,15
U1A
U1A
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
SA_WE#
SA_CAS#
SA_RAS#
SA_BS_0
SA_BS[1]
SA_BS[2]
SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]
SA_CKE[0]
SA_CKE[1]
SA_CKE[3]
SA_CKE[2]
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
SA_CK[0]
SA_CK#[0]
SA_CK[1]
SA_CK#[1]
SA_CK[2]
SA_CK#[2]
SA_CK[3]
SA_CK#[3]
SM_DRAMRST#
SA_DQS[8]
SA_DQS#[8]
SA_ECC_CB[0]
SA_ECC_CB[1]
SA_ECC_CB[2]
SA_ECC_CB[3]
SA_ECC_CB[4]
SA_ECC_CB[5]
SA_ECC_CB[6]
SA_ECC_CB[7]
DDR_A
DDR_A
CPU_SKT_H2
CPU_SKT_H2
AV27
D3_MAA_A0
AY24
D3_MAA_A1
AW24
D3_MAA_A2
AW23
D3_MAA_A3
AV23
D3_MAA_A4
AT24
D3_MAA_A5
AT23
D3_MAA_A6
AU22
D3_MAA_A7
AV22
D3_MAA_A8
AT22
D3_MAA_A9
AV28
D3_MAA_A10
AU21
D3_MAA_A11
AT21
D3_MAA_A12
AW32
D3_MAA_A13
AU20
D3_MAA_A14
AT20
D3_MAA_A15
AW29
AV30
AU28
AY29
D3_SBS_A0
AW28
D3_SBS_A1
AV20
D3_SBS_A2
AU29
D3_SCS_A_#0
AV32
D3_SCS_A_#1
AW30
D3_SCS_A_#2
AU33
D3_SCS_A_#3
AV19
D3_SCKE_A0
AT19
D3_SCKE_A1
AU18
D3_SCKE_A2
AV18
D3_SCKE_A3
AV31
D3_ODT_A0
AU32
D3_ODT_A1
AU30
D3_ODT_A2
AW33
D3_ODT_A3
AY25
AW25
AU24
AU25
AW27
AY27
AV26
AW26
AW18
R498 0 +/-5%
R498 0 +/-5%
*
*
AV13
AV12
AU12
AU14
AW13
AY13
DDR ECC IS NOT SUPPORTED ON DESKTOP SKUS
AU13
ECC TRACES ARE FOR ENGINEERING FUNCTION ONLY
AU11
DESIGN NOTE:
AY12
AW12
D3_MAA_A[15..0] 14,15
D3_WE_A# 14,15
D3_CAS_A# 14,15
D3_RAS_A# 14,15
D3_SBS_A[2..0] 14,15
D3_SCS_A_#0 14
D3_SCS_A_#1 14
D3_SCS_A_#2 15
D3_SCS_A_#3 15
D3_SCKE_A0 14
D3_SCKE_A1 14
D3_SCKE_A2 15
D3_SCKE_A3 15
D3_ODT_A0 14
D3_ODT_A1 14
D3_ODT_A2 15
D3_ODT_A3 15
D3_CK_DDR_A_DP0 14
D3_CK_DDR_A_DN0 14
D3_CK_DDR_A_DP1 14
D3_CK_DDR_A_DN1 14
D3_CK_DDR_A_DP2 15
D3_CK_DDR_A_DN2 15
D3_CK_DDR_A_DP3 15
D3_CK_DDR_A_DN3 15
C560
C560
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
DESIGN NOTE:
RC FILTER
D3_DRAMRST# 14,15,16,17
A A
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
1
950Thursday, April 26, 2012
950Thursday, April 26, 2012
950Thursday, April 26, 2012
1.0C
1.0C
1.0C
of
of
of
5
Title
Title
Title
CPU2-DDR3_CHA
CPU2-DDR3_CHA
CPU2-DDR3_CHA
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
4
3
2
1
D D
C C
B B
D3_DATA_B[63..0]16,17
AM10
AL10
AP10
AR10
AM12
AM13
AR13
AP13
AL12
AL13
AR12
AP12
AR28
AR29
AL28
AL29
AP28
AP29
AM28
AM29
AP32
AP31
AP35
AP34
AR32
AR31
AR35
AR34
AM32
AM31
AL35
AL32
AM34
AL31
AM35
AL34
AH35
AH34
AE34
AE35
AJ35
AJ34
AF33
AF35
AN13
AN29
AP33
AL33
AG35
AN12
AN28
AR33
AM33
AG34
AG7
AG8
AG5
AG6
AM7
AM6
AM9
AP7
AR7
AP6
AR6
AP9
AR9
AH7
AM8
AR8
AH6
AP8
AJ9
AJ8
AJ6
AJ7
AL7
AL6
AL9
AL8
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#7]
?
?
D3_DATA_B0
D3_DATA_B1
D3_DATA_B2
D3_DATA_B3
D3_DATA_B4
D3_DATA_B5
D3_DATA_B6
D3_DATA_B7
D3_DATA_B8
D3_DATA_B9
D3_DATA_B10
D3_DATA_B11
D3_DATA_B12
D3_DATA_B13
D3_DATA_B14
D3_DATA_B15
D3_DATA_B16
D3_DATA_B17
D3_DATA_B18
D3_DATA_B19
D3_DATA_B20
D3_DATA_B21
D3_DATA_B22
D3_DATA_B23
D3_DATA_B24
D3_DATA_B25
D3_DATA_B26
D3_DATA_B27
D3_DATA_B28
D3_DATA_B29
D3_DATA_B30
D3_DATA_B31
D3_DATA_B32
D3_DATA_B33
D3_DATA_B34
D3_DATA_B35
D3_DATA_B36
D3_DATA_B37
D3_DATA_B38
D3_DATA_B39
D3_DATA_B40
D3_DATA_B41
D3_DATA_B42
D3_DATA_B43
D3_DATA_B44
D3_DATA_B45
D3_DATA_B46
D3_DATA_B47
D3_DATA_B48
D3_DATA_B49
D3_DATA_B50
D3_DATA_B51
D3_DATA_B52
D3_DATA_B53
D3_DATA_B54
D3_DATA_B55
D3_DATA_B56
D3_DATA_B57
D3_DATA_B58
D3_DATA_B59
D3_DATA_B60
D3_DATA_B61
D3_DATA_B62
D3_DQS_B_DP016,17
D3_DQS_B_DP116,17
D3_DQS_B_DP216,17
D3_DQS_B_DP316,17
D3_DQS_B_DP416,17
D3_DQS_B_DP516,17
D3_DQS_B_DP616,17
D3_DQS_B_DP716,17
D3_DQS_B_DN016,17
D3_DQS_B_DN116,17
D3_DQS_B_DN216,17
D3_DQS_B_DN316,17
D3_DQS_B_DN416,17
D3_DQS_B_DN516,17
D3_DQS_B_DN616,17
D3_DQS_B_DN716,17
D3_DATA_B63
?
?
SKT_H2
SKT_H2
REV = 4
REV = 4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_WE#
SB_CAS#
SB_RAS#
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]
SB_CKE[0]
SB_CKE[1]
SB_CKE[2]
SB_CKE[3]
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
SB_CK[0]
SB_CK[0]
SB_CK[0]
SB_CK#[0]
SB_CK[1]
SB_CK#[1]
SB_CK[2]
SB_CK#[2]
SB_CK[3]
SB_CK#[3]
SB_DIMM_DQVREF
SA_DIMM_DQVREF
SB_DQS[8]
SB_DQS#[8]
SB_ECC_CB[0]
SB_ECC_CB[1]
SB_ECC_CB[2]
SB_ECC_CB[3]
SB_ECC_CB[4]
SB_ECC_CB[5]
SB_ECC_CB[6]
SB_ECC_CB[7]
DDR_B
DDR_B
2 OF 11
2 OF 11
CPU_SKT_H2
CPU_SKT_H2
U1B
U1B
AK24
AM20
AM19
AK18
AP19
AP18
AM18
AL18
AN18
AY17
AN23
AU17
AT18
AR26
AY16
AV16
AR25
AK25
AP24
AP23
AM24
AW17
AN25
AN26
AL25
AT26
AU16
AY15
AW15
AV15
AL26
AP26
AM26
AK26
AL21
AL22
AL20
AK20
AL23
AM22
AP21
AN21
AH1
AH4
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
AN16
AN15
AL16
AM16
AP16
AR16
AL15
AM15
AR15
AP15
D3_MAA_B[15..0] 16,17
D3_WE_B# 16,17
D3_CAS_B# 16,17
D3_RAS_B# 16,17
D3_SBS_B[2..0] 16,17
D3_SCS_B_#0 16
D3_SCS_B_#1 16
D3_SCS_B_#2 17
D3_SCS_B_#3 17
D3_SCKE_B0 16
D3_SCKE_B1 16
D3_SCKE_B2 17
D3_SCKE_B3 17
D3_ODT_B0 16
D3_ODT_B1 16
D3_ODT_B2 17
D3_ODT_B3 17
D3_CK_DDR_B_DP0 16
D3_CK_DDR_B_DN0 16
D3_CK_DDR_B_DP1 16
D3_CK_DDR_B_DN1 16
D3_CK_DDR_B_DP2 17
D3_CK_DDR_B_DN2 17
D3_CK_DDR_B_DP3 17
D3_CK_DDR_B_DN3 17
DIMM_DQ_CPU_VREF_B 16,17,18
DIMM_DQ_CPU_VREF_A 14,15,18
C540
C540
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
D3_MAA_B10
D3_MAA_B11
D3_MAA_B12
D3_MAA_B13
D3_MAA_B14
D3_MAA_B15
D3_SCS_B_#0
D3_SCS_B_#1
D3_SCS_B_#2
D3_SCS_B_#3
D3_SCKE_B0
D3_SCKE_B1
D3_SCKE_B2
D3_SCKE_B3
C541
C541
*
*
0.1uF
0.1uF
D3_MAA_B0
D3_MAA_B1
D3_MAA_B2
D3_MAA_B3
D3_MAA_B4
D3_MAA_B5
D3_MAA_B6
D3_MAA_B7
D3_MAA_B8
D3_MAA_B9
D3_SBS_B0
D3_SBS_B1
D3_SBS_B2
D3_ODT_B0
D3_ODT_B1
D3_ODT_B2
D3_ODT_B3
*
*
width 10mil spacing 12mil,near CPU
DDR ECC IS NOT SUPPORTED ON DESKTOP SKUS
ECC TRACES ARE FOR ENGINEERING FUNCTION ONLY
DESIGN NOTE:
A A
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
1
10 50Thursday, April 26, 2012
10 50Thursday, April 26, 2012
10 50Thursday, April 26, 2012
1.0C
1.0C
1.0C
of
of
of
5
Title
Title
Title
CPU3-DDR3_CHB
CPU3-DDR3_CHB
CPU3-DDR3_CHB
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
4
3
2
1
G
C292
C292
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
3D3V_SYS
3D3V_DUAL
*
*
DS
2N7002
2N7002
R315
R315
*
*
10K
10K
+/-1%
+/-1%
Dummy
Dummy
R300
R300
*
*
4.7KOhm
4.7KOhm
+/-1%
+/-1%
Dummy
Dummy
1 2
R240
R240
10K
10K
Q40
Q40
#REFDE29#REFDE29
3D3V_SUS
G
C306
C306
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
VCCIO_SEL 43
R210
R210
*
*
220 Ohm
220 Ohm
+/-1%
+/-1%
Dummy
Dummy
V_1D05V_CPU
*
*
R269
R269
10K
10K
DS
Q42
Q42
2N7002
2N7002
FP_RST# 23,39
CPU_RST_N
D D
V_1D05V_CPU
H_VIDSCK_VR44
H_VIDSOUT_VR44
H_VIDALERT_N_VR44
MINIMIZE STUB BETWEEN THESE AND RESISTORS AT SINAI PAGE
PLACE IN CRB AREA
PCH_PECI22,38
H_PROCHOT_N44
PCH_THERMTRIP_N22
H_SKTOCC_N23
DMI/FDI TERMINATION VOLTAGE
C C
B B
DC COUPLED: TX/RX TO VCC ISF SAMPLED HIGH
DC COUPLED: TX/RX TO VSS IF SAMPLED LOW
AC COUPLED: TX SET TO VCC/2, RX SET TO VSS REGARDLESS OF THIS STRAP
PROC_SEL
For future processor compatibility
V_NAND_IO
R559
R559
*
*
2.2KOhm
2.2KOhm
+/-1%
+/-1%
R560 4.7KOhm +/-1%
R560 4.7KOhm +/-1%
*
*
C298
C298
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
PLACE R42, R45,C2 IN SOCKET CAVITY
V_SM
20110212 R381,R382 is 1k
on PDG 0.7
R381
R381
*
*
1K
1K
+/-1%
+/-1%
PRO_DDR_VREF
C437
C437
R382
R382
*
*
0.1uF
0.1uF
1K
1K
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
+/-1%
+/-1%
V_1D05V_CPU
R215
R215
R234
R234
*
*
51
51
+/-1%
+/-1%
Dummy
Dummy
DEFENSIVE SITE
*
*
1K
1K
+/-1%
+/-1%
Dummy
Dummy
R211
R211
*
*
1K
1K
+/-1%
+/-1%
Dummy
Dummy
*
*
RH5
RH5
51 Ohm
51 Ohm
Dummy
Dummy
NVR_CLE 24
H_THERMTRIP_N
H_CATERR_N
PCH_PECI
H_PWRGD
SWITCH_SEL_CPU
V_1D8V_SFR V_NAND_IO
TERMINATION IDEALLY TO BE
PLACED PLACE CLOSE TO EACH OTHER TO REDUCE STUB
NEXT TO IT OR WITHIN 1.5 OF CPU.
Place R216 & R213 near CPU
R213
R201
R201
*
*
91 Ohm
91 Ohm
+/-1%
+/-1%
Dummy
Dummy
H_DRAMPWRGD23
R697 33
R697 33
H_PROCHOT_N
PCH_THERMTRIP_N H_THERMTRIP_N
PROC_SEL
PRO_DDR_VREF
R301 1.5KOhm +/-1% Dummy
R301 1.5KOhm +/-1% Dummy
R213
R216
R216
*
*
*
*
75
75
110Ohm
110Ohm
+/-1%
+/-1%
+/-1%
+/-1%
H_PWRGD23,44
PLACE TRST* TERMINATION
ANYWHERE ON ROUTE.
H_PWRGD
R666
R666
H_PM_SYNC_022
*
*
R232 1.5KOhm +/-1% Dummy
R232 1.5KOhm +/-1% Dummy
*
*
R233 1.5KOhm +/-1% Dummy
R233 1.5KOhm +/-1% Dummy
*
*
R237 1.5KOhm +/-1% Dummy
R237 1.5KOhm +/-1% Dummy
*
*
R248 1.5KOhm +/-1% Dummy
R248 1.5KOhm +/-1% Dummy
*
*
R270 1.5KOhm +/-1% Dummy
R270 1.5KOhm +/-1% Dummy
*
*
*
*
R259 1.5KOhm +/-1% Dummy
R259 1.5KOhm +/-1% Dummy
*
*
R284 1.5KOhm +/-1% Dummy
R284 1.5KOhm +/-1% Dummy
*
*
R238 1.5KOhm +/-1% Dummy
R238 1.5KOhm +/-1% Dummy
*
*
R260 1.5KOhm +/-1% Dummy
R260 1.5KOhm +/-1% Dummy
*
*
R272 1.5KOhm +/-1% Dummy
R272 1.5KOhm +/-1% Dummy
*
*
R285 1.5KOhm +/-1% Dummy
R285 1.5KOhm +/-1% Dummy
*
*
R290 1.5KOhm +/-1% Dummy
R290 1.5KOhm +/-1% Dummy
*
*
R286 1.5KOhm +/-1% Dummy
R286 1.5KOhm +/-1% Dummy
*
*
R271 1.5KOhm +/-1% Dummy
R271 1.5KOhm +/-1% Dummy
*
*
R273 1.5KOhm +/-1% Dummy
R273 1.5KOhm +/-1% Dummy
*
*
R222
R222
1.5KOhm
1.5KOhm
*
*
*
*
+/-1%
+/-1%
Dummy
Dummy
Dummy
Dummy
PLACE TDO TERMINATION
NEAR XDP CONNECTOR
C_CPU_CLK_DP27
C_CPU_CLK_DN27
*
*
TPEV_SNB_PCUSTB_0
TPEV_SNB_PCUSTB_1
R221
R221
1.5KOhm
1.5KOhm
+/-1%
+/-1%
VIDALERT_N
124
124
CPU_RST_N
H_PM_SYNC_0
H_CATERR_N
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8CFG8
CFG9CFG9
CFG10
CFG11CFG11
CFG12CFG12
CFG13CFG13
CFG14CFG14
CFG15CFG15
H_TDO
H_TMS
H_TDI
H_TRST_N
H_PRDY_N
H_PROCHOT_N
H_TCK
AJ19
AJ33
AJ22
AT14
W2
W1
C37
B37
A37
J40
F36
E38
J35
E37
H34
G35
K32
H36
J36
J37
K36
L36
N35
L37
M36
J38
L35
M38
N36
N38
N39
N37
N40
G37
G36
AY3
H7
H8
U1E
U1E
BCLK[0]
BCLK#[0]
VIDSCLK
VIDSOUT
VIDALERT#
UNCOREPWRGOOD
SM_DRAMPWROK
RESET#
PM_SYNC
PECI
CATERR#
PROCHOT#
THERMTRIP#
SKTOCC#
FC_K32
SM_VREF
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD30
RSVD31
RSVD32
RSVD33
CPU_SKT_H2
CPU_SKT_H2
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
RN39
RN39
*
*
1
3
5
7 8
51 +/-5%
51 +/-5%
RN40
RN40
*
*
1
3
5
7 8
51 +/-5%
51 +/-5%
2
4
6
2
4
6
?
?
SKT_H2
SKT_H2
REV = 4
REV = 4
VCCIO_SELECT
VCCSA_SENSE
VCCIO_SENSE
VSSIO_SENSE
VSSAXG_SENSE
VSSAXG_SENSE
VCC_VALIDATION_SENSE
VSSU_VALIDATION_SENSE
VCCAXG_VALIDATION_SENSE
VSSGT_VALIDATION_SENSE
MISC
MISC
5 OF 11
5 OF 11
V_1D05V_CPU
VCCSA_VID_0
VCC_SENSE
VSS_SENSE
TRST#
PRDY#
PREQ#
DBR#
BCLK_ITP
BCLK_ITP#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
RSVD46
P33
P34
T2
VCCSA_SENSE
A36
VCC_SENSE
B36
VSS_SENSE
AB4
VCCP_SENSE
AB3
VSSP_SENSE
L32
VCCAXG_SENSE
M32
VSSAXG_SENSE
L39
H_TDO
TDO
L40
H_TDI
TDI
M40
H_TCK
TCK
L38
H_TMS
TMS
J39
H_TRST_N
K38
H_PRDY_N
K40
H_PREQ_N
E39
H_DBR_N
C40
ITP_CLKINP
D40
ITP_CLKINN
H40
TPEV_SNB_MBP0
H38
TPEV_SNB_MBP1
G38
TPEV_SNB_MBP2
G40
TPEV_SNB_MBP3
G39
TPEV_SNB_MBP4
F38
TPEV_SNB_MBP5
E40
TPEV_SNB_MBP6
F40
TPEV_SNB_MBP7
B39
J33
L34
L33
K34
N33
M34
AV1
AW2
L9
J9
K9
L31
J31
K31
AD34
AD35
?
?
PLTRST_N23,38
Need to be double checked.
VCCSA_VID 41
H_VCCSA_SENSE 41
H_VCC_SENSE 44
H_VSS_SENSE 44
H_VCCIO_SENSE 43
H_VSSIO_SENSE 43
H_VCCAGX_SENSE 44
H_VSSAGX_SENSE 44
TP15TP15
TP5TP5
TP4TP4
TP11TP11
TP12TP12
TP13TP13
TP8TP8
TP9TP9
TP10TP10
TP7TP7
TP6TP6
#REFDE32#REFDE32
1 2
A A
V_1D05V_CPU
*
*
R296
R296
10K
10K
Dummy
5
Dummy
Need check the power and the value of R221
according to the latest CPU datasheet
SWITCH_SEL_CPU
4
3
2
Title
Title
Title
CPU4-MSIC
CPU4-MSIC
CPU4-MSIC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
1
11 50Thursday, April 26, 2012
11 50Thursday, April 26, 2012
11 50Thursday, April 26, 2012
1.0C
1.0C
1.0C
of
of
of
Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
U1F
U1F
A12
VCC
D D
C C
B B
A13
A14
A15
A16
A18
A24
A25
A27
A28
B15
B16
B18
B24
B25
B27
B28
B30
B31
B33
B34
C15
C16
C18
C19
C21
C22
C24
C25
C27
C28
C30
C31
C33
C34
C36
D13
D14
D15
D16
D18
D19
D21
D22
D24
D25
D27
D28
D30
D31
D33
D34
D35
D36
E15
E16
E18
E19
E21
E22
E24
E25
E27
E28
E30
E31
E33
E34
E35
F15
F16
F18
F19
F21
F22
F24
F25
F27
F28
F30
F31
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
CPU_SKT_H2
CPU_SKT_H2
SKT_H2
SKT_H2
REV = 1.6
REV = 1.6
CPU POWER
CPU POWER
6 OF 11
6 OF 11
4
V_CPU_CORE
?
?
F32
VCC
F33
VCC
F34
VCC
G15
VCC
G16
VCC
G18
VCC
G19
VCC
G21
VCC
G22
VCC
G24
VCC
G25
VCC
G27
VCC
G28
VCC
G30
VCC
G31
VCC
G32
VCC
G33
VCC
H13
VCC
H14
VCC
H15
VCC
H16
VCC
H18
VCC
H19
VCC
H21
VCC
H22
VCC
H24
VCC
H25
VCC
H27
VCC
H28
VCC
H30
VCC
H31
VCC
H32
VCC
J12
VCC
J15
VCC
J16
VCC
J18
VCC
J19
VCC
J21
VCC
J22
VCC
J24
VCC
J25
VCC
J27
VCC
J28
VCC
J30
VCC
K15
VCC
K16
VCC
K18
VCC
K19
VCC
K21
VCC
K22
VCC
K24
VCC
K25
VCC
K27
VCC
K28
VCC
K30
VCC
L13
VCC
L14
VCC
L15
VCC
L16
VCC
L18
VCC
L19
VCC
L21
VCC
L22
VCC
L24
VCC
L25
VCC
L27
VCC
L28
VCC
L30
VCC
M14
VCC
M15
VCC
M16
VCC
M18
VCC
M19
VCC
M21
VCC
M22
VCC
M24
VCC
M25
VCC
M27
VCC
M28
VCC
M30
VCC
?
?
V_1D1V_AXG
AB33
AB34
AB35
AB36
AB37
AB38
AB39
AB40
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40
T33
T34
T35
T36
T37
T38
T39
T40
U33
U34
U35
U36
U37
U38
U39
U40
W33
W34
W35
W36
W37
W38
Y33
Y34
Y35
Y36
Y37
Y38
3
U1G
U1G
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
CPU_SKT_H2
CPU_SKT_H2
SKT_H2
SKT_H2
REV = 4
REV = 4
GFX POWERGFX POWER
GFX POWERGFX POWER
7 OF 11
7 OF 11
2
V_1D05V_CPU
M13
A11
A7
AA3
AB8
?
?
V_VCCSA
?
?
V_1D8V_SFR
AG33
AJ16
AJ17
AJ26
AJ28
AJ32
AK15
AK17
AK19
AK21
AK23
AK27
AK29
AK30
AK11
AK12
AF8
B9
D10
D6
E3
E4
G3
G4
J3
J4
J7
J8
L3
L4
L7
N3
N4
N7
R3
R4
R7
U3
U4
U7
V8
W3
H10
H11
H12
J10
K10
K11
L11
L12
M10
M11
M12
SKT_H2
SKT_H2
U1H
U1H
REV = 4
REV = 4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCPLL
VCCPLL
CPU_SKT_H2
CPU_SKT_H2
?
?
IO/SA/PLL
IO/SA/PLL
POWER
POWER
8 OF 11
8 OF 11
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
AJ13
AJ14
AJ23
AJ24
AR20
AR21
AR22
AR23
AR24
AU19
AU23
AU27
AU31
AV21
AV24
AV25
AV29
AV33
AW31
AY23
AY26
AY28
AJ20
?
?
1
V_SM
A A
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
1
12 50Thursday, April 26, 2012
12 50Thursday, April 26, 2012
12 50Thursday, April 26, 2012
1.0C
1.0C
1.0C
of
of
of
5
Title
Title
Title
CPU5-POWER
CPU5-POWER
CPU5-POWER
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
?
?
SKT_H2
SKT_H2
U1I
U1I
A17
VSS
A23
A26
A29
A35
AA33
AA34
AA35
D D
C C
B B
AA36
AA37
AA38
AD33
AD36
AD38
AD39
AD40
AE33
AE36
AF34
AF36
AF37
AF40
AG36
AH33
AH36
AH37
AH38
AH39
AH40
AJ12
AJ15
AJ18
AJ21
AJ25
AJ27
AJ36
AK10
AK13
AK14
AK16
AK22
AK28
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK40
AL11
AL14
AL17
AL19
AL24
AL27
AL30
AL36
AM11
AM14
AM17
AM21
AM23
AM25
AV39
AA6
AB5
AC1
AC6
AD5
AD8
AE3
AF1
AF5
AF6
AF7
AH2
AH3
AH5
AH8
AJ5
AK1
AK4
AK5
AK6
AK7
AK8
AK9
AL5
AM1
AM2
A4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_AK10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_NCTF
VSS_NCTF
CPU_SKT_H2
CPU_SKT_H2
REV = 4
REV = 4
9 OF 11
9 OF 11
?
?
4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
AM27
VSS
AM3
VSS
AM30
VSS
AM36
VSS
AM37
VSS
AM38
VSS
AM39
VSS
AM4
VSS
AM40
VSS
AM5
VSS
AN10
VSS
AN11
VSS
AN14
VSS
AN17
VSS
AN19
VSS
AN22
VSS
AN24
VSS
AN27
VSS
AN30
VSS
AN31
VSS
AN32
VSS
AN33
VSS
AN34
VSS
AN35
VSS
AN36
VSS
AN5
VSS
AN6
VSS
AN7
VSS
AN8
VSS
AN9
VSS
AP1
VSS
AP11
VSS
AP14
VSS
AP17
VSS
AP22
VSS
AP25
VSS
AP27
VSS
AP30
VSS
AP36
VSS
AP37
VSS
AP4
VSS
AP40
VSS
AP5
VSS
AR11
VSS
AR14
VSS
AR17
VSS
AR18
VSS
AR19
VSS
AR27
VSS
AR30
VSS
AR36
VSS
AR5
VSS
AT1
VSS
AT10
VSS
AT12
VSS
AT13
VSS
AT15
VSS
AT16
VSS
AT17
VSS
AT2
VSS
AT25
VSS
AT27
VSS
AT28
VSS
AT29
VSS
AT3
VSS
AT30
VSS
AT31
VSS
AT32
VSS
AT33
VSS
AT34
VSS
AT35
VSS
AT36
VSS
AT37
VSS
AT38
VSS
AT39
VSS
AT4
VSS
AT40
VSS
AT5
VSS
AT6
VSS
AT7
VSS
AT8
VSS
AT9
VSS
AU1
VSS
AU15
VSS
AU26
VSS
AU34
VSS
AU4
VSS
AU6
VSS
AU8
VSS
AV10
VSS
3
CPU_SKT_H2
AV11
AV14
AV17
AV35
AV38
AW10
AW11
AW14
AW16
AW36
AY11
AY14
AY18
AY35
AY37
U1K
U1K
VSS
VSS
VSS
AV3
VSS
VSS
VSS
AV6
VSS
VSS
VSS
VSS
VSS
VSS
AW6
VSS
VSS
VSS
VSS
VSS
AY4
VSS
AY6
VSS
AY8
VSS
B10
VSS
B13
VSS
B14
VSS
B17
VSS
B23
VSS
B26
VSS
B29
VSS
B32
VSS
B35
VSS
B38
VSS
B6
VSS
C11
VSS
C12
VSS
C17
VSS
C20
VSS
C23
VSS
C26
VSS
C29
VSS
C32
VSS
C35
VSS
C7
VSS
C8
VSS
D17
VSS
D2
VSS
D20
VSS
D23
VSS
D26
VSS
D29
VSS
D32
VSS
D37
VSS
D39
VSS
D4
VSS
D5
VSS
D9
VSS
E11
VSS
E12
VSS
E17
VSS
E20
VSS
E23
VSS
E26
VSS
E29
VSS
E32
VSS
E36
VSS
E7
VSS
E8
VSS
F1
VSS
F10
VSS
F13
VSS
F14
VSS
F17
VSS
F2
VSS
F20
VSS
F23
VSS
F26
VSS
F29
VSS
F35
VSS
F37
VSS
F39
VSS
F5
VSS
F6
VSS
F9
VSS
G11
VSS
G12
VSS
G17
VSS
G20
VSS
G23
VSS
G26
VSS
G29
VSS
G34
VSS
G7
VSS
VSS_NCTF
B3
VSS_NCTF
CPU_SKT_H2
G8
VSS
H1
VSS
H17
VSS
H2
VSS
H20
VSS
H23
VSS
H26
VSS
H29
VSS
H33
VSS
H35
VSS
H37
VSS
H39
VSS
H5
VSS
H6
VSS
H9
VSS
J11
VSS
J17
VSS
J20
VSS
J23
VSS
J26
VSS
J29
VSS
J32
VSS
K1
VSS
K12
VSS
K13
VSS
K14
VSS
K17
VSS
K2
VSS
K20
VSS
K23
VSS
K26
VSS
K29
VSS
K33
VSS
K35
VSS
K37
VSS
K39
VSS
K5
VSS
K6
VSS
L10
VSS
L17
VSS
L20
VSS
L23
VSS
L26
VSS
L29
VSS
L8
VSS
M1
VSS
M17
VSS
M2
VSS
M20
VSS
M23
VSS
M26
VSS
M29
VSS
M33
VSS
M35
VSS
M37
VSS
M39
VSS
M5
VSS
M6
VSS
M9
VSS
N8
VSS
P1
VSS
P2
VSS
P36
VSS
P38
VSS
P40
VSS
P5
VSS
P6
VSS
R33
VSS
R35
VSS
R37
VSS
R39
VSS
R8
VSS
T1
VSS
T5
VSS
T6
VSS
U8
VSS
V1
VSS
V2
VSS
V33
VSS
V34
VSS
V35
VSS
V36
VSS
V37
VSS
V38
VSS
V39
VSS
V40
VSS
V5
VSS
W6
VSS
Y5
VSS
Y8
VSS
2
U1_1
U1_1
PT44A11-6401
PT44A11-6401
?
?
SKT_H2
SKT_H2
U1J
U1J
REV = 4
REV = 4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
AB7
RSVD1
AD37
RSVD2
AG4
RSVD3
AJ29
RSVD4
AJ30
RSVD5
AJ31
RSVD6
AV34
RSVD7
AW34
RSVD8
P35
RSVD9
P37
RSVD10
P39
RSVD11
R34
RSVD12
R36
RSVD13
R38
RSVD14
R40
RSVD15
A38
NCTF1
AU40
NCTF2
AW38
NCTF3
C2
NCTF4
D1
NCTF5
SPARES
SPARES
10 OF 11
10 OF 11
CPU_SKT_H2
CPU_SKT_H2
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
1
AT11
AP20
AN20
AU10
AY10
AF4
AB6
AE6
AJ11
D38
C39
C38
J34
N34
?
?
A A
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
1
13 50Thursday, April 26, 2012
13 50Thursday, April 26, 2012
13 50Thursday, April 26, 2012
1.0C
1.0C
1.0C
of
of
of
5
Title
Title
Title
CPU6-GND
CPU6-GND
CPU6-GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
CHANNEL A DIMM 1
SMB ADDRESS:000
D D
D3_ODT_A1 9
D3_ODT_A0 9
195
167
68
79
53
ODT177ODT0
RSVD
NC/PAR_IN
NC/TEST4
NC/ERR_OUT
CB<0>39CB<1>40CB<2>45CB<3>46CB<4>
D3_DQS_A_DP0
7
158
159
164
165
CB<5>
CB<6>
CB<7>
4
D3_DQS_A_DP[7..0] 9,15
D3_DQS_A_DN[7..0] 9,15
D3_DM_A3
D3_DM_A2
D3_DM_A1
D3_DM_A0
D3_DQS_A_DN3
D3_DQS_A_DP3
D3_DQS_A_DP2
D3_DQS_A_DN2
D3_DQS_A_DN1
D3_DQS_A_DP1
D3_DQS_A_DN0
16
15
6
DQS<1>
DQS<0>
DQS*<0>
D3_DQS_A_DP4
D3_DQS_A_DN4
85
34
25
84
33
24
DQS<4>
DQS<3>
DQS<2>
DQS*<4>
DQS*<3>
DQS*<2>
DQS*<1>
D3_DQS_A_DN7
D3_DQS_A_DP7
D3_DQS_A_DP6
D3_DQS_A_DN6
D3_DQS_A_DN5
D3_DQS_A_DP5
112
103
94
111
102
93
DQS<7>
DQS<6>
DQS<5>
DQS*<6>
DQS*<5>
134
43
126
135
125
42
DQS9*
DQS<8>
DQS*<8>
DQS*<7>
DM0/DQS9
DM1/DQS10
D3_DM_A4
203
152
143
204
153
144
DQS12*
DQS11*
DQS10*
DM4/DQS13
DM3/DQS12
DM2/DQS11
3
D3_DATA_A26
D3_DATA_A25
D3_DATA_A24
D3_DATA_A23
D3_DATA_A22
D3_DATA_A21
D3_DATA_A20
D3_DATA_A19
D3_DATA_A18
D3_DATA_A17
D3_DATA_A16
D3_DATA_A15
D3_DATA_A14
D3_DATA_A13
D3_DATA_A12
D3_DATA_A11
D3_DATA_A10
D3_DATA_A9
D3_DATA_A8
D3_DATA_A7
D3_DATA_A6
D3_DATA_A5
D3_DATA_A4
D3_DATA_A3
D3_DATA_A2
D3_DATA_A1
D3_DATA_A0
D3_DM_A7
D3_DM_A6
D3_DM_A5
161
230
221
212
231
222
213
DQS15*
DQS14*
DQS13*
NC/DQS16*
DM7/DQS16
DM6/DQS15
DM5/DQS14
122
123
128
129
13
162
DQ<0>3DQ<1>4DQ<2>9DQ<3>10DQ<4>
DQS17*
DM8/DQS17
DDRIII
DDRIII
131
DQ<5>
DQ<6>
DQ<7>
DQ<8>12DQ<9>
DQ<10>18DQ<11>19DQ<12>
132
137
DQ<13>
138
DQ<14>
DQ<15>
140
DQ<16>21DQ<17>22DQ<18>27DQ<19>28DQ<20>
141
146
147
DQ<21>
DQ<22>
DQ<23>
DQ<24>30DQ<25>31DQ<26>36DQ<27>37DQ<28>
D3_DATA_A31
D3_DATA_A30
D3_DATA_A29
D3_DATA_A28
D3_DATA_A27
149
150
155
156
DQ<29>
DQ<30>
2
D3_DATA_A35
D3_DATA_A34
D3_DATA_A33
D3_DATA_A32
DQ<31>
DQ<32>81DQ<33>82DQ<34>87DQ<35>88DQ<36>
D3_DATA_A39
D3_DATA_A38
D3_DATA_A37
D3_DATA_A36
D3_DATA_A40
200
201
206
207
DQ<37>
DQ<38>
DQ<39>
D3_DATA_A44
D3_DATA_A43
D3_DATA_A42
D3_DATA_A41
209
DQ<40>90DQ<41>91DQ<42>96DQ<43>97DQ<44>
D3_DATA_A49
D3_DATA_A48
D3_DATA_A47
D3_DATA_A46
D3_DATA_A45
210
215
216
100
DQ<45>
DQ<46>
DQ<47>
DQ<48>99DQ<49>
D3_DATA_A54
D3_DATA_A53
D3_DATA_A52
D3_DATA_A51
D3_DATA_A50
105
106
218
219
224
DQ<50>
DQ<51>
DQ<52>
DQ<53>
D3_DATA_A58
D3_DATA_A57
D3_DATA_A56
D3_DATA_A55
225
108
109
114
DQ<54>
DQ<55>
DQ<56>
DQ<57>
DQ<58>
D3_DATA_A62
D3_DATA_A61
D3_DATA_A60
D3_DATA_A59
115
227
228
233
DQ<59>
DQ<60>
DQ<61>
DQ<62>
D3_DATA_A63
234
DIMM1
DIMM1
DDR III
DDR III
DQ<63>
1
D3_DATA_A[63..0] 9,15
BLUE
C C
FREE1
FREE2
198
187
FREE349FREE4
48
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VTT
VTT
239
235
232
229
226
223
220
217
214
211
208
205
202
199
166
163
160
157
154
151
148
145
142
139
136
133
130
127
124
120
240
121
VSS98VSS95VSS92VSS89VSS86VSS83VSS80VSS47VSS44VSS41VSS38VSS35VSS32VSS29VSS26VSS23VSS20VSS17VSS14VSS11VSS8VSS5VSS2VDDQ
119
116
113
110
107
104
101
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD78VDD75VDD72VDD69VDD66VDD65VDD62VDD60VDD57VDD54VDD51VDDSPD
197
194
191
189
186
183
182
179
176
173
170
VREFDQ1SCL
SDA
SA1
SA0
BA071BA1
CKE050CKE1
S0*
S1*76CK1/NU*64CK1/NU63CK0*
CK0
A261A3
A459A558A6
A756A9
A10/AP70A1155A12
A13
A14
A15
VREFCA
67
236
118
BA2
52
238
237
117
190
169
193
185
184A0188A1181
A8
180
178
175
177
CAS*74RAS*
WE*
RESET*
174
73
196
172
171
192
168
V_SM_VTT
CLOSE TO DIMM POWER PIN
V_SM
C535
C535
C536
C536
1.0uF
1.0uF
1.0uF
1.0uF
*
*
*
*
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
V_SM_VTT
B B
A A
C533
C533
*
*
10uF
10uF
C538
C538
C539
C539
C537
C537
1.0uF
1.0uF
0.1uF
0.1uF
1.0uF
1.0uF
*
*
*
*
*
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
*
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
C606
C606
*
*
0.1uF
0.1uF
V_SM
3D3V_SYS
D3_CA_VREF_A15,18
D3_DQ_VREF_A10,15,18
SMB_CLK_MAIN15,16,17,23,36
SMB_DATA_MAIN15,16,17,23,36
D3_SBS_A[2..0]9,15
D3_SCKE_A19
D3_SCKE_A09
D3_SCS_A_#19
D3_SCS_A_#09
D3_CK_DDR_A_DN19
D3_CK_DDR_A_DP19
D3_CK_DDR_A_DN09
D3_CK_DDR_A_DP09
D3_MAA_A[15..0]9,15
D3_CA_VREF_A
D3_DQ_VREF_A
D3_SBS_A2
D3_SBS_A1
D3_SBS_A0
D3_MAA_A0
D3_MAA_A1
D3_MAA_A2
D3_MAA_A3
D3_MAA_A4
D3_MAA_A5
D3_MAA_A6
D3_MAA_A7
D3_MAA_A8
D3_MAA_A9
D3_MAA_A10
D3_MAA_A11
D3_MAA_A12
D3_MAA_A13
D3_MAA_A14
D3_MAA_A15
D3_WE_A# 9,15
D3_RAS_A# 9,15
D3_CAS_A# 9,15
D3_DRAMRST# 9,15,16,17
5
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
DDR3-1:CHA_1
DDR3-1:CHA_1
DDR3-1:CHA_1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
FOXCONN PCEG
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
1
14 50Thursday, April 26, 2012
14 50Thursday, April 26, 2012
14 50Thursday, April 26, 2012
1.0C
1.0C
1.0C
of
of
of
Run Service TW Repair
5
Foxconn Confidential Document,please keep it secret. A1
CHANNEL A DIMM 2
SMB ADDRESS:001
D3_ODT_A3 9
D D
C C
B B
A A
D3_ODT_A2 9
53
195
167
68
79
ODT177ODT0
RSVD
NC/TEST4
NC/PAR_IN
NC/ERR_OUT
VSS
VSS
VSS
VSS
VSS
VTT
VTT
FREE1
FREE2
FREE349FREE4
48
239
235
232
229
226
223
120
240
198
187
V_SM_VTT
CLOSE TO DIMM POWER PIN
V_SM
C500
C500
C503
C503
C501
C501
1.0uF
1.0uF
1.0uF
1.0uF
1.0uF
1.0uF
*
*
*
*
*
*
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
V_SM_VTT
C655
C655
*
*
0.1uF
0.1uF
PLACE BETWEEN DIMM1 AND CPU
V_SM
EC46
EC46
EC45
EC45
820uF
820uF
820uF
820uF
*
*
*
*
*
*
+/-20%
+/-20%
+/-20%
+/-20%
Dummy
Dummy
Dummy
Dummy
CB<0>39CB<1>40CB<2>45CB<3>46CB<4>
VSS
220
*
*
EC47
EC47
820uF
820uF
+/-20%
+/-20%
D3_DQS_A_DN3
D3_DQS_A_DP3
D3_DQS_A_DP2
D3_DQS_A_DN2
D3_DQS_A_DN1
D3_DQS_A_DP1
D3_DQS_A_DP0
D3_DQS_A_DN0
158
159
164
165
25
16
7
24
15
6
CB<5>
CB<6>
CB<7>
DQS<2>
DQS<1>
DQS<0>
DQS*<1>
DQS*<0>
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
217
VSS
214
211
208
205
202
199
166
163
160
157
154
151
148
145
142
C498
C498
C499
C499
1.0uF
1.0uF
1.0uF
1.0uF
*
*
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
D3_DQS_A_DN7
D3_DQS_A_DP7
D3_DQS_A_DP6
D3_DQS_A_DN5
D3_DQS_A_DP5
D3_DQS_A_DP4
D3_DQS_A_DN4
D3_DQS_A_DN6
112
103
94
85
34
111
102
93
84
33
DQS<7>
DQS<6>
DQS<5>
DQS<4>
DQS<3>
DQS*<6>
DQS*<5>
DQS*<4>
DQS*<3>
DQS*<2>
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
139
136
133
130
127
124
121
119
116
113
110
107
104
101
D3_DQS_A_DP[7..0] 9,14
D3_DQS_A_DN[7..0] 9,14
D3_DM_A5
D3_DM_A4
D3_DM_A3
D3_DM_A2
D3_DM_A1
D3_DM_A0
221
212
203
152
143
134
213
204
153
144
135
43
125
126
42
DQS9*
DQS<8>
DQS*<8>
DQS*<7>
DM0/DQS9
VSS98VSS95VSS92VSS89VSS86VSS83VSS80VSS47VSS44VSS41VSS38VSS35VSS32VSS29VSS26VSS23VSS20VSS17VSS14VSS11VSS8VSS5VSS2VDDQ
DQS14*
DQS13*
DQS12*
DQS11*
DQS10*
DM5/DQS14
DM4/DQS13
DM3/DQS12
DM2/DQS11
DM1/DQS10
D3_DATA_A3
D3_DATA_A2
D3_DATA_A1
D3_DATA_A0
D3_DM_A7
D3_DM_A6
161
230
162
222
231
DQ<0>3DQ<1>4DQ<2>9DQ<3>10DQ<4>
DQS17*
DQS15*
NC/DQS16*
DM8/DQS17
DM7/DQS16
DM6/DQS15
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD78VDD75VDD72VDD69VDD66VDD65VDD62VDD60VDD57VDD54VDD51VDDSPD
197
194
191
189
186
183
182
179
176
173
170
D3_CA_VREF_A14,18
D3_DQ_VREF_A10,14,18
SMB_CLK_MAIN14,16,17,23,36
SMB_DATA_MAIN14,16,17,23,36
D3_SBS_A[2..0]9,14
D3_SCKE_A39
D3_SCKE_A29
D3_SCS_A_#39
D3_SCS_A_#29
D3_CK_DDR_A_DN39
D3_CK_DDR_A_DP39
D3_CK_DDR_A_DN29
D3_CK_DDR_A_DP29
D3_MAA_A[15..0]9,14
D3_DATA_A4
122
D3_DATA_A7
D3_DATA_A6
D3_DATA_A5
123
128
129
DQ<5>
DQ<6>
D3_SBS_A2
D3_SBS_A1
D3_SBS_A0
D3_MAA_A0
D3_MAA_A1
D3_MAA_A2
D3_MAA_A3
D3_MAA_A4
D3_MAA_A5
D3_MAA_A6
D3_MAA_A7
D3_MAA_A8
D3_MAA_A9
D3_MAA_A10
D3_MAA_A11
D3_MAA_A12
D3_MAA_A13
D3_MAA_A14
D3_MAA_A15
D3_DATA_A9
D3_DATA_A8
13
DQ<7>
DQ<8>12DQ<9>
3D3V_SYSV_SM
4
D3_DATA_A22
D3_DATA_A21
D3_DATA_A20
D3_DATA_A19
D3_DATA_A18
D3_DATA_A17
D3_DATA_A16
D3_DATA_A15
D3_DATA_A14
D3_DATA_A13
D3_DATA_A12
D3_DATA_A11
D3_DATA_A10
131
132
137
138
140
141
146
DQ<10>18DQ<11>19DQ<12>
DQ<13>
DQ<14>
DQ<15>
DQ<16>21DQ<17>22DQ<18>27DQ<19>28DQ<20>
DQ<21>
DDRIII
DDRIII
VREFDQ1SCL
SDA
SA1
VREFCA
67
236
118
238
237
117
D3_DATA_A23
147
DQ<22>
SA0
D3_DATA_A24
DQ<23>
DQ<24>30DQ<25>31DQ<26>36DQ<27>37DQ<28>
3D3V_SYS
3
D3_DATA_A[63..0] 9,14
D3_DATA_A39
D3_DATA_A38
D3_DATA_A37
D3_DATA_A36
D3_DATA_A35
D3_DATA_A34
D3_DATA_A33
D3_DATA_A32
D3_DATA_A31
D3_DATA_A30
D3_DATA_A29
D3_DATA_A28
D3_DATA_A27
D3_DATA_A26
D3_DATA_A25
149
150
155
156
DQ<29>
DQ<30>
DQ<31>
DQ<32>81DQ<33>82DQ<34>87DQ<35>88DQ<36>
D3_DATA_A48
D3_DATA_A47
D3_DATA_A46
D3_DATA_A45
D3_DATA_A44
D3_DATA_A43
D3_DATA_A42
D3_DATA_A41
D3_DATA_A40
200
201
206
207
209
210
215
216
DQ<37>
DQ<38>
DQ<39>
DQ<40>90DQ<41>91DQ<42>96DQ<43>97DQ<44>
DQ<45>
DQ<46>
DQ<47>
D3_DATA_A63
D3_DATA_A62
D3_DATA_A61
D3_DATA_A60
D3_DATA_A59
D3_DATA_A58
D3_DATA_A57
D3_DATA_A56
D3_DATA_A55
D3_DATA_A54
D3_DATA_A53
D3_DATA_A52
D3_DATA_A51
D3_DATA_A50
D3_DATA_A49
100
105
106
218
219
224
225
108
109
114
115
227
228
233
234
DIMM2
DIMM2
DDRIII
DQ<48>99DQ<49>
DDRIII
DQ<50>
DQ<51>
DQ<52>
DQ<53>
DQ<54>
DQ<55>
DQ<56>
DQ<57>
DQ<58>
DQ<59>
DQ<60>
DQ<61>
DQ<62>
DQ<63>
2
1
WHITE
BA071BA1
CKE050CKE1
S0*
S1*76CK1/NU*64CK1/NU63CK0*
CK0
A261A3
A459A558A6
A756A9
A10/AP70A1155A12
A13
A14
A15
CAS*74RAS*
BA2
52
190
169
193
185
184A0188A1181
180
178
WE*
RESET*
73
175
174
196
172
171A8177
192
168
D3_WE_A# 9,14
D3_RAS_A# 9,14
D3_CAS_A# 9,14
D3_DRAMRST# 9,14,16,17
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
DDR3-2:CHA_2
DDR3-2:CHA_2
DDR3-2:CHA_2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Q77M01-1.0
Q77M01-1.0
Q77M01-1.0
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
1.0Custom
1.0Custom
1.0Custom
of
of
of
15 50Thursday, April 26, 2012
15 50Thursday, April 26, 2012
15 50Thursday, April 26, 2012
Loading...