Fairchild Semiconductor DM74LS74ASJX, DM74LS74ASJ, DM74LS74AN, DM74LS74AMX, DM74LS74AM Datasheet
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© 2000 Fairchild Semiconductor Corporation DS006373 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
DM74LS74A
Dual Positive-Edge-Triggered D Flip-Flops with
Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-triggered D flip-flo ps with complementary outputs. The info rmation on the D inp ut is accepted by the f lip-flops on the
positive going edge of the clock pulse. The triggering
occurs at a voltage level and is not directly r elated to the
transition time of the rising edg e of the clock. The data on
the D input may be changed while the clock is LOW or
HIGH without affecting the outputs as long as the data
setup and hold times are not violated . A low logic level on
the preset or clear inputs will set or reset the outputs
regardless of the logic levels of the other inputs.
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram Function Table
H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
L = LOW Logic Level
↑ = Positive-going Transition
Q0 = The out put logic lev el of Q be fore the in dica ted input con ditio ns were
established.
Note 1: This configuration is nonstable; that is, it will not persist when either
the preset and/or clear inputs return to thei r inactive (HIGH) level.
Order Number Package Number Package Description
DM74LS74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS85ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
PR CLR CLK D Q Q
LHXX H L
HLXX L H
L L X X H (Note 1) H (Note 1)
HH↑ HH L
HH↑ LL H
HHLX Q
0
Q
0
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DM74LS74A
Absolute Maximum Ratings(Note 2)
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the co ndition s
for actual device operation.
Recommended Operating Conditions
Note 3: CL = 15 pF, RL = 2 kΩ, TA = 25°C, and VCC = 5V.
Note 4: C
L
= 50 pF, RL = 2 kΩ, TA = 25°C, and VCC = 5V.
Note 5: The symbol (↑) indicates the rising edge of the clock pulse is used fo r ref erence.
Note 6: T
A
= 25°C and VCC = 5V.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Symbol Parameter Min Nom Max Units
V
CC
Supply Voltage 4.75 5 5.25 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current −0.4 mA
I
OL
LOW Level Output Current 8 mA
f
CLK
Clock Frequency (Note 3) 0 25 MHz
f
CLK
Clock Frequency (Note 4) 0 20 MHz
t
W
Pulse Width Clock HIGH 18
(Note 3) Preset LOW 15 ns
Clear LOW 15
t
W
Pulse Width Clock HIGH 25
(Note 4) Preset LOW 20 ns
Clear LOW 20
t
SU
Setup Time (Note 3)(Note 5) 20↑ ns
t
SU
Setup Time (Note 4)(Note 5) 25↑ ns
t
H
Hold Time (Note 5)(Note 6) 0↑ ns
T
A
Free Air Operating Temperature 0 70 °C
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