Fairchild Semiconductor DM74LS73AN, DM74LS73AM, DM74LS73ACW Datasheet

© 2000 Fairchild Semiconductor Corporation DS006372 www.fairchildsemi.com

August 1986
Revised March 2000

DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

DM74LS73A
Dual Negative-Edge-Triggered Master-Slave

J-K Flip-Flops with Clear and Complementary Outputs

General Description

This device contains two indepe ndent negative-edge-trig­gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip -flops on the fall ing edge of
the clock pulse. The clock triggering occurs at a volta ge
level and is not directly re lated to the transition time of the
negative going edge of the clock pulse. The data on the J
and K inputs is allowed to change while the clock is HIGH
or LOW without affecting the output s as long a s setup and
hold times are not violated. A low logic level on the clear
input will reset the outputs regardless of the levels of the
other inputs.

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram Function Table

H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
↓ = Negative going edge of pulse.
Q0 = Th e output logic level before the indicated input conditions were
established.
Toggle = Each output changes to the complement of its previous level on
each falling edge of th e c lock pulse.

Order Number Package Number Package Description

DM74LS73AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS73AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Outputs

CLR CLK J K Q Q

LXXXL H
H ↓ LL Q

0

Q

0

H ↓ HL H L
H ↓ LH L H
H ↓ H H Toggle

HHXXQ

0

Q

0

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DM74LS73A

Absolute Maximum Ratings(Note 1)

Note 1: The “Absolute Maximum Ratin gs” are those v alues beyon d which

the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the co ndition s
for actual device operation.

Recommended Operating Conditions

Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.
Note 3: C

L

= 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.

Note 4: The symbol (↓) indicates the falling edge of the clock puls e is used for reference.

Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

V

CC

Supply Voltage 4.75 5 5.25 V

V

IH

HIGH Level Input Voltage 2 V

V

IL

LOW Level Input Voltage 0.8 V

I

OH

HIGH Level Output Current −0.4 mA

I

OL

LOW Level Output Current 8 mA

f

CLK

Clock Frequency (Note 2) 0 30 MHz

f

CLK

Clock Frequency (Note 3) 0 25 MHz

t

W

Pulse Width Clock HIGH 20
(Note 2) Preset LOW 25 ns

Clear LOW 25

t

W

Pulse Width Clock HIGH 25
(Note 3) Preset LOW 30 ns

Clear LOW 30

t

SU

Setup Time (Note 2)(Note 4) 20↓ ns

t

SU

Setup Time (Note 3)(Note 4) 25↓ ns

t

H

Hold Time (Note 2)(Note 4) 0↓ ns

t

H

Hold Time (Note 3)(Note 4) 5↓ ns

T

A

Free Air Operating Temperature 0 70 °C