Fairchild Semiconductor DM74LS503N Datasheet

DM74LS503
8-Bit Successive Approximation Register
(with Expansion Control)

DM74LS503 8-Bit Successive Approximation Register

March 1989
Revised March 2000

General Description

The DM74LS503 register has an active LOW Enable (E)
input that is used in cascading two or more packages f or
longer word lengths. A HIGH signal on E
operation, forces Q7 HIG H and prevents the device from
accepting serial data. With the E
connected to the CC
cant) device, the DM74LS503 will be inhibited until the pre­ceding device is filled, causing its CC
This LOW signal then enables the D M74LS503 to accept
the serial data on subsequent clocks.

output of a precedin g (more signifi-

, after a START

input of an DM7 4LS503

output to go LOW.

Features

■ Performs serial-to-parallel conversion

■ Expansion control for longer words

■ Storage and control for successive approximation A to D

conversion

■ Low power Schottky version of 2503

Ordering Code:

Order Number Package Number Package Description

DM74LS503N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection Diagram Logic Symbol

VCC = Pin 16
GND = Pin 8

Pin Descriptions

Pin Names Description

D Serial Data Input
S
CP Clock Pulse Input (Active Rising Edge)
E
CC

Q0–Q7 Parallel Register Outputs

7 Complement of Q7 Output

Q

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Start Input (Active LOW)

Conversion Enable Input (Active LOW)
Conversion Complete Output (Active LOW)

Logic Diagrams

DM74LS503

Note: Cell logic is repeated fo r register stages Q5 to Q1.

Connection for Longer Word Lengths

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