Fairchild Semiconductor DM74LS373WMX, DM74LS373WM, DM74LS373SJX, DM74LS373SJ, DM74LS373N Datasheet

© 2000 Fairchild Semiconductor Corporation DS006431 www.fairchildsemi.com

April 1986
Revised March 2000

DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

DM74LS373 • DM74LS374
3-STATE Octal D-Type Transparent Latches

and Edge-Triggered Flip-Flops

General Description

These 8-bit register s feature totem-pole 3- STATE outputs
designed specifically fo r driving highly-capacitive or rela­tively low-impedance loa ds. Th e hi gh -im ped ance state and
increased high-logic level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bu s-or ga nized sy stem w ith ou t n eed fo r inter­face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.

The eight latches of the DM74LS373 are transparent D­type latches meaning that while the enable (G) is HIGH the
Q outputs will follow the data (D) inputs. When the enable
is taken LOW the outp ut will be latched at th e level of the
data that was set up.

The eight flip-flop s of the DM74L S374 are edge- triggered
D-type flip flops. On the positive transitio n of the clock, the
Q outputs will be set to the logic states that were set up at
the D inputs.

A buffered output control input ca n be used to place the
eight outputs in either a normal l ogic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped­ance state the outputs ne ither load nor dr ive the bus lines
significantly.

The output control does not affect the i nternal oper ation of
the latches or flip-flops. That is, the old data can be
retained o r ne w d ata c a n be e nte re d ev e n whi l e t h e ou t put s
are OFF.

Features

■ Choice of 8 latches or 8 D-type flip-flops in a single
package

■ 3-STATE bus-driving outputs

■ Full parallel-access for loading

■ Buffered control inputs

■ P-N-P inputs reduce D-C loading on data lines

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Order Number Package Number Package Description

DM74LS373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74LS374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
IDM29901NC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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DM74LS373 • DM74LS374

Connection Diagrams

DM74LS373 DM74LS374

Function Tables

DM74LS373 DM74LS374

H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Don’t Care Z = High Impedance State
↑ = Transition from LOW-to-HIGH lev el Q

0

= The level of the output before steady-stat e input conditions were es t ablished.

Logic Diagrams

DM74LS373

Transparent Latches

DM74LS374

Positive-Edge-Triggered Flip-Flops

Output Enable

D Output

Control G

LHHH
LHLL
LLXQ

0

HXXZ

Output

Clock D Output

Control

L ↑ HH
L ↑ LL
LLXQ

0

HXXZ

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DM74LS373 • DM74LS374

Absolute Maximum Ratings(Note 1)

Note 1: The “Absolute Maximum Ratings ” are those val ues beyond w hich

the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the condition s
for actual device operation.

DM74LS373 Recommended Operating Conditions

Note 2: The symbol (↓) indicates the falling edge of the clock pulse is us ed for reference.
Note 3: T

A

= 25°C and VCC = 5V.

DM74LS373 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 4: All typicals are at VCC = 5V, TA = 25°C.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Supply Voltage 7V
Input Voltage 7V
Storage Temperature Range −65°C to +150°C
Operating Free Air Temperature Range 0°C to +70°C

Symbol Parameter Min Nom Max Units

V

CC

Supply Voltage 4.75 5 5.25 V

V

IH

HIGH Level Input Voltage 2 V

V

IL

LOW Level Input Voltage 0.8 V

I

OH

HIGH Level Output Current −2.6 mA

I

OL

LOW Level Output Current 24 mA

t

W

Pulse Width Enable HIGH 15

ns

(Note 3) Enable LOW 15

t

SU

Data Setup Time (Note 2) (Note 3) 5↓ ns

t

H

Data Hold Time (Note 2) (Note 3) 20↓ ns

T

A

Free Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min

Typ

Max Units

(Note 4)

V

I

Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V

V

OH

HIGH Level VCC = Min, IOH = Max

2.4 3.1 V

Output Voltage VIL = Max, VIH = Min

V

OL

LOW Level VCC = Min, IOL = Max
Output Voltage VIL = Max, VIH = Min 0.35 0.5 V

IOL = 12 mA, VCC = Min 0.4

I

I

Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA

I

IH

HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA

I

IL

LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA

I

OZH

Off-State Output Current with VCC = Max, VO = 2.7V

20 µA

HIGH Level Output Voltage Applied VIH = Min, VIL = Max

I

OZL

Off-State Output Current with VCC = Max, VO = 0.4V

−20 µA

LOW Level Output Voltage Applied VIH = Min, VIL = Max

I

OS

Short Circuit Output Current VCC = Max (Note 5) −50 −225 mA

I

CC

Supply Current VCC = Max, OC = 4.5V,

24 40 mA

Dn, Enable = GND