Fairchild Semiconductor DM74LS298N Datasheet
October 1988
Revised March 2000
DM74LS298
Quad 2-Port Register Multiplexer with Storage
DM74LS298 Quad 2-Port Register Multiplexer with Storage
General Description
The DM74LS298 is a qua d 2-port regist er. It is the logical
equivalent of a quad 2-input multiplexer followed by a quad
4-bit edge-triggered register. A Common Select input
selects between two 4-bit input ports (data sources). T he
selected data is tra nsferred t o the outp ut register synchronous with the HIGH-to-LOW transition of the Clock input.
Features
■ Select from two data sources
■ Fully edge-triggered operation
■ Typical power d issipation of 65 mW
Ordering Code:
Order Number Package Number Package Description
DM74LS298N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Logic Symbol
VCC = Pin 16
GND = Pin 8
Pin Descriptions
Pin Names Description
S Common Select Inputs
CP
I0
I1
Q
, I0
a
, I1
a
, Q
a
Clock Pulse Input (Active Falling Edge)
Source 0 Data Inputs
d
Source 1 Data Inputs
d
Flip-Flip Outputs
d
Connection Diagram
Truth Table
Inputs Output
SI0
ll X L
lh X H
hX l L
hX h H
l = LOW Voltage L evel one setup time prio r to the HIGH-to-LOW clo ck
transition.
h = HIGH Voltage Level one se tup time prior to the HIGH-to-LOW clo ck
transition.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
x
I1
x
Q
x
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Functional Description
This device is a high speed quad 2- port regi ster. It selects four bits of data from two so urces (p orts) un der the control of a
Common Select input (S). Th e selected data is tra nsferr ed to the 4-b it output re gister synch ronou s with the HIGH -to-LO W
transition of the Clock input (CP
need be stable only one setup time prior to the HIGH-to-LOW transition of the clock for predictable operation.
DM74LS298
). The 4-bit output register is fully edge-triggered. The Data inputs (Inx) and Select input (S)
Logic Diagram
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