Fairchild Semiconductor DM74AS874WMX, DM74AS874WM, DM74AS874NT Datasheet

© 2000 Fairchild Semiconductor Corporation DS006331 www.fairchildsemi.com

October 1986
Revised March 2000

DM74AS874 Dual 4-Bit D-Type Edge-Triggered Flip-Flop

DM74AS874
Dual 4-Bit D-Type Edge-Triggered Flip-Flop

General Description

These dual 4-bit inverting reg isters feature totem-pole 3­STATE outputs designed specifically for driving highly­capacitive or relatively low-impedance loads. The high­impedance state and incr eased high-logic-level dri ve pro­vide these registers with the capab ility of being connected
directly to and driving the bus lines in a bus-o rga nized sys­tem without need for inte rface or pull-up components. They
are particularly attrac tive for implem enting buffer re gisters,
I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops of the DM74 AS874 are edge-trigg ered
D-type flip-flops. On t he po sitive t ran sition o f the clock, t he
Q outputs will be set to the logic states that were set up at
the D inputs.

A buffered output control input ca n be used to place the
eight outputs in either a normal l ogic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped­ance state the outputs ne ither load nor dr ive the bus lines
significantly.

The output control does not affect the i nternal oper ation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.

The pinout is arra nge d to ease printed circu it b oa rd layo ut.
All data inputs are on one sid e of the package, while all
outputs are on the other side.

Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V

CC

range

■ Advanced oxide-isolated, ion-implanted Schottky TTL
process

■ 3-STATE buffer-type output s drive bus lines directly

■ Space saving 300 mil wide package

■ Bus structured pinout

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram

Order Number Package Number Package Description

DM74AS874WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS874NT N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

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DM74AS874

Function Table

L = LOW State
H = HIGH State
X = Don’t Care
↑ = Positive Edge Transition
Z = High Impedance State
Q

0

= Previous Condit ion of Q

Logic Diagram

Inputs Output

CLR

DCLKOC Q

XXXHZ
LXXLL
HH↑ LH
HL↑ LL
HXLLQ

0