Fairchild Semiconductor DM74AS651WMX, DM74AS651WM, DM74AS651NT Datasheet
© 2000 Fairchild Semiconductor Corporation DS006325 www.fairchildsemi.com
October 1986
Revised March 2000
DM74AS651 • DM74AS652 Octal Bus Transceiver and Register
DM74AS651 • DM74AS652
Octal Bus Transceiver and Register
General Description
These devices incorporate an octal transceiver and an
octal D-type register configured to enab le transmission of
data from bus to bus or internal register to bus. The
DM74AS651 offers 64-In dustria l grade pr oduct gua ranteeing performance from −40°C to +85°C.
These bus transceivers featur e totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The hig h-impedance stat e
and increased high-lo gic-level driv e provide th ese devices
with the capability of being connected directly to and driving the bus lines in a bus- organized system without ne ed
for interface or pull-up componen ts. They are particularly
attractive for imple menting buffer registers, I /O ports, bidirectional bus drivers, and working registers.
The registers in the DM74AS651 and DM74AS652 are
edge-triggered D-type flip- flops. On the positive transition
of the clock (CAB or CBA), the input data is stored.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A LOW
input level selects real-time data and a HIGH level selects
stored data. The select controls have a “make before
break” configuration to eliminate a glitch which wo uld normally occur in a typical multiplexer during the transition
between stored and real-time data.
The Enable (GAB and G
BA) control pins provide four
modes of operation; r eal-time data tr ansfer from b us A-toB, real-time data t ransfer from bus B-to -A, real-ti me bus A
and/or B data transfer to internal storage, or internal stored
data transfer to bus A and/or B.
Features
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full tempera-
ture and V
CC
range
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
■ 3-STATE buffer-type outputs drive bus lines directly
■ Guaranteed performance over industrial temperature
range (−40°C to +85°C) in 64-grade pr oducts
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Order Number Package Number Package Description
DM74AS651WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS651NT N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
DM74AS652WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS652NT N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
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DM74AS651 • DM74AS652
Connection Diagram
Function Table
H = HIGH Level
L = LOW Level
X = Irrelevant
↑ = LOW-to-HIGH Transition
Note 1: The data ou tp ut fu nc t ions may be enabled o r dis abled by various signal s at the GAB and G
BA inputs. Data input fu nc t ions are always enabled,
i.e., data at the bus pins will be stored on eve ry LOW -t o-HIGH transition on th e c lock inputs.
Note 2: If the select control is LOW, the clocks can occur simultaneously. If the select control is HIGH, the clocks must be staggered in order to load bot h
registers.
INPUTS
DATA I/O (Note 1)
OPERATION OR FUNCTION
GAB GBA CAB CBA SAB SBA
A1 B1
DM74AS651 DM74AS652THRU THRU
A8 B8
L H H or L H or L X X
Input Input
Isolation Isolation
LH ↑↑X X Store A and B Data Store A and B Data
LL X X X L
Output Input
Real Time B Data to A Bus Real Time B Data to A Bus
L L X H or L X H Stored B Data to A Bus Stored B Data to A Bus
HH X X L X
Input Output
Real Time A Data to B Bus Real Time A Data to B Bus
H H H or L X H X Stored A Data to B Bus Stored A Data to B Bus
H L H or L H or L H H Output Output
Stored A Data to B Bus Stored A Data to B Bus
& Stored B Data to A Bus & Stored B Data to A Bus
XH ↑ H or L X X Input
Unspecified
(Note 1)
Store A, Hold B Store A, Hold B
HH ↑↑
X
(Note
2)
X Input Output Store A in both registers Store A in both registers
LXH or L↑ XX
Unspecified
(Note 1)
Input Hold A, Store B Hold A, Store B
LL ↑↑X
X
(Note
2)
Output Input Store B in both registers Store B in both registers
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DM74AS651 • DM74AS652
Logic Diagrams
DM74AS651 DM74AS652
Schematics of Inputs and Outputs
Equivalent of All Other Inputs Typical of All DM74AS651, DM74AS652 Outputs