Fairchild Semiconductor DM74AS573N, DM74AS573WMX, DM74AS573WM Datasheet

© 2000 Fairchild Semiconductor Corporation DS006313 www.fairchildsemi.com

October 1986
Revised March 2000

DM74AS573 Octal D-Type Transparent Latch with 3-STATE Outputs

DM74AS573
Octal D-Type Transparent Latch with 3-STATE Outputs

General Description

These 8-bit register s feature totem-pole 3- STATE outputs
designed specifically fo r driving highly-capacitive or rela­tively low-impedance loa ds. Th e hi gh -im ped ance state and
increased HIGH-logic-level drive provide these registers
with the capability of being connected directly to and driv­ing the bus lines in a bus- organized system without ne ed
for interface or pull-up componen ts. They are particularly
attractive for imple menting buffer registers, I /O ports, bidi­rectional bus drivers, and working registers.

The eight latches of the DM74AS573 are transparent D­type latches, meaning that while the enable (G) is HIGH
the Q outputs will follow the data (D) inputs. When the
enable is taken LOW the output will be latched at the level
of the data that was set UP.

A buffered output control input ca n be used to place the
eight outputs in either a normal l ogic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped­ance state the outputs ne ither load nor dr ive the bus lines
significantly.

The output control does not affect the i nternal oper ation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.

The pin-out is arranged to ease printed circuit board layout.
All data inputs are on one side of the package whil e all the
outputs are on the other side.

Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V

CC

range

■ Advanced oxide-isolated, ion-implanted Schottky TTL
process

■ Functionally equivalent with DM74S373

■ Improved AC performance over DM74S373 at approxi-

mately half the power

■ 3-STATE buffer-type outputs drive bus lines directly

■ Bus structured pinout

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram

Order Number Package Number Package Description

DM74AS573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS573N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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DM74AS573

Function Table

L = LOW State
H = HIGH State
X = Don’t Care
Z = High Impedance State
Q0 = Previous Condit ion of Q

Logic Diagram

Output Enable Output

Control G D Q

L HHH
LHLL
LLXQ

0

HXXZ