Fairchild Semiconductor DM74AS374WMX, DM74AS374WM, DM74AS374N Datasheet

© 2000 Fairchild Semiconductor Corporation DS006310 www.fairchildsemi.com

October 1986
Revised March 2000

DM74AS374 Octal D-Type Edge-Tr iggered Flip-Flops with 3-STATE Outputs

DM74AS374
Octal D-Type Edge-Triggered Flip-Flops

with 3-STATE Outputs

General Description

These 8-bit register s feature totem-pole 3- STATE outputs
designed specifically fo r driving highly-capacitive or rela­tively low-impedance loa ds. Th e hi gh -im ped ance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bu s-or ga nized sy stem w ith ou t n eed fo r inter­face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.

The eight flip-flops of the AS374 are edge-triggered D-type
flip-flops. On the p ositive tr ansiti on o f the clock, t he Q out­puts will be set to the logic states that wer e set u p a t the D
inputs.

A buffered output control input ca n be used to place the
eight outputs in either a normal l ogic state (HIGH or LOW
logic levels) or a high impe dance state. In the high-i mped­ance state the outputs ne ither load nor dr ive the bus lines
significantly.

The output control does not affect the i nternal oper ation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V

CC

range

■ Advanced oxide-isolated, ion-implanted Schottky TTL
process

■ Functionally and pin-for -p i n com pat ib le wi th LS and ALS
TTL counterparts

■ Improved AC perform ance over LS and A LS TTL coun­terparts

■ 3-STATE buffer-type outputs drive bus lines directly

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram

Order Number Package Number Package Description

DM74AS374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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DM74AS374

Function Table

L = LOW State
H = HIGH State
X = Don’t Care
↑ = Positive Edge Transition
Z = High Impedance State
Q

0

= Previous Condit ion of Q

Logic Diagram

Output Clock D Output

Control Q

L ↑ HH
L ↑ LL
LLXQ

0

HXXZ