Fairchild Semiconductor DM74AS373WMX, DM74AS373WM, DM74AS373N Datasheet

© 2000 Fairchild Semiconductor Corporation DS006309 www.fairchildsemi.com

April 1984
Revised March 2000

DM74AS373 Octal D-Type Transparent Latch with 3-STATE Outputs

DM74AS373
Octal D-Type Transparent Latch with 3-STATE Outputs

General Description

These 8-bit register s feature totem-pole 3- STATE outputs
designed specifically fo r driving highly-capacitive or rela­tively low-impedance loa ds. Th e hi gh -im ped ance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bu s-or ga nized sy stem w ith ou t n eed fo r inter­face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.

The eight latches of the DM74AS373 are transparent D­type latches, meaning that while the enable (G) is HIGH
the Q outputs will follow the data (D) inputs. When the
enable is taken LOW the output will be latched at the level
of the data that was set up.

A buffered output control input ca n be used to place the
eight outputs in either a normal l ogic state (HIGH or LOW
logic levels) or a high impe dance state. In the high-im ped­ance state the outputs ne ither load nor dr ive the bus lines
significantly.

The output control does not affect the i nternal oper ation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.

Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V

CC

range

■ Advanced oxide-isolated, ion-implanted Schottky TTL
process

■ Functionally and pin for pin compatible w ith LS a nd AL S
TTL counterparts

■ Improved AC perform ance over LS and A LS TTL coun­terparts

■ 3-STATE buffer-type outputs drive bus lines directly

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram

Order Number Package Number Package Description

DM74AS373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74AS373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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DM74AS373

Logic Diagram Function Table

L = LOW State
H = HIGH State
X = Don’t Care
Z = High Impedance State

Q

0

= Previous Condition of Q

Output Enable Output

Control G D Q

LHHH
LHLL
LLXQ

0

HXXZ