Fairchild Semiconductor CD40174BCN, CD40174BCMX, CD40174BCM Datasheet

© 1999 Fairchild Semiconductor Corporation DS005987 www.fairchildsemi.com

October 1987
Revised July 1999

CD40174BC • CD40175BC Hex D-Type Flip-Flop • Quad D-Type Flip-Flop

CD40174BC • CD40175BC
Hex D-Type Flip-Flop • Quad D-Type Flip-Flop

General Description

The CD40174BC con sis ts o f six po si tive- ed ge tri g ger ed D­type fli p-flops; the true outputs from each fli p-flop are exter­nally available. The CD40175BC consists of four positive­edge triggered D-typ e flip-flo ps; both the tr ue and co mple­ment outputs from each flip-flop are externally available.

All flip-flops are controlled by a common clock a nd a com­mon clear. Information at the D inputs meeti ng the set-up
time requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse. The clea ring op er a­tion, enabled by a ne gative pulse at Clear inpu t, clears all

Q outputs to logical “0” and Q

s (CD40175BC only) to logi-

cal “1”.
All inputs are protected from static discharge by diode

clamps to V

DD

and VSS.

Features

■ Wide supply voltage range: 3V to 15V

■ High noise immunity: 0.45 V

DD

(typ.)

■ Low power TTL compatibility:
fan out of 2 driving 74L or 1 driving 74 LS

■ Equivalent to MC14174B, MC14175B

■ Equivalent to MM74C174, MM74C175

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagrams

Pin Assignments for DIP and SOIC

CD40174B

Top View

CD40175B

Top View

Order Number Package Number Package Description

CD40174BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CD40174BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD40175BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CD40175BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2

CD40174BC • CD40175BC

Truth Table

H = HIGH Level
L = LOW Level
X = Irrelevant
↑ = Transition from LOW-to-HIGH lev el

NC = No change
Note 1: Q

for CD40175B only

Inputs Outputs

Clear Clock D Q Q

(Note 1)

LXXLH
H ↑ HHL
H ↑ LLH
HHXNCNC
HLXNCNC

3 www.fairchildsemi.com

CD40174BC • CD40175BC

Absolute Maximum Ratings(Note 2)

(Note 3)

Recommended Operating
Conditions

(Note 3)

Note 2: “Absolute Maximum Ratings” are those values beyond which the
safety of the device can not be guaranteed. T hey are not meant to imply
that the devices should be operated at these lim its. The tab les of “Recom ­mended Operating Conditions” and “Electrical Characteristics” provide con­ditions for actual dev ic e operation.

Note 3: V

SS

= 0V unless otherw is e s pecified.

DC Electrical Characteristics (Note 3)

CD40174BC/CD40175BC

Note 4: IOH and IOL are tested one output at a ti m e.

DC Supply Voltage (VDD) −0.5V to +18V
Input Voltage (V

IN

) −0.5V to VDD +0.5V

DC

Storage Temperature Range (TS) −65°C to +150°C
Power Dissipation (P

D

)
Dual-In-Line 700 mW
Small Outline 500 mW

Lead Temperatu re (T

L

)
(Soldering, 10 seconds) 260°C

DC Supply Voltage (V

DD

) 3V to 15 V

DC

Input Voltage (VIN) 0V to VDD V

DC

Operating Temperature Range (TA) −40°C to +85°C

Symbol Parameter Conditions

−40°C +25°C +85°C

Units

Min Max Min Typ Max Min Max

I

DD

Quiescent Device VDD = 5V, VIN = VDD or V

SS

4430µA

Current VDD = 10V, VIN = VDD or V

SS

8860µA

VDD = 15V, VIN = VDD or V

SS

16 16 120 µA

V

OL

LOW Level VDD = 5V 0.05 0.05 0.05 V
Output Voltage VDD = 10V 0.05 0.05 0.05 V

VDD = 15V 0.05 0.05 0.05 V

V

OH

HIGH Level VDD = 5V 4.95 4.95 5 4.95 V
Output Voltage VDD = 10V 9.95 9.95 10 9.95 V

VDD = 15V 14.95 14.95 15 14.95 V

V

IL

LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5 V
Input Voltage VDD = 10V, VO = 1V or 9V 3.0 3.0 3.0 V

VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0 V

V

IH

HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 V
Input Voltage VDD = 10V, VO = 1V or 9V 7.0 7.0 7.0 V

VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 V

I

OL

LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0. 36 mA
Current (Note 4) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA

VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA

I

OH

HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA
Current (Note 4) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA

VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA

I

IN

Input Current VDD = 15V, VIN = 0V −0.30 −10−5−0.30 −1.0 µA

VDD = 15V, VIN = 15V 0.30 10−50.30 1.0 µA