Fairchild Semiconductor 74ACTQ00SCX, 74ACTQ00SC, 74ACTQ00PC, 74ACTQ00MTCX, 74ACTQ00MTC Datasheet
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August 1990
Revised April 1999
74ACTQ00 Quiet Series Quad 2-Input NAND Gate
© 1999 Fairchild Semiconductor Corporation DS010888.prf www.fairchildsemi.com
74ACTQ00
Quiet Series Quad 2-Input NAND Gate
General Description
The ACTQ00 contain s four 2-input NAND gates and uti lizes Fairchild FACT Quiet Series technology to guarantee quiet output switching and improve dynamic threshold
performance FACT Quiet Series features GTO output
control and undershoot corrector in addition to a split
ground bus for superior ACMOS performance.
Features
■ ICC reduced by 50%
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Improved latch-up immunity
■ Outputs source/sink 24 mA
■ Has TTL-com patible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code .
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Assignment for
DIP and SOIC
Pin Descriptions
FACT, Quiet S eries, FACT Quiet Series, and GTO are trademarks of Fairchild Sem ic onductor Corporation.
Order Number Package Number Package Description
74ACTQ00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74ACTQ00PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
A
n
, B
n
Inputs
O
n
Outputs
www.fairchildsemi.com 2
74ACTQ00
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its pow er
supply, temperature, and ou tput/inp ut loadi ng varia bles. Fairchild does no t
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds on input associated wit h output under test.
Note 3: Maximum te st duration 2.0 ms, one ou t put loaded at a time.
Note 4: DIP package.
Note 5: Max number of outputs defined a s (n ). D at a inputs are 0V to 3V. One output @ GND .
Note 6: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
),
0V to threshold (V
IHD
), f = 1 MHz.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
DC Latch-up Source
or Sink Current ±300 mA
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
I
) 0V to V
CC
Output Voltage (VO) 0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)
V
IN
from 0.8V to 2.0V 125 mV/ns
V
CC
@ 4.5V, 5.5V
Symbol Parameter
V
CC
TA = +25°CTA = −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 4.5 1.5 2.0 2.0 V V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V
V
IL
Maximum LOW Level 4.5 1.5 0.8 0.8 V V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V
V
OH
Minimum HIGH Level 4.5 4.49 4.4 4.4 V I
OUT
= −50 µA
Output Voltage 5.5 5.49 5.4 5.4
VIN = VIL or V
IH
4.5 3.86 3.76 IOH = −24 mA
5.5 4.86 4.76 V IOH = −24 mA (Note 2)
V
OL
Maximum LOW Level 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
VIN = VIL or V
IH
4.5 0.36 0.44 IOL = 24 mA
5.5 0.36 0.44 V IOL = 24 mA (Note 2)
I
IN
Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µAVI = VCC, GND
I
CCT
Maximum ICC/Input 5.5 0.6 1.5 mA V I = VCC − 2.1V
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent Supply Current 5.5 2.0 20.0 µAVIN = VCC or GND
V
OLP
Quiet Output Maximum Dynamic 5.0 1.1 1.5 V Figure 1, Figure 2
V
OL
(Note 4)(Note 5)
V
OLV
Quiet Output Minimum Dynamic 5.0 −0.6 −1.2 V Figure 1, Figure 2
V
OL
(Note 4)(Note 5)
V
IHD
Minimum HIGH Level Dynamic
Input Voltage
5.0 1.9 2.2 V (Note 4)(Note 6)
V
ILD
Maximum LOW Level Dynamic
Input Voltage
5.0 1.2 0.8 V (Note 4)(Note 6)
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