Fairchild Semiconductor 74ACT534SJX, 74ACT534SJ, 74ACT534SCX, 74ACT534SC, 74ACT534PC Datasheet
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© 1999 Fairchild Semiconductor Corporation DS009965 www.fairchildsemi.com
November 1988
Revised November 1999
74ACT534 Octal D-Type Flip-Flop with 3-STATE Outputs
74ACT534
Octal D-Type Flip-Flop with 3-ST ATE Outputs
General Description
The ACT534 is a h igh-speed, low- power octal D -type flipflop featuring separ ate D-type inp uts for each fl ip-flop and
3-STATE outputs for bus-oriented applications. A buffered
Clock (CP) and Output Enabl e (OE
) are common to all flipflops. The ACT534 is th e s ame a s th e AC T374 except that
the outputs are inverted.
Features
■ ICC and IOZ reduced by 5 0%
■ Edge-triggered D-type inputs
■ Buffered positive edge-triggered cl ock
■ 3-STATE outputs for bus-oriented applications
■ Outputs source/sink 24 mA
■ ACT534 has TTL-compatible inputs
■ Inverted output version of ACT374
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACT534SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT534SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT534PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
0–D7
Data Inputs
CP Clock Pulse Input
OE
3-STATE Output Enable Input
O
0–O7
Complementary 3-STATE Outputs
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74ACT534
Functional Description
The ACT534 consists of eight edge-triggered fli p- flop s w ith
individual D-type inp uts and 3-STATE complementary outputs. The buffered cl ock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will s tore the
state of their indi vidual D inputs that meet the s etup and
hold times requiremen ts on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (O E
) LOW, the contents
of the eight flip-flops are available at the outputs. When the
OE
is HIGH, the outputs go to the high impedance state.
Operation of the O E
input does not affect the state of the
flip-flops.
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clo c k Transi ti on
Z = High Impedance
O
0
= Value stored from previous clock cycle
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Output
CP OE D O
L H L
L L H
L L X O
0
X H X Z
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74ACT534
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute max imum ratings are those values beyond w hich damage
to the device may occu r. The databook spe cificatio ns shou ld be met, wit hout exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specif ic at ions.
DC Electrical Characteristics
Note 2: All outputs loaded; thres holds on input associate d w it h output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
I
) 0V to V
CC
Output Voltage (VO) 0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
TA = +25°CTA = −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 4.5 1.5 2.0 2.0
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V
V
IL
Maximum LOW Level 4.5 1.5 0.8 0.8
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V
V
OH
Minimum HIGH Level 4.5 4.49 4.4 4.4
V I
OUT
= −50 µA
Output Voltage 5.5 5.49 5.4 5.4
VIN = VIL or V
IH
4.5 3.86 3.76 V IOH = −24 mA
5.5 4.86 4.76 IOH = −24 mA (Note 2)
V
OL
Maximum LOW Level 4.5 0.001 0.1 0.1
V I
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
VIN = VIL or V
IH
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 I
OL
= 24 mA (Note 2)
I
IN
Maximum Input
5.5 ±0.1 ±1.0 µA V
I
= VCC, GND
Leakage Current
I
OZ
Maximum 3- STATE
5.5 ±0.25 ±2.5 µA
VI = VIL, V
IH
Current VO = VCC, GND
I
CCT
Maximum
5.5 0.6 1.5 mA VI = VCC − 2.1V
ICC/Input
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5 4.0 40.0 µA
VIN = V
CC
Supply Current or GND
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