Fairchild Semiconductor 74ACT18823SSCX, 74ACT18823SSC, 74ACT18823MTDX, 74ACT18823MTD Datasheet
© 1999 Fairchild Semiconductor Corporation DS500294 www.fairchildsemi.com
August 1999
Revised October 1999
74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs
74ACT18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACT18823 contains eighteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP), Clear (CLR
), Clock Enable (EN) and Output Enable
(OE
) are common to each byte and can be shorted
together for full 18-bit operation.
Features
■ Broadside pinout allows for easy board layout
■ Separate control logic for each byte
■ Extra data width for wider address/data p aths or buses
carrying parity
■ Outputs source/sink 24 mA
■ TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
FACT is a trade m ark of F airchild Semicondu ctor Corporation.
Order Number Package Number Package Description
74ACT18823SSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACT18823MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Input (Active LOW)
CLR
n
Clear (Active LOW)
EN
n
Clock Enable (Active LOW)
CP
n
Clock Pulse Input
I
0–I17
Inputs
O
0–O17
Outputs
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74ACT18823
Functional Description
The ACT18823 co nsist s o f e ight een D - type e dg e-t rigg ere d
flip-flops. These have 3-STATE outputs for bus systems
organized with inputs a nd outputs on opposi te sides. The
device is byte contr olled with each byte functionin g identically, but independent of the other. The control p i ns c an b e
shorted together to obtain full 16-b it oper ation. The following description applies to each byte. The buffered clock
(CP
n
) and buffered Output Enable (OEn) are common to all
flip-flops within that byte. The flip-flops will store the state
of their individual D i nputs that meet set-up a nd hold time
requirements on the LOW-to-HIGH CP
n
transition. With
OE
n
LOW, the contents of the flip-flops are available at the
outputs. When OE
n
is HIGH, the outputs go to the imped -
ance state. Ope ration of the OE
n
input does not affect the
state of the flip-flops . In addition to the Clock and Outp ut
Enable pins, there are Clear (CLR
n
) and Clock Enable
(EN
n
) pins. These devices are ideal for parity bus interfa cing in high performance systems.
When CLR
n
is LOW and OEn is LOW, the outputs are
LOW. When CLR
n
is HIGH, data can be enter ed into the
flip-flops. When EN
n
is LOW, data on the inputs is tran s-
ferred to the ou tputs o n the LOW-to-HI GH clock tra nsition.
When the EN
n
is HIGH, the outputs d o not change state,
regardless of the data or clock input transitions.
Function Table
(Note 1)
H= HIGH Voltage Level
L= LOW Voltage Level
X= Immaterial
Z= High Impedance
= LOW-to-HIGH Transition
NC= No Change
Note 1: The table represents the logic for one byte. The two bytes are inde-
pendent of each oth er and function identica lly.
Logic Diagrams
Byte 1 (0:8)
Byte 2 (9:17)
Inputs Internal Output
Function
OE
CLR EN CP I
n
QO
n
HXLL L Z High Z
HXL
H H Z High Z
HLXXX L ZClear
LLXXX L LClear
H H H X X NC Z Hold
LHHXX NC NCHold
HHL
L L Z Load
HHL
H H Z Load
LHL
L L L Load
LHL
H H H Load
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