Fairchild Semiconductor 74ACT16374MTDX, 74ACT16374MTD, 74ACT16374SSCX, 74ACT16374SSC Datasheet

© 1999 Fairchild Semiconductor Corporation DS500298 www.fairchildsemi.com

August 1999
Revised October 1999

74ACT16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs

74ACT16374
16-Bit D-Type Flip-Flop with 3-STATE Outputs

General Description

The ACT16374 conta ins sixteen non-inverti ng D-type flip­flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte
and can be shorted together for full 16-bit operation.

Features

■ Buffered Positive edge-triggered clock

■ Separate control logic for each byte

■ 16-bit version of the ACT374

■ Outputs source/sink 24 mA

■ TTL-compatible inputs

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.

Logic Symbol

Pin Descriptions

Connection Diagram

FACT is a trade m ark of F airchild Semicondu ctor Corporation.

Order Number Package Number Package Description

74ACT16374SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACT16374MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Pin Names Description

OE

n

Output Enable Input (Active LOW)

CP

n

Clock Pulse Input

I

0–I15

Inputs

O

0–O15

Outputs

www.fairchildsemi.com 2

74ACT16374

Functional Description

The ACT16374 consists of sixteen edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The device is byte controlled with each byte functioning
identically, but independent of the ot her. The control pins
can be shorted together to obtain full 16-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flo ps within that byte. The description
which follows applies to each byte. Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requirem ents on the LOW-to-HIG H Clock (CP

n

)

transition. With the Output Enable (OE

n

) LOW, the con-

tents of the flip-flops a re available at the outputs. When
OE

n

is HIGH, the outputs go to the high imped ance state.

Operation of the OE

n

input does not affect the st ate of the

flip-flops.

Tr uth Tables

H = HIGH Voltage Level
L = LOW Voltage Level
X= Immaterial
Z = HIGH Impedance



= LOW-to-HIGH Transition

Logic Diagrams

Byte 1 (0:7)

Byte 2 (8:15)

Inputs Outputs

CP

1

OE

1

I0–I

7

O0–O

7



LH H



LL L
L L X (Previous)
XHX Z

Inputs Outputs

CP

2

OE

2

I8–I

15

O8–O

15



LH H



LL L
L L X (Previous)
XHX Z

3 www.fairchildsemi.com

74ACT16374

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, with­out exception to ensure that the system design is reliable over its power
supply, temperature, and ou tput/inp ut load ing vari ables. Fairchild does n ot
recommend operat ion of FACT circuits outside da t abook specifications.

DC Electrical Characteristics

Note 2: All outputs loaded; thresholds assoc iated with output under t es t .
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V

DC Output Source/Sink Current (I

O

) ±50 mA

DC V

CC

or Ground Current

per Output Pin ± 50 mA

Storage Temperature −65°C to +150°C

Supply Voltage (V

CC

) 4.5V to 5.5V

Input Voltage (V

I

)0V to V

CC

Output Voltage (VO)0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t) 125 mV/ns

V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V

Symbol Parameter

V

CC

TA = +25°CT

A

= −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH 4.5 1.5 2.0 2.0

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

V

IL

Maximum LOW 4.5 1.5 0.8 0.8

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V

V

OH

Minimum HIGH 4.5 4.49 4.4 4.4

VI

OUT

= −50 µA

Output Voltage 5.5 5.49 5.4 5.4

VIN = VIL or V

IH

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 IOH = −24 mA (Note 2)

V

OL

Maximum LOW 4.5 0.001 0.1 0.1

VI

OUT

= 50 µA

Output Voltage 5.5 0.001 0.1 0.1

VIN = VIL or V

IH

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

I

OZ

Maximum 3- STATE

5.5 ± 0.5 ± 5.0 µA

VI = VIL, V

IH

Leakage Current VO = VCC, GND

I

IN

Maximum Input

5.5 ± 0.1 ± 1.0 µAVI = VCC, GND

Leakage Current

I

CCT

Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V

I

CC

Maximum Quiescent

5.5 8.0 80.0 µAVIN = VCC or GND

Supply Current

I

OLD

Minimum Dynamic

5.5

75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note 3) −75 mA V

OHD

= 3.85V Min