Fairchild Semiconductor 74ABT16373CMTD, 74ABT16373CSSCX, 74ABT16373CSSC, 74ABT16373CMTDX Datasheet

© 1999 Fairchild Semiconductor Corporation DS011666 www.fairchildsemi.com

March 1994
Revised November 1999

74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs

74ABT16373
16-Bit Transparent D-Type Latch with 3-STATE Outputs

General Description

The ABT16373 cont ains sixteen n on-inverti ng latches with
3-STAT E outputs and is intende d for bus oriented app lica­tions. The device is byte controlled. T he flip-flops appe ar
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE

) is LOW. When OE is HIGH, the outputs are in

high Z state.

Features

■ Separate control logic for each byte

■ 16-bit version of the ABT373

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Non-destructive hot insertion capability

■ Guaranteed latch-up protection

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Connection Diagram

Order Number Package Number Package Description

74ABT16373CSSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16373CMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Pin Names Description

OE

n

Output Enable Input (Active LOW)

LE

n

Latch Enabl e Input

D

0–D15

Data Inputs

O

0–O15

Outputs

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74ABT16373

Functional Description

The ABT16373 contains sixteen D-type latches with 3­STATE standard outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obt ain full
16-bit operation. The following description applies to each
byte. When the Latch E nable (LE

n

) input is HIGH, data on

the D

n

enters the latches. In this condition the la tches are

transparent, i.e., a latch output will change states each time
its D input changes. When LE

n

is LOW, the latches store

information that was prese nt on the D inputs a setup time
preceding the HIGH-to-LOW transition of LE

n

. The 3-

STATE standard outputs are controlled by the Output
Enable (OE

n

) input. When OEn is LOW, the standard out-

puts are in the 2-state mode. When OE

n

is HIGH, the stan-

dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.

Tr uth Tables

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Previous = previous output prior to HIGH-to-LOW transition of LE

Logic Diagrams

Inputs Outputs

LE

1

OE

1

D0–D

7

O0–O

7

XH X Z
HL L L
HL H H
L L X (Previous)

Inputs Outputs

LE

2

OE

2

D8–D

15

O8–O

15

XH X Z
HL L L
HL H H
LL X (Previous)