Fairchild Semiconductor 74ABT16245CSSC, 74ABT16245CMTDX, 74ABT16245CMTD, 74ABT16245CSSCX Datasheet

© 1999 Fairchild Semiconductor Corporation DS010986 www.fairchildsemi.com

April 1992
Revised November 1999

74ABT16245 16-Bit Transceiver with 3-STATE Outputs

74ABT16245
16-Bit Transceiver with 3-STATE Outputs

General Description

The ABT16245 conta ins s ixteen n on-i nvertin g bidi rectio nal
buffers with 3-STATE outputs and is in tended for bus ori­ented applications. The device is byte controlled. Each
byte has separate control inputs which can be shorted
together for full 16 -bit oper ation. The T /R

inputs determine

the direction of data flow through the device. The OE

inputs
disable both the A and B ports by placing them in a high
impedance state.

Features

■ Bidirectional non-inverting buffers

■ Separate control logic for each byte

■ 16-bit version of the ABT245

■ A and B output sink capability of 64 mA, source

capability of 32 mA

■ Guaranteed output skew

■ Guaranteed multiple output switching specifications

■ Output switching specified for both 50 pF and

250 pF loads

■ Guaranteed simultaneous switching noise level and
dynamic threshold performance

■ Guarante ed latchup protection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Non-destructive hot insertion capability

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.

Logic Symbol

Pin Descriptions

Connection Diagram

Order Number Package Number Package Description

74ABT16245CSSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16245CMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Pin Names Description

OE

n

Output Enable Input (Active LOW)

T/R

n

Transmit/Receive Input

A

0–A15

Side A Inputs/Outputs

B

0–B15

Side B Inputs/Outputs

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74ABT16245

Truth Tables

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

Functional Description

The ABT16245 con tain s sixteen non- inve rting b idire ctional
buffers wit h 3- STA T E ou tpu ts . Th e de v ic e i s byt e cont r ol l ed
with each byte funct ioning identically, but independent of
the other. The control pins can be shorted together to
obtain full 16-bit operation.

Logic Diagrams

Inputs Outputs

OE

1

T/R

1

L L Bus B0–B7 Data to Bus A0–A

7

L H Bus A0–A7 Data to Bus B0–B

7

H X HIGH-Z State on A0–A7, B0–B

7

Inputs Outputs

OE

2

T/R

2

L L Bus B8–B15 Data to Bus A8–A

15

L H Bus A8–A15 Data to Bus B8–B

15

H X HIGH-Z State on A8–A15, B8–B

15

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74ABT16245

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired . Functional operation
under these conditions is not implied.

Note 2: Either voltage lim it or c urrent limit is sufficient to pro te c t in puts.

DC Electrical Characteristics

Note 3: Guaranteed, but not tested.

Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V

CC

Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output

in the Disabled or
Power-Off State −0.5V to 5.5V
in the HIGH State −0.5V to V

CC

Current Applied to Output
in LOW State (Max) twice the r ated I

OL

(mA)
DC Latchup Source Current −500 mA
Over Voltage Latchup (I/O) 10V

Free Air Ambient Temperature −40°C to +85°C
Supply Voltage +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns
Enable Input 20 mV/ns

Symbol Parameter Min Typ Max Units

V

CC

Conditions

V

IH

Input HIGH Voltage 2.0 V Recognized HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min

IIN = −18 mA (OEn, T/Rn)

V

OH

Output HIGH Voltage 2.5 V Min IOH = −3 mA (An, Bn)

2.0 V Min IOH = −32 mA (An, Bn)

V

OL

Output LOW Voltage 0.55 V Min IOL = 64 mA (An, Bn)

I

IH

Input HIGH Current 1

µAMax

VIN = 2.7V (OEn, T/Rn) (Note 3)

1

VIN = VCC (OEn, T/Rn)

I

BVI

Input HIGH Current Breakdown Test

7 µAMax

VIN = 7.0V (OEn, T/Rn)

I

BVIT

Input HIGH Current Breakdown Test (I/O) 100 µAMaxVIN = 5.5V (An, Bn)

I

IL

Input LOW Current −1

µAMax

V

IN

= 0.5V (OEn, T/Rn) (Note 3)

−1

V

IN

= 0.0V (OEn, T/Rn)

V

ID

Input Leakage Test

4.75 V 0.0

IID = 1.9 µA (OEn, T/Rn)
All Other Pins Grounded

IIH + I

OZH

Output Leakage Current 10 µA0 − 5.5V

V

OUT

= 2.7V (An, Bn); OE = 2.0V

I

IL

+ I

OZL

Output Leakage Current −10 µA0 − 5.5V

V

OUT

= 0.5V (An, Bn); OE = 2.0V

I

OS

Output Short-Circuit Current −100 −275 mA Max V

OUT

= 0.0V (An, Bn)

I

CEX

Output HIGH Leakage Current 50 µAMaxV

OUT

= VCC (An, Bn)

I

ZZ

Bus Drainage Test 100 µA0.0V

OUT

= 5.50V (An, Bn);

All Others GND

I

CCH

Power Supply Current 100 µA Max All Outputs HIGH

I

CCL

Power Supply Current 60 mA Max All Outputs LOW

I

CCZ

Power Supply Current

100 µAMax

OEn = VCC, T/Rn = GND or V

CC

All others at VCC or GND

I

CCT

Additional ICC/Input Outputs Enabled 2.5 mA VI = VCC − 2.1V

Outputs 3-STATE 2.5 mA Max

OEn, T/ Rn VI = VCC − 2.1V

Outputs 3-STATE 50 µA Data Input VI = VCC − 2.1V

All others at VCC or GND

I

CCD

Dynamic I

CC

No Load mA/

Max

Outputs OPEN

(Note 3) 0.1

MHz

OEn = GND, T/Rn = GND or V

CC

One Bit Toggling, 50% Duty Cycle