Fairchild Semiconductor 74ABT125CSJX, 74ABT125CSJ, 74ABT125CSCX, 74ABT125CSC, 74ABT125CMTCX Datasheet
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© 1999 Fairchild Semiconductor Corporation DS011667 www.fairchildsemi.com
March 1994
Revised November 1999
74ABT125 Quad Buffer with 3-STATE Outputs
74ABT125
Quad Buffer with 3-STATE Outputs
General Description
The ABT125 conta ins four i ndepend ent non-in verting buffers with 3-STATE outputs.
Features
■ Non-inverting buffers
■ Output sink capability of 64 mA, source capability of
32 mA
■ Guarante ed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Nondestructive hot insertion capability
■ Disable time less than enabl e time to avoi d bus conten-
tion
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
X = Immaterial
Order Number Package Number Package Description
74ABT125CSC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74ABT125CSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT125CMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide
Pin Names Descriptions
A
n
, B
n
Inputs
O
n
Outputs
Inputs Output
A
n
B
n
O
n
L L L
L H H
H X Z
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74ABT125
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditi ons is not implied.
Note 2: Either voltage lim it or c urrent limit is sufficient to prot ect inputs.
DC Electrical Characteristics
Note 3: Guaranteed, but not tested.
Note 4: For 8 bits toggling, I
CCD
< 0.8 mA/MHz.
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to
Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State −0.5V to 5.5V
in the HIGH State −0.5V to V
CC
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
DC Latchup Source Current
(Across Comm Operating Range) −300 mA
Over Voltage Latchup (I/O) 10V
Free Air Ambient Temperature −40°C to +85°C
Supply Voltage +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)
Data Input 50 mV/ns
Enable Inpu t 20 mV/ns
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage V Recognized HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
V
OH
Output HIGHVoltage 2.5 V Min IOH = −3 mA
2.0 V Min IOH = −32 mA
V
OL
Output LOWVoltage 0.55 V Min IOL = 64 mA
I
IH
Input HIGH Current 1
µAMax
VIN = 2.7V (Note 3)
1V
IN
= V
CC
I
BVI
Input HIGH Current Breakdown Test 7 µAMaxVIN = 7.0V
I
IL
Input LOW Current −1
µAMax
VIN = 0.5V (Note 3)
−1V
IN
= 0.0V
V
ID
Input Leakage Test V 0.0 IID = 1.9 µA, All Other Pin Grounded
I
OZH
Output LeakageCurrent 10 µA0−5.5V
V
OUT
= 2.7V; OEn = 2.0V
I
OZL
Output LeakageCurrent −10 µA0−5.5V
V
OUT
= 0.5V; OEn = 2.0V
I
OS
Output Short-Circuit Cu rrent −275 mA Max V
OUT
= 0.0V
I
CEX
Output HIGHLeakage Current 50 µAMaxV
OUT
= V
CC
I
ZZ
Bus DrainageTest 100 µA0.0V
OUT
= 5.5V; All Others GND
I
CCH
Power Supply Current 50 µA Max All Outputs HIGH
I
CCL
Power SupplyCurrent 15 mA Max All Outputs LOW
I
CCZ
Power Supply Current
50 µAMax
OEn = VCC;
All Others at V
CC
or Ground
I
CCT
Additional I
CC
/Input Outputs Enabled 1.5 mA
Max
VI = V
CC
− 2.1V
Outputs 3-STATE 1.5 mA Enable Input VI = VCC − 2.1V
Outputs 3-STATE 50 µA Data Input V I = VCC − 2.1V
All Others at VCC or Ground
I
CCD
Dynamic I
CC
No Load mA/
Max
Outputs Open
(Note 3) 0.1
MHz
OEn = GND, (Note 4)
One Bit Toggling, 50% Duty Cycle
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